From d92c4d74336f323129fbf2d9e4ea2008f36f9657 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 12 Jan 2026 10:22:33 +0000 Subject: [PATCH 0001/2070] drm/amdgpu/mes: Remove idr leftovers v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") removed most of the code using these IDRs but forgot to remove the struct members and init/destroy paths. There is also interrupt handling code in SDMA 5.0 and 5.2 which appears to be using it, but is is unreachable since nothing ever allocates the relevant IDR. We replace those with one time warnings just to avoid any functional difference, but it is also possible they should be removed. v2: also fix up gfx_v12_1.c and sdma_v7_1.c Signed-off-by: Tvrtko Ursulin References: cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") Cc: Alex Deucher Reviewed-by: Christian König Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 9 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 25 ++++++++++++------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 18 +++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 18 +++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 17 +++-------------- 6 files changed, 21 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 6e19836c5ff6f..0d4c77c1b4b5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -115,9 +115,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.adev = adev; - idr_init(&adev->mes.pasid_idr); - idr_init(&adev->mes.gang_id_idr); - idr_init(&adev->mes.queue_id_idr); ida_init(&adev->mes.doorbell_ida); spin_lock_init(&adev->mes.queue_id_lock); mutex_init(&adev->mes.mutex_hidden); @@ -252,9 +249,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) &adev->mes.hung_queue_db_array_cpu_addr[i]); } - idr_destroy(&adev->mes.pasid_idr); - idr_destroy(&adev->mes.gang_id_idr); - idr_destroy(&adev->mes.queue_id_idr); ida_destroy(&adev->mes.doorbell_ida); mutex_destroy(&adev->mes.mutex_hidden); return r; @@ -283,9 +277,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) amdgpu_mes_doorbell_free(adev); - idr_destroy(&adev->mes.pasid_idr); - idr_destroy(&adev->mes.gang_id_idr); - idr_destroy(&adev->mes.queue_id_idr); ida_destroy(&adev->mes.doorbell_ida); mutex_destroy(&adev->mes.mutex_hidden); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 88685c58798e4..bcf2a067dc410 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -77,9 +77,6 @@ struct amdgpu_mes { struct mutex mutex_hidden; - struct idr pasid_idr; - struct idr gang_id_idr; - struct idr queue_id_idr; struct ida doorbell_ida; spinlock_t queue_id_lock; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 86cc90a662965..08ae50a6313f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -30,6 +30,7 @@ #include "amdgpu_psp.h" #include "amdgpu_smu.h" #include "amdgpu_atomfirmware.h" +#include "amdgpu_userq_fence.h" #include "imu_v12_1.h" #include "soc_v1_0.h" #include "gfx_v12_1_pkt.h" @@ -3602,25 +3603,23 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - int i, xcc_id; + u32 doorbell_offset = entry->src_data[0]; u8 me_id, pipe_id, queue_id; struct amdgpu_ring *ring; - uint32_t mes_queue_id = entry->src_data[0]; + int i, xcc_id; DRM_DEBUG("IH: CP EOP\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; + if (adev->enable_mes && doorbell_offset) { + struct amdgpu_userq_fence_driver *fence_drv = NULL; + struct xarray *xa = &adev->userq_xa; + unsigned long flags; - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + xa_lock_irqsave(xa, flags); + fence_drv = xa_load(xa, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + xa_unlock_irqrestore(xa, flags); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 7811cbb1f7ba3..e77e079fe8339 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1704,24 +1704,12 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t mes_queue_id = entry->src_data[0]; - DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } switch (entry->client_id) { case SOC15_IH_CLIENTID_SDMA0: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index dbe5b8f109f6a..50b51965c211e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1617,24 +1617,12 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t mes_queue_id = entry->src_data[0]; - DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } switch (entry->client_id) { case SOC15_IH_CLIENTID_SDMA0: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 5bc45c3e00d18..0824cba48f2e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1494,24 +1494,13 @@ static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { int inst, instances, queue, xcc_id = 0; - uint32_t mes_queue_id = entry->src_data[0]; DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } queue = entry->ring_id & 0xf; if (adev->gfx.funcs && adev->gfx.funcs->ih_node_to_logical_xcc) From e2b86bdde223e3130a0bf64b0af14f175421a650 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 12 Jan 2026 10:22:34 +0000 Subject: [PATCH 0002/2070] drm/amdgpu: Simplify sorting of the bo list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort function only cares about the sign so we can replace the conditionals with a single subtraction. Signed-off-by: Tvrtko Ursulin Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 66fb37b643882..87ec46c56a6ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -60,11 +60,9 @@ static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b) { const struct amdgpu_bo_list_entry *a = _a, *b = _b; - if (a->priority > b->priority) - return 1; - if (a->priority < b->priority) - return -1; - return 0; + BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX); + + return (int)a->priority - (int)b->priority; } int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp, From f213c71d968171562318d1f593e9d2e9ca30f03a Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Thu, 22 Jan 2026 10:51:11 -0500 Subject: [PATCH 0003/2070] drm/amd/include : Update MES v12 API header - SUSPEND Update SUSPEND API to support sdma queues. It's been supportted since 0x82 for gfx12 Signed-off-by: Shaoyun Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/mes_v12_api_def.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index 83e4f01423243..e541a43714a10 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -492,8 +492,10 @@ union MESAPI__SUSPEND { union MES_API_HEADER header; /* false - suspend all gangs; true - specific gang */ struct { - uint32_t suspend_all_gangs : 1; - uint32_t reserved : 31; + uint32_t suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs) + uint32_t query_status : 1; + uint32_t suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs) + uint32_t reserved : 29; }; /* gang_context_addr is valid only if suspend_all = false */ From abb5795ce6ade5721a1be106208e0bd8fdcdd406 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 21 Jan 2026 11:04:06 +0800 Subject: [PATCH 0004/2070] drm/amd/pm: fix smu v13 soft clock frequency setting issue v1: resolve the issue where some freq frequencies cannot be set correctly due to insufficient floating-point precision. v2: patch this convert on 'max' value only. Signed-off-by: Yang Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index efeaa3d577123..b0d6b7b0946d8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -55,6 +55,7 @@ #define SMUQ10_TO_UINT(x) ((x) >> 10) #define SMUQ10_FRAC(x) ((x) & 0x3ff) #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) +#define SMU_V13_SOFT_FREQ_ROUND(x) ((x) + 1) extern const int pmfw_decoded_link_speed[5]; extern const int pmfw_decoded_link_width[7]; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 51f96fdcec24b..70581326dc368 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1554,6 +1554,7 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, return clk_id; if (max > 0) { + max = SMU_V13_SOFT_FREQ_ROUND(max); if (automatic) param = (uint32_t)((clk_id << 16) | 0xffff); else From 5692be2dcde638d33d02a876547554518be954dd Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 21 Jan 2026 11:06:29 +0800 Subject: [PATCH 0005/2070] drm/amd/pm: fix smu v14 soft clock frequency setting issue v1: resolve the issue where some freq frequencies cannot be set correctly due to insufficient floating-point precision. v2: patch this convert on 'max' value only. Signed-off-by: Yang Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h index 613d4d36f32fd..b453e6efc7c9d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h @@ -56,6 +56,7 @@ extern const int decoded_link_width[8]; #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) +#define SMU_V14_SOFT_FREQ_ROUND(x) ((x) + 1) struct smu_14_0_max_sustainable_clocks { uint32_t display_clock; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index f85ba23f9d99a..17caf98bd6ddc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -1177,6 +1177,7 @@ int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, return clk_id; if (max > 0) { + max = SMU_V14_SOFT_FREQ_ROUND(max); if (automatic) param = (uint32_t)((clk_id << 16) | 0xffff); else From 8216ab85d2c987ce750b24b651685fe57556ea06 Mon Sep 17 00:00:00 2001 From: Jon Doron Date: Sat, 20 Dec 2025 15:04:40 +0200 Subject: [PATCH 0006/2070] drm/amdgpu: fix NULL pointer dereference in amdgpu_gmc_filter_faults_remove MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On APUs such as Raven and Renoir (GC 9.1.0, 9.2.2, 9.3.0), the ih1 and ih2 interrupt ring buffers are not initialized. This is by design, as these secondary IH rings are only available on discrete GPUs. See vega10_ih_sw_init() which explicitly skips ih1/ih2 initialization when AMD_IS_APU is set. However, amdgpu_gmc_filter_faults_remove() unconditionally uses ih1 to get the timestamp of the last interrupt entry. When retry faults are enabled on APUs (noretry=0), this function is called from the SVM page fault recovery path, resulting in a NULL pointer dereference when amdgpu_ih_decode_iv_ts_helper() attempts to access ih->ring[]. The crash manifests as: BUG: kernel NULL pointer dereference, address: 0000000000000004 RIP: 0010:amdgpu_ih_decode_iv_ts_helper+0x22/0x40 [amdgpu] Call Trace: amdgpu_gmc_filter_faults_remove+0x60/0x130 [amdgpu] svm_range_restore_pages+0xae5/0x11c0 [amdgpu] amdgpu_vm_handle_fault+0xc8/0x340 [amdgpu] gmc_v9_0_process_interrupt+0x191/0x220 [amdgpu] amdgpu_irq_dispatch+0xed/0x2c0 [amdgpu] amdgpu_ih_process+0x84/0x100 [amdgpu] This issue was exposed by commit 1446226d32a4 ("drm/amdgpu: Remove GC HW IP 9.3.0 from noretry=1") which changed the default for Renoir APU from noretry=1 to noretry=0, enabling retry fault handling and thus exercising the buggy code path. Fix this by adding a check for ih1.ring_size before attempting to use it. Also restore the soft_ih support from commit dd299441654f ("drm/amdgpu: Rework retry fault removal"). This is needed if the hardware doesn't support secondary HW IH rings. v2: additional updates (Alex) Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3814 Fixes: dd299441654f ("drm/amdgpu: Rework retry fault removal") Reviewed-by: Timur Kristóf Reviewed-by: Philip Yang Signed-off-by: Jon Doron Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index d9ff68a43178e..b793ce17140c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -498,8 +498,13 @@ void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, if (adev->irq.retry_cam_enabled) return; + else if (adev->irq.ih1.ring_size) + ih = &adev->irq.ih1; + else if (adev->irq.ih_soft.enabled) + ih = &adev->irq.ih_soft; + else + return; - ih = &adev->irq.ih1; /* Get the WPTR of the last entry in IH ring */ last_wptr = amdgpu_ih_get_wptr(adev, ih); /* Order wptr with ring data. */ From ad50f09513ecdef6f9a999fda8004f4c309e29a5 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 8 Jan 2026 21:45:41 -0500 Subject: [PATCH 0007/2070] drm/amd/display: Enable vstateup hook for DCN401 to be reused Add the hook to the DCN401 header file so that it can be reused in other files Reviewed-by: Leo Chen Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 875ae97489d32..1cdbb65da4a33 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1772,7 +1772,7 @@ static int dcn401_get_power_profile(const struct dc_state *context) return dpm_level; } -static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) +unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) { return pipe_ctx->global_sync.dcn4x.vstartup_lines; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 406246a9867ea..08bec17556174 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -28,6 +28,8 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); +unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); + /* Following are definitions for run time init of reg offsets */ /* HUBP */ From 3313aa04a91c3b20eb0514bf1fed5ad04e7a7b7d Mon Sep 17 00:00:00 2001 From: Matthew Stewart Date: Fri, 9 Jan 2026 13:32:42 -0500 Subject: [PATCH 0008/2070] drm/amd/display: Fix GFX12 family constant checks Using >=, <= for checking the family is not always correct. Reviewed-by: Aurabindo Pillai Signed-off-by: Matthew Stewart Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b4ba60e90c476..0b4fc654e76f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11867,7 +11867,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, * check tiling flags when the FB doesn't have a modifier. */ if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; } else if (adev->family >= AMDGPU_FAMILY_AI) { linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index d95608abb7c46..d3e62f511c8f5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -278,7 +278,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, if (!dcc->enable) return 0; - if (adev->family < AMDGPU_FAMILY_GC_12_0_0 && + if (adev->family != AMDGPU_FAMILY_GC_12_0_0 && format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return -EINVAL; @@ -901,7 +901,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, upper_32_bits(chroma_addr); } - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, From cea42894a576929d78bfbd4143ef520bbe337a33 Mon Sep 17 00:00:00 2001 From: Jack Chang Date: Fri, 1 Aug 2025 11:54:01 +0800 Subject: [PATCH 0009/2070] drm/amd/display: Add FR skipping CTS functions 1. To check whether Sink reaches maximum skipping number Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/dpcd_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index 7d8359a7d99d4..1afa10e85eb59 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -224,6 +224,7 @@ enum dpcd_psr_sink_states { #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A #define DP_SINK_EMISSION_RATE 0x37E +#define DP_SINK_PR_FRAME_SKIP_COUNT 0x337 /* Remove once drm_dp_helper.h is updated upstream */ #ifndef DP_TOTAL_LTTPR_CNT From 1a0e6823d11d4c0f8041c1e404c1903185750a3f Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Mon, 22 Dec 2025 16:30:35 +0800 Subject: [PATCH 0010/2070] drm/amd/display: Enable bootcrc on FW side [Why] The bootcrc feature is controlled on the FW side. [How] Pass the control bits in boot options to FW. Reviewed-by: ChiaHsuan (Tom) Chung Signed-off-by: Wayne Lin Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index 6a2d35756c8ca..639f9835e5e96 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -419,6 +419,9 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; + boot_options.bits.bootcrc_en_at_preos = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_preos; + boot_options.bits.bootcrc_en_at_S0i3 = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_S0i3; + boot_options.bits.bootcrc_boot_mode = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_boot_mode; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } From 964f63db70d6b390486e9fcb317306168286ff93 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Sun, 11 Jan 2026 12:20:51 -0500 Subject: [PATCH 0011/2070] drm/amd/display: perform clear update flags for all DCN asics Existing version check that limits the sequence to clear update flags should be performed for all asics. Exclude DCE asics for now. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ad8ce46ce3103..cb85b7ac2697b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -7506,7 +7506,7 @@ struct dc_update_scratch_space *dc_update_planes_and_stream_init( .stream = stream, .stream_update = stream_update, .update_v3 = version >= DCN_VERSION_4_01 || version == DCN_VERSION_3_2 || version == DCN_VERSION_3_21, - .do_clear_update_flags = version >= DCN_VERSION_3_2 || version == DCN_VERSION_3_01, + .do_clear_update_flags = version >= DCN_VERSION_1_0, }; return scratch; From 5d447178746faa07f0c7e8c2551180ed9581adcd Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 12 Jan 2026 17:53:51 -0500 Subject: [PATCH 0012/2070] drm/amd/display: add setup_stereo for dcn4x or later [why] stereo_sync pin is removed, but we still support display stereo Reviewed-by: Ovidiu (Ovi) Bunea Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 8a23763ca98ec..73f469ce7cdd5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3474,7 +3474,7 @@ void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, triggers, params->num_frames); } -static void dcn10_config_stereo_parameters( +void dcn10_config_stereo_parameters( struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { enum view_3d_format view_format = stream->view_format; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h index 57d30ea225f2b..476095c5dd0cd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h @@ -217,5 +217,7 @@ void dcn10_update_visual_confirm_color( void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); +void dcn10_config_stereo_parameters( + struct dc_stream_state *stream, struct crtc_stereo_flags *flags); #endif /* __DC_HWSS_DCN10_H__ */ From 364abd6d5e6cbc08621cc787d0d73ea3f9ef5f1c Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Tue, 6 Jan 2026 15:46:49 +0800 Subject: [PATCH 0013/2070] drm/amd/display: Remove unnecessary DC FP guard [Why & How] For dcn2x_fast_validate_bw(), not only populate_dml_pipes needs FP guard but also dml_get_voltage_level(). Remove unnecessary DC_FP_START/DC_FP_END guard in dcn20_fast_validate_bw and dcn21_fast_validate_bw. FP guard is already there before calling dcn2x_validate_bandwidth_fp(). Reviewed-by: ChiaHsuan (Tom) Chung Signed-off-by: Wayne Lin Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 -- drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 8d10aac9c510c..46985eb2a623f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -2022,9 +2022,7 @@ bool dcn20_fast_validate_bw( dcn20_merge_pipes_for_validate(dc, context); - DC_FP_START(); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); - DC_FP_END(); *pipe_cnt_out = pipe_cnt; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 2060acd5ae098..967e813a45e51 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -785,9 +785,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, dcn20_merge_pipes_for_validate(dc, context); - DC_FP_START(); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); - DC_FP_END(); *pipe_cnt_out = pipe_cnt; From bcedfec80ac8ae4a6b552698c1144dc06645b882 Mon Sep 17 00:00:00 2001 From: Zhongwei Date: Tue, 13 Jan 2026 15:51:42 +0800 Subject: [PATCH 0014/2070] drm/amd/display: avoid dig reg access timeout on usb4 link training fail [Why] When usb4 link training fails, the dpia sym clock will be disabled and SYMCLK source should be changed back to phy clock. In enable_streams, it is assumed that link training succeeded and will switch from refclk to phy clock. But phy clk here might not be on. Dig reg access timeout will occur. [How] When enable_stream is hit, check if link training failed for usb4. If it did, fall back to the ref clock to avoid reg access timeout. Reviewed-by: Wenjing Liu Signed-off-by: Zhongwei Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 77ac7b22b8dc5..16ea6179640e8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -3058,9 +3058,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); } } else { - if (dccg->funcs->enable_symclk_se) - dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, + if (dccg->funcs->enable_symclk_se && link_enc) { + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA + && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN + && !link->link_status.link_active) { + if (dccg->funcs->disable_symclk_se) + dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } else + dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, + link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } } if (dc->res_pool->dccg->funcs->set_pixel_rate_div) From 81920fce92403c82ce4c15e84927f12ffac05ae2 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Thu, 15 Jan 2026 11:07:53 -0500 Subject: [PATCH 0015/2070] drm/amd/display: Add debug flag to override min dispclk [WHY] Enable dynamic ODM testing without needing a valid dispclk table [HOW] Create a debug flag to specify an override value for min dispclk Reviewed-by: Dmytro Laktyushkin Signed-off-by: Michael Strauss Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d377be76360c4..472d0eeca85e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1210,6 +1210,7 @@ struct dc_debug_options { bool disable_deferred_minimal_transitions; unsigned int num_fast_flips_to_steady_state_override; bool enable_dmu_recovery; + unsigned int force_vmin_threshold; }; From bc3a22b075ae4a99ee196ca85073ac4e462ac27d Mon Sep 17 00:00:00 2001 From: Muaaz Nisar Date: Thu, 18 Dec 2025 17:34:29 -0500 Subject: [PATCH 0016/2070] drm/amd/display: mouse event trigger to boost RR when idle [WHY+HOW] Add trigger event to boost refresh rate on mouse movement. Reviewed-by: Jun Lei Signed-off-by: Muaaz Nisar Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9349cccc8438d..f59020f1a722f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -515,6 +515,19 @@ bool dc_stream_program_cursor_position( } } + /* apply manual trigger */ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* trigger event on first pipe with current stream */ + if (stream == pipe_ctx->stream) { + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + break; + } + } + return true; } From 035cbb02f6b0cff64ed1fb4342acd0894ecfea8c Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Thu, 8 Jan 2026 19:11:31 +0530 Subject: [PATCH 0017/2070] drm/amd/display: Migrate HUBBUB register access from hwseq to hubbub component. [why] Direct HUBBUB register access in the hwseq layer was creating register conflicts. [how] Migrated HUBBUB registers from hwseq to the hubbub component. Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 18 ++++++++++++++++++ .../amd/display/dc/hubbub/dcn10/dcn10_hubbub.h | 4 ++++ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 3 +-- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 ++-- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 1 + .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 1 + .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 1 + .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 1 + 8 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index 7847c1c4927bf..97ef8281a476e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -944,3 +944,21 @@ void hubbub1_construct(struct hubbub *hubbub, hubbub1->debug_test_index_pstate = 0xB; } +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + if (refdiv > 0) + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv); + + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0); +} + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value); + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value); +} + diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index 0a29a758d013e..990d3cd8e0505 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -519,4 +519,8 @@ bool hubbub1_program_pstate_watermarks( unsigned int refclk_mhz, bool safe_to_lower); +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv); + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 73f469ce7cdd5..c1586364ecd45 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2678,8 +2678,7 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, uint32_t fb_base_value; uint32_t fb_offset_value; - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); + dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value); REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 16ea6179640e8..a76436dcbe401 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -46,6 +46,7 @@ #include "dchubbub.h" #include "reg_helper.h" #include "dcn10/dcn10_cm_common.h" +#include "dcn10/dcn10_hubbub.h" #include "vm_helper.h" #include "dccg.h" #include "dc_dmub_srv.h" @@ -3153,8 +3154,7 @@ void dcn20_fpga_init_hw(struct dc *dc) REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); if (REG(REFCLK_CNTL)) REG_WRITE(REFCLK_CNTL, 0); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 1635e5a552ad2..482053c4ad22a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -39,6 +39,7 @@ #include "dccg.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #define CTX \ hws->ctx diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 81bcadf5e57ed..c02ddada723fc 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -36,6 +36,7 @@ #include "dcn10/dcn10_cm_common.h" #include "dcn30/dcn30_cm_common.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "clk_mgr.h" #include "hubp.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 20f700b59847c..2adbcc105aa64 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 2675d7dca5864..f7e16fee75943 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" From 0bc6cbbb9bab2ba9a54cd4bd1eff498981f6bbd7 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 16 Jan 2026 17:25:23 -0500 Subject: [PATCH 0018/2070] drm/amd/display: [FW Promotion] Release 0.1.44.0 * Panel Replay related features/bugfixes * BootCRC feature Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 55 +++++++++++++++++-- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 6d82973ccc188..18e0bdfd6ff41 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -139,6 +139,33 @@ */ #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 +/** + * + * dirty rect cmd version legacy + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 +/** + * dirty rect cmd version with multi edp support + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 +/** + * dirty rect cmd version with external monitor support + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 + +/** + * + * Cursor update cmd version legacy + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 +/** + * Cursor update cmd version with multi edp support + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 +/** + * Cursor update cmd version with external monitor support + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 /** * ABM control version legacy @@ -3929,7 +3956,7 @@ struct dmub_cmd_update_dirty_rect_data { */ union dmub_psr_su_debug_flags debug_flags; /** - * OTG HW instance. + * Pipe index. */ uint8_t pipe_idx; /** @@ -3937,7 +3964,7 @@ struct dmub_cmd_update_dirty_rect_data { */ uint8_t dirty_rect_count; /** - * PSR control version. + * dirty rects cmd version. */ uint8_t cmd_version; /** @@ -3946,6 +3973,14 @@ struct dmub_cmd_update_dirty_rect_data { * Currently the support is only for 0 or 1 */ uint8_t panel_inst; + /** + * OTG HW instance + */ + uint8_t otg_inst; + /** + * Padding for 4 byte alignment + */ + uint8_t padding[3]; }; /** @@ -4071,11 +4106,11 @@ struct dmub_cmd_update_cursor_payload0 { */ uint8_t enable; /** - * OTG HW instance. + * Pipe index. */ uint8_t pipe_idx; /** - * PSR control version. + * Cursor update cmd version. */ uint8_t cmd_version; /** @@ -4089,6 +4124,14 @@ struct dmub_cmd_update_cursor_payload0 { * Registers contains Hubp & Dpp modules */ struct dmub_cursor_position_cfg position_cfg; + /** + * OTG HW instance + */ + uint8_t otg_inst; + /** + * Padding for 4 byte alignment + */ + uint8_t padding[3]; }; struct dmub_cmd_update_cursor_payload1 { @@ -6629,9 +6672,9 @@ struct dmub_cmd_pr_copy_settings_data { */ uint8_t su_y_granularity; /** - * @pad: Align structure to 4 byte boundary. + * @main_link_activity_option: Indicates main link activity option selected */ - uint8_t pad; + uint8_t main_link_activity_option; }; /** From ae625dffa0a22d796c59c3a8421b73bdcbae0d51 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 16 Jan 2026 20:09:08 -0500 Subject: [PATCH 0019/2070] drm/amd/display: Promote DC to 3.2.367 * Fw release 0.1.44.0 * Fixes for corruption on platforms older than DCN4x. * Bug fixes related to USB4 link training * Fixes related to FP guard * Debug helpers and other stability fixes. * Some refactors to improve code quality Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 472d0eeca85e8..ab19b62309450 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.366" +#define DC_VER "3.2.367" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From c66cc7861fa25b9011f7fdb53c4f2eadae28fc67 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 27 Jan 2026 11:07:07 +0800 Subject: [PATCH 0020/2070] drm/amd/pm: fix race in power state check before mutex lock The power state check in amdgpu_dpm_set_powergating_by_smu() is done before acquiring the pm mutex, leading to a race condition where: 1. Thread A checks state and thinks no change is needed 2. Thread B acquires mutex and modifies the state 3. Thread A returns without updating state, causing inconsistency Fix this by moving the mutex lock before the power state check, ensuring atomicity of the state check and modification. Fixes: 6ee27ee27ba8 ("drm/amd/pm: avoid duplicate powergate/ungate setting") Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 4214f7314963f..feadf604b4749 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -80,15 +80,15 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; + mutex_lock(&adev->pm.mutex); + if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - return 0; + goto out_unlock; } - mutex_lock(&adev->pm.mutex); - switch (block_type) { case AMD_IP_BLOCK_TYPE_UVD: case AMD_IP_BLOCK_TYPE_VCE: @@ -115,6 +115,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); +out_unlock: mutex_unlock(&adev->pm.mutex); return ret; From f3dc7a093393ebe47c466878579dd631688d1a3a Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 27 Jan 2026 15:01:27 +0800 Subject: [PATCH 0021/2070] drm/amdgpu: Fix jpeg ring test order in vcn_v4_0_3 Fix the vcn reset sequence in vcn_v4_0_3_ring_reset() to restore JPEG power state and unlock the JPEG powergating mutex before running the JPEG ring post-reset helper. Fixes: d25c67fd9d6f ("drm/amdgpu/vcn4.0.3: rework reset handling") Reviewed-by: Lijo Lazar Signed-off-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index dd247abce1ab0..e78526a4e521e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1742,11 +1742,11 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, goto unlock; } - r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); if (pg_state) amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, AMD_PG_STATE_GATE); mutex_unlock(&adev->jpeg.jpeg_pg_lock); + r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); unlock: mutex_unlock(&vinst->engine_reset_mutex); From fe7b22f88efdc7f51a2805cce4209e6b19e756a2 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 22 Jan 2026 10:19:28 -0500 Subject: [PATCH 0022/2070] drm/amdgpu: Send RMA CPER at bad page loading Some older builds weren't sending RMA CPERs when the bad page threshold was exceeded. Newer builds have resolved this, but there could be systems out there with bad page numbers higher than the threshold, that haven't sent out an RMA CPER. To be thorough and safe, send an RMA CPER when we load the table, if the threshold is met or exceeded, instead of waiting for the next UE to trigger the CPER. Signed-off-by: Kent Russell Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 64dd7a81bff5f..469d04a39d7d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1712,6 +1712,10 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", control->ras_num_bad_pages, ras->bad_page_cnt_threshold); + if (amdgpu_bad_page_threshold != 0 && + control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) + amdgpu_dpm_send_rma_reason(adev); + } else if (hdr->header == RAS_TABLE_HDR_BAD && amdgpu_bad_page_threshold != 0) { if (hdr->version >= RAS_TABLE_VER_V2_1) { From f70ae7cf4cc483099f43a6ec5bb2cc0c27ae511e Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 23 Jul 2025 10:07:28 -0400 Subject: [PATCH 0023/2070] drm/amdkfd: add extended capabilities to device snapshot Add additional capabilities reporting. Signed-off-by: Jonathan Kim Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 + include/uapi/linux/kfd_ioctl.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 27176b2dc7141..8f8a0975f1a7d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -1108,6 +1108,7 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); device_info.capability = topo_dev->node_props.capability; device_info.debug_prop = topo_dev->node_props.debug_prop; + device_info.capability2 = topo_dev->node_props.capability2; if (exception_clear_mask) pdd->exception_status &= ~exception_clear_mask; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 047bcb1cc0789..e72359370857c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -149,6 +149,8 @@ struct kfd_dbg_device_info_entry { __u32 num_xcc; __u32 capability; __u32 debug_prop; + __u32 capability2; + __u32 pad; }; /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ From ff962d7387523fa5c7cab584f38851954dcadc0f Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Wed, 21 Jan 2026 16:42:11 +0800 Subject: [PATCH 0024/2070] drm/amd/pm: Fix null pointer dereference issue If SMU is disabled, during RAS initialization, there will be null pointer dereference issue here. Signed-off-by: Jinzhou Su Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 6b6b05e8f7361..3f70731105a23 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -619,6 +619,9 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; + if (!smu) + return ret; + if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); From 6f086cf3f5fa1a4825428aeb7ae11275f134f1cf Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Wed, 21 Jan 2026 15:25:09 -0600 Subject: [PATCH 0025/2070] drm/amdkfd: gfx12.1 trap handler instruction fixup for VOP3PX A trap may occur in the middle of VOP3PX instruction co-issue. The PC would be restored incorrectly if left unmodified. Identify this case by examining the instruction opcode and rewind the PC 8 bytes if it occurs. Signed-off-by: Jay Cornwall Reviewed-by: Lancelot Six Reviewed-by: Vladimir Indic Cc: Shweta Khatri Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 197 +++++++++--------- .../amd/amdkfd/cwsr_trap_handler_gfx12.asm | 25 ++- 2 files changed, 121 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 39bdc98b8b6db..54fa76f374c90 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -4587,14 +4587,14 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { - 0xbfa00001, 0xbfa003ac, + 0xbfa00001, 0xbfa003be, 0xb0804009, 0xb8f8f804, 0x9178ff78, 0x00008c00, 0xb8fbf811, 0x8b6eff78, 0x00004000, 0xbfa10008, 0x8b6eff7b, 0x00000080, 0xbfa20018, 0x8b6ea07b, - 0xbfa200d1, 0xbf830010, + 0xbfa200da, 0xbf830010, 0xb8fbf811, 0xbfa0fffb, 0x8b6eff7b, 0x00000bd0, 0xbfa20010, 0xb8eef812, @@ -4605,7 +4605,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xf0000000, 0xbfa20005, 0x8b6fff6f, 0x00000200, 0xbfa20002, 0x8b6ea07b, - 0xbfa200bb, 0x9177ff77, + 0xbfa200c4, 0x9177ff77, 0x007fc000, 0xb8fa04a1, 0x847a967a, 0x8c777a77, 0xb8fa0421, 0x847a957a, @@ -4632,43 +4632,46 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xbfa00002, 0x806c846c, 0x826d806d, 0x8b6dff6d, 0x01ffffff, 0xb8fbf811, - 0xbf0d847b, 0xbfa20078, + 0xbf0d847b, 0xbfa20081, 0xf4003eb6, 0xf8000000, 0xbfc70000, 0xf4003bb6, 0xf8000008, 0x8b76ff7a, 0x80000000, 0xbfa20027, 0x9376ff7a, 0x00060019, 0x81f9a376, 0xbf0b8179, - 0xbfa20068, 0x81f9ac76, - 0xbf0b8179, 0xbfa20062, + 0xbfa2006e, 0x81f9ac76, + 0xbf0b8179, 0xbfa20068, 0x81f9b776, 0xbf0b8179, - 0xbfa2005f, 0x8b76ff7a, + 0xbfa20065, 0x8b76ff7a, 0x000001ff, 0xbf06ff76, - 0x000000fe, 0xbfa2005d, + 0x000000fe, 0xbfa20063, 0xbf06ff76, 0x000000ff, - 0xbfa20057, 0xbf06ff76, - 0x000000fa, 0xbfa20054, + 0xbfa2005d, 0xbf06ff76, + 0x000000fa, 0xbfa2005a, 0x81f9ff76, 0x000000e9, - 0xbf0b8179, 0xbfa20050, + 0xbf0b8179, 0xbfa20056, 0x8b76ff7b, 0xffff0000, 0xbf06ff76, 0xbf860000, - 0xbfa10051, 0x9376ff7b, + 0xbfa1005a, 0x9376ff7b, 0x0002000e, 0x8b79ff7b, 0x00003f00, 0x85798679, 0x8c767976, 0xb9763b01, - 0xbfa00049, 0x8b76ff7a, + 0xbfa00052, 0x8b76ff7a, 0xfc000000, 0xbf06ff76, - 0xd4000000, 0xbfa20013, + 0xd4000000, 0xbfa20019, 0xbf06ff76, 0xc8000000, - 0xbfa20027, 0x8b76ff7a, + 0xbfa2002d, 0x8b76ff7a, 0xff000000, 0xbf06ff76, - 0xcf000000, 0xbfa20039, + 0xcf000000, 0xbfa2003f, 0x8b79ff7a, 0xffff0000, + 0xbf06ff79, 0xcc330000, + 0xbfa2003d, 0xbf06ff79, + 0xcc880000, 0xbfa2003a, 0xbf06ff79, 0xcc350000, - 0xbfa20037, 0xbf06ff79, - 0xcc3a0000, 0xbfa20034, + 0xbfa2003a, 0xbf06ff79, + 0xcc3a0000, 0xbfa20037, 0xbf06ff76, 0xcc000000, - 0xbfa10031, 0x8b76ff7b, + 0xbfa10034, 0x8b76ff7b, 0x000001ff, 0xbf06ff76, 0x000000ff, 0xbfa20029, 0xbf06ff76, 0x000000fa, @@ -4691,86 +4694,92 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0x000001ff, 0xbf06ff76, 0x000000ff, 0xbfa20003, 0xbfc70000, 0xbefb006e, - 0xbfa0ffad, 0xbfc70000, - 0xbefb006f, 0xbfa0ffaa, - 0xbfc70000, 0x857a9677, - 0xb97a04a1, 0x857a9577, - 0xb97a0421, 0x857a8e77, - 0xb97a3021, 0x8bfe7e7e, - 0x8bea6a6a, 0x85788978, - 0xb9783244, 0xbe804a6c, - 0xb8faf802, 0xbf0d987a, - 0xbfa10001, 0xbfb00000, - 0x8b6dff6d, 0x01ffffff, - 0xbefa0080, 0xb97a0151, - 0x9177ff77, 0x007fc000, - 0xb8fa04a1, 0x847a967a, - 0x8c777a77, 0xb8fa0421, - 0x847a957a, 0x8c777a77, - 0xb8fa3021, 0x847a8e7a, - 0x8c777a77, 0xb980f821, - 0x00000000, 0xbf0d847b, - 0xbfa20078, 0xf4003eb6, - 0xf8000000, 0xbfc70000, - 0xf4003bb6, 0xf8000008, - 0x8b76ff7a, 0x80000000, - 0xbfa20027, 0x9376ff7a, - 0x00060019, 0x81f9a376, + 0xbfa0ffa7, 0xbfc70000, + 0xbefb006f, 0xbfa0ffa4, + 0x80ec886c, 0x82ed806d, + 0xbfa0fff7, 0xbfc70000, + 0x857a9677, 0xb97a04a1, + 0x857a9577, 0xb97a0421, + 0x857a8e77, 0xb97a3021, + 0x8bfe7e7e, 0x8bea6a6a, + 0x85788978, 0xb9783244, + 0xbe804a6c, 0xb8faf802, + 0xbf0d987a, 0xbfa10001, + 0xbfb00000, 0x8b6dff6d, + 0x01ffffff, 0xbefa0080, + 0xb97a0151, 0x9177ff77, + 0x007fc000, 0xb8fa04a1, + 0x847a967a, 0x8c777a77, + 0xb8fa0421, 0x847a957a, + 0x8c777a77, 0xb8fa3021, + 0x847a8e7a, 0x8c777a77, + 0xb980f821, 0x00000000, + 0xbf0d847b, 0xbfa20081, + 0xf4003eb6, 0xf8000000, + 0xbfc70000, 0xf4003bb6, + 0xf8000008, 0x8b76ff7a, + 0x80000000, 0xbfa20027, + 0x9376ff7a, 0x00060019, + 0x81f9a376, 0xbf0b8179, + 0xbfa2006e, 0x81f9ac76, 0xbf0b8179, 0xbfa20068, - 0x81f9ac76, 0xbf0b8179, - 0xbfa20062, 0x81f9b776, - 0xbf0b8179, 0xbfa2005f, - 0x8b76ff7a, 0x000001ff, - 0xbf06ff76, 0x000000fe, + 0x81f9b776, 0xbf0b8179, + 0xbfa20065, 0x8b76ff7a, + 0x000001ff, 0xbf06ff76, + 0x000000fe, 0xbfa20063, + 0xbf06ff76, 0x000000ff, 0xbfa2005d, 0xbf06ff76, - 0x000000ff, 0xbfa20057, + 0x000000fa, 0xbfa2005a, + 0x81f9ff76, 0x000000e9, + 0xbf0b8179, 0xbfa20056, + 0x8b76ff7b, 0xffff0000, + 0xbf06ff76, 0xbf860000, + 0xbfa1005a, 0x9376ff7b, + 0x0002000e, 0x8b79ff7b, + 0x00003f00, 0x85798679, + 0x8c767976, 0xb9763b01, + 0xbfa00052, 0x8b76ff7a, + 0xfc000000, 0xbf06ff76, + 0xd4000000, 0xbfa20019, + 0xbf06ff76, 0xc8000000, + 0xbfa2002d, 0x8b76ff7a, + 0xff000000, 0xbf06ff76, + 0xcf000000, 0xbfa2003f, + 0x8b79ff7a, 0xffff0000, + 0xbf06ff79, 0xcc330000, + 0xbfa2003d, 0xbf06ff79, + 0xcc880000, 0xbfa2003a, + 0xbf06ff79, 0xcc350000, + 0xbfa2003a, 0xbf06ff79, + 0xcc3a0000, 0xbfa20037, + 0xbf06ff76, 0xcc000000, + 0xbfa10034, 0x8b76ff7b, + 0x000001ff, 0xbf06ff76, + 0x000000ff, 0xbfa20029, 0xbf06ff76, 0x000000fa, - 0xbfa20054, 0x81f9ff76, - 0x000000e9, 0xbf0b8179, - 0xbfa20050, 0x8b76ff7b, - 0xffff0000, 0xbf06ff76, - 0xbf860000, 0xbfa10051, - 0x9376ff7b, 0x0002000e, - 0x8b79ff7b, 0x00003f00, - 0x85798679, 0x8c767976, - 0xb9763b01, 0xbfa00049, - 0x8b76ff7a, 0xfc000000, - 0xbf06ff76, 0xd4000000, - 0xbfa20013, 0xbf06ff76, - 0xc8000000, 0xbfa20027, - 0x8b76ff7a, 0xff000000, - 0xbf06ff76, 0xcf000000, - 0xbfa20039, 0x8b79ff7a, - 0xffff0000, 0xbf06ff79, - 0xcc350000, 0xbfa20037, - 0xbf06ff79, 0xcc3a0000, - 0xbfa20034, 0xbf06ff76, - 0xcc000000, 0xbfa10031, - 0x8b76ff7b, 0x000001ff, - 0xbf06ff76, 0x000000ff, - 0xbfa20029, 0xbf06ff76, - 0x000000fa, 0xbfa20026, - 0x81f6ff76, 0x000000e9, - 0xbf0b8176, 0xbfa20022, - 0x8b76ff7b, 0x0003fe00, - 0xbf06ff76, 0x0001fe00, - 0xbfa2001d, 0x8b76ff7b, - 0x07fc0000, 0xbf06ff76, - 0x03fc0000, 0xbfa20018, - 0xbfa00014, 0x9376ff7a, - 0x00040016, 0x81f68176, - 0xbf0b8176, 0xbfa20012, - 0x9376ff7a, 0x00050011, + 0xbfa20026, 0x81f6ff76, + 0x000000e9, 0xbf0b8176, + 0xbfa20022, 0x8b76ff7b, + 0x0003fe00, 0xbf06ff76, + 0x0001fe00, 0xbfa2001d, + 0x8b76ff7b, 0x07fc0000, + 0xbf06ff76, 0x03fc0000, + 0xbfa20018, 0xbfa00014, + 0x9376ff7a, 0x00040016, 0x81f68176, 0xbf0b8176, - 0xbfa2000d, 0x8b76ff7a, - 0x000001ff, 0xbf06ff76, - 0x000000ff, 0xbfa20008, - 0x8b76ff7b, 0x000001ff, + 0xbfa20012, 0x9376ff7a, + 0x00050011, 0x81f68176, + 0xbf0b8176, 0xbfa2000d, + 0x8b76ff7a, 0x000001ff, 0xbf06ff76, 0x000000ff, - 0xbfa20003, 0xbfc70000, - 0xbefb006e, 0xbfa0ffad, - 0xbfc70000, 0xbefb006f, - 0xbfa0ffaa, 0xbfc70000, + 0xbfa20008, 0x8b76ff7b, + 0x000001ff, 0xbf06ff76, + 0x000000ff, 0xbfa20003, + 0xbfc70000, 0xbefb006e, + 0xbfa0ffa7, 0xbfc70000, + 0xbefb006f, 0xbfa0ffa4, + 0x80ec886c, 0x82ed806d, + 0xbfa0fff7, 0xbfc70000, 0xbeee007e, 0xbeef007f, 0xbefe0180, 0xbefe4d84, 0xbf8a0000, 0x8b7aff7f, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm index b1b1d15bb1e71..456db81998993 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm @@ -37,6 +37,7 @@ #define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3) #define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3) #define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12) +#define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3) #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) @@ -375,9 +376,9 @@ L_TRAP_CASE: L_EXIT_TRAP: s_and_b32 ttmp1, ttmp1, ADDRESS_HI32_MASK -#if HAVE_BANKED_VGPRS +#if HAVE_INSTRUCTION_FIXUP s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) - fixup_vgpr_bank_selection() + fixup_instruction() #endif #if HAVE_XNACK @@ -418,8 +419,8 @@ L_HAVE_VGPRS: save_and_clear_xnack_state_priv(s_save_tmp) #endif -#if HAVE_BANKED_VGPRS - fixup_vgpr_bank_selection() +#if HAVE_INSTRUCTION_FIXUP + fixup_instruction() #endif /* inform SPI the readiness and wait for SPI's go signal */ @@ -1400,8 +1401,8 @@ L_BARRIER_RESTORE_LOOP: L_BARRIER_RESTORE_DONE: end -#if HAVE_BANKED_VGPRS -function fixup_vgpr_bank_selection +#if HAVE_INSTRUCTION_FIXUP +function fixup_instruction // PC read may fault if memory violation has been asserted. // In this case no further progress is expected so fixup is not needed. s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT @@ -1480,8 +1481,13 @@ L_FIXUP_NOT_VOP12C: s_cmp_eq_u32 ttmp10, 0xcf000000 // If 31:24 = 0xcf, this is VOPD3 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If VOPD3, 3 DWORD inst // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD, or VOPD3. - // Might be in VOP3P, but we must ensure we are not VOP3PX2 + // Check if we are in the middle of VOP3PX. s_and_b32 ttmp13, ttmp14, 0xffff0000 // Bits 31:16 + s_cmp_eq_u32 ttmp13, 0xcc330000 // If 31:16 = 0xcc33, this is 8 bytes past VOP3PX + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE + s_cmp_eq_u32 ttmp13, 0xcc880000 // If 31:16 = 0xcc88, this is 8 bytes past VOP3PX + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE + // Might be in VOP3P, but we must ensure we are not VOP3PX2 s_cmp_eq_u32 ttmp13, 0xcc350000 // If 31:16 = 0xcc35, this is VOP3PX2 s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed s_cmp_eq_u32 ttmp13, 0xcc3a0000 // If 31:16 = 0xcc3a, this is VOP3PX2 @@ -1542,6 +1548,11 @@ L_FIXUP_THREE_DWORD: s_mov_b32 ttmp15, ttmp3 // Move possible S_SET_VGPR_MSB into ttmp15 s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB +L_FIXUP_VOP3PX_MIDDLE: + s_sub_co_u32 ttmp0, ttmp0, 8 // Rewind PC 8 bytes to beginning of instruction + s_sub_co_ci_u32 ttmp1, ttmp1, 0 + s_branch L_FIXUP_TWO_DWORD // 2 DWORD inst (2nd half of a 4 DWORD inst) + L_FIXUP_DONE: s_wait_kmcnt 0 // Ensure load of ttmp2 and ttmp3 is done end From 2617caedef13c9d6abec051620e2c81696679973 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 16 Jan 2026 17:33:05 -0500 Subject: [PATCH 0026/2070] drm/amdgpu/soc21: fix xclk for APUs The reference clock is supposed to be 100Mhz, but it appears to actually be slightly lower (99.81Mhz). Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14451 Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 2da733b45c21a..d9cc649d81ad4 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -256,7 +256,13 @@ static u32 soc21_get_config_memsize(struct amdgpu_device *adev) static u32 soc21_get_xclk(struct amdgpu_device *adev) { - return adev->clock.spll.reference_freq; + u32 reference_clock = adev->clock.spll.reference_freq; + + /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ + if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) + return 9981; + + return reference_clock; } From 026faef60e04c0a7d5aea955ba4fec5c034e6413 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 26 Jan 2026 23:44:45 -0500 Subject: [PATCH 0027/2070] drm/amdgpu: Fix cond_exec handling in amdgpu_ib_schedule() The EXEC_COUNT field must be > 0. In the gfx shadow handling we always emit a cond_exec packet after the gfx_shadow packet, but the EXEC_COUNT never gets patched. This leads to a hang when we try and reset queues on gfx11 APUs. Fixes: c68cbbfd54c6 ("drm/amdgpu: cleanup conditional execution") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4789 Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 72ec455fa932c..44f230d67da24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -235,7 +235,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_ib_begin(ring); - if (ring->funcs->emit_gfx_shadow) + if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, init_shadow, vmid); @@ -291,7 +291,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, fence_flags | AMDGPU_FENCE_FLAG_64BIT); } - if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) { + if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec && + adev->gfx.cp_gfx_shadow) { amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0); amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); } From c66e4b399e11f36c3dbcc9f339ee73ebfacd0de6 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 28 Jan 2026 11:35:57 +0800 Subject: [PATCH 0028/2070] drm/amdgpu: validate user queue size constraints MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add validation to ensure user queue sizes meet hardware requirements: - Size must be a power of two for efficient ring buffer wrapping - Size must be at least AMDGPU_GPU_PAGE_SIZE to prevent undersized allocations This prevents invalid configurations that could lead to GPU faults or unexpected behavior. Reviewed-by: Christian König Signed-off-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b0ebf19db10b7..b700c2b914654 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -932,6 +932,17 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, drm_file_err(filp, "invalidate userq queue va or size\n"); return -EINVAL; } + + if (!is_power_of_2(args->in.queue_size)) { + drm_file_err(filp, "Queue size must be a power of 2\n"); + return -EINVAL; + } + + if (args->in.queue_size < AMDGPU_GPU_PAGE_SIZE) { + drm_file_err(filp, "Queue size smaller than AMDGPU_GPU_PAGE_SIZE\n"); + return -EINVAL; + } + if (!args->in.wptr_va || !args->in.rptr_va) { drm_file_err(filp, "invalidate userq queue rptr or wptr\n"); return -EINVAL; From e78e1a41c5cbb319193730b3b02dbad4223881df Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 10:08:25 +0800 Subject: [PATCH 0029/2070] drm/amdgpu: Add a helper macro to align mqd size MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) as fence address and writes a 32 bit fence value to this address. Driver needs to allocate some extra memory(at least 4 DWs) in addition to sizeof(struct mqd) as mqd memory(limited to gfx/compute/sdma queue). For gfx11/12, sizeof(struct mqd) < PAGE_SIZE, KGD allocates mqd memory with PAGE_SIZE aligned works. For gfx12.1, sizeof(struct mqd) == PAGE_SIZE, it doesn't work. KFD mqd manager hardcodes mqd size to PAGE_SIZE/MQD_SIZE across different IP versions to solve this issue. To avoid hardcoding in differnet places and across different IP versions. Let's use AMDGPU_MQD_SIZE_ALIGN instead. It is used in two places. 1. mqd memory alloction 2. mqd stride handling for multi xcc config v2: Use AMDGPU_GPU_PAGE_ALIGN. (Mukul) Signed-off-by: Lang Yu Reviewed-by: David Belanger (v1) Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 9c11535c44c69..447e734c362be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1239,6 +1239,14 @@ struct amdgpu_device { struct amdgpu_kfd_dev kfd; }; +/* + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) + * as fence address and writes a 32 bit fence value to this address. + * Driver needs to allocate at least 4 DWs extra memory in addition to + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. + */ +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) + static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, uint8_t ip, uint8_t inst) { From 26f85ff2735c51b6f36153748769e92e64847c25 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 16 Jan 2026 12:07:39 +0530 Subject: [PATCH 0030/2070] drm/amd/pm: Add smu feature bits data struct Add a bitmap struct to represent smu feature bits and functions to set/clear features. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 1def04826f106..017df903a7bde 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -472,6 +472,11 @@ struct smu_power_context { }; #define SMU_FEATURE_MAX (64) + +struct smu_feature_bits { + DECLARE_BITMAP(bits, SMU_FEATURE_MAX); +}; + struct smu_feature { uint32_t feature_num; DECLARE_BITMAP(supported, SMU_FEATURE_MAX); @@ -1974,4 +1979,80 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id); + +static inline bool smu_feature_bits_is_set(const struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit >= SMU_FEATURE_MAX) + return false; + + return test_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_set_bit(struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit < SMU_FEATURE_MAX) + __set_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_clear_bit(struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit < SMU_FEATURE_MAX) + __clear_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_clearall(struct smu_feature_bits *bits) +{ + bitmap_zero(bits->bits, SMU_FEATURE_MAX); +} + +static inline void smu_feature_bits_fill(struct smu_feature_bits *bits) +{ + bitmap_fill(bits->bits, SMU_FEATURE_MAX); +} + +static inline bool +smu_feature_bits_test_mask(const struct smu_feature_bits *bits, + const unsigned long *mask) +{ + return bitmap_intersects(bits->bits, mask, SMU_FEATURE_MAX); +} + +static inline void smu_feature_bits_from_arr32(struct smu_feature_bits *bits, + const uint32_t *arr, + unsigned int nbits) +{ + bitmap_from_arr32(bits->bits, arr, nbits); +} + +static inline void +smu_feature_bits_to_arr32(const struct smu_feature_bits *bits, uint32_t *arr, + unsigned int nbits) +{ + bitmap_to_arr32(arr, bits->bits, nbits); +} + +static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits, + unsigned int nbits) +{ + return bitmap_empty(bits->bits, nbits); +} + +static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, + const unsigned long *src, + unsigned int nbits) +{ + bitmap_copy(dst->bits, src, nbits); +} + +static inline void smu_feature_bits_or(struct smu_feature_bits *dst, + const struct smu_feature_bits *src1, + const unsigned long *src2, + unsigned int nbits) +{ + bitmap_or(dst->bits, src1->bits, src2, nbits); +} + #endif From b8533f5b5a8a9c782545c48e92da87a2256d646a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 12:00:29 +0530 Subject: [PATCH 0031/2070] drm/amd/pm: Add smu feature interface functions Instead of using bitmap operations, add wrapper interface functions to operate on smu features. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 ++-- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 104 +++++++++++++++++- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 +- .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 4 +- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 4 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 +- 7 files changed, 120 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 3f70731105a23..b635792f59068 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -693,7 +693,6 @@ static int smu_sys_set_pp_table(void *handle, static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) { - struct smu_feature *feature = &smu->smu_feature; uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; int ret = 0; @@ -705,20 +704,19 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) * such scenario. */ if (smu->adev->scpm_enabled) { - bitmap_fill(feature->allowed, SMU_FEATURE_MAX); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } - bitmap_zero(feature->allowed, SMU_FEATURE_MAX); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, SMU_FEATURE_MAX/32); if (ret) return ret; - bitmap_or(feature->allowed, feature->allowed, - (unsigned long *)allowed_feature_mask, - feature->feature_num); + smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED, + (unsigned long *)allowed_feature_mask); return ret; } @@ -1368,9 +1366,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) int i, ret; smu->pool_size = adev->pm.smu_prv_buffer_size; - smu->smu_feature.feature_num = SMU_FEATURE_MAX; - bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); - bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); + smu_feature_init(smu, SMU_FEATURE_MAX); INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); @@ -1659,7 +1655,6 @@ static void smu_wbrf_fini(struct smu_context *smu) static int smu_smc_hw_setup(struct smu_context *smu) { - struct smu_feature *feature = &smu->smu_feature; struct amdgpu_device *adev = smu->adev; uint8_t pcie_gen = 0, pcie_width = 0; uint64_t features_supported; @@ -1822,9 +1817,8 @@ static int smu_smc_hw_setup(struct smu_context *smu) dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); return ret; } - bitmap_copy(feature->supported, - (unsigned long *)&features_supported, - feature->feature_num); + smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, + (unsigned long *)&features_supported); if (!smu_is_dpm_running(smu)) dev_info(adev->dev, "dpm has been disabled\n"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 017df903a7bde..2290298579e1e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -477,10 +477,15 @@ struct smu_feature_bits { DECLARE_BITMAP(bits, SMU_FEATURE_MAX); }; +enum smu_feature_list { + SMU_FEATURE_LIST_SUPPORTED, + SMU_FEATURE_LIST_ALLOWED, + SMU_FEATURE_LIST_MAX, +}; + struct smu_feature { uint32_t feature_num; - DECLARE_BITMAP(supported, SMU_FEATURE_MAX); - DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); + struct smu_feature_bits bits[SMU_FEATURE_LIST_MAX]; }; struct smu_clocks { @@ -2055,4 +2060,99 @@ static inline void smu_feature_bits_or(struct smu_feature_bits *dst, bitmap_or(dst->bits, src1->bits, src2, nbits); } +static inline struct smu_feature_bits * +__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list) +{ + if (unlikely(list >= SMU_FEATURE_LIST_MAX)) { + dev_warn(smu->adev->dev, "Invalid feature list: %d\n", list); + return &smu->smu_feature.bits[SMU_FEATURE_LIST_SUPPORTED]; + } + + return &smu->smu_feature.bits[list]; +} + +static inline bool smu_feature_list_is_set(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return false; + + return smu_feature_bits_is_set(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_set_bit(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return; + + smu_feature_bits_set_bit(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_clear_bit(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return; + + smu_feature_bits_clear_bit(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_set_all(struct smu_context *smu, + enum smu_feature_list list) +{ + smu_feature_bits_fill(__smu_feature_get_list(smu, list)); +} + +static inline void smu_feature_list_clear_all(struct smu_context *smu, + enum smu_feature_list list) +{ + smu_feature_bits_clearall(__smu_feature_get_list(smu, list)); +} + +static inline bool smu_feature_list_is_empty(struct smu_context *smu, + enum smu_feature_list list) +{ + return smu_feature_bits_empty(__smu_feature_get_list(smu, list), + smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_set_bits(struct smu_context *smu, + enum smu_feature_list dst_list, + const unsigned long *src) +{ + smu_feature_bits_copy(__smu_feature_get_list(smu, dst_list), src, + smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_add_bits(struct smu_context *smu, + enum smu_feature_list list, + const unsigned long *src) +{ + struct smu_feature_bits *bits = __smu_feature_get_list(smu, list); + + smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_to_arr32(struct smu_context *smu, + enum smu_feature_list list, + uint32_t *arr) +{ + smu_feature_bits_to_arr32(__smu_feature_get_list(smu, list), arr, + smu->smu_feature.feature_num); +} + +static inline void smu_feature_init(struct smu_context *smu, int feature_num) +{ + if (!feature_num || smu->smu_feature.feature_num != 0) + return; + + smu->smu_feature.feature_num = feature_num; + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_SUPPORTED); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); +} + #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index eb1b9faf8e5c3..1d0f9f8ddf9b5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -750,12 +750,13 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || + feature->feature_num < 64) { ret = -EINVAL; goto failed; } - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 70581326dc368..3b0aa6a2e78ed 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -761,11 +761,11 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || feature->feature_num < 64) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index 17caf98bd6ddc..cabbd234c6e2c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -746,11 +746,11 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || feature->feature_num < 64) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index 6557085a7c728..d77eaac556d9b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -715,11 +715,11 @@ int smu_v15_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || feature->feature_num < 64) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 24835600c1cd8..9bb7e3760c0ff 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -677,7 +677,6 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu, int smu_cmn_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask) { - struct smu_feature *feature = &smu->smu_feature; int feature_id; feature_id = smu_cmn_to_asic_specific_index(smu, @@ -686,9 +685,8 @@ int smu_cmn_feature_is_supported(struct smu_context *smu, if (feature_id < 0) return 0; - WARN_ON(feature_id > feature->feature_num); - - return test_bit(feature_id, feature->supported); + return smu_feature_list_is_set(smu, SMU_FEATURE_LIST_SUPPORTED, + feature_id); } static int __smu_get_enabled_features(struct smu_context *smu, From 8b72cdaa92fe4f9bd9e589bf78520ba14809a74f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 12:14:47 +0530 Subject: [PATCH 0032/2070] drm/amd/pm: Remove unused logic in SMUv14.0.2 Remove commented and redundant logic in get_allowed_feature_mask implementation. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 39 ------------------- 1 file changed, 39 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index faae1da81bd4e..d2aa5fabfca4a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -268,50 +268,11 @@ static int smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) { - struct amdgpu_device *adev = smu->adev; - /*u32 smu_version;*/ - if (num > 2) return -EINVAL; memset(feature_mask, 0xff, sizeof(uint32_t) * num); - if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); - } -#if 0 - if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || - !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); - - if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); - - /* PMFW 78.58 contains a critical fix for gfxoff feature */ - smu_cmn_get_smc_version(smu, NULL, &smu_version); - if ((smu_version < 0x004e3a00) || - !(adev->pm.pp_feature & PP_GFXOFF_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); - - if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); - } - - if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); - - if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); - } - - if (!(adev->pm.pp_feature & PP_ULV_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); -#endif - return 0; } From 040a70d5b5f29af314003647d57d5983319c2d40 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 12:19:40 +0530 Subject: [PATCH 0033/2070] drm/amd/pm: Initialize allowed feature list Instead of returning feature bit mask of allowed features, initialize the allowed features in the callback implementation itself. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 +--- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 24 +---- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 11 +-- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 92 +++++++++---------- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 89 +++++++++--------- .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 11 +-- .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 35 +++---- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 12 +-- .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 80 ++++++++-------- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 11 +-- drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 2 +- 11 files changed, 158 insertions(+), 226 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index b635792f59068..75897ac203c32 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -691,11 +691,8 @@ static int smu_sys_set_pp_table(void *handle, return ret; } -static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) +static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) { - uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; - int ret = 0; - /* * With SCPM enabled, the allowed featuremasks setting(via * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. @@ -710,15 +707,7 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); - ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, - SMU_FEATURE_MAX/32); - if (ret) - return ret; - - smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED, - (unsigned long *)allowed_feature_mask); - - return ret; + return smu_init_allowed_features(smu); } static int smu_set_funcs(struct amdgpu_device *adev) @@ -1949,7 +1938,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block) if (!smu->pm_enabled) return 0; - ret = smu_get_driver_allowed_feature_mask(smu); + ret = smu_init_driver_allowed_feature_mask(smu); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 2290298579e1e..7c63c631f6d42 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -812,11 +812,10 @@ struct pptable_funcs { int (*run_btc)(struct smu_context *smu); /** - * @get_allowed_feature_mask: Get allowed feature mask. - * &feature_mask: Array to store feature mask. - * &num: Elements in &feature_mask. + * @init_allowed_features: Initialize allowed features bitmap. + * Directly sets allowed features using smu_feature wrapper functions. */ - int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); + int (*init_allowed_features)(struct smu_context *smu); /** * @get_current_power_state: Get the current power state. @@ -2052,14 +2051,6 @@ static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, bitmap_copy(dst->bits, src, nbits); } -static inline void smu_feature_bits_or(struct smu_feature_bits *dst, - const struct smu_feature_bits *src1, - const unsigned long *src2, - unsigned int nbits) -{ - bitmap_or(dst->bits, src1->bits, src2, nbits); -} - static inline struct smu_feature_bits * __smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list) { @@ -2128,15 +2119,6 @@ static inline void smu_feature_list_set_bits(struct smu_context *smu, smu->smu_feature.feature_num); } -static inline void smu_feature_list_add_bits(struct smu_context *smu, - enum smu_feature_list list, - const unsigned long *src) -{ - struct smu_feature_bits *bits = __smu_feature_get_list(smu, list); - - smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num); -} - static inline void smu_feature_list_to_arr32(struct smu_context *smu, enum smu_feature_list list, uint32_t *arr) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 7c5ce6a6e2ca7..b22a0e91826dc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -345,14 +345,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu) } static int -arcturus_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +arcturus_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -1877,7 +1872,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, static const struct pptable_funcs arcturus_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, + .init_allowed_features = arcturus_init_allowed_features, /* btc */ .run_btc = arcturus_run_btc, /* dpm/clk tables */ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 1f84654bbc85f..f14eed0525265 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -275,89 +275,83 @@ static bool is_asic_secure(struct smu_context *smu) } static int -navi10_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +navi10_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) - | FEATURE_MASK(FEATURE_PPT_BIT) - | FEATURE_MASK(FEATURE_TDC_BIT) - | FEATURE_MASK(FEATURE_GFX_EDC_BIT) - | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) - | FEATURE_MASK(FEATURE_VR0HOT_BIT) - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) - | FEATURE_MASK(FEATURE_THERMAL_BIT) - | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) - | FEATURE_MASK(FEATURE_DS_LCLK_BIT) - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) - | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) - | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT); if (smu->dc_controlled_by_gpio) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ if (!(is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) && - (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); + } - /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ if (is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) - *(uint64_t *)feature_mask &= - ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); return 0; } @@ -3277,7 +3271,7 @@ static int navi10_set_config_table(struct smu_context *smu, } static const struct pptable_funcs navi10_ppt_funcs = { - .get_allowed_feature_mask = navi10_get_allowed_feature_mask, + .init_allowed_features = navi10_init_allowed_features, .set_default_dpm_table = navi10_set_default_dpm_table, .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index f930ba2733e93..98a02fc082143 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -276,85 +276,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = { }; static int -sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +sienna_cichlid_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_DS_FCLK_BIT) - | FEATURE_MASK(FEATURE_DS_UCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) - | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) - | FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_VR0HOT_BIT) - | FEATURE_MASK(FEATURE_PPT_BIT) - | FEATURE_MASK(FEATURE_TDC_BIT) - | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) - | FEATURE_MASK(FEATURE_THERMAL_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT); } if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && !(adev->flags & AMD_IS_APU)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT); - if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); + } if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT); if (smu->dc_controlled_by_gpio) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); if (amdgpu_device_should_use_aspm(adev)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); return 0; } @@ -3085,7 +3082,7 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu) } static const struct pptable_funcs sienna_cichlid_ppt_funcs = { - .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, + .init_allowed_features = sienna_cichlid_init_allowed_features, .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 9de0b676bb7bf..3b6a34644a920 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -329,14 +329,9 @@ static int aldebaran_init_smc_tables(struct smu_context *smu) return smu_v13_0_init_smc_tables(smu); } -static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +static int aldebaran_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -1967,7 +1962,7 @@ static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, static const struct pptable_funcs aldebaran_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, + .init_allowed_features = aldebaran_init_allowed_features, /* dpm/clk tables */ .set_default_dpm_table = aldebaran_set_default_dpm_table, .populate_umd_state_clk = aldebaran_populate_umd_state_clk, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index ce52b616b9359..9c4298736b289 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -287,49 +287,44 @@ static const uint8_t smu_v13_0_0_throttler_map[] = { }; static int -smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +smu_v13_0_0_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0xff, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); } if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); - /* PMFW 78.58 contains a critical fix for gfxoff feature */ if ((smu->smc_fw_version < 0x004e3a00) || !(adev->pm.pp_feature & PP_GFXOFF_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); } if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); } if (!(adev->pm.pp_feature & PP_ULV_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); return 0; } @@ -3130,7 +3125,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, } static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { - .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_0_init_allowed_features, .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, .i2c_init = smu_v13_0_0_i2c_control_init, .i2c_fini = smu_v13_0_0_i2c_control_fini, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 1e82c43c851aa..bd893e95515f8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -742,15 +742,9 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu) return smu_v13_0_fini_smc_tables(smu); } -static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, - uint32_t num) +static int smu_v13_0_6_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -3836,7 +3830,7 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_6_init_allowed_features, /* dpm/clk tables */ .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table, .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 0375e8484b2a9..415766dbfe6cf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -265,71 +265,67 @@ static const uint8_t smu_v13_0_7_throttler_map[] = { }; static int -smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +smu_v13_0_7_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); } if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); } - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT); if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); return 0; } @@ -2736,7 +2732,7 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, } static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { - .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_7_init_allowed_features, .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, .is_dpm_running = smu_v13_0_7_is_dpm_running, .init_microcode = smu_v13_0_init_microcode, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index d2aa5fabfca4a..3c351ee41e684 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -264,14 +264,9 @@ static const uint8_t smu_v14_0_2_throttler_map[] = { [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), }; -static int -smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +static int smu_v14_0_2_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0xff, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -2757,7 +2752,7 @@ static int smu_v14_0_2_set_power_limit(struct smu_context *smu, } static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { - .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask, + .init_allowed_features = smu_v14_0_2_init_allowed_features, .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table, .i2c_init = smu_v14_0_2_i2c_control_init, .i2c_fini = smu_v14_0_2_i2c_control_fini, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index 0f7778410a3ad..24848da902343 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -70,7 +70,7 @@ #define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu) #define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu) #define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu) -#define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) +#define smu_init_allowed_features(smu) smu_ppt_funcs(init_allowed_features, 0, smu) #define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges) #define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw) #define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu) From a7f2e2a452647e0b3405f690dd18249b89cca46b Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 16:47:39 +0800 Subject: [PATCH 0034/2070] drm/amdgpu: Use AMDGPU_MQD_SIZE_ALIGN in KGD Use AMDGPU_MQD_SIZE_ALIGN for both kernel and user queue. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 18 ++++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 3 ++- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 8b5801d7109c2..77578ecc67828 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -385,6 +385,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; struct amdgpu_ring *ring = &kiq->ring; u32 domain = AMDGPU_GEM_DOMAIN_GTT; + u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size); + u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size); #if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ @@ -424,17 +426,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, for (i = 0; i < adev->gfx.num_gfx_rings; i++) { ring = &adev->gfx.gfx_ring[i]; if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - domain, &ring->mqd_obj, + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size), + PAGE_SIZE, domain, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); return r; } - ring->mqd_size = mqd_size; + ring->mqd_size = gfx_mqd_size; /* prepare MQD backup */ - adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL); + adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL); if (!adev->gfx.me.mqd_backup[i]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; @@ -448,17 +450,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, j = i + xcc_id * adev->gfx.num_compute_rings; ring = &adev->gfx.compute_ring[j]; if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - domain, &ring->mqd_obj, + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size), + PAGE_SIZE, domain, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); return r; } - ring->mqd_size = mqd_size; + ring->mqd_size = compute_mqd_size; /* prepare MQD backup */ - adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL); + adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL); if (!adev->gfx.mec.mqd_backup[j]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 08ae50a6313f3..eb9725ae1607a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2236,7 +2236,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : - sizeof(struct v12_1_compute_mqd); + AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); mqd->cp_hqd_active = prop->hqd_active; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index f2309d72bbe67..9508709abd49a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -289,7 +289,8 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, return -ENOMEM; } - r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size); + r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, + AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); if (r) { DRM_ERROR("Failed to create MQD object for userqueue\n"); goto free_props; From 06f7ec0203a49fd6918c14cfa37f6fd958ffa6e2 Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 16:57:01 +0800 Subject: [PATCH 0035/2070] drm/amdkfd: Adjust parameter of allocate_mqd Make allocate_mqd consistent with other callbacks. Prepare for next patch to use mqd_manager->mqd_size. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 6 ++++-- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 ++- 11 files changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index b542de9d50d11..804851632c4c8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -676,7 +676,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, /* Temporarily release dqm lock to avoid a circular lock dependency */ dqm_unlock(dqm); - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); dqm_lock(dqm); if (!q->mqd_mem_obj) { @@ -2002,7 +2002,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, dqm->asic_ops.init_sdma_vm(dqm, q, qpd); q->properties.tba_addr = qpd->tba_addr; q->properties.tma_addr = qpd->tma_addr; - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); if (!q->mqd_mem_obj) { retval = -ENOMEM; goto out_deallocate_doorbell; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 961a4b84e974d..d987ff7ccfc95 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -130,7 +130,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, kq->queue->device = dev; - kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr->dev, + kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr, &kq->queue->properties); if (!kq->queue->mqd_mem_obj) goto err_allocate_mqd; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index f78b249e1a419..ceb6566ff3e1d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -46,9 +46,10 @@ int pipe_priority_map[] = { KFD_PIPE_PRIORITY_CS_HIGH }; -struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properties *q) +struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q) { struct kfd_mem_obj *mqd_mem_obj; + struct kfd_node *dev = mm->dev; mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); if (!mqd_mem_obj) @@ -61,10 +62,11 @@ struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properti return mqd_mem_obj; } -struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, struct queue_properties *q) { struct kfd_mem_obj *mqd_mem_obj; + struct kfd_node *dev = mm->dev; uint64_t offset; mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 17cc1f25c8d08..2429d278ef0eb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -68,7 +68,7 @@ */ extern int pipe_priority_map[]; struct mqd_manager { - struct kfd_mem_obj* (*allocate_mqd)(struct kfd_node *kfd, + struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm, struct queue_properties *q); void (*init_mqd)(struct mqd_manager *mm, void **mqd, @@ -153,10 +153,10 @@ struct mqd_user_context_save_area_header { uint32_t wave_state_size; }; -struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q); -struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, struct queue_properties *q); void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 05f3ac2eaef9e..90ac3a30e81d2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -73,9 +73,10 @@ static void set_priority(struct cik_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 1695dd78ede8e..97055f808d4a1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -73,9 +73,10 @@ static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 3c0ae28c5923b..5c44d09877374 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -99,9 +99,10 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; int size; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index 729df66ebfb3c..b7ac2dea87758 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -80,9 +80,10 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index 558216395a4dc..0b0d802a09173 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -145,9 +145,10 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; unsigned int size; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index d867dccae6758..dcf4bbfa641b5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -120,10 +120,11 @@ static bool mqd_on_vram(struct amdgpu_device *adev) } } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { int retval; + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj = NULL; /* For V9 only, due to a HW bug, the control stack of a user mode diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index c1fafc5025158..09483f0862d41 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -76,9 +76,10 @@ static void set_priority(struct vi_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd), From 2107cf63ba9302fd46e8ec8764e63010d844a79a Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 17:38:01 +0800 Subject: [PATCH 0036/2070] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager MES is enabled by default from gfx11+, use AMDGPU_MQD_SIZE_ALIGN unconditionally for gfx11+. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 3 ++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 22 +++----------- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 10 +++---- .../drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 29 ++++--------------- 4 files changed, 17 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index ceb6566ff3e1d..d88d0de58edd1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -292,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj, uint64_t kfd_mqd_stride(struct mqd_manager *mm, struct queue_properties *q) { + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0)) + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + return mm->mqd_size; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 5c44d09877374..7e5a7ab6d0c01 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -102,20 +102,11 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - int size; - - /* - * MES write to areas beyond MQD size. So allocate - * 1 PAGE_SIZE memory for MQD is MES is enabled. - */ - if (node->kfd->shared_resources.enable_mes) - size = PAGE_SIZE; - else - size = sizeof(struct v11_compute_mqd); - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -127,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v11_compute_mqd *m; - int size; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff; m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - if (mm->dev->kfd->shared_resources.enable_mes) - size = PAGE_SIZE; - else - size = sizeof(struct v11_compute_mqd); - - memset(m, 0, size); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index b7ac2dea87758..a51f217329db0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -83,14 +83,11 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - /* - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond - * struct MQD size. - */ - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -102,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v12_compute_mqd *m; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - memset(m, 0, PAGE_SIZE); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index 0b0d802a09173..d0776ba2cc999 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -32,17 +32,6 @@ #include "amdgpu_amdkfd.h" #include "kfd_device_queue_manager.h" -#define MQD_SIZE (2 * PAGE_SIZE) - -static uint64_t mqd_stride_v12_1(struct mqd_manager *mm, - struct queue_properties *q) -{ - if (q->type == KFD_QUEUE_TYPE_COMPUTE) - return MQD_SIZE; - else - return PAGE_SIZE; -} - static inline struct v12_1_compute_mqd *get_mqd(void *mqd) { return (struct v12_1_compute_mqd *)mqd; @@ -148,21 +137,14 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - unsigned int size; - /* - * Allocate two PAGE_SIZE memory for Compute MQD as MES writes to areas beyond - * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE. - * For SDMA MQD, we allocate 1 Page_size. - */ if (q->type == KFD_QUEUE_TYPE_COMPUTE) - size = MQD_SIZE * NUM_XCC(node->xcc_mask); - else - size = PAGE_SIZE; + mqd_size *= NUM_XCC(node->xcc_mask); - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -174,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v12_1_compute_mqd *m; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - memset(m, 0, MQD_SIZE); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; @@ -681,7 +664,7 @@ struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, mqd->is_occupied = kfd_is_occupied_cp; mqd->mqd_size = sizeof(struct v12_1_compute_mqd); mqd->get_wave_state = get_wave_state_v12_1; - mqd->mqd_stride = mqd_stride_v12_1; + mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif From 0ab473aabb927ead26dac0d97d68616462244dad Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 20:51:08 -0500 Subject: [PATCH 0037/2070] drm/amdgpu/gfx10: fix wptr reset in KGQ init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with what we already do for KCQs. Reviewed-by: Timur Kristóf Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 41bbedb8e157e..1893ceeeb26c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6880,7 +6880,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset the ring */ ring->wptr = 0; - *ring->wptr_cpu_addr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } From 2afd6aecece03553ffb7a443a2fd859073eb1d6c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 18:09:03 -0500 Subject: [PATCH 0038/2070] drm/amdgpu/gfx11: fix wptr reset in KGQ init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with what we already do for KCQs. Reviewed-by: Timur Kristóf Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 3a4ca104b1612..7bc593889c71e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4214,7 +4214,7 @@ static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset the ring */ ring->wptr = 0; - *ring->wptr_cpu_addr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } From e07ef0f457455c96543d040cc99a11c97a3e961d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 18:13:16 -0500 Subject: [PATCH 0039/2070] drm/amdgpu/gfx12: fix wptr reset in KGQ init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with what we already do for KCQs. Reviewed-by: Timur Kristóf Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 40660b05f9794..3aec7ea773fcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3085,7 +3085,7 @@ static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset the ring */ ring->wptr = 0; - *ring->wptr_cpu_addr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } From 78a51b3e3ed38134610a1f55e305a9422f4df6f5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 22:55:46 -0500 Subject: [PATCH 0040/2070] drm/amdgpu/gfx11: adjust KGQ reset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel gfx queues do not need to be reinitialized or remapped after a reset. This fixes queue reset failures on APUs. v2: preserve init and remap for MMIO case. Fixes: b3e9bfd86658 ("drm/amdgpu/gfx11: add ring reset callbacks") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4789 Reviewed-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 7bc593889c71e..427975b5a1d97 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6828,11 +6828,12 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; + bool use_mmio = false; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); if (r) { dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); @@ -6841,16 +6842,18 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = gfx_v11_0_kgq_init_queue(ring, true); - if (r) { - dev_err(adev->dev, "failed to init kgq\n"); - return r; - } + if (use_mmio) { + r = gfx_v11_0_kgq_init_queue(ring, true); + if (r) { + dev_err(adev->dev, "failed to init kgq\n"); + return r; + } - r = amdgpu_mes_map_legacy_queue(adev, ring, 0); - if (r) { - dev_err(adev->dev, "failed to remap kgq\n"); - return r; + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); + if (r) { + dev_err(adev->dev, "failed to remap kgq\n"); + return r; + } } return amdgpu_ring_reset_helper_end(ring, timedout_fence); From 08df0e26890a810f7150971c2fa4819acad485a8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 23:05:50 -0500 Subject: [PATCH 0041/2070] drm/amdgpu/gfx12: adjust KGQ reset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel gfx queues do not need to be reinitialized or remapped after a reset. Align with gfx11. v2: preserve init and remap for MMIO case. Reviewed-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 3aec7ea773fcf..79ea1af363a53 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5292,11 +5292,12 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; + bool use_mmio = false; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); if (r) { dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); r = gfx_v12_reset_gfx_pipe(ring); @@ -5304,16 +5305,18 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = gfx_v12_0_kgq_init_queue(ring, true); - if (r) { - dev_err(adev->dev, "failed to init kgq\n"); - return r; - } + if (use_mmio) { + r = gfx_v12_0_kgq_init_queue(ring, true); + if (r) { + dev_err(adev->dev, "failed to init kgq\n"); + return r; + } - r = amdgpu_mes_map_legacy_queue(adev, ring, 0); - if (r) { - dev_err(adev->dev, "failed to remap kgq\n"); - return r; + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); + if (r) { + dev_err(adev->dev, "failed to remap kgq\n"); + return r; + } } return amdgpu_ring_reset_helper_end(ring, timedout_fence); From a33c5dd16c7b2b070c17f241ea22295ce19c3e73 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 28 Jan 2026 13:54:31 +0800 Subject: [PATCH 0042/2070] drm/amdgpu: ensure no_hw_access is visible before MMIO Add a full memory barrier after clearing no_hw_access in amdgpu_device_mode1_reset() so subsequent PCI state restore access cannot observe stale state on other CPUs. Fixes: 7edb503fe4b6 ("drm/amd/pm: Disable MMIO access during SMU Mode 1 reset") Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c7f44422939f7..c1ffc63e23ab5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5733,6 +5733,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) /* enable mmio access after mode 1 reset completed */ adev->no_hw_access = false; + /* ensure no_hw_access is updated before we access hw */ + smp_mb(); + amdgpu_device_load_pci_state(adev->pdev); ret = amdgpu_psp_wait_for_bootloader(adev); if (ret) From 6ff8114c93098e4121f2b80c9e0808304ac10e37 Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Tue, 10 Sep 2019 11:24:42 -0400 Subject: [PATCH 0043/2070] Add rock-dbg_defconfig which turns on KFD This file only turns on a substantial smaller set of kernel options, together with all AMD stuff, and supports most use cases on common HW configurations. As a result, building kernel with this config is super fast. Moreover, with this config, KFD folks can easily build the kernel with build_kernel.sh script and verify the change before we push the commit out for review on amd-gfx mailist. Signed-off-by: Yong Zhao Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 4688 +++++++++++++++++++++++++++ 1 file changed, 4688 insertions(+) create mode 100644 arch/x86/configs/rock-dbg_defconfig diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig new file mode 100644 index 0000000000000..5e1de51be9553 --- /dev/null +++ b/arch/x86/configs/rock-dbg_defconfig @@ -0,0 +1,4688 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/x86 5.3.0-rc3 Kernel Configuration +# + +# +# Compiler: gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70400 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set +CONFIG_LOCALVERSION="-kfd" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# CONFIG_CPU_ISOLATION is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_BUILD_BIN2C=y +# CONFIG_IKCONFIG is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +# CONFIG_MEMCG_SWAP_ENABLED is not set +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_BPF_SYSCALL=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_X86_64=y +CONFIG_X86=y +CONFIG_INSTRUCTION_DECODER=y +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ZONE_DMA32=y +CONFIG_AUDIT_ARCH=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_X86_64_SMP=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CC_HAS_SANE_STACKPROTECTOR=y + +# +# Processor type and features +# +CONFIG_ZONE_DMA=y +CONFIG_SMP=y +CONFIG_X86_FEATURE_NAMES=y +# CONFIG_X86_X2APIC is not set +CONFIG_X86_MPPARSE=y +# CONFIG_GOLDFISH is not set +# CONFIG_RETPOLINE is not set +# CONFIG_X86_CPU_RESCTRL is not set +CONFIG_X86_EXTENDED_PLATFORM=y +# CONFIG_X86_VSMP is not set +# CONFIG_X86_GOLDFISH is not set +CONFIG_X86_INTEL_LPSS=y +# CONFIG_X86_AMD_PLATFORM_DEVICE is not set +CONFIG_IOSF_MBI=y +CONFIG_IOSF_MBI_DEBUG=y +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT_DEBUG is not set +CONFIG_PARAVIRT_SPINLOCKS=y +# CONFIG_XEN is not set +CONFIG_KVM_GUEST=y +# CONFIG_PVH is not set +CONFIG_KVM_DEBUG_FS=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_JAILHOUSE_GUEST is not set +# CONFIG_ACRN_GUEST is not set +# CONFIG_MK8 is not set +# CONFIG_MPSC is not set +# CONFIG_MCORE2 is not set +# CONFIG_MATOM is not set +CONFIG_GENERIC_CPU=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_TSC=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_CMOV=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_HPET_TIMER=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_DMI=y +CONFIG_GART_IOMMU=y +CONFIG_CALGARY_IOMMU=y +CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y +# CONFIG_MAXSMP is not set +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=256 +CONFIG_SCHED_SMT=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_IO_APIC=y +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_AMD=y +CONFIG_X86_MCE_THRESHOLD=y +# CONFIG_X86_MCE_INJECT is not set +CONFIG_X86_THERMAL_VECTOR=y + +# +# Performance monitoring +# +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +CONFIG_PERF_EVENTS_INTEL_RAPL=y +CONFIG_PERF_EVENTS_INTEL_CSTATE=y +# CONFIG_PERF_EVENTS_AMD_POWER is not set +# end of Performance monitoring + +CONFIG_X86_16BIT=y +CONFIG_X86_ESPFIX64=y +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_I8K=m +CONFIG_MICROCODE=y +CONFIG_MICROCODE_INTEL=y +CONFIG_MICROCODE_AMD=y +CONFIG_MICROCODE_OLD_INTERFACE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +# CONFIG_X86_5LEVEL is not set +CONFIG_X86_DIRECT_GBPAGES=y +# CONFIG_X86_CPA_STATISTICS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +# CONFIG_AMD_MEM_ENCRYPT is not set +CONFIG_NUMA=y +CONFIG_AMD_NUMA=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_NODES_SPAN_OTHER_NODES=y +# CONFIG_NUMA_EMU is not set +CONFIG_NODES_SHIFT=6 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_X86_PMEM_LEGACY is not set +CONFIG_X86_CHECK_BIOS_CORRUPTION=y +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y +CONFIG_X86_RESERVE_LOW=64 +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_X86_PAT=y +CONFIG_ARCH_USES_PG_UNCACHED=y +CONFIG_ARCH_RANDOM=y +CONFIG_X86_SMAP=y +CONFIG_X86_INTEL_UMIP=y +# CONFIG_X86_INTEL_MPX is not set +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +CONFIG_EFI=y +CONFIG_EFI_STUB=y +CONFIG_EFI_MIXED=y +CONFIG_SECCOMP=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_ARCH_HAS_KEXEC_PURGATORY=y +CONFIG_KEXEC_VERIFY_SIG=y +CONFIG_CRASH_DUMP=y +CONFIG_KEXEC_JUMP=y +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_RELOCATABLE=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_X86_NEED_RELOCS=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_DYNAMIC_MEMORY_LAYOUT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +# CONFIG_COMPAT_VDSO is not set +CONFIG_LEGACY_VSYSCALL_EMULATE=y +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +# CONFIG_LEGACY_VSYSCALL_NONE is not set +# CONFIG_CMDLINE_BOOL is not set +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_HAVE_LIVEPATCH=y +# CONFIG_LIVEPATCH is not set +# end of Processor type and features + +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y + +# +# Power management and ACPI options +# +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +CONFIG_PM_CLK=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_SLEEP=y +# CONFIG_ACPI_PROCFS_POWER is not set +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_FAN=y +# CONFIG_ACPI_TAD is not set +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_NUMA=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=y +# CONFIG_ACPI_CUSTOM_METHOD is not set +CONFIG_ACPI_BGRT=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_NFIT is not set +# CONFIG_ACPI_HMAT is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +# CONFIG_ACPI_APEI_ERST_DEBUG is not set +# CONFIG_DPTF_POWER is not set +# CONFIG_PMIC_OPREGION is not set +# CONFIG_ACPI_CONFIGFS is not set +CONFIG_X86_PM_TIMER=y +CONFIG_SFI=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_PCC_CPUFREQ is not set +CONFIG_X86_ACPI_CPUFREQ=y +# CONFIG_X86_ACPI_CPUFREQ_CPB is not set +# CONFIG_X86_POWERNOW_K8 is not set +# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set +# CONFIG_X86_SPEEDSTEP_CENTRINO is not set +# CONFIG_X86_P4_CLOCKMOD is not set + +# +# shared options +# +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# end of CPU Idle + +# CONFIG_INTEL_IDLE is not set +# end of Power management and ACPI options + +# +# Bus options (PCI etc.) +# +CONFIG_PCI_DIRECT=y +CONFIG_PCI_MMCONFIG=y +CONFIG_MMCONF_FAM10H=y +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +CONFIG_AMD_NB=y +# CONFIG_X86_SYSFB is not set +# end of Bus options (PCI etc.) + +# +# Binary Emulations +# +CONFIG_IA32_EMULATION=y +# CONFIG_X86_X32 is not set +CONFIG_COMPAT_32=y +CONFIG_COMPAT=y +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_SYSVIPC_COMPAT=y +# end of Binary Emulations + +# +# Firmware Drivers +# +# CONFIG_EDD is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_RUNTIME_MAP=y +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_APPLE_PROPERTIES is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_EFI_EARLYCON=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_HAVE_KVM=y +CONFIG_VIRTUALIZATION=y +# CONFIG_KVM is not set +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_HOTPLUG_SMT=y +CONFIG_OPROFILE=m +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_OPROFILE_NMI_TIMER=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_OPTPROBES=y +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_64BIT_TIME=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_REFCOUNT=y +# CONFIG_REFCOUNT_FULL is not set +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_PLUGIN_HOSTCC="" +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_SHA1 is not set +# CONFIG_MODULE_SIG_SHA224 is not set +# CONFIG_MODULE_SIG_SHA256 is not set +# CONFIG_MODULE_SIG_SHA384 is not set +CONFIG_MODULE_SIG_SHA512=y +CONFIG_MODULE_SIG_HASH="sha512" +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_CMDLINE_PARSER=y +# CONFIG_BLK_WBT is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=y +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_SPARSE=y +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_MEMORY_FAILURE=y +CONFIG_HWPOISON_INJECT=m +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_THP_SWAP=y +CONFIG_TRANSPARENT_HUGE_PAGECACHE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_ZSWAP=y +CONFIG_ZPOOL=y +CONFIG_ZBUD=y +# CONFIG_Z3FOLD is not set +CONFIG_ZSMALLOC=y +CONFIG_PGTABLE_MAPPING=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ZONE_DEVICE=y +CONFIG_HMM_MIRROR=y +# CONFIG_DEVICE_PRIVATE is not set +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_HAS_PKEYS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=y +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_NV is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_CDG is not set +# CONFIG_TCP_CONG_BBR is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_NAT=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_SET=m +# CONFIG_NF_TABLES_INET is not set +CONFIG_NF_TABLES_NETDEV=y +# CONFIG_NFT_NUMGEN is not set +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +# CONFIG_NFT_OBJREF is not set +# CONFIG_NFT_QUEUE is not set +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +# CONFIG_NFT_COMPAT is not set +# CONFIG_NFT_HASH is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_XFRM=m +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NFT_DUP_NETDEV is not set +# CONFIG_NFT_FWD_NETDEV is not set +# CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NF_SOCKET_IPV4 is not set +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_SOCKET_IPV6 is not set +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=m +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_NF_TABLES_BRIDGE is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +# CONFIG_NET_EMATCH_U32 is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_CLS_ACT=y +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_NET_ACT_CTINFO is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_ACT_CT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +# CONFIG_AX25 is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_EISA=y +# CONFIG_EISA is not set +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEBUG=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +# CONFIG_PCIE_BW is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_ATS=y +CONFIG_PCI_LOCKLESS_CONFIG=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_LABEL=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set + +# +# PCI controller drivers +# + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support + +# CONFIG_VMD is not set + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +CONFIG_RAPIDIO=y +# CONFIG_RAPIDIO_TSI721 is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +# CONFIG_RAPIDIO_ENUM_BASIC is not set +# CONFIG_RAPIDIO_CHMAN is not set +# CONFIG_RAPIDIO_MPORT_CDEV is not set + +# +# RapidIO Switch drivers +# +# CONFIG_RAPIDIO_TSI57X is not set +# CONFIG_RAPIDIO_CPS_XX is not set +# CONFIG_RAPIDIO_TSI568 is not set +# CONFIG_RAPIDIO_CPS_GEN2 is not set +# CONFIG_RAPIDIO_RXS_GEN3 is not set +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +# end of Generic Driver Options + +# +# Bus devices +# +# end of Bus devices + +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_PARPORT=y +CONFIG_PARPORT_PC=y +CONFIG_PARPORT_SERIAL=y +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_1284 is not set +CONFIG_PNP=y +CONFIG_PNP_DEBUG_MESSAGES=y + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_FD is not set +CONFIG_CDROM=y +# CONFIG_PARIDE is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_ZRAM is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_IBM_ASM is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_VMWARE_VMCI is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# +# CONFIG_INTEL_MIC_BUS is not set + +# +# SCIF Bus Driver +# +# CONFIG_SCIF_BUS is not set + +# +# VOP Bus Driver +# +# CONFIG_VOP_BUS is not set + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# end of Intel MIC & related support + +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# end of Misc devices + +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=y +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_ACPI=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_SIL24=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +CONFIG_SATA_SX4=y +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=y +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PROMISE=y +CONFIG_SATA_SIL=y +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +CONFIG_PATA_AMD=y +# CONFIG_PATA_ARTOP is not set +CONFIG_PATA_ATIIXP=y +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +CONFIG_PATA_OLDPIIX=y +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +CONFIG_PATA_SCH=y +CONFIG_PATA_SERVERWORKS=y +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_PATA_ACPI is not set +CONFIG_ATA_GENERIC=y +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID10 is not set +# CONFIG_MD_RAID456 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_UNSTRIPED is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +CONFIG_DM_MIRROR=y +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_RAID is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_FUSION=y +CONFIG_FUSION_SPI=y +# CONFIG_FUSION_SAS is not set +CONFIG_FUSION_MAX_SGE=128 +# CONFIG_FUSION_CTL is not set +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=y +# CONFIG_MACVTAP is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +CONFIG_NETCONSOLE=y +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_RIONET is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=y +CONFIG_NET_VENDOR_3COM=y +# CONFIG_VORTEX is not set +# CONFIG_TYPHOON is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_ET131X is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +# CONFIG_PCNET32 is not set +# CONFIG_AMD_XGBE is not set +CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_AQTION is not set +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +# CONFIG_ATL2 is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +CONFIG_ALX=y +# CONFIG_NET_VENDOR_AURORA is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCMGENET is not set +CONFIG_BNX2=y +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +CONFIG_TIGON3_HWMON=y +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_BNXT is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_CAVIUM=y +# CONFIG_THUNDER_NIC_PF is not set +# CONFIG_THUNDER_NIC_VF is not set +# CONFIG_THUNDER_NIC_BGX is not set +# CONFIG_THUNDER_NIC_RGX is not set +CONFIG_CAVIUM_PTP=y +# CONFIG_LIQUIDIO is not set +# CONFIG_LIQUIDIO_VF is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_CX_ECAT is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +# CONFIG_DE2104X is not set +# CONFIG_TULIP is not set +# CONFIG_DE4X5 is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_DM9102 is not set +# CONFIG_ULI526X is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +CONFIG_NET_VENDOR_HP=y +# CONFIG_HP100 is not set +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_HINIC is not set +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_E1000E_HWTS=y +CONFIG_IGB=y +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=y +CONFIG_IXGB=y +CONFIG_IXGBE=y +CONFIG_IXGBE_HWMON=y +# CONFIG_IXGBEVF is not set +CONFIG_I40E=y +# CONFIG_I40EVF is not set +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +# CONFIG_IGC is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_MVMDIO is not set +# CONFIG_SKGE is not set +CONFIG_SKY2=y +# CONFIG_SKY2_DEBUG is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_LAN743X is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NATSEMI is not set +# CONFIG_NS83820 is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_8390=y +# CONFIG_NE2K_PCI is not set +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=y +CONFIG_NET_VENDOR_OKI=y +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PACKET_ENGINES=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_QED is not set +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCOM_EMAC is not set +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_ATP is not set +CONFIG_8139CP=y +CONFIG_8139TOO=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +# CONFIG_SXGBE_ETH is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_EPIC100 is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=y +CONFIG_WIZNET_W5300=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +CONFIG_FDDI=y +# CONFIG_DEFXX is not set +# CONFIG_SKFP is not set +# CONFIG_HIPPI is not set +# CONFIG_NET_SB1000 is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLIB=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=y +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=m +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_RTL8152=m +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=m +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=m +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_ARMLINUX is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K_PCI is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_PRISM54 is not set +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLAN_VENDOR_QUANTENNA=y + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_FUJITSU_ES is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +# CONFIG_MOUSE_PS2_VMMOUSE is not set +CONFIG_MOUSE_PS2_SMBUS=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_NOZOMI is not set +# CONFIG_ISI is not set +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_NULL_TTY is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_LPSS=y +# CONFIG_SERIAL_8250_MID is not set +# CONFIG_SERIAL_8250_MOXA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# end of Serial drivers + +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_PRINTER is not set +# CONFIG_PPDEV is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_APPLICOM is not set +# CONFIG_MWAVE is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HPET is not set +# CONFIG_HANGCHECK_TIMER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set +CONFIG_DEVPORT=y +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_CPU is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_I801=y +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +CONFIG_I2C_PIIX4=m +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +# CONFIG_I2C_SCMI is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_MLXCPLD is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_KVM=y +# end of PTP clock support + +CONFIG_PINCTRL=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_BAYTRAIL is not set +# CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_BROXTON is not set +# CONFIG_PINCTRL_CANNONLAKE is not set +# CONFIG_PINCTRL_CEDARFORK is not set +# CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_GEMINILAKE is not set +# CONFIG_PINCTRL_ICELAKE is not set +# CONFIG_PINCTRL_LEWISBURG is not set +# CONFIG_PINCTRL_SUNRISEPOINT is not set +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_K8TEMP is not set +CONFIG_SENSORS_K10TEMP=m +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +CONFIG_SENSORS_DELL_SMM=m +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_XGENE is not set + +# +# ACPI drivers +# +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_ATK0110 is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_EMULATION is not set + +# +# Intel thermal drivers +# +# CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_PKG_TEMP_THERMAL=m +# CONFIG_INTEL_SOC_DTS_THERMAL is not set + +# +# ACPI INT340X thermal drivers +# +# CONFIG_INT340X_THERMAL is not set +# end of ACPI INT340X thermal drivers + +# CONFIG_INTEL_PCH_THERMAL is not set +# end of Intel thermal drivers + +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Pretimeout Governors +# + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDAT_WDT is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_ALIM1535_WDT is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_EBC_C384_WDT is not set +# CONFIG_F71808E_WDT is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_IBMASR is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_IE6XX_WDT is not set +# CONFIG_ITCO_WDT is not set +# CONFIG_IT8712F_WDT is not set +# CONFIG_IT87_WDT is not set +# CONFIG_HP_WATCHDOG is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_NV_TCO is not set +# CONFIG_60XX_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_SMSC_SCH311X_WDT is not set +# CONFIG_SMSC37B787_WDT is not set +# CONFIG_TQMX86_WDT is not set +# CONFIG_VIA_WDT is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +# CONFIG_NI903X_WDT is not set +# CONFIG_NIC7018_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_LPSS_ACPI is not set +# CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +# CONFIG_LIRC is not set +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +# CONFIG_IR_IMON_DECODER is not set +# CONFIG_IR_RCMM_DECODER is not set +# CONFIG_RC_DEVICES is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_AGP=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +# CONFIG_AGP_SIS is not set +# CONFIG_AGP_VIA is not set +CONFIG_INTEL_GTT=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_VGA_SWITCHEROO is not set +CONFIG_DRM=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set + +# +# ACP (Audio CoProcessor) Configuration +# +# CONFIG_DRM_AMD_ACP is not set +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN1_0=y +CONFIG_DRM_AMD_DC_DCN2_0=y +# CONFIG_DRM_AMD_DC_DCN2_1 is not set +CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +# CONFIG_DRM_AMD_DC_HDCP is not set +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_HSA_AMD=y +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_I915 is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_GMA500 is not set +# CONFIG_DRM_UDL is not set +CONFIG_DRM_AST=m +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VESA is not set +# CONFIG_FB_EFI is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_INTEL is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_APPLE is not set +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_SAHARA is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +CONFIG_HID_KYE=y +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +CONFIG_HID_PLANTRONICS=y +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support + +# +# Intel ISH HID support +# +# CONFIG_INTEL_ISH_HID is not set +# end of Intel ISH HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_APU is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_CLEVO_MAIL is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_MLXCPLD is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_NIC78BX is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BD70528 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_FTRTC010 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ACPI=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IOATDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +CONFIG_DW_DMAC_CORE=y +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=y +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_PANEL is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_HYPERV is not set +# end of Microsoft Hyper-V guest support + +# CONFIG_STAGING is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +CONFIG_PMC_ATOM=y +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# end of Common Clock Framework + +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_AMD_IOMMU=y +CONFIG_AMD_IOMMU_V2=m +# CONFIG_INTEL_IOMMU is not set +# CONFIG_IRQ_REMAP is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# IXP4xx SoC drivers +# +# CONFIG_IXP4XX_QMGR is not set +# CONFIG_IXP4XX_NPE is not set +# end of IXP4xx SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_RAS_CEC is not set +# CONFIG_THUNDERBOLT is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +CONFIG_DAX=y +# CONFIG_DEV_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_UNISYS_VISORBUS is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_ONLINE_SCRUB is not set +CONFIG_XFS_WARN=y +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_QUOTACTL_COMPAT=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_FSCACHE=y +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +# CONFIG_CACHEFILES is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# end of DOS/FAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +# CONFIG_EFIVAR_FS is not set +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_RAM is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +# CONFIG_CIFS_DFS_UPCALL is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_COMPAT=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITY_WRITABLE_HOOKS=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_PAGE_TABLE_ISOLATION=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set +# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set +# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS640_SSE2 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +# CONFIG_CRYPTO_MORUS1280_SSE2 is not set +# CONFIG_CRYPTO_MORUS1280_AVX2 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set +# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set +# CONFIG_CRYPTO_ADIANTUM is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32_PCLMUL is not set +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_CRCT10DIF=y +# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_POLY1305_X86_64 is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA1_SSSE3 is not set +# CONFIG_CRYPTO_SHA256_SSSE3 is not set +# CONFIG_CRYPTO_SHA512_SSSE3 is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_AES_X86_64 is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20_X86_64 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set +# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set +# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_X86_64 is not set +# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set +# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_PADLOCK is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +# CONFIG_CORDIC is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_CMA is not set +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_IOMMU_HELPER=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_UACCESS_MCSAFE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_STACK_VALIDATION=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_RODATA_TEST=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_KASAN is not set +CONFIG_KASAN_STACK=1 +# end of Memory Debugging + +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# end of Debug Lockups and Hangs + +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_PROVE_LOCKING=y +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +CONFIG_DEBUG_RWSEMS=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_LOCKDEP=y +# CONFIG_DEBUG_LOCKDEP is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_TRACE_IRQFLAGS=y +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_PROVE_RCU=y +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +# CONFIG_PREEMPTIRQ_EVENTS is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +CONFIG_STACK_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FUNCTION_PROFILER=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_MMIOTRACE=y +CONFIG_TRACING_MAP=y +CONFIG_HIST_TRIGGERS=y +# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK_DBGP is not set +# CONFIG_EARLY_PRINTK_USB_XDBC is not set +# CONFIG_X86_PTDUMP is not set +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DOUBLEFAULT=y +# CONFIG_DEBUG_TLBFLUSH is not set +# CONFIG_IOMMU_DEBUG is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +# CONFIG_X86_DECODER_SELFTEST is not set +# CONFIG_IO_DELAY_0X80 is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_NMI_SELFTEST is not set +CONFIG_X86_DEBUG_FPU=y +# CONFIG_PUNIT_ATOM_DEBUG is not set +CONFIG_UNWINDER_ORC=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_UNWINDER_GUESS is not set +# end of Kernel hacking From 0ac87d9530d1e35db73d181d53a568ed1e5c4b08 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 30 Mar 2021 18:43:07 -0400 Subject: [PATCH 0044/2070] rock-dbg_defconfig: update to 5.11 and enable DEVICE_PRIVATE Update rock-dbg_defconfig for the 5.11 kernel. Enable CONFIG_DEVICE_PRIVATE, which is needed by the new HMM-based SVM memory manager. Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 711 +++++++++++++++++----------- 1 file changed, 443 insertions(+), 268 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 5e1de51be9553..55fa96bf27502 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,19 +1,19 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.3.0-rc3 Kernel Configuration -# - -# -# Compiler: gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# Linux/x86 5.11.0 Kernel Configuration # +CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70400 +CONFIG_GCC_VERSION=70500 +CONFIG_LD_VERSION=230000000 CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # @@ -21,7 +21,6 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="-kfd" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -31,18 +30,22 @@ CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y CONFIG_AUDIT=y @@ -57,10 +60,12 @@ CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y @@ -69,7 +74,6 @@ CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y @@ -77,6 +81,8 @@ CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y # # Timers subsystem @@ -119,6 +125,9 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -134,10 +143,12 @@ CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # +# CONFIG_UCLAMP_TASK is not set # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -145,7 +156,6 @@ CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y -# CONFIG_MEMCG_SWAP_ENABLED is not set CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y @@ -167,6 +177,7 @@ CONFIG_CGROUP_BPF=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y +CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y @@ -183,8 +194,11 @@ CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y @@ -195,7 +209,6 @@ CONFIG_UID16=y CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSCTL_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -220,8 +233,11 @@ CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set @@ -257,7 +273,6 @@ CONFIG_X86_64=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y @@ -281,7 +296,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y @@ -312,10 +326,11 @@ CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y # CONFIG_PARAVIRT_DEBUG is not set CONFIG_PARAVIRT_SPINLOCKS=y +CONFIG_X86_HV_CALLBACK_VECTOR=y # CONFIG_XEN is not set CONFIG_KVM_GUEST=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y # CONFIG_PVH is not set -CONFIG_KVM_DEBUG_FS=y # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_PARAVIRT_CLOCK=y # CONFIG_JAILHOUSE_GUEST is not set @@ -332,6 +347,8 @@ CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=64 CONFIG_X86_DEBUGCTLMSR=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y @@ -342,8 +359,6 @@ CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y CONFIG_GART_IOMMU=y -CONFIG_CALGARY_IOMMU=y -CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y # CONFIG_MAXSMP is not set CONFIG_NR_CPUS_RANGE_BEGIN=2 CONFIG_NR_CPUS_RANGE_END=512 @@ -375,6 +390,7 @@ CONFIG_PERF_EVENTS_INTEL_CSTATE=y CONFIG_X86_16BIT=y CONFIG_X86_ESPFIX64=y CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_IOPL_IOPERM=y CONFIG_I8K=m CONFIG_MICROCODE=y CONFIG_MICROCODE_INTEL=y @@ -385,12 +401,10 @@ CONFIG_X86_CPUID=m # CONFIG_X86_5LEVEL is not set CONFIG_X86_DIRECT_GBPAGES=y # CONFIG_X86_CPA_STATISTICS is not set -CONFIG_ARCH_HAS_MEM_ENCRYPT=y # CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_NUMA=y CONFIG_AMD_NUMA=y CONFIG_X86_64_ACPI_NUMA=y -CONFIG_NODES_SPAN_OTHER_NODES=y # CONFIG_NUMA_EMU is not set CONFIG_NODES_SHIFT=6 CONFIG_ARCH_SPARSEMEM_ENABLE=y @@ -411,13 +425,15 @@ CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_ARCH_RANDOM=y CONFIG_X86_SMAP=y -CONFIG_X86_INTEL_UMIP=y -# CONFIG_X86_INTEL_MPX is not set +CONFIG_X86_UMIP=y CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y -CONFIG_SECCOMP=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set @@ -427,7 +443,7 @@ CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y CONFIG_ARCH_HAS_KEXEC_PURGATORY=y -CONFIG_KEXEC_VERIFY_SIG=y +# CONFIG_KEXEC_SIG is not set CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y CONFIG_PHYSICAL_START=0x1000000 @@ -468,6 +484,7 @@ CONFIG_SUSPEND_FREEZER=y # CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -495,7 +512,6 @@ CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y -# CONFIG_ACPI_PROCFS_POWER is not set CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_AC=y @@ -513,7 +529,6 @@ CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_NUMA=y CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TABLE_UPGRADE=y # CONFIG_ACPI_DEBUG is not set @@ -536,9 +551,9 @@ CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=m # CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_DPTF_POWER is not set -# CONFIG_PMIC_OPREGION is not set +# CONFIG_ACPI_DPTF is not set # CONFIG_ACPI_CONFIGFS is not set +# CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y CONFIG_SFI=y @@ -552,15 +567,13 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers @@ -586,6 +599,8 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +CONFIG_HALTPOLL_CPUIDLE=y # end of CPU Idle # CONFIG_INTEL_IDLE is not set @@ -636,16 +651,20 @@ CONFIG_EFI_VARS_PSTORE=y CONFIG_EFI_RUNTIME_MAP=y # CONFIG_EFI_FAKE_MEMMAP is not set CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y # CONFIG_EFI_BOOTLOADER_CONTROL is not set # CONFIG_EFI_CAPSULE_LOADER is not set # CONFIG_EFI_TEST is not set # CONFIG_APPLE_PROPERTIES is not set # CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_X86=y CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y # # Tegra firmware driver @@ -656,8 +675,9 @@ CONFIG_EFI_EARLYCON=y CONFIG_HAVE_KVM=y CONFIG_VIRTUALIZATION=y # CONFIG_KVM is not set -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_AS_AVX512=y +CONFIG_AS_SHA1_NI=y +CONFIG_AS_SHA256_NI=y # # General architecture-dependent options @@ -665,6 +685,7 @@ CONFIG_VIRTUALIZATION=y CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y +CONFIG_GENERIC_ENTRY=y CONFIG_OPROFILE=m # CONFIG_OPROFILE_EVENT_MULTIPLEX is not set CONFIG_HAVE_OPROFILE=y @@ -672,6 +693,7 @@ CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_CALL_SELFTEST is not set CONFIG_OPTPROBES=y CONFIG_KPROBES_ON_FTRACE=y CONFIG_UPROBES=y @@ -693,10 +715,10 @@ CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_CLK=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y @@ -706,24 +728,29 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y @@ -732,7 +759,6 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -740,12 +766,10 @@ CONFIG_ARCH_MMAP_RND_BITS=28 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y -CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_STACK_VALIDATION=y CONFIG_HAVE_RELIABLE_STACKTRACE=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y @@ -753,11 +777,14 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_REFCOUNT=y -# CONFIG_REFCOUNT_FULL is not set CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -766,17 +793,18 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling -CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 +CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y # CONFIG_MODULE_SIG_FORCE is not set @@ -788,21 +816,27 @@ CONFIG_MODULE_SIG_ALL=y CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set CONFIG_BLK_CMDLINE_PARSER=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types @@ -851,6 +885,7 @@ CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y @@ -874,12 +909,11 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_HAVE_FAST_GUP=y +CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y CONFIG_MEMORY_HOTPLUG=y @@ -888,6 +922,7 @@ CONFIG_MEMORY_HOTPLUG_SPARSE=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y @@ -904,7 +939,6 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_THP_SWAP=y -CONFIG_TRANSPARENT_HUGE_PAGECACHE=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y @@ -913,23 +947,36 @@ CONFIG_CMA=y CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +# CONFIG_ZSWAP_DEFAULT_ON is not set CONFIG_ZPOOL=y CONFIG_ZBUD=y # CONFIG_Z3FOLD is not set CONFIG_ZSMALLOC=y -CONFIG_PGTABLE_MAPPING=y # CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y +CONFIG_DEV_PAGEMAP_OPS=y CONFIG_HMM_MIRROR=y -# CONFIG_DEVICE_PRIVATE is not set +CONFIG_DEVICE_PRIVATE=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y CONFIG_ARCH_HAS_PKEYS=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -949,10 +996,13 @@ CONFIG_UNIX_DIAG=y CONFIG_XFRM=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y +# CONFIG_XFRM_USER_COMPAT is not set # CONFIG_XFRM_INTERFACE is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=y +CONFIG_XFRM_ESP=y # CONFIG_NET_KEY is not set # CONFIG_XDP_SOCKETS is not set CONFIG_INET=y @@ -1015,6 +1065,7 @@ CONFIG_IPV6=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y # CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set @@ -1027,7 +1078,9 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y +# CONFIG_MPTCP is not set CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1078,7 +1131,6 @@ CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_SET=m # CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y # CONFIG_NFT_NUMGEN is not set @@ -1107,6 +1159,7 @@ CONFIG_NF_DUP_NETDEV=m # CONFIG_NFT_DUP_NETDEV is not set # CONFIG_NFT_FWD_NETDEV is not set # CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NFT_REJECT_NETDEV is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m @@ -1288,6 +1341,8 @@ CONFIG_STP=y CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y @@ -1336,6 +1391,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_PIE is not set # CONFIG_NET_SCH_INGRESS is not set # CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # @@ -1381,7 +1437,8 @@ CONFIG_NET_CLS_ACT=y # CONFIG_NET_ACT_SKBMOD is not set # CONFIG_NET_ACT_IFE is not set # CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_TC_SKB_EXT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -1394,6 +1451,7 @@ CONFIG_NETLINK_DIAG=y # CONFIG_HSR is not set # CONFIG_NET_SWITCHDEV is not set # CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -1432,7 +1490,6 @@ CONFIG_WIRELESS=y # CFG80211 needs to be enabled for MAC80211 # CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1446,6 +1503,7 @@ CONFIG_RFKILL_INPUT=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y # CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # @@ -1462,7 +1520,6 @@ CONFIG_PCIEAER=y # CONFIG_PCIEAER_INJECT is not set # CONFIG_PCIE_ECRC is not set CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEBUG=y CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set @@ -1485,6 +1542,11 @@ CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y # CONFIG_PCI_P2PDMA is not set CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_ACPI is not set # CONFIG_HOTPLUG_PCI_CPCI is not set @@ -1493,12 +1555,6 @@ CONFIG_HOTPLUG_PCI=y # # PCI controller drivers # - -# -# Cadence PCIe controllers support -# -# end of Cadence PCIe controllers support - # CONFIG_VMD is not set # @@ -1507,6 +1563,16 @@ CONFIG_HOTPLUG_PCI=y # CONFIG_PCIE_DW_PLAT_HOST is not set # CONFIG_PCI_MESON is not set # end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support # end of PCI controller drivers # @@ -1559,6 +1625,7 @@ CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y # end of Firmware loader CONFIG_ALLOW_DEV_COREDUMP=y @@ -1568,8 +1635,6 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set # end of Generic Driver Options @@ -1577,6 +1642,7 @@ CONFIG_DMA_SHARED_BUFFER=y # # Bus devices # +# CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set @@ -1627,6 +1693,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y # CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_HWMON is not set # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set @@ -1639,7 +1706,6 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_DUMMY_IRQ is not set # CONFIG_IBM_ASM is not set # CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1682,53 +1748,13 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_INTEL_MEI_ME is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_VMWARE_VMCI is not set - -# -# Intel MIC & related support -# - -# -# Intel MIC Bus Driver -# -# CONFIG_INTEL_MIC_BUS is not set - -# -# SCIF Bus Driver -# -# CONFIG_SCIF_BUS is not set - -# -# VOP Bus Driver -# -# CONFIG_VOP_BUS is not set - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# -# end of Intel MIC & related support - # CONFIG_GENWQE is not set # CONFIG_ECHO is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set # end of Misc devices CONFIG_HAVE_IDE=y @@ -1749,7 +1775,6 @@ CONFIG_SCSI_PROC_FS=y CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y @@ -1772,7 +1797,10 @@ CONFIG_SCSI_ISCSI_ATTRS=y # end of SCSI device support CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y # CONFIG_SATA_ZPODD is not set CONFIG_SATA_PMP=y @@ -1884,7 +1912,9 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_THIN_PROVISIONING is not set # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set CONFIG_DM_MIRROR=y # CONFIG_DM_LOG_USERSPACE is not set # CONFIG_DM_RAID is not set @@ -1920,6 +1950,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_IFB is not set @@ -1929,6 +1960,7 @@ CONFIG_MACVLAN=y # CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set # CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1942,10 +1974,6 @@ CONFIG_VETH=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # @@ -2029,8 +2057,6 @@ CONFIG_NET_VENDOR_EMULEX=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_GVE is not set -CONFIG_NET_VENDOR_HP=y -# CONFIG_HP100 is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_HINIC is not set CONFIG_NET_VENDOR_I825XX=y @@ -2091,10 +2117,11 @@ CONFIG_NET_VENDOR_OKI=y CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set CONFIG_NET_VENDOR_QLOGIC=y # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_QED is not set CONFIG_NET_VENDOR_QUALCOMM=y @@ -2160,37 +2187,29 @@ CONFIG_FDDI=y # CONFIG_SKFP is not set # CONFIG_HIPPI is not set # CONFIG_NET_SB1000 is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_THUNDER is not set CONFIG_PHYLIB=y # CONFIG_LED_TRIGGER_PHY is not set +# CONFIG_FIXED_PHY is not set # # MII PHY device drivers # CONFIG_AMD_PHY=y +# CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -# CONFIG_AT803X_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set # CONFIG_BCM87XX_PHY is not set -# CONFIG_BROADCOM_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_FIXED_PHY is not set # CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MICREL_PHY is not set @@ -2206,8 +2225,32 @@ CONFIG_REALTEK_PHY=y # CONFIG_SMSC_PHY is not set # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + # CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -2255,8 +2298,8 @@ CONFIG_USB_BELKIN=y # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_WLAN_VENDOR_ATH=y # CONFIG_ATH_DEBUG is not set @@ -2270,6 +2313,7 @@ CONFIG_WLAN_VENDOR_INTERSIL=y # CONFIG_PRISM54 is not set CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WLAN_VENDOR_RALINK=y CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_WLAN_VENDOR_RSI=y @@ -2277,10 +2321,6 @@ CONFIG_WLAN_VENDOR_ST=y CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLAN_VENDOR_QUANTENNA=y - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set @@ -2295,7 +2335,6 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y CONFIG_INPUT_SPARSEKMAP=y # CONFIG_INPUT_MATRIXKMAP is not set @@ -2398,23 +2437,7 @@ CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINK is not set -# CONFIG_SYNCLINKMP is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_NOZOMI is not set -# CONFIG_ISI is not set -# CONFIG_N_HDLC is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -# CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y -CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # # Serial drivers @@ -2423,6 +2446,7 @@ CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2435,11 +2459,11 @@ CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DWLIB=y # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_8250_LPSS=y # CONFIG_SERIAL_8250_MID is not set -# CONFIG_SERIAL_8250_MOXA is not set # # Non-8250 serial port support @@ -2450,34 +2474,54 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_SPRD is not set # end of Serial drivers +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_ISI is not set +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set # CONFIG_PPDEV is not set +# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set +# CONFIG_NVRAM is not set # CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y # CONFIG_HPET is not set # CONFIG_HANGCHECK_TIMER is not set # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set -CONFIG_DEVPORT=y # CONFIG_XILLYBUS is not set # end of Character devices # CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # # I2C support @@ -2538,7 +2582,6 @@ CONFIG_I2C_PIIX4=m # # CONFIG_I2C_DIOLAN_U2C is not set # CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2584,6 +2627,10 @@ CONFIG_PTP_1588_CLOCK=y # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # CONFIG_PTP_1588_CLOCK_KVM=y +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_VMW is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2593,17 +2640,29 @@ CONFIG_PINCTRL=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_BAYTRAIL is not set # CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_LYNXPOINT is not set +# CONFIG_PINCTRL_ALDERLAKE is not set # CONFIG_PINCTRL_BROXTON is not set # CONFIG_PINCTRL_CANNONLAKE is not set # CONFIG_PINCTRL_CEDARFORK is not set # CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_ELKHARTLAKE is not set +# CONFIG_PINCTRL_EMMITSBURG is not set # CONFIG_PINCTRL_GEMINILAKE is not set # CONFIG_PINCTRL_ICELAKE is not set +# CONFIG_PINCTRL_JASPERLAKE is not set +# CONFIG_PINCTRL_LAKEFIELD is not set # CONFIG_PINCTRL_LEWISBURG is not set # CONFIG_PINCTRL_SUNRISEPOINT is not set +# CONFIG_PINCTRL_TIGERLAKE is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set @@ -2611,6 +2670,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set @@ -2624,6 +2684,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2639,20 +2700,27 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7410 is not set # CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m # CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_AMD_ENERGY is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set CONFIG_SENSORS_DELL_SMM=m @@ -2674,6 +2742,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2681,10 +2750,12 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set @@ -2693,6 +2764,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set @@ -2718,6 +2790,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set # CONFIG_SENSORS_SHTC1 is not set @@ -2734,7 +2807,6 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set @@ -2747,6 +2819,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VIA_CPUTEMP is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set @@ -2769,6 +2842,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_ACPI_POWER is not set # CONFIG_SENSORS_ATK0110 is not set CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y @@ -2776,12 +2850,10 @@ CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set CONFIG_THERMAL_GOV_USER_SPACE=y -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_EMULATION is not set # @@ -2879,7 +2951,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_I2C is not set @@ -2889,12 +2960,15 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set # CONFIG_MFD_INTEL_LPSS_ACPI is not set # CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -2907,6 +2981,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_MFD_VIPERBOARD is not set @@ -2919,7 +2994,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -2965,6 +3039,7 @@ CONFIG_IR_XMP_DECODER=y # CONFIG_IR_IMON_DECODER is not set # CONFIG_IR_RCMM_DECODER is not set # CONFIG_RC_DEVICES is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set # CONFIG_MEDIA_SUPPORT is not set # @@ -2985,6 +3060,7 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set @@ -2992,6 +3068,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_TTM=m CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m CONFIG_DRM_SCHED=m # @@ -3013,7 +3090,6 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set # # ACP (Audio CoProcessor) Configuration @@ -3025,12 +3101,11 @@ CONFIG_DRM_AMDGPU_USERPTR=y # Display Engine Configuration # CONFIG_DRM_AMD_DC=y -CONFIG_DRM_AMD_DC_DCN1_0=y -CONFIG_DRM_AMD_DC_DCN2_0=y -# CONFIG_DRM_AMD_DC_DCN2_1 is not set -CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +CONFIG_DRM_AMD_DC_DCN=y # CONFIG_DRM_AMD_DC_HDCP is not set +# CONFIG_DRM_AMD_DC_SI is not set # CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set # end of Display Engine Configuration CONFIG_HSA_AMD=y @@ -3043,9 +3118,9 @@ CONFIG_HSA_AMD=y # CONFIG_DRM_UDL is not set CONFIG_DRM_AST=m # CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y # @@ -3063,6 +3138,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_VBOXVIDEO is not set # CONFIG_DRM_LEGACY is not set @@ -3139,9 +3215,8 @@ CONFIG_FB_DEFERRED_IO=y # # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_SAHARA is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set @@ -3157,9 +3232,6 @@ CONFIG_HDMI=y # Console display driver support # CONFIG_VGA_CONSOLE=y -CONFIG_VGACON_SOFT_SCROLLBACK=y -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 @@ -3202,6 +3274,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_COUGAR is not set # CONFIG_HID_MACALLY is not set # CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set @@ -3211,7 +3284,9 @@ CONFIG_HID_CYPRESS=y CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y @@ -3295,11 +3370,19 @@ CONFIG_USB_HIDDEV=y # # CONFIG_INTEL_ISH_HID is not set # end of Intel ISH HID support + +# +# AMD SFH HID Support +# +# CONFIG_AMD_SFH_HID is not set +# end of AMD SFH HID Support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y @@ -3309,14 +3392,14 @@ CONFIG_USB_PCI=y # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -3325,6 +3408,7 @@ CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DBGCAP is not set CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set # CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y @@ -3381,6 +3465,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3400,7 +3485,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -3408,6 +3492,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -3432,14 +3517,12 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_GADGET is not set # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # @@ -3451,10 +3534,6 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set # CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3472,7 +3551,10 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set # CONFIG_LEDS_NIC78BX is not set -# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# Flash and Torch LED drivers +# # # LED Triggers @@ -3539,7 +3621,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BD70528 is not set # CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -3548,6 +3629,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set # CONFIG_RTC_DRV_SD3078 is not set @@ -3562,6 +3644,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -3600,7 +3683,10 @@ CONFIG_DMA_ENGINE=y CONFIG_DMA_ACPI=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IDXD is not set # CONFIG_INTEL_IOATDMA is not set +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y @@ -3608,6 +3694,7 @@ CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC_PCI=y # CONFIG_DW_EDMA is not set # CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set # # DMA Clients @@ -3621,7 +3708,10 @@ CONFIG_DW_DMAC_PCI=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -3632,6 +3722,10 @@ CONFIG_SYNC_FILE=y CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support @@ -3639,26 +3733,26 @@ CONFIG_VIRTIO_MENU=y # CONFIG_HYPERV is not set # end of Microsoft Hyper-V guest support +# CONFIG_GREYBUS is not set # CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_PMC_ATOM=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -# end of Common Clock Framework - # CONFIG_HWSPINLOCK is not set # @@ -3683,6 +3777,7 @@ CONFIG_IOMMU_SUPPORT=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=m # CONFIG_INTEL_IOMMU is not set @@ -3712,11 +3807,6 @@ CONFIG_AMD_IOMMU_V2=m # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -3733,11 +3823,9 @@ CONFIG_AMD_IOMMU_V2=m # end of i.MX SoC drivers # -# IXP4xx SoC drivers +# Enable LiteX SoC Builder specific drivers # -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers +# end of Enable LiteX SoC Builder specific drivers # # Qualcomm SoC drivers @@ -3773,9 +3861,11 @@ CONFIG_AMD_IOMMU_V2=m # PHY Subsystem # # CONFIG_GENERIC_PHY is not set +# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -3788,7 +3878,7 @@ CONFIG_AMD_IOMMU_V2=m CONFIG_RAS=y # CONFIG_RAS_CEC is not set -# CONFIG_THUNDERBOLT is not set +# CONFIG_USB4 is not set # # Android @@ -3799,6 +3889,7 @@ CONFIG_RAS=y # CONFIG_LIBNVDIMM is not set CONFIG_DAX=y # CONFIG_DEV_DAX is not set +# CONFIG_DEV_DAX_HMEM is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y @@ -3810,11 +3901,13 @@ CONFIG_NVMEM_SYSFS=y # end of HW tracing support # CONFIG_FPGA is not set +# CONFIG_TEE is not set # CONFIG_UNISYS_VISORBUS is not set # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set +# CONFIG_MOST is not set # end of Device Drivers # @@ -3836,6 +3929,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_XFS_FS=y +CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y @@ -3854,6 +3948,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -3866,11 +3961,11 @@ CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y -CONFIG_QUOTACTL_COMPAT=y CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m +# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -3899,7 +3994,7 @@ CONFIG_ZISOFS=y # end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y @@ -3907,10 +4002,11 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set CONFIG_NTFS_FS=y # CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y -# end of DOS/FAT/NT Filesystems +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -3928,6 +4024,7 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -3956,6 +4053,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -3969,8 +4067,10 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_PMSG is not set # CONFIG_PSTORE_FTRACE is not set # CONFIG_PSTORE_RAM is not set +# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -3983,6 +4083,7 @@ CONFIG_ROOT_NFS=y # CONFIG_NFS_FSCACHE is not set # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -4003,7 +4104,9 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_DEBUG_DUMP_KEYS is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y +# CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -4059,16 +4162,15 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y # CONFIG_DLM is not set # CONFIG_UNICODE is not set +CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_BIG_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set @@ -4090,16 +4192,20 @@ CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 # CONFIG_SECURITY_SMACK is not set # CONFIG_SECURITY_TOMOYO is not set # CONFIG_SECURITY_APPARMOR is not set # CONFIG_SECURITY_LOADPIN is not set # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y # CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set # CONFIG_EVM is not set CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SECURITY_DAC is not set @@ -4128,8 +4234,8 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y @@ -4158,6 +4264,9 @@ CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_CURVE25519_X86 is not set # # Authenticated Encryption with Associated Data @@ -4166,16 +4275,7 @@ CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS640_SSE2 is not set -# CONFIG_CRYPTO_MORUS1280 is not set -# CONFIG_CRYPTO_MORUS1280_SSE2 is not set -# CONFIG_CRYPTO_MORUS1280_AVX2 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y @@ -4195,6 +4295,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -4212,6 +4313,9 @@ CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set # CONFIG_CRYPTO_CRC32_PCLMUL is not set # CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_BLAKE2S_X86 is not set CONFIG_CRYPTO_CRCT10DIF=y # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set CONFIG_CRYPTO_GHASH=y @@ -4242,11 +4346,7 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_AES_X86_64 is not set # CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set # CONFIG_CRYPTO_CAMELLIA is not set @@ -4260,17 +4360,14 @@ CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set # CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_TWOFISH_X86_64 is not set # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set @@ -4301,6 +4398,20 @@ CONFIG_CRYPTO_JITTERENTROPY=y # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_PADLOCK is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set @@ -4309,10 +4420,13 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set # CONFIG_CRYPTO_DEV_QAT_C3XXX is not set # CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y @@ -4344,11 +4458,13 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -4371,6 +4487,7 @@ CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y @@ -4386,6 +4503,7 @@ CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m @@ -4397,12 +4515,14 @@ CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_SWIOTLB=y # CONFIG_DMA_CMA is not set # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_IOMMU_HELPER=y CONFIG_CHECK_SIGNATURE=y @@ -4414,11 +4534,11 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y -CONFIG_DIMLIB=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -4426,7 +4546,7 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_HAS_PMEM_API=y CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_UACCESS_MCSAFE=y +CONFIG_ARCH_HAS_COPY_MC=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set @@ -4446,29 +4566,53 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set -CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_STACK_VALIDATION=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options +# +# Generic Kernel Debugging Instruments +# CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_EARLY_DEBUG=y +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +# end of Generic Kernel Debugging Instruments + CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y @@ -4481,35 +4625,43 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_RODATA_TEST=y +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 # CONFIG_DEBUG_KMEMLEAK_TEST is not set CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y # CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y -# CONFIG_KASAN is not set -CONFIG_KASAN_STACK=1 # end of Memory Debugging -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_DEBUG_SHIRQ=y # -# Debug Lockups and Hangs +# Debug Oops, Lockups and Hangs # +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set @@ -4524,15 +4676,17 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 # CONFIG_WQ_WATCHDOG is not set -# end of Debug Lockups and Hangs +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 +# +# Scheduler Debugging +# CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y +# end of Scheduler Debugging + # CONFIG_DEBUG_TIMEKEEPING is not set # @@ -4540,6 +4694,7 @@ CONFIG_SCHED_STACK_END_CHECK=y # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y +# CONFIG_PROVE_RAW_LOCK_NESTING is not set # CONFIG_LOCK_STAT is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y @@ -4553,25 +4708,35 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y +CONFIG_TRACE_IRQFLAGS_NMI=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_PROVE_RCU=y -# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set @@ -4580,9 +4745,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y @@ -4590,6 +4752,8 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y @@ -4602,22 +4766,28 @@ CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y +CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792 CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set CONFIG_FUNCTION_TRACER=y CONFIG_FUNCTION_GRAPH_TRACER=y -# CONFIG_PREEMPTIRQ_EVENTS is not set +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y # CONFIG_IRQSOFF_TRACER is not set CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y +CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y # CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set # CONFIG_PROFILE_ALL_BRANCHES is not set -CONFIG_STACK_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KPROBE_EVENTS=y # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set @@ -4625,49 +4795,39 @@ CONFIG_UPROBE_EVENTS=y CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_FUNCTION_PROFILER=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y -# CONFIG_FTRACE_STARTUP_TEST is not set -CONFIG_MMIOTRACE=y CONFIG_TRACING_MAP=y +CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y -# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_MMIOTRACE_TEST is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_HIST_TRIGGERS_DEBUG is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_MEMTEST=y -# CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_KGDB=y -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set -CONFIG_KGDB_LOW_LEVEL_TRAP=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x1 -CONFIG_KDB_KEYBOARD=y -CONFIG_KDB_CONTINUE_CATASTROPHIC=0 -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set + +# +# x86 Debugging +# CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set CONFIG_EARLY_PRINTK=y # CONFIG_EARLY_PRINTK_DBGP is not set # CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_X86_PTDUMP is not set # CONFIG_EFI_PGT_DUMP is not set -# CONFIG_DEBUG_WX is not set -CONFIG_DOUBLEFAULT=y # CONFIG_DEBUG_TLBFLUSH is not set # CONFIG_IOMMU_DEBUG is not set CONFIG_HAVE_MMIOTRACE_SUPPORT=y @@ -4685,4 +4845,19 @@ CONFIG_X86_DEBUG_FPU=y CONFIG_UNWINDER_ORC=y # CONFIG_UNWINDER_FRAME_POINTER is not set # CONFIG_UNWINDER_GUESS is not set +# end of x86 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage # end of Kernel hacking From e3b8f7ba7bbfa3301b0bde00ba16fc8a8753601c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 14 Apr 2021 20:13:19 -0400 Subject: [PATCH 0045/2070] rock-dbg_defconfig: Enable Intel IOMMU Enable the Intel IOMMU driver in the rock-dbg_defconfig. This enables testing of DMA mappings on systems with an Intel IOMMU. Signed-off-by: Felix Kuehling Acked-by: Oak Zeng Acked-by: Ramesh Errabolu Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 55fa96bf27502..32191eaa2556f 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -296,6 +296,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y +CONFIG_HAVE_INTEL_TXT=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y @@ -3109,6 +3110,7 @@ CONFIG_DRM_AMD_DC_DCN=y # end of Display Engine Configuration CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y # CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_I915 is not set # CONFIG_DRM_VGEM is not set @@ -3767,6 +3769,7 @@ CONFIG_MAILBOX=y CONFIG_PCC=y # CONFIG_ALTERA_MBOX is not set CONFIG_IOMMU_IOVA=y +CONFIG_IOASID=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -3780,7 +3783,12 @@ CONFIG_IOMMU_SUPPORT=y CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=m -# CONFIG_INTEL_IOMMU is not set +CONFIG_DMAR_TABLE=y +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_SVM is not set +CONFIG_INTEL_IOMMU_DEFAULT_ON=y +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set # CONFIG_IRQ_REMAP is not set # @@ -4181,6 +4189,7 @@ CONFIG_SECURITY_NETWORK=y CONFIG_PAGE_TABLE_ISOLATION=y # CONFIG_SECURITY_NETWORK_XFRM is not set # CONFIG_SECURITY_PATH is not set +# CONFIG_INTEL_TXT is not set CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set From 6e803d152f065301766a424c6d3f5cb98a9ba056 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 7 Jul 2021 17:54:53 -0400 Subject: [PATCH 0046/2070] rock-dbg_defconfig: Update for 5.13 Also build drm as module to make debugging easier. Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 177 +++++++++++++++++----------- 1 file changed, 108 insertions(+), 69 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 32191eaa2556f..4877da183599f 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,12 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.11.0 Kernel Configuration +# Linux/x86 5.13.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=70500 -CONFIG_LD_VERSION=230000000 CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23000 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23000 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -96,6 +99,19 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -173,6 +189,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -203,7 +220,6 @@ CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -232,9 +248,6 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -253,7 +266,6 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -286,7 +298,6 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_FILTER_PGPROT=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y @@ -377,7 +388,6 @@ CONFIG_X86_MCE_INTEL=y CONFIG_X86_MCE_AMD=y CONFIG_X86_MCE_THRESHOLD=y # CONFIG_X86_MCE_INJECT is not set -CONFIG_X86_THERMAL_VECTOR=y # # Performance monitoring @@ -469,12 +479,8 @@ CONFIG_HAVE_LIVEPATCH=y # end of Processor type and features CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management and ACPI options @@ -511,6 +517,7 @@ CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y # CONFIG_ACPI_DEBUGGER is not set CONFIG_ACPI_SPCR_TABLE=y +# CONFIG_ACPI_FPDT is not set CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y @@ -543,6 +550,7 @@ CONFIG_ACPI_HED=y CONFIG_ACPI_BGRT=y # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set # CONFIG_ACPI_NFIT is not set +CONFIG_ACPI_NUMA=y # CONFIG_ACPI_HMAT is not set CONFIG_HAVE_ACPI_APEI=y CONFIG_HAVE_ACPI_APEI_NMI=y @@ -556,7 +564,6 @@ CONFIG_ACPI_APEI_EINJ=m # CONFIG_ACPI_CONFIGFS is not set # CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y -CONFIG_SFI=y # # CPU Frequency scaling @@ -687,10 +694,6 @@ CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y CONFIG_GENERIC_ENTRY=y -CONFIG_OPROFILE=m -# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -746,6 +749,9 @@ CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y @@ -760,6 +766,8 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -774,6 +782,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -784,8 +794,10 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y # # GCOV-based kernel profiling @@ -816,9 +828,12 @@ CONFIG_MODULE_SIG_ALL=y # CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -917,17 +932,22 @@ CONFIG_HAVE_FAST_GUP=y CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG_SPARSE=y # CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MHP_MEMMAP_ON_MEMORY=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_COMPACTION=y # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y @@ -945,6 +965,7 @@ CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y @@ -968,6 +989,7 @@ CONFIG_ZSMALLOC=y CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y CONFIG_DEV_PAGEMAP_OPS=y @@ -1101,8 +1123,7 @@ CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m CONFIG_NETFILTER_CONNCOUNT=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y @@ -1163,6 +1184,7 @@ CONFIG_NF_DUP_NETDEV=m # CONFIG_NFT_REJECT_NETDEV is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1344,7 +1366,6 @@ CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set # CONFIG_BRIDGE_CFM is not set -CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set @@ -1454,14 +1475,15 @@ CONFIG_NETLINK_DIAG=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1503,9 +1525,10 @@ CONFIG_RFKILL_INPUT=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y # CONFIG_FAILOVER is not set CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1528,7 +1551,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y # CONFIG_PCIE_DPC is not set # CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_BW is not set CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y @@ -1588,6 +1610,7 @@ CONFIG_HOTPLUG_PCI=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set CONFIG_RAPIDIO=y # CONFIG_RAPIDIO_TSI721 is not set @@ -1672,13 +1695,11 @@ CONFIG_CDROM=y # CONFIG_PARIDE is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_ZRAM is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SKD is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 @@ -1720,9 +1741,9 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set # @@ -1751,11 +1772,13 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_VMWARE_VMCI is not set # CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices CONFIG_HAVE_IDE=y @@ -1974,12 +1997,6 @@ CONFIG_NET_POLL_CONTROLLER=y CONFIG_VETH=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_MDIO=y CONFIG_NET_VENDOR_3COM=y @@ -2009,7 +2026,6 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set CONFIG_ALX=y -# CONFIG_NET_VENDOR_AURORA is not set CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_B44 is not set # CONFIG_BCMGENET is not set @@ -2078,6 +2094,7 @@ CONFIG_I40E=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_JME is not set CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set @@ -2181,6 +2198,7 @@ CONFIG_WIZNET_W5300=y # CONFIG_WIZNET_BUS_INDIRECT is not set CONFIG_WIZNET_BUS_ANY=y CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set CONFIG_FDDI=y @@ -2213,11 +2231,13 @@ CONFIG_AMD_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y @@ -2323,6 +2343,7 @@ CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_WAN is not set +# CONFIG_WWAN is not set # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set # CONFIG_NETDEVSIM is not set @@ -2489,17 +2510,13 @@ CONFIG_CONSOLE_POLL=y # end of Serial drivers CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_SYNCLINK_GT is not set -# CONFIG_ISI is not set # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set @@ -2510,7 +2527,6 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # CONFIG_NVRAM is not set # CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y @@ -2582,6 +2598,7 @@ CONFIG_I2C_PIIX4=m # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set @@ -2682,9 +2699,11 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2708,13 +2727,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m # CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_AMD_ENERGY is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set @@ -2765,6 +2784,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set @@ -2789,6 +2809,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_SBTSI is not set @@ -2861,6 +2882,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y # Intel thermal drivers # # CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_THERMAL_VECTOR=y CONFIG_X86_PKG_TEMP_THERMAL=m # CONFIG_INTEL_SOC_DTS_THERMAL is not set @@ -2871,6 +2893,7 @@ CONFIG_X86_PKG_TEMP_THERMAL=m # end of ACPI INT340X thermal drivers # CONFIG_INTEL_PCH_THERMAL is not set +# CONFIG_INTEL_TCC_COOLING is not set # end of Intel thermal drivers CONFIG_WATCHDOG=y @@ -2995,7 +3018,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_MFD_LP3943 is not set @@ -3021,6 +3043,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ATC260X_I2C is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set @@ -3055,12 +3078,10 @@ CONFIG_INTEL_GTT=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_VGA_SWITCHEROO is not set -CONFIG_DRM=y +CONFIG_DRM=m # CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_KMS_HELPER=m # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -3142,9 +3163,11 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m # # Frame buffer Devices @@ -3153,14 +3176,14 @@ CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_FOPS=m CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set @@ -3284,6 +3307,7 @@ CONFIG_HID_CYPRESS=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -3326,11 +3350,13 @@ CONFIG_HID_MONTEREY=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_STEAM is not set @@ -3364,7 +3390,7 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_ACPI is not set # end of I2C HID support # @@ -3467,7 +3493,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3580,6 +3606,7 @@ CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -3675,6 +3702,7 @@ CONFIG_RTC_DRV_CMOS=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3688,7 +3716,6 @@ CONFIG_DMA_ACPI=y # CONFIG_INTEL_IDXD is not set # CONFIG_INTEL_IOATDMA is not set # CONFIG_PLX_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y @@ -3697,6 +3724,7 @@ CONFIG_DW_DMAC_PCI=y # CONFIG_DW_EDMA is not set # CONFIG_DW_EDMA_PCIE is not set # CONFIG_SF_PDMA is not set +# CONFIG_INTEL_LDMA is not set # # DMA Clients @@ -3736,6 +3764,7 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_PMC_ATOM=y @@ -3755,6 +3784,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -3776,6 +3806,7 @@ CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # +CONFIG_IOMMU_IO_PGTABLE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set @@ -3845,7 +3876,6 @@ CONFIG_INTEL_IOMMU_FLOPPY_WA=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -3897,9 +3927,9 @@ CONFIG_RAS=y # CONFIG_LIBNVDIMM is not set CONFIG_DAX=y # CONFIG_DEV_DAX is not set -# CONFIG_DEV_DAX_HMEM is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -3984,6 +4014,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -4210,6 +4242,7 @@ CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -4272,6 +4305,7 @@ CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -4333,10 +4367,7 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y # CONFIG_CRYPTO_SHA1_SSSE3 is not set # CONFIG_CRYPTO_SHA256_SSSE3 is not set @@ -4346,7 +4377,6 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set @@ -4369,7 +4399,6 @@ CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_CHACHA20_X86_64 is not set # CONFIG_CRYPTO_SERPENT is not set @@ -4592,6 +4621,7 @@ CONFIG_FRAME_WARN=2048 CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_STACK_VALIDATION=y +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -4661,6 +4691,8 @@ CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y @@ -4712,6 +4744,11 @@ CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y +CONFIG_LOCKDEP_BITS=15 +CONFIG_LOCKDEP_CHAINS_BITS=16 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -4723,6 +4760,7 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_TRACE_IRQFLAGS=y CONFIG_TRACE_IRQFLAGS_NMI=y +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -4766,16 +4804,15 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y -CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792 CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y @@ -4806,6 +4843,7 @@ CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_CC=y CONFIG_TRACING_MAP=y CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y @@ -4867,6 +4905,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking From 851554049acf1c4fe272d7da02f4483c150250ef Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Thu, 25 Feb 2021 15:54:30 -0500 Subject: [PATCH 0047/2070] x86/configs: CRIU update debug rock defconfig - Update debug config for Checkpoint-Restore (CR) support - Also include necessary options for CR with docker containers. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 53 ++++++++++++++++++----------- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 4877da183599f..bc2a34666c1d9 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -249,6 +249,7 @@ CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_USERFAULTFD is not set +CONFIG_USERFAULTFD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y @@ -1015,6 +1016,11 @@ CONFIG_PACKET_DIAG=y CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_UNIX_DIAG=y +CONFIG_SMC_DIAG=y +CONFIG_XDP_SOCKETS_DIAG=y +CONFIG_INET_MPTCP_DIAG=y +CONFIG_TIPC_DIAG=y +CONFIG_VSOCKETS_DIAG=y # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_ALGO=y @@ -1052,15 +1058,17 @@ CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set # CONFIG_NET_FOU is not set # CONFIG_NET_FOU_IP_TUNNELS is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_INET_UDP_DIAG is not set -# CONFIG_INET_RAW_DIAG is not set -# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set CONFIG_TCP_CONG_CUBIC=y @@ -1085,12 +1093,14 @@ CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -# CONFIG_INET6_ESP_OFFLOAD is not set -# CONFIG_INET6_ESPINTCP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_DCCP_DIAG=m +CONFIG_INET_SCTP_DIAG=m # CONFIG_IPV6_ILA is not set # CONFIG_IPV6_VTI is not set CONFIG_IPV6_SIT=y @@ -1146,8 +1156,13 @@ CONFIG_NF_CT_PROTO_UDPLITE=y # CONFIG_NF_CONNTRACK_SANE is not set # CONFIG_NF_CONNTRACK_SIP is not set # CONFIG_NF_CONNTRACK_TFTP is not set -# CONFIG_NF_CT_NETLINK is not set -# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_SCSI_NETLINK=y +CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_NF_NAT=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y @@ -1992,7 +2007,7 @@ CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y # CONFIG_RIONET is not set -# CONFIG_TUN is not set +CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y # CONFIG_NLMON is not set @@ -3990,7 +4005,7 @@ CONFIG_MANDATORY_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y -# CONFIG_FANOTIFY is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set From 60935eca8758801546b963d185f72280f3c14c11 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 23 Mar 2022 10:30:01 -0400 Subject: [PATCH 0048/2070] rock-dbg_defconfig: Update for 5.16 Also enable ACPI HMAT support, to fix boot crash or amdgpu init failure on ALDEBARAN. v2: - Use make savedefconfig to minimize the changes, skipping redundant configs that are implied by others or have same value as default. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 4384 +-------------------------- 1 file changed, 3 insertions(+), 4381 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index bc2a34666c1d9..406fdfaceb550 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,1176 +1,182 @@ -# -# Automatically generated file; DO NOT EDIT. -# Linux/x86 5.13.0 Kernel Configuration -# -CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" -CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70500 -CONFIG_CLANG_VERSION=0 -CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=23000 -CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=23000 -CONFIG_LLD_VERSION=0 -CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_TABLE_SORT=y -CONFIG_THREAD_INFO_IN_TASK=y - -# -# General setup -# -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="-kfd" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_BUILD_SALT="" -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_XZ=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_KERNEL_LZ4=y -CONFIG_HAVE_KERNEL_ZSTD=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_XZ is not set -# CONFIG_KERNEL_LZO is not set -# CONFIG_KERNEL_LZ4 is not set -# CONFIG_KERNEL_ZSTD is not set -CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -# CONFIG_WATCH_QUEUE is not set -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_USELIB=y CONFIG_AUDIT=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_AUDITSYSCALL=y - -# -# IRQ subsystem -# -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y -CONFIG_GENERIC_IRQ_RESERVATION_MODE=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set -# end of IRQ subsystem - -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_ARCH_CLOCKSOURCE_INIT=y -CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y - -# -# Timers subsystem -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ_COMMON=y -# CONFIG_HZ_PERIODIC is not set -CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -# end of Timers subsystem - -CONFIG_BPF=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y - -# -# BPF subsystem -# CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set -# CONFIG_BPF_PRELOAD is not set -# end of BPF subsystem - -# CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -CONFIG_PREEMPT_COUNT=y - -# -# CPU/Task time and stats accounting -# -CONFIG_TICK_CPU_ACCOUNTING=y -# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -# CONFIG_IRQ_TIME_ACCOUNTING is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_PSI is not set -# end of CPU/Task time and stats accounting - # CONFIG_CPU_ISOLATION is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_RCU_EXPERT is not set -CONFIG_SRCU=y -CONFIG_TREE_SRCU=y -CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_RUDE_RCU=y -CONFIG_TASKS_TRACE_RCU=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RCU_NEED_SEGCBLIST=y -# end of RCU Subsystem - -CONFIG_BUILD_BIN2C=y -# CONFIG_IKCONFIG is not set -# CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=18 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 -CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y - -# -# Scheduler features -# -# CONFIG_UCLAMP_TASK is not set -# end of Scheduler features - -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y -CONFIG_CC_HAS_INT128=y -CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y -CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y -CONFIG_CGROUPS=y -CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_WRITEBACK=y -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y -# CONFIG_RT_GROUP_SCHED is not set CONFIG_CGROUP_PIDS=y -# CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -# CONFIG_CGROUP_MISC is not set -# CONFIG_CGROUP_DEBUG is not set -CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_TIME_NS=y -CONFIG_IPC_NS=y CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y -# CONFIG_SYSFS_DEPRECATED is not set -CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_RD_LZ4=y -CONFIG_RD_ZSTD=y -# CONFIG_BOOT_CONFIG is not set -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_LD_ORPHAN_WARN=y -CONFIG_SYSCTL=y -CONFIG_HAVE_UID16=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_EXPERT=y -CONFIG_UID16=y -CONFIG_MULTIUSER=y -CONFIG_SGETMASK_SYSCALL=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_FHANDLE=y -CONFIG_POSIX_TIMERS=y -CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_FUTEX_PI=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_IO_URING=y -CONFIG_ADVISE_SYSCALLS=y -CONFIG_MEMBARRIER=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y -CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_USERFAULTFD=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -# CONFIG_DEBUG_RSEQ is not set -# CONFIG_EMBEDDED is not set -CONFIG_HAVE_PERF_EVENTS=y -# CONFIG_PC104 is not set - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# end of Kernel Performance Events And Counters - -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y # CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y -CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -# end of General setup - -CONFIG_64BIT=y -CONFIG_X86_64=y -CONFIG_X86=y -CONFIG_INSTRUCTION_DECODER=y -CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_MMU=y -CONFIG_ARCH_MMAP_RND_BITS_MIN=28 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_FILTER_PGPROT=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ZONE_DMA32=y -CONFIG_AUDIT_ARCH=y -CONFIG_HAVE_INTEL_TXT=y -CONFIG_X86_64_SMP=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_CC_HAS_SANE_STACKPROTECTOR=y - -# -# Processor type and features -# -CONFIG_ZONE_DMA=y CONFIG_SMP=y -CONFIG_X86_FEATURE_NAMES=y -# CONFIG_X86_X2APIC is not set -CONFIG_X86_MPPARSE=y -# CONFIG_GOLDFISH is not set # CONFIG_RETPOLINE is not set -# CONFIG_X86_CPU_RESCTRL is not set -CONFIG_X86_EXTENDED_PLATFORM=y -# CONFIG_X86_VSMP is not set -# CONFIG_X86_GOLDFISH is not set CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_IOSF_MBI=y CONFIG_IOSF_MBI_DEBUG=y -CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y -# CONFIG_PARAVIRT_DEBUG is not set CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_X86_HV_CALLBACK_VECTOR=y -# CONFIG_XEN is not set -CONFIG_KVM_GUEST=y -CONFIG_ARCH_CPUIDLE_HALTPOLL=y -# CONFIG_PVH is not set -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_JAILHOUSE_GUEST is not set -# CONFIG_ACRN_GUEST is not set -# CONFIG_MK8 is not set -# CONFIG_MPSC is not set -# CONFIG_MCORE2 is not set -# CONFIG_MATOM is not set -CONFIG_GENERIC_CPU=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=6 -CONFIG_X86_L1_CACHE_SHIFT=6 -CONFIG_X86_TSC=y -CONFIG_X86_CMPXCHG64=y -CONFIG_X86_CMOV=y -CONFIG_X86_MINIMUM_CPU_FAMILY=64 -CONFIG_X86_DEBUGCTLMSR=y -CONFIG_IA32_FEAT_CTL=y -CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y -CONFIG_CPU_SUP_INTEL=y -CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_HYGON=y -CONFIG_CPU_SUP_CENTAUR=y -CONFIG_CPU_SUP_ZHAOXIN=y -CONFIG_HPET_TIMER=y -CONFIG_HPET_EMULATE_RTC=y -CONFIG_DMI=y CONFIG_GART_IOMMU=y -# CONFIG_MAXSMP is not set -CONFIG_NR_CPUS_RANGE_BEGIN=2 -CONFIG_NR_CPUS_RANGE_END=512 -CONFIG_NR_CPUS_DEFAULT=64 CONFIG_NR_CPUS=256 -CONFIG_SCHED_SMT=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_MC_PRIO=y -CONFIG_X86_LOCAL_APIC=y -CONFIG_X86_IO_APIC=y CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_X86_MCE=y -# CONFIG_X86_MCELOG_LEGACY is not set -CONFIG_X86_MCE_INTEL=y -CONFIG_X86_MCE_AMD=y -CONFIG_X86_MCE_THRESHOLD=y -# CONFIG_X86_MCE_INJECT is not set - -# -# Performance monitoring -# -CONFIG_PERF_EVENTS_INTEL_UNCORE=y -CONFIG_PERF_EVENTS_INTEL_RAPL=y -CONFIG_PERF_EVENTS_INTEL_CSTATE=y -# CONFIG_PERF_EVENTS_AMD_POWER is not set -# end of Performance monitoring - -CONFIG_X86_16BIT=y -CONFIG_X86_ESPFIX64=y -CONFIG_X86_VSYSCALL_EMULATION=y -CONFIG_X86_IOPL_IOPERM=y CONFIG_I8K=m -CONFIG_MICROCODE=y -CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_AMD=y CONFIG_MICROCODE_OLD_INTERFACE=y CONFIG_X86_MSR=m CONFIG_X86_CPUID=m # CONFIG_X86_5LEVEL is not set -CONFIG_X86_DIRECT_GBPAGES=y -# CONFIG_X86_CPA_STATISTICS is not set -# CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_NUMA=y -CONFIG_AMD_NUMA=y -CONFIG_X86_64_ACPI_NUMA=y -# CONFIG_NUMA_EMU is not set -CONFIG_NODES_SHIFT=6 -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_MEMORY_PROBE=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -# CONFIG_X86_PMEM_LEGACY is not set CONFIG_X86_CHECK_BIOS_CORRUPTION=y -CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y -CONFIG_X86_RESERVE_LOW=64 -CONFIG_MTRR=y -CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 -CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 -CONFIG_X86_PAT=y -CONFIG_ARCH_USES_PG_UNCACHED=y -CONFIG_ARCH_RANDOM=y -CONFIG_X86_SMAP=y -CONFIG_X86_UMIP=y -CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y -CONFIG_X86_INTEL_TSX_MODE_OFF=y -# CONFIG_X86_INTEL_TSX_MODE_ON is not set -# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set -# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y -CONFIG_ARCH_HAS_KEXEC_PURGATORY=y -# CONFIG_KEXEC_SIG is not set CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y -CONFIG_PHYSICAL_START=0x1000000 -CONFIG_RELOCATABLE=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_X86_NEED_RELOCS=y CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_DYNAMIC_MEMORY_LAYOUT=y -CONFIG_RANDOMIZE_MEMORY=y -CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa -CONFIG_HOTPLUG_CPU=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -# CONFIG_COMPAT_VDSO is not set CONFIG_LEGACY_VSYSCALL_EMULATE=y -# CONFIG_LEGACY_VSYSCALL_XONLY is not set -# CONFIG_LEGACY_VSYSCALL_NONE is not set -# CONFIG_CMDLINE_BOOL is not set -CONFIG_MODIFY_LDT_SYSCALL=y -CONFIG_HAVE_LIVEPATCH=y -# CONFIG_LIVEPATCH is not set -# end of Processor type and features - -CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y - -# -# Power management and ACPI options -# -CONFIG_ARCH_HIBERNATION_HEADER=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SUSPEND_SKIP_SYNC is not set -CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y -CONFIG_HIBERNATION_SNAPSHOT_DEV=y -CONFIG_PM_STD_PARTITION="" -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -# CONFIG_PM_AUTOSLEEP is not set CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=100 -CONFIG_PM_WAKELOCKS_GC=y -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_PM_SLEEP_DEBUG=y -# CONFIG_DPM_WATCHDOG is not set -CONFIG_PM_TRACE=y CONFIG_PM_TRACE_RTC=y -CONFIG_PM_CLK=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -# CONFIG_ENERGY_MODEL is not set -CONFIG_ARCH_SUPPORTS_ACPI=y -CONFIG_ACPI=y -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -# CONFIG_ACPI_DEBUGGER is not set -CONFIG_ACPI_SPCR_TABLE=y -# CONFIG_ACPI_FPDT is not set -CONFIG_ACPI_LPIT=y -CONFIG_ACPI_SLEEP=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=m -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BUTTON=y CONFIG_ACPI_VIDEO=m -CONFIG_ACPI_FAN=y -# CONFIG_ACPI_TAD is not set CONFIG_ACPI_DOCK=y -CONFIG_ACPI_CPU_FREQ_PSS=y -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_CPPC_LIB=y -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m -CONFIG_ACPI_THERMAL=y -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ACPI_TABLE_UPGRADE=y -# CONFIG_ACPI_DEBUG is not set CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HOTPLUG_MEMORY=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y CONFIG_ACPI_SBS=m -CONFIG_ACPI_HED=y -# CONFIG_ACPI_CUSTOM_METHOD is not set CONFIG_ACPI_BGRT=y -# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set -# CONFIG_ACPI_NFIT is not set -CONFIG_ACPI_NUMA=y -# CONFIG_ACPI_HMAT is not set -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_HMAT=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=m -# CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_CONFIGFS is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_X86_PM_TIMER=y - -# -# CPU Frequency scaling -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y - -# -# CPU frequency scaling drivers -# -CONFIG_X86_INTEL_PSTATE=y -# CONFIG_X86_PCC_CPUFREQ is not set CONFIG_X86_ACPI_CPUFREQ=y # CONFIG_X86_ACPI_CPUFREQ_CPB is not set -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -# CONFIG_X86_P4_CLOCKMOD is not set - -# -# shared options -# -# end of CPU Frequency scaling - -# -# CPU Idle -# -CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -# CONFIG_CPU_IDLE_GOV_TEO is not set -# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set -CONFIG_HALTPOLL_CPUIDLE=y -# end of CPU Idle - -# CONFIG_INTEL_IDLE is not set -# end of Power management and ACPI options - -# -# Bus options (PCI etc.) -# -CONFIG_PCI_DIRECT=y -CONFIG_PCI_MMCONFIG=y -CONFIG_MMCONF_FAM10H=y -# CONFIG_PCI_CNB20LE_QUIRK is not set -# CONFIG_ISA_BUS is not set -CONFIG_ISA_DMA_API=y -CONFIG_AMD_NB=y -# CONFIG_X86_SYSFB is not set -# end of Bus options (PCI etc.) - -# -# Binary Emulations -# CONFIG_IA32_EMULATION=y -# CONFIG_X86_X32 is not set -CONFIG_COMPAT_32=y -CONFIG_COMPAT=y -CONFIG_COMPAT_FOR_U64_ALIGNMENT=y -CONFIG_SYSVIPC_COMPAT=y -# end of Binary Emulations - -# -# Firmware Drivers -# -# CONFIG_EDD is not set -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set -CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_VARS=y -CONFIG_EFI_ESRT=y -CONFIG_EFI_VARS_PSTORE=y -# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set -CONFIG_EFI_RUNTIME_MAP=y -# CONFIG_EFI_FAKE_MEMMAP is not set -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_APPLE_PROPERTIES is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_RCI2_TABLE is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_UEFI_CPER=y -CONFIG_UEFI_CPER_X86=y -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - -CONFIG_HAVE_KVM=y -CONFIG_VIRTUALIZATION=y -# CONFIG_KVM is not set -CONFIG_AS_AVX512=y -CONFIG_AS_SHA1_NI=y -CONFIG_AS_SHA256_NI=y - -# -# General architecture-dependent options -# -CONFIG_CRASH_CORE=y -CONFIG_KEXEC_CORE=y -CONFIG_HOTPLUG_SMT=y -CONFIG_GENERIC_ENTRY=y -CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y -# CONFIG_STATIC_KEYS_SELFTEST is not set -# CONFIG_STATIC_CALL_SELFTEST is not set -CONFIG_OPTPROBES=y -CONFIG_KPROBES_ON_FTRACE=y -CONFIG_UPROBES=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_KRETPROBES=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_KPROBES_ON_FTRACE=y -CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y -CONFIG_HAVE_NMI=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SET_DIRECT_MAP=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y -CONFIG_HAVE_USER_RETURN_NOTIFIER=y -CONFIG_HAVE_PERF_EVENTS_NMI=y -CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_MMU_GATHER_TABLE_FREE=y -CONFIG_MMU_GATHER_RCU_TABLE_FREE=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y -CONFIG_HAVE_ARCH_SECCOMP=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -# CONFIG_SECCOMP_CACHE_DEBUG is not set -CONFIG_HAVE_ARCH_STACKLEAK=y -CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y -CONFIG_LTO_NONE=y -CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOVE_PUD=y -CONFIG_HAVE_MOVE_PMD=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_HAVE_ARCH_SOFT_DIRTY=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_HAVE_EXIT_THREAD=y -CONFIG_ARCH_MMAP_RND_BITS=28 -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 -CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y -CONFIG_HAVE_STACK_VALIDATION=y -CONFIG_HAVE_RELIABLE_STACKTRACE=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_VMAP_STACK=y -CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y -# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -# CONFIG_LOCK_EVENT_COUNTS is not set -CONFIG_ARCH_HAS_MEM_ENCRYPT=y -CONFIG_HAVE_STATIC_CALL=y -CONFIG_HAVE_STATIC_CALL_INLINE=y -CONFIG_HAVE_PREEMPT_DYNAMIC=y -CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_HAS_ELFCORE_COMPAT=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -# end of GCOV-based kernel profiling - -CONFIG_HAVE_GCC_PLUGINS=y -# end of General architecture-dependent options - -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y -CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y -# CONFIG_MODULE_SIG_FORCE is not set -CONFIG_MODULE_SIG_ALL=y -# CONFIG_MODULE_SIG_SHA1 is not set -# CONFIG_MODULE_SIG_SHA224 is not set -# CONFIG_MODULE_SIG_SHA256 is not set -# CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y -CONFIG_MODULE_SIG_HASH="sha512" -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -CONFIG_MODPROBE_PATH="/sbin/modprobe" -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -# CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set -CONFIG_BLK_CMDLINE_PARSER=y -# CONFIG_BLK_WBT is not set -# CONFIG_BLK_CGROUP_IOLATENCY is not set -# CONFIG_BLK_CGROUP_IOCOST is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set -# CONFIG_BLK_INLINE_ENCRYPTION is not set - -# -# Partition Types -# CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_AIX_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -# CONFIG_CMDLINE_PARTITION is not set -# end of Partition Types - -CONFIG_BLOCK_COMPAT=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y - -# -# IO Schedulers -# -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -# CONFIG_IOSCHED_BFQ is not set -# end of IO Schedulers - -CONFIG_ASN1=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y -CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y -CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y -CONFIG_FREEZER=y - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_ELFCORE=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_SCRIPT=y CONFIG_BINFMT_MISC=y -CONFIG_COREDUMP=y -# end of Executable file formats - -# -# Memory Management options -# -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_FAST_GUP=y -CONFIG_NUMA_KEEP_MEMINFO=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_HAVE_BOOTMEM_INFO_NODE=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_SPARSE=y -# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTREMOVE=y -CONFIG_MHP_MEMMAP_ON_MEMORY=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_COMPACTION=y -# CONFIG_PAGE_REPORTING is not set -CONFIG_MIGRATION=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y -CONFIG_CONTIG_ALLOC=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_VIRT_TO_BUS=y -CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y CONFIG_HWPOISON_INJECT=m CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_THP_SWAP=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" -CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y -# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" -# CONFIG_ZSWAP_DEFAULT_ON is not set -CONFIG_ZPOOL=y -CONFIG_ZBUD=y -# CONFIG_Z3FOLD is not set CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set -# CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y -CONFIG_DEV_PAGEMAP_OPS=y -CONFIG_HMM_MIRROR=y CONFIG_DEVICE_PRIVATE=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y -CONFIG_ARCH_HAS_PKEYS=y -# CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_TEST is not set -# CONFIG_READ_ONLY_THP_FOR_FS is not set -CONFIG_ARCH_HAS_PTE_SPECIAL=y -# end of Memory Management options - CONFIG_NET=y -CONFIG_NET_INGRESS=y -CONFIG_SKB_EXTENSIONS=y - -# -# Networking options -# CONFIG_PACKET=y CONFIG_PACKET_DIAG=y CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_UNIX_DIAG=y -CONFIG_SMC_DIAG=y -CONFIG_XDP_SOCKETS_DIAG=y -CONFIG_INET_MPTCP_DIAG=y -CONFIG_TIPC_DIAG=y -CONFIG_VSOCKETS_DIAG=y -# CONFIG_TLS is not set -CONFIG_XFRM=y -CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y -# CONFIG_XFRM_USER_COMPAT is not set -# CONFIG_XFRM_INTERFACE is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_AH=y -CONFIG_XFRM_ESP=y -# CONFIG_NET_KEY is not set -# CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_FIB_TRIE_STATS is not set CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=y -CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y -# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_NET_IPVTI is not set -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set CONFIG_INET_AH=m CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_IPCOMP=m CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set -CONFIG_TCP_CONG_CUBIC=y # CONFIG_TCP_CONG_WESTWOOD is not set # CONFIG_TCP_CONG_HTCP is not set -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_VEGAS is not set -# CONFIG_TCP_CONG_NV is not set -# CONFIG_TCP_CONG_SCALABLE is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_VENO is not set -# CONFIG_TCP_CONG_YEAH is not set -# CONFIG_TCP_CONG_ILLINOIS is not set -# CONFIG_TCP_CONG_DCTCP is not set -# CONFIG_TCP_CONG_CDG is not set -# CONFIG_TCP_CONG_BBR is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -CONFIG_IPV6=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_ESP_OFFLOAD=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET_DCCP_DIAG=m -CONFIG_INET_SCTP_DIAG=m -# CONFIG_IPV6_ILA is not set -# CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_IPV6_SEG6_LWTUNNEL is not set -# CONFIG_IPV6_SEG6_HMAC is not set -# CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y -# CONFIG_MPTCP is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NET_PTP_CLASSIFY=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y -CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=m - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_INGRESS=y -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_FAMILY_BRIDGE=y -CONFIG_NETFILTER_FAMILY_ARP=y -CONFIG_NETFILTER_NETLINK_ACCT=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_SYSLOG=m -CONFIG_NETFILTER_CONNCOUNT=m -CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y # CONFIG_NF_CONNTRACK_PROCFS is not set CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_LABELS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_FTP is not set -# CONFIG_NF_CONNTRACK_H323 is not set -# CONFIG_NF_CONNTRACK_IRC is not set -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -# CONFIG_NF_CONNTRACK_SNMP is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -# CONFIG_NF_CONNTRACK_SANE is not set -# CONFIG_NF_CONNTRACK_SIP is not set -# CONFIG_NF_CONNTRACK_TFTP is not set -CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_TIMEOUT=m CONFIG_NF_CT_NETLINK_HELPER=m CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_SCSI_NETLINK=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_NF_NAT=m -CONFIG_NF_NAT_REDIRECT=y -CONFIG_NF_NAT_MASQUERADE=y -CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -# CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y -# CONFIG_NFT_NUMGEN is not set CONFIG_NFT_CT=m CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m @@ -1180,36 +186,10 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -# CONFIG_NFT_OBJREF is not set -# CONFIG_NFT_QUEUE is not set CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m -# CONFIG_NFT_COMPAT is not set -# CONFIG_NFT_HASH is not set -CONFIG_NFT_FIB=m CONFIG_NFT_XFRM=m -# CONFIG_NFT_SOCKET is not set -# CONFIG_NFT_OSF is not set -# CONFIG_NFT_TPROXY is not set -# CONFIG_NFT_SYNPROXY is not set CONFIG_NF_DUP_NETDEV=m -# CONFIG_NFT_DUP_NETDEV is not set -# CONFIG_NFT_FWD_NETDEV is not set -# CONFIG_NFT_FIB_NETDEV is not set -# CONFIG_NFT_REJECT_NETDEV is not set -# CONFIG_NF_FLOW_TABLE is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XTABLES_COMPAT=y - -# -# Xtables combined modules -# -CONFIG_NETFILTER_XT_MARK=m -CONFIG_NETFILTER_XT_CONNMARK=m - -# -# Xtables targets -# CONFIG_NETFILTER_XT_TARGET_AUDIT=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -1217,30 +197,19 @@ CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_NAT=m -CONFIG_NETFILTER_XT_TARGET_NETMAP=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m - -# -# Xtables matches -# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CGROUP=m @@ -1255,11 +224,9 @@ CONFIG_NETFILTER_XT_MATCH_CPU=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPCOMP=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_L2TP=m @@ -1279,33 +246,17 @@ CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m -# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -# end of Core Netfilter Configuration - -# CONFIG_IP_SET is not set -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -# CONFIG_NF_SOCKET_IPV4 is not set -CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y -CONFIG_NFT_REJECT_IPV4=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_DUP_IPV4=m -# CONFIG_NF_LOG_ARP is not set CONFIG_NF_LOG_IPV4=m -CONFIG_NF_REJECT_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -1327,1744 +278,127 @@ CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -# end of IP: Netfilter Configuration - -# -# IPv6: Netfilter Configuration -# -# CONFIG_NF_SOCKET_IPV6 is not set -CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y -CONFIG_NFT_REJECT_IPV6=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_DUP_IPV6=m -CONFIG_NF_REJECT_IPV6=m -CONFIG_NF_LOG_IPV6=m CONFIG_IP6_NF_IPTABLES=m -# CONFIG_IP6_NF_MATCH_AH is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_MH is not set -# CONFIG_IP6_NF_MATCH_RPFILTER is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_MATCH_SRH is not set -# CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m -# CONFIG_IP6_NF_TARGET_SYNPROXY is not set CONFIG_IP6_NF_MANGLE=m -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_SECURITY is not set CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m -# CONFIG_IP6_NF_TARGET_NPT is not set -# end of IPv6: Netfilter Configuration - -CONFIG_NF_DEFRAG_IPV6=m -# CONFIG_NF_TABLES_BRIDGE is not set -# CONFIG_NF_CONNTRACK_BRIDGE is not set -# CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_L2TP is not set -CONFIG_STP=y CONFIG_BRIDGE=y -CONFIG_BRIDGE_IGMP_SNOOPING=y -# CONFIG_BRIDGE_VLAN_FILTERING is not set -# CONFIG_BRIDGE_MRP is not set -# CONFIG_BRIDGE_CFM is not set -# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y -# CONFIG_VLAN_8021Q_GVRP is not set -# CONFIG_VLAN_8021Q_MVRP is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_PHONET is not set -# CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFB is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_CBS is not set -# CONFIG_NET_SCH_ETF is not set -# CONFIG_NET_SCH_TAPRIO is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set -# CONFIG_NET_SCH_MQPRIO is not set -# CONFIG_NET_SCH_SKBPRIO is not set -# CONFIG_NET_SCH_CHOKE is not set -# CONFIG_NET_SCH_QFQ is not set -# CONFIG_NET_SCH_CODEL is not set -# CONFIG_NET_SCH_FQ_CODEL is not set -# CONFIG_NET_SCH_CAKE is not set -# CONFIG_NET_SCH_FQ is not set -# CONFIG_NET_SCH_HHF is not set -# CONFIG_NET_SCH_PIE is not set -# CONFIG_NET_SCH_INGRESS is not set -# CONFIG_NET_SCH_PLUG is not set -# CONFIG_NET_SCH_ETS is not set -# CONFIG_NET_SCH_DEFAULT is not set - -# -# Classification -# -CONFIG_NET_CLS=y -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set -# CONFIG_NET_CLS_FW is not set -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_CLS_CGROUP is not set -# CONFIG_NET_CLS_BPF is not set -# CONFIG_NET_CLS_FLOWER is not set -# CONFIG_NET_CLS_MATCHALL is not set CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -# CONFIG_NET_EMATCH_CMP is not set -# CONFIG_NET_EMATCH_NBYTE is not set -# CONFIG_NET_EMATCH_U32 is not set -# CONFIG_NET_EMATCH_META is not set -# CONFIG_NET_EMATCH_TEXT is not set -# CONFIG_NET_EMATCH_IPT is not set CONFIG_NET_CLS_ACT=y -# CONFIG_NET_ACT_POLICE is not set -# CONFIG_NET_ACT_GACT is not set -# CONFIG_NET_ACT_MIRRED is not set -# CONFIG_NET_ACT_SAMPLE is not set -# CONFIG_NET_ACT_IPT is not set -# CONFIG_NET_ACT_NAT is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_ACT_SIMP is not set -# CONFIG_NET_ACT_SKBEDIT is not set -# CONFIG_NET_ACT_CSUM is not set -# CONFIG_NET_ACT_MPLS is not set -# CONFIG_NET_ACT_VLAN is not set -# CONFIG_NET_ACT_BPF is not set -# CONFIG_NET_ACT_CONNMARK is not set -# CONFIG_NET_ACT_CTINFO is not set -# CONFIG_NET_ACT_SKBMOD is not set -# CONFIG_NET_ACT_IFE is not set -# CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_GATE is not set -# CONFIG_NET_TC_SKB_EXT is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set -CONFIG_DNS_RESOLVER=y -# CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_VSOCKETS is not set CONFIG_NETLINK_DIAG=y -# CONFIG_MPLS is not set -# CONFIG_NET_NSH is not set -# CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set -# CONFIG_QRTR is not set -# CONFIG_NET_NCSI is not set -CONFIG_PCPU_DEV_REFCNT=y -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_XPS=y -# CONFIG_CGROUP_NET_PRIO is not set -CONFIG_CGROUP_NET_CLASSID=y -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -# CONFIG_BPF_STREAM_PARSER is not set -CONFIG_NET_FLOW_LIMIT=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# end of Network testing -# end of Networking options - CONFIG_HAMRADIO=y - -# -# Packet Radio protocols -# -# CONFIG_AX25 is not set -# CONFIG_CAN is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_AF_KCM is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y -CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set -# CONFIG_CEPH_LIB is not set -# CONFIG_NFC is not set -# CONFIG_PSAMPLE is not set -# CONFIG_NET_IFE is not set -# CONFIG_LWTUNNEL is not set -CONFIG_DST_CACHE=y -CONFIG_GRO_CELLS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y -# CONFIG_FAILOVER is not set -CONFIG_ETHTOOL_NETLINK=y - -# -# Device Drivers -# -CONFIG_HAVE_EISA=y -# CONFIG_EISA is not set -CONFIG_HAVE_PCI=y CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y -# CONFIG_PCIEAER_INJECT is not set -# CONFIG_PCIE_ECRC is not set -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -# CONFIG_PCIEASPM_PERFORMANCE is not set -CONFIG_PCIE_PME=y -# CONFIG_PCIE_DPC is not set -# CONFIG_PCIE_PTM is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_DEBUG is not set CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y -# CONFIG_PCI_PF_STUB is not set -CONFIG_PCI_ATS=y -CONFIG_PCI_LOCKLESS_CONFIG=y CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -# CONFIG_PCI_P2PDMA is not set -CONFIG_PCI_LABEL=y -# CONFIG_PCIE_BUS_TUNE_OFF is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_ACPI is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set - -# -# PCI controller drivers -# -# CONFIG_VMD is not set - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCI_MESON is not set -# end of DesignWare PCI Core Support - -# -# Mobiveil PCIe Core Support -# -# end of Mobiveil PCIe Core Support - -# -# Cadence PCIe controllers support -# -# end of Cadence PCIe controllers support -# end of PCI controller drivers - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set -# end of PCI Endpoint - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set -# end of PCI switch controller drivers - -# CONFIG_CXL_BUS is not set -# CONFIG_PCCARD is not set CONFIG_RAPIDIO=y -# CONFIG_RAPIDIO_TSI721 is not set -CONFIG_RAPIDIO_DISC_TIMEOUT=30 -# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set CONFIG_RAPIDIO_DMA_ENGINE=y -# CONFIG_RAPIDIO_DEBUG is not set -# CONFIG_RAPIDIO_ENUM_BASIC is not set -# CONFIG_RAPIDIO_CHMAN is not set -# CONFIG_RAPIDIO_MPORT_CDEV is not set - -# -# RapidIO Switch drivers -# -# CONFIG_RAPIDIO_TSI57X is not set -# CONFIG_RAPIDIO_CPS_XX is not set -# CONFIG_RAPIDIO_TSI568 is not set -# CONFIG_RAPIDIO_CPS_GEN2 is not set -# CONFIG_RAPIDIO_RXS_GEN3 is not set -# end of RapidIO Switch drivers - -# -# Generic Driver Options -# CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set - -# -# Firmware loader -# -CONFIG_FW_LOADER=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set -# CONFIG_FW_LOADER_COMPRESS is not set -CONFIG_FW_CACHE=y -# end of Firmware loader - -CONFIG_ALLOW_DEV_COREDUMP=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DMA_FENCE_TRACE is not set -# end of Generic Driver Options - -# -# Bus devices -# -# CONFIG_MHI_BUS is not set -# end of Bus devices - -# CONFIG_CONNECTOR is not set -# CONFIG_GNSS is not set -# CONFIG_MTD is not set -# CONFIG_OF is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_EFI_VARS=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y CONFIG_PARPORT_SERIAL=y -# CONFIG_PARPORT_PC_FIFO is not set -# CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_AX88796 is not set -# CONFIG_PARPORT_1284 is not set -CONFIG_PNP=y -CONFIG_PNP_DEBUG_MESSAGES=y - -# -# Protocols -# -CONFIG_PNPACPI=y -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_BLK_DEV_FD is not set -CONFIG_CDROM=y -# CONFIG_PARIDE is not set -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set - -# -# NVME Support -# -CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y -# CONFIG_NVME_MULTIPATH is not set -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_FC is not set -# CONFIG_NVME_TCP is not set -# CONFIG_NVME_TARGET is not set -# end of NVME Support - -# -# Misc devices -# -# CONFIG_AD525X_DPOT is not set -# CONFIG_DUMMY_IRQ is not set -# CONFIG_IBM_ASM is not set -# CONFIG_PHANTOM is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set -# CONFIG_SRAM is not set -# CONFIG_DW_XDATA_PCIE is not set -# CONFIG_PCI_ENDPOINT_TEST is not set -# CONFIG_XILINX_SDFEC is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -# CONFIG_EEPROM_EE1004 is not set -# end of EEPROM support - -# CONFIG_CB710_CORE is not set - -# -# Texas Instruments shared transport line discipline -# -# end of Texas Instruments shared transport line discipline - -# CONFIG_SENSORS_LIS3_I2C is not set -# CONFIG_ALTERA_STAPL is not set -# CONFIG_INTEL_MEI is not set -# CONFIG_INTEL_MEI_ME is not set -# CONFIG_INTEL_MEI_TXE is not set -# CONFIG_VMWARE_VMCI is not set -# CONFIG_GENWQE is not set -# CONFIG_ECHO is not set -# CONFIG_BCM_VK is not set -# CONFIG_MISC_ALCOR_PCI is not set -# CONFIG_MISC_RTSX_PCI is not set -# CONFIG_MISC_RTSX_USB is not set -# CONFIG_HABANA_AI is not set -# CONFIG_UACCE is not set -# CONFIG_PVPANIC is not set -# end of Misc devices - -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=y -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# end of SCSI Transports - # CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# end of SCSI device support - CONFIG_ATA=y -CONFIG_SATA_HOST=y -CONFIG_PATA_TIMINGS=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_ATA_FORCE=y -CONFIG_ATA_ACPI=y -# CONFIG_SATA_ZPODD is not set -CONFIG_SATA_PMP=y - -# -# Controllers with non-SFF native interface -# CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_ACARD_AHCI is not set CONFIG_SATA_SIL24=y -CONFIG_ATA_SFF=y - -# -# SFF controllers with custom DMA interface -# -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set CONFIG_SATA_SX4=y -CONFIG_ATA_BMDMA=y - -# -# SATA SFF controllers with BMDMA -# CONFIG_ATA_PIIX=y -# CONFIG_SATA_DWC is not set -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set CONFIG_SATA_PROMISE=y CONFIG_SATA_SIL=y -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set - -# -# PATA SFF controllers with BMDMA -# -# CONFIG_PATA_ALI is not set CONFIG_PATA_AMD=y -# CONFIG_PATA_ARTOP is not set CONFIG_PATA_ATIIXP=y -# CONFIG_PATA_ATP867X is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87415 is not set CONFIG_PATA_OLDPIIX=y -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RDC is not set CONFIG_PATA_SCH=y CONFIG_PATA_SERVERWORKS=y -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TOSHIBA is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set - -# -# PIO-only SFF controllers -# -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_RZ1000 is not set - -# -# Generic fallback / legacy drivers -# -# CONFIG_PATA_ACPI is not set CONFIG_ATA_GENERIC=y -# CONFIG_PATA_LEGACY is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y -CONFIG_MD_AUTODETECT=y -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID10 is not set -# CONFIG_MD_RAID456 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_MD_FAULTY is not set -# CONFIG_BCACHE is not set -CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y -# CONFIG_DM_DEBUG is not set -# CONFIG_DM_UNSTRIPED is not set -# CONFIG_DM_CRYPT is not set -# CONFIG_DM_SNAPSHOT is not set -# CONFIG_DM_THIN_PROVISIONING is not set -# CONFIG_DM_CACHE is not set -# CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_EBS is not set -# CONFIG_DM_ERA is not set -# CONFIG_DM_CLONE is not set CONFIG_DM_MIRROR=y -# CONFIG_DM_LOG_USERSPACE is not set -# CONFIG_DM_RAID is not set CONFIG_DM_ZERO=y -# CONFIG_DM_MULTIPATH is not set -# CONFIG_DM_DELAY is not set -# CONFIG_DM_DUST is not set -# CONFIG_DM_INIT is not set -# CONFIG_DM_UEVENT is not set -# CONFIG_DM_FLAKEY is not set -# CONFIG_DM_VERITY is not set -# CONFIG_DM_SWITCH is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_DM_INTEGRITY is not set -# CONFIG_TARGET_CORE is not set CONFIG_FUSION=y CONFIG_FUSION_SPI=y -# CONFIG_FUSION_SAS is not set -CONFIG_FUSION_MAX_SGE=128 -# CONFIG_FUSION_CTL is not set -# CONFIG_FUSION_LOGGING is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set -# end of IEEE 1394 (FireWire) support - -# CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_CORE=y -# CONFIG_BONDING is not set -# CONFIG_DUMMY is not set -# CONFIG_WIREGUARD is not set -# CONFIG_EQUALIZER is not set -# CONFIG_NET_FC is not set -# CONFIG_IFB is not set -# CONFIG_NET_TEAM is not set CONFIG_MACVLAN=y -# CONFIG_MACVTAP is not set -# CONFIG_IPVLAN is not set -# CONFIG_VXLAN is not set -# CONFIG_GENEVE is not set -# CONFIG_BAREUDP is not set -# CONFIG_GTP is not set -# CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_RIONET is not set CONFIG_TUN=y -# CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y -# CONFIG_NLMON is not set -# CONFIG_ARCNET is not set -CONFIG_ETHERNET=y -CONFIG_MDIO=y -CONFIG_NET_VENDOR_3COM=y -# CONFIG_VORTEX is not set -# CONFIG_TYPHOON is not set -CONFIG_NET_VENDOR_ADAPTEC=y -# CONFIG_ADAPTEC_STARFIRE is not set -CONFIG_NET_VENDOR_AGERE=y -# CONFIG_ET131X is not set -CONFIG_NET_VENDOR_ALACRITECH=y -# CONFIG_SLICOSS is not set -CONFIG_NET_VENDOR_ALTEON=y -# CONFIG_ACENIC is not set -# CONFIG_ALTERA_TSE is not set -CONFIG_NET_VENDOR_AMAZON=y -# CONFIG_ENA_ETHERNET is not set -CONFIG_NET_VENDOR_AMD=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_PCNET32 is not set -# CONFIG_AMD_XGBE is not set -CONFIG_NET_VENDOR_AQUANTIA=y -# CONFIG_AQTION is not set -CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_ATHEROS=y -# CONFIG_ATL2 is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set CONFIG_ALX=y -CONFIG_NET_VENDOR_BROADCOM=y -# CONFIG_B44 is not set -# CONFIG_BCMGENET is not set CONFIG_BNX2=y -# CONFIG_CNIC is not set CONFIG_TIGON3=y -CONFIG_TIGON3_HWMON=y -# CONFIG_BNX2X is not set -# CONFIG_SYSTEMPORT is not set -# CONFIG_BNXT is not set -CONFIG_NET_VENDOR_BROCADE=y -# CONFIG_BNA is not set -CONFIG_NET_VENDOR_CADENCE=y -# CONFIG_MACB is not set -CONFIG_NET_VENDOR_CAVIUM=y -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_VF is not set -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_RGX is not set CONFIG_CAVIUM_PTP=y -# CONFIG_LIQUIDIO is not set -# CONFIG_LIQUIDIO_VF is not set -CONFIG_NET_VENDOR_CHELSIO=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -CONFIG_NET_VENDOR_CISCO=y -# CONFIG_ENIC is not set -CONFIG_NET_VENDOR_CORTINA=y -# CONFIG_CX_ECAT is not set -# CONFIG_DNET is not set -CONFIG_NET_VENDOR_DEC=y CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -# CONFIG_TULIP is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_ULI526X is not set -CONFIG_NET_VENDOR_DLINK=y -# CONFIG_DL2K is not set -# CONFIG_SUNDANCE is not set -CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_BE2NET is not set -CONFIG_NET_VENDOR_EZCHIP=y -CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set -CONFIG_NET_VENDOR_HUAWEI=y -# CONFIG_HINIC is not set -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_INTEL=y CONFIG_E100=y CONFIG_E1000=y CONFIG_E1000E=y -CONFIG_E1000E_HWTS=y CONFIG_IGB=y -CONFIG_IGB_HWMON=y CONFIG_IGBVF=y CONFIG_IXGB=y CONFIG_IXGBE=y -CONFIG_IXGBE_HWMON=y -# CONFIG_IXGBEVF is not set CONFIG_I40E=y -# CONFIG_I40EVF is not set -# CONFIG_ICE is not set -# CONFIG_FM10K is not set -# CONFIG_IGC is not set -CONFIG_NET_VENDOR_MICROSOFT=y -# CONFIG_JME is not set -CONFIG_NET_VENDOR_MARVELL=y -# CONFIG_MVMDIO is not set -# CONFIG_SKGE is not set CONFIG_SKY2=y -# CONFIG_SKY2_DEBUG is not set -CONFIG_NET_VENDOR_MELLANOX=y -# CONFIG_MLX4_EN is not set -# CONFIG_MLX5_CORE is not set -# CONFIG_MLXSW_CORE is not set -# CONFIG_MLXFW is not set -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_KSZ884X_PCI is not set -CONFIG_NET_VENDOR_MICROCHIP=y -# CONFIG_LAN743X is not set -CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_NET_VENDOR_MYRI=y -# CONFIG_MYRI10GE is not set -# CONFIG_FEALNX is not set -CONFIG_NET_VENDOR_NATSEMI=y -# CONFIG_NATSEMI is not set -# CONFIG_NS83820 is not set -CONFIG_NET_VENDOR_NETERION=y -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set -CONFIG_NET_VENDOR_NETRONOME=y -# CONFIG_NFP is not set -CONFIG_NET_VENDOR_NI=y -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_8390=y -# CONFIG_NE2K_PCI is not set -CONFIG_NET_VENDOR_NVIDIA=y CONFIG_FORCEDETH=y -CONFIG_NET_VENDOR_OKI=y -# CONFIG_ETHOC is not set -CONFIG_NET_VENDOR_PACKET_ENGINES=y -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_NET_VENDOR_PENSANDO=y -# CONFIG_IONIC is not set -CONFIG_NET_VENDOR_QLOGIC=y -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_QED is not set -CONFIG_NET_VENDOR_QUALCOMM=y -# CONFIG_QCOM_EMAC is not set -# CONFIG_RMNET is not set -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set -CONFIG_NET_VENDOR_REALTEK=y -# CONFIG_ATP is not set CONFIG_8139CP=y CONFIG_8139TOO=y -CONFIG_8139TOO_PIO=y -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set CONFIG_R8169=y -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set -CONFIG_NET_VENDOR_SILAN=y -# CONFIG_SC92031 is not set -CONFIG_NET_VENDOR_SIS=y -# CONFIG_SIS900 is not set -# CONFIG_SIS190 is not set -CONFIG_NET_VENDOR_SMSC=y -# CONFIG_EPIC100 is not set -# CONFIG_SMSC911X is not set -# CONFIG_SMSC9420 is not set -CONFIG_NET_VENDOR_SOCIONEXT=y -CONFIG_NET_VENDOR_STMICRO=y -# CONFIG_STMMAC_ETH is not set -CONFIG_NET_VENDOR_SUN=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NIU is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set -CONFIG_NET_VENDOR_TEHUTI=y -# CONFIG_TEHUTI is not set -CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_PHY_SEL is not set -# CONFIG_TLAN is not set -CONFIG_NET_VENDOR_VIA=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_NET_VENDOR_WIZNET=y CONFIG_WIZNET_W5100=y CONFIG_WIZNET_W5300=y -# CONFIG_WIZNET_BUS_DIRECT is not set -# CONFIG_WIZNET_BUS_INDIRECT is not set -CONFIG_WIZNET_BUS_ANY=y -CONFIG_NET_VENDOR_XILINX=y -# CONFIG_XILINX_EMACLITE is not set -# CONFIG_XILINX_AXI_EMAC is not set -# CONFIG_XILINX_LL_TEMAC is not set CONFIG_FDDI=y -# CONFIG_DEFXX is not set -# CONFIG_SKFP is not set -# CONFIG_HIPPI is not set -# CONFIG_NET_SB1000 is not set -CONFIG_PHYLIB=y -# CONFIG_LED_TRIGGER_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# MII PHY device drivers -# CONFIG_AMD_PHY=y -# CONFIG_ADIN_PHY is not set -# CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BCM54140_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM84881_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CORTINA_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MARVELL_88X2222_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_MICROCHIP_PHY is not set -# CONFIG_MICROCHIP_T1_PHY is not set -# CONFIG_MICROSEMI_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_NXP_C45_TJA11XX_PHY is not set -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_QSEMI_PHY is not set -CONFIG_REALTEK_PHY=y -# CONFIG_RENESAS_PHY is not set -# CONFIG_ROCKCHIP_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_XILINX_GMII2RGMII is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_THUNDER is not set - -# -# MDIO Multiplexers -# - -# -# PCS device drivers -# -# CONFIG_PCS_XPCS is not set -# end of PCS device drivers - -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=m -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set CONFIG_USB_RTL8152=m -# CONFIG_USB_LAN78XX is not set CONFIG_USB_USBNET=m -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_CDC_NCM=m -# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -# CONFIG_USB_NET_CDC_MBIM is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_SR9700 is not set -# CONFIG_USB_NET_SR9800 is not set -# CONFIG_USB_NET_SMSC75XX is not set -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -CONFIG_USB_NET_NET1080=m -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -CONFIG_USB_NET_CDC_SUBSET_ENABLE=m -CONFIG_USB_NET_CDC_SUBSET=m -# CONFIG_USB_ALI_M5632 is not set -# CONFIG_USB_AN2720 is not set -CONFIG_USB_BELKIN=y # CONFIG_USB_ARMLINUX is not set -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_KC2190 is not set # CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_CX82310_ETH is not set -# CONFIG_USB_NET_KALMIA is not set -# CONFIG_USB_NET_QMI_WWAN is not set -# CONFIG_USB_HSO is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_USB_SIERRA_NET is not set -# CONFIG_USB_VL600 is not set -# CONFIG_USB_NET_CH9200 is not set -# CONFIG_USB_NET_AQC111 is not set -# CONFIG_USB_RTL8153_ECM is not set -CONFIG_WLAN=y -CONFIG_WLAN_VENDOR_ADMTEK=y -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATH5K_PCI is not set -CONFIG_WLAN_VENDOR_ATMEL=y -CONFIG_WLAN_VENDOR_BROADCOM=y -CONFIG_WLAN_VENDOR_CISCO=y -CONFIG_WLAN_VENDOR_INTEL=y -CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_PRISM54 is not set -CONFIG_WLAN_VENDOR_MARVELL=y -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_WLAN_VENDOR_MICROCHIP=y -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_WLAN_VENDOR_REALTEK=y -CONFIG_WLAN_VENDOR_RSI=y -CONFIG_WLAN_VENDOR_ST=y -CONFIG_WLAN_VENDOR_TI=y -CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_WLAN_VENDOR_QUANTENNA=y -# CONFIG_WAN is not set -# CONFIG_WWAN is not set -# CONFIG_VMXNET3 is not set -# CONFIG_FUJITSU_ES is not set -# CONFIG_NETDEVSIM is not set -# CONFIG_NET_FAILOVER is not set -# CONFIG_ISDN is not set -# CONFIG_NVM is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y -# CONFIG_INPUT_MATRIXKMAP is not set - -# -# Userland interfaces -# CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1050 is not set -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -CONFIG_MOUSE_PS2_CYPRESS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -# CONFIG_MOUSE_PS2_VMMOUSE is not set -CONFIG_MOUSE_PS2_SMBUS=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set -# CONFIG_RMI4_CORE is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_USERIO is not set -# CONFIG_GAMEPORT is not set -# end of Hardware I/O ports -# end of Input device support - -# -# Character devices -# -CONFIG_TTY=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -CONFIG_LDISC_AUTOLOAD=y - -# -# Serial drivers -# -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SERIAL_8250_16550A_VARIANTS is not set -# CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_DMA=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DWLIB=y -# CONFIG_SERIAL_8250_DW is not set -# CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_LPSS=y # CONFIG_SERIAL_8250_MID is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_KGDB_NMI is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_CONSOLE_POLL=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_LANTIQ is not set -# CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_BCM63XX is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_RP2 is not set -# CONFIG_SERIAL_FSL_LPUART is not set -# CONFIG_SERIAL_FSL_LINFLEXUART is not set -# CONFIG_SERIAL_SPRD is not set -# end of Serial drivers - CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_N_HDLC is not set -# CONFIG_N_GSM is not set -# CONFIG_NOZOMI is not set -# CONFIG_NULL_TTY is not set -# CONFIG_SERIAL_DEV_BUS is not set -# CONFIG_TTY_PRINTK is not set -# CONFIG_PRINTER is not set -# CONFIG_PPDEV is not set -# CONFIG_VIRTIO_CONSOLE is not set -# CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_APPLICOM is not set -# CONFIG_MWAVE is not set -CONFIG_DEVMEM=y -# CONFIG_NVRAM is not set -# CONFIG_RAW_DRIVER is not set -CONFIG_DEVPORT=y -# CONFIG_HPET is not set -# CONFIG_HANGCHECK_TIMER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set -# CONFIG_XILLYBUS is not set -# end of Character devices - -# CONFIG_RANDOM_TRUST_CPU is not set -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_ACPI_I2C_OPREGION=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -# CONFIG_I2C_MUX is not set -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_SMBUS=y -CONFIG_I2C_ALGOBIT=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_AMD_MP2 is not set CONFIG_I2C_I801=y -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_ISMT is not set CONFIG_I2C_PIIX4=m -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - -# -# ACPI drivers -# -# CONFIG_I2C_SCMI is not set - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set -# CONFIG_I2C_EMEV2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_XILINX is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_CP2615 is not set -# CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_MLXCPLD is not set -# end of I2C Hardware Bus support - -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_SLAVE is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# end of I2C support - -# CONFIG_I3C is not set -# CONFIG_SPI is not set -# CONFIG_SPMI is not set -# CONFIG_HSI is not set -CONFIG_PPS=y -# CONFIG_PPS_DEBUG is not set - -# -# PPS clients support -# -# CONFIG_PPS_CLIENT_KTIMER is not set -# CONFIG_PPS_CLIENT_LDISC is not set -# CONFIG_PPS_CLIENT_PARPORT is not set -# CONFIG_PPS_CLIENT_GPIO is not set - -# -# PPS generators support -# - -# -# PTP clock support -# -CONFIG_PTP_1588_CLOCK=y - -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# -CONFIG_PTP_1588_CLOCK_KVM=y -# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set -# CONFIG_PTP_1588_CLOCK_IDTCM is not set -# CONFIG_PTP_1588_CLOCK_VMW is not set -# CONFIG_PTP_1588_CLOCK_OCP is not set -# end of PTP clock support - -CONFIG_PINCTRL=y -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_LYNXPOINT is not set -# CONFIG_PINCTRL_ALDERLAKE is not set -# CONFIG_PINCTRL_BROXTON is not set -# CONFIG_PINCTRL_CANNONLAKE is not set -# CONFIG_PINCTRL_CEDARFORK is not set -# CONFIG_PINCTRL_DENVERTON is not set -# CONFIG_PINCTRL_ELKHARTLAKE is not set -# CONFIG_PINCTRL_EMMITSBURG is not set -# CONFIG_PINCTRL_GEMINILAKE is not set -# CONFIG_PINCTRL_ICELAKE is not set -# CONFIG_PINCTRL_JASPERLAKE is not set -# CONFIG_PINCTRL_LAKEFIELD is not set -# CONFIG_PINCTRL_LEWISBURG is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -# CONFIG_PINCTRL_TIGERLAKE is not set - -# -# Renesas pinctrl drivers -# -# end of Renesas pinctrl drivers - -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -# CONFIG_POWER_RESET is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_POWER_SUPPLY_HWMON=y -# CONFIG_PDA_POWER is not set -# CONFIG_TEST_POWER is not set -# CONFIG_CHARGER_ADP5061 is not set -# CONFIG_BATTERY_CW2015 is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_CHARGER_SBS is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_LTC4162L is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_GOLDFISH is not set -# CONFIG_CHARGER_BD99954 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM1177 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AHT10 is not set -# CONFIG_SENSORS_AS370 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -# CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m -# CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ASPEED is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_CORSAIR_PSU is not set -# CONFIG_SENSORS_DRIVETEMP is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_DS1621 is not set -CONFIG_SENSORS_DELL_SMM=m -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_FSCHMD is not set -# CONFIG_SENSORS_FTSTEUTATES is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_HIH6130 is not set -# CONFIG_SENSORS_I5500 is not set -# CONFIG_SENSORS_CORETEMP is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX127 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31730 is not set -# CONFIG_SENSORS_MAX6621 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_TPS23861 is not set -# CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_NPCM7XX is not set -# CONFIG_SENSORS_NZXT_KRAKEN2 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_PMBUS is not set -# CONFIG_SENSORS_SBTSI is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH5627 is not set -# CONFIG_SENSORS_SCH5636 is not set -# CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP108 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_VIA_CPUTEMP is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83773G is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_XGENE is not set - -# -# ACPI drivers -# -# CONFIG_SENSORS_ACPI_POWER is not set -# CONFIG_SENSORS_ATK0110 is not set -CONFIG_THERMAL=y -# CONFIG_THERMAL_NETLINK is not set -# CONFIG_THERMAL_STATISTICS is not set -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set -CONFIG_THERMAL_GOV_STEP_WISE=y -# CONFIG_THERMAL_GOV_BANG_BANG is not set -CONFIG_THERMAL_GOV_USER_SPACE=y -# CONFIG_THERMAL_EMULATION is not set - -# -# Intel thermal drivers -# -# CONFIG_INTEL_POWERCLAMP is not set -CONFIG_X86_THERMAL_VECTOR=y -CONFIG_X86_PKG_TEMP_THERMAL=m -# CONFIG_INTEL_SOC_DTS_THERMAL is not set - -# -# ACPI INT340X thermal drivers -# -# CONFIG_INT340X_THERMAL is not set -# end of ACPI INT340X thermal drivers - -# CONFIG_INTEL_PCH_THERMAL is not set -# CONFIG_INTEL_TCC_COOLING is not set -# end of Intel thermal drivers - CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_CORE is not set -# CONFIG_WATCHDOG_NOWAYOUT is not set -CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -# CONFIG_WATCHDOG_SYSFS is not set - -# -# Watchdog Pretimeout Governors -# - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_WDAT_WDT is not set -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_ZIIRAVE_WATCHDOG is not set -# CONFIG_CADENCE_WATCHDOG is not set -# CONFIG_DW_WATCHDOG is not set -# CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_ACQUIRE_WDT is not set -# CONFIG_ADVANTECH_WDT is not set -# CONFIG_ALIM1535_WDT is not set -# CONFIG_ALIM7101_WDT is not set -# CONFIG_EBC_C384_WDT is not set -# CONFIG_F71808E_WDT is not set -# CONFIG_SP5100_TCO is not set -# CONFIG_SBC_FITPC2_WATCHDOG is not set -# CONFIG_EUROTECH_WDT is not set -# CONFIG_IB700_WDT is not set -# CONFIG_IBMASR is not set -# CONFIG_WAFER_WDT is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_IE6XX_WDT is not set -# CONFIG_ITCO_WDT is not set -# CONFIG_IT8712F_WDT is not set -# CONFIG_IT87_WDT is not set -# CONFIG_HP_WATCHDOG is not set -# CONFIG_SC1200_WDT is not set -# CONFIG_PC87413_WDT is not set -# CONFIG_NV_TCO is not set -# CONFIG_60XX_WDT is not set -# CONFIG_CPU5_WDT is not set -# CONFIG_SMSC_SCH311X_WDT is not set -# CONFIG_SMSC37B787_WDT is not set -# CONFIG_TQMX86_WDT is not set -# CONFIG_VIA_WDT is not set -# CONFIG_W83627HF_WDT is not set -# CONFIG_W83877F_WDT is not set -# CONFIG_W83977F_WDT is not set -# CONFIG_MACHZ_WDT is not set -# CONFIG_SBC_EPX_C3_WATCHDOG is not set -# CONFIG_NI903X_WDT is not set -# CONFIG_NIC7018_WDT is not set - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set -CONFIG_BCMA_POSSIBLE=y -# CONFIG_BCMA is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_AS3711 is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_MADERA is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MP2629 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -# CONFIG_MFD_INTEL_LPSS_PCI is not set -# CONFIG_MFD_INTEL_PMT is not set -# CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6360 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_MFD_VIPERBOARD is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SYSCON is not set -# CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MFD_ATC260X_I2C is not set -# end of Multifunction device drivers - -# CONFIG_REGULATOR is not set CONFIG_RC_CORE=y -CONFIG_RC_MAP=y -# CONFIG_LIRC is not set CONFIG_RC_DECODERS=y CONFIG_IR_NEC_DECODER=y CONFIG_IR_RC5_DECODER=y @@ -3075,1852 +409,140 @@ CONFIG_IR_SANYO_DECODER=y CONFIG_IR_SHARP_DECODER=y CONFIG_IR_MCE_KBD_DECODER=y CONFIG_IR_XMP_DECODER=y -# CONFIG_IR_IMON_DECODER is not set -# CONFIG_IR_RCMM_DECODER is not set -# CONFIG_RC_DEVICES is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# CONFIG_AGP=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_VIA is not set -CONFIG_INTEL_GTT=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -# CONFIG_VGA_SWITCHEROO is not set CONFIG_DRM=m -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=m -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -# CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_TTM=m -CONFIG_DRM_VRAM_HELPER=m -CONFIG_DRM_TTM_HELPER=m -CONFIG_DRM_SCHED=m - -# -# I2C encoder or helper chips -# -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips - -# -# ARM devices -# -# end of ARM devices - -# CONFIG_DRM_RADEON is not set CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMDGPU_USERPTR=y - -# -# ACP (Audio CoProcessor) Configuration -# -# CONFIG_DRM_AMD_ACP is not set -# end of ACP (Audio CoProcessor) Configuration - -# -# Display Engine Configuration -# -CONFIG_DRM_AMD_DC=y -CONFIG_DRM_AMD_DC_DCN=y -# CONFIG_DRM_AMD_DC_HDCP is not set -# CONFIG_DRM_AMD_DC_SI is not set -# CONFIG_DEBUG_KERNEL_DC is not set -# CONFIG_DRM_AMD_SECURE_DISPLAY is not set -# end of Display Engine Configuration - CONFIG_HSA_AMD=y -CONFIG_HSA_AMD_SVM=y -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_I915 is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_VKMS is not set -# CONFIG_DRM_VMWGFX is not set -# CONFIG_DRM_GMA500 is not set -# CONFIG_DRM_UDL is not set CONFIG_DRM_AST=m -# CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set -# CONFIG_DRM_VIRTIO_GPU is not set -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -# end of Display Panels - -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_PANEL_BRIDGE=y - -# -# Display Interface Bridges -# -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# end of Display Interface Bridges - -# CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_CIRRUS_QEMU is not set -# CONFIG_DRM_GM12U320 is not set -# CONFIG_DRM_SIMPLEDRM is not set -# CONFIG_DRM_VBOXVIDEO is not set -# CONFIG_DRM_GUD is not set -# CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m - -# -# Frame buffer Devices -# -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=m -CONFIG_FB_CFB_COPYAREA=m -CONFIG_FB_CFB_IMAGEBLIT=m -CONFIG_FB_SYS_FILLRECT=m -CONFIG_FB_SYS_COPYAREA=m -CONFIG_FB_SYS_IMAGEBLIT=m -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=m -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ARC is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_VESA is not set -# CONFIG_FB_EFI is not set -# CONFIG_FB_N411 is not set -# CONFIG_FB_HGA is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_LE80578 is not set -# CONFIG_FB_INTEL is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_SIMPLE is not set -# CONFIG_FB_SM712 is not set -# end of Frame buffer Devices - -# -# Backlight & LCD device support -# -# CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_QCOM_WLED is not set -# CONFIG_BACKLIGHT_SAHARA is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set -# end of Backlight & LCD device support - -CONFIG_HDMI=y - -# -# Console display driver support -# -CONFIG_VGA_CONSOLE=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DUMMY_CONSOLE_COLUMNS=80 -CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -# end of Console display driver support - -# CONFIG_LOGO is not set -# end of Graphics support - -# CONFIG_SOUND is not set - -# -# HID support -# -CONFIG_HID=y CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y -# CONFIG_UHID is not set -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# CONFIG_HID_A4TECH=y -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set CONFIG_HID_APPLE=y -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_ASUS is not set -# CONFIG_HID_AUREAL is not set CONFIG_HID_BELKIN=y -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_BIGBEN_FF is not set CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y -# CONFIG_HID_CORSAIR is not set -# CONFIG_HID_COUGAR is not set -# CONFIG_HID_MACALLY is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EMS_FF is not set -# CONFIG_HID_ELAN is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y -# CONFIG_HID_FT260 is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_GLORIOUS is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_VIVALDI is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_JABRA is not set -# CONFIG_HID_TWINHAN is not set CONFIG_HID_KENSINGTON=y -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set CONFIG_HID_LOGITECH=y -# CONFIG_HID_LOGITECH_DJ is not set -# CONFIG_HID_LOGITECH_HIDPP is not set -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -# CONFIG_LOGIG940_FF is not set -# CONFIG_LOGIWHEELS_FF is not set -# CONFIG_HID_MAGICMOUSE is not set -# CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set -# CONFIG_HID_REDRAGON is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y -# CONFIG_HID_PLAYSTATION is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SEMITEK is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_UDRAW_PS3 is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_WIIMOTE is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set -# end of Special HID drivers - -# -# USB HID support -# -CONFIG_USB_HID=y CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y -# end of USB HID support - -# -# I2C HID support -# -# CONFIG_I2C_HID_ACPI is not set -# end of I2C HID support - -# -# Intel ISH HID support -# -# CONFIG_INTEL_ISH_HID is not set -# end of Intel ISH HID support - -# -# AMD SFH HID Support -# -# CONFIG_AMD_SFH_HID is not set -# end of AMD SFH HID Support -# end of HID support - -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y -CONFIG_USB_PCI=y -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_FEW_INIT_RETRIES is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set -CONFIG_USB_AUTOSUSPEND_DELAY=2 -# CONFIG_USB_MON is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DBGCAP is not set -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PCI_RENESAS is not set -# CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_EHCI_PCI=y -# CONFIG_USB_EHCI_FSL is not set CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y -# CONFIG_USB_OHCI_HCD_PLATFORM is not set CONFIG_USB_UHCI_HCD=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HCD_TEST_MODE is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_REALTEK is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_ENE_UB6250 is not set -# CONFIG_USB_UAS is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS_SUPPORT is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_DWC3 is not set -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_CHIPIDEA is not set -# CONFIG_USB_ISP1760 is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_APPLE_MFI_FASTCHARGE is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_EHSET_TEST_FIXTURE is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_YUREX is not set -# CONFIG_USB_EZUSB_FX2 is not set -# CONFIG_USB_HUB_USB251XB is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set -# CONFIG_USB_LINK_LAYER_TEST is not set - -# -# USB Physical Layer drivers -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_USB_ISP1301 is not set -# end of USB Physical Layer drivers - -# CONFIG_USB_GADGET is not set -# CONFIG_TYPEC is not set -# CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set -# CONFIG_LEDS_CLASS_MULTICOLOR is not set -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set - -# -# LED drivers -# -# CONFIG_LEDS_APU is not set -# CONFIG_LEDS_LM3530 is not set -# CONFIG_LEDS_LM3532 is not set -# CONFIG_LEDS_LM3642 is not set -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_CLEVO_MAIL is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_INTEL_SS4200 is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TLC591XX is not set -# CONFIG_LEDS_LM355x is not set - -# -# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -# -# CONFIG_LEDS_BLINKM is not set -# CONFIG_LEDS_MLXCPLD is not set -# CONFIG_LEDS_MLXREG is not set -# CONFIG_LEDS_USER is not set -# CONFIG_LEDS_NIC78BX is not set - -# -# Flash and Torch LED drivers -# - -# -# LED Triggers -# CONFIG_LEDS_TRIGGERS=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_ONESHOT is not set -# CONFIG_LEDS_TRIGGER_DISK is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_CPU is not set -# CONFIG_LEDS_TRIGGER_ACTIVITY is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_LEDS_TRIGGER_TRANSIENT is not set -# CONFIG_LEDS_TRIGGER_CAMERA is not set -# CONFIG_LEDS_TRIGGER_PANIC is not set -# CONFIG_LEDS_TRIGGER_NETDEV is not set -# CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set -# CONFIG_LEDS_TRIGGER_TTY is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set -CONFIG_RTC_NVMEM=y - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_SD3078 is not set - -# -# SPI RTC drivers -# -CONFIG_RTC_I2C_AND_SPI=y - -# -# SPI and I2C RTC drivers -# -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set -# CONFIG_RTC_DRV_RX6110 is not set - -# -# Platform RTC drivers -# -CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_FTRTC010 is not set - -# -# HID Sensor RTC drivers -# -# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ACPI=y -# CONFIG_ALTERA_MSGDMA is not set -# CONFIG_INTEL_IDMA64 is not set -# CONFIG_INTEL_IDXD is not set -# CONFIG_INTEL_IOATDMA is not set -# CONFIG_PLX_DMA is not set -# CONFIG_QCOM_HIDMA_MGMT is not set -# CONFIG_QCOM_HIDMA is not set -CONFIG_DW_DMAC_CORE=y -# CONFIG_DW_DMAC is not set -CONFIG_DW_DMAC_PCI=y -# CONFIG_DW_EDMA is not set -# CONFIG_DW_EDMA_PCIE is not set -# CONFIG_SF_PDMA is not set -# CONFIG_INTEL_LDMA is not set - -# -# DMA Clients -# -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_DMATEST is not set - -# -# DMABUF options -# -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -# CONFIG_UDMABUF is not set -# CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_DEBUG is not set -# CONFIG_DMABUF_SELFTESTS is not set -# CONFIG_DMABUF_HEAPS is not set -# end of DMABUF options - -# CONFIG_AUXDISPLAY is not set -# CONFIG_PANEL is not set -# CONFIG_UIO is not set -# CONFIG_VFIO is not set -# CONFIG_VIRT_DRIVERS is not set -CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTIO_MMIO is not set -# CONFIG_VDPA is not set -CONFIG_VHOST_MENU=y -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set - -# -# Microsoft Hyper-V guest support -# -# CONFIG_HYPERV is not set -# end of Microsoft Hyper-V guest support - -# CONFIG_GREYBUS is not set -# CONFIG_COMEDI is not set -# CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set -CONFIG_PMC_ATOM=y -# CONFIG_CHROME_PLATFORMS is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_SURFACE_PLATFORMS=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_GPE is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_MAX9485 is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_XILINX_VCU is not set -# CONFIG_HWSPINLOCK is not set - -# -# Clock Source drivers -# -CONFIG_CLKEVT_I8253=y -CONFIG_I8253_LOCK=y -CONFIG_CLKBLD_I8253=y -# end of Clock Source drivers - -CONFIG_MAILBOX=y -CONFIG_PCC=y -# CONFIG_ALTERA_MBOX is not set -CONFIG_IOMMU_IOVA=y -CONFIG_IOASID=y -CONFIG_IOMMU_API=y -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -CONFIG_IOMMU_IO_PGTABLE=y -# end of Generic IOMMU Pagetable Support - -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y -CONFIG_AMD_IOMMU_V2=m -CONFIG_DMAR_TABLE=y CONFIG_INTEL_IOMMU=y -# CONFIG_INTEL_IOMMU_SVM is not set -CONFIG_INTEL_IOMMU_DEFAULT_ON=y -CONFIG_INTEL_IOMMU_FLOPPY_WA=y # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set -# CONFIG_IRQ_REMAP is not set - -# -# Remoteproc drivers -# -# CONFIG_REMOTEPROC is not set -# end of Remoteproc drivers - -# -# Rpmsg drivers -# -# CONFIG_RPMSG_QCOM_GLINK_RPM is not set -# CONFIG_RPMSG_VIRTIO is not set -# end of Rpmsg drivers - -# CONFIG_SOUNDWIRE is not set - -# -# SOC (System On Chip) specific Drivers -# - -# -# Amlogic SoC drivers -# -# end of Amlogic SoC drivers - -# -# Broadcom SoC drivers -# -# end of Broadcom SoC drivers - -# -# NXP/Freescale QorIQ SoC drivers -# -# end of NXP/Freescale QorIQ SoC drivers - -# -# i.MX SoC drivers -# -# end of i.MX SoC drivers - -# -# Enable LiteX SoC Builder specific drivers -# -# end of Enable LiteX SoC Builder specific drivers - -# -# Qualcomm SoC drivers -# -# end of Qualcomm SoC drivers - -# CONFIG_SOC_TI is not set - -# -# Xilinx SoC drivers -# -# end of Xilinx SoC drivers -# end of SOC (System On Chip) specific Drivers - -# CONFIG_PM_DEVFREQ is not set -# CONFIG_EXTCON is not set -# CONFIG_MEMORY is not set -# CONFIG_IIO is not set -# CONFIG_NTB is not set -# CONFIG_VME_BUS is not set -# CONFIG_PWM is not set - -# -# IRQ chip support -# -# end of IRQ chip support - -# CONFIG_IPACK_BUS is not set -# CONFIG_RESET_CONTROLLER is not set - -# -# PHY Subsystem -# -# CONFIG_GENERIC_PHY is not set -# CONFIG_USB_LGM_PHY is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_INTEL_LGM_EMMC is not set -# end of PHY Subsystem - -# CONFIG_POWERCAP is not set -# CONFIG_MCB is not set - -# -# Performance monitor support -# -# end of Performance monitor support - -CONFIG_RAS=y -# CONFIG_RAS_CEC is not set -# CONFIG_USB4 is not set - -# -# Android -# -# CONFIG_ANDROID is not set -# end of Android - -# CONFIG_LIBNVDIMM is not set CONFIG_DAX=y -# CONFIG_DEV_DAX is not set -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -# CONFIG_NVMEM_RMEM is not set - -# -# HW tracing support -# -# CONFIG_STM is not set -# CONFIG_INTEL_TH is not set -# end of HW tracing support - -# CONFIG_FPGA is not set -# CONFIG_TEE is not set -# CONFIG_UNISYS_VISORBUS is not set -# CONFIG_SIOX is not set -# CONFIG_SLIMBUS is not set -# CONFIG_INTERCONNECT is not set -# CONFIG_COUNTER is not set -# CONFIG_MOST is not set -# end of Device Drivers - -# -# File systems -# -CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y -CONFIG_FS_IOMAP=y -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT2=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set CONFIG_XFS_FS=y -CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y -# CONFIG_XFS_ONLINE_SCRUB is not set CONFIG_XFS_WARN=y -# CONFIG_XFS_DEBUG is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set -# CONFIG_FS_DAX is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -# CONFIG_EXPORTFS_BLOCK_OPS is not set -CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y -# CONFIG_FS_ENCRYPTION is not set -# CONFIG_FS_VERITY is not set -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -# CONFIG_QUOTA_DEBUG is not set -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m -# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=y -# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set -CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y -# CONFIG_OVERLAY_FS_INDEX is not set -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -# CONFIG_OVERLAY_FS_METACOPY is not set - -# -# Caches -# -CONFIG_NETFS_SUPPORT=y -# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y -# CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set -# CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set -# CONFIG_CACHEFILES is not set -# end of Caches - -# -# CD-ROM/DVD Filesystems -# CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y -# CONFIG_UDF_FS is not set -# end of CD-ROM/DVD Filesystems - -# -# DOS/FAT/EXFAT/NT Filesystems -# -CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_FAT_DEFAULT_UTF8 is not set -# CONFIG_EXFAT_FS is not set CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y -# end of DOS/FAT/EXFAT/NT Filesystems - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y -CONFIG_PROC_VMCORE=y -# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_CHILDREN=y -CONFIG_PROC_PID_ARCH_STATUS=y -CONFIG_KERNFS=y -CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_MEMFD_CREATE=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y # CONFIG_EFIVAR_FS is not set -# end of Pseudo filesystems - -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ORANGEFS_FS is not set -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX6FS_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_PSTORE=y -CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 -CONFIG_PSTORE_DEFLATE_COMPRESS=y -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -# CONFIG_PSTORE_CONSOLE is not set -# CONFIG_PSTORE_PMSG is not set -# CONFIG_PSTORE_FTRACE is not set -# CONFIG_PSTORE_RAM is not set -# CONFIG_PSTORE_BLK is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_EROFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y -CONFIG_NFS_V2=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -# CONFIG_NFS_SWAP is not set -# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y -# CONFIG_NFS_FSCACHE is not set -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -# CONFIG_NFSD is not set -CONFIG_GRACE_PERIOD=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_DEBUG is not set -# CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -CONFIG_CIFS_DEBUG=y -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set -# CONFIG_CIFS_DFS_UPCALL is not set -# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y -# CONFIG_CIFS_ROOT is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set -# CONFIG_UNICODE is not set -CONFIG_IO_WQ=y -# end of File systems - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_REQUEST_CACHE is not set -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set -# CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY=y -CONFIG_SECURITY_WRITABLE_HOOKS=y -# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y -CONFIG_PAGE_TABLE_ISOLATION=y -# CONFIG_SECURITY_NETWORK_XFRM is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_INTEL_TXT is not set -CONFIG_LSM_MMAP_MIN_ADDR=65536 -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -# CONFIG_HARDENED_USERCOPY is not set -# CONFIG_FORTIFY_SOURCE is not set -# CONFIG_STATIC_USERMODEHELPER is not set CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y -CONFIG_SECURITY_SELINUX_DEVELOP=y -CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 -CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 -# CONFIG_SECURITY_SMACK is not set -# CONFIG_SECURITY_TOMOYO is not set -# CONFIG_SECURITY_APPARMOR is not set -# CONFIG_SECURITY_LOADPIN is not set -# CONFIG_SECURITY_YAMA is not set -# CONFIG_SECURITY_SAFESETID is not set -# CONFIG_SECURITY_LOCKDOWN_LSM is not set -# CONFIG_SECURITY_LANDLOCK is not set -CONFIG_INTEGRITY=y -# CONFIG_INTEGRITY_SIGNATURE is not set -CONFIG_INTEGRITY_AUDIT=y -# CONFIG_IMA is not set -# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set -# CONFIG_EVM is not set -CONFIG_DEFAULT_SECURITY_SELINUX=y -# CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" - -# -# Kernel hardening options -# - -# -# Memory initialization -# -CONFIG_INIT_STACK_NONE=y -# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -# end of Memory initialization -# end of Kernel hardening options -# end of Security options - -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_USER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_PCRYPT is not set -# CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=y -# CONFIG_CRYPTO_TEST is not set - -# -# Public-key cryptography -# -CONFIG_CRYPTO_RSA=y -# CONFIG_CRYPTO_DH is not set -# CONFIG_CRYPTO_ECDH is not set -# CONFIG_CRYPTO_ECDSA is not set -# CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set -# CONFIG_CRYPTO_CURVE25519 is not set -# CONFIG_CRYPTO_CURVE25519_X86 is not set - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_GCM=y -# CONFIG_CRYPTO_CHACHA20POLY1305 is not set -# CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y - -# -# Block modes -# CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CFB is not set -CONFIG_CRYPTO_CTR=y -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_OFB is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_KEYWRAP is not set -# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set -# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set -# CONFIG_CRYPTO_ADIANTUM is not set -# CONFIG_CRYPTO_ESSIV is not set - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32C_INTEL is not set -# CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_CRC32_PCLMUL is not set -# CONFIG_CRYPTO_XXHASH is not set -# CONFIG_CRYPTO_BLAKE2B is not set -# CONFIG_CRYPTO_BLAKE2S is not set -# CONFIG_CRYPTO_BLAKE2S_X86 is not set -CONFIG_CRYPTO_CRCT10DIF=y -# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set -CONFIG_CRYPTO_GHASH=y -# CONFIG_CRYPTO_POLY1305 is not set -# CONFIG_CRYPTO_POLY1305_X86_64 is not set CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA1_SSSE3 is not set -# CONFIG_CRYPTO_SHA256_SSSE3 is not set -# CONFIG_CRYPTO_SHA512_SSSE3 is not set -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_SHA3 is not set -# CONFIG_CRYPTO_SM3 is not set -# CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set -# CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_TWOFISH_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set -# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_842 is not set -# CONFIG_CRYPTO_LZ4 is not set -# CONFIG_CRYPTO_LZ4HC is not set -# CONFIG_CRYPTO_ZSTD is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_DRBG_HMAC=y -# CONFIG_CRYPTO_DRBG_HASH is not set -# CONFIG_CRYPTO_DRBG_CTR is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_USER_API_HASH is not set -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_USER_API_AEAD is not set -CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y -# CONFIG_CRYPTO_LIB_BLAKE2S is not set -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_PADLOCK is not set -# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set -# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -# CONFIG_CRYPTO_DEV_CCP is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set -# CONFIG_CRYPTO_DEV_QAT_C62X is not set -# CONFIG_CRYPTO_DEV_QAT_4XXX is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set -# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -# CONFIG_CRYPTO_DEV_SAFEXCEL is not set -# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -CONFIG_ASYMMETRIC_KEY_TYPE=y -CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_X509_CERTIFICATE_PARSER=y -# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set -CONFIG_PKCS7_MESSAGE_PARSER=y -# CONFIG_PKCS7_TEST_KEY is not set -# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set - -# -# Certificates for signature checking -# -CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" -CONFIG_SYSTEM_TRUSTED_KEYRING=y -CONFIG_SYSTEM_TRUSTED_KEYS="" -# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set -# CONFIG_SECONDARY_TRUSTED_KEYRING is not set -# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -# end of Certificates for signature checking - -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -# CONFIG_PACKING is not set -CONFIG_BITREVERSE=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -# CONFIG_CORDIC is not set -# CONFIG_PRIME_NUMBERS is not set -CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_IOMAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -CONFIG_ARCH_USE_SYM_ANNOTATIONS=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC32_SELFTEST is not set -CONFIG_CRC32_SLICEBY8=y -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SARWATE is not set -# CONFIG_CRC32_BIT is not set -# CONFIG_CRC64 is not set -# CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -# CONFIG_CRC8 is not set -CONFIG_XXHASH=y -# CONFIG_RANDOM32_SELFTEST is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DEC=y -CONFIG_XZ_DEC_X86=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_BCJ=y -# CONFIG_XZ_DEC_TEST is not set -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_INTERVAL_TREE=y -CONFIG_XARRAY_MULTI=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_SWIOTLB=y -# CONFIG_DMA_CMA is not set -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_DMA_MAP_BENCHMARK is not set -CONFIG_SGL_ALLOC=y -CONFIG_IOMMU_HELPER=y -CONFIG_CHECK_SIGNATURE=y -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_GLOB=y -# CONFIG_GLOB_SELFTEST is not set -CONFIG_NLATTR=y -CONFIG_CLZ_TAB=y -# CONFIG_IRQ_POLL is not set -CONFIG_MPILIB=y -CONFIG_OID_REGISTRY=y -CONFIG_UCS2_STRING=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_VDSO_TIME_NS=y -CONFIG_FONT_SUPPORT=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_SG_POOL=y -CONFIG_ARCH_HAS_PMEM_API=y -CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_COPY_MC=y -CONFIG_ARCH_STACKWALK=y -CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set -# end of Library routines - -# -# Kernel hacking -# - -# -# printk and dmesg options -# CONFIG_PRINTK_TIME=y -# CONFIG_PRINTK_CALLER is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y -CONFIG_DYNAMIC_DEBUG_CORE=y -CONFIG_SYMBOLIC_ERRNAME=y -CONFIG_DEBUG_BUGVERBOSE=y -# end of printk and dmesg options - -# -# Compile-time checks and compiler options -# -# CONFIG_DEBUG_INFO is not set -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_HEADERS_INSTALL is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set -CONFIG_STACK_VALIDATION=y -# CONFIG_VMLINUX_MAP is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# end of Compile-time checks and compiler options - -# -# Generic Kernel Debugging Instruments -# -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -# CONFIG_DEBUG_FS_ALLOW_NONE is not set -CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB=y -CONFIG_KGDB_HONOUR_BLOCKLIST=y -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set CONFIG_KGDB_LOW_LEVEL_TRAP=y CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y -CONFIG_KDB_CONTINUE_CATASTROPHIC=0 -CONFIG_ARCH_HAS_EARLY_DEBUG=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_HAVE_ARCH_KCSAN=y -# end of Generic Kernel Debugging Instruments - -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_RODATA_TEST=y -CONFIG_ARCH_HAS_DEBUG_WX=y -# CONFIG_DEBUG_WX is not set -CONFIG_GENERIC_PTDUMP=y -# CONFIG_PTDUMP_DEBUGFS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 -# CONFIG_DEBUG_KMEMLEAK_TEST is not set CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y -# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_VM_PGTABLE is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y -# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_KASAN_VMALLOC=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_HAVE_ARCH_KFENCE=y -# CONFIG_KFENCE is not set -# end of Memory Debugging - CONFIG_DEBUG_SHIRQ=y - -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_LOCKUP_DETECTOR=y -CONFIG_SOFTLOCKUP_DETECTOR=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y CONFIG_HARDLOCKUP_DETECTOR=y -# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_TEST_LOCKUP is not set -# end of Debug Oops, Lockups and Hangs - -# -# Scheduler Debugging -# -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -# end of Scheduler Debugging - -# CONFIG_DEBUG_TIMEKEEPING is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y -# CONFIG_PROVE_RAW_LOCK_NESTING is not set -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y -CONFIG_DEBUG_RWSEMS=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_LOCKDEP=y -CONFIG_LOCKDEP_BITS=15 -CONFIG_LOCKDEP_CHAINS_BITS=16 -CONFIG_LOCKDEP_STACK_TRACE_BITS=19 -CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 -CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 -# CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_SCF_TORTURE_TEST is not set -# CONFIG_CSD_LOCK_WAIT_DEBUG is not set -# end of Lock Debugging (spinlocks, mutexes, etc...) - -CONFIG_TRACE_IRQFLAGS=y -CONFIG_TRACE_IRQFLAGS_NMI=y -# CONFIG_DEBUG_IRQFLAGS is not set -CONFIG_STACKTRACE=y -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set - -# -# Debug kernel data structures -# -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# end of Debug kernel data structures - -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -CONFIG_PROVE_RCU=y -# CONFIG_RCU_SCALE_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set -# CONFIG_RCU_EQS_DEBUG is not set -# end of RCU Debugging - -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_LATENCYTOP is not set -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_FENTRY=y -CONFIG_HAVE_OBJTOOL_MCOUNT=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACER_MAX_TRACE=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_PREEMPTIRQ_TRACEPOINTS=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_BOOTTIME_TRACING is not set -CONFIG_FUNCTION_TRACER=y -CONFIG_FUNCTION_GRAPH_TRACER=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_FUNCTION_PROFILER=y CONFIG_STACK_TRACER=y -# CONFIG_IRQSOFF_TRACER is not set CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y -CONFIG_TRACER_SNAPSHOT=y -# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KPROBE_EVENTS=y -# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set -CONFIG_UPROBE_EVENTS=y -CONFIG_BPF_EVENTS=y -CONFIG_DYNAMIC_EVENTS=y -CONFIG_PROBE_EVENTS=y -# CONFIG_BPF_KPROBE_OVERRIDE is not set -CONFIG_FTRACE_MCOUNT_RECORD=y -CONFIG_FTRACE_MCOUNT_USE_CC=y -CONFIG_TRACING_MAP=y -CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y -# CONFIG_TRACE_EVENT_INJECT is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_FTRACE_RECORD_RECURSION is not set -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set -# CONFIG_MMIOTRACE_TEST is not set -# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_SYNTH_EVENT_GEN_TEST is not set -# CONFIG_KPROBE_EVENT_GEN_TEST is not set -# CONFIG_HIST_TRIGGERS_DEBUG is not set -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set - -# -# x86 Debugging -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_EARLY_PRINTK_DBGP is not set -# CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_EFI_PGT_DUMP is not set -# CONFIG_DEBUG_TLBFLUSH is not set -# CONFIG_IOMMU_DEBUG is not set -CONFIG_HAVE_MMIOTRACE_SUPPORT=y -# CONFIG_X86_DECODER_SELFTEST is not set -# CONFIG_IO_DELAY_0X80 is not set CONFIG_IO_DELAY_0XED=y -# CONFIG_IO_DELAY_UDELAY is not set -# CONFIG_IO_DELAY_NONE is not set -# CONFIG_DEBUG_BOOT_PARAMS is not set -# CONFIG_CPA_DEBUG is not set -# CONFIG_DEBUG_ENTRY is not set -# CONFIG_DEBUG_NMI_SELFTEST is not set -CONFIG_X86_DEBUG_FPU=y -# CONFIG_PUNIT_ATOM_DEBUG is not set -CONFIG_UNWINDER_ORC=y -# CONFIG_UNWINDER_FRAME_POINTER is not set -# CONFIG_UNWINDER_GUESS is not set -# end of x86 Debugging - -# -# Kernel Testing and Coverage -# -# CONFIG_KUNIT is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y -# end of Kernel Testing and Coverage -# end of Kernel hacking From f3afd654b7db6af54f5a2a39229d3a21a3a8f594 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 29 Jun 2022 12:43:19 -0500 Subject: [PATCH 0049/2070] x86/configs: Update defconfig with peer-to-peer configs - Update defconfig for PCI_P2PDMA - Update defconfig for DMABUF_MOVE_NOTIFY - Update defconfig for HSA_AMD_P2P Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 406fdfaceb550..0ad80a8c8eab0 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -303,6 +303,7 @@ CONFIG_PCIEAER=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y CONFIG_PCI_IOV=y +CONFIG_PCI_P2PDMA=y CONFIG_HOTPLUG_PCI=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_DMA_ENGINE=y @@ -417,6 +418,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_P2P=y CONFIG_DRM_AST=m CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -453,6 +455,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set CONFIG_DMADEVICES=y +CONFIG_DMABUF_MOVE_NOTIFY=y # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_AMD_IOMMU=y CONFIG_INTEL_IOMMU=y From 2ad09850fae37bc835b6165df9ba2ecf24ecbee4 Mon Sep 17 00:00:00 2001 From: Max Erenberg Date: Tue, 5 Nov 2024 21:36:41 -0500 Subject: [PATCH 0050/2070] x86/configs: add VIRTIO configs to debug rock defconfig These options are necessary to use virtio devices with QEMU. Signed-off-by: Max Erenberg Reviewed-by: Amber Lin --- arch/x86/configs/rock-dbg_defconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 0ad80a8c8eab0..565e447c6230b 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -353,6 +353,20 @@ CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_TUN=y CONFIG_VETH=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MENU=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_9P_FS=y +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y +CONFIG_DRM_VIRTIO_GPU=y CONFIG_ALX=y CONFIG_BNX2=y CONFIG_TIGON3=y From 35230a13b331feb3fd65f2e158b0111efe336192 Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Wed, 17 Dec 2025 18:50:11 +0530 Subject: [PATCH 0051/2070] drm/amd/display: Migrate DCCG register access from hwseq to dccg component. [why] Direct DCCG register access in hwseq layer was creating register conflicts. [how] Migrated DCCG registers from hwseq to dccg component. Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../amd/display/dc/dccg/dcn20/dcn20_dccg.c | 54 ++++++++++++++++++- .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 18 +++++-- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 29 +++------- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 9 ++-- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 ++ 12 files changed, 98 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c index 33d8bd91cb014..50b98822b6fdb 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c @@ -131,6 +131,54 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg) { + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* Hardcoded register values for DCN20 + * These are specific to 100Mhz refclk + * Different ASICs with different refclk may override this in their own init + */ + REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); + REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); + + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); +} + +void dccg2_refclk_setup(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* REFCLK programming that must occur after hubbub initialization */ + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); +} + +bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464; +} + +void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (allow) { + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + } else { + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); + } +} + +void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); } static const struct dccg_funcs dccg2_funcs = { @@ -139,7 +187,11 @@ static const struct dccg_funcs dccg2_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done }; struct dccg *dccg2_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 8bdffd9ff31b1..237a684ded860 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -46,7 +46,9 @@ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\ + SR(DCCG_GATE_DISABLE_CNTL),\ + SR(DCCG_GATE_DISABLE_CNTL2) #define DCCG_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -81,7 +83,8 @@ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ + DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) @@ -130,7 +133,8 @@ type DISPCLK_CHG_FWD_CORR_DISABLE;\ type DISPCLK_FREQ_CHANGE_CNTL;\ type OTG_ADD_PIXEL[MAX_PIPES];\ - type OTG_DROP_PIXEL[MAX_PIPES]; + type OTG_DROP_PIXEL[MAX_PIPES];\ + type DC_MEM_GLOBAL_PWR_REQ_DIS; #define DCCG3_REG_FIELD_LIST(type) \ type HDMICHARCLK0_EN;\ @@ -515,6 +519,14 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg); +void dccg2_refclk_setup(struct dccg *dccg); + +bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg); + +void dccg2_allow_clock_gating(struct dccg *dccg, bool allow); + +void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable); + struct dccg *dccg2_create( struct dc_context *ctx, const struct dccg_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index c1586364ecd45..f89b2f5a9bbd3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -1885,9 +1885,8 @@ void dcn10_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index a76436dcbe401..87a1dc27def4a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -357,26 +357,10 @@ void dcn20_enable_power_gating_plane( void dcn20_dccg_init(struct dce_hwseq *hws) { - /* - * set MICROSECOND_TIME_BASE_DIV - * 100Mhz refclk -> 0x120264 - * 27Mhz refclk -> 0x12021b - * 48Mhz refclk -> 0x120230 - * - */ - REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); + struct dc *dc = hws->ctx->dc; - /* - * set MILLISECOND_TIME_BASE_DIV - * 100Mhz refclk -> 0x1186a0 - * 27Mhz refclk -> 0x106978 - * 48Mhz refclk -> 0x10bb80 - * - */ - REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); - - /* This value is dependent on the hardware pipeline delay so set once per SOC */ - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init) + dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg); } void dcn20_disable_vga( @@ -3155,8 +3139,11 @@ void dcn20_fpga_init_hw(struct dc *dc) REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); - if (REG(REFCLK_CNTL)) - REG_WRITE(REFCLK_CNTL, 0); + + hws->funcs.dccg_init(hws); + + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup) + dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 482053c4ad22a..7cd225a6cf6cb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -364,9 +364,8 @@ void dcn201_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index e2269211553ce..062745389d9a4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -33,6 +33,7 @@ #include "vmid.h" #include "reg_helper.h" #include "hw/clk_mgr.h" +#include "hw/dccg.h" #include "dc_dmub_srv.h" #include "abm.h" #include "link_service.h" @@ -87,12 +88,10 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_ bool dcn21_s0i3_golden_init_wa(struct dc *dc) { - struct dce_hwseq *hws = dc->hwseq; - uint32_t value = 0; + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done) + return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); - value = REG_READ(MICROSECOND_TIME_BASE_DIV); - - return value != 0x00120464; + return false; } void dcn21_exit_optimized_pwr_state( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index c02ddada723fc..3ff15ec9dc17f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -798,9 +798,8 @@ void dcn30_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 2adbcc105aa64..91a672a46289f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -249,9 +249,8 @@ void dcn31_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 3cd44c6602b32..3f76fba7dcccc 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -959,9 +959,8 @@ void dcn32_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index f7e16fee75943..1c7263f9ef51d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -288,7 +288,8 @@ void dcn35_init_hw(struct dc *dc) } if (dc->debug.disable_mem_low_power) { - REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power) + dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false); } if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 86400938abd2e..567ed207d7cd4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -324,9 +324,8 @@ void dcn401_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 1e6ffd86a4c0a..a26d31ab7cba2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -224,6 +224,9 @@ struct dccg_funcs { void (*otg_drop_pixel)(struct dccg *dccg, uint32_t otg_inst); void (*dccg_init)(struct dccg *dccg); + void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */ + void (*allow_clock_gating)(struct dccg *dccg, bool allow); + void (*enable_memory_low_power)(struct dccg *dccg, bool enable); void (*set_dpstreamclk_root_clock_gating)( struct dccg *dccg, int dp_hpo_inst, @@ -334,6 +337,7 @@ struct dccg_funcs { void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable); + bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg); }; #endif //__DAL_DCCG_H__ From d8bd615770e19da4236c05f6262cd9d38a079f06 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 16 Jan 2026 22:17:15 -0500 Subject: [PATCH 0052/2070] drm/amd/display: Add lpddr5 handling to dml2.1 [Why & How] Memory bandwidth calculations work differently than for ddr. Add lpddr5 handling. Reviewed-by: Charlene Liu Signed-off-by: Dmytro Laktyushkin Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../dml21/inc/dml_top_soc_parameter_types.h | 3 + .../src/dml2_core/dml2_core_dcn4_calcs.c | 26 ++++++-- .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 59 ++++++++++++------- .../src/inc/dml2_internal_shared_types.h | 1 + 4 files changed, 64 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h index 1fbc520c25404..c4cce870877a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h @@ -115,9 +115,12 @@ struct dml2_dram_params { unsigned int channel_width_bytes; unsigned int channel_count; unsigned int transactions_per_clock; + bool alt_clock_bw_conversion; }; +#define ENABLE_WCK struct dml2_soc_state_table { + struct dml2_clk_table wck_ratio; struct dml2_clk_table uclk; struct dml2_clk_table fclk; struct dml2_clk_table dcfclk; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 01b87be24ce3d..37699cc9e5c14 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -7077,10 +7077,21 @@ static void calculate_excess_vactive_bandwidth_required( } } -static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config) +static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) { double bw_mbps = 0; - bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; + int i; + + if (!dram_config->alt_clock_bw_conversion) + bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; + else + for (i = 0; i < dram_bw_table->num_entries; i++) + if (dram_bw_table->entries[i].min_uclk_khz >= uclk_khz) { + bw_mbps = (double)dram_bw_table->entries[i].pre_derate_dram_bw_kbps / 1000.0; + break; + } + + ASSERT(bw_mbps > 0); return bw_mbps; } @@ -7964,7 +7975,9 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dispclk / 1000; mode_lib->ms.max_dscclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dscclk / 1000; mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dppclk / 1000; - mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config); + mode_lib->ms.uclk_freq_mhz = (double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz / 1000.0; + if (!mode_lib->ms.uclk_freq_mhz) + mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config); mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps / 1000); mode_lib->ms.max_dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_table.num_entries - 1].pre_derate_dram_bw_kbps / 1000); mode_lib->ms.qos_param_index = get_qos_param_index((unsigned int) (mode_lib->ms.uclk_freq_mhz * 1000.0), mode_lib->soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params); @@ -10407,7 +10420,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex mode_lib->mp.Dcfclk = programming->min_clocks.dcn4x.active.dcfclk_khz / 1000.0; mode_lib->mp.FabricClock = programming->min_clocks.dcn4x.active.fclk_khz / 1000.0; - mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz, &mode_lib->soc.clk_table.dram_config); + mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz, &mode_lib->soc.clk_table.dram_config, &min_clk_table->dram_bw_table); mode_lib->mp.uclk_freq_mhz = programming->min_clocks.dcn4x.active.uclk_khz / 1000.0; mode_lib->mp.GlobalDPPCLK = programming->min_clocks.dcn4x.dpprefclk_khz / 1000.0; s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; @@ -10485,7 +10498,10 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); DML_LOG_VERBOSE("DML::%s: min_clk_index = %0d\n", __func__, in_out_params->min_clk_index); DML_LOG_VERBOSE("DML::%s: min_clk_table min_fclk_khz = %ld\n", __func__, min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_fclk_khz); - DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config)); + if (min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz) + DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz / 1000.0); + else + DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config)); for (k = 0; k < mode_lib->mp.num_active_pipes; ++k) { DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]); DML_LOG_VERBOSE("DML::%s: Per-plane DPPPerSurface[%0d] = %d\n", __func__, k, mode_lib->mp.NoOfDPP[k]); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c index 22969a533a7b5..5c713f2e6eca0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c @@ -7,14 +7,24 @@ #include "dml_top_types.h" #include "lib_float_math.h" -static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config) +static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config, struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) { double uclk_khz = 0; - unsigned long uclk_mbytes_per_tick = 0; - uclk_mbytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; + if (!dram_config->alt_clock_bw_conversion) { + unsigned long uclk_bytes_per_tick = 0; - uclk_khz = (double)bandwidth_kbps / uclk_mbytes_per_tick; + uclk_bytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; + uclk_khz = (double)bandwidth_kbps / uclk_bytes_per_tick; + } else { + int i; + /* For lpddr5 bytes per tick changes with mpstate, use table to find uclk*/ + for (i = 0; i < dram_bw_table->num_entries; i++) + if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) { + uclk_khz = dram_bw_table->entries[i].min_uclk_khz; + break; + } + } return uclk_khz; } @@ -34,7 +44,7 @@ static void get_minimum_clocks_for_latency(struct dml2_dpmm_map_mode_to_soc_dpm_ *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; *uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].pre_derate_dram_bw_kbps, - &in_out->soc_bb->clk_table.dram_config); + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); } static unsigned long dml_round_up(double a) @@ -53,14 +63,18 @@ static void calculate_system_active_minimums(struct dml2_dpmm_map_mode_to_soc_dp double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); if (in_out->display_cfg->display_config.hostvm_enable) - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); else - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -97,11 +111,13 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; /* assumes DF throttling is enabled */ - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -128,11 +144,13 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency); /* assumes DF throttling is disabled */ - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -167,8 +185,9 @@ static void calculate_idle_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_ double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_fclk_avg = (double)mode_support_result->global.active.average_bw_sdp_kbps / in_out->soc_bb->fabric_datapath_to_dcn_data_return_bytes; min_fclk_avg = (double)min_fclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.fclk_derate_percent / 100); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h index 1a6c0727cd2af..a6bd75f30d202 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h @@ -16,6 +16,7 @@ struct dram_bw_to_min_clk_table_entry { unsigned long long pre_derate_dram_bw_kbps; + unsigned long min_uclk_khz; unsigned long min_fclk_khz; unsigned long min_dcfclk_khz; }; From 034796507065718518529940cab9c109f69f4c1b Mon Sep 17 00:00:00 2001 From: Peichen Huang Date: Fri, 9 Jan 2026 17:04:25 +0800 Subject: [PATCH 0053/2070] drm/amd/display: External panel replay fsm control [WHY] To correctly control external panel replay fsm. [HOW] 1. External panel replay is 1-A option only now. 2. Update cursor update and dirty rects commands for external panel replay support. 3. Add external panel replay support flag in dc. Reviewed-by: Robin Chen Signed-off-by: Peichen Huang Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 15 ++++-- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../dc/link/protocols/link_dp_panel_replay.c | 52 +++++++++++++++++++ 5 files changed, 80 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index cb85b7ac2697b..4305691ba45e6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3860,7 +3860,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) return; memset(&cmd, 0x0, sizeof(cmd)); @@ -3880,7 +3880,11 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (srf_updates[i].surface->flip_immediate) continue; - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + if (dc->config.frame_update_cmd_version2) + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + else + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); @@ -3894,6 +3898,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); } } @@ -3916,7 +3921,7 @@ static void build_dmub_update_dirty_rect( if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) return; memset(&cmd, 0x0, sizeof(cmd)); @@ -3935,7 +3940,12 @@ static void build_dmub_update_dirty_rect( /* Do not send in immediate flip mode */ if (srf_updates[i].surface->flip_immediate) continue; - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + + if (dc->config.frame_update_cmd_version2) + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + else + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); @@ -3948,6 +3958,7 @@ static void build_dmub_update_dirty_rect( continue; update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd; dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; (*dmub_cmd_count)++; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ab19b62309450..ce2eceba2ab7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -560,6 +560,7 @@ struct dc_config { bool enable_dpia_pre_training; bool unify_link_enc_assignment; bool enable_cursor_offload; + bool frame_update_cmd_version2; struct spl_sharpness_range dcn_sharpness_range; struct spl_sharpness_range dcn_override_sharpness_range; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index dc1b3f6c22c96..e4dd5ca709877 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1034,12 +1034,19 @@ static void dc_build_cursor_update_payload0( struct pipe_ctx *pipe_ctx, uint8_t p_idx, struct dmub_cmd_update_cursor_payload0 *payload) { + struct dc *dc = pipe_ctx->stream->ctx->dc; struct hubp *hubp = pipe_ctx->plane_res.hubp; unsigned int panel_inst = 0; - if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, - pipe_ctx->stream->link, &panel_inst)) - return; + if (dc->config.frame_update_cmd_version2 == true) { + /* Don't need panel_inst for command version2 */ + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + } else { + if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, + pipe_ctx->stream->link, &panel_inst)) + return; + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + } /* Payload: Cursor Rect is built from position & attribute * x & y are obtained from postion @@ -1052,8 +1059,8 @@ static void dc_build_cursor_update_payload0( payload->enable = hubp->pos.cur_ctl.bits.cur_enable; payload->pipe_idx = p_idx; - payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; payload->panel_inst = panel_inst; + payload->otg_inst = pipe_ctx->stream_res.tg->inst; } static void dc_build_cursor_position_update_payload0( diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 0e953059ff6d8..2e38b6840c711 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1230,7 +1230,7 @@ struct replay_settings { uint32_t replay_desync_error_fail_count; /* The frame skip number dal send to DMUB */ uint16_t frame_skip_number; - /* Current Panel Replay event */ + /* Current Panel Replay events */ uint32_t replay_events; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index bbd6f93f5c981..cc3b44cf76626 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -35,6 +35,46 @@ #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B +static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz) +{ + // at least 2 frames for static screen + unsigned int num_frames = 2; + + // get number of frames for at least 50ms + if (vsync_rate_hz > 40) + num_frames = (vsync_rate_hz + 10) / 20; + + return num_frames; +} + +static void dp_pr_set_static_screen_param(struct dc_link *link) +{ + struct dc_static_screen_params params = {0}; + struct dc *dc = link->ctx->dc; + // only support DP sst for now + if (!dc_is_dp_sst_signal(link->connector_signal)) + return; + + for (int i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream && + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { + struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; + unsigned int vsync_rate_hz = div64_u64(div64_u64( + (stream->timing.pix_clk_100hz * (u64)100), + stream->timing.v_total), + stream->timing.h_total); + + params.triggers.cursor_update = true; + params.triggers.overlay_update = true; + params.triggers.surface_update = true; + params.num_frames = dp_pr_calc_num_static_frames(vsync_rate_hz); + + dc_stream_set_static_screen_params(dc, &stream, 1, ¶ms); + break; + } + } +} + static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) { /* To-do: Setup Replay */ @@ -159,6 +199,9 @@ bool dp_pr_get_panel_inst(const struct dc *dc, if (!dc || !link || !inst_out) return false; + if (dc->config.frame_update_cmd_version2 == false) + return dc_get_edp_link_panel_inst(dc, link, inst_out); + if (!dc_is_dp_sst_signal(link->connector_signal)) /* only supoprt DP sst (eDP included) for now */ return false; @@ -199,6 +242,9 @@ bool dp_pr_enable(struct dc_link *link, bool enable) if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; + if (enable && !dc_is_embedded_signal(link->connector_signal)) + dp_pr_set_static_screen_param(link); + if (link->replay_settings.replay_allow_active != enable) { //for sending PR enable commands to DMUB memset(&cmd, 0, sizeof(cmd)); @@ -276,6 +322,12 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / pipe_ctx->stream->timing.dsc_cfg.num_slices_v; + if (dc_is_embedded_signal(link->connector_signal)) + cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C; + else + // For external DP, use option 1-A + cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A; + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; } From 65a0629a49031eb4994ade5a438cc67678b0107f Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Mon, 19 Jan 2026 16:09:50 -0500 Subject: [PATCH 0054/2070] drm/amd/display: Make DCN35 OTG disable w/a reusable The logic for the OTG disable workaround is particularly complex and should be leveraged going forward instead of reimplementing and maintaining it for multiple ASIC. Reviewed-by: Ovidiu Bunea Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 72558cc55a9a5..7abe6811e4dfa 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -186,7 +186,7 @@ static int dcn35_get_active_display_cnt_wa( return display_count; } -static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, +void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h index a12a9bf90806e..83e2263563fe0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h @@ -64,4 +64,10 @@ void dcn351_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_dcn35 *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg); + +void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower, + bool disable); + #endif //__DCN35_CLK_MGR_H__ From f0986b9a5822a288225810ceebb5f4a1506480c0 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 14 Jan 2026 14:55:38 -0500 Subject: [PATCH 0055/2070] drm/amd/display: Make DSC FGCG a DSC block level function [Why] FGCG shouldn't be called at the DC resource level as part of DSC creation because dc_create is intended for SW init, not HW init, and register access is not guaranteed to work at this phase. [How] Add a set_fgcg function at the DSC interface level. Existing ASIC can continue using the function in DC resource to retain current compatibility but further development should favor calling the function pointer during init_hw (if it exists). Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h index 81c83d5fe0422..ad7ef83694ea1 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h @@ -115,6 +115,7 @@ struct dsc_funcs { void (*dsc_disconnect)(struct display_stream_compressor *dsc); void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc); void (*dsc_get_single_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz); + void (*set_fgcg)(struct display_stream_compressor *dsc, bool enable); }; #endif From ababf771362880bf424890ea96f87e3871ea883b Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 16 Jan 2026 16:49:46 -0500 Subject: [PATCH 0056/2070] drm/amd/display: Make some DCN35 DCCG symbols non-static In order to have few DCN35 functions be leveraged for future ASIC implementations. Expose them to the dcn35_dccg.h header. Reviewed-by: Ovidiu Bunea Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 30 +++++++------------ .../amd/display/dc/dccg/dcn35/dcn35_dccg.h | 17 +++++++++++ 2 files changed, 27 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index bd2f528137b20..838c6617c0294 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1105,7 +1105,7 @@ static void dccg35_enable_dpstreamclk_new(struct dccg *dccg, dccg35_set_dpstreamclk_src_new(dccg, src, inst); } -static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) +void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); uint32_t dispclk_rdivider_value = 0; @@ -1114,6 +1114,7 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) if (dispclk_rdivider_value != 0) REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); } + static void dccg35_wait_for_dentist_change_done( struct dccg *dccg) { @@ -1151,8 +1152,7 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg, } -static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, - int req_dppclk) +void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1498,11 +1498,7 @@ static void dccg35_set_dpstreamclk( __func__, dp_hpo_inst, (src == REFCLK) ? 0 : 1, otg_inst); } - -static void dccg35_set_dpstreamclk_root_clock_gating( - struct dccg *dccg, - int dp_hpo_inst, - bool enable) +void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1669,10 +1665,7 @@ static void dccg35_set_valid_pixel_rate( dccg35_set_dtbclk_dto(dccg, &dto_params); } -static void dccg35_dpp_root_clock_control( - struct dccg *dccg, - unsigned int dpp_inst, - bool clock_on) +void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1704,9 +1697,7 @@ static void dccg35_dpp_root_clock_control( DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on); } -static void dccg35_disable_symclk32_se( - struct dccg *dccg, - int hpo_se_inst) +void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1813,7 +1804,7 @@ void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value) REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); } -static void dccg35_enable_dscclk(struct dccg *dccg, int inst) +void dccg35_enable_dscclk(struct dccg *dccg, int inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1860,8 +1851,7 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) udelay(10); } -static void dccg35_disable_dscclk(struct dccg *dccg, - int inst) +void dccg35_disable_dscclk(struct dccg *dccg, int inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1906,7 +1896,7 @@ static void dccg35_disable_dscclk(struct dccg *dccg, udelay(10); } -static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) +void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -2013,7 +2003,7 @@ static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg * return num_enabled_symclk_fe; } -static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) +void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) { uint8_t num_enabled_symclk_fe = 0; struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h index 7b9c36456cd9b..554700287c1ab 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h @@ -249,8 +249,25 @@ struct dccg *dccg35_create( void dccg35_init(struct dccg *dccg); +void dccg35_trigger_dio_fifo_resync(struct dccg *dccg); + +void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); + void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value); void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); +void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable); + +void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable); + +void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on); + +void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst); + +void dccg35_enable_dscclk(struct dccg *dccg, int inst); +void dccg35_disable_dscclk(struct dccg *dccg, int inst); + +void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); +void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); #endif //__DCN35_DCCG_H__ From 604ca6ffed2dfb06386fa86d7f5acfaf42bbebd5 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 14 Jan 2026 17:20:31 -0700 Subject: [PATCH 0057/2070] drm/amd/display: Fix writeback on DCN 3.2+ [WHAT] 1. Set no scaling for writeback as they are hardcoded in DCN3.2+. 2. Set no fast plane update for writeback commits. Reviewed-by: Harry Wentland Signed-off-by: Alex Hung Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0b4fc654e76f8..56332f3f95ef4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10662,10 +10662,10 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm, wb_info->dwb_params.capture_rate = dwb_capture_rate_0; - wb_info->dwb_params.scaler_taps.h_taps = 4; - wb_info->dwb_params.scaler_taps.v_taps = 4; - wb_info->dwb_params.scaler_taps.h_taps_c = 2; - wb_info->dwb_params.scaler_taps.v_taps_c = 2; + wb_info->dwb_params.scaler_taps.h_taps = 1; + wb_info->dwb_params.scaler_taps.v_taps = 1; + wb_info->dwb_params.scaler_taps.h_taps_c = 1; + wb_info->dwb_params.scaler_taps.v_taps_c = 1; wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; @@ -11681,6 +11681,8 @@ static bool should_reset_plane(struct drm_atomic_state *state, struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; struct amdgpu_device *adev = drm_to_adev(plane->dev); + struct drm_connector_state *new_con_state; + struct drm_connector *connector; int i; /* @@ -11691,6 +11693,15 @@ static bool should_reset_plane(struct drm_atomic_state *state, state->allow_modeset) return true; + /* Check for writeback commit */ + for_each_new_connector_in_state(state, connector, new_con_state, i) { + if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) + continue; + + if (new_con_state->writeback_job) + return true; + } + if (amdgpu_in_reset(adev) && state->allow_modeset) return true; From 52d33eed1eb5c57bfbdda8f152d0a355eeb38e58 Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Tue, 20 Jan 2026 16:29:38 +0800 Subject: [PATCH 0058/2070] drm/amd/display: Fix IGT link training failure on Replay panel [Why] IGT link-training-configs test fails to set the link rate on Replay panels because some link rate types are not supported in debugfs. As a result, debugfs treats these link rates as invalid, causing the IGT test to fail. [How] Add missing link rate types to resolve this issue. Reviewed-by: ChiaHsuan Chung Signed-off-by: Ray Wu Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index b9ed29ec60dc0..5fb573214f18b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -302,8 +302,11 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, switch (param[1]) { case LINK_RATE_LOW: + case LINK_RATE_RATE_2: + case LINK_RATE_RATE_3: case LINK_RATE_HIGH: case LINK_RATE_RBR2: + case LINK_RATE_RATE_6: case LINK_RATE_HIGH2: case LINK_RATE_HIGH3: case LINK_RATE_UHBR10: From 0b00d80e24df1963eb7c0bb5afc0bc06bb316e17 Mon Sep 17 00:00:00 2001 From: Ian Chen Date: Wed, 3 Dec 2025 16:59:07 +0800 Subject: [PATCH 0059/2070] drm/amd/display: Add oem panel config for new features [WHAT] Add oem panel config for below features: - CACP_v2 - Adaptive VariBright - Replay_FrameSkipping - Replay_teamsOpt - Ramless Idle Opt Reviewed-by: Robin Chen Signed-off-by: Ian Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_types.h | 25 ++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2e38b6840c711..bddb16bb76d41 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1256,7 +1256,7 @@ struct dc_panel_config { unsigned int max_nonboost_brightness_millinits; unsigned int min_brightness_millinits; } nits_brightness; - /* PSR */ + /* PSR/Replay */ struct psr { bool disable_psr; bool disallow_psrsu; @@ -1266,6 +1266,8 @@ struct dc_panel_config { bool rc_allow_fullscreen_VPB; bool read_psrcap_again; unsigned int replay_enable_option; + bool enable_frame_skipping; + bool enable_teams_optimization; } psr; /* ABM */ struct varib { @@ -1282,6 +1284,27 @@ struct dc_panel_config { struct ilr { bool optimize_edp_link_rate; /* eDP ILR */ } ilr; + /* Adaptive VariBright*/ + struct adaptive_vb { + bool disable_adaptive_vb; + unsigned int default_abm_vb_levels; // default value = 0xDCAA6414 + unsigned int default_cacp_vb_levels; + unsigned int default_abm_vb_hdr_levels; // default value = 0xB4805A40 + unsigned int default_cacp_vb_hdr_levels; + unsigned int abm_scaling_factors; // default value = 0x23210012 + unsigned int cacp_scaling_factors; + unsigned int battery_life_configures; // default value = 0x0A141E + unsigned int abm_backlight_adaptive_pwl_1; // default value = 0x6A4F7244 + unsigned int abm_backlight_adaptive_pwl_2; // default value = 0x4C615659 + unsigned int abm_backlight_adaptive_pwl_3; // default value = 0x0064 + unsigned int cacp_backlight_adaptive_pwl_1; + unsigned int cacp_backlight_adaptive_pwl_2; + unsigned int cacp_backlight_adaptive_pwl_3; + } adaptive_vb; + /* Ramless Idle Opt*/ + struct rio { + bool disable_rio; + } rio; }; #define MAX_SINKS_PER_LINK 4 From b3c2e063d7b1b079ab24c9baf00ba298a115ffac Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Tue, 20 Jan 2026 16:55:43 +0800 Subject: [PATCH 0060/2070] drm/amd/display: Fix IGT ILR link training failure on Replay panel [Why & How] Fix the IGT ilr_link-training-configs test failure by directly using the supported link rates from DPCD. Reviewed-by: ChiaHsuan Chung Signed-off-by: Ray Wu Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 5fb573214f18b..cfe35442dfcb2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -46,6 +46,7 @@ #include "amdgpu_dm_psr.h" #endif +#define MULTIPLIER_TO_LR 270000 struct dmub_debugfs_trace_header { uint32_t entry_count; uint32_t reserved[3]; @@ -3507,6 +3508,10 @@ static ssize_t edp_ilr_write(struct file *f, const char __user *buf, uint8_t param_nums = 0; long param[2]; bool valid_input = true; + uint8_t supported_link_rates[16] = {0}; + uint32_t entry = 0; + uint32_t link_rate_in_khz = 0; + uint8_t dpcd_rev = 0; if (size == 0) return -EINVAL; @@ -3551,6 +3556,20 @@ static ssize_t edp_ilr_write(struct file *f, const char __user *buf, return size; } + if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, + supported_link_rates, sizeof(supported_link_rates))) + return -EINVAL; + + dpcd_rev = link->dpcd_caps.dpcd_rev.raw; + if (dpcd_rev < DP_DPCD_REV_13 || + (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) { + return size; + } + + entry = param[1] * 2; + link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 + + supported_link_rates[entry]) * 200; + /* save user force lane_count, link_rate to preferred settings * spread spectrum will not be changed */ @@ -3558,7 +3577,7 @@ static ssize_t edp_ilr_write(struct file *f, const char __user *buf, prefer_link_settings.lane_count = param[0]; prefer_link_settings.use_link_rate_set = true; prefer_link_settings.link_rate_set = param[1]; - prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; + prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR; mutex_lock(&adev->dm.dc_lock); dc_link_set_preferred_training_settings(dc, &prefer_link_settings, From 9d7132afa6e81c3b9964ee7c33c8cccbcd185b79 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Tue, 20 Jan 2026 22:40:07 +0000 Subject: [PATCH 0061/2070] drm/amd/display: Fix a NULL pointer dereference in dcn20_hwseq.c [why] hws->funcs.dccg_init is accessed without checking if it is NULL, which may lead to a NULL pointer dereference. [how] Add a NULL check before calling dccg_init. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Wenjing Liu Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 87a1dc27def4a..307e8f8060e6d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -3140,7 +3140,8 @@ void dcn20_fpga_init_hw(struct dc *dc) dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); - hws->funcs.dccg_init(hws); + if (hws->funcs.dccg_init) + hws->funcs.dccg_init(hws); if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup) dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg); From 1b7a819f054b4c1ec7d6f330c66ec779d0d3c818 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Tue, 6 Jan 2026 17:35:51 -0500 Subject: [PATCH 0062/2070] drm/amd/display: Add Gfx Base Case For Linear Tiling Handling [Why] Post-driver cases always use linear tiling yet there is no dedicated Gfx handling for this condition. [How] Add DcGfxBase/DalGfxBase to gfx version enums and set tiling to linear when it is used. Also, enforce the use of proper tiling format as tiling information is used. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Carbones Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 7 +++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ++- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 +++ drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 +++ drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 1 + drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c | 2 ++ drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c | 2 ++ drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c | 2 ++ drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 7 ++++++- .../amd/display/dc/resource/dcn32/dcn32_resource_helpers.c | 3 ++- 13 files changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 56332f3f95ef4..ca40166ca924a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8032,6 +8032,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc, dc_plane_state->plane_size.chroma_size.height = stream->src.height; dc_plane_state->plane_size.chroma_size.width = stream->src.width; dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; + dc_plane_state->tiling_info.gfxversion = DcGfxVersion9; dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; dc_plane_state->rotation = ROTATION_ANGLE_0; dc_plane_state->is_tiling_rotated = false; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4305691ba45e6..441b7e0a3b222 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2768,6 +2768,7 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct case DcGfxVersion7: case DcGfxVersion8: case DcGfxVersionUnknown: + case DcGfxBase: default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 052d573408c3e..a13d9d7dd6c50 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -2065,6 +2065,13 @@ void get_surface_tile_visual_confirm_color( while (bottom_pipe_ctx->bottom_pipe != NULL) bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; + if (bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxBase) { + /* LINEAR Surface - set border color to red */ + color->color_r_cr = color_value; + return; + } + + ASSERT(bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9); switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { case DC_SW_LINEAR: /* LINEAR Surface - set border color to red */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 848c267ef11e7..b4e5a79e97497 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -4434,6 +4434,7 @@ enum dc_status dc_validate_global_state( if (dc->res_pool->funcs->patch_unknown_plane_state && pipe_ctx->plane_state && + pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9 && pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); if (result != DC_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index cfa569a7bff1b..7121629da38ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -342,7 +342,8 @@ enum swizzle_mode_addr3_values { }; enum dc_gfxversion { - DcGfxVersion7 = 0, + DcGfxBase = 0, + DcGfxVersion7, DcGfxVersion8, DcGfxVersion9, DcGfxVersion10, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 1c2009e38aa12..5df58fadc8621 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -100,6 +100,7 @@ static enum mi_bits_per_pixel get_mi_bpp( static enum mi_tiling_format get_mi_tiling( struct dc_tiling_info *tiling_info) { + ASSERT(tiling_info->gfxversion == DcGfxVersion8); switch (tiling_info->gfx8.array_mode) { case DC_ARRAY_1D_TILED_THIN1: case DC_ARRAY_1D_TILED_THICK: @@ -433,6 +434,7 @@ static void program_tiling( struct dce_mem_input *dce_mi, const struct dc_tiling_info *info) { if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ + ASSERT(info->gfxversion == DcGfxVersion9); REG_UPDATE_6(GRPH_CONTROL, GRPH_SW_MODE, info->gfx9.swizzle, GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), @@ -447,6 +449,7 @@ static void program_tiling( } if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */ + ASSERT(info->gfxversion == DcGfxVersion8); REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, GRPH_BANK_WIDTH, info->gfx8.bank_width, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 2c43c24226385..67cfca3361fb9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -165,6 +165,8 @@ static void program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { + ASSERT(info->gfxversion == DcGfxVersion8); + uint32_t value = 0; set_reg_field_value(value, info->gfx8.num_banks, @@ -541,6 +543,7 @@ static const unsigned int *get_dvmm_hw_setting( else bpp = bpp_8; + ASSERT(tiling_info->gfxversion == DcGfxVersion8); switch (tiling_info->gfx8.array_mode) { case DC_ARRAY_1D_TILED_THIN1: case DC_ARRAY_1D_TILED_THICK: diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index 74962791302f6..71eeee02c0fa5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -1006,6 +1006,7 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( pipe->plane_state->format); + ASSERT(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( pipe->plane_state->tiling_info.gfx9.swizzle); v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index 6378e3fd72494..e697d9bf1b44c 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c @@ -145,6 +145,8 @@ void hubp1_program_tiling( { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + ASSERT(info->gfxversion == DcGfxVersion9); + REG_UPDATE_6(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), NUM_BANKS, log_2(info->gfx9.num_banks), diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index 92288de4cc10c..4715e60e812ac 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -313,6 +313,8 @@ static void hubp2_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { + ASSERT(info->gfxversion == DcGfxVersion9); + REG_UPDATE_3(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), PIPE_INTERLEAVE, info->gfx9.pipe_interleave, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 0cc6f45589898..207c2f86b7d78 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -321,6 +321,8 @@ void hubp3_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { + ASSERT(info->gfxversion == DcGfxVersion9); + REG_UPDATE_4(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), PIPE_INTERLEAVE, info->gfx9.pipe_interleave, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index c205500290ecd..861e940250af2 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -589,7 +589,12 @@ void hubp401_program_tiling( * * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default. */ - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); + if (info->gfxversion == DcGfxAddr3) { + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); + } else { + /* linear */ + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, 0); + } } void hubp401_program_size( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index f5a4e97c40ced..7d99f5d79e6dc 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -401,7 +401,8 @@ void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, */ if (pipe_cnt == 1) { pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; - if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { + if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfxversion != DcGfxBase && + !(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9 && pipe->plane_state->tiling_info.gfx9.swizzle == DC_SW_LINEAR)) { if (!is_dual_plane(pipe->plane_state->format)) { pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; pipes[0].pipe.src.unbounded_req_mode = true; From 5d02ea2545162319cfd7b46675d8ec6d8129edcd Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 29 Jan 2026 13:47:22 -0600 Subject: [PATCH 0063/2070] drm/amd: Set minimum version for set_hw_resource_1 on gfx11 to 0x52 commit f81cd793119e7 ("drm/amd/amdgpu: Fix MES init sequence") caused a dependency on new enough MES firmware to use amdgpu. This was fixed on most gfx11 and gfx12 hardware with commit 0180e0a5dd5c6 ("drm/amdgpu/mes: add compatibility checks for set_hw_resource_1"), but this left out that GC 11.0.4 had breakage at MES 0x51. Bump the requirement to 0x52 instead. Cc: stable@vger.kernel.org Reported-by: danijel@nausys.com Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4576 Fixes: f81cd793119e7 ("drm/amd/amdgpu: Fix MES init sequence") Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 81bf9385d55a0..09ebb13ca5e81 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1673,7 +1673,7 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) if (r) goto failure; - if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) { + if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { r = mes_v11_0_set_hw_resources_1(&adev->mes); if (r) { DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); From a3a285f535d61186e6604fca63aa85eb70b72e09 Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Thu, 8 Jan 2026 18:37:57 +0530 Subject: [PATCH 0064/2070] drm/amd/display: Migrate DIO registers access from hwseq to dio component. [why] Direct DIO registers access in hwseq layer was creating register conflicts. [how] Migrated DIO registers from hwseq to dio component. Reviewed-by: Jun Lei Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dio/Makefile | 2 +- .../drm/amd/display/dc/dio/dcn10/dcn10_dio.c | 47 +++++++++++++++++++ .../drm/amd/display/dc/dio/dcn10/dcn10_dio.h | 42 +++++++++++++++++ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 10 ++-- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 10 ++-- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 4 +- .../gpu/drm/amd/display/dc/inc/core_types.h | 2 + drivers/gpu/drm/amd/display/dc/inc/hw/dio.h | 22 +++++++++ .../dc/resource/dcn401/dcn401_resource.c | 41 ++++++++++++++++ 13 files changed, 179 insertions(+), 18 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dio.h diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile b/drivers/gpu/drm/amd/display/dc/dio/Makefile index 0dfd480976f77..02eec03dc2041 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dio/Makefile @@ -27,7 +27,7 @@ ifdef CONFIG_DRM_AMD_DC_FP ############################################################################### # DCN10 ############################################################################### -DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o +DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o dcn10_dio.o AMD_DAL_DIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/dio/dcn10/,$(DIO_DCN10)) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c new file mode 100644 index 0000000000000..edcf4e67483bb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#include "dc_hw_types.h" +#include "dm_services.h" +#include "reg_helper.h" +#include "dcn10_dio.h" + +#define CTX \ + dio10->base.ctx +#define REG(reg)\ + dio10->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + dio10->shifts->field_name, dio10->masks->field_name + +static void dcn10_dio_mem_pwr_ctrl(struct dio *dio, bool enable_i2c_light_sleep) +{ + struct dcn10_dio *dio10 = TO_DCN10_DIO(dio); + + /* power AFMT HDMI memory */ + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (enable_i2c_light_sleep) + REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); +} + +static const struct dio_funcs dcn10_dio_funcs = { + .mem_pwr_ctrl = dcn10_dio_mem_pwr_ctrl, +}; + +void dcn10_dio_construct( + struct dcn10_dio *dio10, + struct dc_context *ctx, + const struct dcn_dio_registers *regs, + const struct dcn_dio_shift *shifts, + const struct dcn_dio_mask *masks) +{ + dio10->base.ctx = ctx; + dio10->base.funcs = &dcn10_dio_funcs; + + dio10->regs = regs; + dio10->shifts = shifts; + dio10->masks = masks; +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h new file mode 100644 index 0000000000000..369c5996326eb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef __DCN10_DIO_H__ +#define __DCN10_DIO_H__ + +#include "dio.h" + +#define TO_DCN10_DIO(dio_base) \ + container_of(dio_base, struct dcn10_dio, base) + +#define DIO_REG_LIST_DCN10()\ + SR(DIO_MEM_PWR_CTRL) + +struct dcn_dio_registers { + uint32_t DIO_MEM_PWR_CTRL; +}; + +struct dcn_dio_shift { + uint8_t I2C_LIGHT_SLEEP_FORCE; +}; + +struct dcn_dio_mask { + uint32_t I2C_LIGHT_SLEEP_FORCE; +}; + +struct dcn10_dio { + struct dio base; + const struct dcn_dio_registers *regs; + const struct dcn_dio_shift *shifts; + const struct dcn_dio_mask *masks; +}; + +void dcn10_dio_construct( + struct dcn10_dio *dio10, + struct dc_context *ctx, + const struct dcn_dio_registers *regs, + const struct dcn_dio_shift *shifts, + const struct dcn_dio_mask *masks); + +#endif /* __DCN10_DIO_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index f89b2f5a9bbd3..5243177c1faad 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -50,6 +50,7 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dsc.h" +#include "dio/dcn10/dcn10_dio.h" #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" @@ -1881,7 +1882,8 @@ void dcn10_init_hw(struct dc *dc) /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ if (!is_optimized_init_done) - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 7cd225a6cf6cb..ce18d75fd9918 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -40,6 +40,8 @@ #include "clk_mgr.h" #include "reg_helper.h" #include "dcn10/dcn10_hubbub.h" +#include "dio/dcn10/dcn10_dio.h" + #define CTX \ hws->ctx @@ -360,7 +362,8 @@ void dcn201_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 3ff15ec9dc17f..d58f2cf2615c0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -53,6 +53,7 @@ #include "dcn30/dcn30_resource.h" #include "link_service.h" #include "dc_state_priv.h" +#include "dio/dcn10/dcn10_dio.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -794,7 +795,8 @@ void dcn30_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 91a672a46289f..db2f7cbb12ff5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -53,6 +53,7 @@ #include "dcn30/dcn30_vpg.h" #include "dce/dce_i2c_hw.h" #include "dce/dmub_abm_lcd.h" +#include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER_INIT(logger) @@ -237,12 +238,9 @@ void dcn31_init_hw(struct dc *dc) abms[i]->funcs->abm_init(abms[i], backlight, user_level); } - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - // Set i2c to light sleep until engine is setup - if (dc->debug.enable_mem_low_power.bits.i2c) - REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); + /* Power on DIO memory (AFMT HDMI) and set I2C to light sleep */ + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, dc->debug.enable_mem_low_power.bits.i2c); if (hws->funcs.setup_hpo_hw_control) hws->funcs.setup_hpo_hw_control(hws, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 3f76fba7dcccc..37300e12e6455 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -52,6 +52,7 @@ #include "link_service.h" #include "../dcn20/dcn20_hwseq.h" #include "dc_state_priv.h" +#include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER_INIT(logger) @@ -955,7 +956,8 @@ void dcn32_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 1c7263f9ef51d..b5a4cefbd35f2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -53,6 +53,7 @@ #include "dcn30/dcn30_vpg.h" #include "dce/dce_i2c_hw.h" #include "dsc.h" +#include "dio/dcn10/dcn10_dio.h" #include "dcn20/dcn20_optc.h" #include "dcn30/dcn30_cm_common.h" #include "dcn31/dcn31_hwseq.h" @@ -272,12 +273,9 @@ void dcn35_init_hw(struct dc *dc) } } - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - // Set i2c to light sleep until engine is setup - if (dc->debug.enable_mem_low_power.bits.i2c) - REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0); + /* Power on DIO memory (AFMT HDMI) and optionally disable I2C light sleep */ + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, !dc->debug.enable_mem_low_power.bits.i2c); if (hws->funcs.setup_hpo_hw_control) hws->funcs.setup_hpo_hw_control(hws, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 567ed207d7cd4..9cda39d0ed95f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -39,6 +39,7 @@ #include "dc_state_priv.h" #include "link_enc_cfg.h" #include "../hw_sequencer.h" +#include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER_INIT(logger) @@ -320,7 +321,8 @@ void dcn401_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 61d8ef759aca9..43579b0e14825 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -35,6 +35,7 @@ #include "hubp.h" #include "mpc.h" #include "dwb.h" +#include "hw/dio.h" #include "mcif_wb.h" #include "panel_cntl.h" #include "dmub/inc/dmub_cmd.h" @@ -250,6 +251,7 @@ struct resource_pool { struct timing_generator *timing_generators[MAX_PIPES]; struct stream_encoder *stream_enc[MAX_PIPES * 2]; struct hubbub *hubbub; + struct dio *dio; struct mpc *mpc; struct pp_smu_funcs *pp_smu; struct dce_aux *engines[MAX_PIPES]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dio.h new file mode 100644 index 0000000000000..532bf54cf2c48 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dio.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef __DC_DIO_H__ +#define __DC_DIO_H__ + +#include "dc_types.h" + +struct dc_context; +struct dio; + +struct dio_funcs { + void (*mem_pwr_ctrl)(struct dio *dio, bool enable_i2c_light_sleep); +}; + +struct dio { + const struct dio_funcs *funcs; + struct dc_context *ctx; +}; + +#endif /* __DC_DIO_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 1cdbb65da4a33..df3acf5895828 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -21,6 +21,7 @@ #include "dcn401/dcn401_hubbub.h" #include "dcn401/dcn401_mpc.h" #include "dcn401/dcn401_hubp.h" +#include "dio/dcn10/dcn10_dio.h" #include "irq/dcn401/irq_service_dcn401.h" #include "dcn401/dcn401_dpp.h" #include "dcn401/dcn401_optc.h" @@ -634,6 +635,22 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; +#define dio_regs_init() \ + DIO_REG_LIST_DCN10() + +static struct dcn_dio_registers dio_regs; + +#define DIO_MASK_SH_LIST_DCN401(mask_sh)\ + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) + +static const struct dcn_dio_shift dio_shift = { + DIO_MASK_SH_LIST_DCN401(__SHIFT) +}; + +static const struct dcn_dio_mask dio_mask = { + DIO_MASK_SH_LIST_DCN401(_MASK) +}; + static const struct resource_caps res_cap_dcn4_01 = { .num_timing_generator = 4, .num_opp = 4, @@ -881,6 +898,22 @@ static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx) return &hubbub2->base; } +static struct dio *dcn401_dio_create(struct dc_context *ctx) +{ + struct dcn10_dio *dio10 = kzalloc(sizeof(struct dcn10_dio), GFP_KERNEL); + + if (!dio10) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT dio_regs + dio_regs_init(); + + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); + + return &dio10->base; +} + static struct hubp *dcn401_hubp_create( struct dc_context *ctx, uint32_t inst) @@ -2071,6 +2104,14 @@ static bool dcn401_resource_construct( goto create_fail; } + /* DIO */ + pool->base.dio = dcn401_dio_create(ctx); + if (pool->base.dio == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dio!\n"); + goto create_fail; + } + /* HUBPs, DPPs, OPPs, TGs, ABMs */ for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { From 271adbd9ed723e367c72ad82d49ab2d8ecd9062a Mon Sep 17 00:00:00 2001 From: Zheng Austin Date: Mon, 19 Jan 2026 17:46:39 -0500 Subject: [PATCH 0065/2070] drm/amd/display: Match expected data types [Why/How] Data types should match what is expected. Update/cast data accordingly. Also change ASSERT to use DML_ASSERT instead Reviewed-by: Dillon Varone Signed-off-by: Zheng Austin Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../src/dml2_core/dml2_core_dcn4_calcs.c | 4 +-- .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 34 +++++++++---------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 37699cc9e5c14..ca5ac3c0deb56 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -7080,7 +7080,7 @@ static void calculate_excess_vactive_bandwidth_required( static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) { double bw_mbps = 0; - int i; + unsigned int i; if (!dram_config->alt_clock_bw_conversion) bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; @@ -7091,7 +7091,7 @@ static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2 break; } - ASSERT(bw_mbps > 0); + DML_ASSERT(bw_mbps > 0); return bw_mbps; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c index 5c713f2e6eca0..9d7741fd0adb1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c @@ -17,7 +17,7 @@ static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const uclk_bytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; uclk_khz = (double)bandwidth_kbps / uclk_bytes_per_tick; } else { - int i; + unsigned int i; /* For lpddr5 bytes per tick changes with mpstate, use table to find uclk*/ for (i = 0; i < dram_bw_table->num_entries; i++) if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) { @@ -63,17 +63,17 @@ static void calculate_system_active_minimums(struct dml2_dpmm_map_mode_to_soc_dp double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100), + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); if (in_out->display_cfg->display_config.hostvm_enable) - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100), + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); else - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100), + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -111,12 +111,12 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; /* assumes DF throttling is enabled */ - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100), + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100), + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -144,12 +144,12 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency); /* assumes DF throttling is disabled */ - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100), + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100), + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -185,8 +185,8 @@ static void calculate_idle_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_ double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps - / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100), + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100)), &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_fclk_avg = (double)mode_support_result->global.active.average_bw_sdp_kbps / in_out->soc_bb->fabric_datapath_to_dcn_data_return_bytes; From c14b33e6514be898a5a6a524aad00a980a06bfb1 Mon Sep 17 00:00:00 2001 From: Chenyu Chen Date: Thu, 22 Jan 2026 17:19:07 +0800 Subject: [PATCH 0066/2070] drm/amd/display: Add CRC 32-bit mode support for DCN3.6+ [Why] DCN 3.6+ hardware supports CRC-32 polynomial in addition to the legacy CRC-16. Enable 32-bit CRC values per color component for improvement of precision in display validation. [How] When userspace sets crc_poly_mode (0=CRC-16, 1=CRC-32) via the debugfs interface, the value is stored in dm_irq_params.crc_poly_mode. When CRC source configuration triggers amdgpu_dm_crtc_configure_crc_source(), crc_poly_mode is retrieved from dm_irq_params and passed to dc_stream_configure_crc(). In the DC layer, dc_stream_configure_crc() sets crc_poly_mode into the crc_params structure and passes it to optc35_configure_crc(). If the hardware supports the OTG_CRC_POLY_SEL register, the register is programmed to select CRC-16 or CRC-32 polynomial. When reading CRC values, optc35_get_crc() checks whether CRC32 register masks are available. If present, it reads 32-bit CRC values from OTG_CRC0/1_DATA_R32/G32/B32 registers; otherwise, it falls back to reading 16-bit CRC values from legacy OTG_CRC0/1_DATA_RG/B registers. Reviewed-by: ChiaHsuan Chung Signed-off-by: Chenyu Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 15 ++- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 46 +++++++++ .../display/amdgpu_dm/amdgpu_dm_irq_params.h | 1 + drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 +- .../amd/display/dc/inc/hw/timing_generator.h | 7 ++ .../amd/display/dc/optc/dcn10/dcn10_optc.h | 19 +++- .../amd/display/dc/optc/dcn35/dcn35_optc.c | 96 ++++++++++++++++++- .../amd/display/dc/optc/dcn35/dcn35_optc.h | 10 ++ .../dc/resource/dcn36/dcn36_resource.c | 12 ++- 10 files changed, 203 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 5851f2d55dde1..1b03f2bf8d7a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -506,6 +506,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct amdgpu_dm_connector *aconnector = NULL; bool enable = amdgpu_dm_is_valid_crc_source(source); int ret = 0; + enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16; /* Configuration will be deferred to stream enable. */ if (!stream_state) @@ -528,10 +529,18 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, amdgpu_dm_replay_disable(stream_state); } + /* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */ + if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && + (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1))) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + crc_poly_mode = acrtc->dm_irq_params.crc_poly_mode; + } + /* Enable or disable CRTC CRC generation */ if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { if (!dc_stream_configure_crc(stream_state->ctx->dc, - stream_state, NULL, enable, enable, 0, true)) { + stream_state, NULL, enable, enable, 0, true, crc_poly_mode)) { ret = -EINVAL; goto unlock; } @@ -877,7 +886,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE) /* update ROI via dm*/ dc_stream_configure_crc(stream_state->ctx->dc, stream_state, - &crc_window, true, true, i, false); + &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode); reset_crc_frame_count[i] = true; @@ -901,7 +910,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE) /* Avoid ROI window get changed, keep overwriting. */ dc_stream_configure_crc(stream_state->ctx->dc, stream_state, - &crc_window, true, true, i, false); + &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode); /* crc ready for psp to read out */ crtc_ctx->crc_info.crc[i].crc_ready = true; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index cfe35442dfcb2..d6d43f1bf6d25 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3839,6 +3839,50 @@ static int crc_win_update_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, crc_win_update_set, "%llu\n"); + +/* + * Trigger to set crc polynomial mode + * 0: 16-bit CRC, 1: 32-bit CRC + * only accepts 0 or 1 for supported hwip versions + */ +static int crc_poly_mode_set(void *data, u64 val) +{ + struct drm_crtc *crtc = data; + struct amdgpu_crtc *acrtc; + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + + if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && + (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) && + (val < 2)) { + acrtc = to_amdgpu_crtc(crtc); + mutex_lock(&adev->dm.dc_lock); + spin_lock_irq(&adev_to_drm(adev)->event_lock); + acrtc->dm_irq_params.crc_poly_mode = val; + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + mutex_unlock(&adev->dm.dc_lock); + } + + return 0; +} + +/* + * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC) + */ +static int crc_poly_mode_get(void *data, u64 *val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + *val = acrtc->dm_irq_params.crc_poly_mode; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get, + crc_poly_mode_set, "%llu\n"); #endif void crtc_debugfs_init(struct drm_crtc *crtc) { @@ -3858,6 +3902,8 @@ void crtc_debugfs_init(struct drm_crtc *crtc) &crc_win_y_end_fops); debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, &crc_win_update_fops); + debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc, + &crc_poly_mode_fops); dput(dir); #endif debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h index 3c9995275cbda..f0c1b0c1faa9f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h @@ -39,6 +39,7 @@ struct dm_irq_params { #ifdef CONFIG_DEBUG_FS enum amdgpu_dm_pipe_crc_source crc_src; + int crc_poly_mode; /* enum crc_poly_mode from timing_generator.h */ #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY struct crc_window_param window_param[MAX_CRC_WINDOW_NUM]; /* At least one CRC window is activated or not*/ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 441b7e0a3b222..e7d2b861dedd0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -701,6 +701,7 @@ dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream, * once. * @idx: Capture CRC on which CRC engine instance * @reset: Reset CRC engine before the configuration + * @crc_poly_mode: CRC polynomial mode * * By default, the entire frame is used to calculate the CRC. * @@ -709,7 +710,7 @@ dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream, */ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, struct crc_params *crc_window, bool enable, bool continuous, - uint8_t idx, bool reset) + uint8_t idx, bool reset, enum crc_poly_mode crc_poly_mode) { struct pipe_ctx *pipe; struct crc_params param; @@ -733,6 +734,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_start = 0; param.windowb_x_end = pipe->stream->timing.h_addressable; param.windowb_y_end = pipe->stream->timing.v_addressable; + param.crc_poly_mode = crc_poly_mode; if (crc_window) { param.windowa_x_start = crc_window->windowa_x_start; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 719b98d8e8ca5..9960494007ffb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -584,7 +584,8 @@ bool dc_stream_configure_crc(struct dc *dc, bool enable, bool continuous, uint8_t idx, - bool reset); + bool reset, + enum crc_poly_mode crc_poly_mode); bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index da7bf59c4b9d1..671ab1fc73207 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -122,6 +122,12 @@ enum timing_synchronization_type { VBLANK_SYNCHRONIZABLE }; +enum crc_poly_mode { + CRC_POLY_MODE_16, + CRC_POLY_MODE_32, + CRC_POLY_MODE_MAX, +}; + struct crc_params { /* Regions used to calculate CRC*/ uint16_t windowa_x_start; @@ -144,6 +150,7 @@ struct crc_params { uint8_t crc_eng_inst; bool reset; + enum crc_poly_mode crc_poly_mode; }; struct dcn_otg_state { diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 803bcc25601c0..0b3f974f452e5 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -244,7 +244,13 @@ uint32_t OTG_TRIGB_MANUAL_TRIG; \ uint32_t OTG_UPDATE_LOCK; \ uint32_t OTG_V_TOTAL_INT_STATUS; \ - uint32_t OTG_VSYNC_NOM_INT_STATUS + uint32_t OTG_VSYNC_NOM_INT_STATUS; \ + uint32_t OTG_CRC0_DATA_R32; \ + uint32_t OTG_CRC0_DATA_G32; \ + uint32_t OTG_CRC0_DATA_B32; \ + uint32_t OTG_CRC1_DATA_R32; \ + uint32_t OTG_CRC1_DATA_G32; \ + uint32_t OTG_CRC1_DATA_B32 struct dcn_optc_registers { @@ -657,6 +663,15 @@ struct dcn_optc_registers { type OTG_V_COUNT_STOP;\ type OTG_V_COUNT_STOP_TIMER; +#define TG_REG_FIELD_LIST_DCN3_6(type) \ + type OTG_CRC_POLY_SEL; \ + type CRC0_R_CR32; \ + type CRC0_G_Y32; \ + type CRC0_B_CB32; \ + type CRC1_R_CR32; \ + type CRC1_G_Y32; \ + type CRC1_B_CB32; + #define TG_REG_FIELD_LIST_DCN401(type) \ type OPTC_SEGMENT_WIDTH_LAST;\ type OTG_PSTATE_KEEPOUT_START;\ @@ -670,6 +685,7 @@ struct dcn_optc_shift { TG_REG_FIELD_LIST_DCN2_0(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) + TG_REG_FIELD_LIST_DCN3_6(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) }; @@ -678,6 +694,7 @@ struct dcn_optc_mask { TG_REG_FIELD_LIST_DCN2_0(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) + TG_REG_FIELD_LIST_DCN3_6(uint32_t) TG_REG_FIELD_LIST_DCN401(uint32_t) }; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index f699e95059f3e..0953acbcc6d45 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -180,6 +180,96 @@ static void optc35_phantom_crtc_post_enable(struct timing_generator *optc) REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); } +/** + * optc35_get_crc - Capture CRC result per component + * + * @optc: timing_generator instance. + * @idx: index of crc engine to get CRC from + * @r_cr: primary CRC signature for red data. + * @g_y: primary CRC signature for green data. + * @b_cb: primary CRC signature for blue data. + * + * This function reads the CRC signature from the OPTC registers. Notice that + * we have three registers to keep the CRC result per color component (RGB). + * + * For different DCN versions: + * - If CRC32 registers (OTG_CRC0_DATA_R32/G32/B32) are available, read from + * 32-bit CRC registers. DCN 3.6+ supports both CRC-32 and CRC-16 polynomials + * selectable via OTG_CRC_POLY_SEL. + * - Otherwise, read from legacy 16-bit CRC registers (OTG_CRC0_DATA_RG/B) + * which only support CRC-16 polynomial. + * + * Returns: + * If CRC is disabled, return false; otherwise, return true, and the CRC + * results in the parameters. + */ +static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx, + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) +{ + uint32_t field = 0; + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + + /* Early return if CRC is not enabled for this CRTC */ + if (!field) + return false; + + if (optc1->tg_mask->CRC0_R_CR32 != 0 && optc1->tg_mask->CRC1_R_CR32 != 0 && + optc1->tg_mask->CRC0_G_Y32 != 0 && optc1->tg_mask->CRC1_G_Y32 != 0 && + optc1->tg_mask->CRC0_B_CB32 != 0 && optc1->tg_mask->CRC1_B_CB32 != 0) { + switch (idx) { + case 0: + /* OTG_CRC0_DATA_R32/G32/B32 has the CRC32 results */ + REG_GET(OTG_CRC0_DATA_R32, + CRC0_R_CR32, r_cr); + REG_GET(OTG_CRC0_DATA_G32, + CRC0_G_Y32, g_y); + REG_GET(OTG_CRC0_DATA_B32, + CRC0_B_CB32, b_cb); + break; + case 1: + /* OTG_CRC1_DATA_R32/G32/B32 has the CRC32 results */ + REG_GET(OTG_CRC1_DATA_R32, + CRC1_R_CR32, r_cr); + REG_GET(OTG_CRC1_DATA_G32, + CRC1_G_Y32, g_y); + REG_GET(OTG_CRC1_DATA_B32, + CRC1_B_CB32, b_cb); + break; + default: + return false; + } + } else { + switch (idx) { + case 0: + /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */ + REG_GET_2(OTG_CRC0_DATA_RG, + CRC0_R_CR, r_cr, + CRC0_G_Y, g_y); + + /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC0_DATA_B, + CRC0_B_CB, b_cb); + break; + case 1: + /* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */ + REG_GET_2(OTG_CRC1_DATA_RG, + CRC1_R_CR, r_cr, + CRC1_G_Y, g_y); + + /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC1_DATA_B, + CRC1_B_CB, b_cb); + break; + default: + return false; + } + } + + return true; +} + static bool optc35_configure_crc(struct timing_generator *optc, const struct crc_params *params) { @@ -266,6 +356,10 @@ static bool optc35_configure_crc(struct timing_generator *optc, default: return false; } + if (optc1->tg_mask->OTG_CRC_POLY_SEL != 0) { + REG_UPDATE(OTG_CRC_CNTL, + OTG_CRC_POLY_SEL, params->crc_poly_mode); + } return true; } @@ -488,7 +582,7 @@ static const struct timing_generator_funcs dcn35_tg_funcs = { .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, .clear_optc_underflow = optc1_clear_optc_underflow, .setup_global_swap_lock = NULL, - .get_crc = optc1_get_crc, + .get_crc = optc35_get_crc, .configure_crc = optc35_configure_crc, .set_dsc_config = optc3_set_dsc_config, .get_dsc_status = optc2_get_dsc_status, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h index 733a2f149d9a9..5c2cb1f277838 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h @@ -74,6 +74,16 @@ SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh) +#define OPTC_COMMON_MASK_SH_LIST_DCN3_6(mask_sh)\ + OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_POLY_SEL, mask_sh),\ + SF(OTG_CRC320_OTG_CRC0_DATA_R32, CRC0_R_CR32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC0_DATA_G32, CRC0_G_Y32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC0_DATA_B32, CRC0_B_CB32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC1_DATA_R32, CRC1_R_CR32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC1_DATA_G32, CRC1_G_Y32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC1_DATA_B32, CRC1_B_CB32, mask_sh) + void dcn35_timing_generator_init(struct optc *optc1); void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 6469d5fe2e6d4..0ee16926db4e2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -460,16 +460,22 @@ static const struct dcn30_mpc_mask mpc_mask = { }; #define optc_regs_init(id)\ - OPTC_COMMON_REG_LIST_DCN3_5_RI(id) + OPTC_COMMON_REG_LIST_DCN3_5_RI(id),\ + SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id) static struct dcn_optc_registers optc_regs[4]; static const struct dcn_optc_shift optc_shift = { - OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) + OPTC_COMMON_MASK_SH_LIST_DCN3_6(__SHIFT) }; static const struct dcn_optc_mask optc_mask = { - OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK) + OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK) }; #define hubp_regs_init(id)\ From 665ca60d9a6f588f1db660c9725c3f5637b214e3 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Wed, 21 Jan 2026 14:24:37 -0500 Subject: [PATCH 0067/2070] drm/amd/display: Init DMUB DPIA Only for APU [why & how] 1. There is no need to init dpia in dgpu 2. Add additional dpia flags a. dpia hpd dynamic control b. consolidated dpia link training to dp c. dynamic bw allocation support Reviewed-by: Roman Li Signed-off-by: Fangzhi Zuo Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ca40166ca924a..631b44fd6dae1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1244,6 +1244,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) struct dmub_srv *dmub_srv = adev->dm.dmub_srv; struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; const struct firmware *dmub_fw = adev->dm.dmub_fw; + struct dc *dc = adev->dm.dc; struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; struct abm *abm = adev->dm.dc->res_pool->abm; struct dc_context *ctx = adev->dm.dc->ctx; @@ -1349,18 +1350,15 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) for (i = 0; i < fb_info->num_fb; ++i) hw_params.fb[i] = &fb_info->fb[i]; - switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { - case IP_VERSION(3, 1, 3): - case IP_VERSION(3, 1, 4): - case IP_VERSION(3, 5, 0): - case IP_VERSION(3, 5, 1): - case IP_VERSION(3, 6, 0): - case IP_VERSION(4, 0, 1): + /* Enable usb4 dpia in the FW APU */ + if (dc->caps.is_apu && + dc->res_pool->usb4_dpia_count != 0 && + !dc->debug.dpia_debug.bits.disable_dpia) { hw_params.dpia_supported = true; - hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; - break; - default: - break; + hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia; + hw_params.dpia_hpd_int_enable_supported = false; + hw_params.enable_non_transparent_setconfig = dc->config.consolidated_dpia_dp_lt; + hw_params.disable_dpia_bw_allocation = !dc->config.usb4_bw_alloc_support; } switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { From 8afb4cce7b282cf662efb1b21eae4af1175c9789 Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Fri, 23 Jan 2026 16:13:01 +0530 Subject: [PATCH 0068/2070] drm/amd/display: DIO memory leak fix. [why] Allocated memory for dcn10_dio but not freed in dcn401_resource. [how] Add kfree for it in dcn401_resource. Reviewed-by: Aric Cyr Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index df3acf5895828..4875faffe8735 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1532,6 +1532,11 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) if (pool->base.dccg != NULL) dcn_dccg_destroy(&pool->base.dccg); + if (pool->base.dio != NULL) { + kfree(TO_DCN10_DIO(pool->base.dio)); + pool->base.dio = NULL; + } + if (pool->base.oem_device != NULL) { struct dc *dc = pool->base.oem_device->ctx->dc; From a78dc0af6ef33c79f903008b2d6f3de2004aece9 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Wed, 7 Jan 2026 09:42:27 -0500 Subject: [PATCH 0069/2070] drm/amd/display: Add Handling for gfxversion DcGfxBase [Why] There is no way to set tiling in dml in the case that gfxversion is DcGfxBase. [How] Where tiling is updated based on Gfx, add case for DcGfxBase and set tiling to dml2_sw_linear. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Carbones Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index bf5e7f4e04167..3f4963ce3a002 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -460,6 +460,9 @@ static void populate_dml21_surface_config_from_plane_state( case DcGfxAddr3: surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); break; + case DcGfxBase: + surface->tiling = dml2_sw_linear; + break; } } From 491ca368183982121602d6ff7c5664c642d71639 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 23 Jan 2026 17:13:14 -0500 Subject: [PATCH 0070/2070] drm/amd/display: [FW Promotion] Release 0.1.45.0 Add new enum definition for panel replay ml activity options. Acked-by: ChiaHsuan Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 18e0bdfd6ff41..3b4f5e990ec5d 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -736,6 +736,16 @@ union pr_hw_flags { uint32_t u32All; }; +/** + * Definition of Panel Replay ML Activity Options + */ +enum pr_ml_activity_option { + OPTION_DEFAULT = 0x00, // VESA Option Default (1C) + OPTION_1A = 0x01, // VESA Option 1A + OPTION_1B = 0x02, // VESA Option 1B + OPTION_1C = 0x03, // VESA Option 1C +}; + union fw_assisted_mclk_switch_version { struct { uint8_t minor : 5; From 780e00f71faa67c0b9d5035a367b7389a9fb8fc3 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 23 Jan 2026 22:39:10 -0500 Subject: [PATCH 0071/2070] drm/amd/display: Promote DC to 3.2.368 This version brings along following fixes: - Migrate DCCG register access from hwseq to dccg component. - Add lpddr5 handling to dml2.1 - Correct external pr fsm control - Make DCN35 OTG disable w/a reusable - Make DSC FGCG a DSC block level function - Make some DCN35 DCCG symbols reusable - Fix writeback on DCN 3.2+ - Fix IGT link training failure on Replay panel - Fix system resume lag issue - Add oem panel config for new features - Fix IGT ILR link training failure on Replay panel - Fix a NULL pointer dereference in dcn20_hwseq.c - Add Gfx Base Case For Linear Tiling Handling - Migrate DIO registers access from hwseq to dio component. - Match expected data types - Add CRC 32-bit mode support for DCN3.6+ - Init DMUB DPIA Only for APU - DIO memory leak fix. - Add Handling for gfxversion DcGfxBase Acked-by: ChiaHsuan Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ce2eceba2ab7c..fdfcfa416d16b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.367" +#define DC_VER "3.2.368" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From e160780f019e5e8ee4a046045a1c473c86044923 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Tue, 20 Jan 2026 19:19:08 +0800 Subject: [PATCH 0072/2070] drm/amdgpu: statistic xgmi training error count Report xgmi training error uncorrectable error count. Change-Id: I4c777fe48807cc164176ad7d98ee500176625a6e Signed-off-by: Stanley.Yang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index aad530c46a9f4..9e32f343097ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -1176,7 +1176,7 @@ static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_ban switch (type) { case ACA_SMU_TYPE_UE: - if (ext_error_code != 0 && ext_error_code != 9) + if (ext_error_code != 0 && ext_error_code != 1 && ext_error_code != 9) count = 0ULL; bank->aca_err_type = ACA_ERROR_TYPE_UE; From e063b76266dc6234da4b46b61812ea3d315424da Mon Sep 17 00:00:00 2001 From: Bert Karwatzki Date: Sun, 1 Feb 2026 01:24:45 +0100 Subject: [PATCH 0073/2070] Revert "drm/amd: Check if ASPM is enabled from PCIe subsystem" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 7294863a6f01248d72b61d38478978d638641bee. This commit was erroneously applied again after commit 0ab5d711ec74 ("drm/amd: Refactor `amdgpu_aspm` to be evaluated per device") removed it, leading to very hard to debug crashes, when used with a system with two AMD GPUs of which only one supports ASPM. Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-acpi/20251006120944.7880-1-spasswolf@web.de/ Link: https://github.com/acpica/acpica/issues/1060 Fixes: 0ab5d711ec74 ("drm/amd: Refactor `amdgpu_aspm` to be evaluated per device") Signed-off-by: Bert Karwatzki Reviewed-by: Christian König Reviewed-by: Mario Limonciello (AMD) (add stable tag) Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index d6d0a6e34c6bf..95d26f086d545 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2405,9 +2405,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, return -ENODEV; } - if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) - amdgpu_aspm = 0; - if (amdgpu_virtual_display || amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) supports_atomic = true; From 83633859edac0454ea7cd12d2bebcd59cafec6f7 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 14:37:34 +0530 Subject: [PATCH 0074/2070] drm/amd/pm: Use feature bits data structure Feature bits are not necessarily restricted to 64-bits. Use smu_feature_bits data structure to represent feature mask for checking DPM status. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 17 ++++++++++ .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 21 +++++++----- .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 16 +++++---- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 26 ++++++++------- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 26 ++++++++------- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 28 +++++++++------- .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 25 ++++++++------ .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 22 ++++++++----- .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 33 ++++++++++--------- .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 28 +++++++++------- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 22 +++++++++---- .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 22 ++++++++----- .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 28 +++++++++------- .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 32 ++++++++++-------- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 18 +++++----- .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 32 ++++++++++-------- 16 files changed, 237 insertions(+), 159 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 7c63c631f6d42..c58290686f0d0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -477,6 +477,23 @@ struct smu_feature_bits { DECLARE_BITMAP(bits, SMU_FEATURE_MAX); }; +/* + * Helpers for initializing smu_feature_bits statically. + * Use SMU_FEATURE_BIT_INIT() which automatically handles array indexing: + * static const struct smu_feature_bits example = { + * .bits = { + * SMU_FEATURE_BIT_INIT(5), + * SMU_FEATURE_BIT_INIT(10), + * SMU_FEATURE_BIT_INIT(65), + * SMU_FEATURE_BIT_INIT(100) + * } + * }; + */ +#define SMU_FEATURE_BITS_ELEM(bit) ((bit) / BITS_PER_LONG) +#define SMU_FEATURE_BITS_POS(bit) ((bit) % BITS_PER_LONG) +#define SMU_FEATURE_BIT_INIT(bit) \ + [SMU_FEATURE_BITS_ELEM(bit)] = (1UL << SMU_FEATURE_BITS_POS(bit)) + enum smu_feature_list { SMU_FEATURE_LIST_SUPPORTED, SMU_FEATURE_LIST_ALLOWED, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index b22a0e91826dc..814f24b7ccc4c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -65,14 +65,15 @@ #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 #define SMU_FEATURES_HIGH_SHIFT 32 -#define SMC_DPM_FEATURE ( \ - FEATURE_DPM_PREFETCHER_MASK | \ - FEATURE_DPM_GFXCLK_MASK | \ - FEATURE_DPM_UCLK_MASK | \ - FEATURE_DPM_SOCCLK_MASK | \ - FEATURE_DPM_MP0CLK_MASK | \ - FEATURE_DPM_FCLK_MASK | \ - FEATURE_DPM_XGMI_MASK) +static const struct smu_feature_bits arcturus_dpm_features = { + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT) } +}; #define smnPCIE_ESM_CTRL 0x111003D0 @@ -1527,12 +1528,14 @@ static bool arcturus_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c index 4a5dcc8936658..406acfbbbc63a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c @@ -60,11 +60,13 @@ static struct gfx_user_settings { static uint32_t cyan_skillfish_sclk_default; -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOC_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits cyan_skillfish_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOC_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping cyan_skillfish_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), @@ -362,6 +364,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; /* we need to re-init after suspend so return false */ if (adev->in_suspend) @@ -378,7 +381,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK, &cyan_skillfish_sclk_default); - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index f14eed0525265..f5be643951084 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -58,16 +58,18 @@ #undef pr_info #undef pr_debug -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) +static const struct smu_feature_bits navi10_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFX_PACE_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT) + } +}; #define SMU_11_0_GFX_BUSY_THRESHOLD 15 @@ -1620,12 +1622,14 @@ static bool navi10_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int navi10_get_fan_speed_rpm(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 98a02fc082143..7d23b6c8c5388 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -60,16 +60,18 @@ #undef pr_info #undef pr_debug -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) +static const struct smu_feature_bits sienna_cichlid_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) + } +}; #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 @@ -1535,12 +1537,14 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&sienna_cichlid_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 4de1778ea6b31..f8b76577d0087 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -58,17 +58,19 @@ #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits vangogh_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), @@ -505,6 +507,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; /* we need to re-init after suspend so return false */ if (adev->in_suspend) @@ -515,7 +518,8 @@ static bool vangogh_is_dpm_running(struct smu_context *smu) if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&vangogh_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 3b6a34644a920..4185c7282a11f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -61,15 +61,18 @@ [smu_feature] = {1, (aldebaran_feature)} #define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ - FEATURE_MASK(FEATURE_DPM_VCN_BIT)) +static const struct smu_feature_bits aldebaran_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATIONS), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN_BIT) + } +}; #define smnPCIE_ESM_CTRL 0x111003D0 @@ -1396,11 +1399,13 @@ static bool aldebaran_is_dpm_running(struct smu_context *smu) { int ret; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&aldebaran_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 9c4298736b289..0856c1c34d7a2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -59,14 +59,16 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) +static const struct smu_feature_bits smu_v13_0_0_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) + } +}; #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 @@ -690,12 +692,14 @@ static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v13_0_0_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int smu_v13_0_0_system_features_control(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 41c61362f7fc2..741762f4bd2cf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -52,24 +52,25 @@ #define mmMP1_SMN_C2PMSG_90 0x029a #define mmMP1_SMN_C2PMSG_90_BASE_IDX 1 -#define FEATURE_MASK(feature) (1ULL << feature) - #define SMU_13_0_4_UMD_PSTATE_GFXCLK 938 #define SMU_13_0_4_UMD_PSTATE_SOCCLK 938 #define SMU_13_0_4_UMD_PSTATE_FCLK 1875 -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \ - FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits smu_v13_0_4_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), @@ -213,13 +214,15 @@ static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v13_0_4_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index e4be727789c00..7311162e50f00 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -51,17 +51,19 @@ #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4) #define mmMP1_C2PMSG_33_BASE_IDX 0 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)) +static const struct smu_feature_bits smu_v13_0_5_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), @@ -231,13 +233,15 @@ static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v13_0_5_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index bd893e95515f8..97866e5701921 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -76,12 +76,18 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin"); [smu_feature] = { 1, (smu_13_0_6_feature) } #define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE \ - (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \ - FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \ - FEATURE_MASK(FEATURE_DPM_VCN)) +static const struct smu_feature_bits smu_v13_0_6_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN) + } +}; #define smnPCIE_ESM_CTRL 0x93D0 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288 @@ -2284,6 +2290,7 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) { int ret; uint64_t feature_enabled; + uint32_t feature_mask[2]; if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) return smu_v13_0_12_is_dpm_running(smu); @@ -2293,7 +2300,8 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v13_0_6_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 415766dbfe6cf..eeff6c874635d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -59,14 +59,16 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) +static const struct smu_feature_bits smu_v13_0_7_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) + } +}; #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 @@ -698,12 +700,14 @@ static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v13_0_7_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 7f70f79c3b2f7..2331dbb9181ab 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -55,17 +55,19 @@ #define SMU_13_0_1_UMD_PSTATE_SOCCLK 678 #define SMU_13_0_1_UMD_PSTATE_FCLK 1800 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits yellow_carp_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), @@ -258,13 +260,15 @@ static bool yellow_carp_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&yellow_carp_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int yellow_carp_post_smu_init(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c index a4e376e8328ce..019e43fdecd63 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c @@ -72,19 +72,21 @@ #define SMU_14_0_4_UMD_PSTATE_GFXCLK 938 #define SMU_14_0_4_UMD_PSTATE_SOCCLK 938 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \ - FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VPE_DPM_BIT)) +static const struct smu_feature_bits smu_v14_0_0_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT) + } +}; enum smu_mall_pg_config { SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0, @@ -471,13 +473,15 @@ static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v14_0_0_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 3c351ee41e684..eb8bad2de1cc2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -56,13 +56,13 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT)) +static const struct smu_feature_bits smu_v14_0_2_dpm_features = { + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT) } +}; #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 #define DEBUGSMC_MSG_Mode1Reset 2 @@ -590,12 +590,14 @@ static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v14_0_2_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index b48444706c1e3..d66e9a1a0ef83 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -70,19 +70,21 @@ #define SMU_15_0_UMD_PSTATE_FCLK 1800 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \ - FEATURE_MASK(FEATURE_NPU_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VPE_DPM_BIT)) +static const struct smu_feature_bits smu_v15_0_0_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_NPU_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT) + } +}; enum smu_mall_pg_config { SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0, @@ -445,13 +447,15 @@ static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; uint64_t feature_enabled; + uint32_t feature_mask[2]; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + smu_feature_bits_to_arr32(&smu_v15_0_0_dpm_features, feature_mask, 64); + return !!(feature_enabled & *(uint64_t *)feature_mask); } static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu, From f316d0bafad90cfe93f972a5b2e877a82569d8f4 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 16:04:06 +0530 Subject: [PATCH 0075/2070] drm/amd/pm: Change get_enabled_mask signature Use smu_feature_bits instead of uint64_t pointer and operate on feature bits. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 +++-- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 9 ++- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 7 +- .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 14 ++-- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 +- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 7 +- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 7 +- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +- .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 20 +++--- .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 11 ++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 7 +- .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 7 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 72 +++++++++---------- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 +- 21 files changed, 123 insertions(+), 117 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 75897ac203c32..797da21e2e5f6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1646,7 +1646,7 @@ static int smu_smc_hw_setup(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; uint8_t pcie_gen = 0, pcie_width = 0; - uint64_t features_supported; + struct smu_feature_bits features_supported; int ret = 0; switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { @@ -1807,7 +1807,7 @@ static int smu_smc_hw_setup(struct smu_context *smu) return ret; } smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, - (unsigned long *)&features_supported); + features_supported.bits); if (!smu_is_dpm_running(smu)) dev_info(adev->dev, "dpm has been disabled\n"); @@ -3152,10 +3152,19 @@ static int smu_read_sensor(void *handle, *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; *size = 4; break; - case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: - ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); + case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { + struct smu_feature_bits feature_mask; + uint32_t features[2]; + + /* TBD: need to handle for > 64 bits */ + ret = smu_feature_get_enabled_mask(smu, &feature_mask); + if (!ret) { + smu_feature_bits_to_arr32(&feature_mask, features, 64); + *(uint64_t *)data = *(uint64_t *)features; + } *size = 8; break; + } case AMDGPU_PP_SENSOR_UVD_POWER: *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; *size = 4; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index c58290686f0d0..4019ef8595040 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1229,7 +1229,8 @@ struct pptable_funcs { * on the SMU. * &feature_mask: Enabled feature mask. */ - int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); + int (*get_enabled_mask)(struct smu_context *smu, + struct smu_feature_bits *feature_mask); /** * @feature_is_enabled: Test if a feature is enabled. @@ -2061,6 +2062,12 @@ static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits, return bitmap_empty(bits->bits, nbits); } +static inline bool smu_feature_bits_full(const struct smu_feature_bits *bits, + unsigned int nbits) +{ + return bitmap_full(bits->bits, nbits); +} + static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, const unsigned long *src, unsigned int nbits) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 814f24b7ccc4c..0c4afd1e1aab0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -1527,15 +1527,14 @@ static int arcturus_set_performance_level(struct smu_context *smu, static bool arcturus_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + arcturus_dpm_features.bits); } static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c index 406acfbbbc63a..87953a4d0a433 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c @@ -363,8 +363,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; /* we need to re-init after suspend so return false */ if (adev->in_suspend) @@ -381,8 +380,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK, &cyan_skillfish_sclk_default); - smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + cyan_skillfish_dpm_features.bits); } static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu, @@ -569,12 +568,13 @@ static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu, return 0; } -static int cyan_skillfish_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) +static int +cyan_skillfish_get_enabled_mask(struct smu_context *smu, + struct smu_feature_bits *feature_mask) { if (!feature_mask) return -EINVAL; - memset(feature_mask, 0xff, sizeof(*feature_mask)); + smu_feature_bits_fill(feature_mask); return 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index f5be643951084..737bfdfb814c5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1621,15 +1621,14 @@ static int navi10_display_config_changed(struct smu_context *smu) static bool navi10_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + navi10_dpm_features.bits); } static int navi10_get_fan_speed_rpm(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 7d23b6c8c5388..6268bc5ed3e68 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1536,15 +1536,14 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu) static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&sienna_cichlid_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + sienna_cichlid_dpm_features.bits); } static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index f8b76577d0087..08179840697e1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -506,8 +506,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; /* we need to re-init after suspend so return false */ if (adev->in_suspend) @@ -518,8 +517,8 @@ static bool vangogh_is_dpm_running(struct smu_context *smu) if (ret) return false; - smu_feature_bits_to_arr32(&vangogh_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + vangogh_dpm_features.bits); } static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 5346b60b09b98..31e21ff8859a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -1434,11 +1434,11 @@ static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) } static int renoir_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { if (!feature_mask) return -EINVAL; - memset(feature_mask, 0xff, sizeof(*feature_mask)); + smu_feature_bits_fill(feature_mask); return 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 4185c7282a11f..ad23682217eeb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1398,14 +1398,13 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ static bool aldebaran_is_dpm_running(struct smu_context *smu) { int ret; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&aldebaran_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + aldebaran_dpm_features.bits); } static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 0856c1c34d7a2..de770c10da3d6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -691,15 +691,14 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v13_0_0_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_0_dpm_features.bits); } static int smu_v13_0_0_system_features_control(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 9a34e5460b35a..3d60d3c1e5858 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -52,10 +52,13 @@ #define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \ [smu_feature] = { 1, (smu_13_0_12_feature) } -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE \ - (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK)) +static const struct smu_feature_bits smu_v13_0_12_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK) + } +}; #define NUM_JPEG_RINGS_FW 10 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \ @@ -199,14 +202,14 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu) } static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { int ret; ret = smu_cmn_get_enabled_mask(smu, feature_mask); if (ret == -EIO) { - *feature_mask = 0; + smu_feature_bits_clearall(feature_mask); ret = 0; } @@ -372,14 +375,15 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) bool smu_v13_0_12_is_dpm_running(struct smu_context *smu) { int ret; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_12_dpm_features.bits); } int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 741762f4bd2cf..75b90ac0c29c5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -213,16 +213,15 @@ static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v13_0_4_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_4_dpm_features.bits); } static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index 7311162e50f00..8ee5002e3d6b2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -232,16 +232,15 @@ static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v13_0_5_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_5_dpm_features.bits); } static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 97866e5701921..be7d77eee2b07 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2272,14 +2272,14 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, } static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { int ret; ret = smu_cmn_get_enabled_mask(smu, feature_mask); if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) { - *feature_mask = 0; + smu_feature_bits_clearall(feature_mask); ret = 0; } @@ -2289,8 +2289,7 @@ static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu, static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) { int ret; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) return smu_v13_0_12_is_dpm_running(smu); @@ -2300,8 +2299,8 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) if (ret) return false; - smu_feature_bits_to_arr32(&smu_v13_0_6_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_6_dpm_features.bits); } static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index eeff6c874635d..fe3d6bfe68121 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -699,15 +699,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v13_0_7_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_7_dpm_features.bits); } static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 2331dbb9181ab..f9789b1fcbf83 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -259,16 +259,15 @@ static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) static bool yellow_carp_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&yellow_carp_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + yellow_carp_dpm_features.bits); } static int yellow_carp_post_smu_init(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c index 019e43fdecd63..dbdf7653cc534 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c @@ -472,16 +472,15 @@ static int smu_v14_0_0_read_sensor(struct smu_context *smu, static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v14_0_0_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v14_0_0_dpm_features.bits); } static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index eb8bad2de1cc2..becfd356b4e71 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -589,15 +589,14 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v14_0_2_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v14_0_2_dpm_features.bits); } static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index d66e9a1a0ef83..c3f22844ba2f1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -446,16 +446,15 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu, static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; - uint32_t feature_mask[2]; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - smu_feature_bits_to_arr32(&smu_v15_0_0_dpm_features, feature_mask, 64); - return !!(feature_enabled & *(uint64_t *)feature_mask); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v15_0_0_dpm_features.bits); } static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 9bb7e3760c0ff..a9e0b52bc739d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -690,7 +690,7 @@ int smu_cmn_feature_is_supported(struct smu_context *smu, } static int __smu_get_enabled_features(struct smu_context *smu, - uint64_t *enabled_features) + struct smu_feature_bits *enabled_features) { return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features); } @@ -699,7 +699,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask) { struct amdgpu_device *adev = smu->adev; - uint64_t enabled_features; + struct smu_feature_bits enabled_features; int feature_id; if (__smu_get_enabled_features(smu, &enabled_features)) { @@ -712,7 +712,8 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu, * enabled. Also considering they have no feature_map available, the * check here can avoid unwanted feature_map check below. */ - if (enabled_features == ULLONG_MAX) + if (smu_feature_bits_full(&enabled_features, + smu->smu_feature.feature_num)) return 1; feature_id = smu_cmn_to_asic_specific_index(smu, @@ -721,7 +722,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu, if (feature_id < 0) return 0; - return test_bit(feature_id, (unsigned long *)&enabled_features); + return smu_feature_bits_is_set(&enabled_features, feature_id); } bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, @@ -763,45 +764,38 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, } int smu_cmn_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { - uint32_t *feature_mask_high; - uint32_t *feature_mask_low; + uint32_t features[2]; int ret = 0, index = 0; if (!feature_mask) return -EINVAL; - feature_mask_low = &((uint32_t *)feature_mask)[0]; - feature_mask_high = &((uint32_t *)feature_mask)[1]; - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetEnabledSmuFeatures); if (index > 0) { - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_GetEnabledSmuFeatures, - 0, - feature_mask_low); + ret = smu_cmn_send_smc_msg_with_param( + smu, SMU_MSG_GetEnabledSmuFeatures, 0, &features[0]); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_GetEnabledSmuFeatures, - 1, - feature_mask_high); + ret = smu_cmn_send_smc_msg_with_param( + smu, SMU_MSG_GetEnabledSmuFeatures, 1, &features[1]); } else { - ret = smu_cmn_send_smc_msg(smu, - SMU_MSG_GetEnabledSmuFeaturesHigh, - feature_mask_high); + ret = smu_cmn_send_smc_msg( + smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &features[1]); if (ret) return ret; - ret = smu_cmn_send_smc_msg(smu, - SMU_MSG_GetEnabledSmuFeaturesLow, - feature_mask_low); + ret = smu_cmn_send_smc_msg( + smu, SMU_MSG_GetEnabledSmuFeaturesLow, &features[0]); } + if (!ret) + smu_feature_bits_from_arr32(feature_mask, features, 64); + return ret; } @@ -886,7 +880,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, char *buf) { int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; - uint64_t feature_mask; + struct smu_feature_bits feature_mask; + uint32_t features[2]; int i, feature_index; uint32_t count = 0; size_t size = 0; @@ -894,8 +889,10 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, if (__smu_get_enabled_features(smu, &feature_mask)) return 0; - size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", - upper_32_bits(feature_mask), lower_32_bits(feature_mask)); + /* TBD: Need to handle for > 64 bits */ + smu_feature_bits_to_arr32(&feature_mask, features, 64); + size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", + features[1], features[0]); memset(sort_feature, -1, sizeof(sort_feature)); @@ -916,12 +913,13 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, if (sort_feature[feature_index] < 0) continue; - size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n", - count++, - smu_get_feature_name(smu, sort_feature[feature_index]), - feature_index, - !!test_bit(feature_index, (unsigned long *)&feature_mask) ? - "enabled" : "disabled"); + size += sysfs_emit_at( + buf, size, "%02d. %-20s (%2d) : %s\n", count++, + smu_get_feature_name(smu, sort_feature[feature_index]), + feature_index, + smu_feature_bits_is_set(&feature_mask, feature_index) ? + "enabled" : + "disabled"); } return size; @@ -931,7 +929,8 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) { int ret = 0; - uint64_t feature_mask; + struct smu_feature_bits feature_mask; + uint64_t feature_mask_u64; uint64_t feature_2_enabled = 0; uint64_t feature_2_disabled = 0; @@ -939,8 +938,9 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, if (ret) return ret; - feature_2_enabled = ~feature_mask & new_mask; - feature_2_disabled = feature_mask & ~new_mask; + feature_mask_u64 = *(uint64_t *)feature_mask.bits; + feature_2_enabled = ~feature_mask_u64 & new_mask; + feature_2_disabled = feature_mask_u64 & ~new_mask; if (feature_2_enabled) { ret = smu_cmn_feature_update_enable_state(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index 92ad2ece7a363..b7bfddc65fb21 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -141,7 +141,7 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); int smu_cmn_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask); + struct smu_feature_bits *feature_mask); uint64_t smu_cmn_get_indep_throttler_status( const unsigned long dep_status, From 41cd95e90361b9ce6d8597ab278ad4a6e54a2e96 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 18:32:19 +0530 Subject: [PATCH 0076/2070] drm/amd/pm: Add default feature number definition The number of default features could be different from the actual width of the bitmap. Use a different definition for it. Also increase the max width of bitmap to 128. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 ++- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 ++++-- 7 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 797da21e2e5f6..9f52b7b241982 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1355,7 +1355,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) int i, ret; smu->pool_size = adev->pm.smu_prv_buffer_size; - smu_feature_init(smu, SMU_FEATURE_MAX); + smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 4019ef8595040..512493a8452b3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -471,7 +471,8 @@ struct smu_power_context { struct smu_power_gate power_gate; }; -#define SMU_FEATURE_MAX (64) +#define SMU_FEATURE_NUM_DEFAULT (64) +#define SMU_FEATURE_MAX (128) struct smu_feature_bits { DECLARE_BITMAP(bits, SMU_FEATURE_MAX); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 1d0f9f8ddf9b5..56efcfa327dfd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -751,7 +751,7 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) uint32_t feature_mask[2]; if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || - feature->feature_num < 64) { + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) { ret = -EINVAL; goto failed; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 3b0aa6a2e78ed..63a65ea802fd5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -762,7 +762,7 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu) uint32_t feature_mask[2]; if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || - feature->feature_num < 64) + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) return -EINVAL; smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index cabbd234c6e2c..7dc6687c3693b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -747,7 +747,7 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu) uint32_t feature_mask[2]; if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || - feature->feature_num < 64) + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) return -EINVAL; smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index d77eaac556d9b..a2854d528bab5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -716,7 +716,7 @@ int smu_v15_0_set_allowed_mask(struct smu_context *smu) uint32_t feature_mask[2]; if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || - feature->feature_num < 64) + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) return -EINVAL; smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index a9e0b52bc739d..6fd50c2fd20e0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -794,7 +794,8 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu, } if (!ret) - smu_feature_bits_from_arr32(feature_mask, features, 64); + smu_feature_bits_from_arr32(feature_mask, features, + SMU_FEATURE_NUM_DEFAULT); return ret; } @@ -909,7 +910,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n", "No", "Feature", "Bit", "State"); - for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) { + for (feature_index = 0; feature_index < smu->smu_feature.feature_num; + feature_index++) { if (sort_feature[feature_index] < 0) continue; From a1cba36f9229d2c82f9bb9ea52d5623401a5f900 Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Wed, 21 Jan 2026 16:27:46 +0800 Subject: [PATCH 0077/2070] drm/amdgpu/psp_v15_0_8: Add get ras capability Add get ras capability for psp 15.0.8. v2:Remove APU type check and IP version check. Signed-off-by: Jinzhou Su Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c index 5249f5bd2a10e..b2d7cbd894c03 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c @@ -187,6 +187,26 @@ static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value) WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); } +static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + u32 reg_data; + + /* query ras cap should be done from host side */ + if (amdgpu_sriov_vf(adev)) + return false; + + if (!con) + return false; + + reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127); + adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); + con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; + + return true; +} + static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) { @@ -334,6 +354,7 @@ static const struct psp_funcs psp_v15_0_8_funcs = { .ring_get_wptr = psp_v15_0_8_ring_get_wptr, .ring_set_wptr = psp_v15_0_8_ring_set_wptr, .get_fw_type = psp_v15_0_8_get_fw_type, + .get_ras_capability = psp_v15_0_8_get_ras_capability, }; void psp_v15_0_8_set_psp_funcs(struct psp_context *psp) From 46e34112d2553459433ad926ec6d2652d7cd129e Mon Sep 17 00:00:00 2001 From: Andrew Martin Date: Tue, 11 Nov 2025 16:43:45 -0500 Subject: [PATCH 0078/2070] drm/amdgpu: Ignored various return code The return code of a non void function should not be ignored. In cases where we do not care, the code needs to suppress it. Signed-off-by: Andrew Martin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 8 +++----- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++++++-- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 9 +++++---- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 877d0df50376a..3bfd79c89df32 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -317,8 +317,7 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) { if (amdgpu_device_should_recover_gpu(adev)) - amdgpu_reset_domain_schedule(adev->reset_domain, - &adev->kfd.reset_work); + (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work); } int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, @@ -720,9 +719,8 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) if (gfx_block != NULL) gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); } - amdgpu_dpm_switch_power_profile(adev, - PP_SMC_POWER_PROFILE_COMPUTE, - !idle); + (void)amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle); + } bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 88621cb7d4098..732ad1224a619 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2804,8 +2804,12 @@ static int runtime_enable(struct kfd_process *p, uint64_t r_debug, * SET_SHADER_DEBUGGER clears any stale process context data * saved in MES. */ - if (pdd->dev->kfd->shared_resources.enable_mes) - kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + if (pdd->dev->kfd->shared_resources.enable_mes) { + ret = kfd_dbg_set_mes_debug_mode( + pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + if (ret) + return ret; + } } p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 8f8a0975f1a7d..1dae317858e93 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -575,9 +575,9 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags) continue; if (!pdd->dev->kfd->shared_resources.enable_mes) - debug_refresh_runlist(pdd->dev->dqm); + (void)debug_refresh_runlist(pdd->dev->dqm); else - kfd_dbg_set_mes_debug_mode(pdd, true); + (void)kfd_dbg_set_mes_debug_mode(pdd, true); } } @@ -637,9 +637,10 @@ void kfd_dbg_trap_deactivate(struct kfd_process *target, bool unwind, int unwind pr_err("Failed to release debug vmid on [%i]\n", pdd->dev->id); if (!pdd->dev->kfd->shared_resources.enable_mes) - debug_refresh_runlist(pdd->dev->dqm); + (void)debug_refresh_runlist(pdd->dev->dqm); else - kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + (void)kfd_dbg_set_mes_debug_mode(pdd, + !kfd_dbg_has_cwsr_workaround(pdd->dev)); } kfd_dbg_set_workaround(target, false); From bd13b407c1037b99e249d2c20dcbd81cf8568d2f Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 9 Jan 2026 15:26:36 -0500 Subject: [PATCH 0079/2070] drm/amdgpu: Fix double deletion of validate_list If amdgpu_amdkfd_gpuvm_free_memory_of_gpu() fails after kgd_mem is removed from validate_list, the mem handle still lingers in the KFD idr. This means when process is terminated, kfd_process_free_outstanding_kfd_bos() will call amdgpu_amdkfd_gpuvm_free_memory_of_gpu() again resulting in double deletion. To avoid this - (a) Check if list is empty before deleting it (b) Rearragne amdgpu_amdkfd_gpuvm_free_memory_of_gpu() such that it can be safely called again if it returns failure the first time. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 768998c82b433..00ea69baa126d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1924,21 +1924,21 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Make sure restore workers don't access the BO any more */ mutex_lock(&process_info->lock); - list_del(&mem->validate_list); + if (!list_empty(&mem->validate_list)) + list_del_init(&mem->validate_list); mutex_unlock(&process_info->lock); + ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); + if (unlikely(ret)) + return ret; + /* Cleanup user pages and MMU notifiers */ if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { amdgpu_hmm_unregister(mem->bo); - mutex_lock(&process_info->notifier_lock); amdgpu_hmm_range_free(mem->range); - mutex_unlock(&process_info->notifier_lock); + mem->range = NULL; } - ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); - if (unlikely(ret)) - return ret; - amdgpu_amdkfd_remove_eviction_fence(mem->bo, process_info->eviction_fence); pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va, From 47f221faeac56572b836cd7b975771da4ce2466c Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Thu, 22 Jan 2026 12:20:29 -0300 Subject: [PATCH 0080/2070] drm/amd/display: fix wrong color value mapping on MCM shaper LUT Some shimmer/colorful points appears when using the steamOS color pipeline for HDR on gaming with DCN32. These points look like black values being wrongly mapped to red/blue/green values. It was caused because the number of hw points in regular LUTs and in a shaper LUT was treated as the same. DCN3+ regular LUTs have 257 bases and implicit deltas (i.e. HW calculates them), but shaper LUT is a special case: it has 256 bases and 256 deltas, as in DCN1-2 regular LUTs, and outputs 14-bit values. Fix that by setting by decreasing in 1 the number of HW points computed in the LUT segmentation so that shaper LUT (i.e. fixpoint == true) keeps the same DCN10 CM logic and regular LUTs go with `hw_points + 1`. CC: Krunoslav Kovac Fixes: 4d5fd3d08ea9 ("drm/amd/display: PQ tail accuracy") Signed-off-by: Melissa Wen Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c index 0690c346f2c52..a4f14b16564c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c @@ -163,6 +163,11 @@ bool cm3_helper_translate_curve_to_hw_format( hw_points += (1 << seg_distr[k]); } + // DCN3+ have 257 pts in lieu of no separate slope registers + // Prior HW had 256 base+slope pairs + // Shaper LUT (i.e. fixpoint == true) is still 256 bases and 256 deltas + hw_points = fixpoint ? (hw_points - 1) : hw_points; + j = 0; for (k = 0; k < (region_end - region_start); k++) { increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); @@ -223,8 +228,6 @@ bool cm3_helper_translate_curve_to_hw_format( corner_points[1].green.slope = dc_fixpt_zero; corner_points[1].blue.slope = dc_fixpt_zero; - // DCN3+ have 257 pts in lieu of no separate slope registers - // Prior HW had 256 base+slope pairs lut_params->hw_points_num = hw_points + 1; k = 0; From b4722c0abaebfee6a6266da10402dea55172b559 Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Mon, 8 Dec 2025 22:44:15 -0100 Subject: [PATCH 0081/2070] drm/amd/display: extend delta clamping logic to CM3 LUT helper Commit 27fc10d1095f ("drm/amd/display: Fix the delta clamping for shaper LUT") fixed banding when using plane shaper LUT in DCN10 CM helper. The problem is also present in DCN30 CM helper, fix banding by extending the same bug delta clamping fix to CM3. Signed-off-by: Melissa Wen Reviewed-by: Harry Wentland --- .../amd/display/dc/dcn30/dcn30_cm_common.c | 30 +++++++++++++++---- .../display/dc/dwb/dcn30/dcn30_cm_common.h | 2 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 9 +++--- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 17 ++++++----- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 16 +++++----- 5 files changed, 49 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c index a4f14b16564c2..227aa8672d17b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c @@ -105,9 +105,12 @@ void cm_helper_program_gamcor_xfer_func( #define NUMBER_REGIONS 32 #define NUMBER_SW_SEGMENTS 16 -bool cm3_helper_translate_curve_to_hw_format( - const struct dc_transfer_func *output_tf, - struct pwl_params *lut_params, bool fixpoint) +#define DC_LOGGER \ + ctx->logger + +bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, + const struct dc_transfer_func *output_tf, + struct pwl_params *lut_params, bool fixpoint) { struct curve_points3 *corner_points; struct pwl_result_data *rgb_resulted; @@ -251,6 +254,10 @@ bool cm3_helper_translate_curve_to_hw_format( if (fixpoint == true) { i = 1; while (i != hw_points + 2) { + uint32_t red_clamp; + uint32_t green_clamp; + uint32_t blue_clamp; + if (i >= hw_points) { if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) rgb_plus_1->red = dc_fixpt_add(rgb->red, @@ -263,9 +270,20 @@ bool cm3_helper_translate_curve_to_hw_format( rgb_minus_1->delta_blue); } - rgb->delta_red_reg = dc_fixpt_clamp_u0d10(rgb->delta_red); - rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green); - rgb->delta_blue_reg = dc_fixpt_clamp_u0d10(rgb->delta_blue); + rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); + + red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red); + green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green); + blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue); + + if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10) + DC_LOG_ERROR("Losing delta precision while programming shaper LUT."); + + rgb->delta_red_reg = red_clamp & 0x3ff; + rgb->delta_green_reg = green_clamp & 0x3ff; + rgb->delta_blue_reg = blue_clamp & 0x3ff; rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red); rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green); rgb->blue_reg = dc_fixpt_clamp_u0d14(rgb->blue); diff --git a/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h b/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h index b86347c9b0389..95f9318a54efc 100644 --- a/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h +++ b/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h @@ -59,7 +59,7 @@ void cm_helper_program_gamcor_xfer_func( const struct pwl_params *params, const struct dcn3_xfer_func_reg *reg); -bool cm3_helper_translate_curve_to_hw_format( +bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, const struct dc_transfer_func *output_tf, struct pwl_params *lut_params, bool fixpoint); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index d58f2cf2615c0..d04cfd403b7ee 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -241,7 +241,7 @@ bool dcn30_set_blend_lut( if (plane_state->blend_tf.type == TF_TYPE_HWPWL) blend_lut = &plane_state->blend_tf.pwl; else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { - result = cm3_helper_translate_curve_to_hw_format( + result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, &plane_state->blend_tf, &dpp_base->regamma_params, false); if (!result) return result; @@ -336,8 +336,9 @@ bool dcn30_set_input_transfer_func(struct dc *dc, if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL) params = &plane_state->in_transfer_func.pwl; else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && - cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func, - &dpp_base->degamma_params, false)) + cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_transfer_func, + &dpp_base->degamma_params, false)) params = &dpp_base->degamma_params; result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); @@ -408,7 +409,7 @@ bool dcn30_set_output_transfer_func(struct dc *dc, params = &stream->out_transfer_func.pwl; else if (pipe_ctx->stream->out_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && - cm3_helper_translate_curve_to_hw_format( + cm3_helper_translate_curve_to_hw_format(stream->ctx, &stream->out_transfer_func, &mpc->blender_params, false)) params = &mpc->blender_params; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 37300e12e6455..1be1213496729 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -493,8 +493,9 @@ bool dcn32_set_mcm_luts( if (plane_state->blend_tf.type == TF_TYPE_HWPWL) lut_params = &plane_state->blend_tf.pwl; else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { - result = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf, - &dpp_base->regamma_params, false); + result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); if (!result) return result; @@ -509,8 +510,9 @@ bool dcn32_set_mcm_luts( else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { // TODO: dpp_base replace ASSERT(false); - cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func, - &dpp_base->shaper_params, true); + cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); lut_params = &dpp_base->shaper_params; } @@ -550,8 +552,9 @@ bool dcn32_set_input_transfer_func(struct dc *dc, if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL) params = &plane_state->in_transfer_func.pwl; else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && - cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func, - &dpp_base->degamma_params, false)) + cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_transfer_func, + &dpp_base->degamma_params, false)) params = &dpp_base->degamma_params; dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); @@ -582,7 +585,7 @@ bool dcn32_set_output_transfer_func(struct dc *dc, params = &stream->out_transfer_func.pwl; else if (pipe_ctx->stream->out_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && - cm3_helper_translate_curve_to_hw_format( + cm3_helper_translate_curve_to_hw_format(stream->ctx, &stream->out_transfer_func, &mpc->blender_params, false)) params = &mpc->blender_params; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 9cda39d0ed95f..b91517b9fedcf 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -432,7 +432,7 @@ void dcn401_populate_mcm_luts(struct dc *dc, if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format( + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, mcm_luts.lut1d_func, &dpp_base->regamma_params, false); m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; @@ -452,7 +452,7 @@ void dcn401_populate_mcm_luts(struct dc *dc, m_lut_params.pwl = &mcm_luts.shaper->pwl; else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { ASSERT(false); - rval = cm3_helper_translate_curve_to_hw_format( + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, mcm_luts.shaper, &dpp_base->regamma_params, true); m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; @@ -629,8 +629,9 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, if (plane_state->blend_tf.type == TF_TYPE_HWPWL) lut_params = &plane_state->blend_tf.pwl; else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf, - &dpp_base->regamma_params, false); + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); lut_params = rval ? &dpp_base->regamma_params : NULL; } result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); @@ -641,8 +642,9 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, lut_params = &plane_state->in_shaper_func.pwl; else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { // TODO: dpp_base replace - rval = cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func, - &dpp_base->shaper_params, true); + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); lut_params = rval ? &dpp_base->shaper_params : NULL; } result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); @@ -676,7 +678,7 @@ bool dcn401_set_output_transfer_func(struct dc *dc, params = &stream->out_transfer_func.pwl; else if (pipe_ctx->stream->out_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && - cm3_helper_translate_curve_to_hw_format( + cm3_helper_translate_curve_to_hw_format(stream->ctx, &stream->out_transfer_func, &mpc->blender_params, false)) params = &mpc->blender_params; From 1e82a71e8e16d825592fb11ab7479772067b0bcb Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Fri, 16 Jan 2026 12:50:49 -0300 Subject: [PATCH 0082/2070] drm/amd/display: remove assert around dpp_base replacement There is nothing wrong if in_shaper_func type is DISTRIBUTED POINTS. Remove the assert placed for a TODO to avoid misinterpretations. Signed-off-by: Melissa Wen Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 1be1213496729..2767d3a97812e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -509,7 +509,6 @@ bool dcn32_set_mcm_luts( lut_params = &plane_state->in_shaper_func.pwl; else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { // TODO: dpp_base replace - ASSERT(false); cm3_helper_translate_curve_to_hw_format(plane_state->ctx, &plane_state->in_shaper_func, &dpp_base->shaper_params, true); From dac9a97941a035c019e9bd7a4dd9e670372b9c5f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 22 Jan 2026 12:11:49 +0530 Subject: [PATCH 0083/2070] drm/amdgpu: Skip vcn poison irq release on VF VF doesn't enable VCN poison irq in VCNv2.5. Skip releasing it and avoid call trace during deinitialization. [ 71.913601] [drm] clean up the vf2pf work item [ 71.915088] ------------[ cut here ]------------ [ 71.915092] WARNING: CPU: 3 PID: 1079 at /tmp/amd.aFkFvSQl/amd/amdgpu/amdgpu_irq.c:641 amdgpu_irq_put+0xc6/0xe0 [amdgpu] [ 71.915355] Modules linked in: amdgpu(OE-) amddrm_ttm_helper(OE) amdttm(OE) amddrm_buddy(OE) amdxcp(OE) amddrm_exec(OE) amd_sched(OE) amdkcl(OE) drm_suballoc_helper drm_display_helper cec rc_core i2c_algo_bit video wmi binfmt_misc nls_iso8859_1 intel_rapl_msr intel_rapl_common input_leds joydev serio_raw mac_hid qemu_fw_cfg sch_fq_codel dm_multipath scsi_dh_rdac scsi_dh_emc scsi_dh_alua efi_pstore ip_tables x_tables autofs4 btrfs blake2b_generic raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor raid6_pq libcrc32c raid1 raid0 hid_generic crct10dif_pclmul crc32_pclmul polyval_clmulni polyval_generic ghash_clmulni_intel usbhid 8139too sha256_ssse3 sha1_ssse3 hid psmouse bochs i2c_i801 ahci drm_vram_helper libahci i2c_smbus lpc_ich drm_ttm_helper 8139cp mii ttm aesni_intel crypto_simd cryptd [ 71.915484] CPU: 3 PID: 1079 Comm: rmmod Tainted: G OE 6.8.0-87-generic #88~22.04.1-Ubuntu [ 71.915489] Hardware name: Red Hat KVM/RHEL, BIOS 1.16.3-2.el9_5.1 04/01/2014 [ 71.915492] RIP: 0010:amdgpu_irq_put+0xc6/0xe0 [amdgpu] [ 71.915768] Code: 75 84 b8 ea ff ff ff eb d4 44 89 ea 48 89 de 4c 89 e7 e8 fd fc ff ff 5b 41 5c 41 5d 41 5e 5d 31 d2 31 f6 31 ff e9 55 30 3b c7 <0f> 0b eb d4 b8 fe ff ff ff eb a8 e9 b7 3b 8a 00 66 2e 0f 1f 84 00 [ 71.915771] RSP: 0018:ffffcf0800eafa30 EFLAGS: 00010246 [ 71.915775] RAX: 0000000000000000 RBX: ffff891bda4b0668 RCX: 0000000000000000 [ 71.915777] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000 [ 71.915779] RBP: ffffcf0800eafa50 R08: 0000000000000000 R09: 0000000000000000 [ 71.915781] R10: 0000000000000000 R11: 0000000000000000 R12: ffff891bda480000 [ 71.915782] R13: 0000000000000000 R14: 0000000000000001 R15: 0000000000000000 [ 71.915792] FS: 000070cff87c4c40(0000) GS:ffff893abfb80000(0000) knlGS:0000000000000000 [ 71.915795] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 71.915797] CR2: 00005fa13073e478 CR3: 000000010d634006 CR4: 0000000000770ef0 [ 71.915800] PKRU: 55555554 [ 71.915802] Call Trace: [ 71.915805] [ 71.915809] vcn_v2_5_hw_fini+0x19e/0x1e0 [amdgpu] Signed-off-by: Lijo Lazar Reviewed-by: Mangesh Gadre --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index cebee453871c1..006a154511971 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -521,7 +521,9 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) RREG32_SOC15(VCN, i, mmUVD_STATUS))) vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) + /* VF doesn't enable interrupt operations for RAS */ + if (!amdgpu_sriov_vf(adev) && + amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) amdgpu_irq_put(adev, &vinst->ras_poison_irq, 0); } From 61ccc4ce8a5d00b81c24c6a6cb9d4e325b9c51f7 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 30 Jan 2026 15:44:28 +0530 Subject: [PATCH 0084/2070] drm/amd/pm: Remove buffer allocation in SMUv13.0.6 No longer required to allocate temporary buffer while fetching metrcis, instead, use metrics table cache data directly. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 27 +++++++++---------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index be7d77eee2b07..3a9210083ce33 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2564,9 +2564,10 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; int version = smu_v13_0_6_get_metrics_version(smu); struct smu_v13_0_6_partition_metrics *xcp_metrics; - MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; + struct smu_table_context *smu_table = &smu->smu_table; struct amdgpu_device *adev = smu->adev; int ret, inst, i, j, k, idx; + MetricsTableV0_t *metrics_v0; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; struct amdgpu_xcp *xcp; @@ -2586,22 +2587,20 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; smu_v13_0_6_partition_metrics_init(xcp_metrics, 1, 1); - metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); - if (!metrics_v0) - return -ENOMEM; - - ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); + ret = smu_v13_0_6_get_metrics_table(smu, NULL, false); if (ret) return ret; + metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table; + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) return smu_v13_0_12_get_xcp_metrics(smu, xcp, table, metrics_v0); - metrics_v1 = (MetricsTableV1_t *)metrics_v0; - metrics_v2 = (MetricsTableV2_t *)metrics_v0; + metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table; + metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table; per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS)); @@ -2677,21 +2676,21 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table { struct smu_v13_0_6_gpu_metrics *gpu_metrics; int version = smu_v13_0_6_get_metrics_version(smu); - MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; + struct smu_table_context *smu_table = &smu->smu_table; struct amdgpu_device *adev = smu->adev; int ret = 0, xcc_id, inst, i, j; + MetricsTableV0_t *metrics_v0; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; u16 link_width_level; u8 num_jpeg_rings; bool per_inst; - metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); - ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); + ret = smu_v13_0_6_get_metrics_table(smu, NULL, false); if (ret) return ret; - metrics_v2 = (MetricsTableV2_t *)metrics_v0; + metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table; gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)smu_driver_table_ptr( smu, SMU_DRIVER_TABLE_GPU_METRICS); @@ -2702,8 +2701,8 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table goto fill; } - metrics_v1 = (MetricsTableV1_t *)metrics_v0; - metrics_v2 = (MetricsTableV2_t *)metrics_v0; + metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table; + metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table; gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)); From 22965aef1f49cc8d84eb6328adc1b6b361e357b6 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Thu, 8 Jan 2026 17:08:06 +0100 Subject: [PATCH 0085/2070] drm/amdgpu: remove gart_window_lock usage from gmc v12_1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Same as what was done in commit 904de683fa5f ("drm/amdgpu: remove gart_window_lock usage from gmc v12") for v12. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index ef6e550ce7c3d..dc8865c5879c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -345,9 +345,7 @@ static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, return; } - mutex_lock(&adev->mman.gtt_window_lock); gmc_v12_1_flush_vm_hub(adev, vmid, vmhub, 0); - mutex_unlock(&adev->mman.gtt_window_lock); return; } From d34ed0a786524885a46b9802033ecd7602c8e4e8 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 18 Nov 2025 14:58:43 +0100 Subject: [PATCH 0086/2070] drm/amdgpu: statically assign gart windows to ttm entities MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If multiple entities share the same window we must make sure that jobs using them are executed sequentially. This commit gives separate windows to each entity, so jobs from multiple entities could execute in parallel if needed. (for now they all use the first sdma engine, so it makes no difference yet). The entity stores the gart window offsets to centralize the "window id" to "window offset" in a single place. default_entity doesn't get any windows reserved since there is no use for them. --- v3: - renamed gart_window_lock -> lock (Christian) - added amdgpu_ttm_buffer_entity_init (Christian) - fixed gart_addr in svm_migrate_gart_map (Felix) - renamed gart_window_idX -> gart_window_offs[] - added amdgpu_compute_gart_address v4: - u32 -> u64 - added kerneldoc v5: - removed gtt_window_lock - simplified gart window creation and use: entities using a single window now uses window #0 instead of #1 - fix dst_addr calculation in kfd_migrate.c --- Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Felix Kuehling Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 64 +++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 21 ++++++-- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 12 ++--- 4 files changed, 72 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index b793ce17140c4..e87cb8ccfcd9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -742,7 +742,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, * translation. Avoid this by doing the invalidation from the SDMA * itself at least for GART. */ - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&adev->mman.default_entity.lock); r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base, AMDGPU_FENCE_OWNER_UNDEFINED, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, @@ -755,7 +755,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; amdgpu_ring_pad_ib(ring, &job->ibs[0]); fence = amdgpu_job_submit(job); - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); dma_fence_wait(fence, false); dma_fence_put(fence); @@ -763,7 +763,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, return; error_alloc: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 15d561e3d87f7..447518ca777a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -228,9 +228,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity, *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); - *addr = adev->gmc.gart_start; - *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * - AMDGPU_GPU_PAGE_SIZE; + *addr = amdgpu_compute_gart_address(&adev->gmc, entity, window); *addr += offset; num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); @@ -248,7 +246,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity, src_addr += job->ibs[0].gpu_addr; dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); - dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; + dst_addr += (entity->gart_window_offs[window] >> AMDGPU_GPU_PAGE_SHIFT) * 8; amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); @@ -313,7 +311,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, amdgpu_res_first(src->mem, src->offset, size, &src_mm); amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (src_mm.remaining) { uint64_t from, to, cur_size, tiling_flags; uint32_t num_type, data_format, max_com, write_compress_disable; @@ -368,7 +366,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, amdgpu_res_next(&dst_mm, cur_size); } error: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); *f = fence; return r; } @@ -1580,7 +1578,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, if (r) goto out; - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&adev->mman.default_entity.lock); amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start; @@ -1592,7 +1590,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, PAGE_SIZE, 0); fence = amdgpu_ttm_job_submit(adev, job, num_dw); - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) r = -ETIMEDOUT; @@ -2014,6 +2012,27 @@ static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) adev->rmmio_remap.bo = NULL; } +static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *entity, + int starting_gart_window, + u32 num_gart_windows) +{ + int i; + + mutex_init(&entity->lock); + + if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) + return starting_gart_window; + + for (i = 0; i < num_gart_windows; i++) { + entity->gart_window_offs[i] = + (u64)starting_gart_window * AMDGPU_GTT_MAX_TRANSFER_SIZE * + AMDGPU_GPU_PAGE_SIZE; + starting_gart_window++; + } + + return starting_gart_window; +} + /* * amdgpu_ttm_init - Init the memory management (ttm) as well as various * gtt/vram related fields. @@ -2028,8 +2047,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) uint64_t gtt_size; int r; - mutex_init(&adev->mman.gtt_window_lock); - dma_set_max_seg_size(adev->dev, UINT_MAX); /* No others user of address space so set it to 0 */ r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, @@ -2303,6 +2320,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) { struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); + u32 used_windows; uint64_t size; int r; @@ -2346,6 +2364,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) drm_sched_entity_destroy(&adev->mman.clear_entity.base); goto error_free_entity; } + + /* Statically assign GART windows to each entity. */ + used_windows = amdgpu_ttm_buffer_entity_init(&adev->mman.default_entity, 0, 0); + used_windows = amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, + used_windows, 2); + used_windows = amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, + used_windows, 1); } else { drm_sched_entity_destroy(&adev->mman.default_entity.base); drm_sched_entity_destroy(&adev->mman.clear_entity.base); @@ -2504,6 +2529,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, struct dma_fence **fence) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_ttm_buffer_entity *entity; struct amdgpu_res_cursor cursor; u64 addr; int r = 0; @@ -2514,11 +2540,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, if (!fence) return -EINVAL; + entity = &adev->mman.clear_entity; *fence = dma_fence_get_stub(); amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (cursor.remaining) { struct dma_fence *next = NULL; u64 size; @@ -2531,13 +2558,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, /* Never clear more than 256MiB at once to avoid timeouts */ size = min(cursor.size, 256ULL << 20); - r = amdgpu_ttm_map_buffer(&adev->mman.clear_entity, - &bo->tbo, bo->tbo.resource, &cursor, - 1, false, &size, &addr); + r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &cursor, + 0, false, &size, &addr); if (r) goto err; - r = amdgpu_ttm_fill_mem(adev, &adev->mman.clear_entity, 0, addr, size, resv, + r = amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv, &next, true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) @@ -2549,7 +2575,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, amdgpu_res_next(&cursor, size); } err: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); return r; } @@ -2574,7 +2600,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (dst.remaining) { struct dma_fence *next; uint64_t cur_size, to; @@ -2583,7 +2609,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, cur_size = min(dst.size, 256ULL << 20); r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &dst, - 1, false, &cur_size, &to); + 0, false, &cur_size, &to); if (r) goto error; @@ -2599,7 +2625,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, amdgpu_res_next(&dst, cur_size); } error: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); if (f) *f = dma_fence_get(fence); dma_fence_put(fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 143201ecea3fe..871388b86503e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -29,6 +29,7 @@ #include #include "amdgpu_vram_mgr.h" #include "amdgpu_hmm.h" +#include "amdgpu_gmc.h" #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -39,7 +40,7 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 +#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -54,6 +55,8 @@ struct amdgpu_gtt_mgr { struct amdgpu_ttm_buffer_entity { struct drm_sched_entity base; + struct mutex lock; + u64 gart_window_offs[2]; }; struct amdgpu_mman { @@ -67,8 +70,7 @@ struct amdgpu_mman { struct amdgpu_ring *buffer_funcs_ring; bool buffer_funcs_enabled; - struct mutex gtt_window_lock; - + /* @default_entity: for workarounds, has no gart windows */ struct amdgpu_ttm_buffer_entity default_entity; struct amdgpu_ttm_buffer_entity clear_entity; struct amdgpu_ttm_buffer_entity move_entity; @@ -205,6 +207,19 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, } #endif +/** + * amdgpu_compute_gart_address() - Returns GART address of an entity's window + * @gmc: The &struct amdgpu_gmc instance to use + * @entity: The &struct amdgpu_ttm_buffer_entity owning the GART window + * @index: The window to use (must be 0 or 1) + */ +static inline u64 amdgpu_compute_gart_address(struct amdgpu_gmc *gmc, + struct amdgpu_ttm_buffer_entity *entity, + int index) +{ + return gmc->gart_start + entity->gart_window_offs[index]; +} + void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 7a8990b30fa0b..01031ef972726 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -59,8 +59,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, void *cpu_addr; int r; - /* use gart window 0 */ - *gart_addr = adev->gmc.gart_start; + *gart_addr = amdgpu_compute_gart_address(&adev->gmc, entity, 0); num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes = npages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; @@ -78,6 +77,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, src_addr += job->ibs[0].gpu_addr; dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); + dst_addr += (entity->gart_window_offs[0] >> AMDGPU_GPU_PAGE_SHIFT) * 8; amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); @@ -116,7 +116,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, * multiple GTT_MAX_PAGES transfer, all sdma operations are serialized, wait for * the last sdma finish fence which is returned to check copy memory is done. * - * Context: Process context, takes and releases gtt_window_lock + * Context: Process context * * Return: * 0 - OK, otherwise error code @@ -136,9 +136,9 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, u64 size; int r; - entity = &adev->mman.default_entity; + entity = &adev->mman.move_entity; - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (npages) { size = min(GTT_MAX_PAGES, npages); @@ -175,7 +175,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, } out_unlock: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); return r; } From 19e9362761cc7fd1d603126a75f3ce495215a338 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Fri, 9 Jan 2026 16:19:10 +0100 Subject: [PATCH 0087/2070] drm/amdgpu: add amdgpu_ttm_buffer_entity_fini func MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to have init/fini functions to hold all the init and teardown code for amdgpu_ttm_buffer_entity. For now only drm_sched_entity init/destroy function calls are moved here, but as entities gain new members it will make code simpler. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 73 +++++++++++++------------ 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 447518ca777a5..91c7e220e2d39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2013,10 +2013,18 @@ static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) } static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *entity, + enum drm_sched_priority prio, + struct drm_gpu_scheduler **scheds, + int num_schedulers, int starting_gart_window, u32 num_gart_windows) { - int i; + int i, r; + + r = drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, NULL); + if (r) + return r; + mutex_init(&entity->lock); @@ -2033,6 +2041,11 @@ static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *entity return starting_gart_window; } +static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_ttm_buffer_entity *entity) +{ + drm_sched_entity_destroy(&entity->base); +} + /* * amdgpu_ttm_init - Init the memory management (ttm) as well as various * gtt/vram related fields. @@ -2320,7 +2333,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) { struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); - u32 used_windows; uint64_t size; int r; @@ -2334,47 +2346,36 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) ring = adev->mman.buffer_funcs_ring; sched = &ring->sched; - r = drm_sched_entity_init(&adev->mman.default_entity.base, - DRM_SCHED_PRIORITY_KERNEL, &sched, - 1, NULL); - if (r) { + r = amdgpu_ttm_buffer_entity_init(&adev->mman.default_entity, + DRM_SCHED_PRIORITY_KERNEL, &sched, 1, + 0, 0); + if (r < 0) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", - r); + "Failed setting up TTM entity (%d)\n", r); return; } - r = drm_sched_entity_init(&adev->mman.clear_entity.base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { + r = amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, + DRM_SCHED_PRIORITY_NORMAL, &sched, 1, + r, 1); + if (r < 0) { dev_err(adev->dev, - "Failed setting up TTM BO clear entity (%d)\n", - r); - goto error_free_entity; + "Failed setting up TTM BO clear entity (%d)\n", r); + goto error_free_default_entity; } - r = drm_sched_entity_init(&adev->mman.move_entity.base, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { + r = amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, + DRM_SCHED_PRIORITY_NORMAL, &sched, 1, + r, 2); + if (r < 0) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", - r); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); - goto error_free_entity; + "Failed setting up TTM BO move entity (%d)\n", r); + goto error_free_clear_entity; } - - /* Statically assign GART windows to each entity. */ - used_windows = amdgpu_ttm_buffer_entity_init(&adev->mman.default_entity, 0, 0); - used_windows = amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, - used_windows, 2); - used_windows = amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, - used_windows, 1); } else { - drm_sched_entity_destroy(&adev->mman.default_entity.base); - drm_sched_entity_destroy(&adev->mman.clear_entity.base); - drm_sched_entity_destroy(&adev->mman.move_entity.base); + amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.move_entity); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ @@ -2391,8 +2392,10 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) return; -error_free_entity: - drm_sched_entity_destroy(&adev->mman.default_entity.base); +error_free_clear_entity: + amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); +error_free_default_entity: + amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); } static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, From 1bb0a3cc397345a3ead953ecfc5cb045976556f8 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Wed, 28 Jan 2026 16:47:01 +0100 Subject: [PATCH 0088/2070] drm/amdgpu: add amdgpu_gtt_node_to_byte_offset helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having a helper avoids code duplication. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 871388b86503e..c43f352df9531 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -220,6 +220,14 @@ static inline u64 amdgpu_compute_gart_address(struct amdgpu_gmc *gmc, return gmc->gart_start + entity->gart_window_offs[index]; } +/** + * amdgpu_gtt_node_to_byte_offset() - Returns a byte offset of a gtt node + */ +static inline u64 amdgpu_gtt_node_to_byte_offset(const struct drm_mm_node *gtt_node) +{ + return gtt_node->start * (u64)PAGE_SIZE; +} + void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); From 66a80158aa2a0c579b0a6aa8908207d74299df8b Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 26 Jan 2026 09:48:16 +0100 Subject: [PATCH 0089/2070] amdgpu/vce: use amdgpu_gtt_mgr_alloc_entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of reserving a number of GTT pages for VCE 1.0 this commit now uses amdgpu_gtt_mgr_alloc_entries to allocate the pages when initializing vce 1.0. While at it remove the "does the VCPU BO already have a 32-bit address" check as suggested by Timur. This decouples vce init from gtt init. --- v7: renamed variables (Christian) --- Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 18 ----------- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 33 +++++++++++---------- 4 files changed, 18 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index dd9b845d57834..f2e89fb4b666c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -332,7 +332,6 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - start += amdgpu_vce_required_gart_pages(adev); size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index a7d8f1ce6ac2d..eb4a15db2ef20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -450,24 +450,6 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) } } -/** - * amdgpu_vce_required_gart_pages() - gets number of GART pages required by VCE - * - * @adev: amdgpu_device pointer - * - * Returns how many GART pages we need before GTT for the VCE IP block. - * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details. - * For VCE2+, this is not needed so return zero. - */ -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev) -{ - /* VCE IP block not added yet, so can't use amdgpu_ip_version */ - if (adev->family == AMDGPU_FAMILY_SI) - return 512; - - return 0; -} - /** * amdgpu_vce_get_create_msg - generate a VCE create msg * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 1c3464ce50378..778c714c8385d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -52,6 +52,7 @@ struct amdgpu_vce { uint32_t srbm_soft_reset; unsigned num_rings; uint32_t keyselect; + struct drm_mm_node gart_node; }; int amdgpu_vce_early_init(struct amdgpu_device *adev); @@ -61,7 +62,6 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib); int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c index 9ae4246185560..5b7b46d242c6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -47,11 +47,6 @@ #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 -#define VCE_V1_0_GART_PAGE_START \ - (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) -#define VCE_V1_0_GART_ADDR_START \ - (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) - static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); @@ -535,27 +530,29 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) */ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) { - u64 gpu_addr = amdgpu_bo_gpu_offset(adev->vce.vcpu_bo); u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); u64 max_vcpu_bo_addr = 0xffffffff - bo_size; u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE; u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID; + u64 vce_gart_start_offs; + int r; - /* - * Check if the VCPU BO already has a 32-bit address. - * Eg. if MC is configured to put VRAM in the low address range. - */ - if (gpu_addr <= max_vcpu_bo_addr) - return 0; + r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, + &adev->vce.gart_node, num_pages, + DRM_MM_INSERT_LOW); + if (r) + return r; + + vce_gart_start_offs = amdgpu_gtt_node_to_byte_offset(&adev->vce.gart_node); /* Check if we can map the VCPU BO in GART to a 32-bit address. */ - if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) + if (adev->gmc.gart_start + vce_gart_start_offs > max_vcpu_bo_addr) return -EINVAL; - amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START, + amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_node.start, num_pages, flags, adev->gart.ptr); - adev->vce.gpu_addr = adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; + adev->vce.gpu_addr = adev->gmc.gart_start + vce_gart_start_offs; if (adev->vce.gpu_addr > max_vcpu_bo_addr) return -EINVAL; @@ -610,7 +607,11 @@ static int vce_v1_0_sw_fini(struct amdgpu_ip_block *ip_block) if (r) return r; - return amdgpu_vce_sw_fini(adev); + r = amdgpu_vce_sw_fini(adev); + + amdgpu_gtt_mgr_free_entries(&adev->mman.gtt_mgr, &adev->vce.gart_node); + + return r; } /** From cca7274e5e8b177298c1f4afc59f3303f520cec0 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 26 Jan 2026 10:17:24 +0100 Subject: [PATCH 0090/2070] amdgpu/ttm: use amdgpu_gtt_mgr_alloc_entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use amdgpu_gtt_mgr_alloc_entries for each entity instead of reserving a fixed number of pages. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 66 ++++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + 2 files changed, 43 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 91c7e220e2d39..e3486967ec5e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2012,37 +2012,47 @@ static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) adev->rmmio_remap.bo = NULL; } -static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *entity, +static int amdgpu_ttm_buffer_entity_init(struct amdgpu_gtt_mgr *mgr, + struct amdgpu_ttm_buffer_entity *entity, enum drm_sched_priority prio, struct drm_gpu_scheduler **scheds, int num_schedulers, - int starting_gart_window, u32 num_gart_windows) { - int i, r; + int i, r, num_pages; r = drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, NULL); if (r) return r; - mutex_init(&entity->lock); if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) - return starting_gart_window; + return -EINVAL; + if (num_gart_windows == 0) + return 0; + + num_pages = num_gart_windows * AMDGPU_GTT_MAX_TRANSFER_SIZE; + r = amdgpu_gtt_mgr_alloc_entries(mgr, &entity->gart_node, num_pages, + DRM_MM_INSERT_BEST); + if (r) { + drm_sched_entity_destroy(&entity->base); + return r; + } for (i = 0; i < num_gart_windows; i++) { entity->gart_window_offs[i] = - (u64)starting_gart_window * AMDGPU_GTT_MAX_TRANSFER_SIZE * - AMDGPU_GPU_PAGE_SIZE; - starting_gart_window++; + amdgpu_gtt_node_to_byte_offset(&entity->gart_node) + + i * AMDGPU_GTT_MAX_TRANSFER_SIZE * PAGE_SIZE; } - return starting_gart_window; + return 0; } -static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_ttm_buffer_entity *entity) +static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_gtt_mgr *mgr, + struct amdgpu_ttm_buffer_entity *entity) { + amdgpu_gtt_mgr_free_entries(mgr, &entity->gart_node); drm_sched_entity_destroy(&entity->base); } @@ -2346,36 +2356,42 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) ring = adev->mman.buffer_funcs_ring; sched = &ring->sched; - r = amdgpu_ttm_buffer_entity_init(&adev->mman.default_entity, - DRM_SCHED_PRIORITY_KERNEL, &sched, 1, - 0, 0); + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.default_entity, + DRM_SCHED_PRIORITY_KERNEL, + &sched, 1, 0); if (r < 0) { dev_err(adev->dev, "Failed setting up TTM entity (%d)\n", r); return; } - r = amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, - r, 1); + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.clear_entity, + DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, 1); if (r < 0) { dev_err(adev->dev, "Failed setting up TTM BO clear entity (%d)\n", r); goto error_free_default_entity; } - r = amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, - r, 2); + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.move_entity, + DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, 2); if (r < 0) { dev_err(adev->dev, "Failed setting up TTM BO move entity (%d)\n", r); goto error_free_clear_entity; } } else { - amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); - amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); - amdgpu_ttm_buffer_entity_fini(&adev->mman.move_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.move_entity); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ @@ -2393,9 +2409,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) return; error_free_clear_entity: - amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entity); error_free_default_entity: - amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); } static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index c43f352df9531..8af0aab7608cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -56,6 +56,7 @@ struct amdgpu_gtt_mgr { struct amdgpu_ttm_buffer_entity { struct drm_sched_entity base; struct mutex lock; + struct drm_mm_node gart_node; u64 gart_window_offs[2]; }; From 23ce3ddf5c710478a236bf53a93f48630b559c19 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 26 Jan 2026 10:17:43 +0100 Subject: [PATCH 0091/2070] amdgpu/gtt: remove AMDGPU_GTT_NUM_TRANSFER_WINDOWS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not needed anymore. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 5 +---- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 - 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index f2e89fb4b666c..9b0bcf6aca445 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -324,16 +324,13 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) { struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; struct ttm_resource_manager *man = &mgr->manager; - uint64_t start, size; man->use_tt = true; man->func = &amdgpu_gtt_mgr_func; ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); - start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; - drm_mm_init(&mgr->mm, start, size); + drm_mm_init(&mgr->mm, 0, adev->gmc.gart_size >> PAGE_SHIFT); spin_lock_init(&mgr->lock); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 8af0aab7608cb..f927b793c395f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -40,7 +40,6 @@ #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; From 8bf8d05a35c9528379cd259293491f4cf509f08f Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 18 Nov 2025 15:15:04 +0100 Subject: [PATCH 0092/2070] drm/amdgpu: add missing lock in amdgpu_benchmark_do_move MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Taking the entity lock is required to guarantee the ordering of execution. The next commit will add a check that the lock is held. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c index 1cbba9803d314..98ccd7ab9e9a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -35,6 +35,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, struct dma_fence *fence; int i, r; + mutex_lock(&adev->mman.default_entity.lock); stime = ktime_get(); for (i = 0; i < n; i++) { r = amdgpu_copy_buffer(adev, &adev->mman.default_entity, @@ -47,6 +48,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, if (r) goto exit_do_move; } + mutex_unlock(&adev->mman.default_entity.lock); exit_do_move: etime = ktime_get(); From 80d38eebc6dc59c9adae1444f64b831708b43db4 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 18 Nov 2025 15:09:14 +0100 Subject: [PATCH 0093/2070] drm/amdgpu: check entity lock is held in amdgpu_ttm_job_submit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drm_sched_job_arm and drm_sched_entity_push_job must be called under the same lock to guarantee the order of execution. This commit adds a check in amdgpu_ttm_job_submit and fix the places where the lock was missing. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index e3486967ec5e2..5feba7044951c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -163,7 +163,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } static struct dma_fence * -amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_job *job, u32 num_dw) +amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_job *job, u32 num_dw) { struct amdgpu_ring *ring; @@ -171,6 +172,8 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_job *job, u32 nu amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); + lockdep_assert_held(&entity->lock); + return amdgpu_job_submit(job); } @@ -267,7 +270,7 @@ static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity, amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); } - dma_fence_put(amdgpu_ttm_job_submit(adev, job, num_dw)); + dma_fence_put(amdgpu_ttm_job_submit(adev, entity, job, num_dw)); return 0; } @@ -1589,7 +1592,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, 0); - fence = amdgpu_ttm_job_submit(adev, job, num_dw); + fence = amdgpu_ttm_job_submit(adev, &adev->mman.default_entity, job, num_dw); mutex_unlock(&adev->mman.default_entity.lock); if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) @@ -2487,7 +2490,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev, byte_count -= cur_size_in_bytes; } - *fence = amdgpu_ttm_job_submit(adev, job, num_dw); + *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); return 0; @@ -2530,7 +2533,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, byte_count -= cur_size; } - *fence = amdgpu_ttm_job_submit(adev, job, num_dw); + *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); return 0; } From 9464df568bc698e24aacedc262b6b4b0b412fef1 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Fri, 19 Sep 2025 10:35:27 +0200 Subject: [PATCH 0094/2070] drm/amdgpu: double AMDGPU_GTT_MAX_TRANSFER_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Makes copies/evictions faster when gart windows are required. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index f927b793c395f..bf101215757e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -39,7 +39,7 @@ #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) -#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 +#define AMDGPU_GTT_MAX_TRANSFER_SIZE 1024 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; From 54bc24ae83b1f7e39c8a75412852d017838cf6a2 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 9 Sep 2025 15:39:24 +0200 Subject: [PATCH 0095/2070] drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All sdma versions used the same logic, so add a helper and move the common code to a single place. --- v2: pass amdgpu_vm_pte_funcs as well v3: drop all the *_set_vm_pte_funcs one liners v5: rebased --- Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ++++++++++++ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 35 ++++++------------------ drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 35 ++++++------------------ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 31 ++++++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 29 ++++++-------------- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 29 ++++++-------------- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 29 ++++++-------------- drivers/gpu/drm/amd/amdgpu/si_dma.c | 31 ++++++--------------- 13 files changed, 113 insertions(+), 249 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 447e734c362be..af4042387f3b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1536,6 +1536,8 @@ struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, + const struct amdgpu_vm_pte_funcs *vm_pte_funcs); /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 6a2ea200d90c8..24c1f95ec5072 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3227,3 +3227,20 @@ void amdgpu_vm_print_task_info(struct amdgpu_device *adev, task_info->process_name, task_info->tgid, task_info->task.comm, task_info->task.pid); } + +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, + const struct amdgpu_vm_pte_funcs *vm_pte_funcs) +{ + struct drm_gpu_scheduler *sched; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) { + if (adev->sdma.has_page_queue) + sched = &adev->sdma.instance[i].page.sched; + else + sched = &adev->sdma.instance[i].ring.sched; + adev->vm_manager.vm_pte_scheds[i] = sched; + } + adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; + adev->vm_manager.vm_pte_funcs = vm_pte_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 9e8715b4739da..22780c09177d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -53,7 +53,6 @@ static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); -static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block); u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); @@ -919,6 +918,14 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev, } } +static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = cik_sdma_vm_copy_pte, + + .write_pte = cik_sdma_vm_write_pte, + .set_pte_pde = cik_sdma_vm_set_pte_pde, +}; + static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -933,7 +940,7 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); cik_sdma_set_buffer_funcs(adev); - cik_sdma_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); return 0; } @@ -1337,26 +1344,6 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = cik_sdma_vm_copy_pte, - - .write_pte = cik_sdma_vm_write_pte, - .set_pte_pde = cik_sdma_vm_set_pte_pde, -}; - -static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version cik_sdma_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 92ce580647cdc..0090ace49024f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -51,7 +51,6 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); @@ -809,6 +808,14 @@ static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } +static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v2_4_vm_copy_pte, + + .write_pte = sdma_v2_4_vm_write_pte, + .set_pte_pde = sdma_v2_4_vm_set_pte_pde, +}; + static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -822,7 +829,7 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) sdma_v2_4_set_ring_funcs(adev); sdma_v2_4_set_buffer_funcs(adev); - sdma_v2_4_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs); sdma_v2_4_set_irq_funcs(adev); return 0; @@ -1232,26 +1239,6 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v2_4_vm_copy_pte, - - .write_pte = sdma_v2_4_vm_write_pte, - .set_pte_pde = sdma_v2_4_vm_set_pte_pde, -}; - -static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v2_4_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 1c076bd1cf73e..2526d393162ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -51,7 +51,6 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); @@ -1082,6 +1081,14 @@ static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } +static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v3_0_vm_copy_pte, + + .write_pte = sdma_v3_0_vm_write_pte, + .set_pte_pde = sdma_v3_0_vm_set_pte_pde, +}; + static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1102,7 +1109,7 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v3_0_set_ring_funcs(adev); sdma_v3_0_set_buffer_funcs(adev); - sdma_v3_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); sdma_v3_0_set_irq_funcs(adev); return 0; @@ -1674,26 +1681,6 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v3_0_vm_copy_pte, - - .write_pte = sdma_v3_0_vm_write_pte, - .set_pte_pde = sdma_v3_0_vm_set_pte_pde, -}; - -static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v3_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index f38004e6064e5..a35d9951e22a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -129,7 +129,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_0[] = { static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); @@ -1751,6 +1750,14 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) } } +static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v4_0_vm_copy_pte, + + .write_pte = sdma_v4_0_vm_write_pte, + .set_pte_pde = sdma_v4_0_vm_set_pte_pde, +}; + static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1769,7 +1776,7 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v4_0_set_ring_funcs(adev); sdma_v4_0_set_buffer_funcs(adev); - sdma_v4_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); sdma_v4_0_set_irq_funcs(adev); sdma_v4_0_set_ras_funcs(adev); @@ -2615,30 +2622,6 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v4_0_vm_copy_pte, - - .write_pte = sdma_v4_0_vm_write_pte, - .set_pte_pde = sdma_v4_0_vm_set_pte_pde, -}; - -static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - struct drm_gpu_scheduler *sched; - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - if (adev->sdma.has_page_queue) - sched = &adev->sdma.instance[i].page.sched; - else - sched = &adev->sdma.instance[i].ring.sched; - adev->vm_manager.vm_pte_scheds[i] = sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - static void sdma_v4_0_get_ras_error_count(uint32_t value, uint32_t instance, uint32_t *sec_count) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index a1443990d5c60..7f77367848d43 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -104,7 +104,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); @@ -1347,6 +1346,14 @@ static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, }; +static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v4_4_2_vm_copy_pte, + + .write_pte = sdma_v4_4_2_vm_write_pte, + .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, +}; + static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1362,7 +1369,7 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) sdma_v4_4_2_set_ring_funcs(adev); sdma_v4_4_2_set_buffer_funcs(adev); - sdma_v4_4_2_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); sdma_v4_4_2_set_irq_funcs(adev); sdma_v4_4_2_set_ras_funcs(adev); return 0; @@ -2316,30 +2323,6 @@ static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v4_4_2_vm_copy_pte, - - .write_pte = sdma_v4_4_2_vm_write_pte, - .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, -}; - -static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - struct drm_gpu_scheduler *sched; - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - if (adev->sdma.has_page_queue) - sched = &adev->sdma.instance[i].page.sched; - else - sched = &adev->sdma.instance[i].ring.sched; - adev->vm_manager.vm_pte_scheds[i] = sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - /** * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA * @adev: Pointer to the AMDGPU device structure diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index e77e079fe8339..d72bd3adfccf1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -110,7 +110,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = { static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring); static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring); @@ -1357,6 +1356,13 @@ static const struct amdgpu_sdma_funcs sdma_v5_0_sdma_funcs = { .soft_reset_kernel_queue = &sdma_v5_0_soft_reset_engine, }; +static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v5_0_vm_copy_pte, + .write_pte = sdma_v5_0_vm_write_pte, + .set_pte_pde = sdma_v5_0_vm_set_pte_pde, +}; + static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1368,7 +1374,7 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v5_0_set_ring_funcs(adev); sdma_v5_0_set_buffer_funcs(adev); - sdma_v5_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs); sdma_v5_0_set_irq_funcs(adev); sdma_v5_0_set_mqd_funcs(adev); @@ -2061,27 +2067,6 @@ static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) } } -static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v5_0_vm_copy_pte, - .write_pte = sdma_v5_0_vm_write_pte, - .set_pte_pde = sdma_v5_0_vm_set_pte_pde, -}; - -static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - if (adev->vm_manager.vm_pte_funcs == NULL) { - adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; - } -} - const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 5, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 50b51965c211e..5aa500fe554bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -111,7 +111,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = { static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring); static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring); @@ -1248,6 +1247,13 @@ static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } +static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v5_2_vm_copy_pte, + .write_pte = sdma_v5_2_vm_write_pte, + .set_pte_pde = sdma_v5_2_vm_set_pte_pde, +}; + static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1259,7 +1265,7 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) sdma_v5_2_set_ring_funcs(adev); sdma_v5_2_set_buffer_funcs(adev); - sdma_v5_2_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs); sdma_v5_2_set_irq_funcs(adev); sdma_v5_2_set_mqd_funcs(adev); @@ -2072,27 +2078,6 @@ static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) } } -static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v5_2_vm_copy_pte, - .write_pte = sdma_v5_2_vm_write_pte, - .set_pte_pde = sdma_v5_2_vm_set_pte_pde, -}; - -static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - if (adev->vm_manager.vm_pte_funcs == NULL) { - adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; - } -} - const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 5, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index eec659194718d..45d13ac09f9bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -120,7 +120,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = { static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v6_0_start(struct amdgpu_device *adev); @@ -1280,6 +1279,13 @@ static void sdma_v6_0_get_csa_info(struct amdgpu_device *adev, csa_info->alignment = SDMA6_CSA_ALIGNMENT; } +static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v6_0_vm_copy_pte, + .write_pte = sdma_v6_0_vm_write_pte, + .set_pte_pde = sdma_v6_0_vm_set_pte_pde, +}; + static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1308,7 +1314,7 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v6_0_set_ring_funcs(adev); sdma_v6_0_set_buffer_funcs(adev); - sdma_v6_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); sdma_v6_0_set_irq_funcs(adev); sdma_v6_0_set_mqd_funcs(adev); sdma_v6_0_set_ras_funcs(adev); @@ -1902,25 +1908,6 @@ static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v6_0_vm_copy_pte, - .write_pte = sdma_v6_0_vm_write_pte, - .set_pte_pde = sdma_v6_0_vm_set_pte_pde, -}; - -static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 6, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 8d16ef257bcb9..f938be0524cd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -119,7 +119,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v7_0_start(struct amdgpu_device *adev); @@ -1264,6 +1263,13 @@ static void sdma_v7_0_get_csa_info(struct amdgpu_device *adev, csa_info->alignment = SDMA7_CSA_ALIGNMENT; } +static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { + .copy_pte_num_dw = 8, + .copy_pte = sdma_v7_0_vm_copy_pte, + .write_pte = sdma_v7_0_vm_write_pte, + .set_pte_pde = sdma_v7_0_vm_set_pte_pde, +}; + static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1294,7 +1300,7 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v7_0_set_ring_funcs(adev); sdma_v7_0_set_buffer_funcs(adev); - sdma_v7_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs); sdma_v7_0_set_irq_funcs(adev); sdma_v7_0_set_mqd_funcs(adev); adev->sdma.get_csa_info = &sdma_v7_0_get_csa_info; @@ -1843,25 +1849,6 @@ static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { - .copy_pte_num_dw = 8, - .copy_pte = sdma_v7_0_vm_copy_pte, - .write_pte = sdma_v7_0_vm_write_pte, - .set_pte_pde = sdma_v7_0_vm_set_pte_pde, -}; - -static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 7, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 0824cba48f2e7..3de76afe3e454 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -110,7 +110,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_1[] = { static void sdma_v7_1_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v7_1_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v7_1_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v7_1_inst_start(struct amdgpu_device *adev, uint32_t inst_mask); @@ -1248,6 +1247,13 @@ static void sdma_v7_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } +static const struct amdgpu_vm_pte_funcs sdma_v7_1_vm_pte_funcs = { + .copy_pte_num_dw = 8, + .copy_pte = sdma_v7_1_vm_copy_pte, + .write_pte = sdma_v7_1_vm_write_pte, + .set_pte_pde = sdma_v7_1_vm_set_pte_pde, +}; + static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1261,7 +1267,7 @@ static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block) sdma_v7_1_set_ring_funcs(adev); sdma_v7_1_set_buffer_funcs(adev); - sdma_v7_1_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs); sdma_v7_1_set_irq_funcs(adev); sdma_v7_1_set_mqd_funcs(adev); @@ -1753,25 +1759,6 @@ static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v7_1_vm_pte_funcs = { - .copy_pte_num_dw = 8, - .copy_pte = sdma_v7_1_vm_copy_pte, - .write_pte = sdma_v7_1_vm_write_pte, - .set_pte_pde = sdma_v7_1_vm_set_pte_pde, -}; - -static void sdma_v7_1_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v7_1_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v7_1_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 7, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 74fcaa340d9b1..3e58feb2d5e4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -37,7 +37,6 @@ const u32 sdma_offsets[SDMA_MAX_INSTANCE] = static void si_dma_set_ring_funcs(struct amdgpu_device *adev); static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); -static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); static void si_dma_set_irq_funcs(struct amdgpu_device *adev); /** @@ -473,6 +472,14 @@ static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } +static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { + .copy_pte_num_dw = 5, + .copy_pte = si_dma_vm_copy_pte, + + .write_pte = si_dma_vm_write_pte, + .set_pte_pde = si_dma_vm_set_pte_pde, +}; + static int si_dma_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -481,7 +488,7 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block) si_dma_set_ring_funcs(adev); si_dma_set_buffer_funcs(adev); - si_dma_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs); si_dma_set_irq_funcs(adev); return 0; @@ -830,26 +837,6 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { - .copy_pte_num_dw = 5, - .copy_pte = si_dma_vm_copy_pte, - - .write_pte = si_dma_vm_write_pte, - .set_pte_pde = si_dma_vm_set_pte_pde, -}; - -static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version si_dma_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, From 0f1a117ff4b474ef11e993c96df40d66286f63d9 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Wed, 19 Nov 2025 14:13:00 +0100 Subject: [PATCH 0096/2070] drm/amdgpu: move sched status check inside amdgpu_ttm_set_buffer_funcs_status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It avoids duplicated code and allows to output a warning. --- v4: move check inside the existing if (enable) test --- Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 +++++ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c1ffc63e23ab5..2765f2ddcbeb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3156,9 +3156,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) if (r) goto init_failed; - if (adev->mman.buffer_funcs_ring && - adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); /* Don't init kfd if whole hive need to be reset during init */ if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { @@ -4050,8 +4048,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev) r = amdgpu_device_ip_resume_phase2(adev); - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); if (r) return r; @@ -5197,8 +5194,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) return 0; unwind_evict: - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); amdgpu_fence_driver_hw_init(adev); unwind_userq: @@ -5932,8 +5928,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) if (r) goto out; - if (tmp_adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); + amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); r = amdgpu_device_ip_resume_phase3(tmp_adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5feba7044951c..0977a10679dc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2357,6 +2357,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) struct amdgpu_ring *ring; struct drm_gpu_scheduler *sched; + if (!adev->mman.buffer_funcs_ring || !adev->mman.buffer_funcs_ring->sched.ready) { + dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); + return; + } + ring = adev->mman.buffer_funcs_ring; sched = &ring->sched; r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, From fd753eaa24f5301183c184820702cbe910f1bb26 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 23 Jan 2026 15:37:49 +0800 Subject: [PATCH 0097/2070] drm/amdgpu: add mqd_update callback to AMDGPU user queue interface Extend the AMDGPU user queue function interface to support MQD updates by adding an mqd_update callback. v2: add the input paramter struct drm_amdgpu_userq_in in mqd_update Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 5845d89590346..f4d1d46ae15ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -81,6 +81,8 @@ struct amdgpu_usermode_queue { struct amdgpu_userq_funcs { int (*mqd_create)(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args); + int (*mqd_update)(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args); void (*mqd_destroy)(struct amdgpu_usermode_queue *uq); int (*unmap)(struct amdgpu_usermode_queue *queue); int (*map)(struct amdgpu_usermode_queue *queue); From aba885f00d50d83d6671cd996a5cfed7810af85b Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 23 Jan 2026 19:58:29 +0800 Subject: [PATCH 0098/2070] drm/amd/ras: statistic xgmi training error count Report xgmi training error uncorrectable error count. Change-Id: I9f878cfc8b4e37fb9dfc59b3aed3fe782aa04dbe Signed-off-by: Stanley.Yang Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c index 29df98948703b..210fbd8851a6d 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c @@ -299,7 +299,7 @@ static int aca_parse_xgmi_bank(struct ras_core_context *ras_core, count = ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); if (bank->ecc_type == RAS_ERR_TYPE__UE) { - if (ext_error_code != 0 && ext_error_code != 9) + if (ext_error_code != 0 && ext_error_code != 1 && ext_error_code != 9) count = 0ULL; ecc->ue_count = count; } else if (bank->ecc_type == RAS_ERR_TYPE__CE) { From 48ffed016370caec2a012477459e026eb8a51c40 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 23 Jan 2026 16:39:20 +0800 Subject: [PATCH 0099/2070] drm/amdgpu: Add CU mask support for MQD properties Add new fields to the amdgpu_mqd_prop structure to track CU (Compute Unit) mask information, including the mask itself, count, flags, and a flag to indicate if user-specified CU masking is active. v2: Create a generic function amdgpu_gfx_mqd_symmetrically_map_cu_mask() Suggested-by: Alex Deucher Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 49 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 + 3 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index af4042387f3b1..1f5d15110e43b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -791,6 +791,12 @@ struct amd_powerplay { (rid == 0x01) || \ (rid == 0x10)))) +enum amdgpu_mqd_update_flag { + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ +}; + struct amdgpu_mqd_prop { uint64_t mqd_gpu_addr; uint64_t hqd_base_gpu_addr; @@ -811,6 +817,10 @@ struct amdgpu_mqd_prop { uint64_t fence_address; bool tmz_queue; bool kernel_queue; + uint32_t *cu_mask; + uint32_t cu_mask_count; + uint32_t cu_flags; + bool is_user_cu_masked; }; struct amdgpu_mqd { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 77578ecc67828..cab3196a87fb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -503,6 +503,55 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id) &ring->mqd_ptr); } +void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, + uint32_t cu_mask_count, uint32_t *se_mask) +{ + struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; + struct amdgpu_gfx_config *gfx_info = &adev->gfx.config; + uint32_t cu_per_sh[8][4] = {0}; + int i, se, sh, cu, cu_bitmap_sh_mul; + int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; + bool wgp_mode_req = amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0); + int cu_inc = wgp_mode_req ? 2 : 1; + uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1; + int num_xcc, inc, inst = 0; + + if (xcc_inst < 0) + xcc_inst = 0; + + num_xcc = hweight16(adev->gfx.xcc_mask); + if (!num_xcc) + num_xcc = 1; + + inc = cu_inc * num_xcc; + + cu_bitmap_sh_mul = 2; + + for (se = 0; se < gfx_info->max_shader_engines; se++) + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) + cu_per_sh[se][sh] = hweight32( + cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * + cu_bitmap_sh_mul]); + + for (i = 0; i < gfx_info->max_shader_engines; i++) + se_mask[i] = 0; + + i = inst; + for (cu = 0; cu < 16; cu += cu_inc) { + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { + for (se = 0; se < gfx_info->max_shader_engines; se++) { + if (cu_per_sh[se][sh] > cu) { + if ((i / 32) < cu_mask_count && (cu_mask[i / 32] & (1 << (i % 32)))) + se_mask[se] |= en_mask << (cu + sh * 16); + i += inc; + if (i >= cu_mask_count * 32) + return; + } + } + } + } +} + int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 585cc8e81bb28..720ed3a2c78c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -583,6 +583,8 @@ int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, unsigned mqd_size, int xcc_id); void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); +void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, + uint32_t cu_mask_count, uint32_t *se_mask); int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); From e0cab498e96708166c45f173235c3e45f5d6dc67 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 23 Jan 2026 13:00:13 +0800 Subject: [PATCH 0100/2070] drm/amdgpu/gfx11: add CU mask support for compute MQD initialization Extend the GFX11 compute MQD initialization to support Compute Unit (CU) masking for fine-grained resource allocation. This allows compute queues to be limited to specific CUs for performance isolation and debugging purposes. Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 427975b5a1d97..b1a1b8a10a08b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4238,6 +4238,37 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) return gfx_v11_0_cp_gfx_start(adev); } +static void gfx_v11_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, + struct v11_compute_mqd *mqd, + struct amdgpu_mqd_prop *prop) +{ + uint32_t se_mask[8] = {0}; + uint32_t wa_mask; + bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); + + if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) + return; + + if (has_wa_flag) { + wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? + 0xffff : 0xffffffff; + mqd->compute_static_thread_mgmt_se0 = wa_mask; + mqd->compute_static_thread_mgmt_se1 = wa_mask; + mqd->compute_static_thread_mgmt_se2 = wa_mask; + mqd->compute_static_thread_mgmt_se3 = wa_mask; + return; + } + + amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, + prop->cu_mask_count, se_mask); + + mqd->compute_static_thread_mgmt_se0 = se_mask[0]; + mqd->compute_static_thread_mgmt_se1 = se_mask[1]; + mqd->compute_static_thread_mgmt_se2 = se_mask[2]; + mqd->compute_static_thread_mgmt_se3 = se_mask[3]; +} + static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) { @@ -4372,6 +4403,8 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, /* set UQ fenceaddress */ mqd->fence_address_lo = lower_32_bits(prop->fence_address); mqd->fence_address_hi = upper_32_bits(prop->fence_address); + /* set CU mask */ + gfx_v11_0_compute_mqd_set_cu_mask(adev, mqd, prop); return 0; } From 81fd416d4e3b18b0456b8ff40967510cd6266a97 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 23 Jan 2026 13:05:29 +0800 Subject: [PATCH 0101/2070] drm/amdgpu/gfx12: add CU mask support for compute MQD initialization Extend the GFX12 compute MQD initialization to support Compute Unit (CU) masking for fine-grained resource allocation. This allows compute queues to be limited to specific CUs for performance isolation and debugging purposes. Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 79ea1af363a53..a418ae609c363 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3109,6 +3109,37 @@ static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) return gfx_v12_0_cp_gfx_start(adev); } +static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, + struct v12_compute_mqd *mqd, + struct amdgpu_mqd_prop *prop) +{ + uint32_t se_mask[8] = {0}; + uint32_t wa_mask; + bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); + + if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) + return; + + if (has_wa_flag) { + wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? + 0xffff : 0xffffffff; + mqd->compute_static_thread_mgmt_se0 = wa_mask; + mqd->compute_static_thread_mgmt_se1 = wa_mask; + mqd->compute_static_thread_mgmt_se2 = wa_mask; + mqd->compute_static_thread_mgmt_se3 = wa_mask; + return; + } + + amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, + prop->cu_mask_count, se_mask); + + mqd->compute_static_thread_mgmt_se0 = se_mask[0]; + mqd->compute_static_thread_mgmt_se1 = se_mask[1]; + mqd->compute_static_thread_mgmt_se2 = se_mask[2]; + mqd->compute_static_thread_mgmt_se3 = se_mask[3]; +} + static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) { @@ -3242,6 +3273,8 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, /* set UQ fenceaddress */ mqd->fence_address_lo = lower_32_bits(prop->fence_address); mqd->fence_address_hi = upper_32_bits(prop->fence_address); + /* set CU mask */ + gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop); return 0; } From be203a8e80d84b07ae80d163ac9eb4e0447a3463 Mon Sep 17 00:00:00 2001 From: Zilin Guan Date: Thu, 29 Jan 2026 09:25:32 +0000 Subject: [PATCH 0102/2070] drm/amdgpu: Fix memory leak in amdgpu_acpi_enumerate_xcc() In amdgpu_acpi_enumerate_xcc(), if amdgpu_acpi_dev_init() returns -ENOMEM, the function returns directly without releasing the allocated xcc_info, resulting in a memory leak. Fix this by ensuring that xcc_info is properly freed in the error paths. Compile tested only. Issue found using a prototype static analysis tool and code review. Fixes: 4d5275ab0b18 ("drm/amdgpu: Add parsing of acpi xcc objects") Reviewed-by: Lijo Lazar Signed-off-by: Zilin Guan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index c126d1bf2bc83..02d5abf9df2ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1186,8 +1186,10 @@ int amdgpu_acpi_enumerate_xcc(void) if (!dev_info) ret = amdgpu_acpi_dev_init(&dev_info, xcc_info, sbdf); - if (ret == -ENOMEM) + if (ret == -ENOMEM) { + kfree(xcc_info); return ret; + } if (!dev_info) { kfree(xcc_info); From ddd65c39cc45adf666149ba35104ce2064716779 Mon Sep 17 00:00:00 2001 From: Zilin Guan Date: Thu, 29 Jan 2026 09:05:42 +0000 Subject: [PATCH 0103/2070] drm/amdgpu: Use kvfree instead of kfree in amdgpu_gmc_get_nps_memranges() amdgpu_discovery_get_nps_info() internally allocates memory for ranges using kvcalloc(), which may use vmalloc() for large allocation. Using kfree() to release vmalloc memory will lead to a memory corruption. Use kvfree() to safely handle both kmalloc and vmalloc allocations. Compile tested only. Issue found using a prototype static analysis tool and code review. Fixes: b194d21b9bcc ("drm/amdgpu: Use NPS ranges from discovery table") Reviewed-by: Lijo Lazar Signed-off-by: Zilin Guan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index e87cb8ccfcd9b..3709ec26708d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1436,7 +1436,7 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, if (!*exp_ranges) *exp_ranges = range_cnt; err: - kfree(ranges); + kvfree(ranges); return ret; } From 748ae168b473e1dffe99e5017a9ed8d3484ecd1c Mon Sep 17 00:00:00 2001 From: Zilin Guan Date: Thu, 29 Jan 2026 08:35:15 +0000 Subject: [PATCH 0104/2070] drm/amdgpu: Fix memory leak in amdgpu_ras_init() When amdgpu_nbio_ras_sw_init() fails in amdgpu_ras_init(), the function returns directly without freeing the allocated con structure, leading to a memory leak. Fix this by jumping to the release_con label to properly clean up the allocated memory before returning the error code. Compile tested only. Issue found using a prototype static analysis tool and code review. Fixes: fdc94d3a8c88 ("drm/amdgpu: Rework pcie_bif ras sw_init") Reviewed-by: Tao Zhou Signed-off-by: Zilin Guan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index f582113d78b74..b28fcf932f7ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4352,7 +4352,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) * to handle fatal error */ r = amdgpu_nbio_ras_sw_init(adev); if (r) - return r; + goto release_con; if (adev->nbio.ras && adev->nbio.ras->init_ras_controller_interrupt) { From c66ddb0c824dc9aabc020cc6a54113bbe8d74a77 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 3 Feb 2026 11:51:45 -0500 Subject: [PATCH 0105/2070] drm/amdgpu/sdma5: enable queue resets unconditionally There is no firmware version dependency. Fixes: 59fd50b8663b ("drm/amdgpu: Add sysfs interface for sdma reset mask") Cc: Jesse Zhang Reviewed-by: Jesse.Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index d72bd3adfccf1..52f4e9e099cbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1430,18 +1430,9 @@ static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { - case IP_VERSION(5, 0, 0): - case IP_VERSION(5, 0, 2): - case IP_VERSION(5, 0, 5): - if ((adev->sdma.instance[0].fw_version >= 35) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - default: - break; - } + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; /* Allocate memory for SDMA IP Dump buffer */ ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); From 38777c3ca57948ef2449fad60e6274d0dfd6d623 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 3 Feb 2026 11:52:46 -0500 Subject: [PATCH 0106/2070] drm/amdgpu/sdma5.2: enable queue resets unconditionally There is no firmware version dependency. This also enables sdma queue resets on all SDMA 5.2.x based chips. Fixes: 59fd50b8663b ("drm/amdgpu: Add sysfs interface for sdma reset mask") Cc: Jesse Zhang Reviewed-by: Jesse.Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 5aa500fe554bc..0a8269795241d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1348,25 +1348,9 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { - case IP_VERSION(5, 2, 0): - case IP_VERSION(5, 2, 2): - case IP_VERSION(5, 2, 3): - case IP_VERSION(5, 2, 4): - if ((adev->sdma.instance[0].fw_version >= 76) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - case IP_VERSION(5, 2, 5): - if ((adev->sdma.instance[0].fw_version >= 34) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - default: - break; - } + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; /* Allocate memory for SDMA IP Dump buffer */ ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); From e5cb3af5e8b64e12632b7b1933398e5688eda903 Mon Sep 17 00:00:00 2001 From: Sunday Clement Date: Mon, 2 Feb 2026 12:41:39 -0500 Subject: [PATCH 0107/2070] drm/amdkfd: Fix out-of-bounds write in kfd_event_page_set() The kfd_event_page_set() function writes KFD_SIGNAL_EVENT_LIMIT * 8 bytes via memset without checking the buffer size parameter. This allows unprivileged userspace to trigger an out-of bounds kernel memory write by passing a small buffer, leading to potential privilege escalation. Signed-off-by: Sunday Clement Reviewed-by: Alexander Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 1ad312af8ff0c..13416bff77636 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -331,6 +331,12 @@ static int kfd_event_page_set(struct kfd_process *p, void *kernel_address, if (p->signal_page) return -EBUSY; + if (size < KFD_SIGNAL_EVENT_LIMIT * 8) { + pr_err("Event page size %llu is too small, need at least %lu bytes\n", + size, (unsigned long)(KFD_SIGNAL_EVENT_LIMIT * 8)); + return -EINVAL; + } + page = kzalloc(sizeof(*page), GFP_KERNEL); if (!page) return -ENOMEM; From f431c7df279301b168f13e19a1a940eb0127e9aa Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 2 Feb 2026 13:17:39 +0800 Subject: [PATCH 0108/2070] drm/amdgpu: Protect GPU register accesses in powergated state in some paths Ungate GPU CG/PG in device_fini_hw and device_halt to protect GPU register accesses, e.g. GC registers are accessed in amdgpu_irq_disable_all() and amdgpu_fence_driver_hw_fini(). Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2765f2ddcbeb5..78fe4f3857934 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3502,9 +3502,6 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) } } - amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); - amdgpu_amdkfd_suspend(adev, true); amdgpu_amdkfd_teardown_processes(adev); amdgpu_userq_suspend(adev); @@ -4899,6 +4896,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_virt_fini_data_exchange(adev); } + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); + /* disable all interrupts */ amdgpu_irq_disable_all(adev); if (adev->mode_info.mode_config_initialized) { @@ -7355,6 +7355,9 @@ void amdgpu_device_halt(struct amdgpu_device *adev) amdgpu_xcp_dev_unplug(adev); drm_dev_unplug(ddev); + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); + amdgpu_irq_disable_all(adev); amdgpu_fence_driver_hw_fini(adev); From a4722360543c60549950da639d736c43bc6be274 Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Tue, 9 Dec 2025 12:09:06 -0300 Subject: [PATCH 0109/2070] drm/amd/display: expose plane blend LUT in HW with MCM Since commit 39923050615cd ("drm/amd/display: Clear DPP 3DLUT Cap") there is a flag in the mpc_color_caps that indicates the pre-blend usage of MPC color caps. Do the same as commit a0c3e8bfbab6 ("drm/amd/display: Use mpc.preblend flag to indicate preblend") and use the mpc.preblend flag to expose plane blend LUT/TF properties on AMD display driver. CC: Matthew Schwartz Signed-off-by: Melissa Wen Tested-by: Matthew Schwartz Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index d3e62f511c8f5..ce56734c09b86 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1650,7 +1650,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, MAX_COLOR_3DLUT_SIZE); } - if (dpp_color_caps.ogam_ram) { + if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) { drm_object_attach_property(&plane->base, mode_info.plane_blend_lut_property, 0); drm_object_attach_property(&plane->base, From 55e44842e70e745d685c2d6fbf5ae27339e8836b Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 27 Jan 2026 13:52:33 -0500 Subject: [PATCH 0110/2070] drm/amdgpu: Use 5-level paging if gmc support 57-bit VA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Regardless if CPU enable 5-level paging, GPU vm use 5-level paging if gmc init with 57-bit address space support, because ARM64 4-level paging support 48-bit VA, x86 and GPU 4-level paging support 47-bit VA, require 5-level paging on GPU to support ARM64. NPA address space 52-bit mapping on NPA GPU VM require 5-level paging. Debugger trap get device snapshot expect LDS and Scratch base, limit above 57-bit, which is set only for 5-level paging. Signed-off-by: Philip Yang Reviewed-by: Christian König Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 24c1f95ec5072..807f8bcc7de52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2360,26 +2360,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, unsigned max_bits) { unsigned int max_size = 1 << (max_bits - 30); - bool sys_5level_pgtable = false; unsigned int vm_size; uint64_t tmp; -#ifdef CONFIG_X86_64 - /* - * Refer to function configure_5level_paging() for details. - */ - sys_5level_pgtable = (native_read_cr4() & X86_CR4_LA57); -#endif - - /* - * If GPU supports 5-level page table, but system uses 4-level page table, - * then use 4-level page table on GPU - */ - if (max_level == 4 && !sys_5level_pgtable) { - min_vm_size = 256 * 1024; - max_level = 3; - } - /* adjust vm size first */ if (amdgpu_vm_size != -1) { vm_size = amdgpu_vm_size; From 164550ea5c0fad475ff17ea704ab61a2e3013047 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 3 Feb 2026 12:09:05 +0530 Subject: [PATCH 0111/2070] drm/amdgpu: clean up the amdgpu_cs_parser_bos MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In low memory conditions, kmalloc can fail. In such conditions unlock the mutex for a clean exit. We do not need to amdgpu_bo_list_put as it's been handled in the amdgpu_cs_parser_fini. Fixes: 737da5363cc0 ("drm/amdgpu: update the functions to use amdgpu version of hmm") Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202602030017.7E0xShmH-lkp@intel.com/ Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index d591dce0f3b3c..f3b5bcdbf2ae6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -892,8 +892,10 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo = e->bo; e->range = amdgpu_hmm_range_alloc(NULL); - if (unlikely(!e->range)) - return -ENOMEM; + if (unlikely(!e->range)) { + r = -ENOMEM; + goto out_free_user_pages; + } r = amdgpu_ttm_tt_get_user_pages(bo, e->range); if (r) From 83719581bdc37c6538d7da887bf5bb48f3bfb439 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 27 Jan 2026 13:18:19 +0800 Subject: [PATCH 0112/2070] drm/amdgpu: add MQD update support for user mode compute queues The update functionality allows dynamic adjustment of queue properties at runtime, enabling better resource management and performance tuning for compute workloads. v2: Return an error for non-compute queues. (Alex) remove the parameter minfo V3: put the new paramters in drm_amdgpu_userq_mqd_compute_gfx11. (Alex) v4: move the define AMDGPU_USERQ_OP_MODIFY to patch 6/6 (Alex) add the props input parameter to amdgpu_userq_set_compute_mqd Reviewed-by: Alex Deucher Suggested-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 166 ++++++++++++++++++++- include/uapi/drm/amdgpu_drm.h | 28 ++++ 3 files changed, 194 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1f5d15110e43b..057c8bd2ad89e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -821,6 +821,9 @@ struct amdgpu_mqd_prop { uint32_t cu_mask_count; uint32_t cu_flags; bool is_user_cu_masked; + uint32_t queue_percentage; + /* used in gfx9 and gfx12.1 */ + uint32_t pm4_target_xcc; }; struct amdgpu_mqd { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 9508709abd49a..f4b3073cf9683 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -30,6 +30,26 @@ #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE +/* Mapping queue priority to pipe priority, indexed by queue priority */ +int amdgpu_userq_pipe_priority_map[] = { + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_0, + AMDGPU_RING_PRIO_1, + AMDGPU_RING_PRIO_1, + AMDGPU_RING_PRIO_1, + AMDGPU_RING_PRIO_1, + AMDGPU_RING_PRIO_2, + AMDGPU_RING_PRIO_2, + AMDGPU_RING_PRIO_2, + AMDGPU_RING_PRIO_2, + AMDGPU_RING_PRIO_2 +}; + static int mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo) { @@ -272,6 +292,105 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, return r; } +/** + * amdgpu_userq_set_compute_mqd - Parse compute MQD and update queue props + * @queue: Target user mode queue + * @props: Queue property structure to be updated + * @args: User queue input arguments + * @uq_mgr: User queue manager (for logging) + * + * This function only parses and validates user input, updating queue props + * (no hardware MQD configuration - that's handled in MES layer) + * Returns: 0 on success, negative error code on failure + */ +static int amdgpu_userq_set_compute_mqd(struct amdgpu_usermode_queue *queue, + struct amdgpu_mqd_prop *props, + struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd) +{ + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; + struct amdgpu_device *adev = uq_mgr->adev; + const int max_num_cus = 1024; + size_t cu_mask_size; + uint32_t count; + uint32_t *cu_mask = NULL; + int ret = 0; + + if (!queue || !props || !compute_mqd) + return -EINVAL; + + if (compute_mqd->queue_percentage > AMDGPU_USERQ_MAX_QUEUE_PERCENTAGE) { + DRM_ERROR("Queue percentage must be between 0 to AMDGPU_USERQ_MAX_QUEUE_PERCENTAGE.\n"); + return -EINVAL; + } + + /* Validate priority */ + if (compute_mqd->hqd_queue_priority > AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) { + DRM_ERROR("Queue priority must be between 0 to AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM.\n"); + return -EINVAL; + } + + + /* validate and set CU mask property */ + if (compute_mqd->cu_mask_count) { + if (compute_mqd->cu_mask_count % 32 != 0) { + DRM_ERROR("CU mask count must be a multiple of 32.\n"); + return -EINVAL; + } + count = compute_mqd->cu_mask_count; + + /* Limit CU mask size to prevent excessive memory allocation */ + if (count > max_num_cus) { + DRM_ERROR("CU mask cannot be greater than 1024 bits.\n"); + count = max_num_cus; + cu_mask_size = sizeof(uint32_t) * (max_num_cus / 32); + } else { + cu_mask_size = sizeof(uint32_t) * (compute_mqd->cu_mask_count / 32); + } + + /* Copy CU mask from user space */ + cu_mask = memdup_user(u64_to_user_ptr(compute_mqd->cu_mask_ptr), cu_mask_size); + if (IS_ERR(cu_mask)) { + ret = PTR_ERR(cu_mask); + cu_mask = NULL; + goto cleanup; + } + + /* Validate pairwise CU mask for WGP-based ASICs */ + if (cu_mask && adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) { + for (int i = 0; i < count; i += 2) { + uint32_t cu_pair = (cu_mask[i / 32] >> (i % 32)) & 0x3; + if (cu_pair && cu_pair != 0x3) { + DRM_ERROR("CUs must be adjacent pairwise enabled.\n"); + kfree(cu_mask); + cu_mask = NULL; + ret = -EINVAL; + goto cleanup; + } + } + } + + /* Free old CU mask */ + if (props->cu_mask) { + kfree(props->cu_mask); + props->cu_mask = NULL; + } + + props->cu_mask = cu_mask; + props->cu_mask_count = count; + props->is_user_cu_masked = (cu_mask != NULL); + } + + /* Parse HQD priority and other compute properties */ + props->queue_percentage = compute_mqd->queue_percentage; + props->pm4_target_xcc = compute_mqd->pm4_target_xcc; + props->hqd_queue_priority = compute_mqd->hqd_queue_priority; + props->hqd_pipe_priority = amdgpu_userq_pipe_priority_map[compute_mqd->hqd_queue_priority]; + props->eop_gpu_addr = compute_mqd->eop_va; + +cleanup: + return ret; +} + static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args_in) { @@ -326,10 +445,10 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 2048); if (r) goto free_mqd; + r = amdgpu_userq_set_compute_mqd(queue, userq_props, compute_mqd); + if (r) + goto free_mqd; - userq_props->eop_gpu_addr = compute_mqd->eop_va; - userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; - userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; userq_props->hqd_active = false; userq_props->tmz_queue = mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; @@ -433,11 +552,51 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, return r; } +static int mes_userq_mqd_update(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args_in) +{ + int retval = 0; + struct amdgpu_device *adev = queue->userq_mgr->adev; + struct amdgpu_mqd_prop *userq_props = queue->userq_prop; + struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; + struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd_v11; + + if (!queue || !userq_props) + return -EINVAL; + + if (queue->queue_type != AMDGPU_HW_IP_COMPUTE) + return -EINVAL; + + if (args_in->mqd_size != sizeof(*compute_mqd_v11)) { + DRM_ERROR("Invalid compute IP MQD size\n"); + return -EINVAL; + } + + compute_mqd_v11 = memdup_user(u64_to_user_ptr(args_in->mqd), args_in->mqd_size); + if (IS_ERR(compute_mqd_v11)) { + DRM_ERROR("Failed to read user MQD\n"); + return -ENOMEM; + } + + retval = amdgpu_userq_set_compute_mqd(queue, userq_props, compute_mqd_v11); + if (retval) + goto free; + + userq_props->queue_size = args_in->queue_size; + userq_props->hqd_base_gpu_addr = args_in->queue_va; + + retval = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); + +free: + kfree(compute_mqd_v11); + return retval; +} + static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) { struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); + kfree(queue->userq_prop->cu_mask); kfree(queue->userq_prop); amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); } @@ -514,6 +673,7 @@ static int mes_userq_restore(struct amdgpu_usermode_queue *queue) const struct amdgpu_userq_funcs userq_mes_funcs = { .mqd_create = mes_userq_mqd_create, + .mqd_update = mes_userq_mqd_update, .mqd_destroy = mes_userq_mqd_destroy, .unmap = mes_userq_unmap, .map = mes_userq_map, diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 1d34daa0ebcd5..fb3df55d382a9 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -341,6 +341,7 @@ union drm_amdgpu_ctx { #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ /* for queues that need access to protected content */ #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) +#define AMDGPU_USERQ_MAX_QUEUE_PERCENTAGE 100 /* * This structure is a container to pass input configuration @@ -460,6 +461,33 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 { * to get the size. */ __u64 eop_va; + /** + * @cu_mask_ptr: User-space pointer to CU (Compute Unit) mask array + * Points to an array of __u32 values that define which CUs are enabled + * for this queue (0 = disabled, 1 = enabled per bit) + */ + __u64 cu_mask_ptr; + /** + * @cu_mask_count: Number of entries in the CU mask array + * Total count of __u32 elements in the cu_mask_ptr array (each element + * represents 32 CUs/WGPs) + */ + __u32 cu_mask_count; + /** + * @queue_percentage: Queue resource allocation percentage (0-100) + * Defines the percentage of GPU resources allocated to this queue + */ + __u32 queue_percentage; + /** + * @hqd_queue_priority: Hqd Queue priority (0-15) + * Higher values indicate higher scheduling priority for the queue + */ + __u32 hqd_queue_priority; + /** + * @pm4_target_xcc: PM4 target XCC identifier (for gfx9/gfx12.1) + * Specifies the target XCC (Cross Compute Complex) for PM4 commands + */ + __u32 pm4_target_xcc; }; /* userq signal/wait ioctl */ From ff7aebe31edac6b0187f5669b2e45c613beed9ad Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Wed, 4 Feb 2026 23:15:04 +0800 Subject: [PATCH 0113/2070] drm/amdgpu: avoid sdma ring reset in sriov sdma ring reset is not supported in SRIOV. kfd driver does not check reset mask, and could queue sdma ring reset during unmap_queues_cpsch. Avoid the ring reset for sriov. Signed-off-by: Victor Zhao Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 8b8a04138711c..321310ba2c08e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -558,6 +558,9 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, struct amdgpu_ring *gfx_ring = &sdma_instance->ring; struct amdgpu_ring *page_ring = &sdma_instance->page; + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + mutex_lock(&sdma_instance->engine_reset_mutex); if (!caller_handles_kernel_queues) { From 989fff935a94c579229b35238e0ada759c2df009 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 28 Jan 2026 09:46:19 +0800 Subject: [PATCH 0114/2070] drm/amdgpu: add MODIFY operation for compute queues Implement the AMDGPU_USERQ_OP_MODIFY ioctl operation to enable runtime updates of compute queues. v2: move queue size validate to a separate patch remove the check for AMDGPU_HW_IP_COMPUTE (Alex) Suggested-by: Alex Deucher Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 61 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 3 ++ include/uapi/drm/amdgpu_drm.h | 1 + 3 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b700c2b914654..1a9399379650c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -906,6 +906,7 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, switch (args->in.op) { case AMDGPU_USERQ_OP_CREATE: + case AMDGPU_USERQ_OP_MODIFY: if (args->in.flags & ~(AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK | AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE)) return -EINVAL; @@ -981,6 +982,60 @@ bool amdgpu_userq_enabled(struct drm_device *dev) return false; } +static int amdgpu_modify_queue(struct drm_file *filp, union drm_amdgpu_userq *args) +{ + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_usermode_queue *queue; + const struct amdgpu_userq_funcs *userq_funcs; + int r; + + mutex_lock(&uq_mgr->userq_mutex); + queue = amdgpu_userq_find(uq_mgr, args->in.queue_id); + if (!queue) { + drm_file_err(uq_mgr->file, "Queue %u not found\n", args->in.queue_id); + r = -EINVAL; + goto unlock; + } + + userq_funcs = adev->userq_funcs[queue->queue_type]; + + /* + * Unmap the queue if it's mapped or preempted to ensure a clean update. + * If the queue is already unmapped or hung, we skip this step. + */ + if (queue->state == AMDGPU_USERQ_STATE_MAPPED || + queue->state == AMDGPU_USERQ_STATE_PREEMPTED) { + r = amdgpu_userq_unmap_helper(queue); + if (r) { + drm_file_err(uq_mgr->file, "Failed to unmap queue %llu\n", + queue->doorbell_index); + goto unlock; + } + } + + r = userq_funcs->mqd_update(queue, &args->in); + if (r) + goto unlock; + /* + * If the queue is considered active (has valid size, address, and percentage), + * we attempt to map it. This effectively starts the queue or restarts it + * if it was previously running. + */ + if (AMDGPU_USERQ_IS_ACTIVE(queue)) { + r = amdgpu_userq_map_helper(queue); + if (r) + drm_file_err(uq_mgr->file, "Failed to remap queue %llu after update\n", + queue->doorbell_index); + } + +unlock: + mutex_unlock(&uq_mgr->userq_mutex); + + return r; +} + int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -1000,6 +1055,12 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, drm_file_err(filp, "Failed to create usermode queue\n"); break; + + case AMDGPU_USERQ_OP_MODIFY: + r = amdgpu_modify_queue(filp, args); + if (r) + drm_file_err(filp, "Failed to modify usermode queue\n"); + break; case AMDGPU_USERQ_OP_FREE: r = amdgpu_userq_destroy(filp, args->in.queue_id); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index f4d1d46ae15ec..91d26c251314a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -31,6 +31,9 @@ #define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base) #define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr) #define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name) +#define AMDGPU_USERQ_IS_ACTIVE(q) ((q)->userq_prop->queue_size > 0 && \ + (q)->userq_prop->hqd_base_gpu_addr != 0 && \ + (q)->userq_prop->queue_percentage > 0) enum amdgpu_userq_state { AMDGPU_USERQ_STATE_UNMAPPED = 0, diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index fb3df55d382a9..337dafcb5a52a 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -330,6 +330,7 @@ union drm_amdgpu_ctx { /* user queue IOCTL operations */ #define AMDGPU_USERQ_OP_CREATE 1 #define AMDGPU_USERQ_OP_FREE 2 +#define AMDGPU_USERQ_OP_MODIFY 3 /* queue priority levels */ /* low < normal low < normal high < high */ From d7021d6c7b8aa108a6f70c234c09e22132502f75 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 3 Feb 2026 11:53:51 -0500 Subject: [PATCH 0115/2070] drm/amdgpu/sdma6: enable queue resets unconditionally There is no firmware version dependency. This also enables sdma queue resets on all SDMA 6.x based chips. Fixes: 59fd50b8663b ("drm/amdgpu: Add sysfs interface for sdma reset mask") Cc: Jesse Zhang Reviewed-by: Jesse.Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 45d13ac09f9bb..2643364328498 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1370,18 +1370,9 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { - case IP_VERSION(6, 0, 0): - case IP_VERSION(6, 0, 2): - case IP_VERSION(6, 0, 3): - if ((adev->sdma.instance[0].fw_version >= 21) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - default: - break; - } + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; if (amdgpu_sdma_ras_sw_init(adev)) { dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); From eccc5dd17af14ec1650f5a9ed4d602d2e43933c2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 30 Jan 2026 11:19:49 -0500 Subject: [PATCH 0116/2070] drm/amdgpu: re-add the bad job to the pending list for ring resets Returning DRM_GPU_SCHED_STAT_NO_HANG causes the scheduler to add the bad job back the pending list. We've already set the errors on the fence and killed the bad job at this point so it's the correct behavior. Acked-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 9 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index aaf5477fcd7ac..2c82d9e8c0be1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -92,6 +92,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) struct drm_wedge_task_info *info = NULL; struct amdgpu_task_info *ti = NULL; struct amdgpu_device *adev = ring->adev; + enum drm_gpu_sched_stat status = DRM_GPU_SCHED_STAT_RESET; int idx, r; if (!drm_dev_enter(adev_to_drm(adev), &idx)) { @@ -135,13 +136,19 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) ring->funcs->reset) { dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); + /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ + drm_sched_wqueue_stop(&ring->sched); r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); if (!r) { + /* Start the scheduler again */ + drm_sched_wqueue_start(&ring->sched); atomic_inc(&ring->adev->gpu_reset_counter); dev_err(adev->dev, "Ring %s reset succeeded\n", ring->sched.name); drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, info); + /* This is needed to add the job back to the pending list */ + status = DRM_GPU_SCHED_STAT_NO_HANG; goto exit; } dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); @@ -177,7 +184,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) exit: amdgpu_vm_put_task_info(ti); drm_dev_exit(idx); - return DRM_GPU_SCHED_STAT_RESET; + return status; } int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index b82357c657237..129ad51386535 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -868,8 +868,6 @@ bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence) { - /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ - drm_sched_wqueue_stop(&ring->sched); /* back up the non-guilty commands */ amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence); } @@ -895,8 +893,6 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, amdgpu_ring_write(ring, ring->ring_backup[i]); amdgpu_ring_commit(ring); } - /* Start the scheduler again */ - drm_sched_wqueue_start(&ring->sched); return 0; } From c229158681edf3da3038c9ae2da15fe36b8bb25c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 5 Feb 2026 10:42:54 -0600 Subject: [PATCH 0117/2070] drm/amd: Fix hang on amdgpu unload by using pci_dev_is_disconnected() The commit 28695ca09d32 ("drm/amd: Clean up kfd node on surprise disconnect") introduced early KFD cleanup when drm_dev_is_unplugged() returns true. However, this causes hangs during normal module unload (rmmod amdgpu). The issue occurs because drm_dev_unplug() is called in amdgpu_pci_remove() for all removal scenarios, not just surprise disconnects. This was done intentionally in commit 39934d3ed5725c ("Revert "drm/amdgpu: TA unload messages are not actually sent to psp when amdgpu is uninstalled"") to fix IGT PCI software unplug test failures. As a result, drm_dev_is_unplugged() returns true even during normal module unload, triggering the early KFD cleanup inappropriately. The correct check should distinguish between: - Actual surprise disconnect (eGPU unplugged): pci_dev_is_disconnected() returns true - Normal module unload (rmmod): pci_dev_is_disconnected() returns false Replace drm_dev_is_unplugged() with pci_dev_is_disconnected() to ensure the early cleanup only happens during true hardware disconnect events. Cc: stable@vger.kernel.org Reported-by: Cal Peake Closes: https://lore.kernel.org/all/b0c22deb-c0fa-3343-33cf-fd9a77d7db99@absolutedigital.net/ Fixes: 28695ca09d32 ("drm/amd: Clean up kfd node on surprise disconnect") Acked-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 78fe4f3857934..38169ab7dafd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4921,7 +4921,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) * before ip_fini_early to prevent kfd locking refcount issues by calling * amdgpu_amdkfd_suspend() */ - if (drm_dev_is_unplugged(adev_to_drm(adev))) + if (pci_dev_is_disconnected(adev->pdev)) amdgpu_amdkfd_device_fini_sw(adev); amdgpu_device_ip_fini_early(adev); @@ -4933,7 +4933,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_gart_dummy_page_fini(adev); - if (drm_dev_is_unplugged(adev_to_drm(adev))) + if (pci_dev_is_disconnected(adev->pdev)) amdgpu_device_unmap_mmio(adev); } From 6c470a9bb431339c609a5d6340d25572af9abf25 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 3 Feb 2026 09:48:23 -0500 Subject: [PATCH 0118/2070] drm/amdgpu: Send applicable RMA CPERs at end of RAS init Firmware and monitoring tools may not be ready to receive a CPER when we read the bad pages, so send the CPERs at the end of RAS initialization to ensure that the FW is ready to receive and process the CPER. This removes the previous CPER submission that was added during bad page load, and sends both in-band and out-of-band at the same time. Signed-off-by: Kent Russell Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 ++ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 27 ++++++++++++++++--- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 2 ++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b28fcf932f7ea..856b1bf83533d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4650,6 +4650,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); } + amdgpu_ras_check_bad_page_status(adev); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 469d04a39d7d0..2c5d7f87e593e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1712,10 +1712,6 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", control->ras_num_bad_pages, ras->bad_page_cnt_threshold); - if (amdgpu_bad_page_threshold != 0 && - control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) - amdgpu_dpm_send_rma_reason(adev); - } else if (hdr->header == RAS_TABLE_HDR_BAD && amdgpu_bad_page_threshold != 0) { if (hdr->version >= RAS_TABLE_VER_V2_1) { @@ -1932,3 +1928,26 @@ int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, result); return -EOPNOTSUPP; } + +void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) +{ + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; + + if (!control || amdgpu_bad_page_threshold == 0) + return; + + if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { + if (amdgpu_dpm_send_rma_reason(adev)) + dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); + else + dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); + + if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { + if (amdgpu_cper_generate_bp_threshold_record(adev)) + dev_warn(adev->dev, "Unable to send in-band RMA CPER"); + else + dev_dbg(adev->dev, "Sent in-band RMA CPER"); + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index 2e5d63957e714..a62114800a92a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -193,6 +193,8 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control); +void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; From d115010664a3b46556e0b33710dc58fb60687b58 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 5 Feb 2026 17:33:25 -0500 Subject: [PATCH 0119/2070] Revert "drm/amdgpu: add MODIFY operation for compute queues" This reverts commit 2ea8650f4982ca99bef22f6ffd70733ba4e6030b. The was applied to the wrong branch. The userspace is not ready yet. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 61 ----------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 3 -- include/uapi/drm/amdgpu_drm.h | 1 - 3 files changed, 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 1a9399379650c..b700c2b914654 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -906,7 +906,6 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, switch (args->in.op) { case AMDGPU_USERQ_OP_CREATE: - case AMDGPU_USERQ_OP_MODIFY: if (args->in.flags & ~(AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK | AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE)) return -EINVAL; @@ -982,60 +981,6 @@ bool amdgpu_userq_enabled(struct drm_device *dev) return false; } -static int amdgpu_modify_queue(struct drm_file *filp, union drm_amdgpu_userq *args) -{ - struct amdgpu_fpriv *fpriv = filp->driver_priv; - struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; - struct amdgpu_device *adev = uq_mgr->adev; - struct amdgpu_usermode_queue *queue; - const struct amdgpu_userq_funcs *userq_funcs; - int r; - - mutex_lock(&uq_mgr->userq_mutex); - queue = amdgpu_userq_find(uq_mgr, args->in.queue_id); - if (!queue) { - drm_file_err(uq_mgr->file, "Queue %u not found\n", args->in.queue_id); - r = -EINVAL; - goto unlock; - } - - userq_funcs = adev->userq_funcs[queue->queue_type]; - - /* - * Unmap the queue if it's mapped or preempted to ensure a clean update. - * If the queue is already unmapped or hung, we skip this step. - */ - if (queue->state == AMDGPU_USERQ_STATE_MAPPED || - queue->state == AMDGPU_USERQ_STATE_PREEMPTED) { - r = amdgpu_userq_unmap_helper(queue); - if (r) { - drm_file_err(uq_mgr->file, "Failed to unmap queue %llu\n", - queue->doorbell_index); - goto unlock; - } - } - - r = userq_funcs->mqd_update(queue, &args->in); - if (r) - goto unlock; - /* - * If the queue is considered active (has valid size, address, and percentage), - * we attempt to map it. This effectively starts the queue or restarts it - * if it was previously running. - */ - if (AMDGPU_USERQ_IS_ACTIVE(queue)) { - r = amdgpu_userq_map_helper(queue); - if (r) - drm_file_err(uq_mgr->file, "Failed to remap queue %llu after update\n", - queue->doorbell_index); - } - -unlock: - mutex_unlock(&uq_mgr->userq_mutex); - - return r; -} - int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -1055,12 +1000,6 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, drm_file_err(filp, "Failed to create usermode queue\n"); break; - - case AMDGPU_USERQ_OP_MODIFY: - r = amdgpu_modify_queue(filp, args); - if (r) - drm_file_err(filp, "Failed to modify usermode queue\n"); - break; case AMDGPU_USERQ_OP_FREE: r = amdgpu_userq_destroy(filp, args->in.queue_id); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 91d26c251314a..f4d1d46ae15ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -31,9 +31,6 @@ #define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base) #define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr) #define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name) -#define AMDGPU_USERQ_IS_ACTIVE(q) ((q)->userq_prop->queue_size > 0 && \ - (q)->userq_prop->hqd_base_gpu_addr != 0 && \ - (q)->userq_prop->queue_percentage > 0) enum amdgpu_userq_state { AMDGPU_USERQ_STATE_UNMAPPED = 0, diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 337dafcb5a52a..fb3df55d382a9 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -330,7 +330,6 @@ union drm_amdgpu_ctx { /* user queue IOCTL operations */ #define AMDGPU_USERQ_OP_CREATE 1 #define AMDGPU_USERQ_OP_FREE 2 -#define AMDGPU_USERQ_OP_MODIFY 3 /* queue priority levels */ /* low < normal low < normal high < high */ From a24879cc0135d30b70bea467f19806d7012a375f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 5 Feb 2026 17:34:14 -0500 Subject: [PATCH 0120/2070] Revert "drm/amdgpu: add MQD update support for user mode compute queues" This reverts commit a8941e6c6737452bdfead0a6972890c5ca3a4831. The was applied to the wrong branch. The userspace is not ready yet. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 - drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 166 +-------------------- include/uapi/drm/amdgpu_drm.h | 28 ---- 3 files changed, 3 insertions(+), 194 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 057c8bd2ad89e..1f5d15110e43b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -821,9 +821,6 @@ struct amdgpu_mqd_prop { uint32_t cu_mask_count; uint32_t cu_flags; bool is_user_cu_masked; - uint32_t queue_percentage; - /* used in gfx9 and gfx12.1 */ - uint32_t pm4_target_xcc; }; struct amdgpu_mqd { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index f4b3073cf9683..9508709abd49a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -30,26 +30,6 @@ #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE -/* Mapping queue priority to pipe priority, indexed by queue priority */ -int amdgpu_userq_pipe_priority_map[] = { - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_0, - AMDGPU_RING_PRIO_1, - AMDGPU_RING_PRIO_1, - AMDGPU_RING_PRIO_1, - AMDGPU_RING_PRIO_1, - AMDGPU_RING_PRIO_2, - AMDGPU_RING_PRIO_2, - AMDGPU_RING_PRIO_2, - AMDGPU_RING_PRIO_2, - AMDGPU_RING_PRIO_2 -}; - static int mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo) { @@ -292,105 +272,6 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, return r; } -/** - * amdgpu_userq_set_compute_mqd - Parse compute MQD and update queue props - * @queue: Target user mode queue - * @props: Queue property structure to be updated - * @args: User queue input arguments - * @uq_mgr: User queue manager (for logging) - * - * This function only parses and validates user input, updating queue props - * (no hardware MQD configuration - that's handled in MES layer) - * Returns: 0 on success, negative error code on failure - */ -static int amdgpu_userq_set_compute_mqd(struct amdgpu_usermode_queue *queue, - struct amdgpu_mqd_prop *props, - struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd) -{ - struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; - struct amdgpu_device *adev = uq_mgr->adev; - const int max_num_cus = 1024; - size_t cu_mask_size; - uint32_t count; - uint32_t *cu_mask = NULL; - int ret = 0; - - if (!queue || !props || !compute_mqd) - return -EINVAL; - - if (compute_mqd->queue_percentage > AMDGPU_USERQ_MAX_QUEUE_PERCENTAGE) { - DRM_ERROR("Queue percentage must be between 0 to AMDGPU_USERQ_MAX_QUEUE_PERCENTAGE.\n"); - return -EINVAL; - } - - /* Validate priority */ - if (compute_mqd->hqd_queue_priority > AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) { - DRM_ERROR("Queue priority must be between 0 to AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM.\n"); - return -EINVAL; - } - - - /* validate and set CU mask property */ - if (compute_mqd->cu_mask_count) { - if (compute_mqd->cu_mask_count % 32 != 0) { - DRM_ERROR("CU mask count must be a multiple of 32.\n"); - return -EINVAL; - } - count = compute_mqd->cu_mask_count; - - /* Limit CU mask size to prevent excessive memory allocation */ - if (count > max_num_cus) { - DRM_ERROR("CU mask cannot be greater than 1024 bits.\n"); - count = max_num_cus; - cu_mask_size = sizeof(uint32_t) * (max_num_cus / 32); - } else { - cu_mask_size = sizeof(uint32_t) * (compute_mqd->cu_mask_count / 32); - } - - /* Copy CU mask from user space */ - cu_mask = memdup_user(u64_to_user_ptr(compute_mqd->cu_mask_ptr), cu_mask_size); - if (IS_ERR(cu_mask)) { - ret = PTR_ERR(cu_mask); - cu_mask = NULL; - goto cleanup; - } - - /* Validate pairwise CU mask for WGP-based ASICs */ - if (cu_mask && adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) { - for (int i = 0; i < count; i += 2) { - uint32_t cu_pair = (cu_mask[i / 32] >> (i % 32)) & 0x3; - if (cu_pair && cu_pair != 0x3) { - DRM_ERROR("CUs must be adjacent pairwise enabled.\n"); - kfree(cu_mask); - cu_mask = NULL; - ret = -EINVAL; - goto cleanup; - } - } - } - - /* Free old CU mask */ - if (props->cu_mask) { - kfree(props->cu_mask); - props->cu_mask = NULL; - } - - props->cu_mask = cu_mask; - props->cu_mask_count = count; - props->is_user_cu_masked = (cu_mask != NULL); - } - - /* Parse HQD priority and other compute properties */ - props->queue_percentage = compute_mqd->queue_percentage; - props->pm4_target_xcc = compute_mqd->pm4_target_xcc; - props->hqd_queue_priority = compute_mqd->hqd_queue_priority; - props->hqd_pipe_priority = amdgpu_userq_pipe_priority_map[compute_mqd->hqd_queue_priority]; - props->eop_gpu_addr = compute_mqd->eop_va; - -cleanup: - return ret; -} - static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args_in) { @@ -445,10 +326,10 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 2048); if (r) goto free_mqd; - r = amdgpu_userq_set_compute_mqd(queue, userq_props, compute_mqd); - if (r) - goto free_mqd; + userq_props->eop_gpu_addr = compute_mqd->eop_va; + userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; + userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; userq_props->hqd_active = false; userq_props->tmz_queue = mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; @@ -552,51 +433,11 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, return r; } -static int mes_userq_mqd_update(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args_in) -{ - int retval = 0; - struct amdgpu_device *adev = queue->userq_mgr->adev; - struct amdgpu_mqd_prop *userq_props = queue->userq_prop; - struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; - struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd_v11; - - if (!queue || !userq_props) - return -EINVAL; - - if (queue->queue_type != AMDGPU_HW_IP_COMPUTE) - return -EINVAL; - - if (args_in->mqd_size != sizeof(*compute_mqd_v11)) { - DRM_ERROR("Invalid compute IP MQD size\n"); - return -EINVAL; - } - - compute_mqd_v11 = memdup_user(u64_to_user_ptr(args_in->mqd), args_in->mqd_size); - if (IS_ERR(compute_mqd_v11)) { - DRM_ERROR("Failed to read user MQD\n"); - return -ENOMEM; - } - - retval = amdgpu_userq_set_compute_mqd(queue, userq_props, compute_mqd_v11); - if (retval) - goto free; - - userq_props->queue_size = args_in->queue_size; - userq_props->hqd_base_gpu_addr = args_in->queue_va; - - retval = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); - -free: - kfree(compute_mqd_v11); - return retval; -} - static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) { struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); - kfree(queue->userq_prop->cu_mask); kfree(queue->userq_prop); amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); } @@ -673,7 +514,6 @@ static int mes_userq_restore(struct amdgpu_usermode_queue *queue) const struct amdgpu_userq_funcs userq_mes_funcs = { .mqd_create = mes_userq_mqd_create, - .mqd_update = mes_userq_mqd_update, .mqd_destroy = mes_userq_mqd_destroy, .unmap = mes_userq_unmap, .map = mes_userq_map, diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index fb3df55d382a9..1d34daa0ebcd5 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -341,7 +341,6 @@ union drm_amdgpu_ctx { #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ /* for queues that need access to protected content */ #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) -#define AMDGPU_USERQ_MAX_QUEUE_PERCENTAGE 100 /* * This structure is a container to pass input configuration @@ -461,33 +460,6 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 { * to get the size. */ __u64 eop_va; - /** - * @cu_mask_ptr: User-space pointer to CU (Compute Unit) mask array - * Points to an array of __u32 values that define which CUs are enabled - * for this queue (0 = disabled, 1 = enabled per bit) - */ - __u64 cu_mask_ptr; - /** - * @cu_mask_count: Number of entries in the CU mask array - * Total count of __u32 elements in the cu_mask_ptr array (each element - * represents 32 CUs/WGPs) - */ - __u32 cu_mask_count; - /** - * @queue_percentage: Queue resource allocation percentage (0-100) - * Defines the percentage of GPU resources allocated to this queue - */ - __u32 queue_percentage; - /** - * @hqd_queue_priority: Hqd Queue priority (0-15) - * Higher values indicate higher scheduling priority for the queue - */ - __u32 hqd_queue_priority; - /** - * @pm4_target_xcc: PM4 target XCC identifier (for gfx9/gfx12.1) - * Specifies the target XCC (Cross Compute Complex) for PM4 commands - */ - __u32 pm4_target_xcc; }; /* userq signal/wait ioctl */ From 6b259b3381907d0ee537a9966d21a42427935880 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 6 Feb 2026 14:23:59 +0800 Subject: [PATCH 0121/2070] drm/amd/pm: Add acc counter & fw timestamp to xcp metrics Add accumulation counter and firmware timestamp to partition metrics for smu_v13_0_6 & smu_v13_0_12 v2: Use U64 for accumulation counter (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 3 +++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 6 +++++- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 3d60d3c1e5858..f2a6ecb64c032 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -823,6 +823,9 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp idx++; } + xcp_metrics->accumulation_counter = metrics->AccumulationCounter; + xcp_metrics->firmware_timestamp = metrics->Timestamp; + return sizeof(*xcp_metrics); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 3a9210083ce33..07592e285cf56 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2668,6 +2668,8 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, idx++; } } + xcp_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version); + xcp_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); return sizeof(*xcp_metrics); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 0588a5aa952d6..07d4cb6562b06 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -259,7 +259,11 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, SMU_13_0_6_MAX_XCC); \ SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ - SMU_13_0_6_MAX_XCC); + SMU_13_0_6_MAX_XCC); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_partition_metrics, SMU_13_0_6_PARTITION_METRICS_FIELDS); From d7172dc8fb2c3b4300a9f2004207fa750811249b Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 6 Feb 2026 16:32:31 +0800 Subject: [PATCH 0122/2070] drm/amd/pm: Use U64 for accumulation counter Use U64 for accumulation counter in gpu metrics for smu_v13_0_6 and smu_v13_0_12 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 07d4cb6562b06..ffb06564f8308 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -140,7 +140,7 @@ extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ SMU_MTYPE(U64), system_clock_counter); \ SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ - SMU_MTYPE(U32), accumulation_counter); \ + SMU_MTYPE(U64), accumulation_counter); \ SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ SMU_MTYPE(U32), prochot_residency_acc); \ SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ From 70b3ae935f7066cf89f599d2fed778005b290c7c Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 12 Jan 2026 10:22:37 +0000 Subject: [PATCH 0123/2070] drm/amdgpu: Remove a few holes from struct amdgpu_ctx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-order the struct members a bit to avoid some holes: /* size: 408, cachelines: 7, members: 15 */ /* sum members: 393, holes: 4, sum holes: 15 */ /* last cacheline: 24 bytes */ /* size: 400, cachelines: 7, members: 15 */ /* sum members: 393, holes: 1, sum holes: 7 */ /* last cacheline: 16 bytes */ While doing so we notice a duplicate but will address than in the following patch. Signed-off-by: Tvrtko Ursulin Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index 090dfe86f75ba..aed758d0acaad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -44,20 +44,20 @@ struct amdgpu_ctx_entity { struct amdgpu_ctx { struct kref refcount; - struct amdgpu_ctx_mgr *mgr; + spinlock_t ring_lock; unsigned reset_counter; unsigned reset_counter_query; - uint64_t generation; - spinlock_t ring_lock; - struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM]; - bool preamble_presented; int32_t init_priority; int32_t override_priority; + uint32_t stable_pstate; atomic_t guilty; + bool preamble_presented; + uint64_t generation; unsigned long ras_counter_ce; unsigned long ras_counter_ue; - uint32_t stable_pstate; + struct amdgpu_ctx_mgr *mgr; struct amdgpu_ctx_mgr *ctx_mgr; + struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM]; }; struct amdgpu_ctx_mgr { From 880d8a18369a7e4f213d616830eb212c36b69861 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 3 Jan 2026 13:29:19 -0500 Subject: [PATCH 0124/2070] drm/amdgpu: don't call drm_sched_stop/start() in asic reset We only want to stop the work queues, not mess with the fences, etc. v2: add the job back to the pending list. v3: return the proper job status so scheduler adds the job back to the pending list Acked-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 38169ab7dafd2..726930431f332 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6306,7 +6306,7 @@ static void amdgpu_device_halt_activities(struct amdgpu_device *adev, if (!amdgpu_ring_sched_ready(ring)) continue; - drm_sched_stop(&ring->sched, job ? &job->base : NULL); + drm_sched_wqueue_stop(&ring->sched); if (need_emergency_restart) amdgpu_job_stop_all_jobs_on_sched(&ring->sched); @@ -6390,7 +6390,7 @@ static int amdgpu_device_sched_resume(struct list_head *device_list, if (!amdgpu_ring_sched_ready(ring)) continue; - drm_sched_start(&ring->sched, 0); + drm_sched_wqueue_start(&ring->sched); } if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 2c82d9e8c0be1..55172c2dcc355 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -92,7 +92,6 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) struct drm_wedge_task_info *info = NULL; struct amdgpu_task_info *ti = NULL; struct amdgpu_device *adev = ring->adev; - enum drm_gpu_sched_stat status = DRM_GPU_SCHED_STAT_RESET; int idx, r; if (!drm_dev_enter(adev_to_drm(adev), &idx)) { @@ -147,8 +146,6 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) ring->sched.name); drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, info); - /* This is needed to add the job back to the pending list */ - status = DRM_GPU_SCHED_STAT_NO_HANG; goto exit; } dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); @@ -184,7 +181,8 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) exit: amdgpu_vm_put_task_info(ti); drm_dev_exit(idx); - return status; + /* This is needed to add the job back to the pending list */ + return DRM_GPU_SCHED_STAT_NO_HANG; } int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, From d1244886e5d0e6d32ab6379ba58fd524ff220ce3 Mon Sep 17 00:00:00 2001 From: Tom Chung Date: Tue, 20 Jan 2026 18:10:31 +0800 Subject: [PATCH 0125/2070] drm/amd/display: Fix system resume lag issue [Why] System will try to apply idle power optimizations setting during system resume. But system power state is still in D3 state, and it will cause the idle power optimizations command not actually to be sent to DMUB and cause some platforms to go into IPS. [How] Set power state to D0 first before calling the dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false) Reviewed-by: Nicholas Kazlauskas Signed-off-by: Tom Chung Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 631b44fd6dae1..d870ce267b375 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3479,7 +3479,17 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) struct dc_commit_streams_params commit_params = {}; if (dm->dc->caps.ips_support) { + if (!amdgpu_in_reset(adev)) + mutex_lock(&dm->dc_lock); + + /* Need to set POWER_STATE_D0 first or it will not execute + * idle_power_optimizations command to DMUB. + */ + dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); + + if (!amdgpu_in_reset(adev)) + mutex_unlock(&dm->dc_lock); } if (amdgpu_in_reset(adev)) { From 76b1ea2def904df59d479717180c965ea1a578a7 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Fri, 23 Jan 2026 14:47:01 +0800 Subject: [PATCH 0126/2070] drm/amd/display: Avoid updating surface with the same surface under MPO [Why & How] Although it's dummy updates of surface update for committing stream updates, we should not have dummy_updates[j].surface all indicating to the same surface under multiple surfaces case. Otherwise, copy_surface_update_to_plane() in update_planes_and_stream_state() will update to the same surface only. Reviewed-by: Harry Wentland Signed-off-by: Wayne Lin Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d870ce267b375..9fcb4677d0f06 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10974,7 +10974,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) continue; } for (j = 0; j < status->plane_count; j++) - dummy_updates[j].surface = status->plane_states[0]; + dummy_updates[j].surface = status->plane_states[j]; sort(dummy_updates, status->plane_count, sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); From 307dddf0873a683a707d3ff51865836815dfebfe Mon Sep 17 00:00:00 2001 From: Leon Huang Date: Tue, 20 Jan 2026 16:04:09 +0800 Subject: [PATCH 0127/2070] drm/amd/display: Check frame skip capability in Sink side [Why&How] Frame skip capability is described in AMD VSDB in EDID. Need to retrieve the cap and determine fr.skipping mode enablement Reviewed-by: ChunTao Tso Signed-off-by: Leon Huang Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../display/dc/link/protocols/link_dp_panel_replay.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index cc3b44cf76626..4a9e86d32dbbd 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -34,6 +34,7 @@ link->ctx->logger #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B +#define DP_SINK_ENABLE_FRAME_SKIPPING_MODE_SHIFT (5) static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz) { @@ -89,6 +90,7 @@ static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_s union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 }; union dpcd_alpm_configuration alpm_config; + uint8_t data = 0; replay_context.controllerId = CONTROLLER_ID_UNDEFINED; @@ -186,6 +188,14 @@ static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_s DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw, sizeof(alpm_config.raw)); + + //Enable frame skipping + if (link->replay_settings.config.frame_skip_supported) + data = data | (1 << DP_SINK_ENABLE_FRAME_SKIPPING_MODE_SHIFT); + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_SINK_PR_ENABLE_AND_CONFIGURATION, + (uint8_t *)&(data), sizeof(uint8_t)); } return true; From b660967bd161721a262e68e1f213fde34ab37326 Mon Sep 17 00:00:00 2001 From: YiLing Chen Date: Tue, 27 Jan 2026 13:32:40 +0800 Subject: [PATCH 0128/2070] drm/amd/display: set enable_legacy_fast_update to false for DCN36 [Why/How] Align the default value of the flag with DCN35/351. Reviewed-by: Nicholas Kazlauskas Signed-off-by: YiLing Chen Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 0ee16926db4e2..1d8ca312fe1eb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -775,7 +775,7 @@ static const struct dc_debug_options debug_defaults_drv = { }; static const struct dc_check_config config_defaults = { - .enable_legacy_fast_update = true, + .enable_legacy_fast_update = false, }; static const struct dc_panel_config panel_config_defaults = { From 03e04e50387806bf1ff7fd24cb27f078d84c413e Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Wed, 21 Jan 2026 16:05:00 +0530 Subject: [PATCH 0129/2070] drm/amd/display: Refactor virtual directory reorganize encoder and hwss files. [why] Virtual encoders & hwss were grouped in a separate directory, not aligned with dio and link component structure. [how] Moved virtual_link_encoder and virtual_stream_encoder to dc/dio/virtual/. Moved virtual_link_hwss to dc/link/hwss/ and renamed to link_hwss_virtual. Removed dc/virtual/ directory. Updated all includes and build files (Makefiles) Reviewed-by: Nicholas Kazlauskas Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 4 +-- drivers/gpu/drm/amd/display/dc/dio/Makefile | 9 ++++++ .../{ => dio}/virtual/virtual_link_encoder.c | 2 -- .../{ => dio}/virtual/virtual_link_encoder.h | 0 .../virtual/virtual_stream_encoder.c | 1 - .../virtual/virtual_stream_encoder.h | 0 drivers/gpu/drm/amd/display/dc/link/Makefile | 3 +- .../hwss/link_hwss_virtual.c} | 2 +- .../hwss/link_hwss_virtual.h} | 6 ++-- .../dc/resource/dce100/dce100_resource.c | 2 +- .../dc/resource/dce120/dce120_resource.c | 2 +- .../dc/resource/dcn10/dcn10_resource.c | 2 +- .../dc/resource/dcn20/dcn20_resource.c | 2 +- .../dc/resource/dcn201/dcn201_resource.c | 2 +- .../dc/resource/dcn21/dcn21_resource.c | 2 +- .../dc/resource/dcn30/dcn30_resource.c | 2 +- .../dc/resource/dcn301/dcn301_resource.c | 2 +- .../dc/resource/dcn31/dcn31_resource.c | 2 +- .../dc/resource/dcn314/dcn314_resource.c | 2 +- .../dc/resource/dcn315/dcn315_resource.c | 2 +- .../dc/resource/dcn316/dcn316_resource.c | 2 +- .../dc/resource/dcn32/dcn32_resource.c | 2 +- .../dc/resource/dcn321/dcn321_resource.c | 2 +- .../dc/resource/dcn35/dcn35_resource.c | 2 +- .../dc/resource/dcn351/dcn351_resource.c | 2 +- .../dc/resource/dcn36/dcn36_resource.c | 2 +- .../dc/resource/dcn401/dcn401_resource.c | 2 +- .../gpu/drm/amd/display/dc/virtual/Makefile | 30 ------------------- 30 files changed, 37 insertions(+), 60 deletions(-) rename drivers/gpu/drm/amd/display/dc/{ => dio}/virtual/virtual_link_encoder.c (99%) rename drivers/gpu/drm/amd/display/dc/{ => dio}/virtual/virtual_link_encoder.h (100%) rename drivers/gpu/drm/amd/display/dc/{ => dio}/virtual/virtual_stream_encoder.c (99%) rename drivers/gpu/drm/amd/display/dc/{ => dio}/virtual/virtual_stream_encoder.h (100%) rename drivers/gpu/drm/amd/display/dc/{virtual/virtual_link_hwss.c => link/hwss/link_hwss_virtual.c} (98%) rename drivers/gpu/drm/amd/display/dc/{virtual/virtual_link_hwss.h => link/hwss/link_hwss_virtual.h} (92%) delete mode 100644 drivers/gpu/drm/amd/display/dc/virtual/Makefile diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 7277ed21552f3..93d02956c5eb5 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -22,7 +22,7 @@ # # Makefile for Display Core (dc) component. -DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg +DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg ifdef CONFIG_DRM_AMD_DC_FP diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e7d2b861dedd0..17ba7af0ddcd9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -53,7 +53,7 @@ #include "dpp.h" #include "timing_generator.h" #include "abm.h" -#include "virtual/virtual_link_encoder.h" +#include "dio/virtual/virtual_link_encoder.h" #include "hubp.h" #include "link_hwss.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b4e5a79e97497..639831295b219 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -37,7 +37,7 @@ #include "dpp.h" #include "core_types.h" #include "set_mode_types.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dpcd_defs.h" #include "link_enc_cfg.h" #include "link_service.h" @@ -45,7 +45,7 @@ #include "dc_state_priv.h" #include "dc_stream_priv.h" -#include "virtual/virtual_link_hwss.h" +#include "link/hwss/link_hwss_virtual.h" #include "link/hwss/link_hwss_dio.h" #include "link/hwss/link_hwss_dpia.h" #include "link/hwss/link_hwss_hpo_dp.h" diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile b/drivers/gpu/drm/amd/display/dc/dio/Makefile index 02eec03dc2041..2f5619078e1f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dio/Makefile @@ -23,6 +23,15 @@ # # +############################################################################### +# VIRTUAL +############################################################################### +DIO_VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o + +AMD_DAL_DIO_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/dio/virtual/,$(DIO_VIRTUAL)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DIO_VIRTUAL) + ifdef CONFIG_DRM_AMD_DC_FP ############################################################################### # DCN10 diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c index 1d226e0519a56..2655bc194a359 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c @@ -128,5 +128,3 @@ bool virtual_link_encoder_construct( return true; } - - diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.h diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c index ad088d70e1893..c5d2e9404d943 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c @@ -171,4 +171,3 @@ struct stream_encoder *virtual_stream_encoder_create( kfree(enc); return NULL; } - diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.h diff --git a/drivers/gpu/drm/amd/display/dc/link/Makefile b/drivers/gpu/drm/amd/display/dc/link/Makefile index 84dace27daf77..0f3670e302325 100644 --- a/drivers/gpu/drm/amd/display/dc/link/Makefile +++ b/drivers/gpu/drm/amd/display/dc/link/Makefile @@ -43,7 +43,8 @@ AMD_DISPLAY_FILES += $(AMD_DAL_LINK_ACCESSORIES) # hwss ############################################################################### LINK_HWSS = link_hwss_dio.o link_hwss_dpia.o link_hwss_hpo_dp.o \ -link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o +link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o \ +link_hwss_virtual.o AMD_DAL_LINK_HWSS = $(addprefix $(AMDDALPATH)/dc/link/hwss/, \ $(LINK_HWSS)) diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c similarity index 98% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c rename to drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c index 4f7f99156897b..64742c24f7e6e 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c @@ -23,7 +23,7 @@ * */ -#include "virtual_link_hwss.h" +#include "link_hwss_virtual.h" void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h similarity index 92% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h rename to drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h index fbcbc5afb47d6..f6e448c89751a 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h @@ -22,8 +22,8 @@ * Authors: AMD * */ -#ifndef __DC_VIRTUAL_LINK_HWSS_H__ -#define __DC_VIRTUAL_LINK_HWSS_H__ +#ifndef __DC_LINK_HWSS_VIRTUAL_H__ +#define __DC_LINK_HWSS_VIRTUAL_H__ #include "core_types.h" @@ -32,4 +32,4 @@ void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx); void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx); const struct link_hwss *get_virtual_link_hwss(void); -#endif /* __DC_VIRTUAL_LINK_HWSS_H__ */ +#endif /* __DC_LINK_HWSS_VIRTUAL_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index d40d91ec2035f..a929e64524e56 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -31,7 +31,7 @@ #include "resource.h" #include "clk_mgr.h" #include "include/irq_service_interface.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce110/dce110_timing_generator.h" #include "irq/dce110/irq_service_dce110.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index b1570b6b1af30..92890784caa6e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -35,7 +35,7 @@ #include "dce112/dce112_resource.h" #include "dce110/dce110_resource.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce120/dce120_timing_generator.h" #include "irq/dce120/irq_service_dce120.h" #include "dce/dce_opp.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index f12367adf1451..476780a5450fb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -48,7 +48,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" #include "dcn10/dcn10_hubp.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 46985eb2a623f..6731544f0981b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -55,7 +55,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn20/dcn20_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index 055107843a70a..90d38631f63a0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -51,7 +51,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce/dce_aux.h" #include "dce/dce_i2c.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 967e813a45e51..107612595db60 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -57,7 +57,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn20/dcn20_dccg.h" #include "dcn21/dcn21_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index d0ebb733e8024..6cfdc37dab588 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -55,7 +55,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn30/dcn30_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 3ad6a3d4858e7..e1d0c166b4848 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -54,7 +54,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn301/dcn301_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index e853ea1103101..8ad72557b16a4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -64,7 +64,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 3ccde75a4ecbf..5f0fe6e5bd821 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -66,7 +66,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 4e962f522f1be..a8283f21008ef 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -63,7 +63,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 5a95dd54cb429..4da0e9320159b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -63,7 +63,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index b276fec3e479a..d3b92c61b7ad1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -65,7 +65,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 3466ca34c93fe..d08691ea27ea2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -68,7 +68,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 45454a0972642..945da8cffada4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -70,7 +70,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn35/dcn35_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index e3c5871658077..e660889904a99 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -49,7 +49,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn35/dcn35_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 1d8ca312fe1eb..7582217bd06d5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -49,7 +49,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn35/dcn35_dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 4875faffe8735..f5e02a1ff771f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -47,7 +47,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn401/dcn401_dccg.h" #include "dcn10/dcn10_resource.h" diff --git a/drivers/gpu/drm/amd/display/dc/virtual/Makefile b/drivers/gpu/drm/amd/display/dc/virtual/Makefile deleted file mode 100644 index 931facd4dab5d..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/virtual/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2017 Advanced Micro Devices, Inc. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -# OTHER DEALINGS IN THE SOFTWARE. -# -# -# Makefile for the virtual sub-component of DAL. -# It provides the control and status of HW CRTC block. - -VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o virtual_link_hwss.o - -AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL)) - -AMD_DISPLAY_FILES += $(AMD_DAL_VIRTUAL) From 20b1f8aa6a78c13baef029c0d96b54673eccafce Mon Sep 17 00:00:00 2001 From: Peichen Huang Date: Mon, 26 Jan 2026 11:56:28 +0800 Subject: [PATCH 0130/2070] drm/amd/display: use enum value for panel replay setting [WHY & HOW] use enum value for Panel Replay setting. Reviewed-by: Robin Chen Signed-off-by: Peichen Huang Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/protocols/link_dp_panel_replay.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index 4a9e86d32dbbd..7e45d1e767bb1 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -333,10 +333,10 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con pipe_ctx->stream->timing.dsc_cfg.num_slices_v; if (dc_is_embedded_signal(link->connector_signal)) - cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C; + cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1C; else // For external DP, use option 1-A - cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A; + cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1A; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; From d1feab0f32424138be72193998e3ff5eea8f68a9 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Thu, 5 Feb 2026 17:31:24 -0500 Subject: [PATCH 0131/2070] drm/amd/display: guard NULL manual-trigger callback in cursor programming KASAN reports a NULL instruction fetch (RIP=0x0) from dc_stream_program_cursor_position(): BUG: kernel NULL pointer dereference, address: 0000000000000000 RIP: 0010:0x0 Call Trace: dc_stream_program_cursor_position+0x344/0x920 [amdgpu] amdgpu_dm_atomic_commit_tail+... [ +1.041013] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ +0.000027] #PF: supervisor instruction fetch in kernel mode [ +0.000013] #PF: error_code(0x0010) - not-present page [ +0.000012] PGD 0 P4D 0 [ +0.000017] Oops: Oops: 0010 [#1] SMP KASAN NOPTI [ +0.000017] CPU: 0 UID: 0 PID: 10 Comm: kworker/0:1 Tainted: G E 6.18.0+ #3 PREEMPT(voluntary) [ +0.000023] Tainted: [E]=UNSIGNED_MODULE [ +0.000010] Hardware name: ASUS System Product Name/ROG STRIX B550-F GAMING (WI-FI), BIOS 1401 12/03/2020 [ +0.000016] Workqueue: events drm_mode_rmfb_work_fn [ +0.000022] RIP: 0010:0x0 [ +0.000017] Code: Unable to access opcode bytes at 0xffffffffffffffd6. [ +0.000015] RSP: 0018:ffffc9000017f4c8 EFLAGS: 00010246 [ +0.000016] RAX: 0000000000000000 RBX: ffff88810afdda80 RCX: 1ffff110457000d1 [ +0.000014] RDX: 1ffffffff87b75bd RSI: 0000000000000000 RDI: ffff88810afdda80 [ +0.000014] RBP: ffffc9000017f538 R08: 0000000000000000 R09: ffff88822b800690 [ +0.000013] R10: 0000000000000000 R11: 0000000000000000 R12: ffffffffc3dbac20 [ +0.000014] R13: 0000000000000000 R14: ffff88811ab80000 R15: dffffc0000000000 [ +0.000014] FS: 0000000000000000(0000) GS:ffff888434599000(0000) knlGS:0000000000000000 [ +0.000015] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ +0.000013] CR2: ffffffffffffffd6 CR3: 000000010ee88000 CR4: 0000000000350ef0 [ +0.000014] Call Trace: [ +0.000010] [ +0.000010] dc_stream_program_cursor_position+0x344/0x920 [amdgpu] [ +0.001086] ? __pfx_mutex_lock+0x10/0x10 [ +0.000015] ? unwind_next_frame+0x18b/0xa70 [ +0.000019] amdgpu_dm_atomic_commit_tail+0x1124/0xfa20 [amdgpu] [ +0.001040] ? ret_from_fork_asm+0x1a/0x30 [ +0.000018] ? filter_irq_stacks+0x90/0xa0 [ +0.000022] ? __pfx_amdgpu_dm_atomic_commit_tail+0x10/0x10 [amdgpu] [ +0.001058] ? kasan_save_track+0x18/0x70 [ +0.000015] ? kasan_save_alloc_info+0x37/0x60 [ +0.000015] ? __kasan_kmalloc+0xc3/0xd0 [ +0.000013] ? __kmalloc_cache_noprof+0x1aa/0x600 [ +0.000016] ? drm_atomic_helper_setup_commit+0x788/0x1450 [ +0.000017] ? drm_atomic_helper_commit+0x7e/0x290 [ +0.000014] ? drm_atomic_commit+0x205/0x2e0 [ +0.000015] ? process_one_work+0x629/0xf80 [ +0.000016] ? worker_thread+0x87f/0x1570 [ +0.000020] ? srso_return_thunk+0x5/0x5f [ +0.000014] ? __kasan_check_write+0x14/0x30 [ +0.000014] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? _raw_spin_lock_irq+0x8a/0xf0 [ +0.000015] ? __pfx__raw_spin_lock_irq+0x10/0x10 [ +0.000016] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? __kasan_check_write+0x14/0x30 [ +0.000014] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? __wait_for_common+0x204/0x460 [ +0.000015] ? sched_clock_noinstr+0x9/0x10 [ +0.000014] ? __pfx_schedule_timeout+0x10/0x10 [ +0.000014] ? local_clock_noinstr+0xe/0xd0 [ +0.000015] ? __pfx___wait_for_common+0x10/0x10 [ +0.000014] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? __wait_for_common+0x204/0x460 [ +0.000014] ? __pfx_schedule_timeout+0x10/0x10 [ +0.000015] ? __kasan_kmalloc+0xc3/0xd0 [ +0.000015] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? wait_for_completion_timeout+0x1d/0x30 [ +0.000015] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? drm_crtc_commit_wait+0x32/0x180 [ +0.000015] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? drm_atomic_helper_wait_for_dependencies+0x46a/0x800 [ +0.000019] commit_tail+0x231/0x510 [ +0.000017] drm_atomic_helper_commit+0x219/0x290 [ +0.000015] ? __pfx_drm_atomic_helper_commit+0x10/0x10 [ +0.000016] drm_atomic_commit+0x205/0x2e0 [ +0.000014] ? __pfx_drm_atomic_commit+0x10/0x10 [ +0.000013] ? __pfx_drm_connector_free+0x10/0x10 [ +0.000014] ? __pfx___drm_printfn_info+0x10/0x10 [ +0.000017] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? drm_atomic_set_crtc_for_connector+0x49e/0x660 [ +0.000015] ? drm_atomic_set_fb_for_plane+0x155/0x290 [ +0.000015] drm_framebuffer_remove+0xa9b/0x1240 [ +0.000014] ? finish_task_switch.isra.0+0x15a/0x840 [ +0.000015] ? __switch_to+0x385/0xda0 [ +0.000015] ? srso_safe_ret+0x1/0x20 [ +0.000013] ? __pfx_drm_framebuffer_remove+0x10/0x10 [ +0.000016] ? kasan_print_address_stack_frame+0x221/0x280 [ +0.000015] drm_mode_rmfb_work_fn+0x14b/0x240 [ +0.000015] process_one_work+0x629/0xf80 [ +0.000012] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? __kasan_check_write+0x14/0x30 [ +0.000019] worker_thread+0x87f/0x1570 [ +0.000013] ? __pfx__raw_spin_lock_irqsave+0x10/0x10 [ +0.000014] ? __pfx_try_to_wake_up+0x10/0x10 [ +0.000017] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? kasan_print_address_stack_frame+0x227/0x280 [ +0.000017] ? __pfx_worker_thread+0x10/0x10 [ +0.000014] kthread+0x396/0x830 [ +0.000013] ? __pfx__raw_spin_lock_irq+0x10/0x10 [ +0.000015] ? __pfx_kthread+0x10/0x10 [ +0.000012] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? __kasan_check_write+0x14/0x30 [ +0.000014] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? recalc_sigpending+0x180/0x210 [ +0.000015] ? srso_return_thunk+0x5/0x5f [ +0.000013] ? __pfx_kthread+0x10/0x10 [ +0.000014] ret_from_fork+0x31c/0x3e0 [ +0.000014] ? __pfx_kthread+0x10/0x10 [ +0.000013] ret_from_fork_asm+0x1a/0x30 [ +0.000019] [ +0.000010] Modules linked in: rfcomm(E) cmac(E) algif_hash(E) algif_skcipher(E) af_alg(E) snd_seq_dummy(E) snd_hrtimer(E) qrtr(E) xt_MASQUERADE(E) nf_nat(E) nf_conntrack(E) nf_defrag_ipv6(E) nf_defrag_ipv4(E) xt_mark(E) xt_tcpudp(E) nft_compat(E) nf_tables(E) x_tables(E) bnep(E) snd_hda_codec_alc882(E) snd_hda_codec_atihdmi(E) snd_hda_codec_realtek_lib(E) snd_hda_codec_hdmi(E) snd_hda_codec_generic(E) iwlmvm(E) snd_hda_intel(E) binfmt_misc(E) snd_hda_codec(E) snd_hda_core(E) mac80211(E) snd_intel_dspcfg(E) snd_intel_sdw_acpi(E) snd_hwdep(E) snd_pcm(E) libarc4(E) snd_seq_midi(E) snd_seq_midi_event(E) snd_rawmidi(E) amd_atl(E) intel_rapl_msr(E) snd_seq(E) intel_rapl_common(E) iwlwifi(E) jc42(E) snd_seq_device(E) btusb(E) snd_timer(E) btmtk(E) btrtl(E) edac_mce_amd(E) eeepc_wmi(E) polyval_clmulni(E) btbcm(E) ghash_clmulni_intel(E) asus_wmi(E) ee1004(E) platform_profile(E) btintel(E) snd(E) nls_iso8859_1(E) aesni_intel(E) soundcore(E) i2c_piix4(E) cfg80211(E) sparse_keymap(E) wmi_bmof(E) bluetooth(E) k10temp(E) rapl(E) [ +0.000300] i2c_smbus(E) ccp(E) joydev(E) input_leds(E) gpio_amdpt(E) mac_hid(E) sch_fq_codel(E) msr(E) parport_pc(E) ppdev(E) lp(E) parport(E) efi_pstore(E) nfnetlink(E) dmi_sysfs(E) autofs4(E) cdc_ether(E) usbnet(E) amdgpu(E) amdxcp(E) hid_generic(E) i2c_algo_bit(E) drm_ttm_helper(E) ttm(E) drm_exec(E) drm_panel_backlight_quirks(E) gpu_sched(E) drm_suballoc_helper(E) video(E) drm_buddy(E) usbhid(E) drm_display_helper(E) r8152(E) hid(E) mii(E) cec(E) ahci(E) rc_core(E) igc(E) libahci(E) wmi(E) [ +0.000294] CR2: 0000000000000000 [ +0.000013] ---[ end trace 0000000000000000 ]--- The crash happens when we unconditionally call into the timing generator manual trigger hook: pipe_ctx->stream_res.tg->funcs->program_manual_trigger(...) On some configurations the timing generator (tg), its funcs table, or the program_manual_trigger callback can be NULL. Guard all of these before calling the hook. If the first pipe matching the stream cannot trigger, keep scanning to find another matching pipe with a valid hook. The issue was originally found on Vg20/DCE 12.1 Mario successfully tested on Polaris 11/DCE 11.2 Cc: Aurabindo Pillai Cc: Alexander Deucher Cc: Christian Koenig Suggested-by: Aurabindo Pillai Signed-off-by: Vitaly Prosyak Reviewed-by: Aurabindo Pillai Reviewed-and-tested-by: Mario Kleiner --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index f59020f1a722f..ecd08580937de 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -522,8 +522,10 @@ bool dc_stream_program_cursor_position( struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; /* trigger event on first pipe with current stream */ - if (stream == pipe_ctx->stream) { - pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + if (stream == pipe_ctx->stream && + pipe_ctx->stream_res.tg->funcs->program_manual_trigger) { + pipe_ctx->stream_res.tg->funcs->program_manual_trigger( + pipe_ctx->stream_res.tg); break; } } From 5787f3d8e5363856b96ccacb24ab8f9922e0158f Mon Sep 17 00:00:00 2001 From: Leo Li Date: Mon, 3 Nov 2025 11:14:59 -0500 Subject: [PATCH 0132/2070] drm/amd/display: Increase DCN35 SR enter/exit latency [Why & How] On Framework laptops with DDR5 modules, underflow can be observed. It's unclear why it only occurs on specific desktop contents. However, increasing enter/exit latencies by 3us seems to resolve it. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4463 Reviewed-by: Nicholas Kazlauskas Signed-off-by: Leo Li Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 16 ++++++++-------- .../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 7abe6811e4dfa..6fc5247526132 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -766,32 +766,32 @@ static struct wm_table ddr5_wm_table = { .wm_inst = WM_A, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, { .wm_inst = WM_B, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, { .wm_inst = WM_C, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, { .wm_inst = WM_D, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 817a370e80a77..8a177d5ae213e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { }, }, .num_states = 5, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .sr_exit_z8_time_us = 250.0, .sr_enter_plus_exit_z8_time_us = 350.0, .fclk_change_latency_us = 24.0, From b34412a0fdc1a1c11da8cddc9e2e1d6bc46bb693 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Fri, 23 Jan 2026 17:00:06 -0500 Subject: [PATCH 0133/2070] drm/amd/display: Make GPIO HPD path conditional [Why] Avoid unnecessary GPIO configuration attempts on dcn that doesn't support it. [How] Conditionally use GPIO HPD detection or rely on hw encoder path. Reviewed-by: Charlene Liu Signed-off-by: Roman Li Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/link/link_factory.c | 8 +++++--- drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c | 9 +++++++-- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 5fbcf04c62518..6f4c3c73e113e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -564,9 +564,11 @@ static bool construct_phy(struct dc_link *link, enc_init_data.analog_engine = find_analog_engine(link, &enc_init_data.analog_encoder); enc_init_data.encoder = link_encoder; enc_init_data.analog_engine = link_analog_engine; - enc_init_data.hpd_gpio = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, - link->ctx->gpio_service); - + if (link->ctx->dce_version <= DCN_VERSION_4_01) + enc_init_data.hpd_gpio = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, + link->ctx->gpio_service); + else + enc_init_data.hpd_gpio = NULL; if (enc_init_data.hpd_gpio) { dal_gpio_open(enc_init_data.hpd_gpio, GPIO_MODE_INTERRUPT); dal_gpio_unlock_pin(enc_init_data.hpd_gpio); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c index 29f3a03687b2d..b157d05b67ad2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c @@ -136,8 +136,13 @@ enum hpd_source_id get_hpd_line(struct dc_link *link) hpd_id = HPD_SOURCEID_UNKNOWN; - hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, - link->ctx->gpio_service); + /* Use GPIO path where supported, otherwise use hardware encoder path */ + if (link->ctx && link->ctx->dce_version <= DCN_VERSION_4_01) { + hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, + link->ctx->gpio_service); + } else { + hpd = NULL; + } if (hpd) { switch (dal_irq_get_source(hpd)) { From e6c4b6c72d9ab4bffcc584ba8e75fa7a41a82211 Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Mon, 26 Jan 2026 15:55:18 +0800 Subject: [PATCH 0134/2070] drm/amd/display: Parse all extension blocks for VSDB [Why] VSDB parsing loop only searched within the first extension block. If the VSDB was located in a subsequent extension block, it would not be found. [How] Calculate the total length of all extension blocks (EDID_LENGTH * edid->extensions) and use that as the loop boundary, allowing the parser to search through all available extension blocks. Reviewed-by: Tom Chung Signed-off-by: Ray Wu Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9fcb4677d0f06..510df1134b56a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13149,6 +13149,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, u8 *edid_ext = NULL; int i; int j = 0; + int total_ext_block_len; if (edid == NULL || edid->extensions == 0) return -ENODEV; @@ -13160,7 +13161,8 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, break; } - while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) { + total_ext_block_len = EDID_LENGTH * edid->extensions; + while (j < total_ext_block_len - sizeof(struct amd_vsdb_block)) { struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); From 3de1ab83ed819839500ebb6f2905256dbbe18ef4 Mon Sep 17 00:00:00 2001 From: Muaaz Nisar Date: Wed, 21 Jan 2026 14:25:38 -0500 Subject: [PATCH 0135/2070] Revert "drm/amd/display: mouse event trigger to boost RR when idle" This reverts commit 67f77421bdb59680ff047cb230a4f00946539e6b. It cause some regression. Reviewed-by: Sreeja Golui Signed-off-by: Muaaz Nisar Signed-off-by: Tom Chung --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index ecd08580937de..9349cccc8438d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -515,21 +515,6 @@ bool dc_stream_program_cursor_position( } } - /* apply manual trigger */ - int i; - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - - /* trigger event on first pipe with current stream */ - if (stream == pipe_ctx->stream && - pipe_ctx->stream_res.tg->funcs->program_manual_trigger) { - pipe_ctx->stream_res.tg->funcs->program_manual_trigger( - pipe_ctx->stream_res.tg); - break; - } - } - return true; } From 20c2814c155419b9a0a7b3bfd0e51f848b8aaf44 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Wed, 28 Jan 2026 15:52:46 -0500 Subject: [PATCH 0136/2070] drm/amd/display: Correct hubp GfxVersion verification [Why] DcGfxBase case was not accounted for in hubp program tiling functions, causing tiling corruption on PNP. [How] Add handling for DcGfxBase so that tiling gets properly cleared. Reviewed-by: Charlene Liu Signed-off-by: Nicholas Carbones Signed-off-by: Tom Chung --- .../amd/display/dc/hubp/dcn10/dcn10_hubp.c | 35 +++++++++++-------- .../amd/display/dc/hubp/dcn20/dcn20_hubp.c | 28 ++++++++------- .../amd/display/dc/hubp/dcn30/dcn30_hubp.c | 28 ++++++++------- 3 files changed, 52 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index e697d9bf1b44c..78c866688c615 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c @@ -145,21 +145,26 @@ void hubp1_program_tiling( { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - ASSERT(info->gfxversion == DcGfxVersion9); - - REG_UPDATE_6(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - NUM_BANKS, log_2(info->gfx9.num_banks), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - NUM_SE, log_2(info->gfx9.num_shader_engines), - NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); - - REG_UPDATE_4(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, info->gfx9.meta_linear, - RB_ALIGNED, info->gfx9.rb_aligned, - PIPE_ALIGNED, info->gfx9.pipe_aligned); + ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase); + + if (info->gfxversion == DcGfxVersion9) { + REG_UPDATE_6(DCSURF_ADDR_CONFIG, + NUM_PIPES, log_2(info->gfx9.num_pipes), + NUM_BANKS, log_2(info->gfx9.num_banks), + PIPE_INTERLEAVE, info->gfx9.pipe_interleave, + NUM_SE, log_2(info->gfx9.num_shader_engines), + NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), + MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); + + REG_UPDATE_4(DCSURF_TILING_CONFIG, + SW_MODE, info->gfx9.swizzle, + META_LINEAR, info->gfx9.meta_linear, + RB_ALIGNED, info->gfx9.rb_aligned, + PIPE_ALIGNED, info->gfx9.pipe_aligned); + } else { + hubp1_clear_tiling(&hubp1->base); + } + } void hubp1_program_size( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index 4715e60e812ac..aaa8f8cf6c303 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -313,18 +313,22 @@ static void hubp2_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion9); - - REG_UPDATE_3(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); - - REG_UPDATE_4(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, 0, - RB_ALIGNED, 0, - PIPE_ALIGNED, 0); + ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase); + + if (info->gfxversion == DcGfxVersion9) { + REG_UPDATE_3(DCSURF_ADDR_CONFIG, + NUM_PIPES, log_2(info->gfx9.num_pipes), + PIPE_INTERLEAVE, info->gfx9.pipe_interleave, + MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); + + REG_UPDATE_4(DCSURF_TILING_CONFIG, + SW_MODE, info->gfx9.swizzle, + META_LINEAR, 0, + RB_ALIGNED, 0, + PIPE_ALIGNED, 0); + } else { + hubp2_clear_tiling(&hubp2->base); + } } void hubp2_program_size( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 207c2f86b7d78..2126830a5a9e1 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -321,18 +321,22 @@ void hubp3_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion9); - - REG_UPDATE_4(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), - NUM_PKRS, log_2(info->gfx9.num_pkrs)); - - REG_UPDATE_3(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, info->gfx9.meta_linear, - PIPE_ALIGNED, info->gfx9.pipe_aligned); + ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase); + + if (info->gfxversion == DcGfxVersion9) { + REG_UPDATE_4(DCSURF_ADDR_CONFIG, + NUM_PIPES, log_2(info->gfx9.num_pipes), + PIPE_INTERLEAVE, info->gfx9.pipe_interleave, + MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), + NUM_PKRS, log_2(info->gfx9.num_pkrs)); + + REG_UPDATE_3(DCSURF_TILING_CONFIG, + SW_MODE, info->gfx9.swizzle, + META_LINEAR, info->gfx9.meta_linear, + PIPE_ALIGNED, info->gfx9.pipe_aligned); + } else { + hubp3_clear_tiling(&hubp2->base); + } } From f1f956f2c6e7fc77c1544f14110c654aadae9446 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Wed, 28 Jan 2026 12:28:54 -0500 Subject: [PATCH 0137/2070] drm/amd/display: Revert "Migrate DCCG register access from hwseq to dccg component." [Why & How] This reverts commit a90acf60ab9dc283d0a13ede90e393c702a985c7, which causes regressions related to HDCP when resuming from S3. Reviewed-by: Joshua Aberback Signed-off-by: Nicholas Carbones Signed-off-by: Tom Chung --- .../amd/display/dc/dccg/dcn20/dcn20_dccg.c | 54 +------------------ .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 18 ++----- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 29 +++++++--- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 9 ++-- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 -- 12 files changed, 49 insertions(+), 98 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c index 50b98822b6fdb..33d8bd91cb014 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c @@ -131,54 +131,6 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg) { - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - /* Hardcoded register values for DCN20 - * These are specific to 100Mhz refclk - * Different ASICs with different refclk may override this in their own init - */ - REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); - REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); - - if (REG(REFCLK_CNTL)) - REG_WRITE(REFCLK_CNTL, 0); -} - -void dccg2_refclk_setup(struct dccg *dccg) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - /* REFCLK programming that must occur after hubbub initialization */ - if (REG(REFCLK_CNTL)) - REG_WRITE(REFCLK_CNTL, 0); -} - -bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464; -} - -void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (allow) { - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - } else { - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); - } -} - -void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); } static const struct dccg_funcs dccg2_funcs = { @@ -187,11 +139,7 @@ static const struct dccg_funcs dccg2_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init, - .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ - .allow_clock_gating = dccg2_allow_clock_gating, - .enable_memory_low_power = dccg2_enable_memory_low_power, - .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done + .dccg_init = dccg2_init }; struct dccg *dccg2_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 237a684ded860..8bdffd9ff31b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -46,9 +46,7 @@ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\ - SR(DCCG_GATE_DISABLE_CNTL),\ - SR(DCCG_GATE_DISABLE_CNTL2) + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) #define DCCG_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -83,8 +81,7 @@ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ - DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) @@ -133,8 +130,7 @@ type DISPCLK_CHG_FWD_CORR_DISABLE;\ type DISPCLK_FREQ_CHANGE_CNTL;\ type OTG_ADD_PIXEL[MAX_PIPES];\ - type OTG_DROP_PIXEL[MAX_PIPES];\ - type DC_MEM_GLOBAL_PWR_REQ_DIS; + type OTG_DROP_PIXEL[MAX_PIPES]; #define DCCG3_REG_FIELD_LIST(type) \ type HDMICHARCLK0_EN;\ @@ -519,14 +515,6 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg); -void dccg2_refclk_setup(struct dccg *dccg); - -bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg); - -void dccg2_allow_clock_gating(struct dccg *dccg, bool allow); - -void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable); - struct dccg *dccg2_create( struct dc_context *ctx, const struct dccg_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 5243177c1faad..9613d1ceb5dcb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -1887,8 +1887,9 @@ void dcn10_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) - dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 307e8f8060e6d..0ee3a0041c619 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -357,10 +357,26 @@ void dcn20_enable_power_gating_plane( void dcn20_dccg_init(struct dce_hwseq *hws) { - struct dc *dc = hws->ctx->dc; + /* + * set MICROSECOND_TIME_BASE_DIV + * 100Mhz refclk -> 0x120264 + * 27Mhz refclk -> 0x12021b + * 48Mhz refclk -> 0x120230 + * + */ + REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); + + /* + * set MILLISECOND_TIME_BASE_DIV + * 100Mhz refclk -> 0x1186a0 + * 27Mhz refclk -> 0x106978 + * 48Mhz refclk -> 0x10bb80 + * + */ + REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init) - dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg); + /* This value is dependent on the hardware pipeline delay so set once per SOC */ + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); } void dcn20_disable_vga( @@ -3140,11 +3156,8 @@ void dcn20_fpga_init_hw(struct dc *dc) dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); - if (hws->funcs.dccg_init) - hws->funcs.dccg_init(hws); - - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup) - dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg); + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index ce18d75fd9918..6298bd87a18b7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -367,8 +367,9 @@ void dcn201_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) - dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index 062745389d9a4..e2269211553ce 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -33,7 +33,6 @@ #include "vmid.h" #include "reg_helper.h" #include "hw/clk_mgr.h" -#include "hw/dccg.h" #include "dc_dmub_srv.h" #include "abm.h" #include "link_service.h" @@ -88,10 +87,12 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_ bool dcn21_s0i3_golden_init_wa(struct dc *dc) { - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done) - return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); + struct dce_hwseq *hws = dc->hwseq; + uint32_t value = 0; - return false; + value = REG_READ(MICROSECOND_TIME_BASE_DIV); + + return value != 0x00120464; } void dcn21_exit_optimized_pwr_state( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index d04cfd403b7ee..333275088a6c2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -801,8 +801,9 @@ void dcn30_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) - dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index db2f7cbb12ff5..fa35d538a10a5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -247,8 +247,9 @@ void dcn31_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) - dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 2767d3a97812e..01fa459ae7b06 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -963,8 +963,9 @@ void dcn32_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) - dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index b5a4cefbd35f2..0cbd75ab61a1e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -286,8 +286,7 @@ void dcn35_init_hw(struct dc *dc) } if (dc->debug.disable_mem_low_power) { - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power) - dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false); + REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); } if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index b91517b9fedcf..d1515039e8249 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -326,8 +326,9 @@ void dcn401_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) - dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index a26d31ab7cba2..1e6ffd86a4c0a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -224,9 +224,6 @@ struct dccg_funcs { void (*otg_drop_pixel)(struct dccg *dccg, uint32_t otg_inst); void (*dccg_init)(struct dccg *dccg); - void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */ - void (*allow_clock_gating)(struct dccg *dccg, bool allow); - void (*enable_memory_low_power)(struct dccg *dccg, bool enable); void (*set_dpstreamclk_root_clock_gating)( struct dccg *dccg, int dp_hpo_inst, @@ -337,7 +334,6 @@ struct dccg_funcs { void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable); - bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg); }; #endif //__DAL_DCCG_H__ From f72c330470a8f6d347a2ad0dc80d1d7a0a58a254 Mon Sep 17 00:00:00 2001 From: Clay King Date: Fri, 30 Jan 2026 11:40:06 -0500 Subject: [PATCH 0138/2070] drm/amd/display: bypass post csc for additional color spaces in dal [Why] For RGB BT2020 full and limited color spaces, overlay adjustments were applied twice (once by MM and once by DAL). This results in incorrect colours and a noticeable difference between mpo and non-mpo cases. [How] Add RGB BT2020 full and limited color spaces to list that bypasses post csc adjustment. Reviewed-by: Aric Cyr Signed-off-by: Clay King Signed-off-by: Tom Chung --- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 21 ++++++++++++++++--- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 4 ++++ .../amd/display/dc/dpp/dcn401/dcn401_dpp.c | 6 +++--- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index ef4a161171814..c7923531da83d 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -376,10 +376,10 @@ void dpp3_cnv_setup ( tbl_entry.color_space = input_color_space; - if (color_space >= COLOR_SPACE_YCBCR601) - select = INPUT_CSC_SELECT_ICSC; - else + if (dpp3_should_bypass_post_csc_for_colorspace(color_space)) select = INPUT_CSC_SELECT_BYPASS; + else + select = INPUT_CSC_SELECT_ICSC; dpp3_program_post_csc(dpp_base, color_space, select, &tbl_entry); @@ -1541,3 +1541,18 @@ bool dpp3_construct( return true; } +bool dpp3_should_bypass_post_csc_for_colorspace(enum dc_color_space dc_color_space) +{ + switch (dc_color_space) { + case COLOR_SPACE_UNKNOWN: + case COLOR_SPACE_SRGB: + case COLOR_SPACE_XR_RGB: + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_MSREF_SCRGB: + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + return true; + default: + return false; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h index d4a70b4379eaf..6a61b99d6a798 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h @@ -644,4 +644,8 @@ void dpp3_program_cm_dealpha( void dpp3_cm_get_gamut_remap(struct dpp *dpp_base, struct dpp_grph_csc_adjustment *adjust); + +bool dpp3_should_bypass_post_csc_for_colorspace( + enum dc_color_space dc_color_space); + #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c index 96c2c853de42c..2d6a646462e21 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c @@ -206,10 +206,10 @@ void dpp401_dpp_setup( tbl_entry.color_space = input_color_space; - if (color_space >= COLOR_SPACE_YCBCR601) - select = INPUT_CSC_SELECT_ICSC; - else + if (dpp3_should_bypass_post_csc_for_colorspace(color_space)) select = INPUT_CSC_SELECT_BYPASS; + else + select = INPUT_CSC_SELECT_ICSC; dpp3_program_post_csc(dpp_base, color_space, select, &tbl_entry); From 7a04ae1c75f7767e0e11e238c014f69f74d1d0d1 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 7 Jan 2026 17:31:37 -0700 Subject: [PATCH 0139/2070] drm/amd/display: Fix the incorrect type in dml_print [Why & How] soc->max_outstanding_reqs is a dml_uint_t, not a dml_float_t. Reviewed-by: Austin Zheng Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Hung Signed-off-by: Tom Chung --- drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c index 89890c88fd66f..4022f91193ed9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c @@ -655,7 +655,7 @@ __DML_DLL_EXPORT__ void dml_print_soc_bounding_box(const struct soc_bounding_box dml_print("DML: soc_bbox: refclk_mhz = %f\n", soc->refclk_mhz); dml_print("DML: soc_bbox: amclk_mhz = %f\n", soc->amclk_mhz); - dml_print("DML: soc_bbox: max_outstanding_reqs = %f\n", soc->max_outstanding_reqs); + dml_print("DML: soc_bbox: max_outstanding_reqs = %d\n", soc->max_outstanding_reqs); dml_print("DML: soc_bbox: pct_ideal_sdp_bw_after_urgent = %f\n", soc->pct_ideal_sdp_bw_after_urgent); dml_print("DML: soc_bbox: pct_ideal_fabric_bw_after_urgent = %f\n", soc->pct_ideal_fabric_bw_after_urgent); dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_only = %f\n", soc->pct_ideal_dram_bw_after_urgent_pixel_only); From 826b9838823111c8a3d30deca1d1b4f8c5aac93b Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 30 Jan 2026 16:29:05 -0500 Subject: [PATCH 0140/2070] drm/amd/display: [FW Promotion] Release 0.1.46.0 Add some struct member and enum for panel replay Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 3b4f5e990ec5d..6f388c910e18a 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1638,6 +1638,11 @@ enum dmub_gpint_command { * DESC: Initiates IPS wake sequence. */ DMUB_GPINT__IPS_DEBUG_WAKE = 137, + /** + * DESC: Do panel power off sequence + * ARGS: 1 - Power off + */ + DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138, }; /** @@ -4408,6 +4413,7 @@ enum dmub_cmd_panel_replay_type { enum dmub_cmd_panel_replay_state_update_subtype { PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, PR_STATE_UPDATE_SYNC_MODE = 0x2, + PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3, }; enum dmub_cmd_panel_replay_general_subtype { @@ -6701,6 +6707,13 @@ struct dmub_rb_cmd_pr_copy_settings { struct dmub_cmd_pr_copy_settings_data data; }; +union dmub_pr_runtime_flags { + struct { + uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR + } bitfields; + uint32_t u32All; +}; + struct dmub_cmd_pr_update_state_data { /** * Panel Instance. @@ -6719,6 +6732,8 @@ struct dmub_cmd_pr_update_state_data { */ uint32_t coasting_vtotal; uint32_t sync_mode; + + union dmub_pr_runtime_flags pr_runtime_flags; }; struct dmub_cmd_pr_general_cmd_data { From 2094073a228379bc3a001ff71368869025cdd3c1 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 30 Jan 2026 18:35:15 -0500 Subject: [PATCH 0141/2070] drm/amd/display: Promote DC to 3.2.369 This version brings along following update: -Fix system resume lag issue -Correct hubp GfxVersion verification -Add parse all extension blocks for VSDB -Increase DCN35 SR enter/exit latency -Refactor virtual directory reorganize encoder and hwss files -Set enable_legacy_fast_update to false for DCN36 -Have dm_atomic_state context aligned with dc_state current -Avoid updating surface with the same surface under MPO Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fdfcfa416d16b..ce08477d1ccd9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.368" +#define DC_VER "3.2.369" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 262ab71b9da98569e43833034279b19bd587b73a Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 6 Feb 2026 20:06:19 +0530 Subject: [PATCH 0142/2070] drm/amd/display: Fix dc_link NULL handling in HPD init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_dm_hpd_init() may see connectors without a valid dc_link. The code already checks dc_link for the polling decision, but later unconditionally dereferences it when setting up HPD interrupts. Assign dc_link early and skip connectors where it is NULL. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.c:940 amdgpu_dm_hpd_init() error: we previously assumed 'dc_link' could be null (see line 931) drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.c 923 /* 924 * Analog connectors may be hot-plugged unlike other connector 925 * types that don't support HPD. Only poll analog connectors. 926 */ 927 use_polling |= 928 amdgpu_dm_connector->dc_link && ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The patch adds this NULL check but hopefully it can be removed 929 dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id); 930 931 dc_link = amdgpu_dm_connector->dc_link; dc_link assigned here. 932 933 /* 934 * Get a base driver irq reference for hpd ints for the lifetime 935 * of dm. Note that only hpd interrupt types are registered with 936 * base driver; hpd_rx types aren't. IOW, amdgpu_irq_get/put on 937 * hpd_rx isn't available. DM currently controls hpd_rx 938 * explicitly with dc_interrupt_set() 939 */ --> 940 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { ^^^^^^^^^^^^^^^^^^^^^^^ If it's NULL then we are trouble because we dereference it here. 941 irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1; 942 /* 943 * TODO: There's a mismatch between mode_info.num_hpd 944 * and what bios reports as the # of connectors with hpd Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Cc: Timur Kristóf Cc: Harry Wentland Cc: Mario Limonciello Cc: Alex Hung Cc: Aurabindo Pillai Cc: ChiaHsuan Chung Cc: Roman Li Reported-by: Dan Carpenter Signed-off-by: Srinivasan Shanmugam Reviewed-by: Timur Kristóf Change-Id: Ib6f3a040d409fc10ebd1d0fe518b092c999040d7 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index e7b0928bd3db7..5948e2a6219e3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -919,16 +919,15 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) continue; amdgpu_dm_connector = to_amdgpu_dm_connector(connector); + dc_link = amdgpu_dm_connector->dc_link; + if (!dc_link) + continue; /* * Analog connectors may be hot-plugged unlike other connector * types that don't support HPD. Only poll analog connectors. */ - use_polling |= - amdgpu_dm_connector->dc_link && - dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id); - - dc_link = amdgpu_dm_connector->dc_link; + use_polling |= dc_connector_supports_analog(dc_link->link_id.id); /* * Get a base driver irq reference for hpd ints for the lifetime From 2862456c2fd8a25de39198b1ace9b1b0d2058f09 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 6 Feb 2026 19:53:05 +0530 Subject: [PATCH 0143/2070] drm/amdgpu: Fix missing unwind in amdgpu_ib_schedule() error path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_ib_schedule() returns early after calling amdgpu_ring_undo(). This skips the common free_fence cleanup path. Other error paths were already changed to use goto free_fence, but this one was missed. Change the early return to goto free_fence so all error paths clean up the same way. Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:232 amdgpu_ib_schedule() warn: missing unwind goto? drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 124 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 125 struct amdgpu_ib *ibs, struct amdgpu_job *job, 126 struct dma_fence **f) 127 { ... 224 225 if (ring->funcs->insert_start) 226 ring->funcs->insert_start(ring); 227 228 if (job) { 229 r = amdgpu_vm_flush(ring, job, need_pipe_sync); 230 if (r) { 231 amdgpu_ring_undo(ring); --> 232 return r; The patch changed the other error paths to goto free_fence but this one was accidentally skipped. 233 } 234 } 235 236 amdgpu_ring_ib_begin(ring); ... 338 339 free_fence: 340 if (!job) 341 kfree(af); 342 return r; 343 } Fixes: f903b85ed0f1 ("drm/amdgpu: fix possible fence leaks from job structure") Reported-by: Dan Carpenter Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher Change-Id: I89c53e3fc1378c431256ff286669d1e292f198ab --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 44f230d67da24..bfa64cd7a62d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, r = amdgpu_vm_flush(ring, job, need_pipe_sync); if (r) { amdgpu_ring_undo(ring); - return r; + goto free_fence; } } From 8e8e048164625dc181f49ba6ca16b634bfaff7c2 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 6 Feb 2026 21:18:11 +0530 Subject: [PATCH 0144/2070] drm/amdkfd: Fix watch_id bounds checking in debug address watch v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The address watch clear code receives watch_id as an unsigned value (u32), but some helper functions were using a signed int and checked bits by shifting with watch_id. If a very large watch_id is passed from userspace, it can be converted to a negative value. This can cause invalid shifts and may access memory outside the watch_points array. drm/amdkfd: Fix watch_id bounds checking in debug address watch v2 Fix this by checking that watch_id is within MAX_WATCH_ADDRESSES before using it. Also use BIT(watch_id) to test and clear bits safely. This keeps the behavior unchanged for valid watch IDs and avoids undefined behavior for invalid ones. Fixes the below: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debug.c:448 kfd_dbg_trap_clear_dev_address_watch() error: buffer overflow 'pdd->watch_points' 4 <= u32max user_rl='0-3,2147483648-u32max' uncapped drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debug.c 433 int kfd_dbg_trap_clear_dev_address_watch(struct kfd_process_device *pdd, 434 uint32_t watch_id) 435 { 436 int r; 437 438 if (!kfd_dbg_owns_dev_watch_id(pdd, watch_id)) kfd_dbg_owns_dev_watch_id() doesn't check for negative values so if watch_id is larger than INT_MAX it leads to a buffer overflow. (Negative shifts are undefined). 439 return -EINVAL; 440 441 if (!pdd->dev->kfd->shared_resources.enable_mes) { 442 r = debug_lock_and_unmap(pdd->dev->dqm); 443 if (r) 444 return r; 445 } 446 447 amdgpu_gfx_off_ctrl(pdd->dev->adev, false); --> 448 pdd->watch_points[watch_id] = pdd->dev->kfd2kgd->clear_address_watch( 449 pdd->dev->adev, 450 watch_id); v2: (as per, Jonathan Kim) - Add early watch_id >= MAX_WATCH_ADDRESSES validation in the set path to match the clear path. - Drop the redundant bounds check in kfd_dbg_owns_dev_watch_id(). Fixes: e0f85f4690d0 ("drm/amdkfd: add debug set and clear address watch points operation") Reported-by: Dan Carpenter Cc: Jonathan Kim Cc: Felix Kuehling Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 1dae317858e93..bedb95ce96590 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -404,27 +404,25 @@ static int kfd_dbg_get_dev_watch_id(struct kfd_process_device *pdd, int *watch_i return -ENOMEM; } -static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, int watch_id) +static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id) { spin_lock(&pdd->dev->watch_points_lock); /* process owns device watch point so safe to clear */ - if ((pdd->alloc_watch_ids >> watch_id) & 0x1) { - pdd->alloc_watch_ids &= ~(0x1 << watch_id); - pdd->dev->alloc_watch_ids &= ~(0x1 << watch_id); + if (pdd->alloc_watch_ids & BIT(watch_id)) { + pdd->alloc_watch_ids &= ~BIT(watch_id); + pdd->dev->alloc_watch_ids &= ~BIT(watch_id); } spin_unlock(&pdd->dev->watch_points_lock); } -static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, int watch_id) +static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id) { bool owns_watch_id = false; spin_lock(&pdd->dev->watch_points_lock); - owns_watch_id = watch_id < MAX_WATCH_ADDRESSES && - ((pdd->alloc_watch_ids >> watch_id) & 0x1); - + owns_watch_id = pdd->alloc_watch_ids & BIT(watch_id); spin_unlock(&pdd->dev->watch_points_lock); return owns_watch_id; @@ -435,6 +433,9 @@ int kfd_dbg_trap_clear_dev_address_watch(struct kfd_process_device *pdd, { int r; + if (watch_id >= MAX_WATCH_ADDRESSES) + return -EINVAL; + if (!kfd_dbg_owns_dev_watch_id(pdd, watch_id)) return -EINVAL; @@ -472,6 +473,9 @@ int kfd_dbg_trap_set_dev_address_watch(struct kfd_process_device *pdd, if (r) return r; + if (*watch_id >= MAX_WATCH_ADDRESSES) + return -EINVAL; + if (!pdd->dev->kfd->shared_resources.enable_mes) { r = debug_lock_and_unmap(pdd->dev->dqm); if (r) { From 023dd9fd3dd13ed169fa9cd3b737fdf0e07605b5 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 4 Feb 2026 01:38:23 -0500 Subject: [PATCH 0145/2070] drm/amd/pm: use sysfs_streq for string matching in amdgpu_pm The driver uses strncmp() to compare sysfs attribute strings, which does not handle trailing newlines and lacks NULL safety. sysfs_streq() is the recommended function for sysfs string equality checks in the kernel, providing safer and more correct behavior. replace strncmp() with sysfs_streq() in drivers/gpu/drm/amd/pm/amdgpu_pm.c Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 07641c9413d2f..938361ecae055 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -243,11 +243,11 @@ static ssize_t amdgpu_set_power_dpm_state(struct device *dev, enum amd_pm_state_type state; int ret; - if (strncmp("battery", buf, strlen("battery")) == 0) + if (sysfs_streq(buf, "battery")) state = POWER_STATE_TYPE_BATTERY; - else if (strncmp("balanced", buf, strlen("balanced")) == 0) + else if (sysfs_streq(buf, "balanced")) state = POWER_STATE_TYPE_BALANCED; - else if (strncmp("performance", buf, strlen("performance")) == 0) + else if (sysfs_streq(buf, "performance")) state = POWER_STATE_TYPE_PERFORMANCE; else return -EINVAL; @@ -363,29 +363,28 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, enum amd_dpm_forced_level level; int ret = 0; - if (strncmp("low", buf, strlen("low")) == 0) { + if (sysfs_streq(buf, "low")) level = AMD_DPM_FORCED_LEVEL_LOW; - } else if (strncmp("high", buf, strlen("high")) == 0) { + else if (sysfs_streq(buf, "high")) level = AMD_DPM_FORCED_LEVEL_HIGH; - } else if (strncmp("auto", buf, strlen("auto")) == 0) { + else if (sysfs_streq(buf, "auto")) level = AMD_DPM_FORCED_LEVEL_AUTO; - } else if (strncmp("manual", buf, strlen("manual")) == 0) { + else if (sysfs_streq(buf, "manual")) level = AMD_DPM_FORCED_LEVEL_MANUAL; - } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { + else if (sysfs_streq(buf, "profile_exit")) level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; - } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { + else if (sysfs_streq(buf, "profile_standard")) level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; - } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { + else if (sysfs_streq(buf, "profile_min_sclk")) level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; - } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { + else if (sysfs_streq(buf, "profile_min_mclk")) level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; - } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { + else if (sysfs_streq(buf, "profile_peak")) level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; - } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { + else if (sysfs_streq(buf, "perf_determinism")) level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; - } else { + else return -EINVAL; - } ret = amdgpu_pm_get_access(adev); if (ret < 0) From 9d9f7a7ab50ea8d8dbba1f0d9f288ee9783dc1c1 Mon Sep 17 00:00:00 2001 From: Benjamin Welton Date: Wed, 9 Oct 2024 21:32:55 -0700 Subject: [PATCH 0146/2070] Add kfd_ioctl_profiler to contain profiler kernel driver changes kfd_ioctl_profiler takes a similar approach to that of kfd_ioctl_dbg_trap (which contains debugger related IOCTL services) where kfd_ioctl_profiler will contain all profiler related IOCTL services. The IOCTL is designed to be expanded as needed to support additional profiler functionality. The current functionality of the IOCTL is to allow for profilers which need PMC counters from GPU devices to both signal to other profilers that may be on the system that the device has active PMC profiling taking place on it (multiple PMC profilers on the same device can result in corrupted counter data) and to setup the device to allow for the collection of SQ PMC data on all queues on the device. For PMC data for the SQ block (such as SQ_WAVES) to be available to a profiler, mmPERFCOUNT_ENABLE must be set on the queues. When profiling a single process, the profiler can inject PM4 packets into each queue to turn on PERFCOUNT_ENABLE. When profiling system wide, the profiler does not have this option and must have a way to turn on profiling for queues in which it cannot inject packets into directly. Accomplishing this requires a few steps: 1. Checking if the user has the necessary permissions to profile system wide on the device. This check uses the same check that linux perf uses to determine if a user has the necessary permissions to profile at this scope (primarily if the process has CAP_SYS_PERFMON or is root). 2. Locking the device for profiling. This is done by setting a lock bit on the device struct and storing the process that locked the device. 3. Iterating all queues on the device and issuing an MQD Update to enable perfcounting on the queues. 4. Actions to cleanup if the process exits or releases the lock. The IOCTL also contains a link to the existing PC Sampling IOCTL as well. This is per a suggestion that we should potentially remove the PC Sampling IOCTL to have it be a part of the profiler IOCTL. This is a future change. In addition, we do expect to expand the profiler IOCTL to include additional profiler functionality in the future (which necessitates the use of a version number). Signed-off-by: Benjamin Welton Signed-off-by: Perry Yuan Acked-by: Kent Russell Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 82 +++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 ++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 14 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 8 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 15 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 11 +++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 +++ include/uapi/linux/kfd_ioctl.h | 29 +++++++ 12 files changed, 216 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 732ad1224a619..dbb111a33678a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include @@ -3204,6 +3205,84 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v return 0; } +static inline uint32_t profile_lock_device(struct kfd_process *p, + uint32_t gpu_id, uint32_t op) +{ + struct kfd_process_device *pdd; + struct kfd_dev *kfd; + int status = -EINVAL; + + if (!p) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + kfd = pdd->dev->kfd; + + mutex_lock(&kfd->profiler_lock); + if (op == 1) { + if (!kfd->profiler_process) { + kfd->profiler_process = p; + status = 0; + } else if (kfd->profiler_process == p) { + status = -EALREADY; + } else { + status = -EBUSY; + } + } else if (op == 0 && kfd->profiler_process == p) { + kfd->profiler_process = NULL; + status = 0; + } + mutex_unlock(&kfd->profiler_lock); + + return status; +} + +static inline int kfd_profiler_pmc(struct kfd_process *p, + struct kfd_ioctl_pmc_settings *args) +{ + struct kfd_process_device *pdd; + struct device_queue_manager *dqm; + int status; + + /* Check if we have the correct permissions. */ + if (!perfmon_capable()) + return -EPERM; + + /* Lock/Unlock the device based on the parameter given in OP */ + status = profile_lock_device(p, args->gpu_id, args->lock); + if (status != 0) + return status; + + /* Enable/disable perfcount if requested */ + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + dqm = pdd->dev->dqm; + mutex_unlock(&p->mutex); + + dqm->ops.set_perfcount(dqm, args->perfcount_enable); + return status; +} + +static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_profiler_args *args = data; + + switch (args->op) { + case KFD_IOC_PROFILER_VERSION: + args->version = KFD_IOC_PROFILER_VERSION_NUM; + return 0; + case KFD_IOC_PROFILER_PMC: + return kfd_profiler_pmc(p, &args->pmc); + } + return -EINVAL; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3325,6 +3404,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, kfd_ioctl_create_process, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, + kfd_ioctl_profiler, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 9a66ee661e57c..f231e46e85287 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -936,6 +936,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -971,6 +974,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); + mutex_destroy(&kfd->profiler_lock); } kfree(kfd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 804851632c4c8..4170a283db5ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -305,6 +305,29 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + pqm_update_mqd(qpd->pqm, q->properties.queue_id, + &minfo); + } + } + dqm_unlock(dqm); +} + static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -2967,6 +2990,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -2987,6 +3011,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index ef07e44916f80..74a3bcec3e4e5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -200,6 +200,8 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); + void (*set_perfcount)(struct device_queue_manager *dqm, + int enable); }; struct device_queue_manager_asic_ops { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 97055f808d4a1..993d60a24d50a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -124,10 +124,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -142,6 +141,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -221,6 +226,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 7e5a7ab6d0c01..4a574bbb5f379 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -164,10 +164,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -182,6 +181,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -259,6 +263,12 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index a51f217329db0..7173f6470e5e8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -139,10 +139,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -157,6 +156,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index dcf4bbfa641b5..d4659a438be56 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -218,10 +218,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) { + if (q->tba_addr) m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); - } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -236,6 +235,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -318,6 +322,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 09483f0862d41..e8967f5e38920 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -149,6 +149,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -231,6 +236,12 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9849b54f54ba0..8983065645fa9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -384,6 +384,11 @@ struct kfd_dev { int kfd_dev_lock; atomic_t kfd_processes_count; + + /* Lock for profiler process */ + struct mutex profiler_lock; + /* Process currently holding the lock */ + struct kfd_process *profiler_process; }; enum kfd_mempool { @@ -556,6 +561,8 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ + UPDATE_FLAG_PERFCOUNT_ENABLE = 5, + UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index ba25d83c23e78..214be98226571 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1110,6 +1110,16 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } +static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->dev->kfd->profiler_lock); + if (pdd->dev->kfd->profiler_process == p) { + pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + pdd->dev->kfd->profiler_process = NULL; + } + mutex_unlock(&pdd->dev->kfd->profiler_lock); +} + static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1121,6 +1131,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + kfd_process_profiler_release(p, pdd); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index e72359370857c..a8b2a18d07cf1 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1558,6 +1558,29 @@ struct kfd_ioctl_dbg_trap_args { }; }; +#define KFD_IOC_PROFILER_VERSION_NUM 1 +enum kfd_profiler_ops { + KFD_IOC_PROFILER_PMC = 0, + KFD_IOC_PROFILER_VERSION = 2, +}; + +/** + * Enables/Disables GPU Specific profiler settings + */ +struct kfd_ioctl_pmc_settings { + __u32 gpu_id; /* This is the user_gpu_id */ + __u32 lock; /* Lock GPU for Profiling */ + __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ +}; + +struct kfd_ioctl_profiler_args { + __u32 op; /* kfd_profiler_op */ + union { + struct kfd_ioctl_pmc_settings pmc; + __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ + }; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1684,4 +1707,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_COMMAND_START 0x01 #define AMDKFD_COMMAND_END 0x28 +#define AMDKFD_IOC_PROFILER \ + AMDKFD_IOWR(0x86, struct kfd_ioctl_profiler_args) + +#define AMDKFD_COMMAND_START_2 0x80 +#define AMDKFD_COMMAND_END_2 0x87 + #endif From 9d5c5b543cd57d773dc9a54f3b10ee302badd32c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 18 Jan 2026 15:57:41 +0100 Subject: [PATCH 0147/2070] drm/amd/display: Reject cursor plane on DCE when scaled differently than primary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently DCE doesn't support the overlay cursor, so the dm_crtc_get_cursor_mode() function returns DM_CURSOR_NATIVE_MODE unconditionally. The outcome is that it doesn't check for the conditions that would necessitate the overlay cursor, meaning that it doesn't reject cases where the native cursor mode isn't supported on DCE. Remove the early return from dm_crtc_get_cursor_mode() for DCE and instead let it perform the necessary checks and return DM_CURSOR_OVERLAY_MODE. Add a later check that rejects when DM_CURSOR_OVERLAY_MODE would be used with DCE. Fixes: 1b04dcca4fb1 ("drm/amd/display: Introduce overlay cursor mode") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4600 Suggested-by: Leo Li Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 510df1134b56a..ef9df52dd34bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12309,10 +12309,9 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, /* Overlay cursor not supported on HW before DCN * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions - * as previous DCN generations, so enable native mode on DCN401 in addition to DCE + * as previous DCN generations, so enable native mode on DCN401 */ - if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 || - amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { *cursor_mode = DM_CURSOR_NATIVE_MODE; return 0; } @@ -12632,6 +12631,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * need to be added for DC to not disable a plane by mistake */ if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { + drm_dbg(dev, "Overlay cursor not supported on DCE\n"); + ret = -EINVAL; + goto fail; + } + ret = drm_atomic_add_affected_planes(state, crtc); if (ret) goto fail; From 1db5ecb3e7085267e86331445852f3902d539053 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 6 Nov 2025 11:12:37 +0800 Subject: [PATCH 0148/2070] drm/amdgpu: add new performance monitor PSP interfaces Introduce new psp interfaces and structures for performance monitoring hardware control. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 21 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 17 +++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 79a49cba8d406..58f691db2e97f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -359,6 +359,27 @@ struct spirom_bo { }; #endif +enum psp_ptl_cmd { + PSP_PTL_PERF_MON_QUERY = 0xA0000000, + PSP_PTL_PERF_MON_SET = 0xA0000001, +}; + +enum psp_ptl_format_type { + GFX_FTYPE_I8 = 0x00000000, + GFX_FTYPE_F16 = 0x00000001, + GFX_FTYPE_BF16 = 0x00000002, + GFX_FTYPE_F32 = 0x00000003, + GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_INVALID = 0xFFFFFFFF, +}; + +struct psp_ptl_perf_req { + enum psp_ptl_cmd req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + struct psp_context { struct amdgpu_device *adev; struct psp_ring km_ring; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index e8f768638fd59..ac34bac3c8391 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -107,6 +107,7 @@ enum psp_gfx_cmd_id GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ /* Dynamic memory partitioninig (NPS mode change)*/ GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ + GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */ GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr */ GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation extended addr */ }; @@ -373,6 +374,13 @@ struct psp_gfx_cmd_fb_memory_part { uint32_t resvd; }; +struct psp_gfx_cmd_req_perf_hw { + uint32_t req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -389,6 +397,7 @@ union psp_gfx_commands struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; struct psp_gfx_cmd_fb_memory_part cmd_memory_part; + struct psp_gfx_cmd_req_perf_hw cmd_req_perf_hw; }; struct psp_gfx_uresp_reserved @@ -415,12 +424,20 @@ struct psp_gfx_uresp_fw_reserve_info { uint32_t reserve_size; }; +struct psp_gfx_uresp_perf_hw { + uint32_t resp; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* Union of command-specific responses for GPCOM ring. */ union psp_gfx_uresp { struct psp_gfx_uresp_reserved reserved; struct psp_gfx_uresp_bootcfg boot_cfg; struct psp_gfx_uresp_fwar_db_info fwar_db_info; struct psp_gfx_uresp_fw_reserve_info fw_reserve_info; + struct psp_gfx_uresp_perf_hw perf_hw_info; }; /* Structure of GFX Response buffer. From 09b69d137e1db4f028741fc893507d02768ea8fb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Feb 2026 11:59:40 -0500 Subject: [PATCH 0149/2070] drm/amdgpu: remove some retired module parameters The mes and mes_kiq parameters we originally added for mes bring up. However, mes is required for operation on gfx11 and newer so these parameters aren't actually used by the driver anymore. Remove them. Reviewed-by: Kent Russell Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 -------------------- 2 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1f5d15110e43b..0f6e9cdbe7d84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -217,9 +217,7 @@ extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; extern int amdgpu_async_gfx_ring; extern int amdgpu_mcbp; extern int amdgpu_discovery; -extern int amdgpu_mes; extern int amdgpu_mes_log_enable; -extern int amdgpu_mes_kiq; extern int amdgpu_uni_mes; extern int amdgpu_noretry; extern int amdgpu_force_asic_type; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 95d26f086d545..03814a23eb540 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -223,9 +223,7 @@ uint amdgpu_dc_visual_confirm; int amdgpu_async_gfx_ring = 1; int amdgpu_mcbp = -1; int amdgpu_discovery = -1; -int amdgpu_mes; int amdgpu_mes_log_enable = 0; -int amdgpu_mes_kiq; int amdgpu_uni_mes = 1; int amdgpu_noretry = -1; int amdgpu_force_asic_type = -1; @@ -690,15 +688,6 @@ MODULE_PARM_DESC(discovery, "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); module_param_named(discovery, amdgpu_discovery, int, 0444); -/** - * DOC: mes (int) - * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. - * (0 = disabled (default), 1 = enabled) - */ -MODULE_PARM_DESC(mes, - "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); -module_param_named(mes, amdgpu_mes, int, 0444); - /** * DOC: mes_log_enable (int) * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. @@ -708,15 +697,6 @@ MODULE_PARM_DESC(mes_log_enable, "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); -/** - * DOC: mes_kiq (int) - * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. - * (0 = disabled (default), 1 = enabled) - */ -MODULE_PARM_DESC(mes_kiq, - "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); -module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); - /** * DOC: uni_mes (int) * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. From e844f2ff7298ec65e5a0941574007e99279ea637 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 29 Jan 2026 14:49:13 -0500 Subject: [PATCH 0150/2070] drm/amdgpu: add a helper to calculate ring distance Add a helper to calculate the distance in DWs between two wptrs. Reviewed-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index cb0fb1a989d2f..1abd8fdb5cef6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -522,6 +522,17 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, ring->count_dw -= count_dw; } +static inline unsigned int amdgpu_ring_get_dw_distance(struct amdgpu_ring *ring, + u64 start_wptr, u64 end_wptr) +{ + unsigned int start = start_wptr & ring->buf_mask; + unsigned int end = end_wptr & ring->buf_mask; + + if (end < start) + end += ring->ring_size >> 2; + return end - start; +} + /** * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute * @ring: amdgpu_ring structure @@ -532,18 +543,13 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) { - unsigned cur; - if (!ring->funcs->init_cond_exec) return; WARN_ON(offset > ring->buf_mask); WARN_ON(ring->ring[offset] != 0); - cur = (ring->wptr - 1) & ring->buf_mask; - if (cur < offset) - cur += ring->ring_size >> 2; - ring->ring[offset] = cur - offset; + ring->ring[offset] = amdgpu_ring_get_dw_distance(ring, offset, ring->wptr - 1); } int amdgpu_ring_test_helper(struct amdgpu_ring *ring); From 2700122fa389b685ca3991190e13bd0ca8beab81 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Thu, 22 Jan 2026 18:00:27 +0800 Subject: [PATCH 0151/2070] drm/amd/pm: use debug port for mode1 reset request on smu 13&14 use debug port for mode1 reset request so fw can handle mode1 reset even when it is stuck. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 15 ++----- .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 45 ++++++++++++++++++- 2 files changed, 46 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index de770c10da3d6..784a1af46527a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2615,21 +2615,11 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - u32 smu_version; - int ret; /* SRIOV does not support SMU mode1 reset */ if (amdgpu_sriov_vf(adev)) return false; - /* PMFW support is available since 78.41 */ - ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); - if (ret) - return false; - - if (smu_version < 0x004e2900) - return false; - return true; } @@ -2828,8 +2818,9 @@ static int smu_v13_0_0_mode1_reset(struct smu_context *smu) /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */ smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m); - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_Mode1Reset, param, NULL); + ret = smu_cmn_send_debug_smc_msg_with_param(smu, + DEBUGSMC_MSG_Mode1Reset, param); + break; case IP_VERSION(13, 0, 10): diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index fe3d6bfe68121..a6c22ae86c985 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -74,6 +74,17 @@ static const struct smu_feature_bits smu_v13_0_7_dpm_features = { #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 + +#define DEBUGSMC_MSG_Mode1Reset 2 + #define PP_OD_FEATURE_GFXCLK_FMIN 0 #define PP_OD_FEATURE_GFXCLK_FMAX 1 #define PP_OD_FEATURE_UCLK_FMIN 2 @@ -2734,6 +2745,36 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, return ret; } +static int smu_v13_0_7_mode1_reset(struct smu_context *smu) +{ + int ret; + + ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); + if (!ret) { + /* disable mmio access while doing mode 1 reset*/ + smu->adev->no_hw_access = true; + /* ensure no_hw_access is globally visible before any MMIO */ + smp_mb(); + msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + } + + return ret; +} + +static void smu_v13_0_7_init_msg_ctl(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map); + + /* Set up debug mailbox registers */ + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; +} + static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .init_allowed_features = smu_v13_0_7_init_allowed_features, .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, @@ -2795,7 +2836,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .baco_enter = smu_v13_0_baco_enter, .baco_exit = smu_v13_0_baco_exit, .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported, - .mode1_reset = smu_v13_0_mode1_reset, + .mode1_reset = smu_v13_0_7_mode1_reset, .set_mp1_state = smu_v13_0_7_set_mp1_state, .set_df_cstate = smu_v13_0_7_set_df_cstate, .gpo_control = smu_v13_0_gpo_control, @@ -2814,5 +2855,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) smu->pwr_src_map = smu_v13_0_7_pwr_src_map; smu->workload_map = smu_v13_0_7_workload_map; smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION; - smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map); + smu_v13_0_7_init_msg_ctl(smu); } From 9b69b4ecd06188366f5a4185b947446cb4948efa Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Thu, 22 Jan 2026 18:04:01 +0800 Subject: [PATCH 0152/2070] drm/amd/pm: send unload command to smu during modprobe -r amdgpu Send unload command to smu during modprobe -r amdgpu for smu 13/14. 1. This can fix the high voltage/temperatue issue after driver is unloaded. 2. Reloading driver could fail but with the debug port based mode1 reset during driver is reloaded, it is good and safe. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +++---- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 - drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 +------- 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 726930431f332..6756d5faabd94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4649,9 +4649,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, dev_info(adev->dev, "Pending hive reset.\n"); amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_MINIMAL_XGMI); - } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && - !amdgpu_device_has_display_hardware(adev)) { - r = psp_gpu_reset(adev); } else { tmp = amdgpu_reset_method; /* It should do a default reset when loading or reloading the driver, diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 9f52b7b241982..18ece5c714c5e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -810,7 +810,7 @@ static int smu_early_init(struct amdgpu_ip_block *ip_block) smu->adev = adev; smu->pm_enabled = !!amdgpu_dpm; smu->is_apu = false; - smu->smu_baco.state = SMU_BACO_STATE_NONE; + smu->smu_baco.state = SMU_BACO_STATE_EXIT; smu->smu_baco.platform_support = false; smu->smu_baco.maco_support = false; smu->user_dpm_profile.fan_mode = -1; @@ -2120,9 +2120,8 @@ static int smu_reset_mp1_state(struct smu_context *smu) int ret = 0; if ((!adev->in_runpm) && (!adev->in_suspend) && - (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == - IP_VERSION(13, 0, 10) && - !amdgpu_device_has_display_hardware(adev)) + (!amdgpu_in_reset(adev)) && !smu->is_apu && + amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 512493a8452b3..a6303d093c50e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -536,7 +536,6 @@ enum smu_reset_mode { enum smu_baco_state { SMU_BACO_STATE_ENTER = 0, SMU_BACO_STATE_EXIT, - SMU_BACO_STATE_NONE, }; struct smu_baco_context { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 784a1af46527a..468d51f5f9187 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2768,13 +2768,7 @@ static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, switch (mp1_state) { case PP_MP1_STATE_UNLOAD: - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_PrepareMp1ForUnload, - 0x55, NULL); - - if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) - ret = smu_v13_0_disable_pmfw_state(smu); - + ret = smu_cmn_set_mp1_state(smu, mp1_state); break; default: /* Ignore others */ From 5f9dbdcf6e6745f1ddec90b133f273e987ff38ba Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 12 Jan 2026 10:22:38 +0000 Subject: [PATCH 0153/2070] drm/amdgpu: Remove duplicate struct member MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Struct amdgpu_ctx contains two copies of the pointer to the context manager. Remove one. Signed-off-by: Tvrtko Ursulin Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 5c344665b43cd..b19e96d4c183b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -232,7 +232,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, } else { struct amdgpu_fpriv *fpriv; - fpriv = container_of(ctx->ctx_mgr, struct amdgpu_fpriv, ctx_mgr); + /* TODO: Stop using fpriv here, we only need the xcp_id. */ + fpriv = container_of(ctx->mgr, struct amdgpu_fpriv, ctx_mgr); r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, &num_scheds, &scheds); if (r) @@ -349,7 +350,6 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, else ctx->stable_pstate = current_stable_pstate; - ctx->ctx_mgr = &(fpriv->ctx_mgr); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index aed758d0acaad..cf8d700a22fe8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -56,7 +56,6 @@ struct amdgpu_ctx { unsigned long ras_counter_ce; unsigned long ras_counter_ue; struct amdgpu_ctx_mgr *mgr; - struct amdgpu_ctx_mgr *ctx_mgr; struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM]; }; From 320a83dd8b027eb89a8adfa28773983ef98e54ba Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 4 Nov 2025 17:45:55 +0800 Subject: [PATCH 0154/2070] drm/amdgpu: add psp interfaces for peak tops limiter driver Introduce a Peak Tops Limiter (PTL) driver that dynamically caps engine frequency to ensure delivered TOPS never exceeds a defined TOPS_limit. This initial implementation provides core data structures and kernel-space interfaces (set/get, enable/disable) to manage PTL state. PTL performs a firmware handshake to initialize its state and update predefined format types. It supports updating these format types at runtime while user-space tools automatically switch PTL state, and also allows explicitly switching PTL state via newly added commands. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 111 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 + drivers/gpu/drm/amd/include/amdgpu_ptl.h | 50 ++++++++ .../gpu/drm/amd/include/kgd_kfd_interface.h | 1 + 7 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/include/amdgpu_ptl.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index cdbab7f8cee8c..4fee011c2e261 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -38,6 +38,8 @@ #include "amdgpu_vm.h" #include "amdgpu_xcp.h" #include "kfd_topology.h" +#include "amdgpu_ptl.h" + extern uint64_t amdgpu_amdkfd_total_mem_size; enum TLB_FLUSH_TYPE { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6756d5faabd94..32e5787f04e07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4435,6 +4435,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); + mutex_init(&adev->psp.ptl.mutex); mutex_init(&adev->notifier_lock); mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index b0540b009e84a..3d0d71bfe73dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -679,6 +679,8 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "SPATIAL_PARTITION"; case GFX_CMD_ID_FB_NPS_MODE: return "NPS_MODE_CHANGE"; + case GFX_CMD_ID_PERF_HW: + return "PERF MONITORING HW"; default: return "UNKNOWN CMD"; } @@ -1197,6 +1199,115 @@ int psp_memory_partition(struct psp_context *psp, int mode) return ret; } +static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, + uint32_t *ptl_fmt) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) + return -EINVAL; + + switch (fmt) { + case AMDGPU_PTL_FMT_I8: + *ptl_fmt = GFX_FTYPE_I8; + break; + case AMDGPU_PTL_FMT_F16: + *ptl_fmt = GFX_FTYPE_F16; + break; + case AMDGPU_PTL_FMT_BF16: + *ptl_fmt = GFX_FTYPE_BF16; + break; + case AMDGPU_PTL_FMT_F32: + *ptl_fmt = GFX_FTYPE_F32; + break; + case AMDGPU_PTL_FMT_F64: + *ptl_fmt = GFX_FTYPE_F64; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +{ + struct psp_gfx_cmd_resp *cmd; + struct amdgpu_ptl *ptl = &psp->ptl; + int ret; + + cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_PERF_HW; + cmd->cmd.cmd_req_perf_hw.req = req_code; + cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; + cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; + cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + goto out; + + /* Parse response */ + switch (req_code) { + case PSP_PTL_PERF_MON_QUERY: + *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; + *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; + *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + break; + case PSP_PTL_PERF_MON_SET: + /* Update cached state only on success */ + ptl->enabled = *ptl_state; + ptl->fmt1 = *fmt1; + ptl->fmt2 = *fmt2; + break; + } + +out: + release_psp_cmd_buf(psp); + return ret; +} + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2) +{ + uint32_t ptl_fmt1, ptl_fmt2; + struct psp_context *psp; + struct amdgpu_ptl *ptl; + + if (!adev || !ptl_state || !fmt1 || !fmt2) + return -EINVAL; + + if (amdgpu_sriov_vf(adev)) + return 0; + + psp = &adev->psp; + ptl = &psp->ptl; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || + psp->sos.fw_version < 0x0036081a) + return -EOPNOTSUPP; + + /* Verify formats */ + if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || + psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) + return -EINVAL; + + /* + * Add check to skip if state and formats are identical to current ones + */ + if (req_code == PSP_PTL_PERF_MON_SET && + ptl->enabled == *ptl_state && + ptl->fmt1 == ptl_fmt1 && + ptl->fmt2 == ptl_fmt2) + return 0; + + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 58f691db2e97f..332633f6f4be9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -31,6 +31,7 @@ #include "ta_ras_if.h" #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" +#include "amdgpu_ptl.h" #define PSP_FENCE_BUFFER_SIZE 0x1000 #define PSP_CMD_BUFFER_SIZE 0x1000 @@ -470,6 +471,7 @@ struct psp_context { #if defined(CONFIG_DEBUG_FS) struct spirom_bo *spirom_dump_trip; #endif + struct amdgpu_ptl ptl; }; struct amdgpu_psp_funcs { @@ -653,5 +655,4 @@ void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type); - #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index dbb111a33678a..9c37e82485409 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -44,6 +44,7 @@ #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" #include "kfd_debug.h" +#include "amdgpu_ptl.h" static long kfd_ioctl(struct file *, unsigned int, unsigned long); static int kfd_open(struct inode *, struct file *); diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h new file mode 100644 index 0000000000000..f309c6571e851 --- /dev/null +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -0,0 +1,50 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_PTL_H__ +#define __AMDGPU_PTL_H__ + +enum amdgpu_ptl_fmt { + AMDGPU_PTL_FMT_I8 = 0, + AMDGPU_PTL_FMT_F16 = 1, + AMDGPU_PTL_FMT_BF16 = 2, + AMDGPU_PTL_FMT_F32 = 3, + AMDGPU_PTL_FMT_F64 = 4, + AMDGPU_PTL_FMT_F8 = 5, + AMDGPU_PTL_FMT_VECTOR = 6, + AMDGPU_PTL_FMT_INVALID = 7, +}; + +struct amdgpu_ptl { + enum amdgpu_ptl_fmt fmt1; + enum amdgpu_ptl_fmt fmt2; + bool enabled; + bool hw_supported; + /* Protects PTL state and format updates */ + struct mutex mutex; +}; + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2); +#endif /* __AMDGPU_PTL_H__ */ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 9aba8596faa7e..6df5afb242aef 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -33,6 +33,7 @@ #include #include "amdgpu_irq.h" #include "amdgpu_gfx.h" +#include "amdgpu_ptl.h" struct pci_dev; struct amdgpu_device; From d8a4f446312eef4719f45cb33c926f3d54c99ab6 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Mon, 24 Nov 2025 04:40:21 +0000 Subject: [PATCH 0155/2070] drm/amdgpu: Load TA ucode for PSP 15_0_0 TOC and TA both are required Signed-off-by: Pratik Vishwakarma Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v15_0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c index 3aca293e2f0c4..723ddae176448 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c @@ -45,6 +45,10 @@ static int psp_v15_0_0_init_microcode(struct psp_context *psp) if (err) return err; + err = psp_init_ta_microcode(psp, ucode_prefix); + if (err) + return err; + return 0; } From bf56fb40055d78e333659b8c3784cba411a60ac6 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Wed, 28 Jan 2026 03:52:03 +0000 Subject: [PATCH 0156/2070] drm/amd/swsmu: Add new param regs for SMU15 Some SMU messages have changed to multi reg read/write Initialize during smu_early_init Signed-off-by: Pratik Vishwakarma Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index c3f22844ba2f1..d58b0bc2bf782 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -52,6 +52,12 @@ #define mmMP1_SMN_C2PMSG_32 0x0060 #define mmMP1_SMN_C2PMSG_32_BASE_IDX 1 +#define mmMP1_SMN_C2PMSG_33 0x0061 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_34 0x0062 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 1 + /* MALLPowerController message arguments (Defines for the Cache mode control) */ #define SMU_MALL_PMFW_CONTROL 0 #define SMU_MALL_DRIVER_CONTROL 1 @@ -1347,7 +1353,9 @@ static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu) ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30); ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31); ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32); - ctl->config.num_arg_regs = 1; + ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_33); + ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_34); + ctl->config.num_arg_regs = 3; ctl->ops = &smu_msg_v1_ops; ctl->default_timeout = adev->usec_timeout * 20; ctl->message_map = smu_v15_0_0_message_map; From 8aa861edce2d4b58dc3bc10ed8ed9b7dd4da3685 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Thu, 8 Jan 2026 09:01:02 +0000 Subject: [PATCH 0157/2070] drm/amdgpu: Add support for update_table for SMU15 Add update_table for SMU 15_0_0 Signed-off-by: Pratik Vishwakarma Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 5 ++ .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 58 +++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index 14e8d8c7a80a8..af87c31ca9a49 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -241,5 +241,10 @@ int smu_v15_0_enable_thermal_alert(struct smu_context *smu); int smu_v15_0_disable_thermal_alert(struct smu_context *smu); +int smu_v15_0_0_update_table(struct smu_context *smu, + enum smu_table_id table_index, + int argument, void *table_data, + bool drv2smu); + #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index a2854d528bab5..d7a4d5d6cc8da 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -1726,6 +1726,64 @@ int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu) return ret; } +int smu_v15_0_0_update_table(struct smu_context *smu, + enum smu_table_id table_index, + int argument, + void *table_data, + bool drv2smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct amdgpu_device *adev = smu->adev; + struct smu_table *table = &smu_table->driver_table; + int table_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_TABLE, + table_index); + uint64_t address; + uint32_t table_size; + int ret; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) + return -EINVAL; + + table_size = smu_table->tables[table_index].size; + + if (drv2smu) { + memcpy(table->cpu_addr, table_data, table_size); + /* + * Flush hdp cache: to guard the content seen by + * GPU is consitent with CPU. + */ + amdgpu_hdp_flush(adev, NULL); + } + + address = table->mc_address; + + struct smu_msg_args args = { + .msg = drv2smu ? + SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + .num_args = 3, + .num_out_args = 0, + }; + + args.args[0] = table_id; + args.args[1] = (uint32_t)lower_32_bits(address); + args.args[2] = (uint32_t)upper_32_bits(address); + + ret = ctl->ops->send_msg(ctl, &args); + + if (ret) + return ret; + + if (!drv2smu) { + amdgpu_hdp_invalidate(adev, NULL); + memcpy(table_data, table->cpu_addr, table_size); + } + + return 0; +} + int smu_v15_0_set_default_dpm_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; From a863e5bb6be239041e2bc20d9adc880df0ad1702 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Thu, 8 Jan 2026 09:05:30 +0000 Subject: [PATCH 0158/2070] drm/admgpu: Update metrics_table for SMU15 Use multi param based get op for metrics_table Signed-off-by: Pratik Vishwakarma Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index d58b0bc2bf782..b42d56f7e6212 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -246,6 +246,36 @@ static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en) return ret; } +static int smu_v15_0_0_get_metrics_table(struct smu_context *smu, + void *metrics_table, + bool bypass_cache) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = + smu_table->tables[SMU_TABLE_SMU_METRICS].size; + int ret; + + if (bypass_cache || + !smu_table->metrics_time || + time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) { + ret = smu_v15_0_0_update_table(smu, + SMU_TABLE_SMU_METRICS, + 0, + smu_table->metrics_table, + false); + if (ret) { + dev_info(smu->adev->dev, "Failed to export SMU15_0_0 metrics table!\n"); + return ret; + } + smu_table->metrics_time = jiffies; + } + + if (metrics_table) + memcpy(metrics_table, smu_table->metrics_table, table_size); + + return 0; +} + static int smu_v15_0_0_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) @@ -255,7 +285,7 @@ static int smu_v15_0_0_get_smu_metrics_data(struct smu_context *smu, SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; int ret = 0; - ret = smu_cmn_get_metrics_table(smu, NULL, false); + ret = smu_v15_0_0_get_metrics_table(smu, NULL, false); if (ret) return ret; @@ -530,7 +560,7 @@ static ssize_t smu_v15_0_0_get_gpu_metrics(struct smu_context *smu, SmuMetrics_t metrics; int ret = 0; - ret = smu_cmn_get_metrics_table(smu, &metrics, true); + ret = smu_v15_0_0_get_metrics_table(smu, &metrics, false); if (ret) return ret; From 8b3e019587f47264d69418b25ca625dbc640502d Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Thu, 8 Jan 2026 08:46:53 +0000 Subject: [PATCH 0159/2070] drm/amdgpu: Fix set_default_dpm_tables Use smu_v15_0_0_update_table instead of common api Signed-off-by: Pratik Vishwakarma Acked-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index d7a4d5d6cc8da..37fe4c1bdbd9c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -1788,7 +1788,7 @@ int smu_v15_0_set_default_dpm_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; - return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, + return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); } From bfd6852e78b77bf4388da972f1a1463f1afe7ccc Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Thu, 8 Jan 2026 08:49:06 +0000 Subject: [PATCH 0160/2070] drm/amdgpu: Fix is_dpm_running Use multi args for get_enabled_mask to fix is_dpm_running Signed-off-by: Pratik Vishwakarma Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index b42d56f7e6212..c1ce603fcdd1e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -479,12 +479,36 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu, return ret; } +static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu, + struct smu_feature_bits *feature_mask) +{ + int ret; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + if (!feature_mask) + return -EINVAL; + + struct smu_msg_args args = { + .msg = SMU_MSG_GetEnabledSmuFeatures, + .num_args = 0, + .num_out_args = 2, + }; + + ret = ctl->ops->send_msg(ctl, &args); + + if (!ret) + smu_feature_bits_from_arr32(feature_mask, args.out_args, + SMU_FEATURE_NUM_DEFAULT); + + return ret; +} + static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; struct smu_feature_bits feature_enabled; - ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); + ret = smu_v15_0_0_get_enabled_mask(smu, &feature_enabled); if (ret) return false; @@ -1356,7 +1380,7 @@ static const struct pptable_funcs smu_v15_0_0_ppt_funcs = { .is_dpm_running = smu_v15_0_0_is_dpm_running, .set_watermarks_table = smu_v15_0_0_set_watermarks_table, .get_gpu_metrics = smu_v15_0_0_get_gpu_metrics, - .get_enabled_mask = smu_cmn_get_enabled_mask, + .get_enabled_mask = smu_v15_0_0_get_enabled_mask, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .set_driver_table_location = smu_v15_0_set_driver_table_location, .gfx_off_control = smu_v15_0_gfx_off_control, From dbf78b37223b48bf18f372a4b135c14a11be7392 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Fri, 9 Jan 2026 12:15:47 +0000 Subject: [PATCH 0161/2070] drm/amdgpu: Drop unsupported function drop set_driver_table_location Signed-off-by: Pratik Vishwakarma Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index c1ce603fcdd1e..5260de5344ae7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -1382,7 +1382,6 @@ static const struct pptable_funcs smu_v15_0_0_ppt_funcs = { .get_gpu_metrics = smu_v15_0_0_get_gpu_metrics, .get_enabled_mask = smu_v15_0_0_get_enabled_mask, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, - .set_driver_table_location = smu_v15_0_set_driver_table_location, .gfx_off_control = smu_v15_0_gfx_off_control, .mode2_reset = smu_v15_0_0_mode2_reset, .get_dpm_ultimate_freq = smu_v15_0_common_get_dpm_ultimate_freq, From d370108aad028664e5617c8635c2cd8b1461180d Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Tue, 10 Feb 2026 15:46:38 -0500 Subject: [PATCH 0162/2070] Revert "drm/amdgpu: add psp interfaces for peak tops limiter driver" This reverts commit 5e3ca897602f6cfa4e8ba799146d0fdfeadc6acd. Reason for revert: Not for upstream yet. Change-Id: Ia8644a6a590091ac8e18c6848375d5aacec6b1a1 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 111 ------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 - drivers/gpu/drm/amd/include/amdgpu_ptl.h | 50 -------- .../gpu/drm/amd/include/kgd_kfd_interface.h | 1 - 7 files changed, 1 insertion(+), 168 deletions(-) delete mode 100644 drivers/gpu/drm/amd/include/amdgpu_ptl.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 4fee011c2e261..cdbab7f8cee8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -38,8 +38,6 @@ #include "amdgpu_vm.h" #include "amdgpu_xcp.h" #include "kfd_topology.h" -#include "amdgpu_ptl.h" - extern uint64_t amdgpu_amdkfd_total_mem_size; enum TLB_FLUSH_TYPE { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 32e5787f04e07..6756d5faabd94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4435,7 +4435,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); - mutex_init(&adev->psp.ptl.mutex); mutex_init(&adev->notifier_lock); mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 3d0d71bfe73dd..b0540b009e84a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -679,8 +679,6 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "SPATIAL_PARTITION"; case GFX_CMD_ID_FB_NPS_MODE: return "NPS_MODE_CHANGE"; - case GFX_CMD_ID_PERF_HW: - return "PERF MONITORING HW"; default: return "UNKNOWN CMD"; } @@ -1199,115 +1197,6 @@ int psp_memory_partition(struct psp_context *psp, int mode) return ret; } -static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, - uint32_t *ptl_fmt) -{ - struct amdgpu_device *adev = psp->adev; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) - return -EINVAL; - - switch (fmt) { - case AMDGPU_PTL_FMT_I8: - *ptl_fmt = GFX_FTYPE_I8; - break; - case AMDGPU_PTL_FMT_F16: - *ptl_fmt = GFX_FTYPE_F16; - break; - case AMDGPU_PTL_FMT_BF16: - *ptl_fmt = GFX_FTYPE_BF16; - break; - case AMDGPU_PTL_FMT_F32: - *ptl_fmt = GFX_FTYPE_F32; - break; - case AMDGPU_PTL_FMT_F64: - *ptl_fmt = GFX_FTYPE_F64; - break; - default: - return -EINVAL; - } - - return 0; -} - -static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, - uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) -{ - struct psp_gfx_cmd_resp *cmd; - struct amdgpu_ptl *ptl = &psp->ptl; - int ret; - - cmd = acquire_psp_cmd_buf(psp); - - cmd->cmd_id = GFX_CMD_ID_PERF_HW; - cmd->cmd.cmd_req_perf_hw.req = req_code; - cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; - cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; - cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; - - ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); - if (ret) - goto out; - - /* Parse response */ - switch (req_code) { - case PSP_PTL_PERF_MON_QUERY: - *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; - *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; - *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; - break; - case PSP_PTL_PERF_MON_SET: - /* Update cached state only on success */ - ptl->enabled = *ptl_state; - ptl->fmt1 = *fmt1; - ptl->fmt2 = *fmt2; - break; - } - -out: - release_psp_cmd_buf(psp); - return ret; -} - -int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, - uint32_t *ptl_state, - enum amdgpu_ptl_fmt *fmt1, - enum amdgpu_ptl_fmt *fmt2) -{ - uint32_t ptl_fmt1, ptl_fmt2; - struct psp_context *psp; - struct amdgpu_ptl *ptl; - - if (!adev || !ptl_state || !fmt1 || !fmt2) - return -EINVAL; - - if (amdgpu_sriov_vf(adev)) - return 0; - - psp = &adev->psp; - ptl = &psp->ptl; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || - psp->sos.fw_version < 0x0036081a) - return -EOPNOTSUPP; - - /* Verify formats */ - if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || - psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) - return -EINVAL; - - /* - * Add check to skip if state and formats are identical to current ones - */ - if (req_code == PSP_PTL_PERF_MON_SET && - ptl->enabled == *ptl_state && - ptl->fmt1 == ptl_fmt1 && - ptl->fmt2 == ptl_fmt2) - return 0; - - return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); -} - int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 332633f6f4be9..58f691db2e97f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -31,7 +31,6 @@ #include "ta_ras_if.h" #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" -#include "amdgpu_ptl.h" #define PSP_FENCE_BUFFER_SIZE 0x1000 #define PSP_CMD_BUFFER_SIZE 0x1000 @@ -471,7 +470,6 @@ struct psp_context { #if defined(CONFIG_DEBUG_FS) struct spirom_bo *spirom_dump_trip; #endif - struct amdgpu_ptl ptl; }; struct amdgpu_psp_funcs { @@ -655,4 +653,5 @@ void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type); + #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9c37e82485409..dbb111a33678a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -44,7 +44,6 @@ #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" #include "kfd_debug.h" -#include "amdgpu_ptl.h" static long kfd_ioctl(struct file *, unsigned int, unsigned long); static int kfd_open(struct inode *, struct file *); diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h deleted file mode 100644 index f309c6571e851..0000000000000 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2026 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __AMDGPU_PTL_H__ -#define __AMDGPU_PTL_H__ - -enum amdgpu_ptl_fmt { - AMDGPU_PTL_FMT_I8 = 0, - AMDGPU_PTL_FMT_F16 = 1, - AMDGPU_PTL_FMT_BF16 = 2, - AMDGPU_PTL_FMT_F32 = 3, - AMDGPU_PTL_FMT_F64 = 4, - AMDGPU_PTL_FMT_F8 = 5, - AMDGPU_PTL_FMT_VECTOR = 6, - AMDGPU_PTL_FMT_INVALID = 7, -}; - -struct amdgpu_ptl { - enum amdgpu_ptl_fmt fmt1; - enum amdgpu_ptl_fmt fmt2; - bool enabled; - bool hw_supported; - /* Protects PTL state and format updates */ - struct mutex mutex; -}; - -int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, - uint32_t *ptl_state, - enum amdgpu_ptl_fmt *fmt1, - enum amdgpu_ptl_fmt *fmt2); -#endif /* __AMDGPU_PTL_H__ */ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 6df5afb242aef..9aba8596faa7e 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -33,7 +33,6 @@ #include #include "amdgpu_irq.h" #include "amdgpu_gfx.h" -#include "amdgpu_ptl.h" struct pci_dev; struct amdgpu_device; From b52d042822a14dff2918bafb6494d08a39260a5a Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Tue, 10 Feb 2026 15:48:19 -0500 Subject: [PATCH 0163/2070] Revert "drm/amdgpu: add new performance monitor PSP interfaces" This reverts commit c26586038fe01ba6f47ae9ef1892f55aeabaac7e. Reason for revert: not ready for upstream yet. Change-Id: I68ab2ebe8ea10d861faa54b435b1da08d4f5df32 --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 21 --------------------- drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 17 ----------------- 2 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 58f691db2e97f..79a49cba8d406 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -359,27 +359,6 @@ struct spirom_bo { }; #endif -enum psp_ptl_cmd { - PSP_PTL_PERF_MON_QUERY = 0xA0000000, - PSP_PTL_PERF_MON_SET = 0xA0000001, -}; - -enum psp_ptl_format_type { - GFX_FTYPE_I8 = 0x00000000, - GFX_FTYPE_F16 = 0x00000001, - GFX_FTYPE_BF16 = 0x00000002, - GFX_FTYPE_F32 = 0x00000003, - GFX_FTYPE_F64 = 0x00000004, - GFX_FTYPE_INVALID = 0xFFFFFFFF, -}; - -struct psp_ptl_perf_req { - enum psp_ptl_cmd req; - uint32_t ptl_state; - uint32_t pref_format1; - uint32_t pref_format2; -}; - struct psp_context { struct amdgpu_device *adev; struct psp_ring km_ring; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index ac34bac3c8391..e8f768638fd59 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -107,7 +107,6 @@ enum psp_gfx_cmd_id GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ /* Dynamic memory partitioninig (NPS mode change)*/ GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ - GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */ GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr */ GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation extended addr */ }; @@ -374,13 +373,6 @@ struct psp_gfx_cmd_fb_memory_part { uint32_t resvd; }; -struct psp_gfx_cmd_req_perf_hw { - uint32_t req; - uint32_t ptl_state; - uint32_t pref_format1; - uint32_t pref_format2; -}; - /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -397,7 +389,6 @@ union psp_gfx_commands struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; struct psp_gfx_cmd_fb_memory_part cmd_memory_part; - struct psp_gfx_cmd_req_perf_hw cmd_req_perf_hw; }; struct psp_gfx_uresp_reserved @@ -424,20 +415,12 @@ struct psp_gfx_uresp_fw_reserve_info { uint32_t reserve_size; }; -struct psp_gfx_uresp_perf_hw { - uint32_t resp; - uint32_t ptl_state; - uint32_t pref_format1; - uint32_t pref_format2; -}; - /* Union of command-specific responses for GPCOM ring. */ union psp_gfx_uresp { struct psp_gfx_uresp_reserved reserved; struct psp_gfx_uresp_bootcfg boot_cfg; struct psp_gfx_uresp_fwar_db_info fwar_db_info; struct psp_gfx_uresp_fw_reserve_info fw_reserve_info; - struct psp_gfx_uresp_perf_hw perf_hw_info; }; /* Structure of GFX Response buffer. From 1f99cac61a56a87aa0e5156f679940496ee3d57c Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Tue, 10 Feb 2026 15:49:00 -0500 Subject: [PATCH 0164/2070] Revert "Add kfd_ioctl_profiler to contain profiler kernel driver changes" This reverts commit 7a9d05ef009826025e3264add42781f037a791ad. Reason for revert: not ready for upstream yet Change-Id: Iaa3d60e2001f3d01c690638eed9387f229f3bbea --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 82 ------------------- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 - .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 ------ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 - .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 +--- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 14 +--- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 8 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 15 +--- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 11 --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 -- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 --- include/uapi/linux/kfd_ioctl.h | 29 ------- 12 files changed, 8 insertions(+), 216 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index dbb111a33678a..732ad1224a619 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,7 +21,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include #include #include #include @@ -3205,84 +3204,6 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v return 0; } -static inline uint32_t profile_lock_device(struct kfd_process *p, - uint32_t gpu_id, uint32_t op) -{ - struct kfd_process_device *pdd; - struct kfd_dev *kfd; - int status = -EINVAL; - - if (!p) - return -EINVAL; - - mutex_lock(&p->mutex); - pdd = kfd_process_device_data_by_id(p, gpu_id); - mutex_unlock(&p->mutex); - - if (!pdd || !pdd->dev || !pdd->dev->kfd) - return -EINVAL; - - kfd = pdd->dev->kfd; - - mutex_lock(&kfd->profiler_lock); - if (op == 1) { - if (!kfd->profiler_process) { - kfd->profiler_process = p; - status = 0; - } else if (kfd->profiler_process == p) { - status = -EALREADY; - } else { - status = -EBUSY; - } - } else if (op == 0 && kfd->profiler_process == p) { - kfd->profiler_process = NULL; - status = 0; - } - mutex_unlock(&kfd->profiler_lock); - - return status; -} - -static inline int kfd_profiler_pmc(struct kfd_process *p, - struct kfd_ioctl_pmc_settings *args) -{ - struct kfd_process_device *pdd; - struct device_queue_manager *dqm; - int status; - - /* Check if we have the correct permissions. */ - if (!perfmon_capable()) - return -EPERM; - - /* Lock/Unlock the device based on the parameter given in OP */ - status = profile_lock_device(p, args->gpu_id, args->lock); - if (status != 0) - return status; - - /* Enable/disable perfcount if requested */ - mutex_lock(&p->mutex); - pdd = kfd_process_device_data_by_id(p, args->gpu_id); - dqm = pdd->dev->dqm; - mutex_unlock(&p->mutex); - - dqm->ops.set_perfcount(dqm, args->perfcount_enable); - return status; -} - -static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) -{ - struct kfd_ioctl_profiler_args *args = data; - - switch (args->op) { - case KFD_IOC_PROFILER_VERSION: - args->version = KFD_IOC_PROFILER_VERSION_NUM; - return 0; - case KFD_IOC_PROFILER_PMC: - return kfd_profiler_pmc(p, &args->pmc); - } - return -EINVAL; -} - #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3404,9 +3325,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, kfd_ioctl_create_process, 0), - - AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, - kfd_ioctl_profiler, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index f231e46e85287..9a66ee661e57c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -936,9 +936,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); - kfd->profiler_process = NULL; - mutex_init(&kfd->profiler_lock); - kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -974,7 +971,6 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); - mutex_destroy(&kfd->profiler_lock); } kfree(kfd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 4170a283db5ba..804851632c4c8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -305,29 +305,6 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } -static void set_perfcount(struct device_queue_manager *dqm, int enable) -{ - struct device_process_node *cur; - struct qcm_process_device *qpd; - struct queue *q; - struct mqd_update_info minfo = { 0 }; - - if (!dqm) - return; - - minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : - UPDATE_FLAG_PERFCOUNT_DISABLE); - dqm_lock(dqm); - list_for_each_entry(cur, &dqm->queues, list) { - qpd = cur->qpd; - list_for_each_entry(q, &qpd->queues_list, list) { - pqm_update_mqd(qpd->pqm, q->properties.queue_id, - &minfo); - } - } - dqm_unlock(dqm); -} - static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -2990,7 +2967,6 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; - dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -3011,7 +2987,6 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; - dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 74a3bcec3e4e5..ef07e44916f80 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -200,8 +200,6 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); - void (*set_perfcount)(struct device_queue_manager *dqm, - int enable); }; struct device_queue_manager_asic_ops { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 993d60a24d50a..97055f808d4a1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -124,9 +124,10 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) + if (q->format == KFD_QUEUE_FORMAT_AQL) { m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; + } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -141,12 +142,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } - mutex_lock(&mm->dev->kfd->profiler_lock); - if (mm->dev->kfd->profiler_process != NULL) - m->compute_perfcount_enable = 1; - - mutex_unlock(&mm->dev->kfd->profiler_lock); - *mqd = m; if (gart_addr) *gart_addr = addr; @@ -226,13 +221,6 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; - if (minfo) { - if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) - m->compute_perfcount_enable = 1; - else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) - m->compute_perfcount_enable = 0; - } - update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 4a574bbb5f379..7e5a7ab6d0c01 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -164,9 +164,10 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) + if (q->format == KFD_QUEUE_FORMAT_AQL) { m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; + } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -181,11 +182,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } - mutex_lock(&mm->dev->kfd->profiler_lock); - if (mm->dev->kfd->profiler_process != NULL) - m->compute_perfcount_enable = 1; - mutex_unlock(&mm->dev->kfd->profiler_lock); - *mqd = m; if (gart_addr) *gart_addr = addr; @@ -263,12 +259,6 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; - if (minfo) { - if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) - m->compute_perfcount_enable = 1; - else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) - m->compute_perfcount_enable = 0; - } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index 7173f6470e5e8..a51f217329db0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -139,9 +139,10 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) + if (q->format == KFD_QUEUE_FORMAT_AQL) { m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; + } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -156,11 +157,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } - mutex_lock(&mm->dev->kfd->profiler_lock); - if (mm->dev->kfd->profiler_process != NULL) - m->compute_perfcount_enable = 1; - mutex_unlock(&mm->dev->kfd->profiler_lock); - *mqd = m; if (gart_addr) *gart_addr = addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index d4659a438be56..dcf4bbfa641b5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -218,9 +218,10 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) + if (q->tba_addr) { m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); + } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -235,11 +236,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } - mutex_lock(&mm->dev->kfd->profiler_lock); - if (mm->dev->kfd->profiler_process != NULL) - m->compute_perfcount_enable = 1; - mutex_unlock(&mm->dev->kfd->profiler_lock); - *mqd = m; if (gart_addr) *gart_addr = addr; @@ -322,13 +318,6 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; - if (minfo) { - if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) - m->compute_perfcount_enable = 1; - else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) - m->compute_perfcount_enable = 0; - } - if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index e8967f5e38920..09483f0862d41 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -149,11 +149,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } - mutex_lock(&mm->dev->kfd->profiler_lock); - if (mm->dev->kfd->profiler_process != NULL) - m->compute_perfcount_enable = 1; - mutex_unlock(&mm->dev->kfd->profiler_lock); - *mqd = m; if (gart_addr) *gart_addr = addr; @@ -236,12 +231,6 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; - if (minfo) { - if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) - m->compute_perfcount_enable = 1; - else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) - m->compute_perfcount_enable = 0; - } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 8983065645fa9..9849b54f54ba0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -384,11 +384,6 @@ struct kfd_dev { int kfd_dev_lock; atomic_t kfd_processes_count; - - /* Lock for profiler process */ - struct mutex profiler_lock; - /* Process currently holding the lock */ - struct kfd_process *profiler_process; }; enum kfd_mempool { @@ -561,8 +556,6 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ - UPDATE_FLAG_PERFCOUNT_ENABLE = 5, - UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 214be98226571..ba25d83c23e78 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1110,16 +1110,6 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } -static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) -{ - mutex_lock(&pdd->dev->kfd->profiler_lock); - if (pdd->dev->kfd->profiler_process == p) { - pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); - pdd->dev->kfd->profiler_process = NULL; - } - mutex_unlock(&pdd->dev->kfd->profiler_lock); -} - static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1131,7 +1121,6 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); - kfd_process_profiler_release(p, pdd); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index a8b2a18d07cf1..e72359370857c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1558,29 +1558,6 @@ struct kfd_ioctl_dbg_trap_args { }; }; -#define KFD_IOC_PROFILER_VERSION_NUM 1 -enum kfd_profiler_ops { - KFD_IOC_PROFILER_PMC = 0, - KFD_IOC_PROFILER_VERSION = 2, -}; - -/** - * Enables/Disables GPU Specific profiler settings - */ -struct kfd_ioctl_pmc_settings { - __u32 gpu_id; /* This is the user_gpu_id */ - __u32 lock; /* Lock GPU for Profiling */ - __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ -}; - -struct kfd_ioctl_profiler_args { - __u32 op; /* kfd_profiler_op */ - union { - struct kfd_ioctl_pmc_settings pmc; - __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ - }; -}; - #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1707,10 +1684,4 @@ struct kfd_ioctl_profiler_args { #define AMDKFD_COMMAND_START 0x01 #define AMDKFD_COMMAND_END 0x28 -#define AMDKFD_IOC_PROFILER \ - AMDKFD_IOWR(0x86, struct kfd_ioctl_profiler_args) - -#define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x87 - #endif From 3b4582cb3eb8673d5735af514275900e8e65eff6 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Wed, 28 Jan 2026 10:03:18 +0000 Subject: [PATCH 0165/2070] drm/amd: Drop MALL Not supported on SMU 15_0_0 Signed-off-by: Pratik Vishwakarma Acked-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index 5260de5344ae7..72a78fc5c827a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -58,19 +58,6 @@ #define mmMP1_SMN_C2PMSG_34 0x0062 #define mmMP1_SMN_C2PMSG_34_BASE_IDX 1 -/* MALLPowerController message arguments (Defines for the Cache mode control) */ -#define SMU_MALL_PMFW_CONTROL 0 -#define SMU_MALL_DRIVER_CONTROL 1 - -/* - * MALLPowerState message arguments - * (Defines for the Allocate/Release Cache mode if in driver mode) - */ -#define SMU_MALL_EXIT_PG 0 -#define SMU_MALL_ENTER_PG 1 - -#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON - #define SMU_15_0_UMD_PSTATE_GFXCLK 700 #define SMU_15_0_UMD_PSTATE_SOCCLK 678 #define SMU_15_0_UMD_PSTATE_FCLK 1800 From 358090a640ddb40053230ef77126091a9b293962 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Wed, 28 Jan 2026 10:10:36 +0000 Subject: [PATCH 0166/2070] drm/amdgpu: enable mode2 reset for SMU IP v15.0.0 Set the default reset method to mode2 for SMU 15.0.0. Signed-off-by: Kanala Ramalingeswara Reddy Signed-off-by: Pratik Vishwakarma Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index d9cc649d81ad4..79d132fc8ca9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -422,6 +422,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev) case IP_VERSION(14, 0, 1): case IP_VERSION(14, 0, 4): case IP_VERSION(14, 0, 5): + case IP_VERSION(15, 0, 0): return AMD_RESET_METHOD_MODE2; default: if (amdgpu_dpm_is_baco_supported(adev)) From b64ee282da6ea46c32564af9acc893680936f906 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Wed, 28 Jan 2026 10:12:44 +0000 Subject: [PATCH 0167/2070] drm/amd: Add CG/PG flags for GC 11.5.4 Enable GFXOff for GC 11.5.4 Signed-off-by: Pratik Vishwakarma Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 79d132fc8ca9c..8122a5cacf07a 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -839,9 +839,28 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) break; case IP_VERSION(11, 5, 4): adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | - AMD_CG_SUPPORT_JPEG_MGCG; + AMD_CG_SUPPORT_JPEG_MGCG | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_FGCG | + AMD_CG_SUPPORT_REPEATER_FGCG | + AMD_CG_SUPPORT_GFX_PERF_CLK | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_HDP_DS | + AMD_CG_SUPPORT_HDP_SD | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_IH_CG | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS; adev->pg_flags = AMD_PG_SUPPORT_VCN | - AMD_PG_SUPPORT_JPEG; + AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_GFX_PG; adev->external_rev_id = adev->rev_id + 0x1; break; default: From 48308a813c4ccc85dedb043506185aec0b2c14a5 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Wed, 4 Feb 2026 02:30:42 +0000 Subject: [PATCH 0168/2070] drm/amd/smu: Fix User mode stable P-states SMU15 SMU 15_0_0 exports only soft limits for CLKs Use correct messages Signed-off-by: Pratik Vishwakarma Acked-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index 72a78fc5c827a..4dc8f0095713c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -1026,26 +1026,21 @@ static int smu_v15_0_0_set_soft_freq_limited_range(struct smu_context *smu, switch (clk_type) { case SMU_GFXCLK: case SMU_SCLK: - msg_set_min = SMU_MSG_SetHardMinGfxClk; + msg_set_min = SMU_MSG_SetSoftMinGfxclk; msg_set_max = SMU_MSG_SetSoftMaxGfxClk; break; case SMU_FCLK: - msg_set_min = SMU_MSG_SetHardMinFclkByFreq; + msg_set_min = SMU_MSG_SetSoftMinFclk; msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; break; case SMU_SOCCLK: - msg_set_min = SMU_MSG_SetHardMinSocclkByFreq; + msg_set_min = SMU_MSG_SetSoftMinSocclkByFreq; msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; break; case SMU_VCLK: case SMU_DCLK: - msg_set_min = SMU_MSG_SetHardMinVcn0; - msg_set_max = SMU_MSG_SetSoftMaxVcn0; - break; - case SMU_VCLK1: - case SMU_DCLK1: - msg_set_min = SMU_MSG_SetHardMinVcn1; - msg_set_max = SMU_MSG_SetSoftMaxVcn1; + msg_set_min = SMU_MSG_SetSoftMinVcn; + msg_set_max = SMU_MSG_SetSoftMaxVcn; break; default: return -EINVAL; From 78b53137e718de9639b8a52f051c4486aaf8c2c4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 23 Jan 2026 09:27:23 -0500 Subject: [PATCH 0169/2070] drm/amdgpu: reorder IB schedule sequence This reorders the IB schedule sequence to cleanly separate the vm operation from the IB submission. This makes the two independent so we can cleanly associate each one with its respective fence. v2: fixes for VCN Acked-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 22 +++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +++++++++++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index bfa64cd7a62d4..031a7d77daa7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -215,16 +215,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, dma_fence_put(tmp); } - if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) - ring->funcs->emit_mem_sync(ring); - - if (ring->funcs->emit_wave_limit && - ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) - ring->funcs->emit_wave_limit(ring, true); - - if (ring->funcs->insert_start) - ring->funcs->insert_start(ring); - if (job) { r = amdgpu_vm_flush(ring, job, need_pipe_sync); if (r) { @@ -235,6 +225,16 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_ib_begin(ring); + if (ring->funcs->insert_start) + ring->funcs->insert_start(ring); + + if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) + ring->funcs->emit_mem_sync(ring); + + if (ring->funcs->emit_wave_limit && + ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) + ring->funcs->emit_wave_limit(ring, true); + if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, init_shadow, vmid); @@ -323,6 +323,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) ring->funcs->emit_wave_limit(ring, false); + amdgpu_ring_ib_end(ring); /* Save the wptr associated with this fence. * This must be last for resets to work properly * as we need to save the wptr associated with this @@ -331,7 +332,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, */ amdgpu_fence_save_wptr(af); - amdgpu_ring_ib_end(ring); amdgpu_ring_commit(ring); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 807f8bcc7de52..dfad7d11826c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -815,6 +815,17 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, return 0; amdgpu_ring_ib_begin(ring); + + /* There is no matching insert_end for this on purpose for the vm flush. + * The IB portion of the submission has both. Having multiple + * insert_start sequences is ok, but you can only have one insert_end + * per submission based on the way VCN FW works. For JPEG + * you can as many insert_start and insert_end sequences as you like as + * long as the rest of the packets come between start and end sequences. + */ + if (ring->funcs->insert_start) + ring->funcs->insert_start(ring); + if (ring->funcs->init_cond_exec) patch = amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); From 6c6b4b50f3ffd5d92191f9c4ccc7738f4d8aa404 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Tue, 10 Feb 2026 15:32:01 +0800 Subject: [PATCH 0170/2070] drm/amdgpu: Adjust usleep_range in fence wait Tune the sleep interval in the PSP fence wait loop from 10-100us to 60-100us.This adjustment results in an overall wait window of 1.2s (60us * 20000 iterations) to 2 seconds (100us * 20000 iterations), which guarantees that we can retrieve the correct fence value Signed-off-by: Ce Sun Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index b0540b009e84a..5eeea965032ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -735,7 +735,7 @@ psp_cmd_submit_buf(struct psp_context *psp, ras_intr = amdgpu_ras_intr_triggered(); if (ras_intr) break; - usleep_range(10, 100); + usleep_range(60, 100); amdgpu_device_invalidate_hdp(psp->adev, NULL); } From bfd98467630e44117f52cf6082e23a6e1f161a23 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 9 Feb 2026 17:32:00 +0800 Subject: [PATCH 0171/2070] drm/amdgpu: return when ras table checksum is error end the function flow when ras table checksum is error Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 2c5d7f87e593e..6fba9d5b29ea6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1701,10 +1701,12 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) } res = __verify_ras_table_checksum(control); - if (res) + if (res) { dev_err(adev->dev, "RAS table incorrect checksum or error:%d\n", res); + return -EINVAL; + } /* Warn if we are at 90% of the threshold or above */ From f0b16753ba927efb38e5ec8cdc1743c0470f382a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 6 Feb 2026 19:13:23 +0530 Subject: [PATCH 0172/2070] drm/amdgpu: Move xgmi status to interface header These definitions are used by user APIs. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 ++---- drivers/gpu/drm/amd/include/kgd_pp_interface.h | 5 +++++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 9e32f343097ec..0ca6fa40a87c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -42,8 +42,6 @@ #define XGMI_STATE_DISABLE 0xD1 #define XGMI_STATE_LS0 0x81 -#define XGMI_LINK_ACTIVE 1 -#define XGMI_LINK_INACTIVE 0 static DEFINE_MUTEX(xgmi_mutex); @@ -365,9 +363,9 @@ int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num) return -ENOLINK; if ((xgmi_state_reg_val & 0xFF) == XGMI_STATE_LS0) - return XGMI_LINK_ACTIVE; + return AMDGPU_XGMI_LINK_ACTIVE; - return XGMI_LINK_INACTIVE; + return AMDGPU_XGMI_LINK_INACTIVE; } /** diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 9fd78fcff15c3..6683ffd6aa681 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -1829,4 +1829,9 @@ struct amdgpu_partition_metrics_v1_1 { struct gpu_metrics_attr metrics_attrs[]; }; +enum amdgpu_xgmi_link_status { + AMDGPU_XGMI_LINK_INACTIVE = 0, + AMDGPU_XGMI_LINK_ACTIVE = 1, +}; + #endif From d56a3cd05c0fafe152af76a7027d3a3f0fb892f8 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 9 Feb 2026 18:54:45 +0100 Subject: [PATCH 0173/2070] drm/amdgpu: fix sync handling in amdgpu_dma_buf_move_notify MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Invalidating a dmabuf will impact other users of the shared BO. In the scenario where process A moves the BO, it needs to inform process B about the move and process B will need to update its page table. The commit fixes a synchronisation bug caused by the use of the ticket: it made amdgpu_vm_handle_moved behave as if updating the page table immediately was correct but in this case it's not. An example is the following scenario, with 2 GPUs and glxgears running on GPU0 and Xorg running on GPU1, on a system where P2P PCI isn't supported: glxgears: export linear buffer from GPU0 and import using GPU1 submit frame rendering to GPU0 submit tiled->linear blit Xorg: copy of linear buffer The sequence of jobs would be: drm_sched_job_run # GPU0, frame rendering drm_sched_job_queue # GPU0, blit drm_sched_job_done # GPU0, frame rendering drm_sched_job_run # GPU0, blit move linear buffer for GPU1 access # amdgpu_dma_buf_move_notify -> update pt # GPU0 It this point the blit job on GPU0 is still running and would likely produce a page fault. Cc: stable@vger.kernel.org Fixes: a448cb003edc ("drm/amdgpu: implement amdgpu_gem_prime_move_notify v2") Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index b9c38a4fe546a..656c267dbe587 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -514,8 +514,15 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) r = dma_resv_reserve_fences(resv, 2); if (!r) r = amdgpu_vm_clear_freed(adev, vm, NULL); + + /* Don't pass 'ticket' to amdgpu_vm_handle_moved: we want the clear=true + * path to be used otherwise we might update the PT of another process + * while it's using the BO. + * With clear=true, amdgpu_vm_bo_update will sync to command submission + * from the same VM. + */ if (!r) - r = amdgpu_vm_handle_moved(adev, vm, ticket); + r = amdgpu_vm_handle_moved(adev, vm, NULL); if (r && r != -EBUSY) DRM_ERROR("Failed to invalidate VM page tables (%d))\n", From 2bedc707daa43ee2444892e0b4fbdfc8bb6acda5 Mon Sep 17 00:00:00 2001 From: Pratik Vishwakarma Date: Wed, 11 Feb 2026 08:35:30 +0000 Subject: [PATCH 0174/2070] drm/amd/swsmu: Move IP specific functions Move SMU v15_0_0 specific functions to IP file - smu_v15_0_0_set_default_dpm_tables and - smu_v15_0_0_update_table Signed-off-by: Pratik Vishwakarma Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 7 -- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 66 ------------------ .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 68 ++++++++++++++++++- 3 files changed, 67 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index af87c31ca9a49..ab4a64f54e797 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -226,8 +226,6 @@ int smu_v15_0_deep_sleep_control(struct smu_context *smu, int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu); -int smu_v15_0_set_default_dpm_tables(struct smu_context *smu); - int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size, @@ -241,10 +239,5 @@ int smu_v15_0_enable_thermal_alert(struct smu_context *smu); int smu_v15_0_disable_thermal_alert(struct smu_context *smu); -int smu_v15_0_0_update_table(struct smu_context *smu, - enum smu_table_id table_index, - int argument, void *table_data, - bool drv2smu); - #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index 37fe4c1bdbd9c..a2f446d38be88 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -1726,72 +1726,6 @@ int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu) return ret; } -int smu_v15_0_0_update_table(struct smu_context *smu, - enum smu_table_id table_index, - int argument, - void *table_data, - bool drv2smu) -{ - struct smu_table_context *smu_table = &smu->smu_table; - struct amdgpu_device *adev = smu->adev; - struct smu_table *table = &smu_table->driver_table; - int table_id = smu_cmn_to_asic_specific_index(smu, - CMN2ASIC_MAPPING_TABLE, - table_index); - uint64_t address; - uint32_t table_size; - int ret; - struct smu_msg_ctl *ctl = &smu->msg_ctl; - - if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) - return -EINVAL; - - table_size = smu_table->tables[table_index].size; - - if (drv2smu) { - memcpy(table->cpu_addr, table_data, table_size); - /* - * Flush hdp cache: to guard the content seen by - * GPU is consitent with CPU. - */ - amdgpu_hdp_flush(adev, NULL); - } - - address = table->mc_address; - - struct smu_msg_args args = { - .msg = drv2smu ? - SMU_MSG_TransferTableDram2Smu : - SMU_MSG_TransferTableSmu2Dram, - .num_args = 3, - .num_out_args = 0, - }; - - args.args[0] = table_id; - args.args[1] = (uint32_t)lower_32_bits(address); - args.args[2] = (uint32_t)upper_32_bits(address); - - ret = ctl->ops->send_msg(ctl, &args); - - if (ret) - return ret; - - if (!drv2smu) { - amdgpu_hdp_invalidate(adev, NULL); - memcpy(table_data, table->cpu_addr, table_size); - } - - return 0; -} - -int smu_v15_0_set_default_dpm_tables(struct smu_context *smu) -{ - struct smu_table_context *smu_table = &smu->smu_table; - - return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, - smu_table->clocks_table, false); -} - int smu_v15_0_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index 4dc8f0095713c..660335d7bda95 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -233,6 +233,72 @@ static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en) return ret; } +static int smu_v15_0_0_update_table(struct smu_context *smu, + enum smu_table_id table_index, + int argument, + void *table_data, + bool drv2smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct amdgpu_device *adev = smu->adev; + struct smu_table *table = &smu_table->driver_table; + int table_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_TABLE, + table_index); + uint64_t address; + uint32_t table_size; + int ret; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) + return -EINVAL; + + table_size = smu_table->tables[table_index].size; + + if (drv2smu) { + memcpy(table->cpu_addr, table_data, table_size); + /* + * Flush hdp cache: to guard the content seen by + * GPU is consitent with CPU. + */ + amdgpu_hdp_flush(adev, NULL); + } + + address = table->mc_address; + + struct smu_msg_args args = { + .msg = drv2smu ? + SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + .num_args = 3, + .num_out_args = 0, + }; + + args.args[0] = table_id; + args.args[1] = (uint32_t)lower_32_bits(address); + args.args[2] = (uint32_t)upper_32_bits(address); + + ret = ctl->ops->send_msg(ctl, &args); + + if (ret) + return ret; + + if (!drv2smu) { + amdgpu_hdp_invalidate(adev, NULL); + memcpy(table_data, table->cpu_addr, table_size); + } + + return 0; +} + +static int smu_v15_0_0_set_default_dpm_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, + smu_table->clocks_table, false); +} + static int smu_v15_0_0_get_metrics_table(struct smu_context *smu, void *metrics_table, bool bypass_cache) @@ -1357,7 +1423,7 @@ static const struct pptable_funcs smu_v15_0_0_ppt_funcs = { .system_features_control = smu_v15_0_0_system_features_control, .dpm_set_vcn_enable = smu_v15_0_set_vcn_enable, .dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable, - .set_default_dpm_table = smu_v15_0_set_default_dpm_tables, + .set_default_dpm_table = smu_v15_0_0_set_default_dpm_tables, .read_sensor = smu_v15_0_0_read_sensor, .is_dpm_running = smu_v15_0_0_is_dpm_running, .set_watermarks_table = smu_v15_0_0_set_watermarks_table, From b8e91ab3ec70a5a2fdc11d59a14d1819d255dbdb Mon Sep 17 00:00:00 2001 From: decce6 Date: Tue, 10 Feb 2026 07:26:00 +0000 Subject: [PATCH 0175/2070] drm/radeon: Add HAINAN clock adjustment This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from 850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This patch is for radeon. Signed-off-by: decce6 Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/si_dpm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 9deb91970d4df..f12227145ef08 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -2925,6 +2925,11 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, max_sclk = 60000; max_mclk = 80000; } + if ((rdev->pdev->device == 0x666f) && + (rdev->pdev->revision == 0x00)) { + max_sclk = 80000; + max_mclk = 95000; + } } else if (rdev->family == CHIP_OLAND) { if ((rdev->pdev->revision == 0xC7) || (rdev->pdev->revision == 0x80) || From 8d372855b9234f18bfaad870921c1bf781d1e52c Mon Sep 17 00:00:00 2001 From: decce6 Date: Tue, 10 Feb 2026 07:24:01 +0000 Subject: [PATCH 0176/2070] drm/amdgpu: Add HAINAN clock adjustment This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from 850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This patch is for amdgpu. Signed-off-by: decce6 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 0f8f69481f5bb..d8959e0f109cf 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3464,6 +3464,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, max_sclk = 60000; max_mclk = 80000; } + if ((adev->pdev->device == 0x666f) && + (adev->pdev->revision == 0x00)) { + max_sclk = 80000; + max_mclk = 95000; + } } else if (adev->asic_type == CHIP_OLAND) { if ((adev->pdev->revision == 0xC7) || (adev->pdev->revision == 0x80) || From 302387850c0116fd00c0b1454adbf1451dbf77be Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 10 Feb 2026 16:53:08 -0500 Subject: [PATCH 0177/2070] drm/amdgpu: set family for GC 11.5.4 Set the family for GC 11.5.4 Fixes: 47ae1f938d12 ("drm/amdgpu: add support for GC IP version 11.5.4") Cc: Tim Huang Cc: Pratik Vishwakarma Cc: Roman Li Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 +++- include/uapi/drm/amdgpu_drm.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 41e63c2869125..4143a25a498bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2988,9 +2988,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): - case IP_VERSION(11, 5, 4): adev->family = AMDGPU_FAMILY_GC_11_5_0; break; + case IP_VERSION(11, 5, 4): + adev->family = AMDGPU_FAMILY_GC_11_5_4; + break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): case IP_VERSION(12, 1, 0): diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 1d34daa0ebcd5..ebbd861ef0bc6 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1667,6 +1667,7 @@ struct drm_amdgpu_info_uq_metadata { #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ +#define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */ #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ #if defined(__cplusplus) From f4bfa6815431bf48969ed08ae0c58355edd84905 Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Tue, 27 Jan 2026 18:00:59 +0800 Subject: [PATCH 0178/2070] drm/amdgpu:Add psp v13_0_15 ip block Add support for psp v13_0_15 ip block Signed-off-by: Mangesh Gadre Reviewed-by: Asad Kamal Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++++- drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 15 +++++++++++---- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 4 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 4143a25a498bf..fc8c1f36be580 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2164,6 +2164,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(13, 0, 11): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): case IP_VERSION(14, 0, 0): case IP_VERSION(14, 0, 1): case IP_VERSION(14, 0, 4): diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 5eeea965032ae..a7c7b378c696c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -148,6 +148,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp) break; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): ret = psp_init_cap_microcode(psp, ucode_prefix); ret &= psp_init_ta_microcode(psp, ucode_prefix); break; @@ -219,6 +220,7 @@ static int psp_early_init(struct amdgpu_ip_block *ip_block) psp->autoload_supported = false; break; case IP_VERSION(13, 0, 12): + case IP_VERSION(13, 0, 15): psp_v13_0_set_psp_funcs(psp); psp->autoload_supported = false; adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); @@ -383,7 +385,8 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) return false; db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index af4a7d7c4abd8..d1e1a43695210 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_15_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_15_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); @@ -121,6 +123,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; @@ -156,7 +159,8 @@ static void psp_v13_0_bootloader_print_status(struct psp_context *psp, if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) { at = 0; for_each_inst(i, adev->aid_mask) { bl_status_reg = @@ -202,7 +206,8 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) retry_cnt = ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))) ? PSP_VMBX_POLLING_LIMIT : 10; /* Wait for bootloader to signify that it is ready having bit 31 of @@ -232,7 +237,8 @@ static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) { ret = psp_v13_0_wait_for_vmbx_ready(psp); if (ret) amdgpu_ras_query_boot_status(adev, 4); @@ -872,7 +878,8 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp) if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) && (!(adev->flags & AMD_IS_APU))) { reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 54b14751fd7a4..4e037a6978f09 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1478,7 +1478,8 @@ static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && - (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) && + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 15))) { /* AMD_CG_SUPPORT_DRM_MGCG */ data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); if (!(data & 0x01000000)) From 0341c3ad6f2ca49c8329f9b6afe897ee611f3a77 Mon Sep 17 00:00:00 2001 From: Siwei He Date: Mon, 9 Feb 2026 16:13:20 -0500 Subject: [PATCH 0179/2070] drm/amdkfd: Fix APU to use GTT, not VRAM for MQD Add a check in mqd_on_vram. If the device prefers GTT, it returns false Fixes: d4a814f400d4 ("drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM") Signed-off-by: Siwei He Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index dcf4bbfa641b5..5578c241b7d0a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -111,6 +111,9 @@ static void set_priority(struct v9_mqd *m, struct queue_properties *q) static bool mqd_on_vram(struct amdgpu_device *adev) { + if (adev->apu_prefer_gtt) + return false; + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 4, 3): case IP_VERSION(9, 5, 0): From 24eef7ae5998d05dc86383d1cc6ccf0eb346681c Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 6 Feb 2026 20:49:23 +0530 Subject: [PATCH 0180/2070] drm/amd/display: Fix out-of-bounds stream encoder index v3 eng_id can be negative and that stream_enc_regs[] can be indexed out of bounds. eng_id is used directly as an index into stream_enc_regs[], which has only 5 entries. When eng_id is 5 (ENGINE_ID_DIGF) or negative, this can access memory past the end of the array. Add a bounds check using ARRAY_SIZE() before using eng_id as an index. The unsigned cast also rejects negative values. This avoids out-of-bounds access. Fixes the below smatch error: dcn*_resource.c: stream_encoder_create() may index stream_enc_regs[eng_id] out of bounds (size 5). drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn351/dcn351_resource.c 1246 static struct stream_encoder *dcn35_stream_encoder_create( 1247 enum engine_id eng_id, 1248 struct dc_context *ctx) 1249 { ... 1255 1256 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1257 if (eng_id <= ENGINE_ID_DIGF) { ENGINE_ID_DIGF is 5. should <= be dc_bios, 1283 eng_id, vpg, afmt, --> 1284 &stream_enc_regs[eng_id], ^^^^^^^^^^^^^^^^^^^^^^^ This stream_enc_regs[] array has 5 elements so we are one element beyond the end of the array. ... 1287 return &enc1->base; 1288 } v2: use explicit bounds check as suggested by Roman/Dan; avoid unsigned int cast v3: The compiler already knows how to compare the two values, so the cast (int) is not needed. (Roman) Fixes: 2728e9c7c842 ("drm/amd/display: add DC changes for DCN351") Reported-by: Dan Carpenter Cc: Harry Wentland Cc: Mario Limonciello Cc: Alex Hung Cc: Aurabindo Pillai Cc: ChiaHsuan Chung Cc: Roman Li Signed-off-by: Srinivasan Shanmugam Reviewed-by: Roman Li Change-Id: I26e866337eb69739c66d29ac4fc9612d243c84ee --- .../drm/amd/display/dc/resource/dcn315/dcn315_resource.c | 8 ++++---- .../drm/amd/display/dc/resource/dcn316/dcn316_resource.c | 8 ++++---- .../drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 8 ++++---- .../drm/amd/display/dc/resource/dcn321/dcn321_resource.c | 8 ++++---- .../drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 8 ++++---- .../drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 8 ++++---- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index a8283f21008ef..3ae787a377b18 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1230,12 +1230,12 @@ static struct stream_encoder *dcn315_stream_encoder_create( /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 4da0e9320159b..4b8668458f038 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -1223,12 +1223,12 @@ static struct stream_encoder *dcn316_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index d3b92c61b7ad1..a55078458ba54 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1211,12 +1211,12 @@ static struct stream_encoder *dcn32_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn32_vpg_create(ctx, vpg_inst); afmt = dcn32_afmt_create(ctx, afmt_inst); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index d08691ea27ea2..188c3f24f110a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1192,12 +1192,12 @@ static struct stream_encoder *dcn321_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn321_vpg_create(ctx, vpg_inst); afmt = dcn321_afmt_create(ctx, afmt_inst); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 945da8cffada4..5ea805fcff482 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1274,12 +1274,12 @@ static struct stream_encoder *dcn35_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index e660889904a99..424b52e2dd7b2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1254,12 +1254,12 @@ static struct stream_encoder *dcn35_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); From 7976fa7d68dfa1716adedae291a47ba5d19b10ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 20 Jan 2026 12:57:21 +0100 Subject: [PATCH 0181/2070] drm/amdgpu: lock both VM and BO in amdgpu_gem_object_open MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VM was not locked in the past since we initially only cleared the linked list element and not added it to any VM state. But this has changed quite some time ago, we just never realized this problem because the VM state lock was masking it. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 19 +++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 22 ++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ 4 files changed, 42 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 00ea69baa126d..6893d175f7c33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -878,6 +878,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo *bo[2] = {NULL, NULL}; struct amdgpu_bo_va *bo_va; bool same_hive = false; + struct drm_exec exec; int i, ret; if (!va) { @@ -958,19 +959,25 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, goto unwind; } - /* Add BO to VM internal data structures */ - ret = amdgpu_bo_reserve(bo[i], false); - if (ret) { - pr_debug("Unable to reserve BO during memory attach"); - goto unwind; + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); + drm_exec_until_all_locked(&exec) { + ret = amdgpu_vm_lock_pd(vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto unwind; + ret = drm_exec_lock_obj(&exec, &bo[i]->tbo.base); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto unwind; } + bo_va = amdgpu_vm_bo_find(vm, bo[i]); if (!bo_va) bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]); else ++bo_va->ref_count; attachment[i]->bo_va = bo_va; - amdgpu_bo_unreserve(bo[i]); + drm_exec_fini(&exec); if (unlikely(!attachment[i]->bo_va)) { ret = -ENOMEM; pr_err("Failed to add BO object to VM. ret == %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5f9fa2140f094..5c90de58cc285 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -232,6 +232,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; struct mm_struct *mm; + struct drm_exec exec; int r; mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); @@ -242,9 +243,18 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, !amdgpu_vm_is_bo_always_valid(vm, abo)) return -EPERM; - r = amdgpu_bo_reserve(abo, false); - if (r) - return r; + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); + drm_exec_until_all_locked(&exec) { + r = drm_exec_prepare_obj(&exec, &abo->tbo.base, 1); + drm_exec_retry_on_contention(&exec); + if (unlikely(r)) + goto out_unlock; + + r = amdgpu_vm_lock_pd(vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (unlikely(r)) + goto out_unlock; + } amdgpu_vm_bo_update_shared(abo); bo_va = amdgpu_vm_bo_find(vm, abo); @@ -260,8 +270,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, amdgpu_bo_unreserve(abo); return r; } - - amdgpu_bo_unreserve(abo); + drm_exec_fini(&exec); /* Validate and add eviction fence to DMABuf imports with dynamic * attachment in compute VMs. Re-validation will be done by @@ -294,7 +303,10 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, } } mutex_unlock(&vm->process_info->lock); + return r; +out_unlock: + drm_exec_fini(&exec); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 1878e0faa722a..f69332eed0512 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1445,6 +1445,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) { struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv; + struct drm_exec exec; int r, pasid; /* Ensure IB tests are run on ring */ @@ -1484,7 +1485,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) if (r) goto error_pasid; + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); + drm_exec_until_all_locked(&exec) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (unlikely(r)) + goto error_vm; + } + fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); + drm_exec_fini(&exec); if (!fpriv->prt_va) { r = -ENOMEM; goto error_vm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index dfad7d11826c1..baa3823629390 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1746,6 +1746,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, { struct amdgpu_bo_va *bo_va; + amdgpu_vm_assert_locked(vm); + bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); if (bo_va == NULL) { return NULL; From b12a0e7f5a0bf8c2e64dfe73b96ac81204549f16 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Mon, 15 Dec 2025 17:14:21 -0500 Subject: [PATCH 0182/2070] drm/amd/display: Add static keyword for sharpness tables [Why & How] Sharpness tables are only accessed in dc_spl_isharp_filters source file. Reviewed-by: Joshua Aberback Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c index 1d9edb89e47a1..a75ab23b0726a 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c @@ -293,7 +293,7 @@ static const uint16_t filter_isharp_bs_3tap_64p_s1_12[99] = { }; /* Pre-generated 1DLUT for given setup and sharpness level */ -struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { +static struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { { 0, 0, { @@ -332,7 +332,7 @@ struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = }, }; -struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = { +static struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = { {1125, 1000, 0}, {11, 10, 1}, {1075, 1000, 2}, From 9b75fa1558b7836c77fd00a61b77c1a4401ebfc3 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 9 Dec 2025 16:20:26 -0500 Subject: [PATCH 0183/2070] drm/amd/display: Refactor fams2 calculations [WHY&HOW] Cleanup calculations based on version to improve for future expansion. Reviewed-by: Austin Zheng Signed-off-by: Dillon Varone Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../amd/display/dc/dml2_0/dml21/dml21_utils.c | 205 +++++++++--------- .../amd/display/dc/dml2_0/dml21/dml21_utils.h | 1 + 2 files changed, 107 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c index f667026cb43eb..732b994b88643 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c @@ -374,128 +374,135 @@ void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *c dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state); } -void dml21_build_fams2_programming(const struct dc *dc, +static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx) { - int i, j, k; + int dc_stream_idx, dc_plane_idx, dc_pipe_idx; unsigned int num_fams2_streams = 0; - /* reset fams2 data */ - memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); - memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); - memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES); - memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)); + for (dc_stream_idx = 0; dc_stream_idx < context->stream_count; dc_stream_idx++) { + int dml_stream_idx; + struct dc_stream_state *phantom_stream; + struct dc_stream_status *phantom_status; + enum fams2_stream_type type = 0; - if ((dml_ctx->v21.mode_programming.programming->fams2_required) || - (dml_ctx->v21.mode_programming.programming->legacy_pstate_info_for_dmu)) { - for (i = 0; i < context->stream_count; i++) { - int dml_stream_idx; - struct dc_stream_state *phantom_stream; - struct dc_stream_status *phantom_status; - enum fams2_stream_type type = 0; + union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams]; + union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams]; - union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams]; - union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams]; + struct dc_stream_state *stream = context->streams[dc_stream_idx]; - struct dc_stream_state *stream = context->streams[i]; + if (context->stream_status[dc_stream_idx].plane_count == 0 || + dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) { + /* can ignore blanked or phantom streams */ + continue; + } - if (context->stream_status[i].plane_count == 0 || - dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) { - /* can ignore blanked or phantom streams */ - continue; - } + dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream->stream_id); + if (dml_stream_idx < 0) { + ASSERT(dml_stream_idx >= 0); + continue; + } - dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream->stream_id); - if (dml_stream_idx < 0) { - ASSERT(dml_stream_idx >= 0); - continue; + /* copy static state from PMO */ + memcpy(static_base_state, + &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, + sizeof(union dmub_cmd_fams2_config)); + + memcpy(static_sub_state, + &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params, + sizeof(union dmub_cmd_fams2_config)); + + switch (dc->debug.fams_version.minor) { + case 1: + default: + type = static_base_state->stream_v1.base.type; + + /* get information from context */ + static_base_state->stream_v1.base.num_planes = context->stream_status[dc_stream_idx].plane_count; + static_base_state->stream_v1.base.otg_inst = context->stream_status[dc_stream_idx].primary_otg_inst; + + /* populate pipe masks for planes */ + for (dc_plane_idx = 0; dc_plane_idx < context->stream_status[dc_stream_idx].plane_count; dc_plane_idx++) { + for (dc_pipe_idx = 0; dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) { + if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream && + context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == stream->stream_id && + context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == context->stream_status[dc_stream_idx].plane_states[dc_plane_idx]) { + static_base_state->stream_v1.base.pipe_mask |= (1 << dc_pipe_idx); + static_base_state->stream_v1.base.plane_pipe_masks[dc_plane_idx] |= (1 << dc_pipe_idx); + } + } } + } - /* copy static state from PMO */ - memcpy(static_base_state, - &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, - sizeof(union dmub_cmd_fams2_config)); - - if (dc->debug.fams_version.major == 3) { - memcpy(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams], - &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params_v2, - sizeof(union dmub_fams2_stream_static_sub_state_v2)); - } else { - memcpy(static_sub_state, - &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params, - sizeof(union dmub_cmd_fams2_config)); - } + + /* get per method programming */ + switch (type) { + case FAMS2_STREAM_TYPE_VBLANK: + case FAMS2_STREAM_TYPE_VACTIVE: + case FAMS2_STREAM_TYPE_DRR: + break; + case FAMS2_STREAM_TYPE_SUBVP: + phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream); + if (!phantom_stream) + break; + + phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream); + + /* phantom status should always be present */ + ASSERT(phantom_status); + if (!phantom_status) + break; switch (dc->debug.fams_version.minor) { case 1: default: - type = static_base_state->stream_v1.base.type; - - /* get information from context */ - static_base_state->stream_v1.base.num_planes = context->stream_status[i].plane_count; - static_base_state->stream_v1.base.otg_inst = context->stream_status[i].primary_otg_inst; - - /* populate pipe masks for planes */ - for (j = 0; j < context->stream_status[i].plane_count; j++) { - for (k = 0; k < dc->res_pool->pipe_count; k++) { - if (context->res_ctx.pipe_ctx[k].stream && - context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id && - context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) { - static_base_state->stream_v1.base.pipe_mask |= (1 << k); - static_base_state->stream_v1.base.plane_pipe_masks[j] |= (1 << k); + static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; + + /* populate pipe masks for phantom planes */ + for (dc_plane_idx = 0; dc_plane_idx < phantom_status->plane_count; dc_plane_idx++) { + for (dc_pipe_idx = 0; dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) { + if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream && + context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == phantom_stream->stream_id && + context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == phantom_status->plane_states[dc_plane_idx]) { + switch (dc->debug.fams_version.minor) { + case 1: + default: + static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << dc_pipe_idx); + static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[dc_plane_idx] |= (1 << dc_pipe_idx); + } } } } } + break; + default: + ASSERT(false); + break; + } + num_fams2_streams++; + } - /* get per method programming */ - switch (type) { - case FAMS2_STREAM_TYPE_VBLANK: - case FAMS2_STREAM_TYPE_VACTIVE: - case FAMS2_STREAM_TYPE_DRR: - break; - case FAMS2_STREAM_TYPE_SUBVP: - phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream); - if (!phantom_stream) - break; - - phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream); - - /* phantom status should always be present */ - ASSERT(phantom_status); - if (!phantom_status) - break; - - switch (dc->debug.fams_version.minor) { - case 1: - default: - static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; - - /* populate pipe masks for phantom planes */ - for (j = 0; j < phantom_status->plane_count; j++) { - for (k = 0; k < dc->res_pool->pipe_count; k++) { - if (context->res_ctx.pipe_ctx[k].stream && - context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id && - context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) { - switch (dc->debug.fams_version.minor) { - case 1: - default: - static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << k); - static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 << k); - } - } - } - } - } - break; - default: - ASSERT(false); - break; - } + return num_fams2_streams; +} + +void dml21_build_fams2_programming(const struct dc *dc, + struct dc_state *context, + struct dml2_context *dml_ctx) +{ + unsigned int num_fams2_streams = 0; + + /* reset fams2 data */ + memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); + memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); + memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES); + memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)); - num_fams2_streams++; + if (dml_ctx->v21.mode_programming.programming->fams2_required || + dml_ctx->v21.mode_programming.programming->legacy_pstate_info_for_dmu) { + if (dc->debug.fams_version.major == 2) { + num_fams2_streams = dml21_build_fams2_stream_programming_v2(dc, context, dml_ctx); } } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h index 4bff52eaaef8d..bff945a4ab3a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h @@ -9,6 +9,7 @@ struct dc_state; struct dc_plane_state; struct pipe_ctx; +struct dc_dmub_srv; struct dml2_context; struct dml2_display_rq_regs; From 61d6efe9ca462068c8d15557ae2076fc1e202d61 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 23 Jan 2026 09:52:40 -0500 Subject: [PATCH 0184/2070] drm/amd/display: Add gpuvm and hvm params to dml21 [Why & How] Add missing params to display configuration for dml21 Reviewed-by: Charlene Liu Signed-off-by: Dmytro Laktyushkin Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../display/dc/dml2_0/dml21/dml21_translation_helper.c | 8 ++++++-- .../dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index 3f4963ce3a002..f4bcebd7ec7fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -737,8 +737,12 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); dml_dispcfg->gpuvm_enable = dml_ctx->config.gpuvm_enable; - dml_dispcfg->gpuvm_max_page_table_levels = 4; - dml_dispcfg->hostvm_enable = false; + if (dml_ctx->v21.dml_init.soc_bb.gpuvm_max_page_table_levels) + dml_dispcfg->gpuvm_max_page_table_levels = dml_ctx->v21.dml_init.soc_bb.gpuvm_max_page_table_levels; + else + dml_dispcfg->gpuvm_max_page_table_levels = 4; + dml_dispcfg->hostvm_enable = dml_ctx->config.hostvm_enable; + dml_dispcfg->hostvm_max_non_cached_page_table_levels = dml_ctx->v21.dml_init.soc_bb.hostvm_max_non_cached_page_table_levels; dml_dispcfg->minimize_det_reallocation = true; dml_dispcfg->overrides.enable_subvp_implicit_pmo = true; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h index c4cce870877a1..ddbb8dfa9ff88 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h @@ -160,6 +160,8 @@ struct dml2_soc_bb { unsigned long return_bus_width_bytes; unsigned long hostvm_min_page_size_kbytes; unsigned long gpuvm_min_page_size_kbytes; + unsigned int hostvm_max_non_cached_page_table_levels; + unsigned int gpuvm_max_page_table_levels; double phy_downspread_percent; double dcn_downspread_percent; double dispclk_dppclk_vco_speed_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h index 9a9c27962f681..5ee489682f2ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h @@ -239,6 +239,7 @@ struct dml2_configuration_options { bool use_clock_dc_limits; bool gpuvm_enable; + bool hostvm_enable; bool force_tdlut_enable; void *bb_from_dmub; }; From 1da6bf361336115c9eb19cd0eb6a464d8618d735 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 28 Jan 2026 11:09:23 -0500 Subject: [PATCH 0185/2070] drm/amd/display: Expose functions of other dcn use [Why & HOw] Expose some functions for later dcns to reuse Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dmytro Laktyushkin Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 15 +++++---------- .../amd/display/dc/hubbub/dcn401/dcn401_hubbub.c | 10 +++++----- .../amd/display/dc/hubbub/dcn401/dcn401_hubbub.h | 10 ++++++++++ .../drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 6 +++--- .../drm/amd/display/dc/optc/dcn35/dcn35_optc.h | 9 +++++++++ 5 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 663a18ee51628..3063b6ab32e5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -595,16 +595,6 @@ void dccg401_set_dp_dto( bool enable = false; - if (params->otg_inst > 3) { - /* dcn401 only has 4 instances */ - BREAK_TO_DEBUGGER(); - return; - } - if (!params->refclk_hz) { - BREAK_TO_DEBUGGER(); - return; - } - if (!dc_is_tmds_signal(params->signal)) { uint64_t dto_integer; uint64_t dto_phase_hz; @@ -612,6 +602,11 @@ void dccg401_set_dp_dto( enable = true; + if (!params->refclk_hz) { + BREAK_TO_DEBUGGER(); + return; + } + /* Set DTO values: * int = target_pix_rate / reference_clock * phase = target_pix_rate - int * reference_clock, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index d11afd1ce72a2..941dce439e979 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -41,7 +41,7 @@ #define FN(reg_name, field_name) \ hubbub2->shifts->field_name, hubbub2->masks->field_name -static void dcn401_init_crb(struct hubbub *hubbub) +void dcn401_init_crb(struct hubbub *hubbub) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1110,7 +1110,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub, return true; } -static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg) +void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1147,7 +1147,7 @@ static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, un } } -static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase) +void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1170,7 +1170,7 @@ static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned comp } } -static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) +void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1192,7 +1192,7 @@ static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) } } -static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower) +bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h index b1d9ea9d1c3d6..f487155444299 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h @@ -194,6 +194,11 @@ bool hubbub401_get_dcc_compression_cap( const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output); +bool dcn401_program_arbiter( + struct hubbub *hubbub, + struct dml2_display_arb_regs *arb_regs, + bool safe_to_lower); + void hubbub401_construct(struct dcn20_hubbub *hubbub2, struct dc_context *ctx, const struct dcn_hubbub_registers *hubbub_regs, @@ -203,4 +208,9 @@ void hubbub401_construct(struct dcn20_hubbub *hubbub2, int pixel_chunk_size_kb, int config_return_buffer_size_kb); +void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); +void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); +void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst); +void dcn401_init_crb(struct hubbub *hubbub); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index 0953acbcc6d45..5aafd0eedf668 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -270,7 +270,7 @@ static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx, return true; } -static bool optc35_configure_crc(struct timing_generator *optc, +bool optc35_configure_crc(struct timing_generator *optc, const struct crc_params *params) { struct optc *optc1 = DCN10TG_FROM_TG(optc); @@ -437,7 +437,7 @@ void optc35_set_drr( REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0); } -static void optc35_set_long_vtotal( +void optc35_set_long_vtotal( struct timing_generator *optc, const struct long_vtotal_params *params) { @@ -524,7 +524,7 @@ static void optc35_set_long_vtotal( } } -static void optc35_wait_otg_disable(struct timing_generator *optc) +void optc35_wait_otg_disable(struct timing_generator *optc) { struct optc *optc1; uint32_t is_master_en; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h index 5c2cb1f277838..82e0818c8f9f4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h @@ -90,4 +90,13 @@ void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable); void optc35_set_drr(struct timing_generator *optc, const struct drr_params *params); +void optc35_set_long_vtotal( + struct timing_generator *optc, + const struct long_vtotal_params *params); + +bool optc35_configure_crc(struct timing_generator *optc, + const struct crc_params *params); + +void optc35_wait_otg_disable(struct timing_generator *optc); + #endif /* __DC_OPTC_DCN35_H__ */ From 842550349ff35b938ea30847218b9c7ed656f97b Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 2 Feb 2026 20:34:42 -0500 Subject: [PATCH 0186/2070] drm/amd/display: Disable SR feature on eDP1 by default [Why & How] Disable SR feature on eDP1 by default. Reviewed-by: Wenjing Liu Signed-off-by: Charlene Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 12 ++++++++++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 ++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 - drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 +- drivers/gpu/drm/amd/display/dc/link/link_detection.c | 2 +- 5 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 1f41d6540b830..bf2a356b34756 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1153,11 +1153,19 @@ void dm_helpers_init_panel_settings( void dm_helpers_override_panel_settings( struct dc_context *ctx, - struct dc_panel_config *panel_config) + struct dc_link *link) { + unsigned int panel_inst = 0; + // Feature DSC if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) - panel_config->dsc.disable_dsc_edp = true; + link->panel_config.dsc.disable_dsc_edp = true; + + if (dc_get_edp_link_panel_inst(ctx->dc, link, &panel_inst) && panel_inst == 1) { + link->panel_config.psr.disable_psr = true; + link->panel_config.psr.disallow_psrsu = true;; + link->panel_config.psr.disallow_replay = true; + } } void *dm_helpers_allocate_gpu_mem( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index fd491b7a3cd70..99d6d6c935610 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -80,12 +80,20 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link) link->psr_settings.psr_feature_enabled = false; } else { + unsigned int panel_inst = 0; + if (link_supports_psrsu(link)) link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; else link->psr_settings.psr_version = DC_PSR_VERSION_1; link->psr_settings.psr_feature_enabled = true; + + /*disable allow psr/psrsu/replay on eDP1*/ + if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) { + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + link->psr_settings.psr_feature_enabled = false; + } } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ce08477d1ccd9..4c4239cac863d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -505,7 +505,6 @@ union allow_lttpr_non_transparent_mode { } bits; unsigned char raw; }; - /* Structure to hold configuration flags set by dm at dc creation. */ struct dc_config { bool gpu_vm_support; diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 7014b8c2c9564..2818df555e627 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -209,7 +209,7 @@ void dm_helpers_init_panel_settings( struct dc_sink *sink); void dm_helpers_override_panel_settings( struct dc_context *ctx, - struct dc_panel_config *config); + struct dc_link *link); int dm_helper_dmub_aux_transfer_sync( struct dc_context *ctx, const struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 578509e8d0e25..b2c020071cbfb 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1333,7 +1333,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, // Pickup base DM settings dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); // Override dc_panel_config if system has specific settings - dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); + dm_helpers_override_panel_settings(dc_ctx, link); //sink only can use supported link rate table, we are foreced to enable it if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN) From cab6b735dc1bee3dd0021b9208b2d2ac476495dd Mon Sep 17 00:00:00 2001 From: Muaaz Nisar Date: Wed, 4 Feb 2026 03:08:01 -0500 Subject: [PATCH 0187/2070] drm/amd/display: Implementing ramless idle mouse trigger [Why & How] Adding mouse trigger in dc_stream to recover from low refresh rate idle state upon mouse movement without vsync interrupts. Reviewed-by: Aric Cyr Signed-off-by: Muaaz Nisar Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++++ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 +++++++++++++++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 9 +++++++++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 17ba7af0ddcd9..6f3c283431d43 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3369,6 +3369,10 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->scaler_sharpener_update = *update->scaler_sharpener_update; if (update->sharpening_required) stream->sharpening_required = *update->sharpening_required; + + if (update->drr_trigger_mode) { + stream->drr_trigger_mode = *update->drr_trigger_mode; + } } static void backup_planes_and_stream_state( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9349cccc8438d..191f6435e7c64 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -515,6 +515,21 @@ bool dc_stream_program_cursor_position( } } + if (stream->drr_trigger_mode == DRR_TRIGGER_ON_FLIP_AND_CURSOR) { + /* apply manual trigger */ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* trigger event on first pipe with current stream */ + if (stream == pipe_ctx->stream) { + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + break; + } + } + } + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 9960494007ffb..86394203cee79 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -183,6 +183,11 @@ struct luminance_data { int dm_max_decrease_from_nominal; }; +enum dc_drr_trigger_mode { + DRR_TRIGGER_ON_FLIP = 0, + DRR_TRIGGER_ON_FLIP_AND_CURSOR, +}; + struct dc_stream_state { // sink is deprecated, new code should not reference // this pointer @@ -316,6 +321,8 @@ struct dc_stream_state { bool scaler_sharpener_update; bool sharpening_required; + enum dc_drr_trigger_mode drr_trigger_mode; + struct dc_update_scratch_space *update_scratch; }; @@ -366,6 +373,8 @@ struct dc_stream_update { bool *hw_cursor_req; bool *scaler_sharpener_update; bool *sharpening_required; + + enum dc_drr_trigger_mode *drr_trigger_mode; }; bool dc_is_stream_unchanged( From 2676b86370f55294d9e7a618b56ee5ae5aab6241 Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Tue, 3 Feb 2026 15:37:07 +0530 Subject: [PATCH 0188/2070] drm/amd/display: Migrate DCCG registers access from hwseq to dccg component. [Why] Direct DCCG register access in hwseq layer was creating register conflicts. [How] Migrated DCCG registers from hwseq-dccg component. Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../amd/display/dc/dccg/dcn20/dcn20_dccg.c | 54 ++++++++++++++++++- .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 14 +++-- .../amd/display/dc/dccg/dcn201/dcn201_dccg.c | 7 ++- .../amd/display/dc/dccg/dcn21/dcn21_dccg.c | 6 ++- .../amd/display/dc/dccg/dcn30/dcn30_dccg.c | 6 ++- .../amd/display/dc/dccg/dcn301/dcn301_dccg.c | 6 ++- .../amd/display/dc/dccg/dcn31/dcn31_dccg.c | 5 ++ .../amd/display/dc/dccg/dcn314/dcn314_dccg.c | 7 ++- .../amd/display/dc/dccg/dcn32/dcn32_dccg.c | 5 ++ .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 11 +++- .../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 2 + .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 29 +++------- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 9 ++-- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 5 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 ++ 21 files changed, 143 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c index 33d8bd91cb014..733b85d450d99 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c @@ -131,6 +131,54 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg) { + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* Hardcoded register values for DCN20 + * These are specific to 100Mhz refclk + * Different ASICs with different refclk may override this in their own init + */ + REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); + REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); + + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); +} + +void dccg2_refclk_setup(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* REFCLK programming that must occur after hubbub initialization */ + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); +} + +bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464; +} + +void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (allow) { + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + } else { + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); + } +} + +void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); } static const struct dccg_funcs dccg2_funcs = { @@ -139,7 +187,11 @@ static const struct dccg_funcs dccg2_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg2_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 8bdffd9ff31b1..3711d400773af 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -37,7 +37,8 @@ SR(REFCLK_CNTL),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ - SR(DISPCLK_FREQ_CHANGE_CNTL) + SR(DISPCLK_FREQ_CHANGE_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) #define DCCG_REG_LIST_DCN2() \ DCCG_COMMON_REG_LIST_DCN_BASE(),\ @@ -81,7 +82,8 @@ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ + DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) @@ -130,7 +132,8 @@ type DISPCLK_CHG_FWD_CORR_DISABLE;\ type DISPCLK_FREQ_CHANGE_CNTL;\ type OTG_ADD_PIXEL[MAX_PIPES];\ - type OTG_DROP_PIXEL[MAX_PIPES]; + type OTG_DROP_PIXEL[MAX_PIPES];\ + type DC_MEM_GLOBAL_PWR_REQ_DIS; #define DCCG3_REG_FIELD_LIST(type) \ type HDMICHARCLK0_EN;\ @@ -515,6 +518,11 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg); +void dccg2_refclk_setup(struct dccg *dccg); +void dccg2_allow_clock_gating(struct dccg *dccg, bool allow); +void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable); +bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg); + struct dccg *dccg2_create( struct dc_context *ctx, const struct dccg_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c index 9a3402148fde0..79d14ce19393a 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c @@ -24,6 +24,7 @@ */ #include "dcn201_dccg.h" +#include "dcn20/dcn20_dccg.h" #include "reg_helper.h" #include "core_types.h" @@ -56,7 +57,11 @@ static const struct dccg_funcs dccg201_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg201_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c index d07c04458d31a..b48dcafbae66a 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c @@ -103,7 +103,11 @@ static const struct dccg_funcs dccg21_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg21_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c index d445dfefc047a..adec7c3c2d494 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c @@ -49,7 +49,11 @@ static const struct dccg_funcs dccg3_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg3_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c index 97e9be87afd9e..fc9bddd94b508 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c @@ -48,7 +48,11 @@ static const struct dccg_funcs dccg301_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg301_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c index 97df04b7e39d1..c647dff5234a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c @@ -26,6 +26,7 @@ #include "reg_helper.h" #include "core_types.h" #include "dcn31_dccg.h" +#include "dcn20/dcn20_dccg.h" #include "dal_asic_id.h" #define TO_DCN_DCCG(dccg)\ @@ -850,6 +851,10 @@ static const struct dccg_funcs dccg31_funcs = { .disable_dsc = dccg31_disable_dscclk, .enable_dsc = dccg31_enable_dscclk, .dccg_read_reg_state = dccg31_read_reg_state, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg31_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c index ef3db6beba25c..2e9c4b13988a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c @@ -29,6 +29,7 @@ #include "dcn31/dcn31_dccg.h" #include "dcn314_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -378,7 +379,11 @@ static const struct dccg_funcs dccg314_funcs = { .trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync, .set_valid_pixel_rate = dccg314_set_valid_pixel_rate, .set_dtbclk_p_src = dccg314_set_dtbclk_p_src, - .dccg_read_reg_state = dccg31_read_reg_state + .dccg_read_reg_state = dccg31_read_reg_state, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg314_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c index 21a6ca5ca1927..ce697c3249fbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c @@ -26,6 +26,7 @@ #include "reg_helper.h" #include "core_types.h" #include "dcn32_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -347,6 +348,10 @@ static const struct dccg_funcs dccg32_funcs = { .get_pixel_rate_div = dccg32_get_pixel_rate_div, .trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync, .set_dtbclk_p_src = dccg32_set_dtbclk_p_src, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg32_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 838c6617c0294..943ec19830764 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -26,6 +26,7 @@ #include "core_types.h" #include "resource.h" #include "dcn35_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -2411,6 +2412,10 @@ static const struct dccg_funcs dccg35_funcs_new = { .enable_symclk_se = dccg35_enable_symclk_se_cb, .disable_symclk_se = dccg35_disable_symclk_se_cb, .set_dtbclk_p_src = dccg35_set_dtbclk_p_src_cb, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; static const struct dccg_funcs dccg35_funcs = { @@ -2442,8 +2447,12 @@ static const struct dccg_funcs dccg35_funcs = { .enable_symclk_se = dccg35_enable_symclk_se, .disable_symclk_se = dccg35_disable_symclk_se, .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done, /* Deprecated - for backward compatibility only */ .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, - .dccg_read_reg_state = dccg31_read_reg_state, + .dccg_read_reg_state = dccg31_read_reg_state }; struct dccg *dccg35_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 3063b6ab32e5f..f1d3945608920 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -27,6 +27,7 @@ #include "core_types.h" #include "dcn401_dccg.h" #include "dcn31/dcn31_dccg.h" +#include "dcn20/dcn20_dccg.h" /* #include "dmub_common.h" @@ -861,6 +862,7 @@ static const struct dccg_funcs dccg401_funcs = { .update_dpp_dto = dccg401_update_dpp_dto, .get_dccg_ref_freq = dccg401_get_dccg_ref_freq, .dccg_init = dccg401_init, + .allow_clock_gating = dccg2_allow_clock_gating, .set_dpstreamclk = dccg401_set_dpstreamclk, .enable_symclk32_se = dccg31_enable_symclk32_se, .disable_symclk32_se = dccg31_disable_symclk32_se, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 9613d1ceb5dcb..5243177c1faad 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -1887,9 +1887,8 @@ void dcn10_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 0ee3a0041c619..307e8f8060e6d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -357,26 +357,10 @@ void dcn20_enable_power_gating_plane( void dcn20_dccg_init(struct dce_hwseq *hws) { - /* - * set MICROSECOND_TIME_BASE_DIV - * 100Mhz refclk -> 0x120264 - * 27Mhz refclk -> 0x12021b - * 48Mhz refclk -> 0x120230 - * - */ - REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); - - /* - * set MILLISECOND_TIME_BASE_DIV - * 100Mhz refclk -> 0x1186a0 - * 27Mhz refclk -> 0x106978 - * 48Mhz refclk -> 0x10bb80 - * - */ - REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); + struct dc *dc = hws->ctx->dc; - /* This value is dependent on the hardware pipeline delay so set once per SOC */ - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init) + dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg); } void dcn20_disable_vga( @@ -3156,8 +3140,11 @@ void dcn20_fpga_init_hw(struct dc *dc) dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); - if (REG(REFCLK_CNTL)) - REG_WRITE(REFCLK_CNTL, 0); + if (hws->funcs.dccg_init) + hws->funcs.dccg_init(hws); + + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup) + dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 6298bd87a18b7..ce18d75fd9918 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -367,9 +367,8 @@ void dcn201_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index e2269211553ce..062745389d9a4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -33,6 +33,7 @@ #include "vmid.h" #include "reg_helper.h" #include "hw/clk_mgr.h" +#include "hw/dccg.h" #include "dc_dmub_srv.h" #include "abm.h" #include "link_service.h" @@ -87,12 +88,10 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_ bool dcn21_s0i3_golden_init_wa(struct dc *dc) { - struct dce_hwseq *hws = dc->hwseq; - uint32_t value = 0; + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done) + return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); - value = REG_READ(MICROSECOND_TIME_BASE_DIV); - - return value != 0x00120464; + return false; } void dcn21_exit_optimized_pwr_state( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 333275088a6c2..d04cfd403b7ee 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -801,9 +801,8 @@ void dcn30_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index fa35d538a10a5..db2f7cbb12ff5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -247,9 +247,8 @@ void dcn31_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 01fa459ae7b06..2767d3a97812e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -963,9 +963,8 @@ void dcn32_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 0cbd75ab61a1e..b5a4cefbd35f2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -286,7 +286,8 @@ void dcn35_init_hw(struct dc *dc) } if (dc->debug.disable_mem_low_power) { - REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power) + dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false); } if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index d1515039e8249..b91517b9fedcf 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -326,9 +326,8 @@ void dcn401_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 1e6ffd86a4c0a..d6f5e01a0b66c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -224,6 +224,10 @@ struct dccg_funcs { void (*otg_drop_pixel)(struct dccg *dccg, uint32_t otg_inst); void (*dccg_init)(struct dccg *dccg); + void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */ + void (*allow_clock_gating)(struct dccg *dccg, bool allow); + void (*enable_memory_low_power)(struct dccg *dccg, bool enable); + bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg); void (*set_dpstreamclk_root_clock_gating)( struct dccg *dccg, int dp_hpo_inst, From 3635475afc23e56ffc27b37c060dbb48acde4551 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Wed, 4 Feb 2026 16:52:48 -0500 Subject: [PATCH 0189/2070] Revert "drm/amd/display: Add Handling for gfxversion DcGfxBase" This reverts commit e563d5a20036 ("drm/amd/display: Add Handling for gfxversion DcGfxBase") Reason for revert: Cause some regressions Reviewed-by: Dillon Varone Signed-off-by: Nicholas Carbones Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index f4bcebd7ec7fb..75a2799979615 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -460,9 +460,6 @@ static void populate_dml21_surface_config_from_plane_state( case DcGfxAddr3: surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); break; - case DcGfxBase: - surface->tiling = dml2_sw_linear; - break; } } From 327890a7918a57656634bd0fa2593f926436b770 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Mon, 9 Feb 2026 11:34:00 +0800 Subject: [PATCH 0190/2070] Revert "drm/amd/display: Correct hubp GfxVersion verification" This reverts commit 5ea2687f98a ("drm/amd/display: Correct hubp GfxVersion verification") Reason for revert: Got blank screen issues while doing PNP Reviewed-by: Joshua Aberback Signed-off-by: Nicholas Carbones Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../amd/display/dc/hubp/dcn10/dcn10_hubp.c | 35 ++++++++----------- .../amd/display/dc/hubp/dcn20/dcn20_hubp.c | 28 +++++++-------- .../amd/display/dc/hubp/dcn30/dcn30_hubp.c | 28 +++++++-------- 3 files changed, 39 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index 78c866688c615..e697d9bf1b44c 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c @@ -145,26 +145,21 @@ void hubp1_program_tiling( { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase); - - if (info->gfxversion == DcGfxVersion9) { - REG_UPDATE_6(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - NUM_BANKS, log_2(info->gfx9.num_banks), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - NUM_SE, log_2(info->gfx9.num_shader_engines), - NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); - - REG_UPDATE_4(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, info->gfx9.meta_linear, - RB_ALIGNED, info->gfx9.rb_aligned, - PIPE_ALIGNED, info->gfx9.pipe_aligned); - } else { - hubp1_clear_tiling(&hubp1->base); - } - + ASSERT(info->gfxversion == DcGfxVersion9); + + REG_UPDATE_6(DCSURF_ADDR_CONFIG, + NUM_PIPES, log_2(info->gfx9.num_pipes), + NUM_BANKS, log_2(info->gfx9.num_banks), + PIPE_INTERLEAVE, info->gfx9.pipe_interleave, + NUM_SE, log_2(info->gfx9.num_shader_engines), + NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), + MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); + + REG_UPDATE_4(DCSURF_TILING_CONFIG, + SW_MODE, info->gfx9.swizzle, + META_LINEAR, info->gfx9.meta_linear, + RB_ALIGNED, info->gfx9.rb_aligned, + PIPE_ALIGNED, info->gfx9.pipe_aligned); } void hubp1_program_size( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index aaa8f8cf6c303..4715e60e812ac 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -313,22 +313,18 @@ static void hubp2_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase); - - if (info->gfxversion == DcGfxVersion9) { - REG_UPDATE_3(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); - - REG_UPDATE_4(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, 0, - RB_ALIGNED, 0, - PIPE_ALIGNED, 0); - } else { - hubp2_clear_tiling(&hubp2->base); - } + ASSERT(info->gfxversion == DcGfxVersion9); + + REG_UPDATE_3(DCSURF_ADDR_CONFIG, + NUM_PIPES, log_2(info->gfx9.num_pipes), + PIPE_INTERLEAVE, info->gfx9.pipe_interleave, + MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); + + REG_UPDATE_4(DCSURF_TILING_CONFIG, + SW_MODE, info->gfx9.swizzle, + META_LINEAR, 0, + RB_ALIGNED, 0, + PIPE_ALIGNED, 0); } void hubp2_program_size( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 2126830a5a9e1..207c2f86b7d78 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -321,22 +321,18 @@ void hubp3_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase); - - if (info->gfxversion == DcGfxVersion9) { - REG_UPDATE_4(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), - NUM_PKRS, log_2(info->gfx9.num_pkrs)); - - REG_UPDATE_3(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, info->gfx9.meta_linear, - PIPE_ALIGNED, info->gfx9.pipe_aligned); - } else { - hubp3_clear_tiling(&hubp2->base); - } + ASSERT(info->gfxversion == DcGfxVersion9); + + REG_UPDATE_4(DCSURF_ADDR_CONFIG, + NUM_PIPES, log_2(info->gfx9.num_pipes), + PIPE_INTERLEAVE, info->gfx9.pipe_interleave, + MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), + NUM_PKRS, log_2(info->gfx9.num_pkrs)); + + REG_UPDATE_3(DCSURF_TILING_CONFIG, + SW_MODE, info->gfx9.swizzle, + META_LINEAR, info->gfx9.meta_linear, + PIPE_ALIGNED, info->gfx9.pipe_aligned); } From a8ecd36f0de5e1b70ec6186f367b88323bfa5f66 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Mon, 9 Feb 2026 11:37:23 +0800 Subject: [PATCH 0191/2070] Revert "drm/amd/display: Add Gfx Base Case For Linear Tiling Handling" This reverts commit 27ca0d596700 ("drm/amd/display: Add Gfx Base Case For Linear Tiling Handling") Reason for revert: Got blank screen issues while doing PNP Reviewed-by: Joshua Aberback Signed-off-by: Nicholas Carbones Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 7 ------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 - drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 +-- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 --- drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 1 - drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c | 2 -- drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c | 2 -- drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c | 2 -- drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 7 +------ .../amd/display/dc/resource/dcn32/dcn32_resource_helpers.c | 3 +-- 13 files changed, 3 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ef9df52dd34bf..9a9f8362811f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8040,7 +8040,6 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc, dc_plane_state->plane_size.chroma_size.height = stream->src.height; dc_plane_state->plane_size.chroma_size.width = stream->src.width; dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; - dc_plane_state->tiling_info.gfxversion = DcGfxVersion9; dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; dc_plane_state->rotation = ROTATION_ANGLE_0; dc_plane_state->is_tiling_rotated = false; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 6f3c283431d43..984b4bc5f53c6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2770,7 +2770,6 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct case DcGfxVersion7: case DcGfxVersion8: case DcGfxVersionUnknown: - case DcGfxBase: default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index a13d9d7dd6c50..052d573408c3e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -2065,13 +2065,6 @@ void get_surface_tile_visual_confirm_color( while (bottom_pipe_ctx->bottom_pipe != NULL) bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; - if (bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxBase) { - /* LINEAR Surface - set border color to red */ - color->color_r_cr = color_value; - return; - } - - ASSERT(bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9); switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { case DC_SW_LINEAR: /* LINEAR Surface - set border color to red */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 639831295b219..03d125f794b05 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -4434,7 +4434,6 @@ enum dc_status dc_validate_global_state( if (dc->res_pool->funcs->patch_unknown_plane_state && pipe_ctx->plane_state && - pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9 && pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); if (result != DC_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 7121629da38ed..cfa569a7bff1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -342,8 +342,7 @@ enum swizzle_mode_addr3_values { }; enum dc_gfxversion { - DcGfxBase = 0, - DcGfxVersion7, + DcGfxVersion7 = 0, DcGfxVersion8, DcGfxVersion9, DcGfxVersion10, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 5df58fadc8621..1c2009e38aa12 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -100,7 +100,6 @@ static enum mi_bits_per_pixel get_mi_bpp( static enum mi_tiling_format get_mi_tiling( struct dc_tiling_info *tiling_info) { - ASSERT(tiling_info->gfxversion == DcGfxVersion8); switch (tiling_info->gfx8.array_mode) { case DC_ARRAY_1D_TILED_THIN1: case DC_ARRAY_1D_TILED_THICK: @@ -434,7 +433,6 @@ static void program_tiling( struct dce_mem_input *dce_mi, const struct dc_tiling_info *info) { if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ - ASSERT(info->gfxversion == DcGfxVersion9); REG_UPDATE_6(GRPH_CONTROL, GRPH_SW_MODE, info->gfx9.swizzle, GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), @@ -449,7 +447,6 @@ static void program_tiling( } if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */ - ASSERT(info->gfxversion == DcGfxVersion8); REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, GRPH_BANK_WIDTH, info->gfx8.bank_width, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index 67cfca3361fb9..2c43c24226385 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -165,8 +165,6 @@ static void program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion8); - uint32_t value = 0; set_reg_field_value(value, info->gfx8.num_banks, @@ -543,7 +541,6 @@ static const unsigned int *get_dvmm_hw_setting( else bpp = bpp_8; - ASSERT(tiling_info->gfxversion == DcGfxVersion8); switch (tiling_info->gfx8.array_mode) { case DC_ARRAY_1D_TILED_THIN1: case DC_ARRAY_1D_TILED_THICK: diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index 71eeee02c0fa5..74962791302f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -1006,7 +1006,6 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( pipe->plane_state->format); - ASSERT(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( pipe->plane_state->tiling_info.gfx9.swizzle); v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index e697d9bf1b44c..6378e3fd72494 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c @@ -145,8 +145,6 @@ void hubp1_program_tiling( { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - ASSERT(info->gfxversion == DcGfxVersion9); - REG_UPDATE_6(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), NUM_BANKS, log_2(info->gfx9.num_banks), diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index 4715e60e812ac..92288de4cc10c 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -313,8 +313,6 @@ static void hubp2_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion9); - REG_UPDATE_3(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), PIPE_INTERLEAVE, info->gfx9.pipe_interleave, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 207c2f86b7d78..0cc6f45589898 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -321,8 +321,6 @@ void hubp3_program_tiling( const struct dc_tiling_info *info, const enum surface_pixel_format pixel_format) { - ASSERT(info->gfxversion == DcGfxVersion9); - REG_UPDATE_4(DCSURF_ADDR_CONFIG, NUM_PIPES, log_2(info->gfx9.num_pipes), PIPE_INTERLEAVE, info->gfx9.pipe_interleave, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 861e940250af2..c205500290ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -589,12 +589,7 @@ void hubp401_program_tiling( * * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default. */ - if (info->gfxversion == DcGfxAddr3) { - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); - } else { - /* linear */ - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, 0); - } + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); } void hubp401_program_size( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index 7d99f5d79e6dc..f5a4e97c40ced 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -401,8 +401,7 @@ void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, */ if (pipe_cnt == 1) { pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; - if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfxversion != DcGfxBase && - !(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9 && pipe->plane_state->tiling_info.gfx9.swizzle == DC_SW_LINEAR)) { + if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { if (!is_dual_plane(pipe->plane_state->format)) { pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; pipes[0].pipe.src.unbounded_req_mode = true; From 737b16f1e02205d2344541acf1438ac7452b3bc1 Mon Sep 17 00:00:00 2001 From: Saidireddy Yenugu Date: Wed, 21 Jan 2026 18:57:25 +0530 Subject: [PATCH 0192/2070] drm/amd/display: Skip eDP detection when no sink [Why & How] When there is no eDP panel connected and during s0ix resume, unnecessary eDP power sequence and HPD happening, resulting in ~2 seconds delay. Fixed the issue by avoiding link detect for eDP connection with no sink in dm_resume. Reviewed-by: Mario Limonciello Signed-off-by: Saidireddy Yenugu Co-developed-by: ThummarDip Kishorbhai Signed-off-by: ThummarDip Kishorbhai Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9a9f8362811f1..c3c045c8144f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3614,6 +3614,11 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) if (aconnector->mst_root) continue; + /* Skip eDP detection, when there is no sink present */ + if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && + !aconnector->dc_link->edp_sink_present) + continue; + guard(mutex)(&aconnector->hpd_lock); if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); From c63065b45e02c09bd3fd36dae359aab75481e0c1 Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Thu, 29 Jan 2026 11:26:13 +0100 Subject: [PATCH 0193/2070] drm/amd/display: Refactor and fix link_dpms I2C [Why] link_dpms.c issues I2C writes during HDMI link enablement. Current implementation contains a lot of duplicated code with copy-paste errors. [How] * Refactor common logic into helper functions. * Invert logic with early returns to decrease indentation. * Sequence writes by looping over data arrays. * Fix write_i2c_retimer_setting is_over_340mhz checking reg_settings instead of reg_settings_6g in the i2c_reg_index <= 0x20 check. Reviewed-by: Wenjing Liu Signed-off-by: Dominik Kaszewski Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/link/link_dpms.c | 475 ++++++------------ 1 file changed, 165 insertions(+), 310 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 91742bde4dc28..befbe005af68b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -320,344 +320,203 @@ static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, return result; } -static bool write_i2c(struct pipe_ctx *pipe_ctx, - uint8_t address, uint8_t *buffer, uint32_t length) +static bool write_i2c( + const struct dc_link *link, + uint8_t address, + uint8_t *buffer, + uint32_t length +) { - struct i2c_command cmd = {0}; - struct i2c_payload payload = {0}; + struct i2c_payload payload = { + .write = true, + .address = address, + .length = length, + .data = buffer, + }; + struct i2c_command cmd = { + .payloads = &payload, + .number_of_payloads = 1, + .engine = I2C_COMMAND_ENGINE_DEFAULT, + .speed = link->ctx->dc->caps.i2c_speed_in_khz, + }; + + return dm_helpers_submit_i2c(link->ctx, link, &cmd); +} - memset(&payload, 0, sizeof(payload)); - memset(&cmd, 0, sizeof(cmd)); +static bool write_i2c_retimer_offset_value( + const struct dc_link *link, + uint8_t address, + uint8_t offset, + uint8_t value +) +{ + DC_LOGGER_INIT(link->ctx->logger); + uint8_t buffer[] = { offset, value }; + const bool success = write_i2c(link, address, buffer, sizeof(buffer)); + + RETIMER_REDRIVER_INFO( + "Retimer write, address: 0x%x, offset: 0x%x, value: 0x%x, success: %d\n", + address, offset, value, success + ); + return success; +} - cmd.number_of_payloads = 1; - cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; - cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; +static bool write_i2c_retimer_vga( + const struct dc_link *link, + uint8_t address +) +{ + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t vga_data[][2] = { + { 0xFF, 0x01 }, + { 0x00, 0x23 }, + { 0xFF, 0x00 }, + }; + + for (size_t i = 0; i < ARRAY_SIZE(vga_data); i++) { + if (!write_i2c_retimer_offset_value(link, address, vga_data[i][0], vga_data[i][1])) { + DC_LOG_ERROR("Set retimer failed, vga index: %zu\n", i); + return false; + } + } + return true; +} - payload.address = address; - payload.data = buffer; - payload.length = length; - payload.write = true; - cmd.payloads = &payload; +static bool write_i2c_retimer_byte( + const struct dc_link *link, + uint8_t address, + uint8_t index, + uint8_t value +) +{ + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t apply_rx_tx_change = 0x4; - if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, - pipe_ctx->stream->link, &cmd)) + if (index > 0x20) return true; - return false; + if (!write_i2c_retimer_offset_value(link, address, index, value)) { + DC_LOG_ERROR("Set retimer failed, 3g index: 0x%x, value: 0x%x\n", index, value); + return false; + } + + // Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A + // needs to be set to 1 on every 0x0A-0x0C write. + if (0x0A <= index && index <= 0x0C) { + uint8_t offset = 0x0A; + + // Query current value from offset 0x0A + if (index == 0x0A) { + // Just written correct value, so no need to read it back + } else { + if (!link_query_ddc_data( + link->ddc, address, &offset, 1, &value, 1 + )) { + DC_LOG_ERROR("Set retimer failed, link_query_ddc_data\n"); + return false; + } + } + + value |= apply_rx_tx_change; + if (!write_i2c_retimer_offset_value(link, address, offset, value)) { + DC_LOG_ERROR("Set retimer failed, 3g offset: 0x%x, value: 0x%x\n", offset, value); + return false; + } + } + return true; } -static void write_i2c_retimer_setting( - struct pipe_ctx *pipe_ctx, +static bool write_i2c_retimer_setting( + const struct dc_link *link, bool is_vga_mode, bool is_over_340mhz, struct ext_hdmi_settings *settings) { - uint8_t slave_address = (settings->slv_addr >> 1); - uint8_t buffer[2]; - const uint8_t apply_rx_tx_change = 0x4; - uint8_t offset = 0xA; - uint8_t value = 0; - int i = 0; - bool i2c_success = false; - DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); - - memset(&buffer, 0, sizeof(buffer)); - - /* Start Ext-Hdmi programming*/ - - for (i = 0; i < settings->reg_num; i++) { - /* Apply 3G settings */ - if (settings->reg_settings[i].i2c_reg_index <= 0x20) { - - buffer[0] = settings->reg_settings[i].i2c_reg_index; - buffer[1] = settings->reg_settings[i].i2c_reg_val; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t address = settings->slv_addr >> 1; - if (!i2c_success) - goto i2c_write_fail; + for (size_t i = 0; i < settings->reg_num; i++) { + const uint8_t index = settings->reg_settings[i].i2c_reg_index; + uint8_t value = settings->reg_settings[i].i2c_reg_val; - /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A - * needs to be set to 1 on every 0xA-0xC write. - */ - if (settings->reg_settings[i].i2c_reg_index == 0xA || - settings->reg_settings[i].i2c_reg_index == 0xB || - settings->reg_settings[i].i2c_reg_index == 0xC) { - - /* Query current value from offset 0xA */ - if (settings->reg_settings[i].i2c_reg_index == 0xA) - value = settings->reg_settings[i].i2c_reg_val; - else { - i2c_success = - link_query_ddc_data( - pipe_ctx->stream->link->ddc, - slave_address, &offset, 1, &value, 1); - if (!i2c_success) - goto i2c_write_fail; - } - - buffer[0] = offset; - /* Set APPLY_RX_TX_CHANGE bit to 1 */ - buffer[1] = value | apply_rx_tx_change; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - } + if (!write_i2c_retimer_byte(link, address, index, value)) { + DC_LOG_ERROR("Set retimer failed, index: %zu\n", i); + return false; } } - /* Apply 3G settings */ if (is_over_340mhz) { - for (i = 0; i < settings->reg_num_6g; i++) { - /* Apply 3G settings */ - if (settings->reg_settings[i].i2c_reg_index <= 0x20) { - - buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; - buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - - if (!i2c_success) - goto i2c_write_fail; - - /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A - * needs to be set to 1 on every 0xA-0xC write. - */ - if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || - settings->reg_settings_6g[i].i2c_reg_index == 0xB || - settings->reg_settings_6g[i].i2c_reg_index == 0xC) { - - /* Query current value from offset 0xA */ - if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) - value = settings->reg_settings_6g[i].i2c_reg_val; - else { - i2c_success = - link_query_ddc_data( - pipe_ctx->stream->link->ddc, - slave_address, &offset, 1, &value, 1); - if (!i2c_success) - goto i2c_write_fail; - } + for (size_t i = 0; i < settings->reg_num_6g; i++) { + const uint8_t index = settings->reg_settings_6g[i].i2c_reg_index; + uint8_t value = settings->reg_settings_6g[i].i2c_reg_val; - buffer[0] = offset; - /* Set APPLY_RX_TX_CHANGE bit to 1 */ - buffer[1] = value | apply_rx_tx_change; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - } + if (!write_i2c_retimer_byte(link, address, index, value)) { + DC_LOG_ERROR("Set retimer failed, 6g index: %zu\n", i); + return false; } } } if (is_vga_mode) { - /* Program additional settings if using 640x480 resolution */ - - /* Write offset 0xFF to 0x01 */ - buffer[0] = 0xff; - buffer[1] = 0x01; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x00 to 0x23 */ - buffer[0] = 0x00; - buffer[1] = 0x23; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0xff to 0x00 */ - buffer[0] = 0xff; - buffer[1] = 0x00; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - } - - return; - -i2c_write_fail: - DC_LOG_DEBUG("Set retimer failed"); + return write_i2c_retimer_vga(link, address); + } + return true; } -static void write_i2c_default_retimer_setting( - struct pipe_ctx *pipe_ctx, +static bool write_i2c_default_retimer_setting( + const struct dc_link *link, bool is_vga_mode, bool is_over_340mhz) { - uint8_t slave_address = (0xBA >> 1); - uint8_t buffer[2]; - bool i2c_success = false; - DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); + const uint8_t address = 0xBA >> 1; - memset(&buffer, 0, sizeof(buffer)); - - /* Program Slave Address for tuning single integrity */ - /* Write offset 0x0A to 0x13 */ - buffer[0] = 0x0A; - buffer[1] = 0x13; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0A to 0x17 */ - buffer[0] = 0x0A; - buffer[1] = 0x17; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0B to 0xDA or 0xD8 */ - buffer[0] = 0x0B; - buffer[1] = is_over_340mhz ? 0xDA : 0xD8; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0A to 0x17 */ - buffer[0] = 0x0A; - buffer[1] = 0x17; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0C to 0x1D or 0x91 */ - buffer[0] = 0x0C; - buffer[1] = is_over_340mhz ? 0x1D : 0x91; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0A to 0x17 */ - buffer[0] = 0x0A; - buffer[1] = 0x17; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t data[][2] = { + { 0x0A, 0x13 }, + { 0x0A, 0x17 }, + { 0x0B, is_over_340mhz ? 0xDA : 0xD8 }, + { 0x0A, 0x17 }, + { 0x0C, is_over_340mhz ? 0x1D : 0x91 }, + { 0x0A, 0x17 }, + }; + + for (size_t i = 0; i < ARRAY_SIZE(data); i++) { + if (!write_i2c_retimer_offset_value(link, address, data[i][0], data[i][1])) { + DC_LOG_ERROR("Set default retimer failed, index: %zu\n", i); + return false; + } + } if (is_vga_mode) { - /* Program additional settings if using 640x480 resolution */ - - /* Write offset 0xFF to 0x01 */ - buffer[0] = 0xff; - buffer[1] = 0x01; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x00 to 0x23 */ - buffer[0] = 0x00; - buffer[1] = 0x23; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0xff to 0x00 */ - buffer[0] = 0xff; - buffer[1] = 0x00; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - } - - return; - -i2c_write_fail: - DC_LOG_DEBUG("Set default retimer failed"); + return write_i2c_retimer_vga(link, address); + } + return true; } -static void write_i2c_redriver_setting( - struct pipe_ctx *pipe_ctx, +static bool write_i2c_redriver_setting( + const struct dc_link *link, bool is_over_340mhz) { - uint8_t slave_address = (0xF0 >> 1); - uint8_t buffer[16]; - bool i2c_success = false; - DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); - - memset(&buffer, 0, sizeof(buffer)); - - // Program Slave Address for tuning single integrity - buffer[3] = 0x4E; - buffer[4] = 0x4E; - buffer[5] = 0x4E; - buffer[6] = is_over_340mhz ? 0x4E : 0x4A; - - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ - \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ - offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ - i2c_success = %d\n", - slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); - - if (!i2c_success) - DC_LOG_DEBUG("Set redriver failed"); + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t address = 0xF0 >> 1; + uint8_t buffer[16] = { + [3] = 0x4E, + [4] = 0x4E, + [5] = 0x4E, + [6] = is_over_340mhz ? 0x4E : 0x4A, + }; + + const bool success = write_i2c(link, address, buffer, sizeof(buffer)); + + RETIMER_REDRIVER_INFO( + "Redriver write, address: 0x%x, buffer: { [3]: 0x%x, 0x%x, 0x%x, 0x%x }, success: %d\n", + address, buffer[3], buffer[4], buffer[5], buffer[6], success + ); + + if (!success) + DC_LOG_ERROR("Set redriver failed"); + return success; } static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) @@ -1934,15 +1793,13 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) eng_id = pipe_ctx->stream_res.stream_enc->id; if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { - write_i2c_retimer_setting(pipe_ctx, - is_vga_mode, is_over_340mhz, &settings); + write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings); } else { - write_i2c_default_retimer_setting(pipe_ctx, - is_vga_mode, is_over_340mhz); + write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz); } } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { /* PI3EQX1204, Redriver settings */ - write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); + write_i2c_redriver_setting(link, is_over_340mhz); } } @@ -2353,14 +2210,12 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { /* DP159, Retimer settings */ if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) - write_i2c_retimer_setting(pipe_ctx, - false, false, &settings); + write_i2c_retimer_setting(link, false, false, &settings); else - write_i2c_default_retimer_setting(pipe_ctx, - false, false); + write_i2c_default_retimer_setting(link, false, false); } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { /* PI3EQX1204, Redriver settings */ - write_i2c_redriver_setting(pipe_ctx, false); + write_i2c_redriver_setting(link, false); } } From c49ce77beb48ccb894e9c6806e256e36b56c3409 Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Thu, 29 Jan 2026 11:53:29 +0100 Subject: [PATCH 0194/2070] drm/amd/display: Refactor and fix link_dpms info [Why] get_ext_hdmi_settings contained a copy-paste error, assigning both reg_num_6g and reg_num from dp0_ext_hdmi_6g_reg_num. [How] * Correctly assign reg_num from dp0_ext_hdmi_reg_num. * Refactor and clean the function. Reviewed-by: Wenjing Liu Signed-off-by: Dominik Kaszewski Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/link/link_dpms.c | 165 +++++++++--------- 1 file changed, 84 insertions(+), 81 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index befbe005af68b..89c916dbf6575 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -223,16 +223,32 @@ void link_get_master_pipes_with_dpms_on(const struct dc_link *link, } } -static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, - enum engine_id eng_id, - struct ext_hdmi_settings *settings) +static struct ext_hdmi_settings create_ext_hdmi_settings( + uint8_t address, + uint8_t reg_num, + uint8_t reg_num_6g, + const struct i2c_reg_info *reg_settings, + const struct i2c_reg_info *reg_settings_6g +) { - bool result = false; - int i = 0; - struct integrated_info *integrated_info = - pipe_ctx->stream->ctx->dc_bios->integrated_info; + struct ext_hdmi_settings result = { + .slv_addr = address, + .reg_num = reg_num, + .reg_num_6g = reg_num_6g, + }; + + memcpy(result.reg_settings, reg_settings, sizeof(result.reg_settings)); + memcpy(result.reg_settings_6g, reg_settings_6g, sizeof(result.reg_settings_6g)); + return result; +} - if (integrated_info == NULL) +static bool get_ext_hdmi_settings( + const struct integrated_info *info, + enum engine_id eng_id, + struct ext_hdmi_settings *settings +) +{ + if (!settings || !info) return false; /* @@ -242,82 +258,69 @@ static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, */ // Check if current bios contains ext Hdmi settings - if (integrated_info->gpu_cap_info & 0x20) { - switch (eng_id) { - case ENGINE_ID_DIGA: - settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp0_ext_hdmi_reg_settings, - sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp0_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); - result = true; - break; - case ENGINE_ID_DIGB: - settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp1_ext_hdmi_reg_settings, - sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp1_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); - result = true; - break; - case ENGINE_ID_DIGC: - settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp2_ext_hdmi_reg_settings, - sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp2_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); - result = true; - break; - case ENGINE_ID_DIGD: - settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp3_ext_hdmi_reg_settings, - sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp3_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); - result = true; - break; - default: - break; - } + if (!(info->gpu_cap_info & 0x20)) + return false; - if (result == true) { - // Validate settings from bios integrated info table - if (settings->slv_addr == 0) - return false; - if (settings->reg_num > 9) - return false; - if (settings->reg_num_6g > 3) - return false; + switch (eng_id) { + case ENGINE_ID_DIGA: + *settings = create_ext_hdmi_settings( + info->dp0_ext_hdmi_slv_addr, + info->dp0_ext_hdmi_reg_num, + info->dp0_ext_hdmi_6g_reg_num, + info->dp0_ext_hdmi_reg_settings, + info->dp0_ext_hdmi_6g_reg_settings + ); + break; + case ENGINE_ID_DIGB: + *settings = create_ext_hdmi_settings( + info->dp1_ext_hdmi_slv_addr, + info->dp1_ext_hdmi_reg_num, + info->dp1_ext_hdmi_6g_reg_num, + info->dp1_ext_hdmi_reg_settings, + info->dp1_ext_hdmi_6g_reg_settings + ); + break; + case ENGINE_ID_DIGC: + *settings = create_ext_hdmi_settings( + info->dp2_ext_hdmi_slv_addr, + info->dp2_ext_hdmi_reg_num, + info->dp2_ext_hdmi_6g_reg_num, + info->dp2_ext_hdmi_reg_settings, + info->dp2_ext_hdmi_6g_reg_settings + ); + break; + case ENGINE_ID_DIGD: + *settings = create_ext_hdmi_settings( + info->dp3_ext_hdmi_slv_addr, + info->dp3_ext_hdmi_reg_num, + info->dp3_ext_hdmi_6g_reg_num, + info->dp3_ext_hdmi_reg_settings, + info->dp3_ext_hdmi_6g_reg_settings + ); + break; + default: + return false; + } - for (i = 0; i < settings->reg_num; i++) { - if (settings->reg_settings[i].i2c_reg_index > 0x20) - return false; - } + // Validate settings from bios integrated info table + if ( + !settings->slv_addr + || settings->reg_num > ARRAY_SIZE(settings->reg_settings) + || settings->reg_num_6g > ARRAY_SIZE(settings->reg_settings_6g) + ) { + return false; + } - for (i = 0; i < settings->reg_num_6g; i++) { - if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) - return false; - } - } + for (size_t i = 0; i < settings->reg_num; i++) { + if (settings->reg_settings[i].i2c_reg_index > 0x20) + return false; } - return result; + for (size_t i = 0; i < settings->reg_num_6g; i++) { + if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) + return false; + } + return true; } static bool write_i2c( @@ -1792,7 +1795,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) /* DP159, Retimer settings */ eng_id = pipe_ctx->stream_res.stream_enc->id; - if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { + if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) { write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings); } else { write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz); @@ -2209,7 +2212,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) false); if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { /* DP159, Retimer settings */ - if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) + if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) write_i2c_retimer_setting(link, false, false, &settings); else write_i2c_default_retimer_setting(link, false, false); From a39e9474644b9525b9b77db298856421180a0337 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 5 Feb 2026 20:28:49 -0500 Subject: [PATCH 0195/2070] drm/amd/display: Correct logic check error for fastboot [Why] Fix fastboot broken in driver. This is caused by an open source backport change 7495962c. from the comment, the intended check is to disable fastboot for pre-DCN10. but the logic check is reversed, and causes fastboot to be disabled on all DCN10 and after. fastboot is for driver trying to pick up bios used hw setting and bypass reprogramming the hw if dc_validate_boot_timing() condition meets. Fixes: 7495962cbceb9 ("drm/amd/display: Disable fastboot on DCE 6 too") Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello Reviewed-by: Ovidiu Bunea Signed-off-by: Charlene Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 4659e1b489ba3..4277b6761522d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1964,8 +1964,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) get_edp_streams(context, edp_streams, &edp_stream_num); - /* Check fastboot support, disable on DCE 6-8 because of blank screens */ - if (edp_num && edp_stream_num && dc->ctx->dce_version < DCE_VERSION_10_0) { + /* Check fastboot support, disable on DCE 6-8-10 because of blank screens */ + if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) { for (i = 0; i < edp_num; i++) { edp_link = edp_links[i]; if (edp_link != edp_streams[0]->link) From ed2f59871f9c91a1bbd48c953defc34962392758 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Thu, 5 Feb 2026 22:54:27 -0700 Subject: [PATCH 0196/2070] drm/amd/display: Check return of shaper curve to HW format [Why & How] Check return of cm3_helper_translate_curve_to_hw_format. This is reported as a CHECKED_RETURN error by Coverity. Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Hung Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 2767d3a97812e..a0aaa727e9fa3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -486,7 +486,7 @@ bool dcn32_set_mcm_luts( struct dpp *dpp_base = pipe_ctx->plane_res.dpp; int mpcc_id = pipe_ctx->plane_res.hubp->inst; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; - bool result = true; + bool rval, result; const struct pwl_params *lut_params = NULL; // 1D LUT @@ -509,10 +509,10 @@ bool dcn32_set_mcm_luts( lut_params = &plane_state->in_shaper_func.pwl; else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { // TODO: dpp_base replace - cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, &plane_state->in_shaper_func, &dpp_base->shaper_params, true); - lut_params = &dpp_base->shaper_params; + lut_params = rval ? &dpp_base->shaper_params : NULL; } mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); From 450c6c28e7a7faad7c76a9e1684bb4a8b1bbe9c2 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 4 Feb 2026 22:05:16 -0700 Subject: [PATCH 0197/2070] drm/amd/display: Remove conditional for shaper 3DLUT power-on [Why] Shaper programming has high chance to fail on first time after power-on or reboot. This can be verified by running IGT's kms_colorop. [How] Always power on the shaper and 3DLUT before programming by removing the debug flag of low power mode. Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Hung Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c index 83bbbf34bcac7..badcef027b846 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c @@ -724,8 +724,7 @@ bool mpc32_program_shaper( return false; } - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); current_mode = mpc32_get_shaper_current(mpc, mpcc_id); From 3fd1249bf787fdaba0c4388af283c556256e4a3c Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 6 Feb 2026 18:06:54 -0500 Subject: [PATCH 0198/2070] drm/amd/display: Promote DC to 3.2.370 This version brings along the following updates: - Add static keyword for sharpness tables. - Refactor fams2 calculations. - Add gpuvm and hvm params to dml21. - Expose functions of other dcn use. - Disable SR feature on eDP1 by default. - Implement ramless idle mouse trigger. - Migrate DCCG register access from hwseq to dccg component. - Revert "Add Handling for gfxversion DcGfxBase". - Revert changes to Gfx Linear Tiling handling. - Skip eDP detection when no sink. - Refactor and fix link_dpms I2C. - Refactor and fix link_dpms info. - Correct logic check error for fast boot. - Check return of shaper curve to HW format. - Remove conditional for shaper 3DLUT power-on. Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4c4239cac863d..71f2812acf599 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.369" +#define DC_VER "3.2.370" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 4e947e162672aa4ea028e406419a8ad1cbdfc0cc Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Tue, 10 Feb 2026 20:25:05 +0530 Subject: [PATCH 0199/2070] drm/amdgpu: Make amdgpu_fence_emit() non-failing v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dma_fence_wait(old, false) is not interruptible and cannot return an error. Drop the unreachable error handling in amdgpu_fence_emit(). Since the function can no longer fail, convert amdgpu_fence_emit() to return void and remove return value handling from all callers. v2: - Add comment explaining why dma_fence_wait(..., false) return value is ignored (Alex) Suggested-by: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 17 ++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 ++----- 4 files changed, 13 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 1054d66c54fac..07568516c5066 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -107,16 +107,14 @@ static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af) * @flags: flags to pass into the subordinate .emit_fence() call * * Emits a fence command on the requested ring (all asics). - * Returns 0 on success, -ENOMEM on failure. */ -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, - unsigned int flags) +void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, + unsigned int flags) { struct amdgpu_device *adev = ring->adev; struct dma_fence *fence; struct dma_fence __rcu **ptr; uint32_t seq; - int r; fence = &af->base; af->ring = ring; @@ -141,10 +139,13 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, rcu_read_unlock(); if (old) { - r = dma_fence_wait(old, false); + /* + * dma_fence_wait(old, false) is not interruptible. + * It will not return an error in this case. + * So we can safely ignore the return value. + */ + dma_fence_wait(old, false); dma_fence_put(old); - if (r) - return r; } } @@ -154,8 +155,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, * emitting the fence would mess up the hardware ring buffer. */ rcu_assign_pointer(*ptr, dma_fence_get(fence)); - - return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 031a7d77daa7a..be63779a268ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -297,14 +297,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); } - r = amdgpu_fence_emit(ring, af, fence_flags); - if (r) { - dev_err(adev->dev, "failed to emit fence (%d)\n", r); - if (job && job->vmid) - amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid); - amdgpu_ring_undo(ring); - goto free_fence; - } + amdgpu_fence_emit(ring, af, fence_flags); *f = &af->base; /* get a ref for the job */ if (job) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 1abd8fdb5cef6..5a82db0888f0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -172,8 +172,8 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, - unsigned int flags); +void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, + unsigned int flags); int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, uint32_t timeout); bool amdgpu_fence_process(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index baa3823629390..c0b759d633195 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -783,8 +783,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool cleaner_shader_needed = false; bool pasid_mapping_needed = false; struct dma_fence *fence = NULL; - unsigned int patch; - int r; + unsigned int patch = 0; if (amdgpu_vmid_had_gpu_reset(adev, id)) { gds_switch_needed = true; @@ -856,9 +855,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, } if (vm_flush_needed || pasid_mapping_needed || cleaner_shader_needed) { - r = amdgpu_fence_emit(ring, job->hw_vm_fence, 0); - if (r) - return r; + amdgpu_fence_emit(ring, job->hw_vm_fence, 0); fence = &job->hw_vm_fence->base; /* get a ref for the job */ dma_fence_get(fence); From 294f4e90c09c13c706e11828c34afa468a41433f Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 12 Feb 2026 21:30:50 +0530 Subject: [PATCH 0200/2070] drm/amdgpu: Make amdgpu_vm_flush() non-failing in submission path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_vm_flush() is used during job submission and is not expected to fail. Convert it to return void and simplify the caller. Initialize the COND_EXEC patch location to 0 so it is safe to call amdgpu_ring_patch_cond_exec() when init_cond_exec is not supported. Suggested-by: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher Change-Id: Ic40847763329c6a04728d24f4da9282f9d77b2bc --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 ++------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +++------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index be63779a268ca..eb92c96d290b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -215,13 +215,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, dma_fence_put(tmp); } - if (job) { - r = amdgpu_vm_flush(ring, job, need_pipe_sync); - if (r) { - amdgpu_ring_undo(ring); - goto free_fence; - } - } + if (job) + amdgpu_vm_flush(ring, job, need_pipe_sync); amdgpu_ring_ib_begin(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index c0b759d633195..57f87ce5e9297 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -764,12 +764,9 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, * @need_pipe_sync: is pipe sync needed * * Emit a VM flush when it is necessary. - * - * Returns: - * 0 on success, errno otherwise. */ -int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, - bool need_pipe_sync) +void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, + bool need_pipe_sync) { struct amdgpu_device *adev = ring->adev; struct amdgpu_isolation *isolation = &adev->isolation[ring->xcp_id]; @@ -811,7 +808,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync && !cleaner_shader_needed) - return 0; + return; amdgpu_ring_ib_begin(ring); @@ -900,7 +897,6 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, } amdgpu_ring_ib_end(ring); - return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 139642eacdd0c..322193b97d3cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -512,7 +512,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket, int (*callback)(void *p, struct amdgpu_bo *bo), void *param); -int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); +void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); int amdgpu_vm_update_pdes(struct amdgpu_device *adev, struct amdgpu_vm *vm, bool immediate); int amdgpu_vm_clear_freed(struct amdgpu_device *adev, From 31eb0603d171af3208b48a57729ec3e96d79e15c Mon Sep 17 00:00:00 2001 From: Andrew Martin Date: Mon, 2 Feb 2026 05:42:44 -0500 Subject: [PATCH 0201/2070] drm/amdkfd: Disable MQD queue priority This solves a priority inversion issue, caused by the language runtime making high-priority queues wait for activity on lower-priority queues. Signed-off-by: Andrew Martin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 90ac3a30e81d2..76483d91af98b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -70,7 +70,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct cik_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 97055f808d4a1..0186b3de67c00 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -70,7 +70,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 7e5a7ab6d0c01..c9e3973667824 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -96,7 +96,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index a51f217329db0..3bbc2648f51d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -77,7 +77,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index d0776ba2cc999..0d6b601962eb9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -131,7 +131,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 5578c241b7d0a..3622d8392cb32 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -106,7 +106,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v9_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static bool mqd_on_vram(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 09483f0862d41..e63ef6442b358 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -73,7 +73,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct vi_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; + /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, From d75c16260a5d3c4a60f164ca63d757e8ea2b9420 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 18:18:39 -0500 Subject: [PATCH 0202/2070] drm/amd/display: Add dcn42 version identifiers Add DCN 4.2 asic version identifiers. Signed-off-by: Roman Li Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 + drivers/gpu/drm/amd/display/include/dal_types.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 8aea50aa95330..92510af1bd653 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -252,6 +252,7 @@ enum { #define AMDGPU_FAMILY_GC_11_0_0 145 #define AMDGPU_FAMILY_GC_11_0_1 148 #define AMDGPU_FAMILY_GC_11_5_0 150 +#define AMDGPU_FAMILY_GC_11_5_4 154 #define GC_11_0_0_A0 0x1 #define GC_11_0_2_A0 0x10 #define GC_11_0_3_A0 0x20 diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index a021d12acd741..d30eb24cf11e3 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -65,6 +65,7 @@ enum dce_version { DCN_VERSION_3_51, DCN_VERSION_3_6, DCN_VERSION_4_01, + DCN_VERSION_4_2, DCN_VERSION_MAX }; From 99cdf56fe262eef1f81055cb83c8992258f3a98d Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 30 Jan 2026 15:31:14 -0500 Subject: [PATCH 0203/2070] drm/amdgpu: : Set vmid0 PAGE_TABLE_DEPTH for GFX12.1 GFX12.1 uses 2 level gart table. Set the context register appropriately Signed-off-by: Feifei Xu Signed-off-by: Harish Kasiviswanathan Reviewed-by: Mukul Joshi --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index 7e917eb47a8c1..a72770e3d0e99 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -395,7 +395,10 @@ static void mmhub_v4_2_0_mid_enable_system_domain(struct amdgpu_device *adev, tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, - PAGE_TABLE_DEPTH, 0); + PAGE_TABLE_DEPTH, adev->gmc.vmid0_page_table_depth); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, + PAGE_TABLE_BLOCK_SIZE, + adev->gmc.vmid0_page_table_block_size); tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), From cdbff676e1c807ff003458a394ab137f27243bc2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 18 Jan 2026 18:31:46 +0100 Subject: [PATCH 0204/2070] drm/amd/display: Use dce_audio_create for DCE 6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The only difference between DCE 6 and other DCE versions is that DCE 6 doesn't support DCCG_AUDIO_DTO2_USE_512FBR_DTO. Recently a check was added to dce_aud_wall_dto_setup() to check that. So now DCE 6 can just use dce_aud_wall_dto_setup() just like other DCE versions. Clean up DCE 6 specific audio functions which were otherwise identical to the rest. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/dce/dce_audio.c | 131 ------------------ .../gpu/drm/amd/display/dc/dce/dce_audio.h | 9 -- .../dc/resource/dce60/dce60_resource.c | 2 +- 3 files changed, 1 insertion(+), 141 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index fcad61c618a1a..1276f19164b38 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -1150,98 +1150,6 @@ void dce_aud_wall_dto_setup( } } -#if defined(CONFIG_DRM_AMD_DC_SI) -static void dce60_aud_wall_dto_setup( - struct audio *audio, - enum signal_type signal, - const struct audio_crtc_info *crtc_info, - const struct audio_pll_info *pll_info) -{ - struct dce_audio *aud = DCE_AUD(audio); - - struct azalia_clock_info clock_info = { 0 }; - - if (dc_is_hdmi_signal(signal)) { - uint32_t src_sel; - - /*DTO0 Programming goal: - -generate 24MHz, 128*Fs from 24MHz - -use DTO0 when an active HDMI port is connected - (optionally a DP is connected) */ - - /* calculate DTO settings */ - get_azalia_clock_info_hdmi( - crtc_info->requested_pixel_clock_100Hz, - crtc_info->calculated_pixel_clock_100Hz, - &clock_info); - - DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ - "calculated_pixel_clock_100Hz =%d\n"\ - "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ - crtc_info->requested_pixel_clock_100Hz,\ - crtc_info->calculated_pixel_clock_100Hz,\ - clock_info.audio_dto_module,\ - clock_info.audio_dto_phase); - - /* On TN/SI, Program DTO source select and DTO select before - programming DTO modulo and DTO phase. These bits must be - programmed first, otherwise there will be no HDMI audio at boot - up. This is a HW sequence change (different from old ASICs). - Caution when changing this programming sequence. - - HDMI enabled, using DTO0 - program master CRTC for DTO0 */ - src_sel = pll_info->dto_source - DTO_SOURCE_ID0; - REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, - DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, - DCCG_AUDIO_DTO_SEL, 0); - - /* module */ - REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, - DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); - - /* phase */ - REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, - DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); - } else { - /*DTO1 Programming goal: - -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs) - -default is to used DTO1, and switch to DTO0 when an audio - master HDMI port is connected - -use as default for DP - - calculate DTO settings */ - get_azalia_clock_info_dp( - crtc_info->requested_pixel_clock_100Hz, - pll_info, - &clock_info); - - /* Program DTO select before programming DTO modulo and DTO - phase. default to use DTO1 */ - - REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, - DCCG_AUDIO_DTO_SEL, 1); - - /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) - * Cannot select 512fs for DP - * - * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask - */ - - /* module */ - REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, - DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); - - /* phase */ - REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, - DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); - - /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */ - - } -} -#endif - static bool dce_aud_endpoint_valid(struct audio *audio) { uint32_t value; @@ -1303,18 +1211,6 @@ static const struct audio_funcs funcs = { .destroy = dce_aud_destroy, }; -#if defined(CONFIG_DRM_AMD_DC_SI) -static const struct audio_funcs dce60_funcs = { - .endpoint_valid = dce_aud_endpoint_valid, - .hw_init = dce_aud_hw_init, - .wall_dto_setup = dce60_aud_wall_dto_setup, - .az_enable = dce_aud_az_enable, - .az_disable = dce_aud_az_disable, - .az_configure = dce_aud_az_configure, - .destroy = dce_aud_destroy, -}; -#endif - void dce_aud_destroy(struct audio **audio) { struct dce_audio *aud = DCE_AUD(*audio); @@ -1347,30 +1243,3 @@ struct audio *dce_audio_create( audio->masks = masks; return &audio->base; } - -#if defined(CONFIG_DRM_AMD_DC_SI) -struct audio *dce60_audio_create( - struct dc_context *ctx, - unsigned int inst, - const struct dce_audio_registers *reg, - const struct dce_audio_shift *shifts, - const struct dce_audio_mask *masks - ) -{ - struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); - - if (audio == NULL) { - ASSERT_CRITICAL(audio); - return NULL; - } - - audio->base.ctx = ctx; - audio->base.inst = inst; - audio->base.funcs = &dce60_funcs; - - audio->regs = reg; - audio->shifts = shifts; - audio->masks = masks; - return &audio->base; -} -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h index 1b7b8b079af44..3f1d161a0045a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h @@ -151,15 +151,6 @@ struct audio *dce_audio_create( const struct dce_audio_shift *shifts, const struct dce_audio_mask *masks); -#if defined(CONFIG_DRM_AMD_DC_SI) -struct audio *dce60_audio_create( - struct dc_context *ctx, - unsigned int inst, - const struct dce_audio_registers *reg, - const struct dce_audio_shift *shifts, - const struct dce_audio_mask *masks); -#endif - void dce_aud_destroy(struct audio **audio); void dce_aud_hw_init(struct audio *audio); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index f0152933bee2c..e0fbb08e69854 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -495,7 +495,7 @@ static void read_dce_straps( static struct audio *create_audio( struct dc_context *ctx, unsigned int inst) { - return dce60_audio_create(ctx, inst, + return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); } From 8fd0fc5a45dfb7a24c71096fa1dfa666dc61da06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 18 Jan 2026 18:31:47 +0100 Subject: [PATCH 0205/2070] drm/amd/display: Delete unused dce_clk_mgr.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This file was not compiled or included anywhere and not modified for years. And it has duplicate function definitions of many functions that are defined in other files. That leads to a lot of confusion (for both developers and for code editors), eg. when searching for a definition of a function it can end up on one of the functions in this file instead of the real implementations. I suspect that it was forgotten that this should be deleted after the various clock manager functions were split into hardware generation specific files. Delete it now. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 967 ------------------ 1 file changed, 967 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c deleted file mode 100644 index e7acd6eec1fd6..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +++ /dev/null @@ -1,967 +0,0 @@ -/* - * Copyright 2012-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include - -#include "dce_clk_mgr.h" - -#include "reg_helper.h" -#include "dmcu.h" -#include "core_types.h" -#include "dal_asic_id.h" - -#define TO_DCE_CLK_MGR(clocks)\ - container_of(clocks, struct dce_clk_mgr, base) - -#define REG(reg) \ - (clk_mgr_dce->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name - -#define CTX \ - clk_mgr_dce->base.ctx -#define DC_LOGGER \ - clk_mgr->ctx->logger - -/* Max clock values for each state indexed by "enum clocks_state": */ -static const struct state_dependent_clocks dce80_max_clks_by_state[] = { -/* ClocksStateInvalid - should not be used */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateLow */ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, -/* ClocksStateNominal */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, -/* ClocksStatePerformance */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; - -static const struct state_dependent_clocks dce110_max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; - -static const struct state_dependent_clocks dce112_max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; - -static const struct state_dependent_clocks dce120_max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; - -int dentist_get_divider_from_did(int did) -{ - if (did < DENTIST_BASE_DID_1) - did = DENTIST_BASE_DID_1; - if (did > DENTIST_MAX_DID) - did = DENTIST_MAX_DID; - - if (did < DENTIST_BASE_DID_2) { - return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP - * (did - DENTIST_BASE_DID_1); - } else if (did < DENTIST_BASE_DID_3) { - return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP - * (did - DENTIST_BASE_DID_2); - } else if (did < DENTIST_BASE_DID_4) { - return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP - * (did - DENTIST_BASE_DID_3); - } else { - return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP - * (did - DENTIST_BASE_DID_4); - } -} - -/* SW will adjust DP REF Clock average value for all purposes - * (DP DTO / DP Audio DTO and DP GTC) - if clock is spread for all cases: - -if SS enabled on DP Ref clock and HW de-spreading enabled with SW - calculations for DS_INCR/DS_MODULO (this is planned to be default case) - -if SS enabled on DP Ref clock and HW de-spreading enabled with HW - calculations (not planned to be used, but average clock should still - be valid) - -if SS enabled on DP Ref clock and HW de-spreading disabled - (should not be case with CIK) then SW should program all rates - generated according to average value (case as with previous ASICs) - */ -static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz) -{ - if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { - struct fixed31_32 ss_percentage = dc_fixpt_div_int( - dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage, - clk_mgr_dce->dprefclk_ss_divider), 200); - struct fixed31_32 adj_dp_ref_clk_khz; - - ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage); - adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz); - dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz); - } - return dp_ref_clk_khz; -} - -static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - int dprefclk_wdivider; - int dprefclk_src_sel; - int dp_ref_clk_khz = 600000; - int target_div; - - /* ASSERT DP Reference Clock source is from DFS*/ - REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); - ASSERT(dprefclk_src_sel == 0); - - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ - REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); - - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ - target_div = dentist_get_divider_from_did(dprefclk_wdivider); - - /* Calculate the current DFS clock, in kHz.*/ - dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr_dce->dentist_vco_freq_khz) / target_div; - - return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz); -} - -int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - - return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); -} - -/* unit: in_khz before mode set, get pixel clock from context. ASIC register - * may not be programmed yet - */ -static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context) -{ - uint32_t max_pix_clk = 0; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (pipe_ctx->stream == NULL) - continue; - - /* do not check under lay */ - if (pipe_ctx->top_pipe) - continue; - - if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; - - /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS - * logic for HBR3 still needs Nominal (0.8V) on VDDC rail - */ - if (dc_is_dp_signal(pipe_ctx->stream->signal) && - pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; - } - - return max_pix_clk; -} - -static enum dm_pp_clocks_state dce_get_required_clocks_state( - struct clk_mgr *clk_mgr, - struct dc_state *context) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - int i; - enum dm_pp_clocks_state low_req_clk; - int max_pix_clk = get_max_pixel_clock_for_all_paths(context); - - /* Iterate from highest supported to lowest valid state, and update - * lowest RequiredState with the lowest state that satisfies - * all required clocks - */ - for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) - if (context->bw_ctx.bw.dce.dispclk_khz > - clk_mgr_dce->max_clks_by_state[i].display_clk_khz - || max_pix_clk > - clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz) - break; - - low_req_clk = i + 1; - if (low_req_clk > clk_mgr_dce->max_clks_state) { - /* set max clock state for high phyclock, invalid on exceeding display clock */ - if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz - < context->bw_ctx.bw.dce.dispclk_khz) - low_req_clk = DM_PP_CLOCKS_STATE_INVALID; - else - low_req_clk = clk_mgr_dce->max_clks_state; - } - - return low_req_clk; -} - -static int dce_set_clock( - struct clk_mgr *clk_mgr, - int requested_clk_khz) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct bp_pixel_clock_parameters pxl_clk_params = { 0 }; - struct dc_bios *bp = clk_mgr->ctx->dc_bios; - int actual_clock = requested_clk_khz; - struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; - - /* Make sure requested clock isn't lower than minimum threshold*/ - if (requested_clk_khz > 0) - requested_clk_khz = max(requested_clk_khz, - clk_mgr_dce->dentist_vco_freq_khz / 64); - - /* Prepare to program display clock*/ - pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10; - pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; - - if (clk_mgr_dce->dfs_bypass_active) - pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true; - - bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); - - if (clk_mgr_dce->dfs_bypass_active) { - /* Cache the fixed display clock*/ - clk_mgr_dce->dfs_bypass_disp_clk = - pxl_clk_params.dfs_bypass_display_clock; - actual_clock = pxl_clk_params.dfs_bypass_display_clock; - } - - /* from power down, we need mark the clock state as ClocksStateNominal - * from HWReset, so when resume we will call pplib voltage regulator.*/ - if (requested_clk_khz == 0) - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - - if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) - dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7); - - return actual_clock; -} - -int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct bp_set_dce_clock_parameters dce_clk_params; - struct dc_bios *bp = clk_mgr->ctx->dc_bios; - struct dc *core_dc = clk_mgr->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - int actual_clock = requested_clk_khz; - /* Prepare to program display clock*/ - memset(&dce_clk_params, 0, sizeof(dce_clk_params)); - - /* Make sure requested clock isn't lower than minimum threshold*/ - if (requested_clk_khz > 0) - requested_clk_khz = max(requested_clk_khz, - clk_mgr_dce->dentist_vco_freq_khz / 62); - - dce_clk_params.target_clock_frequency = requested_clk_khz; - dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; - dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; - - bp->funcs->set_dce_clock(bp, &dce_clk_params); - actual_clock = dce_clk_params.target_clock_frequency; - - /* from power down, we need mark the clock state as ClocksStateNominal - * from HWReset, so when resume we will call pplib voltage regulator.*/ - if (requested_clk_khz == 0) - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - - /*Program DP ref Clock*/ - /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ - dce_clk_params.target_clock_frequency = 0; - dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; - - if (!((clk_mgr->ctx->asic_id.chip_family == FAMILY_AI) && - ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))) - dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = - (dce_clk_params.pll_id == - CLOCK_SOURCE_COMBO_DISPLAY_PLL0); - else - dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; - - bp->funcs->set_dce_clock(bp, &dce_clk_params); - - if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { - if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { - if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) - dmcu->funcs->set_psr_wait_loop(dmcu, - actual_clock / 1000 / 7); - } - } - - clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; - return actual_clock; -} - -static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce) -{ - struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - struct integrated_info info = { { { 0 } } }; - struct dc_firmware_info fw_info = { { 0 } }; - int i; - - if (bp->integrated_info) - info = *bp->integrated_info; - - clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq; - if (clk_mgr_dce->dentist_vco_freq_khz == 0) { - bp->funcs->get_firmware_info(bp, &fw_info); - clk_mgr_dce->dentist_vco_freq_khz = - fw_info.smu_gpu_pll_output_freq; - if (clk_mgr_dce->dentist_vco_freq_khz == 0) - clk_mgr_dce->dentist_vco_freq_khz = 3600000; - } - - /*update the maximum display clock for each power state*/ - for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; - - switch (i) { - case 0: - clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; - break; - - case 1: - clk_state = DM_PP_CLOCKS_STATE_LOW; - break; - - case 2: - clk_state = DM_PP_CLOCKS_STATE_NOMINAL; - break; - - case 3: - clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; - break; - - default: - clk_state = DM_PP_CLOCKS_STATE_INVALID; - break; - } - - /*Do not allow bad VBIOS/SBIOS to override with invalid values, - * check for > 100MHz*/ - if (info.disp_clk_voltage[i].max_supported_clk >= 100000) - clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = - info.disp_clk_voltage[i].max_supported_clk; - } - - if (!debug->disable_dfs_bypass && bp->integrated_info) - if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) - clk_mgr_dce->dfs_bypass_enabled = true; -} - -void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce) -{ - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - int ss_info_num = bp->funcs->get_ss_entry_number( - bp, AS_SIGNAL_TYPE_GPU_PLL); - - if (ss_info_num) { - struct spread_spectrum_info info = { { 0 } }; - enum bp_result result = bp->funcs->get_spread_spectrum_info( - bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info); - - /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS - * even if SS not enabled and in that case - * SSInfo.spreadSpectrumPercentage !=0 would be sign - * that SS is enabled - */ - if (result == BP_RESULT_OK && - info.spread_spectrum_percentage != 0) { - clk_mgr_dce->ss_on_dprefclk = true; - clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* TODO: Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - clk_mgr_dce->dprefclk_ss_percentage = - info.spread_spectrum_percentage; - } - - return; - } - - result = bp->funcs->get_spread_spectrum_info( - bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info); - - /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS - * even if SS not enabled and in that case - * SSInfo.spreadSpectrumPercentage !=0 would be sign - * that SS is enabled - */ - if (result == BP_RESULT_OK && - info.spread_spectrum_percentage != 0) { - clk_mgr_dce->ss_on_dprefclk = true; - clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - clk_mgr_dce->dprefclk_ss_percentage = - info.spread_spectrum_percentage; - } - if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss) - clk_mgr_dce->dprefclk_ss_percentage = 0; - } - } -} - -/** - * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info - * @clk_mgr: clock manager base structure - * - * Reads from VBIOS the XGMI spread spectrum info and saves it within - * the dce clock manager. This operation will overwrite the existing dprefclk - * SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also - * sets the ->xgmi_enabled flag. - */ -void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - enum bp_result result; - struct spread_spectrum_info info = { { 0 } }; - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - - clk_mgr_dce->xgmi_enabled = false; - - result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI, - 0, &info); - if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) { - clk_mgr_dce->xgmi_enabled = true; - clk_mgr_dce->ss_on_dprefclk = true; - clk_mgr_dce->dprefclk_ss_divider = - info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - clk_mgr_dce->dprefclk_ss_percentage = - info.spread_spectrum_percentage; - } - } -} - -void dce110_fill_display_configs( - const struct dc_state *context, - struct dm_pp_display_configuration *pp_display_cfg) -{ - int j; - int num_cfgs = 0; - - for (j = 0; j < context->stream_count; j++) { - int k; - - const struct dc_stream_state *stream = context->streams[j]; - struct dm_pp_single_disp_config *cfg = - &pp_display_cfg->disp_configs[num_cfgs]; - const struct pipe_ctx *pipe_ctx = NULL; - - for (k = 0; k < MAX_PIPES; k++) - if (stream == context->res_ctx.pipe_ctx[k].stream) { - pipe_ctx = &context->res_ctx.pipe_ctx[k]; - break; - } - - ASSERT(pipe_ctx != NULL); - - /* only notify active stream */ - if (stream->dpms_off) - continue; - - num_cfgs++; - cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; - cfg->src_height = stream->src.height; - cfg->src_width = stream->src.width; - cfg->ddi_channel_mapping = - stream->link->ddi_channel_mapping.raw; - cfg->transmitter = - stream->link->link_enc->transmitter; - cfg->link_settings.lane_count = - stream->link->cur_link_settings.lane_count; - cfg->link_settings.link_rate = - stream->link->cur_link_settings.link_rate; - cfg->link_settings.link_spread = - stream->link->cur_link_settings.link_spread; - cfg->sym_clock = stream->phy_pix_clk; - /* Round v_refresh*/ - cfg->v_refresh = stream->timing.pix_clk_100hz * 100; - cfg->v_refresh /= stream->timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) - / stream->timing.v_total; - } - - pp_display_cfg->display_count = num_cfgs; -} - -static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) -{ - uint8_t j; - uint32_t min_vertical_blank_time = -1; - - for (j = 0; j < context->stream_count; j++) { - struct dc_stream_state *stream = context->streams[j]; - uint32_t vertical_blank_in_pixels = 0; - uint32_t vertical_blank_time = 0; - - vertical_blank_in_pixels = stream->timing.h_total * - (stream->timing.v_total - - stream->timing.v_addressable); - - vertical_blank_time = vertical_blank_in_pixels - * 10000 / stream->timing.pix_clk_100hz; - - if (min_vertical_blank_time > vertical_blank_time) - min_vertical_blank_time = vertical_blank_time; - } - - return min_vertical_blank_time; -} - -static int determine_sclk_from_bounding_box( - const struct dc *dc, - int required_sclk) -{ - int i; - - /* - * Some asics do not give us sclk levels, so we just report the actual - * required sclk - */ - if (dc->sclk_lvls.num_levels == 0) - return required_sclk; - - for (i = 0; i < dc->sclk_lvls.num_levels; i++) { - if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) - return dc->sclk_lvls.clocks_in_khz[i]; - } - /* - * even maximum level could not satisfy requirement, this - * is unexpected at this stage, should have been caught at - * validation time - */ - ASSERT(0); - return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; -} - -static void dce_pplib_apply_display_requirements( - struct dc *dc, - struct dc_state *context) -{ - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - - pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); - - dce110_fill_display_configs(context, pp_display_cfg); - - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); -} - -static void dce11_pplib_apply_display_requirements( - struct dc *dc, - struct dc_state *context) -{ - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - - pp_display_cfg->all_displays_in_sync = - context->bw_ctx.bw.dce.all_displays_in_sync; - pp_display_cfg->nb_pstate_switch_disable = - context->bw_ctx.bw.dce.nbp_state_change_enable == false; - pp_display_cfg->cpu_cc6_disable = - context->bw_ctx.bw.dce.cpuc_state_change_enable == false; - pp_display_cfg->cpu_pstate_disable = - context->bw_ctx.bw.dce.cpup_state_change_enable == false; - pp_display_cfg->cpu_pstate_separation_time = - context->bw_ctx.bw.dce.blackout_recovery_time_us; - - pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz - / MEMORY_TYPE_MULTIPLIER_CZ; - - pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( - dc, - context->bw_ctx.bw.dce.sclk_khz); - - /* - * As workaround for >4x4K lightup set dcfclock to min_engine_clock value. - * This is not required for less than 5 displays, - * thus don't request decfclk in dc to avoid impact - * on power saving. - * - */ - pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ? - pp_display_cfg->min_engine_clock_khz : 0; - - pp_display_cfg->min_engine_clock_deep_sleep_khz - = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; - - pp_display_cfg->avail_mclk_switch_time_us = - dce110_get_min_vblank_time_us(context); - /* TODO: dce11.2*/ - pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - - pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; - - dce110_fill_display_configs(context, pp_display_cfg); - - /* TODO: is this still applicable?*/ - if (pp_display_cfg->display_count == 1) { - const struct dc_crtc_timing *timing = - &context->streams[0]->timing; - - pp_display_cfg->crtc_index = - pp_display_cfg->disp_configs[0].pipe_idx; - pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; - } - - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); -} - -static void dce_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk); - clk_mgr->clks.dispclk_khz = patched_disp_clk; - } - dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static void dce11_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk); - clk_mgr->clks.dispclk_khz = patched_disp_clk; - } - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static void dce112_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk); - clk_mgr->clks.dispclk_khz = patched_disp_clk; - } - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static void dce12_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; - int max_pix_clk = get_max_pixel_clock_for_all_paths(context); - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; - /* - * When xGMI is enabled, the display clk needs to be adjusted - * with the WAFL link's SS percentage. - */ - if (clk_mgr_dce->xgmi_enabled) - patched_disp_clk = clk_mgr_adjust_dp_ref_freq_for_ss( - clk_mgr_dce, patched_disp_clk); - clock_voltage_req.clocks_in_khz = patched_disp_clk; - clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk); - - dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req); - } - - if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; - clock_voltage_req.clocks_in_khz = max_pix_clk; - clk_mgr->clks.phyclk_khz = max_pix_clk; - - dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req); - } - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static const struct clk_mgr_funcs dce120_funcs = { - .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, - .update_clocks = dce12_update_clocks -}; - -static const struct clk_mgr_funcs dce112_funcs = { - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, - .update_clocks = dce112_update_clocks -}; - -static const struct clk_mgr_funcs dce110_funcs = { - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, - .update_clocks = dce11_update_clocks, -}; - -static const struct clk_mgr_funcs dce_funcs = { - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, - .update_clocks = dce_update_clocks -}; - -static void dce_clk_mgr_construct( - struct dce_clk_mgr *clk_mgr_dce, - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct clk_mgr *base = &clk_mgr_dce->base; - struct dm_pp_static_clock_info static_clk_info = {0}; - - base->ctx = ctx; - base->funcs = &dce_funcs; - - clk_mgr_dce->regs = regs; - clk_mgr_dce->clk_mgr_shift = clk_shift; - clk_mgr_dce->clk_mgr_mask = clk_mask; - - clk_mgr_dce->dfs_bypass_disp_clk = 0; - - clk_mgr_dce->dprefclk_ss_percentage = 0; - clk_mgr_dce->dprefclk_ss_divider = 1000; - clk_mgr_dce->ss_on_dprefclk = false; - - - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) - clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state; - else - clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; - - dce_clock_read_integrated_info(clk_mgr_dce); - dce_clock_read_ss_info(clk_mgr_dce); -} - -struct clk_mgr *dce_clk_mgr_create( - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce80_max_clks_by_state, - sizeof(dce80_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, regs, clk_shift, clk_mask); - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce110_clk_mgr_create( - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce110_max_clks_by_state, - sizeof(dce110_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, regs, clk_shift, clk_mask); - - clk_mgr_dce->base.funcs = &dce110_funcs; - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce112_clk_mgr_create( - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce112_max_clks_by_state, - sizeof(dce112_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, regs, clk_shift, clk_mask); - - clk_mgr_dce->base.funcs = &dce112_funcs; - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce120_max_clks_by_state, - sizeof(dce120_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, NULL, NULL, NULL); - - clk_mgr_dce->dprefclk_khz = 600000; - clk_mgr_dce->base.funcs = &dce120_funcs; - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), - GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state, - sizeof(dce120_max_clks_by_state)); - - dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL); - - clk_mgr_dce->dprefclk_khz = 625000; - clk_mgr_dce->base.funcs = &dce120_funcs; - - return &clk_mgr_dce->base; -} - -void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr); - - kfree(clk_mgr_dce); - *clk_mgr = NULL; -} From be3072105dad868243a0f917df7c2da0f0369463 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 18 Jan 2026 18:31:48 +0100 Subject: [PATCH 0206/2070] drm/amd/display: Remove unused dce60_clk_mgr register definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It turned out that these were actually not necessary. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 30 ++----------------- .../amd/display/dc/inc/hw/clk_mgr_internal.h | 11 ------- 2 files changed, 3 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index 69dd80d9f7388..1fdf344efe1ad 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -43,30 +43,6 @@ #include "dce/dce_6_0_d.h" #include "dce/dce_6_0_sh_mask.h" -#define REG(reg) \ - (clk_mgr->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name - -/* set register offset */ -#define SR(reg_name)\ - .reg_name = mm ## reg_name - -static const struct clk_mgr_registers disp_clk_regs = { - CLK_COMMON_REG_LIST_DCE60_BASE() -}; - -static const struct clk_mgr_shift disp_clk_shift = { - CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT) -}; - -static const struct clk_mgr_mask disp_clk_mask = { - CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK) -}; - - /* Max clock values for each state indexed by "enum clocks_state": */ static const struct state_dependent_clocks dce60_max_clks_by_state[] = { /* ClocksStateInvalid - should not be used */ @@ -155,9 +131,9 @@ void dce60_clk_mgr_construct( dce60_max_clks_by_state, sizeof(dce60_max_clks_by_state)); - clk_mgr->regs = &disp_clk_regs; - clk_mgr->clk_mgr_shift = &disp_clk_shift; - clk_mgr->clk_mgr_mask = &disp_clk_mask; + clk_mgr->regs = NULL; + clk_mgr->clk_mgr_shift = NULL; + clk_mgr->clk_mgr_mask = NULL; clk_mgr->base.funcs = &dce60_funcs; base->clks.max_supported_dispclk_khz = diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index bac8febad69a5..836a28134d415 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -89,11 +89,6 @@ enum dentist_divider_range { .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL -#if defined(CONFIG_DRM_AMD_DC_SI) -#define CLK_COMMON_REG_LIST_DCE60_BASE() \ - SR(DENTIST_DISPCLK_CNTL) -#endif - #define CLK_COMMON_REG_LIST_DCN_BASE() \ SR(DENTIST_DISPCLK_CNTL) @@ -119,12 +114,6 @@ enum dentist_divider_range { CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_SI) -#define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \ - CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ - CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) -#endif - #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) From 07da93dccb0d65be70ccf11247b6ea5508fa17aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 18 Jan 2026 18:31:49 +0100 Subject: [PATCH 0207/2070] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dce60_clk_mgr was basically identical to dce_clk_mgr other than a few minor details. They can be all handled in the same file, reducing duplicated code and easing the maintenance burden for old DCE versions. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 12 -- .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 14 +- .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 ++++++-- .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 142 ------------------ .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 ----- 5 files changed, 52 insertions(+), 216 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index 60021671b386a..612a30a03fca5 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -29,18 +29,6 @@ AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR)) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR) - -ifdef CONFIG_DRM_AMD_DC_SI -############################################################################### -# DCE 60 -############################################################################### -CLK_MGR_DCE60 = dce60_clk_mgr.o - -AMD_DAL_CLK_MGR_DCE60 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60)) - -AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE60) -endif - ############################################################################### # DCE 100 and DCE8x ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 15cf13ec53026..de016ea407b6d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -34,7 +34,6 @@ #include "dce110/dce110_clk_mgr.h" #include "dce112/dce112_clk_mgr.h" #include "dce120/dce120_clk_mgr.h" -#include "dce60/dce60_clk_mgr.h" #include "dcn10/rv1_clk_mgr.h" #include "dcn10/rv2_clk_mgr.h" #include "dcn20/dcn20_clk_mgr.h" @@ -149,18 +148,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p struct hw_asic_id asic_id = ctx->asic_id; switch (asic_id.chip_family) { -#if defined(CONFIG_DRM_AMD_DC_SI) - case FAMILY_SI: { - struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); - - if (clk_mgr == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - dce60_clk_mgr_construct(ctx, clk_mgr); - return &clk_mgr->base; - } -#endif + case FAMILY_SI: case FAMILY_CI: case FAMILY_KV: { struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 6131ede2db7a2..6d41df52d7c9b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = { CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) }; +/* Max clock values for each state indexed by "enum clocks_state": */ +static const struct state_dependent_clocks dce60_max_clks_by_state[] = { +/* ClocksStateInvalid - should not be used */ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/* ClocksStateLow */ +{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, +/* ClocksStateNominal */ +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, +/* ClocksStatePerformance */ +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; /* Max clock values for each state indexed by "enum clocks_state": */ static const struct state_dependent_clocks dce80_max_clks_by_state[] = { @@ -126,6 +138,20 @@ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_r return dp_ref_clk_khz; } +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_context *ctx = clk_mgr_base->ctx; + int dp_ref_clk_khz = 0; + + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) + dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; + else + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; + + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); +} + int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); @@ -134,6 +160,9 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) int dp_ref_clk_khz; int target_div; + if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4) + return dce60_get_dp_ref_freq_khz(clk_mgr_base); + /* ASSERT DP Reference Clock source is from DFS*/ REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); ASSERT(dprefclk_src_sel == 0); @@ -441,27 +470,37 @@ void dce_clk_mgr_construct( struct clk_mgr *base = &clk_mgr->base; struct dm_pp_static_clock_info static_clk_info = {0}; - memcpy(clk_mgr->max_clks_by_state, - dce80_max_clks_by_state, - sizeof(dce80_max_clks_by_state)); + if (ctx->dce_version <= DCE_VERSION_6_4) + memcpy(clk_mgr->max_clks_by_state, + dce60_max_clks_by_state, + sizeof(dce60_max_clks_by_state)); + else + memcpy(clk_mgr->max_clks_by_state, + dce80_max_clks_by_state, + sizeof(dce80_max_clks_by_state)); + base->ctx = ctx; base->funcs = &dce_funcs; - clk_mgr->regs = &disp_clk_regs; - clk_mgr->clk_mgr_shift = &disp_clk_shift; - clk_mgr->clk_mgr_mask = &disp_clk_mask; - clk_mgr->dfs_bypass_disp_clk = 0; + if (ctx->dce_version >= DCE_VERSION_8_0) { + clk_mgr->regs = &disp_clk_regs; + clk_mgr->clk_mgr_shift = &disp_clk_shift; + clk_mgr->clk_mgr_mask = &disp_clk_mask; + } + clk_mgr->dfs_bypass_disp_clk = 0; clk_mgr->dprefclk_ss_percentage = 0; clk_mgr->dprefclk_ss_divider = 1000; clk_mgr->ss_on_dprefclk = false; - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) - clk_mgr->max_clks_state = static_clk_info.max_clocks_state; - else - clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; + if (ctx->dce_version >= DCE_VERSION_8_0) { + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) + clk_mgr->max_clks_state = static_clk_info.max_clocks_state; + else + clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; + clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; + } base->clks.max_supported_dispclk_khz = clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; @@ -469,4 +508,3 @@ void dce_clk_mgr_construct( dce_clock_read_integrated_info(clk_mgr); dce_clock_read_ss_info(clk_mgr); } - diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c deleted file mode 100644 index 1fdf344efe1ad..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright 2020 Mauro Rossi - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - - -#include "dccg.h" -#include "clk_mgr_internal.h" -#include "dce100/dce_clk_mgr.h" -#include "dce110/dce110_clk_mgr.h" -#include "dce60_clk_mgr.h" -#include "reg_helper.h" -#include "dmcu.h" -#include "core_types.h" -#include "dal_asic_id.h" - -/* - * Currently the register shifts and masks in this file are used for dce60 - * which has no DPREFCLK_CNTL register - * TODO: remove this when DENTIST_DISPCLK_CNTL - * is moved to dccg, where it belongs - */ -#include "dce/dce_6_0_d.h" -#include "dce/dce_6_0_sh_mask.h" - -/* Max clock values for each state indexed by "enum clocks_state": */ -static const struct state_dependent_clocks dce60_max_clks_by_state[] = { -/* ClocksStateInvalid - should not be used */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateLow */ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, -/* ClocksStateNominal */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, -/* ClocksStatePerformance */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; - -static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) -{ - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - struct dc_context *ctx = clk_mgr_base->ctx; - int dp_ref_clk_khz = 0; - - if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) - dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; - else - dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; - - return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); -} - -static void dce60_pplib_apply_display_requirements( - struct dc *dc, - struct dc_state *context) -{ - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - - dce110_fill_display_configs(context, pp_display_cfg); - - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); -} - -static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, - struct dc_state *context, - bool safe_to_lower) -{ - struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); - struct dm_pp_power_level_change_request level_change_req; - const int max_disp_clk = - clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; - int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { - patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); - clk_mgr_base->clks.dispclk_khz = patched_disp_clk; - } - dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); -} - - - - - - - - -static struct clk_mgr_funcs dce60_funcs = { - .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz, - .update_clocks = dce60_update_clocks -}; - -void dce60_clk_mgr_construct( - struct dc_context *ctx, - struct clk_mgr_internal *clk_mgr) -{ - struct clk_mgr *base = &clk_mgr->base; - - dce_clk_mgr_construct(ctx, clk_mgr); - - memcpy(clk_mgr->max_clks_by_state, - dce60_max_clks_by_state, - sizeof(dce60_max_clks_by_state)); - - clk_mgr->regs = NULL; - clk_mgr->clk_mgr_shift = NULL; - clk_mgr->clk_mgr_mask = NULL; - clk_mgr->base.funcs = &dce60_funcs; - - base->clks.max_supported_dispclk_khz = - clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; -} - diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h deleted file mode 100644 index eca3e5168089b..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2020 Mauro Rossi - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - - -#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_ -#define DAL_DC_DCE_DCE60_CLK_MGR_H_ - -#include "dc.h" - -void dce60_clk_mgr_construct( - struct dc_context *ctx, - struct clk_mgr_internal *clk_mgr_dce); - -#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */ From af915c8f5707e52320edf4df89126db8059135aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 18 Jan 2026 18:31:50 +0100 Subject: [PATCH 0208/2070] drm/amd/display: Handle DCE 6 in dce110_register_irq_handlers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dce60_register_irq_handlers function was basically identical to dce110_register_irq_handlers. They can use the same function, reducing duplicated code and easing the maintenance burden for old DCE versions. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 165 ++++-------------- 1 file changed, 35 insertions(+), 130 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c3c045c8144f1..e9d40fb0fce01 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4384,105 +4384,6 @@ static int register_hpd_handlers(struct amdgpu_device *adev) return 0; } -#if defined(CONFIG_DRM_AMD_DC_SI) -/* Register IRQ sources and initialize IRQ callbacks */ -static int dce60_register_irq_handlers(struct amdgpu_device *adev) -{ - struct dc *dc = adev->dm.dc; - struct common_irq_params *c_irq_params; - struct dc_interrupt_params int_params = {0}; - int r; - int i; - unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; - - int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; - int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; - - /* - * Actions of amdgpu_irq_add_id(): - * 1. Register a set() function with base driver. - * Base driver will call set() function to enable/disable an - * interrupt in DC hardware. - * 2. Register amdgpu_dm_irq_handler(). - * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts - * coming from DC hardware. - * amdgpu_dm_irq_handler() will re-direct the interrupt to DC - * for acknowledging and handling. - */ - - /* Use VBLANK interrupt */ - for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i + 1, 0); - - if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || - int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || - int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { - drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n"); - return -EINVAL; - } - - c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; - - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; - - if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_crtc_high_irq, c_irq_params)) - return -ENOMEM; - } - - /* Use GRPH_PFLIP interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; - i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { - r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); - - if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || - int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || - int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { - drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n"); - return -EINVAL; - } - - c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; - - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; - - if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_pflip_high_irq, c_irq_params)) - return -ENOMEM; - } - - /* HPD */ - r = amdgpu_irq_add_id(adev, client_id, - VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n"); - return r; - } - - r = register_hpd_handlers(adev); - - return r; -} -#endif - /* Register IRQ sources and initialize IRQ callbacks */ static int dce110_register_irq_handlers(struct amdgpu_device *adev) { @@ -4491,7 +4392,12 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) struct dc_interrupt_params int_params = {0}; int r; int i; + unsigned int src_id; unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; + /* Use different interrupts for VBLANK on DCE 6 vs. newer. */ + const unsigned int vblank_d1 = + adev->dm.dc->ctx->dce_version >= DCE_VERSION_8_0 + ? VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 : 1; if (adev->family >= AMDGPU_FAMILY_AI) client_id = SOC15_IH_CLIENTID_DCE; @@ -4512,8 +4418,9 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) */ /* Use VBLANK interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { - r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); + for (i = 0; i < adev->mode_info.num_crtc; i++) { + src_id = vblank_d1 + i; + r = amdgpu_irq_add_id(adev, client_id, src_id, &adev->crtc_irq); if (r) { drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); return r; @@ -4521,7 +4428,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); + dc_interrupt_to_irq_source(dc, src_id, 0); if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || @@ -4540,33 +4447,36 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) return -ENOMEM; } - /* Use VUPDATE interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { - r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); + if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { + /* Use VUPDATE interrupt */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + src_id = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT + i * 2; + r = amdgpu_irq_add_id(adev, client_id, src_id, &adev->vupdate_irq); + if (r) { + drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n"); + return r; + } - if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || - int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || - int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { - drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n"); - return -EINVAL; - } + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, src_id, 0); - c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; + if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || + int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || + int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { + drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n"); + return -EINVAL; + } - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; + c_irq_params = &adev->dm.vupdate_params[ + int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; - if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_vupdate_high_irq, c_irq_params)) - return -ENOMEM; + if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_vupdate_high_irq, c_irq_params)) + return -ENOMEM; + } } /* Use GRPH_PFLIP interrupt */ @@ -5694,11 +5604,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: - if (dce60_register_irq_handlers(dm->adev)) { - drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); - goto fail; - } - break; #endif case CHIP_BONAIRE: case CHIP_HAWAII: From b7b874d5e524c29b61a67644e8d1720818eca296 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:24 +0100 Subject: [PATCH 0209/2070] drm/amd/display: Use DCE 6 link encoder for DCE 6 analog connectors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DCE 6 should use the DCE 6 specific link encoder. This was a copy paste mistake. Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)") Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index e0fbb08e69854..6e03dab2abdef 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -734,7 +734,7 @@ static struct link_encoder *dce60_link_encoder_create( return NULL; if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { - dce110_link_encoder_construct(enc110, + dce60_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, &link_enc_regs[ENGINE_ID_DACA], From 4256acefdf3944e12fadd662007dabb86d55ea92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:25 +0100 Subject: [PATCH 0210/2070] drm/amd/display: Only use analog link encoder with analog engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some GPUs have analog connectors that work with a DP bridge chip and don't actually have an internal DAC: Those should not use the analog link encoder code path. Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)") Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c | 3 ++- drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 3 ++- drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index a929e64524e56..864634e14de10 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -638,7 +638,8 @@ static struct link_encoder *dce100_link_encoder_create( if (!enc110) return NULL; - if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + if (enc_init_data->connector.id == CONNECTOR_ID_VGA && + enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) { dce110_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 6e03dab2abdef..d06d4645ab6f1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -733,7 +733,8 @@ static struct link_encoder *dce60_link_encoder_create( if (!enc110) return NULL; - if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + if (enc_init_data->connector.id == CONNECTOR_ID_VGA && + enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) { dce60_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 8687104cabb72..cde2c2cba1dd6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -740,7 +740,8 @@ static struct link_encoder *dce80_link_encoder_create( if (!enc110) return NULL; - if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + if (enc_init_data->connector.id == CONNECTOR_ID_VGA && + enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) { dce110_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, From 370ea25231cad2fbdf34d61c114af7d8039cf197 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:26 +0100 Subject: [PATCH 0211/2070] drm/amd/display: Only use analog stream encoder with analog engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some GPUs have analog connectors that work with a DP bridge chip and don't actually have an internal DAC: Those should not use the analog stream encoders. Fixes: 5834c33fd3f6 ("drm/amd/display: Add concept of analog encoders (v2)") Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 864634e14de10..f49d67fcafe0a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -979,7 +979,10 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( struct dc_link *link = stream->link; enum engine_id preferred_engine = link->link_enc->preferred_engine; - if (dc_is_rgb_signal(stream->signal)) + /* Prefer analog engine if the link encoder has one. + * Otherwise, it's an external encoder. + */ + if (dc_is_rgb_signal(stream->signal) && link->link_enc->analog_engine != ENGINE_ID_UNKNOWN) preferred_engine = link->link_enc->analog_engine; for (i = 0; i < pool->stream_enc_count; i++) { From 1c09f70991d2ed3c4367cf93f1f8c0f67fe121b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:27 +0100 Subject: [PATCH 0212/2070] drm/amd/display: Add color depth helper function to BIOS parser MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To improve consistency and avoid duplicating the same code. Also, properly handle all enum values where they weren't handled correctly before. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../drm/amd/display/dc/bios/command_table.c | 101 +++++------------- 1 file changed, 26 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index 76a3559f0ddc1..b638cb5adb92e 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -226,6 +226,28 @@ static enum bp_result encoder_control_dig2_v1( return result; } +static uint8_t dc_color_depth_to_atom(enum dc_color_depth color_depth) +{ + switch (color_depth) { + case COLOR_DEPTH_UNDEFINED: + return PANEL_BPC_UNDEFINE; + case COLOR_DEPTH_666: + return PANEL_6BIT_PER_COLOR; + default: + case COLOR_DEPTH_888: + return PANEL_8BIT_PER_COLOR; + case COLOR_DEPTH_101010: + return PANEL_10BIT_PER_COLOR; + case COLOR_DEPTH_121212: + return PANEL_12BIT_PER_COLOR; + case COLOR_DEPTH_141414: + dm_error("14-bit color not supported by ATOMBIOS\n"); + return PANEL_BPC_UNDEFINE; + case COLOR_DEPTH_161616: + return PANEL_16BIT_PER_COLOR; + } +} + static enum bp_result encoder_control_digx_v3( struct bios_parser *bp, struct bp_encoder_control *cntl) @@ -248,23 +270,7 @@ static enum bp_result encoder_control_digx_v3( cntl->signal, cntl->enable_dp_audio); params.ucLaneNum = (uint8_t)(cntl->lanes_number); - - switch (cntl->color_depth) { - case COLOR_DEPTH_888: - params.ucBitPerColor = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucBitPerColor = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucBitPerColor = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_161616: - params.ucBitPerColor = PANEL_16BIT_PER_COLOR; - break; - default: - break; - } + params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) result = BP_RESULT_OK; @@ -294,23 +300,7 @@ static enum bp_result encoder_control_digx_v4( cntl->signal, cntl->enable_dp_audio)); params.ucLaneNum = (uint8_t)(cntl->lanes_number); - - switch (cntl->color_depth) { - case COLOR_DEPTH_888: - params.ucBitPerColor = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucBitPerColor = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucBitPerColor = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_161616: - params.ucBitPerColor = PANEL_16BIT_PER_COLOR; - break; - default: - break; - } + params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) result = BP_RESULT_OK; @@ -334,23 +324,7 @@ static enum bp_result encoder_control_digx_v5( cntl->signal, cntl->enable_dp_audio)); params.ucLaneNum = (uint8_t)(cntl->lanes_number); - - switch (cntl->color_depth) { - case COLOR_DEPTH_888: - params.ucBitPerColor = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucBitPerColor = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucBitPerColor = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_161616: - params.ucBitPerColor = PANEL_16BIT_PER_COLOR; - break; - default: - break; - } + params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A) switch (cntl->color_depth) { @@ -1797,30 +1771,7 @@ static enum bp_result select_crtc_source_v3( ¶ms.ucEncodeMode)) return BP_RESULT_BADINPUT; - switch (bp_params->color_depth) { - case COLOR_DEPTH_UNDEFINED: - params.ucDstBpc = PANEL_BPC_UNDEFINE; - break; - case COLOR_DEPTH_666: - params.ucDstBpc = PANEL_6BIT_PER_COLOR; - break; - default: - case COLOR_DEPTH_888: - params.ucDstBpc = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucDstBpc = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucDstBpc = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_141414: - dm_error("14-bit color not supported by SelectCRTC_Source v3\n"); - break; - case COLOR_DEPTH_161616: - params.ucDstBpc = PANEL_16BIT_PER_COLOR; - break; - } + params.ucDstBpc = dc_color_depth_to_atom(bp_params->color_depth); if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) result = BP_RESULT_OK; From 8c9ea4139a35b3a72c748ab4dcfbc3f309f7b2fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:28 +0100 Subject: [PATCH 0213/2070] drm/amd/display: Refactor DAC load detection, move to HWSS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Slightly refactor and simplify DAC load detection. This prepares the code to be used for also executing DAC load detection on external DP bridge encoders. DAC load detection belongs better in the hardware sequencer code because the implementation is HW dependent and not all chips support the functionality. The code is cleaner when link detection probably doesn't call the VBIOS directly. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 25 ++++++++----------- .../gpu/drm/amd/display/dc/dc_bios_types.h | 4 +-- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 12 +++++++++ .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 + .../drm/amd/display/dc/link/link_detection.c | 24 +++--------------- 5 files changed, 28 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 9f11e6ca40510..e2b74dda00fc6 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -782,26 +782,17 @@ static enum bp_result bios_parser_encoder_control( static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id, - enum dal_device_type device_type, - uint32_t enum_id) + enum engine_id engine_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; - enum bp_result bp_result; + enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; - bp_params.engine_id = engine_id; - bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id); - - if (engine_id != ENGINE_ID_DACA && - engine_id != ENGINE_ID_DACB) - return BP_RESULT_UNSUPPORTED; - - if (!bp->cmd_tbl.dac_load_detection) - return BP_RESULT_UNSUPPORTED; + bp_params.device_id = get_support_mask_for_device_id( + DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) device_id_mask = ATOM_S0_CRT1_MASK; @@ -815,7 +806,13 @@ static enum bp_result bios_parser_dac_load_detection( bios_0_scratch &= ~device_id_mask; dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); - bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + if (engine_id == ENGINE_ID_DACA || engine_id == ENGINE_ID_DACB) { + if (!bp->cmd_tbl.dac_load_detection) + return BP_RESULT_UNSUPPORTED; + + bp_params.engine_id = engine_id; + bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + } if (bp_result != BP_RESULT_OK) return bp_result; diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 40d7a7d83c406..06fdde281a0c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -99,9 +99,7 @@ struct dc_vbios_funcs { struct bp_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id, - enum dal_device_type device_type, - uint32_t enum_id); + enum engine_id engine_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 4277b6761522d..05b27286091b4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -674,6 +674,17 @@ dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) bios->funcs->encoder_control(bios, &encoder_control); } +static bool +dce110_dac_load_detect(struct dc_link *link) +{ + struct dc_bios *bios = link->ctx->dc_bios; + struct link_encoder *link_enc = link->link_enc; + enum bp_result bp_result; + + bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); + return bp_result == BP_RESULT_OK; +} + void dce110_enable_stream(struct pipe_ctx *pipe_ctx) { enum dc_lane_count lane_count = @@ -3442,6 +3453,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, .disable_link_output = dce110_disable_link_output, + .dac_load_detect = dce110_dac_load_detect, }; static const struct hwseq_private_funcs dce110_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 51b0f0fd8fcdf..5c9a758fde37a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1187,6 +1187,7 @@ struct hw_sequencer_funcs { void (*disable_link_output)(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); + bool (*dac_load_detect)(struct dc_link *link); void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index b2c020071cbfb..45a0b25c4ccf0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -932,28 +932,10 @@ static bool link_detect_ddc_probe(struct dc_link *link) */ static bool link_detect_dac_load_detect(struct dc_link *link) { - struct dc_bios *bios = link->ctx->dc_bios; - struct link_encoder *link_enc = link->link_enc; - enum engine_id engine_id = link_enc->preferred_engine; - enum dal_device_type device_type = DEVICE_TYPE_CRT; - enum bp_result bp_result = BP_RESULT_UNSUPPORTED; - uint32_t enum_id; - - switch (engine_id) { - case ENGINE_ID_DACB: - enum_id = 2; - break; - case ENGINE_ID_DACA: - default: - engine_id = ENGINE_ID_DACA; - enum_id = 1; - break; - } - - if (bios->funcs->dac_load_detection) - bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id); + if (!link->dc->hwss.dac_load_detect) + return false; - return bp_result == BP_RESULT_OK; + return link->dc->hwss.dac_load_detect(link); } /* From 81b41171bf398fad0440264107a62506a6c9bbed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:29 +0100 Subject: [PATCH 0214/2070] drm/amd/display: Implement BIOS parser external encoder control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VBIOS has a function called ExternalEncoderControl which controls the DP bridge encoders that some GPUs use for analog and LVDS output. Fixup this old functionality. For reference, see the legacy non-DC amdgpu display code: amdgpu_atombios_encoder_setup_external_encoder() - Set same parameters for the ENABLE action as the SETUP action - Add missing enum values for DDC setup and DAC load detection - Fix the bits per color field - Clarify the code that sets the link rate - Expose the function so that it can be called by rest of DC A subsequent commit will call this function from DCE HWSS. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 14 +++++++++++ .../drm/amd/display/dc/bios/command_table.c | 23 +++++++++---------- .../gpu/drm/amd/display/dc/dc_bios_types.h | 3 +++ .../amd/display/include/bios_parser_types.h | 2 ++ 4 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index e2b74dda00fc6..82877f7b3b6fb 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -780,6 +780,18 @@ static enum bp_result bios_parser_encoder_control( return bp->cmd_tbl.dig_encoder_control(bp, cntl); } +static enum bp_result bios_parser_external_encoder_control( + struct dc_bios *dcb, + struct bp_external_encoder_control *cntl) +{ + struct bios_parser *bp = BP_FROM_DCB(dcb); + + if (!bp->cmd_tbl.external_encoder_control) + return BP_RESULT_UNSUPPORTED; + + return bp->cmd_tbl.external_encoder_control(bp, cntl); +} + static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, enum engine_id engine_id) @@ -2909,6 +2921,8 @@ static const struct dc_vbios_funcs vbios_funcs = { .encoder_control = bios_parser_encoder_control, + .external_encoder_control = bios_parser_external_encoder_control, + .dac_load_detection = bios_parser_dac_load_detection, .transmitter_control = bios_parser_transmitter_control, diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index b638cb5adb92e..d2d59732d338b 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -2521,6 +2521,7 @@ static enum bp_result external_encoder_control_v3( cpu_to_le16((uint16_t)cntl->connector_obj_id.id); break; case EXTERNAL_ENCODER_CONTROL_SETUP: + case EXTERNAL_ENCODER_CONTROL_ENABLE: /* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in * 10KHz * output display device pixel clock frequency in unit of 10KHz. @@ -2537,26 +2538,24 @@ static enum bp_result external_encoder_control_v3( if (is_input_signal_dp) { /* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz, * only valid in encoder setup with DP mode. */ - if (LINK_RATE_HIGH == cntl->link_rate) - cntl_params->ucConfig |= 1; + if (cntl->link_rate == LINK_RATE_LOW) + cntl_params->ucConfig |= + EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ; + else if (cntl->link_rate == LINK_RATE_HIGH) + cntl_params->ucConfig |= + EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; + else + dm_error("Link rate not supported by external encoder"); + /* output color depth Indicate encoder data bpc format * in DP mode, only valid in encoder setup in DP mode. */ - cntl_params->ucBitPerColor = - (uint8_t)(cntl->color_depth); + cntl_params->ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); } /* Indicate how many lanes used by external encoder, only valid * in encoder setup and enableoutput. */ cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number); break; - case EXTERNAL_ENCODER_CONTROL_ENABLE: - cntl_params->usPixelClock = - cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); - cntl_params->ucEncoderMode = - (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom( - cntl->signal, false); - cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number; - break; default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 06fdde281a0c3..6f96c5cf39fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -97,6 +97,9 @@ struct dc_vbios_funcs { enum bp_result (*encoder_control)( struct dc_bios *bios, struct bp_encoder_control *cntl); + enum bp_result (*external_encoder_control)( + struct dc_bios *bios, + struct bp_external_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, enum engine_id engine_id); diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index f40dc612ec73b..b5d97b394131b 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -93,6 +93,8 @@ enum bp_external_encoder_control_action { EXTERNAL_ENCODER_CONTROL_SETUP = 0xf, EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10, EXTERNAL_ENCODER_CONTROL_BLANK = 0x11, + EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT = 0x12, + EXTERNAL_ENCODER_CONTROL_DDC_SETUP = 0x14, }; enum bp_pipe_control_action { From 3a4c2cd3f1dd3e1d46840cc5061efe3817c1cf6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:30 +0100 Subject: [PATCH 0215/2070] drm/amd/display: Implement DDC probe over AUX channel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DDC probe means that we use the DDC (Display Data Channel) to verify whether a display is connected or not. This was written with mainly analog connectors in mind, so it didn't work over the AUX channel. However, in order to support external DP bridge encoders found in CIK APUs, it needs to work over the AUX channel too. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/link/link_detection.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 45a0b25c4ccf0..8fd796d987b63 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -903,11 +903,18 @@ static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) */ static bool link_detect_ddc_probe(struct dc_link *link) { + enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD); + enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal); + uint8_t edid_header[8] = {0}; + uint8_t zero = 0; + bool ddc_probed; + if (!link->ddc) return false; - uint8_t edid_header[8] = {0}; - bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header)); + set_ddc_transaction_type(link->ddc, transaction_type); + + ddc_probed = link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header)); if (!ddc_probed) return false; From 9f984b6702646a2ada79c8c5e678be1d430f3738 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:31 +0100 Subject: [PATCH 0216/2070] drm/amd/display: Add ability for HWSS to prepare the DDC before use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make it possible to add a HWSS function to prepare the DDC before trying to use it. This is going to be necessary for external DP bridge encoders. This commit just adds the function to common DC code. The actual implementation of this function for DCE is done in a subsequent commit. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 +++ drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 1 + drivers/gpu/drm/amd/display/dc/link/link_detection.c | 3 +++ 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bf2a356b34756..7d0ecce6b0340 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1016,6 +1016,9 @@ enum dc_edid_status dm_helpers_read_local_edid( else ddc = &aconnector->i2c->base; + if (link->dc->hwss.prepare_ddc) + link->dc->hwss.prepare_ddc(link); + /* some dongles read edid incorrectly the first time, * do check sum and retry to make sure read correct edid. */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 5c9a758fde37a..93e171c3a179e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1188,6 +1188,7 @@ struct hw_sequencer_funcs { const struct link_resource *link_res, enum signal_type signal); bool (*dac_load_detect)(struct dc_link *link); + void (*prepare_ddc)(struct dc_link *link); void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8fd796d987b63..2d1f3d13c1773 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -912,6 +912,9 @@ static bool link_detect_ddc_probe(struct dc_link *link) if (!link->ddc) return false; + if (link->dc->hwss.prepare_ddc) + link->dc->hwss.prepare_ddc(link); + set_ddc_transaction_type(link->ddc, transaction_type); ddc_probed = link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header)); From 717e9cac6fa64125427df3c01994330dd6fdb257 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:32 +0100 Subject: [PATCH 0217/2070] drm/amd/display: Use preferred DP link rate if specified MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DisplayPort code already has the concept of preferred link settings, but it only allows setting a preferred lane count and link width at the same time. It does not consider the possiblity that some devices may not work on lower link rates but may support various lane counts. Allow specifying a preferred link rate which will be used as the initial link rate when deciding the DP link settings. This is necessary to support NUTMEG which only works with HBR but not with RBR. For reference, see the legacy non-DC amdgpu display code: amdgpu_atombios_dp_get_dp_link_config() Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index cdc7587cf0b68..e12bf3dd3e464 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -743,6 +743,8 @@ static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_setting { struct dc_link_settings initial_link_setting = { LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; + if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) + initial_link_setting.link_rate = link->preferred_link_setting.link_rate; struct dc_link_settings current_link_setting = initial_link_setting; uint32_t link_bw; From 93803ad5af910ddd9c55b3b868b3dd5019459722 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:33 +0100 Subject: [PATCH 0218/2070] drm/amd/display: Add DCE HWSS support for external DP bridge encoders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some GPUs use external DP bridge encoders NUTMEG and TRAVIS to implement analog and/or LVDS connections. Typically found in CIK APU based laptops or on FM2 motherboards that have analog connectors. These were necessary at the time because Kaveri didn't have a built-in DAC nor LVDS support. These devices sadly don't work transparently and need to be controlled by the driver. Implement the necessary control for the NUTMEG and TRAVIS encoders in the DCE HWSS. For reference, see the legacy non-DC amdgpu display code: amdgpu_atombios_encoder_setup_external_encoder() amdgpu_atombios_encoder_setup_dig() amdgpu_atombios_encoder_setup_ext_encoder_ddc() - Prepare DDC before using it: Call the EXTERNAL_ENCODER_CONTROL_DDC_SETUP action so that the encoder knows to set up DDC over the AUX channel. - When a stream is enabled or disabled: Call the EXTERNAL_ENCODER_CONTROL_ENABLE/DISABLE actions. - Before enabling the DP link: Call the EXTERNAL_ENCODER_CONTROL_SETUP action. This commit just hooks up the HWSS support. Detecting the external DP bridge encoders will be done in a subsequent commit. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 4 ++ .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 54 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 71f2812acf599..eb9de0e48c63c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1682,6 +1682,10 @@ struct dc_scratch_space { struct panel_cntl *panel_cntl; struct link_encoder *link_enc; struct graphics_object_id link_id; + + /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ + struct graphics_object_id ext_enc_id; + /* Endpoint type distinguishes display endpoints which do not have entries * in the BIOS connector table from those that do. Helps when tracking link * encoder to display endpoint assignments. diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 05b27286091b4..ceefecb2307b0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -660,6 +660,48 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) } } +static void +dce110_external_encoder_control(enum bp_external_encoder_control_action action, + struct dc_link *link, + struct dc_crtc_timing *timing) +{ + struct dc *dc = link->ctx->dc; + struct dc_bios *bios = link->ctx->dc_bios; + const struct dc_link_settings *link_settings = &link->cur_link_settings; + enum bp_result bp_result = BP_RESULT_OK; + struct bp_external_encoder_control ext_cntl = { + .action = action, + .connector_obj_id = link->link_enc->connector, + .encoder_id = link->ext_enc_id, + .lanes_number = link_settings->lane_count, + .link_rate = link_settings->link_rate, + + /* Use signal type of the real link encoder, ie. DP */ + .signal = link->connector_signal, + + /* We don't know the timing yet when executing the SETUP action, + * so use a reasonably high default value. It seems that ENABLE + * can change the actual pixel clock but doesn't work with higher + * pixel clocks than what SETUP was called with. + */ + .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000, + .color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888, + }; + DC_LOGGER_INIT(); + + bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl); + + if (bp_result != BP_RESULT_OK) + DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action); +} + +static void +dce110_prepare_ddc(struct dc_link *link) +{ + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL); +} + static void dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) { @@ -717,6 +759,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) if (dc_is_rgb_signal(pipe_ctx->stream->signal)) dce110_dac_encoder_control(pipe_ctx, true); + + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing); } static enum bp_result link_transmitter_control( @@ -1213,6 +1258,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) if (dc_is_rgb_signal(pipe_ctx->stream->signal)) dce110_dac_encoder_control(pipe_ctx, false); + + if (link->ext_enc_id.id) + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL); } void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, @@ -3362,6 +3410,11 @@ void dce110_enable_dp_link_output( } } + if (link->ext_enc_id.id) { + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL); + dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL); + } + if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { if (dc->clk_mgr->funcs->notify_link_rate_change) dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); @@ -3454,6 +3507,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_dp_link_output = dce110_enable_dp_link_output, .disable_link_output = dce110_disable_link_output, .dac_load_detect = dce110_dac_load_detect, + .prepare_ddc = dce110_prepare_ddc, }; static const struct hwseq_private_funcs dce110_private_funcs = { From 3b561394509305d444fb2107cbae6779259e5749 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:34 +0100 Subject: [PATCH 0219/2070] drm/amd/display: Link detection for external DP bridge encoders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deal with some minor idiosyncracies of TRAVIS and NUTMEG chips. - Always use DP signal type with these chips so that the normal DP code paths can work with them without a major refactor of the code base. Properly set this. - NUTMEG seems to only work with HBR, not RBR, so set a preferred link rate for this chip. See amdgpu_atombios_dp_get_dp_link_config() for reference. - NUTMEG is recognized as a DP branch device but reports 0 sinks, which is wrong and confuses DC (it hits an early return). Fix that by hardcoding the sink count to 1. - Fixup old DC code selecting a special panel mode necessary for NUTMEG and TRAVIS. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../drm/amd/display/dc/link/link_detection.c | 20 +++++++++++-------- .../link/protocols/link_edp_panel_control.c | 8 ++------ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 2d1f3d13c1773..d0bb26888f4b1 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -150,14 +150,6 @@ static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, default: return SIGNAL_TYPE_NONE; } - } else if (downstream.type == OBJECT_TYPE_ENCODER) { - switch (downstream.id) { - case ENCODER_ID_EXTERNAL_NUTMEG: - case ENCODER_ID_EXTERNAL_TRAVIS: - return SIGNAL_TYPE_DISPLAY_PORT; - default: - return SIGNAL_TYPE_NONE; - } } return SIGNAL_TYPE_NONE; @@ -174,6 +166,10 @@ static enum signal_type link_detect_sink_signal_type(struct dc_link *link, struct audio_support *aud_support; struct graphics_object_id enc_id; + /* External DP bridges should use DP signal regardless of connector type. */ + if (link->ext_enc_id.id) + return SIGNAL_TYPE_DISPLAY_PORT; + if (link->is_dig_mapping_flexible) enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; else @@ -620,6 +616,14 @@ static bool detect_dp(struct dc_link *link, link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0; } + if (link->ext_enc_id.id) { + /* Fix number of connected sinks reported by external DP bridge */ + link->dpcd_caps.sink_count.bits.SINK_COUNT = 1; + /* NUTMEG requires that we use HBR, doesn't work with RBR. */ + if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_00001A) + link->preferred_link_setting.link_rate = LINK_RATE_HIGH; + } + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index aa02b38e183aa..5b2c1a4911cf0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -100,11 +100,7 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) { - /* We need to explicitly check that connector - * is not DP. Some Travis_VGA get reported - * by video bios as DP. - */ - if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { + if (link->ext_enc_id.id) { switch (link->dpcd_caps.branch_dev_id) { case DP_BRANCH_DEVICE_ID_0022B9: @@ -124,7 +120,7 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) } break; case DP_BRANCH_DEVICE_ID_00001A: - /* alternate scrambler reset is required for Travis + /* alternate scrambler reset is required for NUTMEG * for the case when external chip does not provide * sink device id, alternate scrambler scheme will * be overriden later by querying Encoder feature From 646d6cbbe65e7b4c2fd297ac1c7e241939cc8baf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:35 +0100 Subject: [PATCH 0220/2070] drm/amd/display: Use external DP bridge encoders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement link creation for external DP bridge encoders such as NUTMEG and TRAVIS used with CIK APUs such as Kaveri for supporting analog and LVDS connections. Typically found in CIK APU based laptops or on FM2 motherboards that have analog connectors. When we query connector information from the VBIOS and discover a connector using such an encoder, let's find the real DisplayPort encoder and use that. Set the connector signal type to DP, so the pre-existing DP code paths can work with it without refactoring every signal type check in the DC code base. In the DM, make sure to report correct connector type and also to initialize DP specifics such as the AUX channel. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++++-- .../drm/amd/display/dc/link/link_factory.c | 29 ++++++++++++++++++- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e9d40fb0fce01..06200d0ea805c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8482,6 +8482,12 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) return DRM_MODE_CONNECTOR_VGA; case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: + /* External DP bridges have a different connector type. */ + if (connector_id == CONNECTOR_ID_VGA) + return DRM_MODE_CONNECTOR_VGA; + else if (connector_id == CONNECTOR_ID_LVDS) + return DRM_MODE_CONNECTOR_LVDS; + return DRM_MODE_CONNECTOR_DisplayPort; case SIGNAL_TYPE_DVI_DUAL_LINK: case SIGNAL_TYPE_DVI_SINGLE_LINK: @@ -9154,8 +9160,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, connector_type == DRM_MODE_CONNECTOR_HDMIB) amdgpu_dm_initialize_hdmi_connector(aconnector); - if (connector_type == DRM_MODE_CONNECTOR_DisplayPort - || connector_type == DRM_MODE_CONNECTOR_eDP) + if (dc_is_dp_signal(link->connector_signal)) amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); out_free: diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 6f4c3c73e113e..7b84bf2e845bc 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -367,6 +367,18 @@ static enum transmitter translate_encoder_to_transmitter( } } +static bool encoder_is_external_dp( + struct graphics_object_id encoder) +{ + switch (encoder.id) { + case ENCODER_ID_EXTERNAL_NUTMEG: + case ENCODER_ID_EXTERNAL_TRAVIS: + return true; + default: + return false; + } +} + static void link_destruct(struct dc_link *link) { int i; @@ -514,6 +526,13 @@ static bool construct_phy(struct dc_link *link, * so that we avoid initializing DDC and HPD, etc. */ bp_funcs->get_src_obj(bios, link->link_id, 0, &link_encoder); + + if (encoder_is_external_dp(link_encoder)) { + /* External DP bridge encoders: find the actual link encoder and use that. */ + link->ext_enc_id = link_encoder; + bp_funcs->get_src_obj(bios, link->ext_enc_id, 0, &link_encoder); + } + transmitter_from_encoder = translate_encoder_to_transmitter(link_encoder); link_analog_engine = find_analog_engine(link, &enc_init_data.analog_encoder); @@ -692,6 +711,13 @@ static bool construct_phy(struct dc_link *link, goto create_fail; } + /* For external DP bridge encoders: + * Set the connector signal to DisplayPort so that they can work with + * the pre-existing code paths for DP without a lot of code churn. + */ + if (link->ext_enc_id.id != ENCODER_ID_UNKNOWN) + link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; + LINK_INFO("Connector[%d] description: signal: %s\n", init_params->connector_index, signal_type_to_string(link->connector_signal)); @@ -736,7 +762,8 @@ static bool construct_phy(struct dc_link *link, link->device_tag.dev_id)) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT && - link->connector_signal != SIGNAL_TYPE_RGB) + link->connector_signal != SIGNAL_TYPE_RGB && + link->ext_enc_id.id == ENCODER_ID_UNKNOWN) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD && link->connector_signal == SIGNAL_TYPE_RGB) From 628a5aee98b85a589ec836f37a495cef3e189769 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:36 +0100 Subject: [PATCH 0221/2070] drm/amd/display: Implement DAC load detection on external DP bridge encoders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the pre-existing implementation in the BIOS parser, but call the ExternalEncoderControl function for external encoders instead of the built-in DAC load detection function. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 11 ++++++++++- drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 3 ++- .../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 3 ++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 82877f7b3b6fb..f56f3ee81a223 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -794,11 +794,13 @@ static enum bp_result bios_parser_external_encoder_control( static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id) + enum engine_id engine_id, + struct graphics_object_id ext_enc_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; + struct bp_external_encoder_control ext_cntl = {0}; enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; @@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection( bp_params.engine_id = engine_id; bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + } else if (ext_enc_id.id) { + if (!bp->cmd_tbl.external_encoder_control) + return BP_RESULT_UNSUPPORTED; + + ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT; + ext_cntl.encoder_id = ext_enc_id; + bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl); } if (bp_result != BP_RESULT_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 6f96c5cf39fe8..526f71616f94b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -102,7 +102,8 @@ struct dc_vbios_funcs { struct bp_external_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id); + enum engine_id engine_id, + struct graphics_object_id ext_enc_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index ceefecb2307b0..6e6430909bbaa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -723,7 +723,8 @@ dce110_dac_load_detect(struct dc_link *link) struct link_encoder *link_enc = link->link_enc; enum bp_result bp_result; - bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); + bp_result = bios->funcs->dac_load_detection( + bios, link_enc->analog_engine, link->ext_enc_id); return bp_result == BP_RESULT_OK; } From 02a3a20388104df5ac32ae514a16b0273a58ec6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 26 Jan 2026 22:08:37 +0100 Subject: [PATCH 0222/2070] drm/amdgpu: Use DC by default on CIK APUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that DC supports external DP bridge encoders, it has reached feature parity with the legacy non-DC display driver on CIK APUs: Kaveri, Kabini, Mullins. Use the DC display driver by default on SI APUs, unless it is explicitly disabled using the amdgpu.dc=0 module parameter. DC brings proper support for DP/HDMI audio, DP MST, VRR, 10-bit colors, some HDR features, atomic modesetting, etc. Signed-off-by: Timur Kristóf Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6756d5faabd94..813c6319dd553 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4105,17 +4105,6 @@ bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, case CHIP_VERDE: case CHIP_OLAND: return amdgpu_dc != 0 && IS_ENABLED(CONFIG_DRM_AMD_DC_SI); - case CHIP_KAVERI: - case CHIP_KABINI: - case CHIP_MULLINS: - /* - * We have systems in the wild with these ASICs that require - * TRAVIS and NUTMEG support which is not supported with DC. - * - * Fallback to the non-DC driver here by default so as not to - * cause regressions. - */ - return amdgpu_dc > 0; default: return amdgpu_dc != 0; #else From 940df7788e4efd5fa9d3e784b1e9171ed00e1775 Mon Sep 17 00:00:00 2001 From: Mario Kleiner Date: Fri, 6 Feb 2026 23:38:28 +0100 Subject: [PATCH 0223/2070] drm/amd/display: Use same max plane scaling limits for all 64 bpp formats The plane scaling hw seems to have the same min/max plane scaling limits for all 16 bpc / 64 bpp interleaved pixel color formats. Therefore add cases to amdgpu_dm_plane_get_min_max_dc_plane_scaling() for all the 16 bpc fixed-point / unorm formats to use the same .fp16 up/downscaling factor limits as used by the fp16 floating point formats. So far, 16 bpc unorm formats were not handled, and the default: path returned max/min factors for 32 bpp argb8888 formats, which were wrong and bigger than what many DCE / DCN hw generations could handle. The result sometimes was misscaling of framebuffers with DRM_FORMAT_XRGB16161616, DRM_FORMAT_ARGB16161616, DRM_FORMAT_XBGR16161616, DRM_FORMAT_ABGR16161616, leading to very wrong looking display, as tested on Polaris11 / DCE-11.2. So far this went unnoticed, because only few userspace clients used such 16 bpc unorm framebuffers, and those didn't use hw plane scaling, so they did not experience this issue. With upcoming Mesa 26 exposing 16 bpc unorm formats under both OpenGL and Vulkan under Wayland, and the upcoming GNOME 50 Mutter Wayland compositor allowing for direct scanout of these formats, the scaling hw will be used on these formats if possible for HiDPI display scaling, so it is important to use the correct hw scaling limits to avoid wrong display. Tested on AMD Polaris 11 / DCE 11.2 with upcoming Mesa 26 and GNOME 50 on HiDPI displays with scaling enabled. The mutter Wayland compositor now correctly falls back to scaling via desktop compositing instead of direct scanout, thereby avoiding wrong image display. For unscaled mode, it correctly uses direct scanout. Fixes: 580204038f5b ("drm/amd/display: Enable support for 16 bpc fixed-point framebuffers.") Signed-off-by: Mario Kleiner Tested-by: Mario Kleiner Cc: Alex Deucher Cc: Harry Wentland Cc: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index ce56734c09b86..198064acf9f6f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1060,10 +1060,15 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, *min_downscale = plane_cap->max_downscale_factor.nv12; break; + /* All 64 bpp formats have the same fp16 scaling limits */ case DRM_FORMAT_XRGB16161616F: case DRM_FORMAT_ARGB16161616F: case DRM_FORMAT_XBGR16161616F: case DRM_FORMAT_ABGR16161616F: + case DRM_FORMAT_XRGB16161616: + case DRM_FORMAT_ARGB16161616: + case DRM_FORMAT_XBGR16161616: + case DRM_FORMAT_ABGR16161616: *max_upscale = plane_cap->max_upscale_factor.fp16; *min_downscale = plane_cap->max_downscale_factor.fp16; break; From 93ef6385e90ffd0a7a9d07a4c772f0f79e957ce9 Mon Sep 17 00:00:00 2001 From: Andrew Martin Date: Fri, 12 Dec 2025 15:59:17 +0800 Subject: [PATCH 0224/2070] drm/amdkfd: Check for NULL return values This patch fixes issues when the code moves forward with a potential NULL pointer, without checking. Removed one redundant NULL check for a function parameter. This check is already done in the only caller. Signed-off-by: Andrew Martin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 15 ++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 3 --- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 193ed8becab8d..31b8fa52b42fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -107,7 +107,7 @@ static const char *amdkfd_fence_get_timeline_name(struct dma_fence *f) { struct amdgpu_amdkfd_fence *fence = to_amdgpu_amdkfd_fence(f); - return fence->timeline_name; + return fence ? fence->timeline_name : NULL; } /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 36ffc3c785367..a1087c13f2419 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -2359,7 +2359,7 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image, if (kdev->kfd->hive_id) { for (nid = 0; nid < proximity_domain; ++nid) { peer_dev = kfd_topology_device_by_proximity_domain_no_lock(nid); - if (!peer_dev->gpu) + if (!peer_dev || !peer_dev->gpu) continue; if (peer_dev->gpu->kfd->hive_id != kdev->kfd->hive_id) continue; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index bedb95ce96590..0f7aa51b629eb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -523,10 +523,15 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags) int i, r = 0, rewind_count = 0; for (i = 0; i < target->n_pdds; i++) { + uint32_t caps; + uint32_t caps2; struct kfd_topology_device *topo_dev = - kfd_topology_device_by_id(target->pdds[i]->dev->id); - uint32_t caps = topo_dev->node_props.capability; - uint32_t caps2 = topo_dev->node_props.capability2; + kfd_topology_device_by_id(target->pdds[i]->dev->id); + if (!topo_dev) + return -EINVAL; + + caps = topo_dev->node_props.capability; + caps2 = topo_dev->node_props.capability2; if (!(caps & HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED) && (*flags & KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP)) { @@ -1086,6 +1091,10 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, for (i = 0; i < tmp_num_devices; i++) { struct kfd_process_device *pdd = target->pdds[i]; struct kfd_topology_device *topo_dev = kfd_topology_device_by_id(pdd->dev->id); + if (!topo_dev) { + r = -EINVAL; + break; + } device_info.gpu_id = pdd->dev->id; device_info.exception_status = pdd->exception_status; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index ba25d83c23e78..6d32941ce8c74 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1773,9 +1773,6 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd, struct kfd_node *dev; int ret; - if (!drm_file) - return -EINVAL; - if (pdd->drm_priv) return -EBUSY; From 8cd0f552e940a898f89fa9951dd6934f8e1dd485 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Thu, 12 Feb 2026 12:13:26 -0500 Subject: [PATCH 0225/2070] drm/amdgpu: Set atomics to true for xgmi xgmi support atomics between links. Set them to true. This only set for GFX12 onwards to avoid regression on older generations v2: Use correct xgmi flag that indicates CPU connection Signed-off-by: Harish Kasiviswanathan Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 813c6319dd553..dac849eff52fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4601,9 +4601,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a * internal path natively support atomics, set have_atomics_support to true. */ - } else if ((adev->flags & AMD_IS_APU) && - (amdgpu_ip_version(adev, GC_HWIP, 0) > - IP_VERSION(9, 0, 0))) { + } else if ((adev->flags & AMD_IS_APU && + amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0)) || + (adev->gmc.xgmi.connected_to_cpu && + amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0))) { adev->have_atomics_support = true; } else { adev->have_atomics_support = From b8ae43e1e5e4ac75ee7d8e65aa5500244e76552a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Feb 2026 10:02:32 -0500 Subject: [PATCH 0226/2070] drm/amdgpu: keep vga memory on MacBooks with switchable graphics On Intel MacBookPros with switchable graphics, when the iGPU is enabled, the address of VRAM gets put at 0 in the dGPU's virtual address space. This is non-standard and seems to cause issues with the cursor if it ends up at 0. We have the framework to reserve memory at 0 in the address space, so enable it here if the vram start address is 0. Reviewed-and-tested-by: Mario Kleiner Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4302 Cc: stable@vger.kernel.org Cc: Mario Kleiner Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 3709ec26708d3..20e1395b39882 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1068,6 +1068,16 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) case CHIP_RENOIR: adev->mman.keep_stolen_vga_memory = true; break; + case CHIP_POLARIS10: + case CHIP_POLARIS11: + case CHIP_POLARIS12: + /* MacBookPros with switchable graphics put VRAM at 0 when + * the iGPU is enabled which results in cursor issues if + * the cursor ends up at 0. Reserve vram at 0 in that case. + */ + if (adev->gmc.vram_start == 0) + adev->mman.keep_stolen_vga_memory = true; + break; default: adev->mman.keep_stolen_vga_memory = false; break; From 9919903358dce62f587be07fd1b0abbf3f8a4425 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 17:11:43 -0500 Subject: [PATCH 0227/2070] drm/amd/display: Add dcn42 register headers Register headers for the following IPs: - DCN 4.2.0 - DPCS 4.0.0 Signed-off-by: Roman Li Acked-by: Harry Wentland --- .../include/asic_reg/dcn/dcn_4_2_0_offset.h | 17872 ++++ .../include/asic_reg/dcn/dcn_4_2_0_sh_mask.h | 67277 ++++++++++++++++ .../include/asic_reg/dpcs/dpcs_4_0_0_offset.h | 142 + .../asic_reg/dpcs/dpcs_4_0_0_sh_mask.h | 688 + 4 files changed, 85979 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h new file mode 100644 index 0000000000000..825201f4e113f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h @@ -0,0 +1,17872 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dcn_4_2_0_OFFSET_HEADER +#define _dcn_4_2_0_OFFSET_HEADER + + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x0 +#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000 +#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_READ_POINTER 0x0000 +#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_CONTROL 0x0001 +#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_STATUS 0x0001 +#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_SIZE 0x0001 +#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002 +#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003 +#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004 +#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0 +#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004 +#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_CONTROL 0x0005 +#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_STATUS 0x0005 +#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_SIZE 0x0005 +#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x074c +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dc_perfmon_dc_perfmondebugind +// base address: 0x0 +#define ixPERFMON_DEBUG_ID 0x0000 +#define ixPERFMON_DEBUG01 0x0001 +#define ixPERFMON_DEBUG02 0x0002 +#define ixPERFMON_DEBUG03 0x0003 +#define ixPERFMON_DEBUG04 0x0004 +#define ixPERFMON_DEBUG05 0x0005 +#define ixPERFMON_DEBUG06 0x0006 +#define ixPERFMON_DEBUG07 0x0007 +#define ixPERFMON_DEBUG08 0x0008 +#define ixPERFMON_DEBUG09 0x0009 +#define ixPERFMON_DEBUG0A 0x000a +#define ixPERFMON_DEBUG0B 0x000b +#define ixPERFMON_DEBUG0C 0x000c +#define ixPERFMON_DEBUG0D 0x000d +#define ixPERFMON_DEBUG0E 0x000e +#define ixPERFMON_DEBUG0F 0x000f +#define ixPERFMON_DEBUG10 0x0010 +#define ixPERFMON_DEBUG11 0x0011 +#define ixPERFMON_DEBUG12 0x0012 + + +// addressBlock: mcif_wb0_mcif_wbdebugind +// base address: 0x0 +#define ixMCIF_WB_DEBUG_ID 0x0000 +#define ixID01_WB_FMT_DBG 0x0001 +#define ixID02_WB_FMT_DBG 0x0002 +#define ixID03_WB_FMT_DBG 0x0003 +#define ixID04_WB_MGR_DBG 0x0004 +#define ixID05_WB_MGR_DBG 0x0005 +#define ixID06_WB_MGR_DBG 0x0006 +#define ixID07_WB_MGR_DBG 0x0007 +#define ixID08_WB_ARB_DBG 0x0008 +#define ixID09_WB_ARB_DBG 0x0009 +#define ixID0A_WB_ARB_DBG 0x000a +#define ixID0B_WB_ARB_DBG 0x000b +#define ixID0C_WB_ARB_DBG 0x000c +#define ixID0D_WB_ARB_DBG 0x000d +#define ixID0E_WB_ARB_DBG 0x000e +#define ixID0F_P010_WB_FMT_DBG_Y 0x000f +#define ixID10_P010_WB_FMT_DBG_C 0x0010 +#define ixID11_WB_ARB_P010_DBG 0x0011 +#define ixID12_WB_ARB_P010_DBG 0x0012 + + +// addressBlock: hubbub_dchubbubdebugind +// base address: 0x0 +#define ixDCHUBBUB_KEY_STATUS_DEBUG_1 0x005f +#define ixDCHUBBUB_KEY_STATUS_DEBUG_2 0x0060 + + +// addressBlock: odm0_odmdebugind +// base address: 0x0 +#define ixODM0_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM0_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM0_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM0_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: odm1_odmdebugind +// base address: 0x0 +#define ixODM1_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM1_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM1_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM1_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: odm2_odmdebugind +// base address: 0x0 +#define ixODM2_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM2_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM2_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM2_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: odm3_odmdebugind +// base address: 0x0 +#define ixODM3_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM3_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM3_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM3_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: rbbmif_rbbmifdebugind +// base address: 0x0 +#define ixRBBMIF_DEBUG_ID 0x0000 +#define ixRBBMIF_DEBUG_0 0x0001 +#define ixRBBMIF_DEBUG_1 0x0002 +#define ixRBBMIF_DEBUG_2 0x0003 +#define ixRBBMIF_DEBUG_3 0x0004 +#define ixRBBMIF_DEBUG_4 0x0005 +#define ixRBBMIF_DEBUG_5 0x0006 +#define ixRBBMIF_DEBUG_6 0x0007 +#define ixRBBMIF_DEBUG_7 0x0008 +#define ixRBBMIF_DEBUG_8 0x0009 +#define ixRBBMIF_DEBUG_9 0x000a +#define ixRBBMIF_DEBUG_10 0x000b +#define ixRBBMIF_DEBUG_11 0x000c +#define ixRBBMIF_DEBUG_12 0x000d +#define ixRBBMIF_DEBUG_13 0x000e +#define ixRBBMIF_DEBUG_14 0x000f +#define ixRBBMIF_DEBUG_15 0x0010 +#define ixRBBMIF_DEBUG_16 0x0011 +#define ixRBBMIF_DEBUG_17 0x0012 +#define ixRBBMIF_DEBUG_18 0x0013 +#define ixRBBMIF_DEBUG_19 0x0014 +#define ixRBBMIF_DEBUG_20 0x0015 +#define ixRBBMIF_DEBUG_21 0x0016 +#define ixRBBMIF_DEBUG_22 0x0017 +#define ixRBBMIF_DEBUG_23 0x0018 +#define ixRBBMIF_DEBUG_24 0x0019 +#define ixRBBMIF_DEBUG_25 0x001a +#define ixRBBMIF_DEBUG_26 0x001b +#define ixRBBMIF_DEBUG_27 0x001c +#define ixRBBMIF_DEBUG_28 0x001d +#define ixRBBMIF_DEBUG_29 0x001e +#define ixRBBMIF_DEBUG_30 0x001f +#define ixRBBMIF_DEBUG_31 0x0020 +#define ixRBBMIF_DEBUG_32 0x0021 +#define ixRBBMIF_DEBUG_33 0x0022 +#define ixRBBMIF_DEBUG_34 0x0023 +#define ixRBBMIF_DEBUG_35 0x0024 +#define ixRBBMIF_DEBUG_36 0x0025 +#define ixRBBMIF_DEBUG_37 0x0026 +#define ixRBBMIF_DEBUG_38 0x0027 +#define ixRBBMIF_DEBUG_39 0x0028 +#define ixRBBMIF_DEBUG_40 0x0029 +#define ixRBBMIF_DEBUG_41 0x002a +#define ixRBBMIF_DEBUG_42 0x002b +#define ixRBBMIF_DEBUG_43 0x002c +#define ixRBBMIF_DEBUG_44 0x002d +#define ixRBBMIF_DEBUG_45 0x002e +#define ixRBBMIF_DEBUG_46 0x002f +#define ixRBBMIF_DEBUG_47 0x0030 +#define ixRBBMIF_DEBUG_48 0x0031 +#define ixRBBMIF_DEBUG_49 0x0032 +#define ixRBBMIF_DEBUG_50 0x0033 +#define ixRBBMIF_DEBUG_51 0x0034 +#define ixRBBMIF_DEBUG_52 0x0035 + + +// addressBlock: ihc_ihcdebugind +// base address: 0x0 +#define ixIHC_DEBUG_ID 0x0000 +#define ixIHC_CLIENT_DEBUG_A 0x0001 +#define ixIHC_CLIENT_DEBUG_B 0x0002 +#define ixIHC_CLIENT_DEBUG_C 0x0003 +#define ixIHC_CLIENT_DEBUG_D 0x0004 +#define ixIHC_CLIENT_DEBUG_E 0x0005 + + +// addressBlock: dmu_misc_dmumiscdebugind +// base address: 0x0 +#define ixDMU_MISC_DEBUG_ID 0x0000 +#define ixDMU_MISC_DEBUG_1 0x0001 +#define ixDMU_ZSC_TEST_DEBUG1_DATA 0x0002 +#define ixDMU_ZSC_TEST_DEBUG2_DATA 0x0003 + + +// addressBlock: dc_pg_dc_pgdebugind +// base address: 0x0 +#define ixDCPG_DEBUG_ID 0x0000 +#define ixDCPG_CONTROL_DEBUG_BUS0 0x0001 +#define ixDCPG_CONTROL_DEBUG_BUS1 0x0002 +#define ixDCPG_CONTROL_DEBUG_BUS2 0x0003 +#define ixDCPG_CONTROL_DEBUG_BUS3 0x0004 +#define ixDCPG_CONTROL_DEBUG_BUS16 0x0011 +#define ixDCPG_CONTROL_DEBUG_BUS17 0x0012 +#define ixDCPG_CONTROL_DEBUG_BUS18 0x0013 +#define ixDCPG_CONTROL_DEBUG_BUS19 0x0014 +#define ixDCPG_CONTROL_DEBUG_BUS22 0x0017 +#define ixDCPG_CONTROL_DEBUG_BUS23 0x0018 +#define ixDCPG_CONTROL_DEBUG_BUS24 0x0019 +#define ixDCPG_CONTROL_DEBUG_BUS25 0x001a +#define ixDCPG_CONTROL_DEBUG_BUS26 0x001b + + +// addressBlock: dp0_dpdebugind +// base address: 0x0 +#define ixDP0_DP_DEBUG_ID 0x0000 +#define ixDP0_DP_DEBUG_K 0x00a2 +#define ixDP0_DP_DEBUG_L 0x00a3 +#define ixDP0_DP_DEBUG_M 0x00a4 +#define ixDP0_DP_DEBUG_G 0x00b4 +#define ixDP0_DP_DEBUG_O 0x00fb +#define ixDP0_DP_DEBUG_P 0x00fc +#define ixDP0_DP_DEBUG_Q 0x00fd +#define ixDP0_DP_DEBUG_R 0x00fe +#define ixDP0_DP_DEBUG_S 0x00ff + + +// addressBlock: dp0_dpfedebugind +// base address: 0x0 +#define ixDP0_DP_FE_DEBUG_ID 0x0000 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP0_DP_DEBUG_T 0x0090 +#define ixDP0_DP_DEBUG_U 0x0091 +#define ixDP0_DP_DEBUG_V 0x0092 +#define ixDP0_DP_DEBUG_W 0x0093 +#define ixDP0_DP_DEBUG_X 0x0094 +#define ixDP0_DP_DEBUG_Y 0x0095 +#define ixDP0_DP_DEBUG_Z 0x0096 +#define ixDP0_DP_DEBUG_1A 0x0097 +#define ixDP0_DP_DEBUG_1B 0x0098 +#define ixDP0_DP_DEBUG_I 0x00a0 +#define ixDP0_DP_DEBUG_J 0x00a1 +#define ixDP0_DP_DEBUG_N 0x00a2 +#define ixDP0_DP_DEBUG_H 0x00ac +#define ixDP0_DP_DEBUG_A 0x00ad +#define ixDP0_DP_DEBUG_B 0x00ae +#define ixDP0_DP_DEBUG_C 0x00af +#define ixDP0_DP_DEBUG_D 0x00b0 +#define ixDP0_DP_DEBUG_E 0x00b2 +#define ixDP0_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp0_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig0_digdebugind +// base address: 0x0 +#define ixDIG0_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig0_digfedebugind +// base address: 0x0 +#define ixDIG0_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG0_DIG_VPG_DEBUG0 0x000b +#define ixDIG0_DIG_VPG_DEBUG1 0x000c +#define ixDIG0_DIG_VPG_DEBUG2 0x000d +#define ixDIG0_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp1_dpdebugind +// base address: 0x0 +#define ixDP1_DP_DEBUG_ID 0x0000 +#define ixDP1_DP_DEBUG_K 0x00a2 +#define ixDP1_DP_DEBUG_L 0x00a3 +#define ixDP1_DP_DEBUG_M 0x00a4 +#define ixDP1_DP_DEBUG_G 0x00b4 +#define ixDP1_DP_DEBUG_O 0x00fb +#define ixDP1_DP_DEBUG_P 0x00fc +#define ixDP1_DP_DEBUG_Q 0x00fd +#define ixDP1_DP_DEBUG_R 0x00fe +#define ixDP1_DP_DEBUG_S 0x00ff + + +// addressBlock: dp1_dpfedebugind +// base address: 0x0 +#define ixDP1_DP_FE_DEBUG_ID 0x0000 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP1_DP_DEBUG_T 0x0090 +#define ixDP1_DP_DEBUG_U 0x0091 +#define ixDP1_DP_DEBUG_V 0x0092 +#define ixDP1_DP_DEBUG_W 0x0093 +#define ixDP1_DP_DEBUG_X 0x0094 +#define ixDP1_DP_DEBUG_Y 0x0095 +#define ixDP1_DP_DEBUG_Z 0x0096 +#define ixDP1_DP_DEBUG_1A 0x0097 +#define ixDP1_DP_DEBUG_1B 0x0098 +#define ixDP1_DP_DEBUG_I 0x00a0 +#define ixDP1_DP_DEBUG_J 0x00a1 +#define ixDP1_DP_DEBUG_N 0x00a2 +#define ixDP1_DP_DEBUG_H 0x00ac +#define ixDP1_DP_DEBUG_A 0x00ad +#define ixDP1_DP_DEBUG_B 0x00ae +#define ixDP1_DP_DEBUG_C 0x00af +#define ixDP1_DP_DEBUG_D 0x00b0 +#define ixDP1_DP_DEBUG_E 0x00b2 +#define ixDP1_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp1_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig1_digdebugind +// base address: 0x0 +#define ixDIG1_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig1_digfedebugind +// base address: 0x0 +#define ixDIG1_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG1_DIG_VPG_DEBUG0 0x000b +#define ixDIG1_DIG_VPG_DEBUG1 0x000c +#define ixDIG1_DIG_VPG_DEBUG2 0x000d +#define ixDIG1_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp2_dpdebugind +// base address: 0x0 +#define ixDP2_DP_DEBUG_ID 0x0000 +#define ixDP2_DP_DEBUG_K 0x00a2 +#define ixDP2_DP_DEBUG_L 0x00a3 +#define ixDP2_DP_DEBUG_M 0x00a4 +#define ixDP2_DP_DEBUG_G 0x00b4 +#define ixDP2_DP_DEBUG_O 0x00fb +#define ixDP2_DP_DEBUG_P 0x00fc +#define ixDP2_DP_DEBUG_Q 0x00fd +#define ixDP2_DP_DEBUG_R 0x00fe +#define ixDP2_DP_DEBUG_S 0x00ff + + +// addressBlock: dp2_dpfedebugind +// base address: 0x0 +#define ixDP2_DP_FE_DEBUG_ID 0x0000 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP2_DP_DEBUG_T 0x0090 +#define ixDP2_DP_DEBUG_U 0x0091 +#define ixDP2_DP_DEBUG_V 0x0092 +#define ixDP2_DP_DEBUG_W 0x0093 +#define ixDP2_DP_DEBUG_X 0x0094 +#define ixDP2_DP_DEBUG_Y 0x0095 +#define ixDP2_DP_DEBUG_Z 0x0096 +#define ixDP2_DP_DEBUG_1A 0x0097 +#define ixDP2_DP_DEBUG_1B 0x0098 +#define ixDP2_DP_DEBUG_I 0x00a0 +#define ixDP2_DP_DEBUG_J 0x00a1 +#define ixDP2_DP_DEBUG_N 0x00a2 +#define ixDP2_DP_DEBUG_H 0x00ac +#define ixDP2_DP_DEBUG_A 0x00ad +#define ixDP2_DP_DEBUG_B 0x00ae +#define ixDP2_DP_DEBUG_C 0x00af +#define ixDP2_DP_DEBUG_D 0x00b0 +#define ixDP2_DP_DEBUG_E 0x00b2 +#define ixDP2_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp2_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig2_digdebugind +// base address: 0x0 +#define ixDIG2_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig2_digfedebugind +// base address: 0x0 +#define ixDIG2_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG2_DIG_VPG_DEBUG0 0x000b +#define ixDIG2_DIG_VPG_DEBUG1 0x000c +#define ixDIG2_DIG_VPG_DEBUG2 0x000d +#define ixDIG2_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp3_dpdebugind +// base address: 0x0 +#define ixDP3_DP_DEBUG_ID 0x0000 +#define ixDP3_DP_DEBUG_K 0x00a2 +#define ixDP3_DP_DEBUG_L 0x00a3 +#define ixDP3_DP_DEBUG_M 0x00a4 +#define ixDP3_DP_DEBUG_G 0x00b4 +#define ixDP3_DP_DEBUG_O 0x00fb +#define ixDP3_DP_DEBUG_P 0x00fc +#define ixDP3_DP_DEBUG_Q 0x00fd +#define ixDP3_DP_DEBUG_R 0x00fe +#define ixDP3_DP_DEBUG_S 0x00ff + + +// addressBlock: dp3_dpfedebugind +// base address: 0x0 +#define ixDP3_DP_FE_DEBUG_ID 0x0000 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP3_DP_DEBUG_T 0x0090 +#define ixDP3_DP_DEBUG_U 0x0091 +#define ixDP3_DP_DEBUG_V 0x0092 +#define ixDP3_DP_DEBUG_W 0x0093 +#define ixDP3_DP_DEBUG_X 0x0094 +#define ixDP3_DP_DEBUG_Y 0x0095 +#define ixDP3_DP_DEBUG_Z 0x0096 +#define ixDP3_DP_DEBUG_1A 0x0097 +#define ixDP3_DP_DEBUG_1B 0x0098 +#define ixDP3_DP_DEBUG_I 0x00a0 +#define ixDP3_DP_DEBUG_J 0x00a1 +#define ixDP3_DP_DEBUG_N 0x00a2 +#define ixDP3_DP_DEBUG_H 0x00ac +#define ixDP3_DP_DEBUG_A 0x00ad +#define ixDP3_DP_DEBUG_B 0x00ae +#define ixDP3_DP_DEBUG_C 0x00af +#define ixDP3_DP_DEBUG_D 0x00b0 +#define ixDP3_DP_DEBUG_E 0x00b2 +#define ixDP3_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp3_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig3_digdebugind +// base address: 0x0 +#define ixDIG3_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig3_digfedebugind +// base address: 0x0 +#define ixDIG3_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG3_DIG_VPG_DEBUG0 0x000b +#define ixDIG3_DIG_VPG_DEBUG1 0x000c +#define ixDIG3_DIG_VPG_DEBUG2 0x000d +#define ixDIG3_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp4_dpdebugind +// base address: 0x0 +#define ixDP4_DP_DEBUG_ID 0x0000 +#define ixDP4_DP_DEBUG_K 0x00a2 +#define ixDP4_DP_DEBUG_L 0x00a3 +#define ixDP4_DP_DEBUG_M 0x00a4 +#define ixDP4_DP_DEBUG_G 0x00b4 +#define ixDP4_DP_DEBUG_O 0x00fb +#define ixDP4_DP_DEBUG_P 0x00fc +#define ixDP4_DP_DEBUG_Q 0x00fd +#define ixDP4_DP_DEBUG_R 0x00fe +#define ixDP4_DP_DEBUG_S 0x00ff + + +// addressBlock: dp4_dpfedebugind +// base address: 0x0 +#define ixDP4_DP_FE_DEBUG_ID 0x0000 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP4_DP_DEBUG_T 0x0090 +#define ixDP4_DP_DEBUG_U 0x0091 +#define ixDP4_DP_DEBUG_V 0x0092 +#define ixDP4_DP_DEBUG_W 0x0093 +#define ixDP4_DP_DEBUG_X 0x0094 +#define ixDP4_DP_DEBUG_Y 0x0095 +#define ixDP4_DP_DEBUG_Z 0x0096 +#define ixDP4_DP_DEBUG_1A 0x0097 +#define ixDP4_DP_DEBUG_1B 0x0098 +#define ixDP4_DP_DEBUG_I 0x00a0 +#define ixDP4_DP_DEBUG_J 0x00a1 +#define ixDP4_DP_DEBUG_N 0x00a2 +#define ixDP4_DP_DEBUG_H 0x00ac +#define ixDP4_DP_DEBUG_A 0x00ad +#define ixDP4_DP_DEBUG_B 0x00ae +#define ixDP4_DP_DEBUG_C 0x00af +#define ixDP4_DP_DEBUG_D 0x00b0 +#define ixDP4_DP_DEBUG_E 0x00b2 +#define ixDP4_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp4_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig4_digdebugind +// base address: 0x0 +#define ixDIG4_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig4_digfedebugind +// base address: 0x0 +#define ixDIG4_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG4_DIG_VPG_DEBUG0 0x000b +#define ixDIG4_DIG_VPG_DEBUG1 0x000c +#define ixDIG4_DIG_VPG_DEBUG2 0x000d +#define ixDIG4_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dio_misc_dio_miscdebugind +// base address: 0x0 +#define ixI2C_DEBUG_BUS 0x0002 +#define ixDIO_RBBMIF_DEBUG_0 0x0007 +#define ixDIO_RBBMIF_DEBUG_1 0x0008 +#define ixDIO_RBBMIF_DEBUG_2 0x0009 +#define ixDIO_RBBMIF_DEBUG_3 0x000a +#define ixDIGA_RBBMIF_DEBUG_0 0x000b +#define ixDIGA_RBBMIF_DEBUG_1 0x000c +#define ixDIGA_RBBMIF_DEBUG_2 0x000d +#define ixDIGA_RBBMIF_DEBUG_3 0x000e +#define ixDIGB_RBBMIF_DEBUG_0 0x000f +#define ixDIGB_RBBMIF_DEBUG_1 0x0010 +#define ixDIGB_RBBMIF_DEBUG_2 0x0011 +#define ixDIGB_RBBMIF_DEBUG_3 0x0012 +#define ixDIGC_RBBMIF_DEBUG_0 0x0013 +#define ixDIGC_RBBMIF_DEBUG_1 0x0014 +#define ixDIGC_RBBMIF_DEBUG_2 0x0015 +#define ixDIGC_RBBMIF_DEBUG_3 0x0016 +#define ixDIGD_RBBMIF_DEBUG_0 0x0017 +#define ixDIGD_RBBMIF_DEBUG_1 0x0018 +#define ixDIGD_RBBMIF_DEBUG_2 0x0019 +#define ixDIGD_RBBMIF_DEBUG_3 0x001a +#define ixDIGE_RBBMIF_DEBUG_0 0x001b +#define ixDIGE_RBBMIF_DEBUG_1 0x001c +#define ixDIGE_RBBMIF_DEBUG_2 0x001d +#define ixDIGE_RBBMIF_DEBUG_3 0x001e +#define ixDIGA_DME_DEBUG 0x0027 +#define ixDIGB_DME_DEBUG 0x0028 +#define ixDIGC_DME_DEBUG 0x0029 +#define ixDIGD_DME_DEBUG 0x002a +#define ixDIGE_DME_DEBUG 0x002b +#define ixDIGA_RESYNC_FIFO_DEBUG 0x0033 +#define ixDIGB_RESYNC_FIFO_DEBUG 0x0034 +#define ixDIGC_RESYNC_FIFO_DEBUG 0x0035 +#define ixDIGD_RESYNC_FIFO_DEBUG 0x0036 +#define ixDIGE_RESYNC_FIFO_DEBUG 0x0037 + + +// addressBlock: apg_apg_socclk_debugind +// base address: 0x0 +#define ixAPG_SOCCLK_DEBUG_ID 0x0000 +#define ixAPG_SOCCLK_DEBUG0 0x0001 + + +// addressBlock: apg_apg_encclk_debugind +// base address: 0x0 +#define ixAPG_ENCCLK_DEBUG_ID 0x0000 +#define ixAPG_ENCCLK_DEBUG0 0x0001 +#define ixAPG_ENCCLK_DEBUG1 0x0002 +#define ixAPG_ENCCLK_DEBUG2 0x0003 +#define ixAPG_ENCCLK_DEBUG3 0x0004 + + +// addressBlock: dcoh_top_dcoh_topdebugind +// base address: 0x0 +#define ixDCOH_TOP_DEBUG_ID 0x0000 + + +// addressBlock: dp_aux0_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX0_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX0_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX0_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux0_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX0_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX0_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX0_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX0_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX0_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX0_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX0_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX0_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX0_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux1_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX1_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX1_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX1_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux1_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX1_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX1_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX1_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX1_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX1_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX1_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX1_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX1_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX1_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux2_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX2_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX2_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX2_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux2_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX2_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX2_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX2_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX2_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX2_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX2_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX2_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX2_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX2_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux3_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX3_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX3_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX3_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux3_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX3_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX3_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX3_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX3_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX3_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX3_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX3_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX3_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX3_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux4_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX4_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX4_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX4_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux4_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX4_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX4_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX4_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX4_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX4_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX4_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX4_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX4_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX4_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: hpd0_hpddebugind +// base address: 0x0 +#define ixHPD0_HPD_DEBUG_ID 0x0000 +#define ixHPD0_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd1_hpddebugind +// base address: 0x0 +#define ixHPD1_HPD_DEBUG_ID 0x0000 +#define ixHPD1_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd2_hpddebugind +// base address: 0x0 +#define ixHPD2_HPD_DEBUG_ID 0x0000 +#define ixHPD2_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd3_hpddebugind +// base address: 0x0 +#define ixHPD3_HPD_DEBUG_ID 0x0000 +#define ixHPD3_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd4_hpddebugind +// base address: 0x0 +#define ixHPD4_HPD_DEBUG_ID 0x0000 +#define ixHPD4_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpo_top_hpo_topdebugind +// base address: 0x0 +#define ixHPO_TOP_DEBUG_ID 0x0000 + + +// addressBlock: hdmi_link_enc0_linkencdebugind +// base address: 0x0 +#define ixHDMI_LINK_ENC_DEBUG_ID 0x0000 + + +// addressBlock: hdmi_frl_enc0_frldebugind +// base address: 0x0 +#define ixHDMI_FRL_ENC_DEBUG_ID 0x0000 + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_hdmistreamclk_debugind +// base address: 0x0 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID 0x0000 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0 0x0001 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1 0x0002 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2 0x0003 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3 0x0004 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4 0x0005 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5 0x0006 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6 0x0007 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7 0x0008 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8 0x0009 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9 0x000a +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10 0x000b +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11 0x000c +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12 0x000d +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13 0x000e +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14 0x000f +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15 0x0010 + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_0 0x0001 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_1 0x0002 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_2 0x0003 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_3 0x0004 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_4 0x0005 + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc0_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc1_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc2_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc3_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_link_enc0_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym320_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: dp_link_enc1_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym321_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: dp_link_enc2_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym322_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: dp_link_enc3_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym323_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM0_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM1_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM2_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM3_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM4_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM5_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM6_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM7_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM8_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM9_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM10_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM11_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM12_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM13_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM14_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM15_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: dscc_dsccdebugind0 +// base address: 0x0 +#define ixDSCC_DEBUG_ID 0x0000 +#define ixDSCC_DEBUG_0 0x0001 +#define ixDSCC_DEBUG_1 0x0002 +#define ixDSCC_DEBUG_2 0x0003 +#define ixDSCC_DEBUG_3 0x0004 +#define ixDSCC_DEBUG_4 0x0005 +#define ixDSCC_DEBUG_5 0x0006 +#define ixDSCC_DEBUG_6 0x0007 +#define ixDSCC_DEBUG_7 0x0008 +#define ixDSCC_DEBUG_8 0x0009 +#define ixDSCC_DEBUG_9 0x000a +#define ixDSCC_DEBUG_10 0x000b +#define ixDSCC_DEBUG_11 0x000c +#define ixDSCC_DEBUG_12 0x000d +#define ixDSCC_DEBUG_13 0x000e +#define ixDSCC_DEBUG_14 0x000f +#define ixDSCC_DEBUG_15 0x0010 +#define ixDSCC_DEBUG_16 0x0011 +#define ixDSCC_DEBUG_17 0x0012 +#define ixDSCC_DEBUG_18 0x0013 +#define ixDSCC_DEBUG_19 0x0014 +#define ixDSCC_DEBUG_20 0x0015 +#define ixDSCC_DEBUG_21 0x0016 +#define ixDSCC_DEBUG_22 0x0017 +#define ixDSCC_DEBUG_23 0x0018 +#define ixDSCC_DEBUG_24 0x0019 +#define ixDSCC_DEBUG_25 0x001a +#define ixDSCC_DEBUG_26 0x001b +#define ixDSCC_DEBUG_27 0x001c +#define ixDSCC_DEBUG_28 0x001d + + +// addressBlock: dscc_dscc_dispclk_debugind0 +// base address: 0x0 +#define ixDSCC_DISPCLK_DEBUG_ID 0x0000 +#define ixDSCC_DISPCLK_DEBUG_0 0x0001 +#define ixDSCC_DISPCLK_DEBUG_1 0x0002 +#define ixDSCC_DISPCLK_DEBUG_2 0x0003 +#define ixDSCC_DISPCLK_DEBUG_3 0x0004 +#define ixDSCC_DISPCLK_DEBUG_4 0x0005 +#define ixDSCC_DISPCLK_DEBUG_5 0x0006 +#define ixDSCC_DISPCLK_DEBUG_6 0x0007 +#define ixDSCC_DISPCLK_DEBUG_7 0x0008 +#define ixDSCC_DISPCLK_DEBUG_8 0x0009 +#define ixDSCC_DISPCLK_DEBUG_9 0x000a +#define ixDSCC_DISPCLK_DEBUG_10 0x000b +#define ixDSCC_DISPCLK_DEBUG_11 0x000c +#define ixDSCC_DISPCLK_DEBUG_12 0x000d +#define ixDSCC_DISPCLK_DEBUG_13 0x000e +#define ixDSCC_DISPCLK_DEBUG_14 0x000f +#define ixDSCC_DISPCLK_DEBUG_15 0x0010 +#define ixDSCC_DISPCLK_DEBUG_16 0x0011 +#define ixDSCC_DISPCLK_DEBUG_17 0x0012 +#define ixDSCC_DISPCLK_DEBUG_18 0x0013 +#define ixDSCC_DISPCLK_DEBUG_19 0x0014 +#define ixDSCC_DISPCLK_DEBUG_20 0x0015 +#define ixDSCC_DISPCLK_DEBUG_21 0x0016 +#define ixDSCC_DISPCLK_DEBUG_22 0x0017 +#define ixDSCC_DISPCLK_DEBUG_23 0x0018 +#define ixDSCC_DISPCLK_DEBUG_24 0x0019 +#define ixDSCC_DISPCLK_DEBUG_25 0x001a +#define ixDSCC_DISPCLK_DEBUG_26 0x001b +#define ixDSCC_DISPCLK_DEBUG_27 0x001c +#define ixDSCC_DISPCLK_DEBUG_28 0x001d +#define ixDSCC_DISPCLK_DEBUG_29 0x001e +#define ixDSCC_DISPCLK_DEBUG_30 0x001f +#define ixDSCC_DISPCLK_DEBUG_31 0x0020 +#define ixDSCC_DISPCLK_DEBUG_32 0x0021 +#define ixDSCC_DISPCLK_DEBUG_33 0x0022 + + +// addressBlock: dsccif_dsccifdebugind +// base address: 0x0 +#define ixDSCCIF_DEBUG_ID 0x0000 +#define ixDSCCIF_DEBUG_0 0x0001 +#define ixDSCCIF_DEBUG_1 0x0002 + + +// addressBlock: dsc_top_dsc_topdebugind +// base address: 0x0 +#define ixDSC_TOP_DEBUG_ID 0x0000 +#define ixDSC_TOP_DEBUG_0 0x0001 +#define ixDSC_TOP_DEBUG_1 0x0002 +#define ixDSC_TOP_DEBUG_2 0x0003 + + +// addressBlock: dpia_port0_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT0_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT0_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port1_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT1_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT1_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port2_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT2_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT2_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port3_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT3_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT3_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port4_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT4_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT4_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port5_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT5_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT5_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port_ml0_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml1_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml2_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml3_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml4_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml5_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_aux0_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux1_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux2_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux3_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux4_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux5_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_mu0_dpia_mu_debugind +// base address: 0x0 +#define ixDPIA_MU_DEBUG_ID 0x0000 + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x0 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x20 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x40 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x60 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x80 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0xa0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0xc0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0xe0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDP_DTO_DBUF_EN 0x0044 +#define regDP_DTO_DBUF_EN_BASE_IDX 1 +#define regDSCCLK3_DTO_PARAM 0x0045 +#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 +#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL4 0x0049 +#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 +#define regDPSTREAMCLK_CNTL 0x004a +#define regDPSTREAMCLK_CNTL_BASE_IDX 1 +#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDCCG_PERFMON_CNTL2 0x004e +#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define regDPIASYMCLK_CNTL 0x004f +#define regDPIASYMCLK_CNTL_BASE_IDX 1 +#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 +#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 +#define regOTG_ADD_DROP_PIXEL_CNTL 0x0056 +#define regOTG_ADD_DROP_PIXEL_CNTL_BASE_IDX 1 +#define regDPREFCLK_CNTL 0x0058 +#define regDPREFCLK_CNTL_BASE_IDX 1 +#define regDCE_VERSION 0x005e +#define regDCE_VERSION_BASE_IDX 1 +#define regSYMCLK32_SE_CNTL 0x0065 +#define regSYMCLK32_SE_CNTL_BASE_IDX 1 +#define regSYMCLK32_LE_CNTL 0x0066 +#define regSYMCLK32_LE_CNTL_BASE_IDX 1 +#define regDTBCLK_P_CNTL 0x0068 +#define regDTBCLK_P_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL5 0x0069 +#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 +#define regDSCCLK0_DTO_PARAM 0x006c +#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK1_DTO_PARAM 0x006d +#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK2_DTO_PARAM 0x006e +#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 +#define regOTG_PIXEL_RATE_DIV 0x006f +#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 +#define regMILLISECOND_TIME_BASE_DIV 0x0070 +#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define regDCCG_PERFMON_CNTL 0x0073 +#define regDCCG_PERFMON_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL 0x0074 +#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_CAC_STATUS 0x0077 +#define regDCCG_CAC_STATUS_BASE_IDX 1 +#define regMICROSECOND_TIME_BASE_DIV 0x007b +#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL2 0x007c +#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_DISP_CNTL_REG 0x007f +#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define regOTG0_PIXEL_RATE_CNTL 0x0080 +#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO0_PHASE 0x0081 +#define regDP_DTO0_PHASE_BASE_IDX 1 +#define regDP_DTO0_MODULO 0x0082 +#define regDP_DTO0_MODULO_BASE_IDX 1 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG1_PIXEL_RATE_CNTL 0x0084 +#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO1_PHASE 0x0085 +#define regDP_DTO1_PHASE_BASE_IDX 1 +#define regDP_DTO1_MODULO 0x0086 +#define regDP_DTO1_MODULO_BASE_IDX 1 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG2_PIXEL_RATE_CNTL 0x0088 +#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO2_PHASE 0x0089 +#define regDP_DTO2_PHASE_BASE_IDX 1 +#define regDP_DTO2_MODULO 0x008a +#define regDP_DTO2_MODULO_BASE_IDX 1 +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG3_PIXEL_RATE_CNTL 0x008c +#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO3_PHASE 0x008d +#define regDP_DTO3_PHASE_BASE_IDX 1 +#define regDP_DTO3_MODULO 0x008e +#define regDP_DTO3_MODULO_BASE_IDX 1 +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDPPCLK0_DTO_PARAM 0x0099 +#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK1_DTO_PARAM 0x009a +#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK2_DTO_PARAM 0x009b +#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK3_DTO_PARAM 0x009c +#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 +#define regDCCG_CAC_STATUS2 0x009f +#define regDCCG_CAC_STATUS2_BASE_IDX 1 +#define regSYMCLKA_CLOCK_ENABLE 0x00a0 +#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKB_CLOCK_ENABLE 0x00a1 +#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKC_CLOCK_ENABLE 0x00a2 +#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKD_CLOCK_ENABLE 0x00a3 +#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKE_CLOCK_ENABLE 0x00a4 +#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define regDCCG_SOFT_RESET 0x00a6 +#define regDCCG_SOFT_RESET_BASE_IDX 1 +#define regDSCCLK_DTO_CTRL 0x00a7 +#define regDSCCLK_DTO_CTRL_BASE_IDX 1 +#define regDPPCLK_CTRL 0x00a8 +#define regDPPCLK_CTRL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL6 0x00a9 +#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1 +#define regSYMCLK_PSP_CNTL 0x00aa +#define regSYMCLK_PSP_CNTL_BASE_IDX 1 +#define regDCCG_AUDIO_DTO_SOURCE 0x00ab +#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_PHASE 0x00ac +#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_MODULE 0x00ad +#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_PHASE 0x00ae +#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_MODULE 0x00af +#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define regDPPCLK_DTO_CTRL 0x00b6 +#define regDPPCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_CTRL 0x00b8 +#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define regFORCE_SYMCLK_DISABLE 0x00ba +#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define regDCCG_TEST_CLK_SEL 0x00be +#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 +#define regHDMICHARCLK0_CLOCK_CNTL 0x004a +#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 +#define regPHYASYMCLK_CLOCK_CNTL 0x0052 +#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 +#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 +#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 +#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYESYMCLK_CLOCK_CNTL 0x0056 +#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regHDMISTREAMCLK_CNTL 0x0059 +#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 +#define regDCCG_GATE_DISABLE_CNTL3 0x005a +#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 +#define regHDMISTREAMCLK0_DTO_PARAM 0x005b +#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 +#define regDPIACLK_810M_DTO_PHASE 0x0064 +#define regDPIACLK_810M_DTO_PHASE_BASE_IDX 2 +#define regDPIACLK_540M_DTO_PHASE 0x0065 +#define regDPIACLK_540M_DTO_PHASE_BASE_IDX 2 +#define regDPIACLK_DTO_CNTL 0x0066 +#define regDPIACLK_DTO_CNTL_BASE_IDX 2 +#define regDPIACLK_810M_DTO_MODULO 0x0068 +#define regDPIACLK_810M_DTO_MODULO_BASE_IDX 2 +#define regDPIACLK_540M_DTO_MODULO 0x0069 +#define regDPIACLK_540M_DTO_MODULO_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define regDENTIST_DISPCLK_CNTL 0x0064 +#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX 0x3774 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA 0x3775 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +// base address: 0x0 +#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 +#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 +#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 +#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CNTL 0x0003 +#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 +#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 +#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 +#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_HI 0x0007 +#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_LOW 0x0008 +#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +// base address: 0x30 +#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c +#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d +#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e +#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CNTL 0x000f +#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 +#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 +#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 +#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_HI 0x0013 +#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_LOW 0x0014 +#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define regDOMAIN0_PG_CONFIG 0x0080 +#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN0_PG_STATUS 0x0081 +#define regDOMAIN0_PG_STATUS_BASE_IDX 2 +#define regDOMAIN1_PG_CONFIG 0x0082 +#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN1_PG_STATUS 0x0083 +#define regDOMAIN1_PG_STATUS_BASE_IDX 2 +#define regDOMAIN2_PG_CONFIG 0x0084 +#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN2_PG_STATUS 0x0085 +#define regDOMAIN2_PG_STATUS_BASE_IDX 2 +#define regDOMAIN3_PG_CONFIG 0x0086 +#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN3_PG_STATUS 0x0087 +#define regDOMAIN3_PG_STATUS_BASE_IDX 2 +#define regDOMAIN16_PG_CONFIG 0x0089 +#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN16_PG_STATUS 0x008a +#define regDOMAIN16_PG_STATUS_BASE_IDX 2 +#define regDOMAIN17_PG_CONFIG 0x008b +#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN17_PG_STATUS 0x008c +#define regDOMAIN17_PG_STATUS_BASE_IDX 2 +#define regDOMAIN18_PG_CONFIG 0x008d +#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN18_PG_STATUS 0x008e +#define regDOMAIN18_PG_STATUS_BASE_IDX 2 +#define regDOMAIN19_PG_CONFIG 0x008f +#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN19_PG_STATUS 0x0090 +#define regDOMAIN19_PG_STATUS_BASE_IDX 2 +#define regDOMAIN22_PG_CONFIG 0x0092 +#define regDOMAIN22_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN22_PG_STATUS 0x0093 +#define regDOMAIN22_PG_STATUS_BASE_IDX 2 +#define regDOMAIN23_PG_CONFIG 0x0094 +#define regDOMAIN23_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN23_PG_STATUS 0x0095 +#define regDOMAIN23_PG_STATUS_BASE_IDX 2 +#define regDOMAIN24_PG_CONFIG 0x0096 +#define regDOMAIN24_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN24_PG_STATUS 0x0097 +#define regDOMAIN24_PG_STATUS_BASE_IDX 2 +#define regDOMAIN25_PG_CONFIG 0x0098 +#define regDOMAIN25_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN25_PG_STATUS 0x0099 +#define regDOMAIN25_PG_STATUS_BASE_IDX 2 +#define regDOMAIN26_PG_CONFIG 0x009a +#define regDOMAIN26_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN26_PG_STATUS 0x009b +#define regDOMAIN26_PG_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS 0x009c +#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_2 0x009d +#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_3 0x009e +#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_1 0x009f +#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_2 0x00a0 +#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_3 0x00a1 +#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 +#define regDC_IP_REQUEST_CNTL 0x00a2 +#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 +#define regLONO_MEM_PWR_REQ_CNTL 0x00a6 +#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +// base address: 0x2f8 +#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be +#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf +#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 +#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 +#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 +#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 +#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 +#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_HI 0x00c5 +#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_LOW 0x00c6 +#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define regCC_DC_PIPE_DIS 0x00ca +#define regCC_DC_PIPE_DIS_BASE_IDX 2 +#define regDMU_CLK_CNTL 0x00cb +#define regDMU_CLK_CNTL_BASE_IDX 2 +#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd +#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define regSMU_INTERRUPT_CONTROL 0x00ce +#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define regZSC_CNTL 0x00cf +#define regZSC_CNTL_BASE_IDX 2 +#define regZSC_CNTL2 0x00d0 +#define regZSC_CNTL2_BASE_IDX 2 +#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 +#define regZSC_STATUS 0x00d7 +#define regZSC_STATUS_BASE_IDX 2 +#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8 +#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 +#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9 +#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 +#define regZPR_CLK_UNGATE_DELAY 0x00da +#define regZPR_CLK_UNGATE_DELAY_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define regDC_GPU_TIMER_READ 0x0128 +#define regDC_GPU_TIMER_READ_BASE_IDX 2 +#define regDC_GPU_TIMER_READ_CNTL 0x0129 +#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS 0x012a +#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 +#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 +#define regDCCG_INTERRUPT_DEST 0x0148 +#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST 0x0149 +#define regDMU_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST2 0x014a +#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST 0x014b +#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST2 0x014c +#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define regMMHUBBUB_INTERRUPT_DEST 0x014d +#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define regWB_INTERRUPT_DEST 0x014e +#define regWB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST 0x014f +#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST2 0x0151 +#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regMPC_INTERRUPT_DEST 0x0153 +#define regMPC_INTERRUPT_DEST_BASE_IDX 2 +#define regOPP_INTERRUPT_DEST 0x0154 +#define regOPP_INTERRUPT_DEST_BASE_IDX 2 +#define regOPTC_INTERRUPT_DEST 0x0155 +#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG0_INTERRUPT_DEST 0x0156 +#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG1_INTERRUPT_DEST 0x0157 +#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG2_INTERRUPT_DEST 0x0158 +#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG3_INTERRUPT_DEST 0x0159 +#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG4_INTERRUPT_DEST 0x015a +#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG5_INTERRUPT_DEST 0x015b +#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define regDIG_INTERRUPT_DEST 0x015c +#define regDIG_INTERRUPT_DEST_BASE_IDX 2 +#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d +#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define regDIO_INTERRUPT_DEST 0x015f +#define regDIO_INTERRUPT_DEST_BASE_IDX 2 +#define regDCIO_INTERRUPT_DEST 0x0160 +#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define regHPD_INTERRUPT_DEST 0x0161 +#define regHPD_INTERRUPT_DEST_BASE_IDX 2 +#define regAZ_INTERRUPT_DEST 0x0162 +#define regAZ_INTERRUPT_DEST_BASE_IDX 2 +#define regAUX_INTERRUPT_DEST 0x0163 +#define regAUX_INTERRUPT_DEST_BASE_IDX 2 +#define regDSC_INTERRUPT_DEST 0x0164 +#define regDSC_INTERRUPT_DEST_BASE_IDX 2 +#define regHPO_INTERRUPT_DEST 0x0165 +#define regHPO_INTERRUPT_DEST_BASE_IDX 2 +#define regDPP_INTERRUPT_DEST 0x0166 +#define regDPP_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +// base address: 0x0 +#define regDMCUB_RBBMIF_SEC_CNTL 0x017a +#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define regRBBMIF_TIMEOUT 0x017f +#define regRBBMIF_TIMEOUT_BASE_IDX 2 +#define regRBBMIF_STATUS 0x0180 +#define regRBBMIF_STATUS_BASE_IDX 2 +#define regRBBMIF_STATUS_2 0x0181 +#define regRBBMIF_STATUS_2_BASE_IDX 2 +#define regRBBMIF_INT_STATUS 0x0182 +#define regRBBMIF_INT_STATUS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS 0x0183 +#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS_2 0x0184 +#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define regRBBMIF_STATUS_FLAG 0x0185 +#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define regDMCUB_REGION0_OFFSET 0x018e +#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION0_OFFSET_HIGH 0x018f +#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET 0x0190 +#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 +#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET 0x0192 +#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 +#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET 0x0196 +#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 +#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET 0x0198 +#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 +#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET 0x019a +#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET_HIGH 0x019b +#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET 0x019c +#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET_HIGH 0x019d +#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION0_TOP_ADDRESS 0x019e +#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION1_TOP_ADDRESS 0x019f +#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 +#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 +#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 +#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 +#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 +#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa +#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab +#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac +#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad +#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae +#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af +#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 +#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 +#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 +#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba +#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET 0x01bb +#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc +#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET 0x01bd +#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be +#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET 0x01bf +#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 +#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 +#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ENABLE 0x01c5 +#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ACK 0x01c6 +#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INTERRUPT_STATUS 0x01c7 +#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_INTERRUPT_TYPE 0x01c8 +#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 +#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca +#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb +#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc +#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd +#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_SEC_CNTL 0x01ce +#define regDMCUB_SEC_CNTL_BASE_IDX 2 +#define regDMCUB_MEM_CNTL 0x01cf +#define regDMCUB_MEM_CNTL_BASE_IDX 2 +#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 +#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX0_SIZE 0x01d1 +#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX0_WPTR 0x01d2 +#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX0_RPTR 0x01d3 +#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 +#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX1_SIZE 0x01d5 +#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX1_WPTR 0x01d6 +#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_RPTR 0x01d7 +#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 +#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX0_SIZE 0x01d9 +#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX0_WPTR 0x01da +#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_RPTR 0x01db +#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc +#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX1_SIZE 0x01dd +#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX1_WPTR 0x01de +#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_RPTR 0x01df +#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER0 0x01e0 +#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER1 0x01e1 +#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define regDMCUB_TIMER_WINDOW 0x01e2 +#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define regDMCUB_SCRATCH0 0x01e3 +#define regDMCUB_SCRATCH0_BASE_IDX 2 +#define regDMCUB_SCRATCH1 0x01e4 +#define regDMCUB_SCRATCH1_BASE_IDX 2 +#define regDMCUB_SCRATCH2 0x01e5 +#define regDMCUB_SCRATCH2_BASE_IDX 2 +#define regDMCUB_SCRATCH3 0x01e6 +#define regDMCUB_SCRATCH3_BASE_IDX 2 +#define regDMCUB_SCRATCH4 0x01e7 +#define regDMCUB_SCRATCH4_BASE_IDX 2 +#define regDMCUB_SCRATCH5 0x01e8 +#define regDMCUB_SCRATCH5_BASE_IDX 2 +#define regDMCUB_SCRATCH6 0x01e9 +#define regDMCUB_SCRATCH6_BASE_IDX 2 +#define regDMCUB_SCRATCH7 0x01ea +#define regDMCUB_SCRATCH7_BASE_IDX 2 +#define regDMCUB_SCRATCH8 0x01eb +#define regDMCUB_SCRATCH8_BASE_IDX 2 +#define regDMCUB_SCRATCH9 0x01ec +#define regDMCUB_SCRATCH9_BASE_IDX 2 +#define regDMCUB_SCRATCH10 0x01ed +#define regDMCUB_SCRATCH10_BASE_IDX 2 +#define regDMCUB_SCRATCH11 0x01ee +#define regDMCUB_SCRATCH11_BASE_IDX 2 +#define regDMCUB_SCRATCH12 0x01ef +#define regDMCUB_SCRATCH12_BASE_IDX 2 +#define regDMCUB_SCRATCH13 0x01f0 +#define regDMCUB_SCRATCH13_BASE_IDX 2 +#define regDMCUB_SCRATCH14 0x01f1 +#define regDMCUB_SCRATCH14_BASE_IDX 2 +#define regDMCUB_SCRATCH15 0x01f2 +#define regDMCUB_SCRATCH15_BASE_IDX 2 +#define regDMCUB_SCRATCH16 0x01f3 +#define regDMCUB_SCRATCH16_BASE_IDX 2 +#define regDMCUB_SCRATCH17 0x01f4 +#define regDMCUB_SCRATCH17_BASE_IDX 2 +#define regDMCUB_SCRATCH18 0x01f5 +#define regDMCUB_SCRATCH18_BASE_IDX 2 +#define regDMCUB_CNTL 0x01f6 +#define regDMCUB_CNTL_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN0 0x01f7 +#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN1 0x01f8 +#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define regDMCUB_GPINT_DATAOUT 0x01f9 +#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb +#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define regDMCUB_MEM_PWR_CNTL 0x01fc +#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regDMCUB_TIMER_CURRENT 0x01fd +#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define regDMCUB_PROC_ID 0x01ff +#define regDMCUB_PROC_ID_BASE_IDX 2 +#define regDMCUB_CNTL2 0x0200 +#define regDMCUB_CNTL2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN2 0x0215 +#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN3 0x0216 +#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN4 0x0217 +#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN5 0x0218 +#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN6 0x0219 +#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 +#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a +#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 +#define regDMCUB_SCRATCH19 0x021b +#define regDMCUB_SCRATCH19_BASE_IDX 2 +#define regDMCUB_SCRATCH20 0x021c +#define regDMCUB_SCRATCH20_BASE_IDX 2 +#define regDMCUB_SCRATCH21 0x021d +#define regDMCUB_SCRATCH21_BASE_IDX 2 +#define regDMCUB_SCRATCH22 0x021e +#define regDMCUB_SCRATCH22_BASE_IDX 2 +#define regDMCUB_SCRATCH23 0x021f +#define regDMCUB_SCRATCH23_BASE_IDX 2 +#define regHOST_INTERRUPT_CSR 0x0222 +#define regHOST_INTERRUPT_CSR_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_RDY 0x0223 +#define regDMCUB_REG_INBOX0_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG0 0x0224 +#define regDMCUB_REG_INBOX0_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG1 0x0225 +#define regDMCUB_REG_INBOX0_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG2 0x0226 +#define regDMCUB_REG_INBOX0_MSG2_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG3 0x0227 +#define regDMCUB_REG_INBOX0_MSG3_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG4 0x0228 +#define regDMCUB_REG_INBOX0_MSG4_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG5 0x0229 +#define regDMCUB_REG_INBOX0_MSG5_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG6 0x022a +#define regDMCUB_REG_INBOX0_MSG6_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG7 0x022b +#define regDMCUB_REG_INBOX0_MSG7_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG8 0x022c +#define regDMCUB_REG_INBOX0_MSG8_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG9 0x022d +#define regDMCUB_REG_INBOX0_MSG9_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG10 0x022e +#define regDMCUB_REG_INBOX0_MSG10_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG11 0x022f +#define regDMCUB_REG_INBOX0_MSG11_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG12 0x0230 +#define regDMCUB_REG_INBOX0_MSG12_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG13 0x0231 +#define regDMCUB_REG_INBOX0_MSG13_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG14 0x0232 +#define regDMCUB_REG_INBOX0_MSG14_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_RSP 0x0233 +#define regDMCUB_REG_INBOX0_RSP_BASE_IDX 2 +#define regDMCUB_REG_OUTBOX0_RDY 0x0234 +#define regDMCUB_REG_OUTBOX0_RDY_BASE_IDX 2 +#define regDMCUB_REG_OUTBOX0_MSG0 0x0235 +#define regDMCUB_REG_OUTBOX0_MSG0_BASE_IDX 2 +#define regDMCUB_REG_OUTBOX0_RSP 0x0236 +#define regDMCUB_REG_OUTBOX0_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_RDY 0x0237 +#define regDMCUB_REG_INBOX1_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_MSG0 0x0238 +#define regDMCUB_REG_INBOX1_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_MSG1 0x0239 +#define regDMCUB_REG_INBOX1_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_RSP 0x023a +#define regDMCUB_REG_INBOX1_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_INTERRUPT_CSR 0x023b +#define regDMCUB_REG_INBOX1_INTERRUPT_CSR_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_RDY 0x023c +#define regDMCUB_REG_INBOX2_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_MSG0 0x023d +#define regDMCUB_REG_INBOX2_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_MSG1 0x023e +#define regDMCUB_REG_INBOX2_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_RSP 0x023f +#define regDMCUB_REG_INBOX2_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_RDY 0x0240 +#define regDMCUB_REG_INBOX3_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_MSG0 0x0241 +#define regDMCUB_REG_INBOX3_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_MSG1 0x0242 +#define regDMCUB_REG_INBOX3_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_RSP 0x0243 +#define regDMCUB_REG_INBOX3_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_RDY 0x0244 +#define regDMCUB_REG_INBOX4_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_MSG0 0x0245 +#define regDMCUB_REG_INBOX4_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_MSG1 0x0246 +#define regDMCUB_REG_INBOX4_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_RSP 0x0247 +#define regDMCUB_REG_INBOX4_RSP_BASE_IDX 2 +#define regDMCUB_IDLE_HYSTERESIS_CSR 0x0249 +#define regDMCUB_IDLE_HYSTERESIS_CSR_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_STATUS 0x0274 +#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_PITCH 0x0275 +#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS 0x0276 +#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS2 0x0277 +#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS 0x0278 +#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS2 0x0279 +#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS 0x027a +#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS2 0x027b +#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS 0x027c +#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS2 0x027d +#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define regMCIF_WB_ARBITRATION_CONTROL 0x027e +#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SCLK_CHANGE 0x027f +#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 +#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 +#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 +#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C 0x0284 +#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 +#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C 0x0288 +#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y 0x028a +#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C 0x028c +#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y 0x028e +#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C 0x0290 +#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 +#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 +#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 +#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define regMULTI_LEVEL_QOS_CTRL 0x0297 +#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define regMCIF_WB_SECURITY_LEVEL 0x0298 +#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 +#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 +#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a +#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c +#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e +#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 +#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 +#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 +#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 +#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 +#define regMCIF_WB_VMID_CONTROL 0x02a8 +#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 +#define regMCIF_WB_MIN_TTO 0x02a9 +#define regMCIF_WB_MIN_TTO_BASE_IDX 2 +#define regMCIF_WB_TMZ 0x02b2 +#define regMCIF_WB_TMZ_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define regMCIF_WB_WATERMARK 0x02ab +#define regMCIF_WB_WATERMARK_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONFIG 0x02ac +#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad +#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 +#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 +#define regMMHUBBUB_MIN_TTO 0x02b1 +#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 +#define regMMHUBBUB_CTRL 0x0333 +#define regMMHUBBUB_CTRL_BASE_IDX 2 +#define regWBIF_SMU_WM_CONTROL 0x0334 +#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 +#define regWBIF0_MISC_CTRL 0x0335 +#define regWBIF0_MISC_CTRL_BASE_IDX 2 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_STATUS 0x033e +#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_CNTL 0x033f +#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regMMHUBBUB_CLOCK_CNTL 0x0340 +#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regMMHUBBUB_SOFT_RESET 0x0341 +#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDMU_IF_ERR_STATUS 0x0345 +#define regDMU_IF_ERR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_CLIENT_UNIT_ID 0x0346 +#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_SECURITY_CFG 0x0347 +#define regMMHUBBUB_WARMUP_SECURITY_CFG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 +#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0xd48 +#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x0352 +#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353 +#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON3_PERFCOUNTER_STATE 0x0354 +#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CNTL 0x0355 +#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CNTL2 0x0356 +#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357 +#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358 +#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_HI 0x0359 +#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_LOW 0x035a +#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define regAZ_CLOCK_CNTL 0x0372 +#define regAZ_CLOCK_CNTL_BASE_IDX 2 +#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373 +#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2 +#define regAZ_STRAPS 0x0374 +#define regAZ_STRAPS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +// base address: 0xde8 +#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x037a +#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b +#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON4_PERFCOUNTER_STATE 0x037c +#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CNTL 0x037d +#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CNTL2 0x037e +#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f +#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380 +#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_HI 0x0381 +#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_LOW 0x0382 +#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO 0x03c3 +#define regAZALIA_AUDIO_DTO_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define regAZALIA_SOCCLK_CONTROL 0x03c5 +#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define regAZALIA_DATA_DMA_CONTROL 0x03c7 +#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_BDL_DMA_CONTROL 0x03c8 +#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define regAZALIA_CORB_DMA_CONTROL 0x03ca +#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_RESULT 0x03dd +#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL0 0x03e3 +#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL1 0x03e4 +#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL2 0x03e5 +#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL3 0x03e6 +#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC0_RESULT 0x03e7 +#define regAZALIA_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL0 0x03e8 +#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL1 0x03e9 +#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL2 0x03ea +#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL3 0x03eb +#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC1_RESULT 0x03ec +#define regAZALIA_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_MEM_PWR_CTRL 0x03ee +#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define regAZALIA_MEM_PWR_STATUS 0x03ef +#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +// base address: 0x0 +#define regDCHUBBUB_SDPIF_CFG0 0x046f +#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG1 0x0470 +#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG2 0x0471 +#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 +#define regVM_REQUEST_PHYSICAL 0x0472 +#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 +#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 +#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_BASE 0x0475 +#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_TOP 0x0476 +#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define regDCN_VM_FB_OFFSET 0x0477 +#define regDCN_VM_FB_OFFSET_BASE_IDX 2 +#define regDCN_VM_AGP_BOT 0x0478 +#define regDCN_VM_AGP_BOT_BASE_IDX 2 +#define regDCN_VM_AGP_TOP 0x0479 +#define regDCN_VM_AGP_TOP_BASE_IDX 2 +#define regDCN_VM_AGP_BASE 0x047a +#define regDCN_VM_AGP_BASE_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b +#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c +#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL 0x0483 +#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0484 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 +#define regSDPIF_REQUEST_RATE_LIMIT 0x0485 +#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0486 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0487 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +// base address: 0x0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define regDCHUBBUB_CRC_CTRL 0x04b1 +#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_R 0x04b2 +#define regDCHUBBUB_CRC0_VAL_R_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_G 0x04b3 +#define regDCHUBBUB_CRC0_VAL_G_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_B 0x04b4 +#define regDCHUBBUB_CRC0_VAL_B_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_A 0x04b5 +#define regDCHUBBUB_CRC0_VAL_A_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_R 0x04b6 +#define regDCHUBBUB_CRC1_VAL_R_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_G 0x04b7 +#define regDCHUBBUB_CRC1_VAL_G_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_B 0x04b8 +#define regDCHUBBUB_CRC1_VAL_B_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_A 0x04b9 +#define regDCHUBBUB_CRC1_VAL_A_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT_CNTL 0x04ba +#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT0 0x04bb +#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT1 0x04bc +#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT2 0x04bd +#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 +#define regDCHUBBUB_COMPBUF_CTRL 0x04be +#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET0_CTRL 0x04bf +#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET1_CTRL 0x04c0 +#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET2_CTRL 0x04c1 +#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET3_CTRL 0x04c2 +#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c4 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c5 +#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c6 +#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_STATUS 0x04c7 +#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regCOMPBUF_RESERVED_SPACE 0x04c8 +#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 +#define regDCHUBBUB_DEBUG_CTRL_0 0x04c9 +#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX 0x04cc +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA 0x04cd +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +// base address: 0x0 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04ef +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define regDCHUBBUB_ARB_SAT_LEVEL 0x04f0 +#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define regDCHUBBUB_ARB_QOS_FORCE 0x04f1 +#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04f2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_HVM_STATE_CNTL 0x04f3 +#define regDCHUBBUB_ARB_DRAM_HVM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04f4 +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04f5 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04f6 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04f7 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04f8 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x04f9 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x04fa +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x04fb +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x04fc +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x04fd +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x04fe +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x04ff +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0500 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0501 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0502 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0503 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0504 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0505 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x0506 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x0507 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x0508 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0509 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050a +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050b +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x050c +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x050d +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x050e +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x050f +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0510 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0511 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x0512 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x0513 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0514 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0515 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0516 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x0517 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0518 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x0519 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051a +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051c +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x051d +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x051e +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 +#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_MALL_CNTL 0x0523 +#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0524 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0525 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_LSB 0x0526 +#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_MSB 0x0527 +#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_LSB 0x0528 +#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_MSB 0x0529 +#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_LSB 0x052a +#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_MSB 0x052b +#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_LSB 0x052c +#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_MSB 0x052d +#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define regVTG0_CONTROL 0x052e +#define regVTG0_CONTROL_BASE_IDX 2 +#define regVTG1_CONTROL 0x052f +#define regVTG1_CONTROL_BASE_IDX 2 +#define regVTG2_CONTROL 0x0530 +#define regVTG2_CONTROL_BASE_IDX 2 +#define regVTG3_CONTROL 0x0531 +#define regVTG3_CONTROL_BASE_IDX 2 +#define regDCHUBBUB_SOFT_RESET 0x0532 +#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDCHUBBUB_CLOCK_CNTL 0x0533 +#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regDCFCLK_CNTL 0x0534 +#define regDCFCLK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0535 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0536 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define regDCHUBBUB_VLINE_SNAPSHOT 0x0537 +#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define regDCHUBBUB_CTRL_STATUS 0x0538 +#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053e +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053f +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0540 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define regFMON_CTRL 0x0541 +#define regFMON_CTRL_BASE_IDX 2 +#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0542 +#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCHUBBUB_TEST_DEBUG_DATA 0x0543 +#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0x1534 +#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x054d +#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e +#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON5_PERFCOUNTER_STATE 0x054f +#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CNTL 0x0550 +#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CNTL2 0x0551 +#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552 +#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553 +#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_HI 0x0554 +#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_LOW 0x0555 +#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define regDCN_VM_CONTEXT0_CNTL 0x0559 +#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_CNTL 0x0560 +#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_CNTL 0x0567 +#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_CNTL 0x056e +#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_CNTL 0x0575 +#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_CNTL 0x057c +#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_CNTL 0x0583 +#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_CNTL 0x058a +#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_CNTL 0x0591 +#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_CNTL 0x0598 +#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_CNTL 0x059f +#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_CNTL 0x05a6 +#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_CNTL 0x05ad +#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_CNTL 0x05b4 +#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_CNTL 0x05bb +#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_CNTL 0x05c2 +#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define regDCN_VM_FAULT_CNTL 0x05cb +#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define regDCN_VM_FAULT_STATUS 0x05cc +#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_MSB 0x05cd +#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_LSB 0x05ce +#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_CNTL 0x05f3 +#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP0_HUBP_CLK_CNTL 0x05f4 +#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 +#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 +#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 +#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG 0x05f9 +#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP0_HUBP_DEBUG_CTRL 0x05fa +#define regHUBP0_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK 0x05fb +#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK 0x05fc +#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MALL_STATUS 0x05ff +#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 +#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 +#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_0 0x0643 +#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_1 0x0644 +#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ0_DST_DIMENSIONS 0x0645 +#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ0_DST_AFTER_SCALER 0x0646 +#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 +#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 +#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 +#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a +#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b +#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c +#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d +#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e +#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f +#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 +#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 +#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 +#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 +#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 +#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 +#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 +#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 +#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 +#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY 0x065a +#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ0_CURSOR_SETTINGS 0x065b +#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 +#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 +#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 +#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 +#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 +#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 +#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 +#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a +#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b +#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define regHUBPRET0_HUBPRET_CONTROL 0x066c +#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define regCURSOR0_0_CURSOR_CONTROL 0x0678 +#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SIZE 0x067b +#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_POSITION 0x067c +#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_CNTL 0x0684 +#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_STATUS 0x0686 +#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_CONTROL 0x0689 +#define regCURSOR0_0_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW 0x068a +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH 0x068b +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM 0x068c +#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a74 +#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x069d +#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e +#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON6_PERFCOUNTER_STATE 0x069f +#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CNTL 0x06a0 +#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CNTL2 0x06a1 +#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2 +#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3 +#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_HI 0x06a4 +#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_LOW 0x06a5 +#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_CNTL 0x06cf +#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP1_HUBP_CLK_CNTL 0x06d0 +#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 +#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 +#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 +#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG 0x06d5 +#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP1_HUBP_DEBUG_CTRL 0x06d6 +#define regHUBP1_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK 0x06d7 +#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK 0x06d8 +#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MALL_STATUS 0x06db +#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 +#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 +#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_0 0x071f +#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_1 0x0720 +#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ1_DST_DIMENSIONS 0x0721 +#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ1_DST_AFTER_SCALER 0x0722 +#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 +#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 +#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 +#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 +#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 +#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 +#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 +#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a +#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b +#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c +#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_0 0x072d +#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_1 0x072e +#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_2 0x072f +#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 +#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 +#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 +#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 +#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 +#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 +#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ1_CURSOR_SETTINGS 0x0737 +#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e +#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f +#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 +#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 +#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 +#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 +#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 +#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define regHUBPRET1_HUBPRET_CONTROL 0x0748 +#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define regCURSOR0_1_CURSOR_CONTROL 0x0754 +#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SIZE 0x0757 +#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_POSITION 0x0758 +#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_CNTL 0x0760 +#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_STATUS 0x0762 +#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_CONTROL 0x0765 +#define regCURSOR0_1_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW 0x0766 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH 0x0767 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM 0x0768 +#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1de4 +#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x0779 +#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a +#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON7_PERFCOUNTER_STATE 0x077b +#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CNTL 0x077c +#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CNTL2 0x077d +#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e +#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f +#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_HI 0x0780 +#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_LOW 0x0781 +#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x6e0 +#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d +#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e +#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_TILING_CONFIG 0x079f +#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_CNTL 0x07ab +#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP2_HUBP_CLK_CNTL 0x07ac +#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad +#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae +#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af +#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 +#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG 0x07b1 +#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP2_HUBP_DEBUG_CTRL 0x07b2 +#define regHUBP2_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK 0x07b3 +#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK 0x07b4 +#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MALL_STATUS 0x07b7 +#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x6e0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 +#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 +#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 +#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_0 0x07fb +#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_1 0x07fc +#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ2_DST_DIMENSIONS 0x07fd +#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ2_DST_AFTER_SCALER 0x07fe +#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff +#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 +#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 +#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 +#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 +#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 +#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 +#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 +#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 +#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 +#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 +#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_1 0x080a +#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_2 0x080b +#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_3 0x080c +#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_4 0x080d +#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_5 0x080e +#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_6 0x080f +#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 +#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 +#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ2_CURSOR_SETTINGS 0x0813 +#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a +#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b +#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c +#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d +#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e +#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f +#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 +#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x6e0 +#define regHUBPRET2_HUBPRET_CONTROL 0x0824 +#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 +#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a +#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b +#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +// base address: 0x6e0 +#define regCURSOR0_2_CURSOR_CONTROL 0x0830 +#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SIZE 0x0833 +#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_POSITION 0x0834 +#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 +#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 +#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b +#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_CNTL 0x083c +#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d +#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_STATUS 0x083e +#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f +#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 +#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_CONTROL 0x0841 +#define regCURSOR0_2_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW 0x0842 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH 0x0843 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM 0x0844 +#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x2154 +#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0855 +#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856 +#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON8_PERFCOUNTER_STATE 0x0857 +#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CNTL 0x0858 +#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CNTL2 0x0859 +#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a +#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b +#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_HI 0x085c +#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_LOW 0x085d +#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0xa50 +#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 +#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a +#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_TILING_CONFIG 0x087b +#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_CNTL 0x0887 +#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP3_HUBP_CLK_CNTL 0x0888 +#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 +#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_CONFIG 0x088a +#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b +#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c +#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG 0x088d +#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP3_HUBP_DEBUG_CTRL 0x088e +#define regHUBP3_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK 0x088f +#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK 0x0890 +#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MALL_STATUS 0x0893 +#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0xa50 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ3_VMID_SETTINGS_0 0x089d +#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af +#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc +#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd +#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 +#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 +#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ3_DST_DIMENSIONS 0x08d9 +#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ3_DST_AFTER_SCALER 0x08da +#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS 0x08db +#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc +#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd +#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de +#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df +#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 +#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 +#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 +#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 +#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 +#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 +#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 +#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 +#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 +#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 +#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea +#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb +#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec +#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee +#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ3_CURSOR_SETTINGS 0x08ef +#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 +#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 +#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 +#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 +#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa +#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb +#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc +#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd +#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe +#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff +#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0xa50 +#define regHUBPRET3_HUBPRET_CONTROL 0x0900 +#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 +#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 +#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 +#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +// base address: 0xa50 +#define regCURSOR0_3_CURSOR_CONTROL 0x090c +#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SIZE 0x090f +#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_POSITION 0x0910 +#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 +#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 +#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_CNTL 0x0918 +#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 +#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_STATUS 0x091a +#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b +#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_DATA 0x091c +#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_CONTROL 0x091d +#define regCURSOR0_3_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW 0x091e +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH 0x091f +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM 0x0920 +#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x24c4 +#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0931 +#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932 +#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0933 +#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CNTL 0x0934 +#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CNTL2 0x0935 +#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936 +#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937 +#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_HI 0x0938 +#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_LOW 0x0939 +#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define regDPP_TOP0_DPP_CONTROL 0x0cc5 +#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_R 0x0cc7 +#define regDPP_TOP0_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_G 0x0cc8 +#define regDPP_TOP0_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_B 0x0cc9 +#define regDPP_TOP0_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_A 0x0cca +#define regDPP_TOP0_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_CTRL 0x0ccb +#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP0_HOST_READ_CONTROL 0x0ccc +#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0cd1 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd2 +#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd3 +#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd4 +#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd5 +#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd6 +#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd7 +#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd8 +#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd9 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cda +#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cdb +#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cdc +#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdd +#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT01 0x0cdf +#define regCNVC_CFG0_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT23 0x0ce0 +#define regCNVC_CFG0_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEALPHA 0x0ce1 +#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_MODE 0x0ce2 +#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce3 +#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce4 +#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce5 +#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce6 +#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce7 +#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce8 +#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce9 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0cea +#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ceb +#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0cec +#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0ced +#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0cee +#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cef +#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEGAM 0x0cf0 +#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG0_PRE_REALPHA 0x0cf1 +#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_cur_dispdec +// base address: 0x0 +#define regCM_CUR0_CURSOR0_CONTROL 0x0cf4 +#define regCM_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_COLOR0 0x0cf5 +#define regCM_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_COLOR1 0x0cf6 +#define regCM_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y 0x0cf7 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0cf8 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_MODE 0x0cf9 +#define regCM_CUR0_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C11_C12_A 0x0cfa +#define regCM_CUR0_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C13_C14_A 0x0cfb +#define regCM_CUR0_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C21_C22_A 0x0cfc +#define regCM_CUR0_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C23_C24_A 0x0cfd +#define regCM_CUR0_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C31_C32_A 0x0cfe +#define regCM_CUR0_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C33_C34_A 0x0cff +#define regCM_CUR0_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C11_C12_B 0x0d00 +#define regCM_CUR0_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C13_C14_B 0x0d01 +#define regCM_CUR0_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C21_C22_B 0x0d02 +#define regCM_CUR0_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C23_C24_B 0x0d03 +#define regCM_CUR0_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C31_C32_B 0x0d04 +#define regCM_CUR0_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C33_C34_B 0x0d05 +#define regCM_CUR0_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0d08 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0d09 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL0_SCL_MODE 0x0d0a +#define regDSCL0_SCL_MODE_BASE_IDX 2 +#define regDSCL0_SCL_TAP_CONTROL 0x0d0b +#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_CONTROL 0x0d0c +#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_2TAP_CONTROL 0x0d0d +#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0d0e +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d0f +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d10 +#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d11 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d12 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d13 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d14 +#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d15 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d16 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d17 +#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d18 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL0_SCL_BLACK_COLOR 0x0d19 +#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL0_DSCL_UPDATE 0x0d1a +#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL0_DSCL_AUTOCAL 0x0d1b +#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d1c +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d1d +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL0_OTG_H_BLANK 0x0d1e +#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL0_OTG_V_BLANK 0x0d1f +#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL0_RECOUT_START 0x0d20 +#define regDSCL0_RECOUT_START_BASE_IDX 2 +#define regDSCL0_RECOUT_SIZE 0x0d21 +#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL0_MPC_SIZE 0x0d22 +#define regDSCL0_MPC_SIZE_BASE_IDX 2 +#define regDSCL0_LB_DATA_FORMAT 0x0d23 +#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL0_LB_MEMORY_CTRL 0x0d24 +#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL0_LB_V_COUNTER 0x0d25 +#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d26 +#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d27 +#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL0_OBUF_CONTROL 0x0d28 +#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d29 +#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_MODE 0x0d2a +#define regDSCL0_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_MODE 0x0d2b +#define regDSCL0_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL0_DSCL_SC_MODE 0x0d2c +#define regDSCL0_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL0_DSCL_SC_MATRIX_C0C1 0x0d2d +#define regDSCL0_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL0_DSCL_SC_MATRIX_C2C3 0x0d2e +#define regDSCL0_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0d2f +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0d30 +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0d31 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0d32 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0d33 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0d34 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0d35 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_RINGEST_FORCE 0x0d36 +#define regDSCL0_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF_CNTL 0x0d37 +#define regDSCL0_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0d38 +#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF_CNTL 0x0d39 +#define regDSCL0_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0d3a +#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0 0x0d3b +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1 0x0d3c +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2 0x0d3d +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3 0x0d3e +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4 0x0d3f +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5 0x0d40 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6 0x0d41 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7 0x0d42 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0 0x0d43 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1 0x0d44 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2 0x0d45 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3 0x0d46 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4 0x0d47 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5 0x0d48 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6 0x0d49 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7 0x0d4a +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0 0x0d4b +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1 0x0d4c +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2 0x0d4d +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3 0x0d4e +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4 0x0d4f +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5 0x0d50 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0 0x0d51 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1 0x0d52 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2 0x0d53 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3 0x0d54 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4 0x0d55 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5 0x0d56 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_ISHARP_MODE 0x0d57 +#define regDSCL0_ISHARP_MODE_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_CTRL 0x0d58 +#define regDSCL0_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_INDEX 0x0d59 +#define regDSCL0_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_DATA 0x0d5a +#define regDSCL0_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP 0x0d5b +#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL0_ISHARP_NOISEDET_THRESHOLD 0x0d5c +#define regDSCL0_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL0_ISHARP_NOISE_GAIN_PWL 0x0d5d +#define regDSCL0_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG0 0x0d5e +#define regDSCL0_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG1 0x0d5f +#define regDSCL0_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG2 0x0d60 +#define regDSCL0_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG3 0x0d61 +#define regDSCL0_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG4 0x0d62 +#define regDSCL0_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG5 0x0d63 +#define regDSCL0_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0d64 +#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define regCM0_CM_CONTROL 0x0d69 +#define regCM0_CM_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_CONTROL 0x0d6a +#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C11_C12 0x0d6b +#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C13_C14 0x0d6c +#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C21_C22 0x0d6d +#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C23_C24 0x0d6e +#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C31_C32 0x0d6f +#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C33_C34 0x0d70 +#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C11_C12 0x0d71 +#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C13_C14 0x0d72 +#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C21_C22 0x0d73 +#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C23_C24 0x0d74 +#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C31_C32 0x0d75 +#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C33_C34 0x0d76 +#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_BIAS_CR_R 0x0d77 +#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM0_CM_BIAS_Y_G_CB_B 0x0d78 +#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_CONTROL 0x0d79 +#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d7a +#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_DATA 0x0d7b +#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d7c +#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d7d +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d7e +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d7f +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d80 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d81 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d82 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d83 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d84 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d85 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d86 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d87 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d88 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d89 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d8a +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d8b +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d8c +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d8d +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d8e +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d8f +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d90 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d91 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d92 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d93 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d94 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d95 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d96 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d97 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d98 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d99 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d9a +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d9b +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d9c +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d9d +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d9e +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d9f +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0da0 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0da1 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0da2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0da3 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0da4 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0da5 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0da6 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0da7 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0da8 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0da9 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0daa +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0dab +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0dac +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0dad +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0dae +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0daf +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0db0 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0db1 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0db2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0db3 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0db4 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0db5 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0db6 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0db7 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0db8 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0db9 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0dba +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0dbb +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0dbc +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0dbd +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0dbe +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0dbf +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0dc0 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0dc1 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0dc2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_HDR_MULT_COEF 0x0dc3 +#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_CTRL 0x0dc4 +#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_STATUS 0x0dc5 +#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM0_CM_DEALPHA 0x0dc7 +#define regCM0_CM_DEALPHA_BASE_IDX 2 +#define regCM0_CM_COEF_FORMAT 0x0dc8 +#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM0_CM_TEST_DEBUG_INDEX 0x0dc9 +#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM0_CM_TEST_DEBUG_DATA 0x0dca +#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM0_CM_HIST_CNTL 0x0dcb +#define regCM0_CM_HIST_CNTL_BASE_IDX 2 +#define regCM0_CM_HIST_SCALE_SRC1 0x0dcc +#define regCM0_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM0_CM_HIST_COEFA_SRC2 0x0dcd +#define regCM0_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_COEFB_SRC2 0x0dce +#define regCM0_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_COEFC_SRC2 0x0dcf +#define regCM0_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_SCALE_SRC3 0x0dd0 +#define regCM0_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM0_CM_HIST_BIAS_SRC1 0x0dd1 +#define regCM0_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM0_CM_HIST_BIAS_SRC2 0x0dd2 +#define regCM0_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_BIAS_SRC3 0x0dd3 +#define regCM0_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM0_CM_HIST_LOCK 0x0dd4 +#define regCM0_CM_HIST_LOCK_BASE_IDX 2 +#define regCM0_CM_HIST_INDEX 0x0dd5 +#define regCM0_CM_HIST_INDEX_BASE_IDX 2 +#define regCM0_CM_HIST_DATA 0x0dd6 +#define regCM0_CM_HIST_DATA_BASE_IDX 2 +#define regCM0_CM_HIST_STATUS 0x0dd7 +#define regCM0_CM_HIST_STATUS_BASE_IDX 2 +#define regCM0_CM_HIST_INT_CONTROL 0x0dd8 +#define regCM0_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3890 +#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0e24 +#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0e25 +#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0e26 +#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CNTL 0x0e27 +#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CNTL2 0x0e28 +#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0e29 +#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0e2a +#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_HI 0x0e2b +#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_LOW 0x0e2c +#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define regDPP_TOP1_DPP_CONTROL 0x0e30 +#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_R 0x0e32 +#define regDPP_TOP1_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_G 0x0e33 +#define regDPP_TOP1_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_B 0x0e34 +#define regDPP_TOP1_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_A 0x0e35 +#define regDPP_TOP1_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_CTRL 0x0e36 +#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP1_HOST_READ_CONTROL 0x0e37 +#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3c +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3d +#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3e +#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3f +#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e40 +#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e41 +#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e42 +#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e43 +#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e44 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e45 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e46 +#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e47 +#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e48 +#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT01 0x0e4a +#define regCNVC_CFG1_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT23 0x0e4b +#define regCNVC_CFG1_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEALPHA 0x0e4c +#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4d +#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4e +#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4f +#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e50 +#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e51 +#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e52 +#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e53 +#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e54 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e55 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e56 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e57 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e58 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e59 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e5a +#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEGAM 0x0e5b +#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG1_PRE_REALPHA 0x0e5c +#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_cur_dispdec +// base address: 0x5ac +#define regCM_CUR1_CURSOR0_CONTROL 0x0e5f +#define regCM_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_COLOR0 0x0e60 +#define regCM_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_COLOR1 0x0e61 +#define regCM_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y 0x0e62 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0e63 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_MODE 0x0e64 +#define regCM_CUR1_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C11_C12_A 0x0e65 +#define regCM_CUR1_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C13_C14_A 0x0e66 +#define regCM_CUR1_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C21_C22_A 0x0e67 +#define regCM_CUR1_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C23_C24_A 0x0e68 +#define regCM_CUR1_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C31_C32_A 0x0e69 +#define regCM_CUR1_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C33_C34_A 0x0e6a +#define regCM_CUR1_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C11_C12_B 0x0e6b +#define regCM_CUR1_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C13_C14_B 0x0e6c +#define regCM_CUR1_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C21_C22_B 0x0e6d +#define regCM_CUR1_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C23_C24_B 0x0e6e +#define regCM_CUR1_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C31_C32_B 0x0e6f +#define regCM_CUR1_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C33_C34_B 0x0e70 +#define regCM_CUR1_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e73 +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e74 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL1_SCL_MODE 0x0e75 +#define regDSCL1_SCL_MODE_BASE_IDX 2 +#define regDSCL1_SCL_TAP_CONTROL 0x0e76 +#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_CONTROL 0x0e77 +#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_2TAP_CONTROL 0x0e78 +#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e79 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e7a +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e7b +#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e7c +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e7d +#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e7e +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e7f +#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e80 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e81 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e82 +#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e83 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL1_SCL_BLACK_COLOR 0x0e84 +#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL1_DSCL_UPDATE 0x0e85 +#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL1_DSCL_AUTOCAL 0x0e86 +#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e87 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e88 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL1_OTG_H_BLANK 0x0e89 +#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL1_OTG_V_BLANK 0x0e8a +#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL1_RECOUT_START 0x0e8b +#define regDSCL1_RECOUT_START_BASE_IDX 2 +#define regDSCL1_RECOUT_SIZE 0x0e8c +#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL1_MPC_SIZE 0x0e8d +#define regDSCL1_MPC_SIZE_BASE_IDX 2 +#define regDSCL1_LB_DATA_FORMAT 0x0e8e +#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL1_LB_MEMORY_CTRL 0x0e8f +#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL1_LB_V_COUNTER 0x0e90 +#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e91 +#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e92 +#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL1_OBUF_CONTROL 0x0e93 +#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e94 +#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_MODE 0x0e95 +#define regDSCL1_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_MODE 0x0e96 +#define regDSCL1_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL1_DSCL_SC_MODE 0x0e97 +#define regDSCL1_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL1_DSCL_SC_MATRIX_C0C1 0x0e98 +#define regDSCL1_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL1_DSCL_SC_MATRIX_C2C3 0x0e99 +#define regDSCL1_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0e9a +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0e9b +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0e9c +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0e9d +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0e9e +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0e9f +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0ea0 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_RINGEST_FORCE 0x0ea1 +#define regDSCL1_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF_CNTL 0x0ea2 +#define regDSCL1_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0ea3 +#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF_CNTL 0x0ea4 +#define regDSCL1_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0ea5 +#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0 0x0ea6 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1 0x0ea7 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2 0x0ea8 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3 0x0ea9 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4 0x0eaa +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5 0x0eab +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6 0x0eac +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7 0x0ead +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0 0x0eae +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1 0x0eaf +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2 0x0eb0 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3 0x0eb1 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4 0x0eb2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5 0x0eb3 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6 0x0eb4 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7 0x0eb5 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0 0x0eb6 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1 0x0eb7 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2 0x0eb8 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3 0x0eb9 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4 0x0eba +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5 0x0ebb +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0 0x0ebc +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1 0x0ebd +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2 0x0ebe +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3 0x0ebf +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4 0x0ec0 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5 0x0ec1 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_ISHARP_MODE 0x0ec2 +#define regDSCL1_ISHARP_MODE_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_CTRL 0x0ec3 +#define regDSCL1_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_INDEX 0x0ec4 +#define regDSCL1_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_DATA 0x0ec5 +#define regDSCL1_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP 0x0ec6 +#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL1_ISHARP_NOISEDET_THRESHOLD 0x0ec7 +#define regDSCL1_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL1_ISHARP_NOISE_GAIN_PWL 0x0ec8 +#define regDSCL1_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG0 0x0ec9 +#define regDSCL1_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG1 0x0eca +#define regDSCL1_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG2 0x0ecb +#define regDSCL1_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG3 0x0ecc +#define regDSCL1_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG4 0x0ecd +#define regDSCL1_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG5 0x0ece +#define regDSCL1_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0ecf +#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define regCM1_CM_CONTROL 0x0ed4 +#define regCM1_CM_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_CONTROL 0x0ed5 +#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C11_C12 0x0ed6 +#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C13_C14 0x0ed7 +#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C21_C22 0x0ed8 +#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C23_C24 0x0ed9 +#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C31_C32 0x0eda +#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C33_C34 0x0edb +#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C11_C12 0x0edc +#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C13_C14 0x0edd +#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C21_C22 0x0ede +#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C23_C24 0x0edf +#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C31_C32 0x0ee0 +#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C33_C34 0x0ee1 +#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_BIAS_CR_R 0x0ee2 +#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM1_CM_BIAS_Y_G_CB_B 0x0ee3 +#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_CONTROL 0x0ee4 +#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ee5 +#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_DATA 0x0ee6 +#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0ee7 +#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0ee8 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ee9 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eea +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eeb +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eec +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eed +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eee +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eef +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0ef0 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0ef1 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0ef2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0ef3 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0ef4 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0ef5 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0ef6 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ef7 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ef8 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ef9 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0efa +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0efb +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0efc +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0efd +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0efe +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0eff +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0f00 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0f01 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0f02 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0f03 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0f04 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0f05 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0f06 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0f07 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0f08 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0f09 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0f0a +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0f0b +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0f0c +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0f0d +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0f0e +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0f0f +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0f10 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0f11 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0f12 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0f13 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0f14 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0f15 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0f16 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0f17 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0f18 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0f19 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0f1a +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0f1b +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0f1c +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0f1d +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0f1e +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0f1f +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0f20 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0f21 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0f22 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0f23 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0f24 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0f25 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0f26 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0f27 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0f28 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0f29 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0f2a +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0f2b +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0f2c +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0f2d +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_HDR_MULT_COEF 0x0f2e +#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_CTRL 0x0f2f +#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_STATUS 0x0f30 +#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM1_CM_DEALPHA 0x0f32 +#define regCM1_CM_DEALPHA_BASE_IDX 2 +#define regCM1_CM_COEF_FORMAT 0x0f33 +#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM1_CM_TEST_DEBUG_INDEX 0x0f34 +#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM1_CM_TEST_DEBUG_DATA 0x0f35 +#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM1_CM_HIST_CNTL 0x0f36 +#define regCM1_CM_HIST_CNTL_BASE_IDX 2 +#define regCM1_CM_HIST_SCALE_SRC1 0x0f37 +#define regCM1_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM1_CM_HIST_COEFA_SRC2 0x0f38 +#define regCM1_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_COEFB_SRC2 0x0f39 +#define regCM1_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_COEFC_SRC2 0x0f3a +#define regCM1_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_SCALE_SRC3 0x0f3b +#define regCM1_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM1_CM_HIST_BIAS_SRC1 0x0f3c +#define regCM1_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM1_CM_HIST_BIAS_SRC2 0x0f3d +#define regCM1_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_BIAS_SRC3 0x0f3e +#define regCM1_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM1_CM_HIST_LOCK 0x0f3f +#define regCM1_CM_HIST_LOCK_BASE_IDX 2 +#define regCM1_CM_HIST_INDEX 0x0f40 +#define regCM1_CM_HIST_INDEX_BASE_IDX 2 +#define regCM1_CM_HIST_DATA 0x0f41 +#define regCM1_CM_HIST_DATA_BASE_IDX 2 +#define regCM1_CM_HIST_STATUS 0x0f42 +#define regCM1_CM_HIST_STATUS_BASE_IDX 2 +#define regCM1_CM_HIST_INT_CONTROL 0x0f43 +#define regCM1_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3e3c +#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0f8f +#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0f90 +#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0f91 +#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CNTL 0x0f92 +#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CNTL2 0x0f93 +#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0f94 +#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0f95 +#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_HI 0x0f96 +#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_LOW 0x0f97 +#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0xb58 +#define regDPP_TOP2_DPP_CONTROL 0x0f9b +#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c +#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_R 0x0f9d +#define regDPP_TOP2_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_G 0x0f9e +#define regDPP_TOP2_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_B 0x0f9f +#define regDPP_TOP2_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_A 0x0fa0 +#define regDPP_TOP2_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_CTRL 0x0fa1 +#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa2 +#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0xb58 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa7 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa8 +#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa9 +#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0faa +#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fab +#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0fac +#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fad +#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fae +#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0faf +#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fb0 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_RED 0x0fb1 +#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb3 +#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT01 0x0fb5 +#define regCNVC_CFG2_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT23 0x0fb6 +#define regCNVC_CFG2_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEALPHA 0x0fb7 +#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb8 +#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb9 +#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fba +#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fbb +#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fbc +#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fbd +#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbe +#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbf +#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fc0 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fc1 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fc2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc3 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc4 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc5 +#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEGAM 0x0fc6 +#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG2_PRE_REALPHA 0x0fc7 +#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_cur_dispdec +// base address: 0xb58 +#define regCM_CUR2_CURSOR0_CONTROL 0x0fca +#define regCM_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_COLOR0 0x0fcb +#define regCM_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_COLOR1 0x0fcc +#define regCM_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y 0x0fcd +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0fce +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_MODE 0x0fcf +#define regCM_CUR2_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_A 0x0fd0 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_A 0x0fd1 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_A 0x0fd2 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_A 0x0fd3 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C31_C32_A 0x0fd4 +#define regCM_CUR2_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C33_C34_A 0x0fd5 +#define regCM_CUR2_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_B 0x0fd6 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_B 0x0fd7 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_B 0x0fd8 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_B 0x0fd9 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C31_C32_B 0x0fda +#define regCM_CUR2_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C33_C34_B 0x0fdb +#define regCM_CUR2_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +// base address: 0xb58 +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fde +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fdf +#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL2_SCL_MODE 0x0fe0 +#define regDSCL2_SCL_MODE_BASE_IDX 2 +#define regDSCL2_SCL_TAP_CONTROL 0x0fe1 +#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_CONTROL 0x0fe2 +#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_2TAP_CONTROL 0x0fe3 +#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fe4 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fe5 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fe6 +#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fe7 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fe8 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fe9 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fea +#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0feb +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fec +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fed +#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fee +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL2_SCL_BLACK_COLOR 0x0fef +#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL2_DSCL_UPDATE 0x0ff0 +#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL2_DSCL_AUTOCAL 0x0ff1 +#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0ff2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ff3 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL2_OTG_H_BLANK 0x0ff4 +#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL2_OTG_V_BLANK 0x0ff5 +#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL2_RECOUT_START 0x0ff6 +#define regDSCL2_RECOUT_START_BASE_IDX 2 +#define regDSCL2_RECOUT_SIZE 0x0ff7 +#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL2_MPC_SIZE 0x0ff8 +#define regDSCL2_MPC_SIZE_BASE_IDX 2 +#define regDSCL2_LB_DATA_FORMAT 0x0ff9 +#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL2_LB_MEMORY_CTRL 0x0ffa +#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL2_LB_V_COUNTER 0x0ffb +#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0ffc +#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0ffd +#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL2_OBUF_CONTROL 0x0ffe +#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0fff +#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_MODE 0x1000 +#define regDSCL2_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_MODE 0x1001 +#define regDSCL2_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL2_DSCL_SC_MODE 0x1002 +#define regDSCL2_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL2_DSCL_SC_MATRIX_C0C1 0x1003 +#define regDSCL2_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL2_DSCL_SC_MATRIX_C2C3 0x1004 +#define regDSCL2_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x1005 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1006 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1007 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1008 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1009 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x100a +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x100b +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_RINGEST_FORCE 0x100c +#define regDSCL2_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF_CNTL 0x100d +#define regDSCL2_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x100e +#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF_CNTL 0x100f +#define regDSCL2_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x1010 +#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0 0x1011 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1 0x1012 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2 0x1013 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3 0x1014 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4 0x1015 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5 0x1016 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6 0x1017 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7 0x1018 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0 0x1019 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1 0x101a +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2 0x101b +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3 0x101c +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4 0x101d +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5 0x101e +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6 0x101f +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7 0x1020 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0 0x1021 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1 0x1022 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2 0x1023 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3 0x1024 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4 0x1025 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5 0x1026 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0 0x1027 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1 0x1028 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2 0x1029 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3 0x102a +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4 0x102b +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5 0x102c +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_ISHARP_MODE 0x102d +#define regDSCL2_ISHARP_MODE_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_CTRL 0x102e +#define regDSCL2_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_INDEX 0x102f +#define regDSCL2_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_DATA 0x1030 +#define regDSCL2_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP 0x1031 +#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL2_ISHARP_NOISEDET_THRESHOLD 0x1032 +#define regDSCL2_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL2_ISHARP_NOISE_GAIN_PWL 0x1033 +#define regDSCL2_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG0 0x1034 +#define regDSCL2_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG1 0x1035 +#define regDSCL2_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG2 0x1036 +#define regDSCL2_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG3 0x1037 +#define regDSCL2_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG4 0x1038 +#define regDSCL2_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG5 0x1039 +#define regDSCL2_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x103a +#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +// base address: 0xb58 +#define regCM2_CM_CONTROL 0x103f +#define regCM2_CM_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_CONTROL 0x1040 +#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C11_C12 0x1041 +#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C13_C14 0x1042 +#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C21_C22 0x1043 +#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C23_C24 0x1044 +#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C31_C32 0x1045 +#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C33_C34 0x1046 +#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C11_C12 0x1047 +#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C13_C14 0x1048 +#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C21_C22 0x1049 +#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C23_C24 0x104a +#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C31_C32 0x104b +#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C33_C34 0x104c +#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_BIAS_CR_R 0x104d +#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM2_CM_BIAS_Y_G_CB_B 0x104e +#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_CONTROL 0x104f +#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_INDEX 0x1050 +#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_DATA 0x1051 +#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1052 +#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1053 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1054 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1055 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1056 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1057 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1058 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1059 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x105a +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x105b +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x105c +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x105d +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x105e +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x105f +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1060 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1061 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1062 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1063 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1064 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1065 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x1066 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x1067 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x1068 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x1069 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x106a +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x106b +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x106c +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x106d +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x106e +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x106f +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1070 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1071 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1072 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1073 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1074 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1075 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x1076 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x1077 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x1078 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1079 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x107a +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x107b +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x107c +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x107d +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x107e +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x107f +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1080 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1081 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1082 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1083 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1084 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1085 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x1086 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x1087 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x1088 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x1089 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x108a +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x108b +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x108c +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x108d +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x108e +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x108f +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1090 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1091 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1092 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1093 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1094 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1095 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x1096 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x1097 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x1098 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_HDR_MULT_COEF 0x1099 +#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_CTRL 0x109a +#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_STATUS 0x109b +#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM2_CM_DEALPHA 0x109d +#define regCM2_CM_DEALPHA_BASE_IDX 2 +#define regCM2_CM_COEF_FORMAT 0x109e +#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM2_CM_TEST_DEBUG_INDEX 0x109f +#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM2_CM_TEST_DEBUG_DATA 0x10a0 +#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM2_CM_HIST_CNTL 0x10a1 +#define regCM2_CM_HIST_CNTL_BASE_IDX 2 +#define regCM2_CM_HIST_SCALE_SRC1 0x10a2 +#define regCM2_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM2_CM_HIST_COEFA_SRC2 0x10a3 +#define regCM2_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_COEFB_SRC2 0x10a4 +#define regCM2_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_COEFC_SRC2 0x10a5 +#define regCM2_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_SCALE_SRC3 0x10a6 +#define regCM2_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM2_CM_HIST_BIAS_SRC1 0x10a7 +#define regCM2_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM2_CM_HIST_BIAS_SRC2 0x10a8 +#define regCM2_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_BIAS_SRC3 0x10a9 +#define regCM2_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM2_CM_HIST_LOCK 0x10aa +#define regCM2_CM_HIST_LOCK_BASE_IDX 2 +#define regCM2_CM_HIST_INDEX 0x10ab +#define regCM2_CM_HIST_INDEX_BASE_IDX 2 +#define regCM2_CM_HIST_DATA 0x10ac +#define regCM2_CM_HIST_DATA_BASE_IDX 2 +#define regCM2_CM_HIST_STATUS 0x10ad +#define regCM2_CM_HIST_STATUS_BASE_IDX 2 +#define regCM2_CM_HIST_INT_CONTROL 0x10ae +#define regCM2_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x43e8 +#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x10fa +#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x10fb +#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON12_PERFCOUNTER_STATE 0x10fc +#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CNTL 0x10fd +#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CNTL2 0x10fe +#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x10ff +#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x1100 +#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_HI 0x1101 +#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_LOW 0x1102 +#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0x1104 +#define regDPP_TOP3_DPP_CONTROL 0x1106 +#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 +#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_R 0x1108 +#define regDPP_TOP3_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_G 0x1109 +#define regDPP_TOP3_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_B 0x110a +#define regDPP_TOP3_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_A 0x110b +#define regDPP_TOP3_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_CTRL 0x110c +#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP3_HOST_READ_CONTROL 0x110d +#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0x1104 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1112 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_FORMAT_CONTROL 0x1113 +#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1114 +#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1115 +#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1116 +#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1117 +#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1118 +#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1119 +#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x111a +#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x111b +#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_RED 0x111c +#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111d +#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111e +#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT01 0x1120 +#define regCNVC_CFG3_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT23 0x1121 +#define regCNVC_CFG3_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEALPHA 0x1122 +#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_MODE 0x1123 +#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1124 +#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1125 +#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1126 +#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1127 +#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1128 +#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1129 +#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x112a +#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x112b +#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x112c +#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112d +#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112e +#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112f +#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x1130 +#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEGAM 0x1131 +#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG3_PRE_REALPHA 0x1132 +#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_cur_dispdec +// base address: 0x1104 +#define regCM_CUR3_CURSOR0_CONTROL 0x1135 +#define regCM_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_COLOR0 0x1136 +#define regCM_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_COLOR1 0x1137 +#define regCM_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y 0x1138 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x1139 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_MODE 0x113a +#define regCM_CUR3_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C11_C12_A 0x113b +#define regCM_CUR3_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C13_C14_A 0x113c +#define regCM_CUR3_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C21_C22_A 0x113d +#define regCM_CUR3_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C23_C24_A 0x113e +#define regCM_CUR3_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C31_C32_A 0x113f +#define regCM_CUR3_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_A 0x1140 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C11_C12_B 0x1141 +#define regCM_CUR3_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C13_C14_B 0x1142 +#define regCM_CUR3_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C21_C22_B 0x1143 +#define regCM_CUR3_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C23_C24_B 0x1144 +#define regCM_CUR3_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C31_C32_B 0x1145 +#define regCM_CUR3_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_B 0x1146 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +// base address: 0x1104 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x1149 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x114a +#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL3_SCL_MODE 0x114b +#define regDSCL3_SCL_MODE_BASE_IDX 2 +#define regDSCL3_SCL_TAP_CONTROL 0x114c +#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_CONTROL 0x114d +#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_2TAP_CONTROL 0x114e +#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x114f +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1150 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1151 +#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1152 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1153 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1154 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT 0x1155 +#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1156 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1157 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1158 +#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x1159 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL3_SCL_BLACK_COLOR 0x115a +#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL3_DSCL_UPDATE 0x115b +#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL3_DSCL_AUTOCAL 0x115c +#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x115d +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x115e +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL3_OTG_H_BLANK 0x115f +#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL3_OTG_V_BLANK 0x1160 +#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL3_RECOUT_START 0x1161 +#define regDSCL3_RECOUT_START_BASE_IDX 2 +#define regDSCL3_RECOUT_SIZE 0x1162 +#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL3_MPC_SIZE 0x1163 +#define regDSCL3_MPC_SIZE_BASE_IDX 2 +#define regDSCL3_LB_DATA_FORMAT 0x1164 +#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL3_LB_MEMORY_CTRL 0x1165 +#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL3_LB_V_COUNTER 0x1166 +#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1167 +#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1168 +#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL3_OBUF_CONTROL 0x1169 +#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL3_OBUF_MEM_PWR_CTRL 0x116a +#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_MODE 0x116b +#define regDSCL3_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_MODE 0x116c +#define regDSCL3_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL3_DSCL_SC_MODE 0x116d +#define regDSCL3_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL3_DSCL_SC_MATRIX_C0C1 0x116e +#define regDSCL3_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL3_DSCL_SC_MATRIX_C2C3 0x116f +#define regDSCL3_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x1170 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1171 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1172 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1173 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1174 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1175 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1176 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_RINGEST_FORCE 0x1177 +#define regDSCL3_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF_CNTL 0x1178 +#define regDSCL3_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x1179 +#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF_CNTL 0x117a +#define regDSCL3_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x117b +#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0 0x117c +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1 0x117d +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2 0x117e +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3 0x117f +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4 0x1180 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5 0x1181 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6 0x1182 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7 0x1183 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0 0x1184 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1 0x1185 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2 0x1186 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3 0x1187 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4 0x1188 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5 0x1189 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6 0x118a +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7 0x118b +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0 0x118c +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1 0x118d +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2 0x118e +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3 0x118f +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4 0x1190 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5 0x1191 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0 0x1192 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1 0x1193 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2 0x1194 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3 0x1195 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4 0x1196 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5 0x1197 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_ISHARP_MODE 0x1198 +#define regDSCL3_ISHARP_MODE_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_CTRL 0x1199 +#define regDSCL3_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_INDEX 0x119a +#define regDSCL3_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_DATA 0x119b +#define regDSCL3_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP 0x119c +#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL3_ISHARP_NOISEDET_THRESHOLD 0x119d +#define regDSCL3_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL3_ISHARP_NOISE_GAIN_PWL 0x119e +#define regDSCL3_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG0 0x119f +#define regDSCL3_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG1 0x11a0 +#define regDSCL3_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG2 0x11a1 +#define regDSCL3_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG3 0x11a2 +#define regDSCL3_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG4 0x11a3 +#define regDSCL3_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG5 0x11a4 +#define regDSCL3_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11a5 +#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +// base address: 0x1104 +#define regCM3_CM_CONTROL 0x11aa +#define regCM3_CM_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_CONTROL 0x11ab +#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C11_C12 0x11ac +#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C13_C14 0x11ad +#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C21_C22 0x11ae +#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C23_C24 0x11af +#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C31_C32 0x11b0 +#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C33_C34 0x11b1 +#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C11_C12 0x11b2 +#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C13_C14 0x11b3 +#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C21_C22 0x11b4 +#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C23_C24 0x11b5 +#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C31_C32 0x11b6 +#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C33_C34 0x11b7 +#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_BIAS_CR_R 0x11b8 +#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM3_CM_BIAS_Y_G_CB_B 0x11b9 +#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_CONTROL 0x11ba +#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_INDEX 0x11bb +#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_DATA 0x11bc +#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_CONTROL 0x11bd +#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x11be +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x11bf +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x11c0 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x11c1 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x11c2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x11c3 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x11c4 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x11c5 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x11c6 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x11c7 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x11c8 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x11c9 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x11ca +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x11cb +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x11cc +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x11cd +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x11ce +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x11cf +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x11d0 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x11d1 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x11d2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x11d3 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x11d4 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x11d5 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x11d6 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x11d7 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x11d8 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x11d9 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x11da +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x11db +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11dc +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11dd +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11de +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11df +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11e0 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11e1 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11e2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11e3 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11e4 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11e5 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11e6 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11e7 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11e8 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11e9 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ea +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11eb +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11ec +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11ed +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11ee +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11ef +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11f0 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11f1 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11f2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11f3 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11f4 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11f5 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11f6 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11f7 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11f8 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11f9 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11fa +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11fb +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11fc +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11fd +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11fe +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11ff +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x1200 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x1201 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x1202 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x1203 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_HDR_MULT_COEF 0x1204 +#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_CTRL 0x1205 +#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_STATUS 0x1206 +#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM3_CM_DEALPHA 0x1208 +#define regCM3_CM_DEALPHA_BASE_IDX 2 +#define regCM3_CM_COEF_FORMAT 0x1209 +#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM3_CM_TEST_DEBUG_INDEX 0x120a +#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM3_CM_TEST_DEBUG_DATA 0x120b +#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM3_CM_HIST_CNTL 0x120c +#define regCM3_CM_HIST_CNTL_BASE_IDX 2 +#define regCM3_CM_HIST_SCALE_SRC1 0x120d +#define regCM3_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM3_CM_HIST_COEFA_SRC2 0x120e +#define regCM3_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_COEFB_SRC2 0x120f +#define regCM3_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_COEFC_SRC2 0x1210 +#define regCM3_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_SCALE_SRC3 0x1211 +#define regCM3_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM3_CM_HIST_BIAS_SRC1 0x1212 +#define regCM3_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM3_CM_HIST_BIAS_SRC2 0x1213 +#define regCM3_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_BIAS_SRC3 0x1214 +#define regCM3_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM3_CM_HIST_LOCK 0x1215 +#define regCM3_CM_HIST_LOCK_BASE_IDX 2 +#define regCM3_CM_HIST_INDEX 0x1216 +#define regCM3_CM_HIST_INDEX_BASE_IDX 2 +#define regCM3_CM_HIST_DATA 0x1217 +#define regCM3_CM_HIST_DATA_BASE_IDX 2 +#define regCM3_CM_HIST_STATUS 0x1218 +#define regCM3_CM_HIST_STATUS_BASE_IDX 2 +#define regCM3_CM_HIST_INT_CONTROL 0x1219 +#define regCM3_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x4994 +#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x1265 +#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x1266 +#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON13_PERFCOUNTER_STATE 0x1267 +#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CNTL 0x1268 +#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CNTL2 0x1269 +#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x126a +#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x126b +#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_HI 0x126c +#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_LOW 0x126d +#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux0_dispdec +// base address: 0x0 +#define regDP_AUX0_AUX_CONTROL 0x16b2 +#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_CONTROL 0x16b3 +#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_ARB_CONTROL 0x16b4 +#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x16b5 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_STATUS 0x16b6 +#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_STATUS 0x16b7 +#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_DATA 0x16b8 +#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_DATA 0x16b9 +#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x16ba +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x16bb +#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x16bc +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x16bd +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x16be +#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x16bf +#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x16c1 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_STATUS 0x16c2 +#define regDP_AUX0_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux1_dispdec +// base address: 0x70 +#define regDP_AUX1_AUX_CONTROL 0x16ce +#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_CONTROL 0x16cf +#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_ARB_CONTROL 0x16d0 +#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x16d1 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_STATUS 0x16d2 +#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_STATUS 0x16d3 +#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_DATA 0x16d4 +#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_DATA 0x16d5 +#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x16d6 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x16d7 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x16d8 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x16d9 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x16da +#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x16db +#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x16dd +#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_STATUS 0x16de +#define regDP_AUX1_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux2_dispdec +// base address: 0xe0 +#define regDP_AUX2_AUX_CONTROL 0x16ea +#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_CONTROL 0x16eb +#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_ARB_CONTROL 0x16ec +#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x16ed +#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_STATUS 0x16ee +#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_STATUS 0x16ef +#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_DATA 0x16f0 +#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_DATA 0x16f1 +#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x16f2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x16f3 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x16f4 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x16f5 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x16f6 +#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x16f7 +#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x16f9 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_STATUS 0x16fa +#define regDP_AUX2_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux3_dispdec +// base address: 0x150 +#define regDP_AUX3_AUX_CONTROL 0x1706 +#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_CONTROL 0x1707 +#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_ARB_CONTROL 0x1708 +#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1709 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_STATUS 0x170a +#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_STATUS 0x170b +#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_DATA 0x170c +#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_DATA 0x170d +#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x170e +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x170f +#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1710 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1711 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1712 +#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1713 +#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1715 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_STATUS 0x1716 +#define regDP_AUX3_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux4_dispdec +// base address: 0x1c0 +#define regDP_AUX4_AUX_CONTROL 0x1722 +#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_CONTROL 0x1723 +#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_ARB_CONTROL 0x1724 +#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1725 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_STATUS 0x1726 +#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_STATUS 0x1727 +#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_DATA 0x1728 +#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_DATA 0x1729 +#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x172a +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x172b +#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x172c +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x172d +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x172e +#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x172f +#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1731 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_STATUS 0x1732 +#define regDP_AUX4_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd0_dispdec +// base address: 0x0 +#define regHPD0_DC_HPD_INT_STATUS 0x175a +#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD0_DC_HPD_INT_CONTROL 0x175b +#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_CONTROL 0x175c +#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x175d +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x175e +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd1_dispdec +// base address: 0x20 +#define regHPD1_DC_HPD_INT_STATUS 0x1762 +#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD1_DC_HPD_INT_CONTROL 0x1763 +#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_CONTROL 0x1764 +#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1765 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1766 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd2_dispdec +// base address: 0x40 +#define regHPD2_DC_HPD_INT_STATUS 0x176a +#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD2_DC_HPD_INT_CONTROL 0x176b +#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_CONTROL 0x176c +#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x176d +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x176e +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd3_dispdec +// base address: 0x60 +#define regHPD3_DC_HPD_INT_STATUS 0x1772 +#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD3_DC_HPD_INT_CONTROL 0x1773 +#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_CONTROL 0x1774 +#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1775 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1776 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd4_dispdec +// base address: 0x80 +#define regHPD4_DC_HPD_INT_STATUS 0x177a +#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD4_DC_HPD_INT_CONTROL 0x177b +#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_CONTROL 0x177c +#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x177d +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x177e +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux0_dispdec +// base address: 0x13128 +#define regDPIA_MUX0_DPIA_MUX_CONTROL 0x178a +#define regDPIA_MUX0_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux1_dispdec +// base address: 0x13130 +#define regDPIA_MUX1_DPIA_MUX_CONTROL 0x178c +#define regDPIA_MUX1_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux2_dispdec +// base address: 0x13138 +#define regDPIA_MUX2_DPIA_MUX_CONTROL 0x178e +#define regDPIA_MUX2_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux3_dispdec +// base address: 0x13140 +#define regDPIA_MUX3_DPIA_MUX_CONTROL 0x1790 +#define regDPIA_MUX3_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux4_dispdec +// base address: 0x13148 +#define regDPIA_MUX4_DPIA_MUX_CONTROL 0x1792 +#define regDPIA_MUX4_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux5_dispdec +// base address: 0x13150 +#define regDPIA_MUX5_DPIA_MUX_CONTROL 0x1794 +#define regDPIA_MUX5_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux0_dispdec +// base address: 0x13168 +#define regPHY_MUX0_PHY_MUX_CONTROL 0x179a +#define regPHY_MUX0_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX0_PORT_TYPE 0x179b +#define regPHY_MUX0_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux1_dispdec +// base address: 0x13174 +#define regPHY_MUX1_PHY_MUX_CONTROL 0x179d +#define regPHY_MUX1_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX1_PORT_TYPE 0x179e +#define regPHY_MUX1_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux2_dispdec +// base address: 0x13180 +#define regPHY_MUX2_PHY_MUX_CONTROL 0x17a0 +#define regPHY_MUX2_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX2_PORT_TYPE 0x17a1 +#define regPHY_MUX2_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux3_dispdec +// base address: 0x1318c +#define regPHY_MUX3_PHY_MUX_CONTROL 0x17a3 +#define regPHY_MUX3_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX3_PORT_TYPE 0x17a4 +#define regPHY_MUX3_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux4_dispdec +// base address: 0x13198 +#define regPHY_MUX4_PHY_MUX_CONTROL 0x17a6 +#define regPHY_MUX4_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX4_PORT_TYPE 0x17a7 +#define regPHY_MUX4_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dcoh_top_dispdec +// base address: 0x0 +#define regDCOH_TOP_CLOCK_CONTROL 0x17af +#define regDCOH_TOP_CLOCK_CONTROL_BASE_IDX 2 +#define regDCOH_DCN_STATUS 0x17b0 +#define regDCOH_DCN_STATUS_BASE_IDX 2 +#define regDCOH_TOP_SPARE 0x17b4 +#define regDCOH_TOP_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_CONTROL 0x1840 +#define regFMT0_FMT_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_CNTL 0x1845 +#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_422_CONTROL 0x1849 +#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg0_dispdec +// base address: 0x0 +#define regDPG0_DPG_CONTROL 0x1854 +#define regDPG0_DPG_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_RAMP_CONTROL 0x1855 +#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_DIMENSIONS 0x1856 +#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_R_CR 0x1857 +#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_G_Y 0x1858 +#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_B_CB 0x1859 +#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG0_DPG_OFFSET_SEGMENT 0x185a +#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG0_DPG_STATUS 0x185b +#define regDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define regOPPBUF0_OPPBUF_CONTROL 0x1884 +#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188b +#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x188f +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1890 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA 0x1891 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR 0x1892 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG 0x1893 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB 0x1894 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC 0x1895 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_CONTROL 0x189a +#define regFMT1_FMT_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_CNTL 0x189f +#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_422_CONTROL 0x18a3 +#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg1_dispdec +// base address: 0x168 +#define regDPG1_DPG_CONTROL 0x18ae +#define regDPG1_DPG_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_RAMP_CONTROL 0x18af +#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_DIMENSIONS 0x18b0 +#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_R_CR 0x18b1 +#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_G_Y 0x18b2 +#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_B_CB 0x18b3 +#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG1_DPG_STATUS 0x18b5 +#define regDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define regOPPBUF1_OPPBUF_CONTROL 0x18de +#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e5 +#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18e9 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ea +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA 0x18eb +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR 0x18ec +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG 0x18ed +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB 0x18ee +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC 0x18ef +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_CONTROL 0x18f4 +#define regFMT2_FMT_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_CNTL 0x18f9 +#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb +#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_422_CONTROL 0x18fd +#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg2_dispdec +// base address: 0x2d0 +#define regDPG2_DPG_CONTROL 0x1908 +#define regDPG2_DPG_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_RAMP_CONTROL 0x1909 +#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_DIMENSIONS 0x190a +#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_R_CR 0x190b +#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_G_Y 0x190c +#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_B_CB 0x190d +#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG2_DPG_OFFSET_SEGMENT 0x190e +#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG2_DPG_STATUS 0x190f +#define regDPG2_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define regOPPBUF2_OPPBUF_CONTROL 0x1938 +#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_CONTROL1 0x193d +#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x193f +#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1943 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1944 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA 0x1945 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR 0x1946 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG 0x1947 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB 0x1948 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC 0x1949 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +// base address: 0x438 +#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_CONTROL 0x194e +#define regFMT3_FMT_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_CNTL 0x1953 +#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_422_CONTROL 0x1957 +#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg3_dispdec +// base address: 0x438 +#define regDPG3_DPG_CONTROL 0x1962 +#define regDPG3_DPG_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_RAMP_CONTROL 0x1963 +#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_DIMENSIONS 0x1964 +#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_R_CR 0x1965 +#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_G_Y 0x1966 +#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_B_CB 0x1967 +#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 +#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG3_DPG_STATUS 0x1969 +#define regDPG3_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define regOPPBUF3_OPPBUF_CONTROL 0x1992 +#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 +#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x1999 +#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199d +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x199e +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA 0x199f +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR 0x19a0 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG 0x19a1 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB 0x19a2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC 0x19a3 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define regOPP_TOP_CLK_CONTROL 0x1a5e +#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 +#define regOPP_ABM_CONTROL 0x1a60 +#define regOPP_ABM_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +// base address: 0x8 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +// base address: 0xc +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +// base address: 0x6af8 +#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1abe +#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1abf +#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1ac0 +#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CNTL 0x1ac1 +#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CNTL2 0x1ac2 +#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x1ac3 +#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x1ac4 +#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_HI 0x1ac5 +#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_LOW 0x1ac6 +#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_UNDERFLOW_THRESHOLD 0x1acc +#define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acd +#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1ace +#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acf +#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL 0x1ad0 +#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL2 0x1ad1 +#define regODM0_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1ad2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_MEMORY_CONFIG 0x1ad3 +#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad4 +#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_UNDERFLOW_THRESHOLD 0x1adc +#define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1add +#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1ade +#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_BYTES_PER_PIXEL 0x1adf +#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL 0x1ae0 +#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL2 0x1ae1 +#define regODM1_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1ae2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_MEMORY_CONFIG 0x1ae3 +#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae4 +#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm2_dispdec +// base address: 0x80 +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_UNDERFLOW_THRESHOLD 0x1aec +#define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aed +#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aee +#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aef +#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL 0x1af0 +#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL2 0x1af1 +#define regODM2_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1af2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_MEMORY_CONFIG 0x1af3 +#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af4 +#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm3_dispdec +// base address: 0xc0 +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_UNDERFLOW_THRESHOLD 0x1afc +#define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afd +#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afe +#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_BYTES_PER_PIXEL 0x1aff +#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL 0x1b00 +#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL2 0x1b01 +#define regODM3_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1b02 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_MEMORY_CONFIG 0x1b03 +#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b04 +#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define regOTG0_OTG_H_TOTAL 0x1b2a +#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_H_BLANK_START_END 0x1b2b +#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A 0x1b2c +#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL 0x1b2f +#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MID 0x1b32 +#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36 +#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_V_BLANK_START_END 0x1b38 +#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A 0x1b39 +#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a +#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_CNTL 0x1b3b +#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c +#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_CNTL 0x1b3d +#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e +#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG0_OTG_CONTROL 0x1b43 +#define regOTG0_OTG_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DLPC_CONTROL 0x1b44 +#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_PWA_FRAME_SYNC_CONTROL 0x1b45 +#define regOTG0_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_CONTROL 0x1b46 +#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_STATUS 0x1b47 +#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b48 +#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b49 +#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG0_OTG_STATUS 0x1b4a +#define regOTG0_OTG_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STATUS_POSITION 0x1b4b +#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4c +#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4d +#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4e +#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4f +#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_HV_COUNT 0x1b50 +#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG0_OTG_COUNT_CONTROL 0x1b51 +#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_COUNT_RESET 0x1b52 +#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b53 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b54 +#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_STATUS 0x1b55 +#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STEREO_CONTROL 0x1b56 +#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b57 +#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b58 +#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b59 +#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b5a +#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5b +#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_UPDATE_LOCK 0x1b5c +#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5d +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MASTER_EN 0x1b5e +#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b60 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b61 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b62 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b63 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b64 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b65 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC_CNTL 0x1b66 +#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b67 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b68 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b69 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6a +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_R 0x1b6b +#define regOTG0_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_G 0x1b6c +#define regOTG0_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_B 0x1b6d +#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_C 0x1b6e +#define regOTG0_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6f +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b70 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b71 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b72 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_R 0x1b73 +#define regOTG0_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_G 0x1b74 +#define regOTG0_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_B 0x1b75 +#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_C 0x1b76 +#define regOTG0_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_R 0x1b77 +#define regOTG0_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_G 0x1b78 +#define regOTG0_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_B 0x1b79 +#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_C 0x1b7a +#define regOTG0_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_R 0x1b7b +#define regOTG0_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_G 0x1b7c +#define regOTG0_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_B 0x1b7d +#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_C 0x1b7e +#define regOTG0_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_AES 0x1b7f +#define regOTG0_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b80 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b81 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b82 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b83 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b84 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b85 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b86 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b87 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b88 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b89 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b8a +#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b8b +#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b8c +#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b8d +#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG0_OTG_CLOCK_CONTROL 0x1b8e +#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VSTARTUP_PARAM 0x1b8f +#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_PARAM 0x1b90 +#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VREADY_PARAM 0x1b91 +#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b92 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b93 +#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_GSL_CONTROL 0x1b94 +#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_X 0x1b95 +#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_Y 0x1b96 +#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b97 +#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b98 +#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b99 +#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b9a +#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b9b +#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b9c +#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b9d +#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b9f +#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1ba0 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1ba1 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1ba2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTROL 0x1ba3 +#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTOL2 0x1ba4 +#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO0 0x1ba5 +#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO1 0x1ba6 +#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG0_OTG_REQUEST_CONTROL 0x1ba7 +#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba8 +#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PSTATE_REGISTER 0x1ba9 +#define regOTG0_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG0_OTG_ENCRYPTION 0x1baa +#define regOTG0_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG0_OTG_SPARE_REGISTER 0x1bab +#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x220 +#define regOTG1_OTG_H_TOTAL 0x1bb2 +#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_H_BLANK_START_END 0x1bb3 +#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A 0x1bb4 +#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bb5 +#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_H_TIMING_CNTL 0x1bb6 +#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL 0x1bb7 +#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MIN 0x1bb8 +#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MAX 0x1bb9 +#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MID 0x1bba +#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bbb +#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bbc +#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bbd +#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bbe +#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bbf +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_V_BLANK_START_END 0x1bc0 +#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A 0x1bc1 +#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bc2 +#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_CNTL 0x1bc3 +#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bc4 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_CNTL 0x1bc5 +#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bc6 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bc7 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc9 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG1_OTG_CONTROL 0x1bcb +#define regOTG1_OTG_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DLPC_CONTROL 0x1bcc +#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_PWA_FRAME_SYNC_CONTROL 0x1bcd +#define regOTG1_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_CONTROL 0x1bce +#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_STATUS 0x1bcf +#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bd0 +#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bd1 +#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG1_OTG_STATUS 0x1bd2 +#define regOTG1_OTG_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STATUS_POSITION 0x1bd3 +#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bd4 +#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG1_OTG_NOM_VERT_POSITION 0x1bd5 +#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bd6 +#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_VF_COUNT 0x1bd7 +#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_HV_COUNT 0x1bd8 +#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG1_OTG_COUNT_CONTROL 0x1bd9 +#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_COUNT_RESET 0x1bda +#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bdb +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bdc +#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_STATUS 0x1bdd +#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STEREO_CONTROL 0x1bde +#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bdf +#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1be0 +#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_POSITION 0x1be1 +#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_FRAME 0x1be2 +#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG1_OTG_INTERRUPT_CONTROL 0x1be3 +#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_UPDATE_LOCK 0x1be4 +#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1be5 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MASTER_EN 0x1be6 +#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be8 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be9 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1bea +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1beb +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1bec +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bed +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC_CNTL 0x1bee +#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bef +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bf0 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bf1 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bf2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_R 0x1bf3 +#define regOTG1_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_G 0x1bf4 +#define regOTG1_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_B 0x1bf5 +#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_C 0x1bf6 +#define regOTG1_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf7 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf8 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf9 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bfa +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_R 0x1bfb +#define regOTG1_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_G 0x1bfc +#define regOTG1_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_B 0x1bfd +#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_C 0x1bfe +#define regOTG1_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_R 0x1bff +#define regOTG1_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_G 0x1c00 +#define regOTG1_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_B 0x1c01 +#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_C 0x1c02 +#define regOTG1_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_R 0x1c03 +#define regOTG1_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_G 0x1c04 +#define regOTG1_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_B 0x1c05 +#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_C 0x1c06 +#define regOTG1_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_AES 0x1c07 +#define regOTG1_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1c08 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c09 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c0a +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c0b +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c0c +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c0d +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c0e +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c0f +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c10 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c11 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c12 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c13 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c14 +#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c15 +#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG1_OTG_CLOCK_CONTROL 0x1c16 +#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VSTARTUP_PARAM 0x1c17 +#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_PARAM 0x1c18 +#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VREADY_PARAM 0x1c19 +#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c1a +#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c1b +#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_GSL_CONTROL 0x1c1c +#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_X 0x1c1d +#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_Y 0x1c1e +#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c1f +#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c20 +#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c21 +#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c22 +#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c23 +#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c24 +#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c25 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c27 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c28 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c29 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c2a +#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTROL 0x1c2b +#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTOL2 0x1c2c +#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO0 0x1c2d +#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO1 0x1c2e +#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG1_OTG_REQUEST_CONTROL 0x1c2f +#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c30 +#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PSTATE_REGISTER 0x1c31 +#define regOTG1_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG1_OTG_ENCRYPTION 0x1c32 +#define regOTG1_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG1_OTG_SPARE_REGISTER 0x1c33 +#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg2_dispdec +// base address: 0x440 +#define regOTG2_OTG_H_TOTAL 0x1c3a +#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_H_BLANK_START_END 0x1c3b +#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A 0x1c3c +#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c3d +#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_H_TIMING_CNTL 0x1c3e +#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL 0x1c3f +#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MIN 0x1c40 +#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MAX 0x1c41 +#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MID 0x1c42 +#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c43 +#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c44 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c45 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c46 +#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c47 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_V_BLANK_START_END 0x1c48 +#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A 0x1c49 +#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c4a +#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_CNTL 0x1c4b +#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c4c +#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_CNTL 0x1c4d +#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c4e +#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c4f +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c51 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG2_OTG_CONTROL 0x1c53 +#define regOTG2_OTG_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DLPC_CONTROL 0x1c54 +#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_PWA_FRAME_SYNC_CONTROL 0x1c55 +#define regOTG2_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_CONTROL 0x1c56 +#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_STATUS 0x1c57 +#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c58 +#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c59 +#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG2_OTG_STATUS 0x1c5a +#define regOTG2_OTG_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STATUS_POSITION 0x1c5b +#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c5c +#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG2_OTG_NOM_VERT_POSITION 0x1c5d +#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c5e +#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_VF_COUNT 0x1c5f +#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_HV_COUNT 0x1c60 +#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG2_OTG_COUNT_CONTROL 0x1c61 +#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_COUNT_RESET 0x1c62 +#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c63 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c64 +#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_STATUS 0x1c65 +#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STEREO_CONTROL 0x1c66 +#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c67 +#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c68 +#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c69 +#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c6a +#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c6b +#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_UPDATE_LOCK 0x1c6c +#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c6d +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MASTER_EN 0x1c6e +#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c70 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c71 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c72 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c73 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c74 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c75 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC_CNTL 0x1c76 +#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c77 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c78 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c79 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c7a +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_R 0x1c7b +#define regOTG2_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_G 0x1c7c +#define regOTG2_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_B 0x1c7d +#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_C 0x1c7e +#define regOTG2_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c7f +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c80 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c81 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c82 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_R 0x1c83 +#define regOTG2_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_G 0x1c84 +#define regOTG2_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_B 0x1c85 +#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_C 0x1c86 +#define regOTG2_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_R 0x1c87 +#define regOTG2_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_G 0x1c88 +#define regOTG2_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_B 0x1c89 +#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_C 0x1c8a +#define regOTG2_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_R 0x1c8b +#define regOTG2_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_G 0x1c8c +#define regOTG2_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_B 0x1c8d +#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_C 0x1c8e +#define regOTG2_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_AES 0x1c8f +#define regOTG2_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c90 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c91 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c92 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c93 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c94 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c95 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c96 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c97 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c98 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c99 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c9a +#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c9b +#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c9c +#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c9d +#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG2_OTG_CLOCK_CONTROL 0x1c9e +#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VSTARTUP_PARAM 0x1c9f +#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_PARAM 0x1ca0 +#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VREADY_PARAM 0x1ca1 +#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1ca2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1ca3 +#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_GSL_CONTROL 0x1ca4 +#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_X 0x1ca5 +#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_Y 0x1ca6 +#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1ca7 +#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL0 0x1ca8 +#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL1 0x1ca9 +#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL2 0x1caa +#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL3 0x1cab +#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL4 0x1cac +#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1cad +#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1caf +#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1cb0 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1cb1 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1cb2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTROL 0x1cb3 +#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTOL2 0x1cb4 +#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO0 0x1cb5 +#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO1 0x1cb6 +#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG2_OTG_REQUEST_CONTROL 0x1cb7 +#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1cb8 +#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PSTATE_REGISTER 0x1cb9 +#define regOTG2_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG2_OTG_ENCRYPTION 0x1cba +#define regOTG2_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG2_OTG_SPARE_REGISTER 0x1cbb +#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg3_dispdec +// base address: 0x660 +#define regOTG3_OTG_H_TOTAL 0x1cc2 +#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_H_BLANK_START_END 0x1cc3 +#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A 0x1cc4 +#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cc5 +#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_H_TIMING_CNTL 0x1cc6 +#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL 0x1cc7 +#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MIN 0x1cc8 +#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MAX 0x1cc9 +#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MID 0x1cca +#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_CONTROL 0x1ccb +#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1ccc +#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1ccd +#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cce +#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1ccf +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_V_BLANK_START_END 0x1cd0 +#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A 0x1cd1 +#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cd2 +#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_CNTL 0x1cd3 +#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cd4 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_CNTL 0x1cd5 +#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cd6 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cd7 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cd9 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG3_OTG_CONTROL 0x1cdb +#define regOTG3_OTG_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DLPC_CONTROL 0x1cdc +#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_PWA_FRAME_SYNC_CONTROL 0x1cdd +#define regOTG3_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_CONTROL 0x1cde +#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_STATUS 0x1cdf +#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1ce0 +#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1ce1 +#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG3_OTG_STATUS 0x1ce2 +#define regOTG3_OTG_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STATUS_POSITION 0x1ce3 +#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ce4 +#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG3_OTG_NOM_VERT_POSITION 0x1ce5 +#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ce6 +#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_VF_COUNT 0x1ce7 +#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_HV_COUNT 0x1ce8 +#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG3_OTG_COUNT_CONTROL 0x1ce9 +#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_COUNT_RESET 0x1cea +#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1ceb +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cec +#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_STATUS 0x1ced +#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STEREO_CONTROL 0x1cee +#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cef +#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cf0 +#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cf1 +#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cf2 +#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cf3 +#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_UPDATE_LOCK 0x1cf4 +#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cf5 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MASTER_EN 0x1cf6 +#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cf8 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1cf9 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1cfa +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1cfb +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1cfc +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cfd +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC_CNTL 0x1cfe +#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cff +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d00 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1d01 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d02 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_R 0x1d03 +#define regOTG3_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_G 0x1d04 +#define regOTG3_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_B 0x1d05 +#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_C 0x1d06 +#define regOTG3_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1d07 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d08 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1d09 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d0a +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_R 0x1d0b +#define regOTG3_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_G 0x1d0c +#define regOTG3_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_B 0x1d0d +#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_C 0x1d0e +#define regOTG3_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_R 0x1d0f +#define regOTG3_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_G 0x1d10 +#define regOTG3_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_B 0x1d11 +#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_C 0x1d12 +#define regOTG3_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_R 0x1d13 +#define regOTG3_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_G 0x1d14 +#define regOTG3_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_B 0x1d15 +#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_C 0x1d16 +#define regOTG3_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_AES 0x1d17 +#define regOTG3_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1d18 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d19 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1d1a +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1d1b +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1d1c +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1d1d +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1d1e +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1d1f +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1d20 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1d21 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d22 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d23 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d24 +#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d25 +#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG3_OTG_CLOCK_CONTROL 0x1d26 +#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VSTARTUP_PARAM 0x1d27 +#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_PARAM 0x1d28 +#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VREADY_PARAM 0x1d29 +#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d2a +#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d2b +#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_GSL_CONTROL 0x1d2c +#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_X 0x1d2d +#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_Y 0x1d2e +#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d2f +#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d30 +#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d31 +#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d32 +#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d33 +#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d34 +#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d35 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d37 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d38 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d39 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d3a +#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTROL 0x1d3b +#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTOL2 0x1d3c +#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO0 0x1d3d +#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO1 0x1d3e +#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG3_OTG_REQUEST_CONTROL 0x1d3f +#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d40 +#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PSTATE_REGISTER 0x1d41 +#define regOTG3_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG3_OTG_ENCRYPTION 0x1d42 +#define regOTG3_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG3_OTG_SPARE_REGISTER 0x1d43 +#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define regGSL_SOURCE_SELECT 0x1e2b +#define regGSL_SOURCE_SELECT_BASE_IDX 2 +#define regOPTC_DLPC_CONTROL 0x1e2c +#define regOPTC_DLPC_CONTROL_BASE_IDX 2 +#define regOPTC_CLOCK_CONTROL 0x1e2d +#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL 0x1e2e +#define regODM_MEM_PWR_CTRL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL3 0x1e30 +#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define regODM_MEM_PWR_STATUS 0x1e31 +#define regODM_MEM_PWR_STATUS_BASE_IDX 2 +#define regOPTC_MISC_SPARE_REGISTER 0x1e32 +#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +// base address: 0x79a8 +#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x1e6a +#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x1e6b +#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON15_PERFCOUNTER_STATE 0x1e6c +#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CNTL 0x1e6d +#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CNTL2 0x1e6e +#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x1e6f +#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x1e70 +#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_HI 0x1e71 +#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_LOW 0x1e72 +#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define regDC_I2C_CONTROL 0x1e98 +#define regDC_I2C_CONTROL_BASE_IDX 2 +#define regDC_I2C_ARBITRATION 0x1e99 +#define regDC_I2C_ARBITRATION_BASE_IDX 2 +#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDC_I2C_SW_STATUS 0x1e9b +#define regDC_I2C_SW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_HW_STATUS 0x1e9c +#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC2_HW_STATUS 0x1e9d +#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC3_HW_STATUS 0x1e9e +#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC4_HW_STATUS 0x1e9f +#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_SPEED 0x1ea2 +#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC1_SETUP 0x1ea3 +#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC2_SPEED 0x1ea4 +#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC2_SETUP 0x1ea5 +#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC3_SPEED 0x1ea6 +#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC3_SETUP 0x1ea7 +#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC4_SPEED 0x1ea8 +#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC4_SETUP 0x1ea9 +#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC5_SPEED 0x1eaa +#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC5_SETUP 0x1eab +#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define regDC_I2C_TRANSACTION0 0x1eae +#define regDC_I2C_TRANSACTION0_BASE_IDX 2 +#define regDC_I2C_TRANSACTION1 0x1eaf +#define regDC_I2C_TRANSACTION1_BASE_IDX 2 +#define regDC_I2C_TRANSACTION2 0x1eb0 +#define regDC_I2C_TRANSACTION2_BASE_IDX 2 +#define regDC_I2C_TRANSACTION3 0x1eb1 +#define regDC_I2C_TRANSACTION3_BASE_IDX 2 +#define regDC_I2C_DATA 0x1eb2 +#define regDC_I2C_DATA_BASE_IDX 2 +#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define regDIO_SCRATCH0 0x1eca +#define regDIO_SCRATCH0_BASE_IDX 2 +#define regDIO_SCRATCH1 0x1ecb +#define regDIO_SCRATCH1_BASE_IDX 2 +#define regDIO_SCRATCH2 0x1ecc +#define regDIO_SCRATCH2_BASE_IDX 2 +#define regDIO_SCRATCH3 0x1ecd +#define regDIO_SCRATCH3_BASE_IDX 2 +#define regDIO_SCRATCH4 0x1ece +#define regDIO_SCRATCH4_BASE_IDX 2 +#define regDIO_SCRATCH5 0x1ecf +#define regDIO_SCRATCH5_BASE_IDX 2 +#define regDIO_SCRATCH6 0x1ed0 +#define regDIO_SCRATCH6_BASE_IDX 2 +#define regDIO_SCRATCH7 0x1ed1 +#define regDIO_SCRATCH7_BASE_IDX 2 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_STATUS 0x1edd +#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL 0x1ede +#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL2 0x1edf +#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define regDIO_CLK_CNTL 0x1ee0 +#define regDIO_CLK_CNTL_BASE_IDX 2 +#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define regDIO_PSP_INTERRUPT_STATUS 0x1f00 +#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 +#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 +#define regDIO_STATUS 0x1f02 +#define regDIO_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec +// base address: 0x0 +#define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d +#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e +#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f +#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG3_STREAM_MAPPER_CONTROL 0x1f10 +#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG4_STREAM_MAPPER_CONTROL 0x1f11 +#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +// base address: 0x7d10 +#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1f44 +#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1f45 +#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1f46 +#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CNTL 0x1f47 +#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CNTL2 0x1f48 +#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1f49 +#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1f4a +#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_HI 0x1f4b +#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_LOW 0x1f4c +#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +// base address: 0x154a0 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 +#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_STATUS 0x206c +#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG0_VPG_MEM_PWR 0x206d +#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_DATA 0x206f +#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_apg_apg_dispdec +// base address: 0x154cc +#define regAPG0_APG_CONTROL 0x2073 +#define regAPG0_APG_CONTROL_BASE_IDX 2 +#define regAPG0_APG_CONTROL2 0x2074 +#define regAPG0_APG_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_GEN_CONTROL 0x2075 +#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG0_APG_PACKET_CONTROL 0x2076 +#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG0_APG_DBG_ACP 0x2077 +#define regAPG0_APG_DBG_ACP_BASE_IDX 2 +#define regAPG0_APG_DBG_AUDIO_INFO 0x2079 +#define regAPG0_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG0_APG_DBG_60958_0 0x207a +#define regAPG0_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG0_APG_DBG_60958_1 0x207b +#define regAPG0_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG0_APG_DBG_60958_2 0x207c +#define regAPG0_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL 0x207d +#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x207e +#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_RESULT 0x207f +#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL0 0x2080 +#define regAPG0_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL1 0x2081 +#define regAPG0_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL2 0x2082 +#define regAPG0_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL3 0x2083 +#define regAPG0_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG0_APG_STATUS 0x2084 +#define regAPG0_APG_STATUS_BASE_IDX 2 +#define regAPG0_APG_STATUS2 0x2085 +#define regAPG0_APG_STATUS2_BASE_IDX 2 +#define regAPG0_APG_DBG_AUDIO_DTO_CNTL 0x2086 +#define regAPG0_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG0_APG_MEM_PWR 0x2087 +#define regAPG0_APG_MEM_PWR_BASE_IDX 2 +#define regAPG0_APG_SPARE 0x2089 +#define regAPG0_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +// base address: 0x15544 +#define regDME0_DME_CONTROL 0x2091 +#define regDME0_DME_CONTROL_BASE_IDX 2 +#define regDME0_DME_MEMORY_CONTROL 0x2092 +#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define regDIG0_DIG_FE_CNTL 0x2093 +#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_FE_CLK_CNTL 0x2094 +#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG0_DIG_FE_EN_CNTL 0x2095 +#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096 +#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097 +#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG0_DIG_CLOCK_PATTERN 0x2098 +#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_TEST_PATTERN 0x2099 +#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a +#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL0 0x209b +#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL1 0x209c +#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d +#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_CONTROL 0x209e +#define regDIG0_HDMI_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_STATUS 0x209f +#define regDIG0_HDMI_STATUS_BASE_IDX 2 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1 +#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3 +#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a4 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a5 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a6 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG0_HDMI_GC 0x20a7 +#define regDIG0_HDMI_GC_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a8 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20a9 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20aa +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ab +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ac +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ad +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20ae +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20af +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG0_HDMI_DB_CONTROL 0x20b0 +#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_0 0x20b1 +#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_1 0x20b2 +#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_0 0x20b3 +#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_1 0x20b4 +#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_0 0x20b5 +#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_1 0x20b6 +#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_0 0x20b7 +#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_1 0x20b8 +#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG0_DIG_FE_AUDIO_CNTL 0x20b9 +#define regDIG0_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CLK_CNTL 0x20ba +#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CNTL 0x20bb +#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_EN_CNTL 0x20bc +#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CNTL 0x20e3 +#define regDIG0_TMDS_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL_CHAR 0x20e4 +#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e5 +#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e6 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e7 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e8 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG0_TMDS_CTL_BITS 0x20ea +#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20eb +#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ec +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ed +#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ee +#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_VERSION 0x20f0 +#define regDIG0_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define regDP0_DP_LINK_CNTL 0x211e +#define regDP0_DP_LINK_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT 0x211f +#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP0_DP_MSA_COLORIMETRY 0x2120 +#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP0_DP_CONFIG 0x2121 +#define regDP0_DP_CONFIG_BASE_IDX 2 +#define regDP0_DP_VID_STREAM_CNTL 0x2122 +#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO 0x2123 +#define regDP0_DP_STEER_FIFO_BASE_IDX 2 +#define regDP0_DP_MSA_MISC 0x2124 +#define regDP0_DP_MSA_MISC_BASE_IDX 2 +#define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125 +#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP0_DP_VID_TIMING 0x2126 +#define regDP0_DP_VID_TIMING_BASE_IDX 2 +#define regDP0_DP_VID_N 0x2127 +#define regDP0_DP_VID_N_BASE_IDX 2 +#define regDP0_DP_VID_M 0x2128 +#define regDP0_DP_VID_M_BASE_IDX 2 +#define regDP0_DP_LINK_FRAMING_CNTL 0x2129 +#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP0_DP_HBR2_EYE_PATTERN 0x212a +#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP0_DP_VID_MSA_VBID 0x212b +#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP0_DP_VID_INTERRUPT_CNTL 0x212c +#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CNTL 0x212d +#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM0 0x212f +#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM1 0x2130 +#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM2 0x2131 +#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP0_DP_DPHY_8B10B_CNTL 0x2132 +#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_PRBS_CNTL 0x2133 +#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_SCRAM_CNTL 0x2134 +#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CONTROL0 0x2135 +#define regDP0_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CONTROL1 0x2136 +#define regDP0_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT0 0x2137 +#define regDP0_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT1 0x2138 +#define regDP0_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT2 0x2139 +#define regDP0_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT3 0x213a +#define regDP0_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_STATUS 0x213b +#define regDP0_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP0_DP_TU_CNTL 0x213c +#define regDP0_DP_TU_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT_DB_CNTL 0x213d +#define regDP0_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL 0x2141 +#define regDP0_DP_SEC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL1 0x2142 +#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING1 0x2143 +#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING2 0x2144 +#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING3 0x2145 +#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING4 0x2146 +#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N 0x2147 +#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N_READBACK 0x2148 +#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M 0x2149 +#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M_READBACK 0x214a +#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_TIMESTAMP 0x214b +#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP0_DP_SEC_PACKET_CNTL 0x214c +#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_CNTL 0x214d +#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_UPDATE 0x214f +#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0 0x2150 +#define regDP0_DP_MSE_SAT0_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1 0x2151 +#define regDP0_DP_MSE_SAT1_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2 0x2152 +#define regDP0_DP_MSE_SAT2_BASE_IDX 2 +#define regDP0_DP_MSE_SAT_UPDATE 0x2153 +#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_LINK_TIMING 0x2154 +#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP0_DP_MSE_MISC_CNTL 0x2155 +#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0_STATUS 0x215d +#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1_STATUS 0x215e +#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2_STATUS 0x215f +#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP0_DP_HBLANK_CONTROL 0x2161 +#define regDP0_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM1 0x2162 +#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM2 0x2163 +#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM3 0x2164 +#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM4 0x2165 +#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL 0x2166 +#define regDP0_DP_MSO_CNTL_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL1 0x2167 +#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO_CNTL 0x2168 +#define regDP0_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL2 0x2169 +#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL3 0x216a +#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL4 0x216b +#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL5 0x216c +#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL6 0x216d +#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL7 0x216e +#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP0_DP_DB_CNTL 0x216f +#define regDP0_DP_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_MSA_VBID_MISC 0x2170 +#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171 +#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP0_DP_ALPM_CNTL 0x2173 +#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP8_CNTL 0x2174 +#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP9_CNTL 0x2175 +#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP10_CNTL 0x2176 +#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP11_CNTL 0x2177 +#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP_EN_DB_STATUS 0x2178 +#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179 +#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a +#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b +#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c +#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d +#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e +#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f +#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182 +#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x2183 +#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING 0x2186 +#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2187 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +// base address: 0x15930 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d +#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_STATUS 0x2190 +#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG1_VPG_MEM_PWR 0x2191 +#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_DATA 0x2193 +#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_apg_apg_dispdec +// base address: 0x1595c +#define regAPG1_APG_CONTROL 0x2197 +#define regAPG1_APG_CONTROL_BASE_IDX 2 +#define regAPG1_APG_CONTROL2 0x2198 +#define regAPG1_APG_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_GEN_CONTROL 0x2199 +#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG1_APG_PACKET_CONTROL 0x219a +#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG1_APG_DBG_ACP 0x219b +#define regAPG1_APG_DBG_ACP_BASE_IDX 2 +#define regAPG1_APG_DBG_AUDIO_INFO 0x219d +#define regAPG1_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG1_APG_DBG_60958_0 0x219e +#define regAPG1_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG1_APG_DBG_60958_1 0x219f +#define regAPG1_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG1_APG_DBG_60958_2 0x21a0 +#define regAPG1_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL 0x21a1 +#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x21a2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_RESULT 0x21a3 +#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL0 0x21a4 +#define regAPG1_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL1 0x21a5 +#define regAPG1_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL2 0x21a6 +#define regAPG1_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL3 0x21a7 +#define regAPG1_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG1_APG_STATUS 0x21a8 +#define regAPG1_APG_STATUS_BASE_IDX 2 +#define regAPG1_APG_STATUS2 0x21a9 +#define regAPG1_APG_STATUS2_BASE_IDX 2 +#define regAPG1_APG_DBG_AUDIO_DTO_CNTL 0x21aa +#define regAPG1_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG1_APG_MEM_PWR 0x21ab +#define regAPG1_APG_MEM_PWR_BASE_IDX 2 +#define regAPG1_APG_SPARE 0x21ad +#define regAPG1_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +// base address: 0x159d4 +#define regDME1_DME_CONTROL 0x21b5 +#define regDME1_DME_CONTROL_BASE_IDX 2 +#define regDME1_DME_MEMORY_CONTROL 0x21b6 +#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x490 +#define regDIG1_DIG_FE_CNTL 0x21b7 +#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_FE_CLK_CNTL 0x21b8 +#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG1_DIG_FE_EN_CNTL 0x21b9 +#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba +#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb +#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG1_DIG_CLOCK_PATTERN 0x21bc +#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_TEST_PATTERN 0x21bd +#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be +#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL0 0x21bf +#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL1 0x21c0 +#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_CONTROL 0x21c2 +#define regDIG1_HDMI_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_STATUS 0x21c3 +#define regDIG1_HDMI_STATUS_BASE_IDX 2 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5 +#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6 +#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7 +#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c8 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21c9 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21ca +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG1_HDMI_GC 0x21cb +#define regDIG1_HDMI_GC_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cc +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21cd +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21ce +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21cf +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d0 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d1 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d3 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG1_HDMI_DB_CONTROL 0x21d4 +#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_0 0x21d5 +#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_1 0x21d6 +#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_0 0x21d7 +#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_1 0x21d8 +#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_0 0x21d9 +#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_1 0x21da +#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_0 0x21db +#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_1 0x21dc +#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG1_DIG_FE_AUDIO_CNTL 0x21dd +#define regDIG1_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CLK_CNTL 0x21de +#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CNTL 0x21df +#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_EN_CNTL 0x21e0 +#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CNTL 0x2207 +#define regDIG1_TMDS_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL_CHAR 0x2208 +#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x2209 +#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220a +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220b +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220c +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG1_TMDS_CTL_BITS 0x220e +#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG1_TMDS_DCBALANCER_CONTROL 0x220f +#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2210 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2211 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2212 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_VERSION 0x2214 +#define regDIG1_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x490 +#define regDP1_DP_LINK_CNTL 0x2242 +#define regDP1_DP_LINK_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT 0x2243 +#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP1_DP_MSA_COLORIMETRY 0x2244 +#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP1_DP_CONFIG 0x2245 +#define regDP1_DP_CONFIG_BASE_IDX 2 +#define regDP1_DP_VID_STREAM_CNTL 0x2246 +#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO 0x2247 +#define regDP1_DP_STEER_FIFO_BASE_IDX 2 +#define regDP1_DP_MSA_MISC 0x2248 +#define regDP1_DP_MSA_MISC_BASE_IDX 2 +#define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249 +#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP1_DP_VID_TIMING 0x224a +#define regDP1_DP_VID_TIMING_BASE_IDX 2 +#define regDP1_DP_VID_N 0x224b +#define regDP1_DP_VID_N_BASE_IDX 2 +#define regDP1_DP_VID_M 0x224c +#define regDP1_DP_VID_M_BASE_IDX 2 +#define regDP1_DP_LINK_FRAMING_CNTL 0x224d +#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP1_DP_HBR2_EYE_PATTERN 0x224e +#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP1_DP_VID_MSA_VBID 0x224f +#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP1_DP_VID_INTERRUPT_CNTL 0x2250 +#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CNTL 0x2251 +#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM0 0x2253 +#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM1 0x2254 +#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM2 0x2255 +#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP1_DP_DPHY_8B10B_CNTL 0x2256 +#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_PRBS_CNTL 0x2257 +#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_SCRAM_CNTL 0x2258 +#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CONTROL0 0x2259 +#define regDP1_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CONTROL1 0x225a +#define regDP1_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT0 0x225b +#define regDP1_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT1 0x225c +#define regDP1_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT2 0x225d +#define regDP1_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT3 0x225e +#define regDP1_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_STATUS 0x225f +#define regDP1_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP1_DP_TU_CNTL 0x2260 +#define regDP1_DP_TU_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT_DB_CNTL 0x2261 +#define regDP1_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL 0x2265 +#define regDP1_DP_SEC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL1 0x2266 +#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING1 0x2267 +#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING2 0x2268 +#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING3 0x2269 +#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING4 0x226a +#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N 0x226b +#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N_READBACK 0x226c +#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M 0x226d +#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M_READBACK 0x226e +#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_TIMESTAMP 0x226f +#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP1_DP_SEC_PACKET_CNTL 0x2270 +#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_CNTL 0x2271 +#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_UPDATE 0x2273 +#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0 0x2274 +#define regDP1_DP_MSE_SAT0_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1 0x2275 +#define regDP1_DP_MSE_SAT1_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2 0x2276 +#define regDP1_DP_MSE_SAT2_BASE_IDX 2 +#define regDP1_DP_MSE_SAT_UPDATE 0x2277 +#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_LINK_TIMING 0x2278 +#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP1_DP_MSE_MISC_CNTL 0x2279 +#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0_STATUS 0x2281 +#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1_STATUS 0x2282 +#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2_STATUS 0x2283 +#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP1_DP_HBLANK_CONTROL 0x2285 +#define regDP1_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM1 0x2286 +#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM2 0x2287 +#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM3 0x2288 +#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM4 0x2289 +#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL 0x228a +#define regDP1_DP_MSO_CNTL_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL1 0x228b +#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO_CNTL 0x228c +#define regDP1_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL2 0x228d +#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL3 0x228e +#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL4 0x228f +#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL5 0x2290 +#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL6 0x2291 +#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL7 0x2292 +#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP1_DP_DB_CNTL 0x2293 +#define regDP1_DP_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_MSA_VBID_MISC 0x2294 +#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295 +#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP1_DP_ALPM_CNTL 0x2297 +#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP8_CNTL 0x2298 +#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP9_CNTL 0x2299 +#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP10_CNTL 0x229a +#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP11_CNTL 0x229b +#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP_EN_DB_STATUS 0x229c +#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d +#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e +#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f +#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0 +#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1 +#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2 +#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3 +#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6 +#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x22a7 +#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING 0x22aa +#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x22ab +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +// base address: 0x15dc0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1 +#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_STATUS 0x22b4 +#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG2_VPG_MEM_PWR 0x22b5 +#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_DATA 0x22b7 +#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_apg_apg_dispdec +// base address: 0x15dec +#define regAPG2_APG_CONTROL 0x22bb +#define regAPG2_APG_CONTROL_BASE_IDX 2 +#define regAPG2_APG_CONTROL2 0x22bc +#define regAPG2_APG_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_GEN_CONTROL 0x22bd +#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG2_APG_PACKET_CONTROL 0x22be +#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG2_APG_DBG_ACP 0x22bf +#define regAPG2_APG_DBG_ACP_BASE_IDX 2 +#define regAPG2_APG_DBG_AUDIO_INFO 0x22c1 +#define regAPG2_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG2_APG_DBG_60958_0 0x22c2 +#define regAPG2_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG2_APG_DBG_60958_1 0x22c3 +#define regAPG2_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG2_APG_DBG_60958_2 0x22c4 +#define regAPG2_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL 0x22c5 +#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x22c6 +#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_RESULT 0x22c7 +#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL0 0x22c8 +#define regAPG2_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL1 0x22c9 +#define regAPG2_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL2 0x22ca +#define regAPG2_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL3 0x22cb +#define regAPG2_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG2_APG_STATUS 0x22cc +#define regAPG2_APG_STATUS_BASE_IDX 2 +#define regAPG2_APG_STATUS2 0x22cd +#define regAPG2_APG_STATUS2_BASE_IDX 2 +#define regAPG2_APG_DBG_AUDIO_DTO_CNTL 0x22ce +#define regAPG2_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG2_APG_MEM_PWR 0x22cf +#define regAPG2_APG_MEM_PWR_BASE_IDX 2 +#define regAPG2_APG_SPARE 0x22d1 +#define regAPG2_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +// base address: 0x15e64 +#define regDME2_DME_CONTROL 0x22d9 +#define regDME2_DME_CONTROL_BASE_IDX 2 +#define regDME2_DME_MEMORY_CONTROL 0x22da +#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dispdec +// base address: 0x920 +#define regDIG2_DIG_FE_CNTL 0x22db +#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_FE_CLK_CNTL 0x22dc +#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG2_DIG_FE_EN_CNTL 0x22dd +#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de +#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df +#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG2_DIG_CLOCK_PATTERN 0x22e0 +#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_TEST_PATTERN 0x22e1 +#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL0 0x22e3 +#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL1 0x22e4 +#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_CONTROL 0x22e6 +#define regDIG2_HDMI_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_STATUS 0x22e7 +#define regDIG2_HDMI_STATUS_BASE_IDX 2 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9 +#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea +#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb +#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ec +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ed +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ee +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG2_HDMI_GC 0x22ef +#define regDIG2_HDMI_GC_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f0 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f1 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f3 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f4 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f5 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f6 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f7 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG2_HDMI_DB_CONTROL 0x22f8 +#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_0 0x22f9 +#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_1 0x22fa +#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_0 0x22fb +#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_1 0x22fc +#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_0 0x22fd +#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_1 0x22fe +#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_0 0x22ff +#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_1 0x2300 +#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG2_DIG_FE_AUDIO_CNTL 0x2301 +#define regDIG2_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CLK_CNTL 0x2302 +#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CNTL 0x2303 +#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_EN_CNTL 0x2304 +#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CNTL 0x232b +#define regDIG2_TMDS_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL_CHAR 0x232c +#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232d +#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232e +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x232f +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2330 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG2_TMDS_CTL_BITS 0x2332 +#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG2_TMDS_DCBALANCER_CONTROL 0x2333 +#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2334 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2335 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2336 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_VERSION 0x2338 +#define regDIG2_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp2_dispdec +// base address: 0x920 +#define regDP2_DP_LINK_CNTL 0x2366 +#define regDP2_DP_LINK_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT 0x2367 +#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP2_DP_MSA_COLORIMETRY 0x2368 +#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP2_DP_CONFIG 0x2369 +#define regDP2_DP_CONFIG_BASE_IDX 2 +#define regDP2_DP_VID_STREAM_CNTL 0x236a +#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO 0x236b +#define regDP2_DP_STEER_FIFO_BASE_IDX 2 +#define regDP2_DP_MSA_MISC 0x236c +#define regDP2_DP_MSA_MISC_BASE_IDX 2 +#define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d +#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP2_DP_VID_TIMING 0x236e +#define regDP2_DP_VID_TIMING_BASE_IDX 2 +#define regDP2_DP_VID_N 0x236f +#define regDP2_DP_VID_N_BASE_IDX 2 +#define regDP2_DP_VID_M 0x2370 +#define regDP2_DP_VID_M_BASE_IDX 2 +#define regDP2_DP_LINK_FRAMING_CNTL 0x2371 +#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP2_DP_HBR2_EYE_PATTERN 0x2372 +#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP2_DP_VID_MSA_VBID 0x2373 +#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP2_DP_VID_INTERRUPT_CNTL 0x2374 +#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CNTL 0x2375 +#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM0 0x2377 +#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM1 0x2378 +#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM2 0x2379 +#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP2_DP_DPHY_8B10B_CNTL 0x237a +#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_PRBS_CNTL 0x237b +#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_SCRAM_CNTL 0x237c +#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CONTROL0 0x237d +#define regDP2_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CONTROL1 0x237e +#define regDP2_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT0 0x237f +#define regDP2_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT1 0x2380 +#define regDP2_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT2 0x2381 +#define regDP2_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT3 0x2382 +#define regDP2_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_STATUS 0x2383 +#define regDP2_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP2_DP_TU_CNTL 0x2384 +#define regDP2_DP_TU_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT_DB_CNTL 0x2385 +#define regDP2_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL 0x2389 +#define regDP2_DP_SEC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL1 0x238a +#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING1 0x238b +#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING2 0x238c +#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING3 0x238d +#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING4 0x238e +#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N 0x238f +#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N_READBACK 0x2390 +#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M 0x2391 +#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M_READBACK 0x2392 +#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_TIMESTAMP 0x2393 +#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP2_DP_SEC_PACKET_CNTL 0x2394 +#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_CNTL 0x2395 +#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_UPDATE 0x2397 +#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0 0x2398 +#define regDP2_DP_MSE_SAT0_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1 0x2399 +#define regDP2_DP_MSE_SAT1_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2 0x239a +#define regDP2_DP_MSE_SAT2_BASE_IDX 2 +#define regDP2_DP_MSE_SAT_UPDATE 0x239b +#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_LINK_TIMING 0x239c +#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP2_DP_MSE_MISC_CNTL 0x239d +#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0_STATUS 0x23a5 +#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1_STATUS 0x23a6 +#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2_STATUS 0x23a7 +#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP2_DP_HBLANK_CONTROL 0x23a9 +#define regDP2_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM1 0x23aa +#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM2 0x23ab +#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM3 0x23ac +#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM4 0x23ad +#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL 0x23ae +#define regDP2_DP_MSO_CNTL_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL1 0x23af +#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO_CNTL 0x23b0 +#define regDP2_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL2 0x23b1 +#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL3 0x23b2 +#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL4 0x23b3 +#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL5 0x23b4 +#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL6 0x23b5 +#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL7 0x23b6 +#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP2_DP_DB_CNTL 0x23b7 +#define regDP2_DP_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_MSA_VBID_MISC 0x23b8 +#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9 +#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP2_DP_ALPM_CNTL 0x23bb +#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP8_CNTL 0x23bc +#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP9_CNTL 0x23bd +#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP10_CNTL 0x23be +#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP11_CNTL 0x23bf +#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP_EN_DB_STATUS 0x23c0 +#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1 +#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2 +#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3 +#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4 +#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5 +#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6 +#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7 +#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca +#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x23cb +#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING 0x23ce +#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x23cf +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +// base address: 0x16250 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5 +#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_STATUS 0x23d8 +#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG3_VPG_MEM_PWR 0x23d9 +#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_DATA 0x23db +#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_apg_apg_dispdec +// base address: 0x1627c +#define regAPG3_APG_CONTROL 0x23df +#define regAPG3_APG_CONTROL_BASE_IDX 2 +#define regAPG3_APG_CONTROL2 0x23e0 +#define regAPG3_APG_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_GEN_CONTROL 0x23e1 +#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG3_APG_PACKET_CONTROL 0x23e2 +#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG3_APG_DBG_ACP 0x23e3 +#define regAPG3_APG_DBG_ACP_BASE_IDX 2 +#define regAPG3_APG_DBG_AUDIO_INFO 0x23e5 +#define regAPG3_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG3_APG_DBG_60958_0 0x23e6 +#define regAPG3_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG3_APG_DBG_60958_1 0x23e7 +#define regAPG3_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG3_APG_DBG_60958_2 0x23e8 +#define regAPG3_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL 0x23e9 +#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x23ea +#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_RESULT 0x23eb +#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL0 0x23ec +#define regAPG3_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL1 0x23ed +#define regAPG3_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL2 0x23ee +#define regAPG3_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL3 0x23ef +#define regAPG3_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG3_APG_STATUS 0x23f0 +#define regAPG3_APG_STATUS_BASE_IDX 2 +#define regAPG3_APG_STATUS2 0x23f1 +#define regAPG3_APG_STATUS2_BASE_IDX 2 +#define regAPG3_APG_DBG_AUDIO_DTO_CNTL 0x23f2 +#define regAPG3_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG3_APG_MEM_PWR 0x23f3 +#define regAPG3_APG_MEM_PWR_BASE_IDX 2 +#define regAPG3_APG_SPARE 0x23f5 +#define regAPG3_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +// base address: 0x162f4 +#define regDME3_DME_CONTROL 0x23fd +#define regDME3_DME_CONTROL_BASE_IDX 2 +#define regDME3_DME_MEMORY_CONTROL 0x23fe +#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dispdec +// base address: 0xdb0 +#define regDIG3_DIG_FE_CNTL 0x23ff +#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_FE_CLK_CNTL 0x2400 +#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG3_DIG_FE_EN_CNTL 0x2401 +#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402 +#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403 +#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG3_DIG_CLOCK_PATTERN 0x2404 +#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_TEST_PATTERN 0x2405 +#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406 +#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL0 0x2407 +#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL1 0x2408 +#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_CONTROL 0x240a +#define regDIG3_HDMI_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_STATUS 0x240b +#define regDIG3_HDMI_STATUS_BASE_IDX 2 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d +#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e +#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f +#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2410 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2411 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2412 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG3_HDMI_GC 0x2413 +#define regDIG3_HDMI_GC_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2414 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2415 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2416 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2417 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2418 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x2419 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241a +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241b +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG3_HDMI_DB_CONTROL 0x241c +#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_0 0x241d +#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_1 0x241e +#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_0 0x241f +#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_1 0x2420 +#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_0 0x2421 +#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_1 0x2422 +#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_0 0x2423 +#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_1 0x2424 +#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG3_DIG_FE_AUDIO_CNTL 0x2425 +#define regDIG3_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CLK_CNTL 0x2426 +#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CNTL 0x2427 +#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_EN_CNTL 0x2428 +#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CNTL 0x244f +#define regDIG3_TMDS_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL_CHAR 0x2450 +#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2451 +#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2452 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2453 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2454 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG3_TMDS_CTL_BITS 0x2456 +#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG3_TMDS_DCBALANCER_CONTROL 0x2457 +#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2458 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x2459 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245a +#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_VERSION 0x245c +#define regDIG3_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp3_dispdec +// base address: 0xdb0 +#define regDP3_DP_LINK_CNTL 0x248a +#define regDP3_DP_LINK_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT 0x248b +#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP3_DP_MSA_COLORIMETRY 0x248c +#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP3_DP_CONFIG 0x248d +#define regDP3_DP_CONFIG_BASE_IDX 2 +#define regDP3_DP_VID_STREAM_CNTL 0x248e +#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO 0x248f +#define regDP3_DP_STEER_FIFO_BASE_IDX 2 +#define regDP3_DP_MSA_MISC 0x2490 +#define regDP3_DP_MSA_MISC_BASE_IDX 2 +#define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491 +#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP3_DP_VID_TIMING 0x2492 +#define regDP3_DP_VID_TIMING_BASE_IDX 2 +#define regDP3_DP_VID_N 0x2493 +#define regDP3_DP_VID_N_BASE_IDX 2 +#define regDP3_DP_VID_M 0x2494 +#define regDP3_DP_VID_M_BASE_IDX 2 +#define regDP3_DP_LINK_FRAMING_CNTL 0x2495 +#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP3_DP_HBR2_EYE_PATTERN 0x2496 +#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP3_DP_VID_MSA_VBID 0x2497 +#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP3_DP_VID_INTERRUPT_CNTL 0x2498 +#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CNTL 0x2499 +#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM0 0x249b +#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM1 0x249c +#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM2 0x249d +#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP3_DP_DPHY_8B10B_CNTL 0x249e +#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_PRBS_CNTL 0x249f +#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0 +#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CONTROL0 0x24a1 +#define regDP3_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CONTROL1 0x24a2 +#define regDP3_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT0 0x24a3 +#define regDP3_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT1 0x24a4 +#define regDP3_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT2 0x24a5 +#define regDP3_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT3 0x24a6 +#define regDP3_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_STATUS 0x24a7 +#define regDP3_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP3_DP_TU_CNTL 0x24a8 +#define regDP3_DP_TU_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT_DB_CNTL 0x24a9 +#define regDP3_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL 0x24ad +#define regDP3_DP_SEC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL1 0x24ae +#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING1 0x24af +#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING2 0x24b0 +#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING3 0x24b1 +#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING4 0x24b2 +#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N 0x24b3 +#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N_READBACK 0x24b4 +#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M 0x24b5 +#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M_READBACK 0x24b6 +#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_TIMESTAMP 0x24b7 +#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP3_DP_SEC_PACKET_CNTL 0x24b8 +#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_CNTL 0x24b9 +#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_UPDATE 0x24bb +#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0 0x24bc +#define regDP3_DP_MSE_SAT0_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1 0x24bd +#define regDP3_DP_MSE_SAT1_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2 0x24be +#define regDP3_DP_MSE_SAT2_BASE_IDX 2 +#define regDP3_DP_MSE_SAT_UPDATE 0x24bf +#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_LINK_TIMING 0x24c0 +#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP3_DP_MSE_MISC_CNTL 0x24c1 +#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0_STATUS 0x24c9 +#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1_STATUS 0x24ca +#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2_STATUS 0x24cb +#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP3_DP_HBLANK_CONTROL 0x24cd +#define regDP3_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM1 0x24ce +#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM2 0x24cf +#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM3 0x24d0 +#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM4 0x24d1 +#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL 0x24d2 +#define regDP3_DP_MSO_CNTL_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL1 0x24d3 +#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO_CNTL 0x24d4 +#define regDP3_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL2 0x24d5 +#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL3 0x24d6 +#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL4 0x24d7 +#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL5 0x24d8 +#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL6 0x24d9 +#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL7 0x24da +#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP3_DP_DB_CNTL 0x24db +#define regDP3_DP_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_MSA_VBID_MISC 0x24dc +#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd +#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP3_DP_ALPM_CNTL 0x24df +#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP8_CNTL 0x24e0 +#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP9_CNTL 0x24e1 +#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP10_CNTL 0x24e2 +#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP11_CNTL 0x24e3 +#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP_EN_DB_STATUS 0x24e4 +#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5 +#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6 +#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7 +#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8 +#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9 +#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea +#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb +#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee +#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x24ef +#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING 0x24f2 +#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24f3 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +// base address: 0x166e0 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x24f8 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_PACKET_DATA 0x24f9 +#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x24fa +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x24fb +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_STATUS 0x24fc +#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG4_VPG_MEM_PWR 0x24fd +#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x24fe +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_DATA 0x24ff +#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_apg_apg_dispdec +// base address: 0x1670c +#define regAPG4_APG_CONTROL 0x2503 +#define regAPG4_APG_CONTROL_BASE_IDX 2 +#define regAPG4_APG_CONTROL2 0x2504 +#define regAPG4_APG_CONTROL2_BASE_IDX 2 +#define regAPG4_APG_DBG_GEN_CONTROL 0x2505 +#define regAPG4_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG4_APG_MEM_PWR 0x2517 +#define regAPG4_APG_MEM_PWR_BASE_IDX 2 + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +// base address: 0x16784 +#define regDME4_DME_CONTROL 0x2521 +#define regDME4_DME_CONTROL_BASE_IDX 2 +#define regDME4_DME_MEMORY_CONTROL 0x2522 +#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dispdec +// base address: 0x1240 +#define regDIG4_DIG_FE_CNTL 0x2523 +#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_FE_CLK_CNTL 0x2524 +#define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG4_DIG_FE_EN_CNTL 0x2525 +#define regDIG4_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x2526 +#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x2527 +#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG4_DIG_CLOCK_PATTERN 0x2528 +#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_TEST_PATTERN 0x2529 +#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x252a +#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL0 0x252b +#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL1 0x252c +#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x252d +#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_CONTROL 0x252e +#define regDIG4_HDMI_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_STATUS 0x252f +#define regDIG4_HDMI_STATUS_BASE_IDX 2 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2530 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2531 +#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2532 +#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2533 +#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2534 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x2535 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x2536 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG4_HDMI_GC 0x2537 +#define regDIG4_HDMI_GC_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2538 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2539 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x253a +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x253b +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x253c +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x253d +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x253e +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x253f +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG4_HDMI_DB_CONTROL 0x2540 +#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_0 0x2541 +#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_1 0x2542 +#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_0 0x2543 +#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_1 0x2544 +#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_0 0x2545 +#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_1 0x2546 +#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_0 0x2547 +#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_1 0x2548 +#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG4_DIG_FE_AUDIO_CNTL 0x2549 +#define regDIG4_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CLK_CNTL 0x254a +#define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CNTL 0x254b +#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_EN_CNTL 0x254c +#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CNTL 0x2573 +#define regDIG4_TMDS_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL_CHAR 0x2574 +#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x2575 +#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x2576 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x2577 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x2578 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG4_TMDS_CTL_BITS 0x257a +#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG4_TMDS_DCBALANCER_CONTROL 0x257b +#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x257c +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x257d +#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x257e +#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_VERSION 0x2580 +#define regDIG4_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp4_dispdec +// base address: 0x1240 +#define regDP4_DP_LINK_CNTL 0x25ae +#define regDP4_DP_LINK_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT 0x25af +#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP4_DP_MSA_COLORIMETRY 0x25b0 +#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP4_DP_CONFIG 0x25b1 +#define regDP4_DP_CONFIG_BASE_IDX 2 +#define regDP4_DP_VID_STREAM_CNTL 0x25b2 +#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO 0x25b3 +#define regDP4_DP_STEER_FIFO_BASE_IDX 2 +#define regDP4_DP_MSA_MISC 0x25b4 +#define regDP4_DP_MSA_MISC_BASE_IDX 2 +#define regDP4_DP_DPHY_INTERNAL_CTRL 0x25b5 +#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP4_DP_VID_TIMING 0x25b6 +#define regDP4_DP_VID_TIMING_BASE_IDX 2 +#define regDP4_DP_VID_N 0x25b7 +#define regDP4_DP_VID_N_BASE_IDX 2 +#define regDP4_DP_VID_M 0x25b8 +#define regDP4_DP_VID_M_BASE_IDX 2 +#define regDP4_DP_LINK_FRAMING_CNTL 0x25b9 +#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP4_DP_HBR2_EYE_PATTERN 0x25ba +#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP4_DP_VID_MSA_VBID 0x25bb +#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP4_DP_VID_INTERRUPT_CNTL 0x25bc +#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CNTL 0x25bd +#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x25be +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM0 0x25bf +#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM1 0x25c0 +#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM2 0x25c1 +#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP4_DP_DPHY_8B10B_CNTL 0x25c2 +#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_PRBS_CNTL 0x25c3 +#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_SCRAM_CNTL 0x25c4 +#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CONTROL0 0x25c5 +#define regDP4_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CONTROL1 0x25c6 +#define regDP4_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT0 0x25c7 +#define regDP4_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT1 0x25c8 +#define regDP4_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT2 0x25c9 +#define regDP4_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT3 0x25ca +#define regDP4_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_STATUS 0x25cb +#define regDP4_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP4_DP_TU_CNTL 0x25cc +#define regDP4_DP_TU_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT_DB_CNTL 0x25cd +#define regDP4_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL 0x25d1 +#define regDP4_DP_SEC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL1 0x25d2 +#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING1 0x25d3 +#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING2 0x25d4 +#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING3 0x25d5 +#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING4 0x25d6 +#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N 0x25d7 +#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N_READBACK 0x25d8 +#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M 0x25d9 +#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M_READBACK 0x25da +#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_TIMESTAMP 0x25db +#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP4_DP_SEC_PACKET_CNTL 0x25dc +#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_CNTL 0x25dd +#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_UPDATE 0x25df +#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0 0x25e0 +#define regDP4_DP_MSE_SAT0_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1 0x25e1 +#define regDP4_DP_MSE_SAT1_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2 0x25e2 +#define regDP4_DP_MSE_SAT2_BASE_IDX 2 +#define regDP4_DP_MSE_SAT_UPDATE 0x25e3 +#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_LINK_TIMING 0x25e4 +#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP4_DP_MSE_MISC_CNTL 0x25e5 +#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x25ea +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x25eb +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0_STATUS 0x25ed +#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1_STATUS 0x25ee +#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2_STATUS 0x25ef +#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP4_DP_HBLANK_CONTROL 0x25f1 +#define regDP4_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM1 0x25f2 +#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM2 0x25f3 +#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM3 0x25f4 +#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM4 0x25f5 +#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL 0x25f6 +#define regDP4_DP_MSO_CNTL_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL1 0x25f7 +#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO_CNTL 0x25f8 +#define regDP4_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL2 0x25f9 +#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL3 0x25fa +#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL4 0x25fb +#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL5 0x25fc +#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL6 0x25fd +#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL7 0x25fe +#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP4_DP_DB_CNTL 0x25ff +#define regDP4_DP_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_MSA_VBID_MISC 0x2600 +#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x2601 +#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP4_DP_ALPM_CNTL 0x2603 +#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP8_CNTL 0x2604 +#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP9_CNTL 0x2605 +#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP10_CNTL 0x2606 +#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP11_CNTL 0x2607 +#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP_EN_DB_STATUS 0x2608 +#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2609 +#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x260a +#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x260b +#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x260c +#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x260d +#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS 0x260e +#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL 0x260f +#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0 0x2610 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1 0x2611 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL 0x2612 +#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x2613 +#define regDP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING 0x2616 +#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2617 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_SPARE_DEBUG 0x3002 +#define regDSC_TOP0_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX 0x3003 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA 0x3004 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define regDSCC0_DSCC_CONFIG0 0x300a +#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG1 0x300b +#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG2 0x300c +#define regDSCC0_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_STATUS 0x300d +#define regDSCC0_DSCC_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL0 0x300e +#define regDSCC0_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL1 0x300f +#define regDSCC0_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_STATUS0 0x3010 +#define regDSCC0_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_STATUS1 0x3011 +#define regDSCC0_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG0 0x3012 +#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG1 0x3013 +#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG2 0x3014 +#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG3 0x3015 +#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG4 0x3016 +#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG5 0x3017 +#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG6 0x3018 +#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG7 0x3019 +#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG8 0x301a +#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG9 0x301b +#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG10 0x301c +#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG11 0x301d +#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG12 0x301e +#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG13 0x301f +#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG14 0x3020 +#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG15 0x3021 +#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG16 0x3022 +#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG17 0x3023 +#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG18 0x3024 +#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG19 0x3025 +#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG20 0x3026 +#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG21 0x3027 +#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG22 0x3028 +#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL0 0x3029 +#define regDSCC0_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL1 0x302a +#define regDSCC0_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x302b +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x302c +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x302d +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x302e +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302f +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3030 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x3031 +#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x3032 +#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3033 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3034 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3035 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3036 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3037 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3038 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3039 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x303a +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX0 0x303b +#define regDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX1 0x303c +#define regDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX2 0x303d +#define regDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX3 0x303e +#define regDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303f +#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x3040 +#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA1 0x3041 +#define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA2 0x3042 +#define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA3 0x3043 +#define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3044 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3045 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc140 +#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x3050 +#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x3051 +#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON17_PERFCOUNTER_STATE 0x3052 +#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CNTL 0x3053 +#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CNTL2 0x3054 +#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x3055 +#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x3056 +#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_HI 0x3057 +#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_LOW 0x3058 +#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_SPARE_DEBUG 0x305e +#define regDSC_TOP1_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX 0x305f +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA 0x3060 +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define regDSCC1_DSCC_CONFIG0 0x3066 +#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG1 0x3067 +#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG2 0x3068 +#define regDSCC1_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_STATUS 0x3069 +#define regDSCC1_DSCC_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL0 0x306a +#define regDSCC1_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL1 0x306b +#define regDSCC1_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_STATUS0 0x306c +#define regDSCC1_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_STATUS1 0x306d +#define regDSCC1_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG0 0x306e +#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG1 0x306f +#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG2 0x3070 +#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG3 0x3071 +#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG4 0x3072 +#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG5 0x3073 +#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG6 0x3074 +#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG7 0x3075 +#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG8 0x3076 +#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG9 0x3077 +#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG10 0x3078 +#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG11 0x3079 +#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG12 0x307a +#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG13 0x307b +#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG14 0x307c +#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG15 0x307d +#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG16 0x307e +#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG17 0x307f +#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG18 0x3080 +#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG19 0x3081 +#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG20 0x3082 +#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG21 0x3083 +#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG22 0x3084 +#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL0 0x3085 +#define regDSCC1_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL1 0x3086 +#define regDSCC1_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3087 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3088 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3089 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x308a +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x308b +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x308c +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x308d +#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x308e +#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x308f +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3090 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3091 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3092 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3093 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3094 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3095 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x3096 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3097 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3098 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3099 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX3 0x309a +#define regDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x309b +#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA0 0x309c +#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA1 0x309d +#define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA2 0x309e +#define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA3 0x309f +#define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30a0 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30a1 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc2b0 +#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x30ac +#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x30ad +#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON18_PERFCOUNTER_STATE 0x30ae +#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CNTL 0x30af +#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CNTL2 0x30b0 +#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x30b1 +#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x30b2 +#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_HI 0x30b3 +#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_LOW 0x30b4 +#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +// base address: 0x2e0 +#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 +#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 +#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_SPARE_DEBUG 0x30ba +#define regDSC_TOP2_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX 0x30bb +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA 0x30bc +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +// base address: 0x2e0 +#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd +#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +// base address: 0x2e0 +#define regDSCC2_DSCC_CONFIG0 0x30c2 +#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG1 0x30c3 +#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG2 0x30c4 +#define regDSCC2_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_STATUS 0x30c5 +#define regDSCC2_DSCC_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL0 0x30c6 +#define regDSCC2_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL1 0x30c7 +#define regDSCC2_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_STATUS0 0x30c8 +#define regDSCC2_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_STATUS1 0x30c9 +#define regDSCC2_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG0 0x30ca +#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG1 0x30cb +#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG2 0x30cc +#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG3 0x30cd +#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG4 0x30ce +#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG5 0x30cf +#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG6 0x30d0 +#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG7 0x30d1 +#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG8 0x30d2 +#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG9 0x30d3 +#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG10 0x30d4 +#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG11 0x30d5 +#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG12 0x30d6 +#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG13 0x30d7 +#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG14 0x30d8 +#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG15 0x30d9 +#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG16 0x30da +#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG17 0x30db +#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG18 0x30dc +#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG19 0x30dd +#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG20 0x30de +#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG21 0x30df +#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG22 0x30e0 +#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL0 0x30e1 +#define regDSCC2_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL1 0x30e2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30e3 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30e4 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e5 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e6 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e7 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e8 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e9 +#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30ea +#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x30eb +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x30ec +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x30ed +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x30ee +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x30ef +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x30f0 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x30f1 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x30f2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30f3 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30f4 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f5 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f6 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f7 +#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f8 +#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f9 +#define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA2 0x30fa +#define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA3 0x30fb +#define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30fc +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30fd +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc420 +#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3108 +#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3109 +#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON19_PERFCOUNTER_STATE 0x310a +#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CNTL 0x310b +#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CNTL2 0x310c +#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x310d +#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x310e +#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_HI 0x310f +#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_LOW 0x3110 +#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +// base address: 0x450 +#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 +#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 +#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP3_DSC_SPARE_DEBUG 0x3116 +#define regDSC_TOP3_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX 0x3117 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA 0x3118 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +// base address: 0x450 +#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 +#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +// base address: 0x450 +#define regDSCC3_DSCC_CONFIG0 0x311e +#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_CONFIG1 0x311f +#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_CONFIG2 0x3120 +#define regDSCC3_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC3_DSCC_STATUS 0x3121 +#define regDSCC3_DSCC_STATUS_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_CONTROL0 0x3122 +#define regDSCC3_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_CONTROL1 0x3123 +#define regDSCC3_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_STATUS0 0x3124 +#define regDSCC3_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_STATUS1 0x3125 +#define regDSCC3_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG0 0x3126 +#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG1 0x3127 +#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG2 0x3128 +#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG3 0x3129 +#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG4 0x312a +#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG5 0x312b +#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG6 0x312c +#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG7 0x312d +#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG8 0x312e +#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG9 0x312f +#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG10 0x3130 +#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG11 0x3131 +#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG12 0x3132 +#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG13 0x3133 +#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG14 0x3134 +#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG15 0x3135 +#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG16 0x3136 +#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG17 0x3137 +#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG18 0x3138 +#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG19 0x3139 +#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG20 0x313a +#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG21 0x313b +#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG22 0x313c +#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC3_DSCC_MEM_POWER_CONTROL0 0x313d +#define regDSCC3_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC3_DSCC_MEM_POWER_CONTROL1 0x313e +#define regDSCC3_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313f +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3140 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3141 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3142 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3143 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3144 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3145 +#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3146 +#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3147 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3148 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3149 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x314a +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x314b +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x314c +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x314d +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x314e +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314f +#define regDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX1 0x3150 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX2 0x3151 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX3 0x3152 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x3153 +#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA0 0x3154 +#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA1 0x3155 +#define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA2 0x3156 +#define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA3 0x3157 +#define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3158 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3159 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc590 +#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x3164 +#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x3165 +#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON20_PERFCOUNTER_STATE 0x3166 +#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CNTL 0x3167 +#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CNTL2 0x3168 +#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x3169 +#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x316a +#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_HI 0x316b +#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_LOW 0x316c +#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +// base address: 0x0 +#define regDWB_ENABLE_CLK_CTRL 0x3228 +#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 +#define regDWB_MEM_PWR_CTRL 0x3229 +#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 +#define regFC_MODE_CTRL 0x322a +#define regFC_MODE_CTRL_BASE_IDX 2 +#define regFC_FLOW_CTRL 0x322b +#define regFC_FLOW_CTRL_BASE_IDX 2 +#define regFC_WINDOW_START 0x322c +#define regFC_WINDOW_START_BASE_IDX 2 +#define regFC_WINDOW_SIZE 0x322d +#define regFC_WINDOW_SIZE_BASE_IDX 2 +#define regFC_SOURCE_SIZE 0x322e +#define regFC_SOURCE_SIZE_BASE_IDX 2 +#define regDWB_UPDATE_CTRL 0x322f +#define regDWB_UPDATE_CTRL_BASE_IDX 2 +#define regDWB_CRC_CTRL 0x3230 +#define regDWB_CRC_CTRL_BASE_IDX 2 +#define regDWB_CRC_MASK_R_G 0x3231 +#define regDWB_CRC_MASK_R_G_BASE_IDX 2 +#define regDWB_CRC_MASK_B_A 0x3232 +#define regDWB_CRC_MASK_B_A_BASE_IDX 2 +#define regDWB_CRC_VAL_R_G 0x3233 +#define regDWB_CRC_VAL_R_G_BASE_IDX 2 +#define regDWB_CRC_VAL_B_A 0x3234 +#define regDWB_CRC_VAL_B_A_BASE_IDX 2 +#define regDWB_OUT_CTRL 0x3235 +#define regDWB_OUT_CTRL_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 +#define regDWB_HOST_READ_CONTROL 0x3238 +#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 +#define regDWB_OVERFLOW_STATUS 0x3239 +#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 +#define regDWB_OVERFLOW_COUNTER 0x323a +#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 +#define regDWB_SOFT_RESET 0x323b +#define regDWB_SOFT_RESET_BASE_IDX 2 +#define regDWB_DEBUG_CTRL 0x323c +#define regDWB_DEBUG_CTRL_BASE_IDX 2 +#define regDWB_DEBUG 0x323d +#define regDWB_DEBUG_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0xca20 +#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3288 +#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3289 +#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON21_PERFCOUNTER_STATE 0x328a +#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CNTL 0x328b +#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CNTL2 0x328c +#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x328d +#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x328e +#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_HI 0x328f +#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_LOW 0x3290 +#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +// base address: 0x0 +#define regDWB_HDR_MULT_COEF 0x3294 +#define regDWB_HDR_MULT_COEF_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_MODE 0x3295 +#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 +#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 +#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 +#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 +#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C23_C24 0x329a +#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C31_C32 0x329b +#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C33_C34 0x329c +#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C11_C12 0x329d +#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C13_C14 0x329e +#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C21_C22 0x329f +#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 +#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 +#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 +#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 +#define regDWB_OGAM_CONTROL 0x32a3 +#define regDWB_OGAM_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_LUT_INDEX 0x32a4 +#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 +#define regDWB_OGAM_LUT_DATA 0x32a5 +#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 +#define regDWB_OGAM_LUT_CONTROL 0x32a6 +#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 +#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 +#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 +#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 +#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 +#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 +#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 +#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 +#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 +#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 +#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 +#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 +#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 +#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba +#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb +#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc +#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd +#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_10_11 0x32be +#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf +#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 +#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 +#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 +#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 +#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 +#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 +#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 +#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 +#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 +#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 +#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca +#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb +#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc +#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 +#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 +#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 +#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 +#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 +#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 +#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 +#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_G 0x32da +#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_R 0x32db +#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc +#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd +#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_4_5 0x32de +#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_6_7 0x32df +#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 +#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 +#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 +#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 +#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 +#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 +#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 +#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 +#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 +#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 +#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea +#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb +#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec +#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +// base address: 0x0 +#define regDCHVM_CTRL0 0x3603 +#define regDCHVM_CTRL0_BASE_IDX 2 +#define regDCHVM_CTRL1 0x3604 +#define regDCHVM_CTRL1_BASE_IDX 2 +#define regDCHVM_CLK_CTRL 0x3605 +#define regDCHVM_CLK_CTRL_BASE_IDX 2 +#define regDCHVM_MEM_CTRL 0x3606 +#define regDCHVM_MEM_CTRL_BASE_IDX 2 +#define regDCHVM_RIOMMU_CTRL0 0x3607 +#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 +#define regDCHVM_RIOMMU_STAT0 0x3608 +#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +// base address: 0x1ab8c +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +// base address: 0x1abc0 +#define regAPG5_APG_CONTROL 0x3630 +#define regAPG5_APG_CONTROL_BASE_IDX 2 +#define regAPG5_APG_CONTROL2 0x3631 +#define regAPG5_APG_CONTROL2_BASE_IDX 2 +#define regAPG5_APG_DBG_GEN_CONTROL 0x3632 +#define regAPG5_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG5_APG_MEM_PWR 0x3644 +#define regAPG5_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +// base address: 0x1ac38 +#define regDME5_DME_CONTROL 0x364e +#define regDME5_DME_CONTROL_BASE_IDX 2 +#define regDME5_DME_MEMORY_CONTROL 0x364f +#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +// base address: 0x1ac44 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG5_VPG_GENERIC_PACKET_DATA 0x3652 +#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG5_VPG_GENERIC_STATUS 0x3655 +#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG5_VPG_MEM_PWR 0x3656 +#define regVPG5_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x3657 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG5_VPG_ISRC1_2_DATA 0x3658 +#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +// base address: 0x1ac74 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2 0x368a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3 0x368b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x368f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3690 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3691 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3692 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3693 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS 0x3694 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL 0x3695 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3696 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3697 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3698 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x3699 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +// base address: 0x1ad7c +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x369f +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x36a0 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +// base address: 0x1add0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36b4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36b5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36b8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36b9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36ba +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36bb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36bc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36bf +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36c0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36c1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36c2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36c5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36c6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36c7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36c8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 0x36cb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 0x36cc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 0x36cd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 0x36ce +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 0x36cf +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x36d0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x36d1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL 0x36d3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36d7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36d8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36d9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36da +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36db +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36dc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36dd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36de +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36df +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36e8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36e9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ea +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +// base address: 0x1aedc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +// base address: 0x1af10 +#define regAPG6_APG_CONTROL 0x3704 +#define regAPG6_APG_CONTROL_BASE_IDX 2 +#define regAPG6_APG_CONTROL2 0x3705 +#define regAPG6_APG_CONTROL2_BASE_IDX 2 +#define regAPG6_APG_DBG_GEN_CONTROL 0x3706 +#define regAPG6_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG6_APG_MEM_PWR 0x3718 +#define regAPG6_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +// base address: 0x1af88 +#define regDME6_DME_CONTROL 0x3722 +#define regDME6_DME_CONTROL_BASE_IDX 2 +#define regDME6_DME_MEMORY_CONTROL 0x3723 +#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +// base address: 0x1af94 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3726 +#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_STATUS 0x3729 +#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG6_VPG_MEM_PWR 0x372a +#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x372b +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_DATA 0x372c +#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +// base address: 0x1afc4 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2 0x375e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3 0x375f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x3760 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3761 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3762 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3763 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3764 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3765 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3766 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3767 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS 0x3768 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL 0x3769 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x376a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x376b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x376c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x376d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +// base address: 0x1b0cc +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x3773 +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x3774 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +// base address: 0x1b120 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3788 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3789 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x378c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x378d +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x378e +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x378f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3790 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x3793 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x3794 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x3795 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x3796 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3799 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x379a +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x379b +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x379c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 0x379f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 0x37a0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 0x37a1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 0x37a2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 0x37a3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x37a4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x37a5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL 0x37a7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37a8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37a9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37aa +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ab +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37ac +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37ad +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37ae +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37af +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37b7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37b8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37b9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bc +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37bd +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37be +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +// base address: 0x1b22c +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +// base address: 0x1b260 +#define regAPG7_APG_CONTROL 0x37d8 +#define regAPG7_APG_CONTROL_BASE_IDX 2 +#define regAPG7_APG_CONTROL2 0x37d9 +#define regAPG7_APG_CONTROL2_BASE_IDX 2 +#define regAPG7_APG_DBG_GEN_CONTROL 0x37da +#define regAPG7_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG7_APG_MEM_PWR 0x37ec +#define regAPG7_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +// base address: 0x1b2d8 +#define regDME7_DME_CONTROL 0x37f6 +#define regDME7_DME_CONTROL_BASE_IDX 2 +#define regDME7_DME_MEMORY_CONTROL 0x37f7 +#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +// base address: 0x1b2e4 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_PACKET_DATA 0x37fa +#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_STATUS 0x37fd +#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG7_VPG_MEM_PWR 0x37fe +#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x37ff +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_DATA 0x3800 +#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +// base address: 0x1b314 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2 0x3832 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3 0x3833 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3834 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3835 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3836 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3837 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3838 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3839 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL 0x383a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x383b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS 0x383c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL 0x383d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x383e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x383f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3840 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3841 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc2_dispdec +// base address: 0x1b41c +#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL 0x3847 +#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE 0x3848 +#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym322_dispdec +// base address: 0x1b470 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL 0x385c +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS 0x385d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE 0x3860 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3861 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3862 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3863 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3864 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 0x3867 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 0x3868 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 0x3869 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 0x386a +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 0x386d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 0x386e +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 0x386f +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3870 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 0x3873 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 0x3874 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 0x3875 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 0x3876 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 0x3877 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x3878 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x3879 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL 0x387b +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG 0x387c +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 0x387d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 0x387e +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 0x387f +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3880 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE 0x3881 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 0x3882 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 0x3883 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 0x3884 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 0x3885 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 0x3886 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 0x3887 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 0x3888 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 0x3889 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 0x388a +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 0x388b +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 0x388c +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS 0x388d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3890 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3891 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3892 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +// base address: 0x1b57c +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +// base address: 0x1b5b0 +#define regAPG8_APG_CONTROL 0x38ac +#define regAPG8_APG_CONTROL_BASE_IDX 2 +#define regAPG8_APG_CONTROL2 0x38ad +#define regAPG8_APG_CONTROL2_BASE_IDX 2 +#define regAPG8_APG_DBG_GEN_CONTROL 0x38ae +#define regAPG8_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG8_APG_MEM_PWR 0x38c0 +#define regAPG8_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +// base address: 0x1b628 +#define regDME8_DME_CONTROL 0x38ca +#define regDME8_DME_CONTROL_BASE_IDX 2 +#define regDME8_DME_MEMORY_CONTROL 0x38cb +#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +// base address: 0x1b634 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_PACKET_DATA 0x38ce +#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_STATUS 0x38d1 +#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG8_VPG_MEM_PWR 0x38d2 +#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_DATA 0x38d4 +#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +// base address: 0x1b664 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2 0x3906 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3 0x3907 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3908 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3909 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x390a +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x390b +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x390c +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x390d +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL 0x390e +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x390f +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS 0x3910 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL 0x3911 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3912 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3913 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3914 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3915 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc3_dispdec +// base address: 0x1b76c +#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL 0x391b +#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE 0x391c +#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym323_dispdec +// base address: 0x1b7c0 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL 0x3930 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS 0x3931 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE 0x3934 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3935 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3936 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3937 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3938 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 0x393b +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 0x393c +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 0x393d +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 0x393e +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3941 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 0x3942 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 0x3943 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3944 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 0x3947 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 0x3948 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 0x3949 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 0x394a +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 0x394b +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x394c +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x394d +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL 0x394f +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG 0x3950 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 0x3951 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 0x3952 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 0x3953 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3954 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE 0x3955 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 0x3956 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 0x3957 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 0x3958 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 0x3959 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 0x395a +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 0x395b +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 0x395c +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 0x395d +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 0x395e +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 0x395f +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 0x3960 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS 0x3961 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3964 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3965 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3966 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define regMPCC0_MPCC_TOP_SEL 0x0000 +#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_SEL 0x0001 +#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_OPP_ID 0x0002 +#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL 0x0003 +#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL2 0x0004 +#define regMPCC0_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC0_MPCC_SM_CONTROL 0x0005 +#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0006 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_TOP_GAIN 0x0007 +#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0008 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0009 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x000a +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_BG_R_CR 0x000b +#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC0_MPCC_BG_G_Y 0x000c +#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC0_MPCC_BG_B_CB 0x000d +#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000e +#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC0_MPCC_STATUS 0x000f +#define regMPCC0_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x54 +#define regMPCC1_MPCC_TOP_SEL 0x0015 +#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_SEL 0x0016 +#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_OPP_ID 0x0017 +#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL 0x0018 +#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL2 0x0019 +#define regMPCC1_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC1_MPCC_SM_CONTROL 0x001a +#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001b +#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_TOP_GAIN 0x001c +#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001d +#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001e +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001f +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_BG_R_CR 0x0020 +#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC1_MPCC_BG_G_Y 0x0021 +#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC1_MPCC_BG_B_CB 0x0022 +#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0023 +#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC1_MPCC_STATUS 0x0024 +#define regMPCC1_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +// base address: 0xa8 +#define regMPCC2_MPCC_TOP_SEL 0x002a +#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_SEL 0x002b +#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_OPP_ID 0x002c +#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL 0x002d +#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL2 0x002e +#define regMPCC2_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC2_MPCC_SM_CONTROL 0x002f +#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0030 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_TOP_GAIN 0x0031 +#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0032 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0033 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0034 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_BG_R_CR 0x0035 +#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC2_MPCC_BG_G_Y 0x0036 +#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC2_MPCC_BG_B_CB 0x0037 +#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0038 +#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC2_MPCC_STATUS 0x0039 +#define regMPCC2_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +// base address: 0xfc +#define regMPCC3_MPCC_TOP_SEL 0x003f +#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_SEL 0x0040 +#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_OPP_ID 0x0041 +#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL 0x0042 +#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL2 0x0043 +#define regMPCC3_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC3_MPCC_SM_CONTROL 0x0044 +#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0045 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_TOP_GAIN 0x0046 +#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0047 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0048 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0049 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_BG_R_CR 0x004a +#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC3_MPCC_BG_G_Y 0x004b +#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC3_MPCC_BG_B_CB 0x004c +#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004d +#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC3_MPCC_STATUS 0x004e +#define regMPCC3_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x007e +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x007f +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0080 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0081 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0082 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0083 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0084 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0085 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0086 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0087 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0088 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0089 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x008a +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x008b +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x008c +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x008d +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x008e +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x008f +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0090 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0091 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0092 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0093 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0094 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0095 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0096 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0097 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x0098 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x0099 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x009a +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x009b +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x009c +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x009d +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x009e +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x009f +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00a0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00a1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00a2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00a3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00a4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00a5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00a6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00a7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00a8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00a9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00aa +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00ab +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00ac +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00ad +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00ae +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00af +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00b0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00b1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00b2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00b3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00b4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00b5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00b6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00b7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00b8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00b9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00ba +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00bb +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00bc +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00bd +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00be +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00bf +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00c0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00c1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00c2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00c3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00c4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00c5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00c6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00c7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00c8 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00c9 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00ca +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00cb +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00cc +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00cd +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00ce +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00cf +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00d0 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00d1 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00d2 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00d3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00d4 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00d5 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x178 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x00dc +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x00dd +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x00de +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x00df +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x00e0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x00e1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x00e2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00e3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00e4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00e5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00e6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00e7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00e8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x00e9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x00ea +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x00eb +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x00ec +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x00ed +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ee +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x00ef +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x00f0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x00f1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x00f2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x00f3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x00f4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x00f5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x00f6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x00f7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x00f8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x00f9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x00fa +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x00fb +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x00fc +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x00fd +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x00fe +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x00ff +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x0100 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x0101 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x0102 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x0103 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x0104 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x0105 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0106 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0107 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0108 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0109 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x010a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x010b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x010c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x010d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x010e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x010f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x0110 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x0111 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x0112 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x0113 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x0114 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x0115 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0116 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0117 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0118 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0119 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x011a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x011b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x011c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x011d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x011e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x011f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x0120 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x0121 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x0122 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x0123 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x0124 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x0125 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0126 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0127 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0128 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0129 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x012a +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x012b +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x012c +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x012d +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x012e +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x012f +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x0130 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x0131 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x0132 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x0133 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +// base address: 0x2f0 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x013a +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x013b +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x013c +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x013d +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x013e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x013f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0140 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0141 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0142 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0143 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0144 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0145 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0146 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0147 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0148 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0149 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x014a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x014b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x014c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x014d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x014e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x014f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0150 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0151 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0152 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0153 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x0154 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x0155 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0156 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0157 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0158 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0159 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x015a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x015b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x015c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x015d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x015e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x015f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0160 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0161 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0162 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0163 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0164 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0165 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0166 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0167 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0168 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0169 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x016a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x016b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x016c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x016d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x016e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x016f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0170 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0171 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0172 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0173 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x0174 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x0175 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x0176 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x0177 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x0178 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x0179 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x017a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x017b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x017c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x017d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x017e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x017f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0180 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0181 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0182 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0183 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0184 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x0185 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x0186 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x0187 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x0188 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x0189 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x018a +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x018b +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x018c +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x018d +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x018e +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x018f +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0190 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0191 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +// base address: 0x468 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0198 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0199 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x019a +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x019b +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x019c +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x019d +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x019e +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x019f +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01a0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01a1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01a2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01a3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01a4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01a5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01a6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01a7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01a8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01a9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01aa +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01ab +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01ac +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01ad +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01ae +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01af +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01b0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01b1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01b2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01b3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01b4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01b5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01b6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01b7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01b8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01b9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01ba +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01bb +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01bc +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01bd +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01be +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01bf +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01c0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01c1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01c2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01c3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01c4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01c5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01c6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01c7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01c8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01c9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01ca +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01cb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01cc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01cd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01ce +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01cf +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01d0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01d1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01d2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01d3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01d4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01d5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x01d6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x01d7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x01d8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x01d9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x01da +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x01db +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x01dc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x01dd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x01de +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x01df +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x01e0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x01e1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01e2 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x01e3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x01e4 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x01e5 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x01e6 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x01e7 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x01e8 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x01e9 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x01ea +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x01eb +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x01ec +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x01ed +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x01ee +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x01ef +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define regMPC_OUT0_MUX 0x02b2 +#define regMPC_OUT0_MUX_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CONTROL 0x02b3 +#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x02b4 +#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x02b5 +#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT1_MUX 0x02b6 +#define regMPC_OUT1_MUX_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CONTROL 0x02b7 +#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x02b8 +#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x02b9 +#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT2_MUX 0x02ba +#define regMPC_OUT2_MUX_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CONTROL 0x02bb +#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x02bc +#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x02bd +#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT3_MUX 0x02be +#define regMPC_OUT3_MUX_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CONTROL 0x02bf +#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x02c0 +#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x02c1 +#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT_CSC_COEF_FORMAT 0x02ca +#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 +#define regMPC_OUT0_CSC_MODE 0x02cb +#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_A 0x02cc +#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_A 0x02cd +#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_A 0x02ce +#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_A 0x02cf +#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_A 0x02d0 +#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_A 0x02d1 +#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_B 0x02d2 +#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_B 0x02d3 +#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_B 0x02d4 +#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_B 0x02d5 +#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_B 0x02d6 +#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_B 0x02d7 +#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_MODE 0x02d8 +#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_A 0x02d9 +#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_A 0x02da +#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_A 0x02db +#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_A 0x02dc +#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_A 0x02dd +#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_A 0x02de +#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_B 0x02df +#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_B 0x02e0 +#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_B 0x02e1 +#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_B 0x02e2 +#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_B 0x02e3 +#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_B 0x02e4 +#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_MODE 0x02e5 +#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_A 0x02e6 +#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_A 0x02e7 +#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_A 0x02e8 +#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_A 0x02e9 +#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_A 0x02ea +#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_A 0x02eb +#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_B 0x02ec +#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_B 0x02ed +#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_B 0x02ee +#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_B 0x02ef +#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_B 0x02f0 +#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_B 0x02f1 +#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_MODE 0x02f2 +#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_A 0x02f3 +#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_A 0x02f4 +#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_A 0x02f5 +#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_A 0x02f6 +#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_A 0x02f7 +#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_A 0x02f8 +#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_B 0x02f9 +#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_B 0x02fa +#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_B 0x02fb +#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_B 0x02fc +#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_B 0x02fd +#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_B 0x02fe +#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OCSC_TEST_DEBUG_INDEX 0x031b +#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_OCSC_TEST_DEBUG_DATA 0x031c +#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_rmcm0_dispdec +// base address: 0x0 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_CONTROL 0x031f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R 0x0320 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G 0x0321 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B 0x0322 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R 0x0323 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B 0x0324 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX 0x0325 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA 0x0326 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x0327 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x0328 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x0329 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x032a +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x032b +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x032c +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x032d +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1 0x032e +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3 0x032f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5 0x0330 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7 0x0331 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9 0x0332 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11 0x0333 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13 0x0334 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15 0x0335 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17 0x0336 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19 0x0337 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21 0x0338 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23 0x0339 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25 0x033a +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27 0x033b +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29 0x033c +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31 0x033d +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33 0x033e +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B 0x033f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G 0x0340 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R 0x0341 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B 0x0342 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G 0x0343 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R 0x0344 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1 0x0345 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3 0x0346 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5 0x0347 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7 0x0348 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9 0x0349 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11 0x034a +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13 0x034b +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15 0x034c +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17 0x034d +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19 0x034e +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21 0x034f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23 0x0350 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25 0x0351 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27 0x0352 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29 0x0353 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31 0x0354 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33 0x0355 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_MODE 0x0356 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_MODE_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_INDEX 0x0357 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA 0x0358 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT 0x0359 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x035a +#define regMPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x035b +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R 0x035c +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G 0x035d +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B 0x035e +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x035f +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE 0x0360 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A 0x0361 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A 0x0362 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A 0x0363 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A 0x0364 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A 0x0365 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A 0x0366 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B 0x0367 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B 0x0368 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B 0x0369 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B 0x036a +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B 0x036b +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B 0x036c +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL 0x036d +#define regMPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x036e +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS 0x036f +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_CNTL 0x0370 +#define regMPC_RMCM0_MPC_RMCM_CNTL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX 0x0372 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA 0x0373 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_rmcm1_dispdec +// base address: 0x168 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_CONTROL 0x0379 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R 0x037a +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G 0x037b +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B 0x037c +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R 0x037d +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B 0x037e +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX 0x037f +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA 0x0380 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x0381 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x0382 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x0383 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x0384 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x0385 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x0386 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x0387 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1 0x0388 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3 0x0389 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5 0x038a +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7 0x038b +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9 0x038c +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11 0x038d +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13 0x038e +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15 0x038f +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17 0x0390 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19 0x0391 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21 0x0392 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23 0x0393 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25 0x0394 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27 0x0395 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29 0x0396 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31 0x0397 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33 0x0398 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B 0x0399 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G 0x039a +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R 0x039b +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B 0x039c +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G 0x039d +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R 0x039e +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1 0x039f +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3 0x03a0 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5 0x03a1 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7 0x03a2 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9 0x03a3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11 0x03a4 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13 0x03a5 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15 0x03a6 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17 0x03a7 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19 0x03a8 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21 0x03a9 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23 0x03aa +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25 0x03ab +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27 0x03ac +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29 0x03ad +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31 0x03ae +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33 0x03af +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_MODE 0x03b0 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_MODE_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_INDEX 0x03b1 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA 0x03b2 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT 0x03b3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x03b4 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x03b5 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R 0x03b6 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G 0x03b7 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B 0x03b8 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x03b9 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE 0x03ba +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A 0x03bb +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A 0x03bc +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A 0x03bd +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A 0x03be +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A 0x03bf +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A 0x03c0 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B 0x03c1 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B 0x03c2 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B 0x03c3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B 0x03c4 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B 0x03c5 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B 0x03c6 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL 0x03c7 +#define regMPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x03c8 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS 0x03c9 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_CNTL 0x03ca +#define regMPC_RMCM1_MPC_RMCM_CNTL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_INDEX 0x03cc +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_DATA 0x03cd +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +// base address: 0x17e1c +#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0447 +#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 +#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0448 +#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define regDC_PERFMON22_PERFCOUNTER_STATE 0x0449 +#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CNTL 0x044a +#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CNTL2 0x044b +#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x044c +#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x044d +#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_HI 0x044e +#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_LOW 0x044f +#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec +// base address: 0x0 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x04dd +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x04de +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x04df +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x04e0 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x04e1 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x04e2 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x04e3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x04e4 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x04e5 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x04e6 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x04e7 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x04e8 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x04e9 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x04ea +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x04eb +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x04ec +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x04ed +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x04ee +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x04ef +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x04f0 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x04f1 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x04f2 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x04f3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x04f4 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x04f5 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x04f6 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x04f7 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x04f8 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04f9 +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x04fa +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x04fb +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec +// base address: 0x2c0 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x0503 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x0504 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x0505 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x0506 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x0507 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x0508 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x0509 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x050a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x050b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x050c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x050d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x050e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x050f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0510 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0511 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0512 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0513 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0514 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0515 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0516 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0517 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0518 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0519 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x051a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x051b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x051c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x051d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x051e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x051f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0520 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0521 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0522 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0523 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0524 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0525 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0526 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0527 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0528 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0529 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x052a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x052b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x052c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x052d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x052e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x052f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0530 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0531 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0532 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0533 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0534 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0535 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0536 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0537 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0538 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0539 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x053a +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x053b +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x053c +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x053d +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x053e +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x053f +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0540 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0541 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0542 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0543 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0544 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0545 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0546 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0547 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0548 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0549 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x054a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x054b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x054c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x054d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x054e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x054f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0550 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0551 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0552 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0553 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0554 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0555 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0556 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0557 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0558 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0559 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x055a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x055b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x055c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x055d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x055e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x055f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0560 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0561 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0562 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0563 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0564 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0565 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0566 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0567 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0568 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0569 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x056a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x056b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x056c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x056d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x056e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x056f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0570 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0571 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0572 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0573 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0574 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0575 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0576 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0577 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0578 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0579 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x057a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x057b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x057c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x057d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x057e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x057f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0580 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0581 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0582 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0583 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0584 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0585 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0586 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0587 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0588 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0589 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x058a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x058b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x058c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x058d +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x058e +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x058f +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0590 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0591 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0592 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0593 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0594 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0595 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0596 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0597 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0598 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0599 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x059a +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x059b +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x059c +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x059d +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x059e +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x059f +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x05a0 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x05a1 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x05a2 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x05a3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x05a4 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x05a5 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x05a6 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x05a7 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x05a8 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x05a9 +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x05aa +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x05ab +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec +// base address: 0x580 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x05b3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x05b4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x05b5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x05b6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x05b7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x05b8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x05b9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x05ba +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x05bb +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x05bc +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x05bd +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x05be +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x05bf +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x05c0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x05c1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x05c2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x05c3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x05c4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x05c5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x05c6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x05c7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x05c8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x05c9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x05ca +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x05cb +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x05cc +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x05cd +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x05ce +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x05cf +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x05d0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x05d1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x05d2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x05d3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x05d4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x05d5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x05d6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x05d7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x05d8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x05d9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x05da +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x05db +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x05dc +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x05dd +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x05de +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x05df +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05e0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05e1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05e2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05e3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05e4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05e5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05e6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05e7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05e8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05e9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05ea +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05eb +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ec +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ed +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ee +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05ef +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05f0 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05f1 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05f2 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05f3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05f4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05f5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05f6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05f7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05f8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05f9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05fa +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05fb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05fc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05fd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05fe +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05ff +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0600 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0601 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0602 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0603 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0604 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0605 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0606 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0607 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0608 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0609 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x060a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x060b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x060c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x060d +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x060e +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x060f +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0610 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0611 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0612 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0613 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0614 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0615 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0616 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0617 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0618 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0619 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x061a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x061b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x061c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x061d +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x061e +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x061f +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0620 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0621 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0622 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0623 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0624 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0625 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0626 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0627 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0628 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0629 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x062a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x062b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x062c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x062d +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x062e +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x062f +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0630 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0631 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0632 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0633 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0634 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0635 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0636 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0637 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0638 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0639 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x063a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x063b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x063c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x063d +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x063e +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x063f +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0640 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0641 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0642 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0643 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0644 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0645 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0646 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0647 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0648 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0649 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x064a +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x064b +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x064c +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x064d +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x064e +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x064f +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0650 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0651 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0652 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0653 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0654 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0655 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0656 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0657 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0658 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x0659 +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x065a +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x065b +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec +// base address: 0x840 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0663 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0664 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0665 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0666 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0667 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0668 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0669 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x066a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x066b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x066c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x066d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x066e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x066f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0670 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0671 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0672 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0673 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0674 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0675 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0676 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0677 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0678 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0679 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x067a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x067b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x067c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x067d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x067e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x067f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0680 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0681 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0682 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0683 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0684 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0685 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0686 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0687 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0688 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0689 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x068a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x068b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x068c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x068d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x068e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x068f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0690 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0691 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0692 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0693 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0694 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0695 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0696 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0697 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0698 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0699 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x069a +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x069b +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x069c +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x069d +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x069e +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x069f +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x06a0 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x06a1 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x06a2 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x06a3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x06a4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x06a5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x06a6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x06a7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x06a8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x06a9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x06aa +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x06ab +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x06ac +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x06ad +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x06ae +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x06af +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x06b0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x06b1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x06b2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x06b3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x06b4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x06b5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x06b6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x06b7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x06b8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x06b9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x06ba +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x06bb +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x06bc +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x06bd +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x06be +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x06bf +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x06c0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x06c1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x06c2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x06c3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x06c4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x06c5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x06c6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x06c7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x06c8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x06c9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x06ca +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x06cb +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x06cc +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x06cd +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x06ce +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x06cf +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x06d0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x06d1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x06d2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x06d3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x06d4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x06d5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x06d6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x06d7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x06d8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x06d9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x06da +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x06db +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x06dc +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x06dd +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x06de +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x06df +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x06e0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x06e1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x06e2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x06e3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x06e4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x06e5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x06e6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x06e7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x06e8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x06e9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x06ea +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x06eb +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x06ec +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x06ed +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x06ee +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x06ef +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x06f0 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x06f1 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x06f2 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x06f3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x06f4 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x06f5 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x06f6 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x06f7 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x06f8 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x06f9 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x06fa +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x06fb +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x06fc +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x06fd +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x06fe +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x06ff +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0700 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0701 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0702 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0703 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0704 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0705 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0706 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0707 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0708 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x0709 +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x070a +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x070b +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define regMPC_CLOCK_CONTROL 0x0873 +#define regMPC_CLOCK_CONTROL_BASE_IDX 3 +#define regMPC_SOFT_RESET 0x0874 +#define regMPC_SOFT_RESET_BASE_IDX 3 +#define regMPC_CRC_CTRL 0x0875 +#define regMPC_CRC_CTRL_BASE_IDX 3 +#define regMPC_CRC_SEL_CONTROL 0x0876 +#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 +#define regMPC_CRC_RESULT_A 0x0877 +#define regMPC_CRC_RESULT_A_BASE_IDX 3 +#define regMPC_CRC_RESULT_R 0x0878 +#define regMPC_CRC_RESULT_R_BASE_IDX 3 +#define regMPC_CRC_RESULT_G 0x0879 +#define regMPC_CRC_RESULT_G_BASE_IDX 3 +#define regMPC_CRC_RESULT_B 0x087a +#define regMPC_CRC_RESULT_B_BASE_IDX 3 +#define regMPC_PERFMON_EVENT_CTRL 0x087d +#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 +#define regMPC_BYPASS_BG_AR 0x087e +#define regMPC_BYPASS_BG_AR_BASE_IDX 3 +#define regMPC_BYPASS_BG_GB 0x087f +#define regMPC_BYPASS_BG_GB_BASE_IDX 3 +#define regMPC_HOST_READ_CONTROL 0x0880 +#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 +#define regMPC_DPP_PENDING_STATUS 0x0881 +#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 +#define regMPC_PENDING_STATUS_MISC 0x0882 +#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x0883 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET0 0x0884 +#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET0 0x0885 +#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET0 0x0886 +#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET0 0x0887 +#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0888 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET1 0x0889 +#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET1 0x088a +#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET1 0x088b +#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET1 0x088c +#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x088d +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET2 0x088e +#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET2 0x088f +#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET2 0x0890 +#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET2 0x0891 +#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x0892 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET3 0x0893 +#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET3 0x0894 +#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET3 0x0895 +#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET3 0x0896 +#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regHUBP0_3DLUT_FL_CONFIG 0x0897 +#define regHUBP0_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP0_3DLUT_FL_BIAS_SCALE 0x0898 +#define regHUBP0_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regHUBP1_3DLUT_FL_CONFIG 0x0899 +#define regHUBP1_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP1_3DLUT_FL_BIAS_SCALE 0x089a +#define regHUBP1_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regHUBP2_3DLUT_FL_CONFIG 0x089b +#define regHUBP2_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP2_3DLUT_FL_BIAS_SCALE 0x089c +#define regHUBP2_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regHUBP3_3DLUT_FL_CONFIG 0x089d +#define regHUBP3_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP3_3DLUT_FL_BIAS_SCALE 0x089e +#define regHUBP3_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regMPC_DWB0_MUX 0x08ad +#define regMPC_DWB0_MUX_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d4 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d5 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 +#define regHDMI_STREAM_ENC_AUDIO_CONTROL 0x08d8 +#define regHDMI_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 +#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_apg_apg_dispdec +// base address: 0x2644c +#define regAPG9_APG_CONTROL 0x0913 +#define regAPG9_APG_CONTROL_BASE_IDX 3 +#define regAPG9_APG_CONTROL2 0x0914 +#define regAPG9_APG_CONTROL2_BASE_IDX 3 +#define regAPG9_APG_DBG_GEN_CONTROL 0x0915 +#define regAPG9_APG_DBG_GEN_CONTROL_BASE_IDX 3 +#define regAPG9_APG_MEM_PWR 0x0927 +#define regAPG9_APG_MEM_PWR_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +// base address: 0x264c4 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 +#define regVPG9_VPG_GENERIC_PACKET_DATA 0x0932 +#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 +#define regVPG9_VPG_GENERIC_STATUS 0x0935 +#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 3 +#define regVPG9_VPG_MEM_PWR 0x0936 +#define regVPG9_VPG_MEM_PWR_BASE_IDX 3 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x0937 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 +#define regVPG9_VPG_ISRC1_2_DATA 0x0938 +#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +// base address: 0x264f0 +#define regDME9_DME_CONTROL 0x093c +#define regDME9_DME_CONTROL_BASE_IDX 3 +#define regDME9_DME_MEMORY_CONTROL 0x093d +#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x2790c +#define regHPO_TOP_CLOCK_CONTROL 0x0e43 +#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 +#define regHPO_TOP_HW_CONTROL 0x0e44 +#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +// base address: 0x27958 +#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 +#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 +#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 +#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 +#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a698 +#define regDC_PERFMON23_PERFCOUNTER_CNTL 0x0e66 +#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 3 +#define regDC_PERFMON23_PERFCOUNTER_CNTL2 0x0e67 +#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define regDC_PERFMON23_PERFCOUNTER_STATE 0x0e68 +#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CNTL 0x0e69 +#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CNTL2 0x0e6a +#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x0e6b +#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CVALUE_LOW 0x0e6c +#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_HI 0x0e6d +#define regDC_PERFMON23_PERFMON_HI_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_LOW 0x0e6e +#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b +#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 +#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_CNTL 0x0e82 +#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e83 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_PWL_CNTL 0x0e84 +#define regABM0_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0e85 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e86 +#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e88 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e89 +#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e8a +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0e8b +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e8c +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e8d +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e8e +#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e8f +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e90 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e91 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e92 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e93 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e94 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0e95 +#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e96 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e97 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e98 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e99 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0e9a +#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0e9b +#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0e9c +#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0e9d +#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_INDEX 0x0e9e +#define regABM0_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_DATA 0x0e9f +#define regABM0_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0ea0 +#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm1_dispdec +// base address: 0x104 +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc +#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 +#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_CNTL 0x0ec3 +#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec4 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_PWL_CNTL 0x0ec5 +#define regABM1_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0ec6 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ec7 +#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ec9 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0eca +#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ecb +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0ecc +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ecd +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ece +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ecf +#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed0 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed1 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed2 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed4 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0ed5 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0ed6 +#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0ed7 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0ed8 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0ed9 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0eda +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0edb +#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0edc +#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0edd +#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0ede +#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_INDEX 0x0edf +#define regABM1_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_DATA 0x0ee0 +#define regABM1_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ee1 +#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm2_dispdec +// base address: 0x208 +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_USER_LEVEL 0x0efd +#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 +#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_CNTL 0x0f04 +#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f05 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_PWL_CNTL 0x0f06 +#define regABM2_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f07 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f08 +#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f0a +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f0b +#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f0c +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0f0d +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f0e +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f0f +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f10 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f11 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f12 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f13 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f14 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f15 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f16 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f17 +#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f18 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f19 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1a +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1b +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f1c +#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f1d +#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f1e +#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f1f +#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_INDEX 0x0f20 +#define regABM2_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_DATA 0x0f21 +#define regABM2_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f22 +#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm3_dispdec +// base address: 0x30c +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e +#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 +#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_CNTL 0x0f45 +#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f46 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_PWL_CNTL 0x0f47 +#define regABM3_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f48 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f49 +#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f4b +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f4c +#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f4d +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0f4e +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f4f +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f50 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f51 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f52 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f53 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f54 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f55 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f56 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f57 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f58 +#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f59 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5a +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5b +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f5c +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f5d +#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f5e +#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f5f +#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f60 +#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_INDEX 0x0f61 +#define regABM3_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_DATA 0x0f62 +#define regABM3_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f63 +#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dpia_dpia_mu0_dpiadec +// base address: 0x72000 +#define regDPIA_MU_CLOCK_CTRL 0x13800 +#define regDPIA_MU_CLOCK_CTRL_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0 0x13801 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT0 0x13802 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1 0x13803 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT1 0x13804 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2 0x13805 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT2 0x13806 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3 0x13807 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT3 0x13808 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT0 0x13811 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT1 0x13812 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT2 0x13813 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT3 0x13814 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX 3 +#define regDPIA_MU_TPI_MAX_CREDIT_COUNT 0x13819 +#define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX 3 +#define regDPIA_MU_INTERRUPT_STATUS 0x1381a +#define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX 3 +#define regDPIA_MU_INTERRUPT_CTRL 0x1381b +#define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX 3 +#define regDPIA_MU_LOCAL_INTERRUPT_CTRL 0x1381c +#define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX 3 +#define regDPIA_MU_LOCAL_INTERRUPT_ACK 0x1381d +#define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX 3 +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL 0x1381e +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX 3 +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2 0x1381f +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX 3 +#define regDPIA_MU_RBBMIF_STATUS 0x13820 +#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX 3 +#define regDPIA_MU_MICROSECOND_REF_CTRL 0x13821 +#define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX 3 +#define regDPIA_MU_PORT_ADP_STATUS 0x13822 +#define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX 3 +#define regDPIA_GLUE_CTRL 0x13823 +#define regDPIA_GLUE_CTRL_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL0 0x13825 +#define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL1 0x13826 +#define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL2 0x13827 +#define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL3 0x13828 +#define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL4 0x13829 +#define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL5 0x1382a +#define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX 3 +#define regDPIA_PERF_COUNT_INDEX 0x1382b +#define regDPIA_PERF_COUNT_INDEX_BASE_IDX 3 +#define regDPIA_PERF_COUNT_DATA_LO 0x1382c +#define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX 3 +#define regDPIA_MU_SPARE 0x1382d +#define regDPIA_MU_SPARE_BASE_IDX 3 + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x1300000 +#define regGLOBAL_CAPABILITIES 0x4b7000 +#define regGLOBAL_CAPABILITIES_BASE_IDX 3 +#define regMINOR_VERSION 0x4b7000 +#define regMINOR_VERSION_BASE_IDX 3 +#define regMAJOR_VERSION 0x4b7000 +#define regMAJOR_VERSION_BASE_IDX 3 +#define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001 +#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regINPUT_PAYLOAD_CAPABILITY 0x4b7001 +#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regGLOBAL_CONTROL 0x4b7002 +#define regGLOBAL_CONTROL_BASE_IDX 3 +#define regWAKE_ENABLE 0x4b7003 +#define regWAKE_ENABLE_BASE_IDX 3 +#define regSTATE_CHANGE_STATUS 0x4b7003 +#define regSTATE_CHANGE_STATUS_BASE_IDX 3 +#define regGLOBAL_STATUS 0x4b7004 +#define regGLOBAL_STATUS_BASE_IDX 3 +#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 +#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 +#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regINTERRUPT_CONTROL 0x4b7008 +#define regINTERRUPT_CONTROL_BASE_IDX 3 +#define regINTERRUPT_STATUS 0x4b7009 +#define regINTERRUPT_STATUS_BASE_IDX 3 +#define regWALL_CLOCK_COUNTER 0x4b700c +#define regWALL_CLOCK_COUNTER_BASE_IDX 3 +#define regSTREAM_SYNCHRONIZATION 0x4b700e +#define regSTREAM_SYNCHRONIZATION_BASE_IDX 3 +#define regCORB_LOWER_BASE_ADDRESS 0x4b7010 +#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regCORB_UPPER_BASE_ADDRESS 0x4b7011 +#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x4b7012 +#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_READ_POINTER 0x4b7012 +#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_CONTROL 0x4b7013 +#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_STATUS 0x4b7013 +#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_SIZE 0x4b7013 +#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x4b7014 +#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x4b7015 +#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x4b7016 +#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 3 +#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x4b7016 +#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_CONTROL 0x4b7017 +#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_STATUS 0x4b7017 +#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_SIZE 0x4b7017 +#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 +#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x4b701a +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 +#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c +#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d +#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x4b780c +#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x1300000 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x1300000 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x1300000 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x1300000 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7020 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7021 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7022 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7023 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7024 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7024 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7026 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7027 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7821 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x1300020 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7028 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7029 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b702a +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b702b +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b702c +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b702c +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b702e +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b702f +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7829 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x1300040 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7030 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7031 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7032 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7033 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7034 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7034 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7036 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7037 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7831 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x1300060 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7038 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7039 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b703a +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b703b +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b703c +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b703c +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b703e +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b703f +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7839 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x1300080 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7040 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7041 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7042 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7043 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7044 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7044 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7046 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7047 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7841 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0x13000a0 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7048 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7049 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b704a +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b704b +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b704c +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b704c +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b704e +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b704f +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7849 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0x13000c0 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7050 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7051 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7052 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7053 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7054 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7054 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7056 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7057 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7851 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0x13000e0 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7058 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7059 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b705a +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b705b +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b705c +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b705c +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b705e +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b705f +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7859 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h new file mode 100644 index 0000000000000..4ed96244f61b2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h @@ -0,0 +1,67277 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dcn_4_2_0_SH_MASK_HEADER +#define _dcn_4_2_0_SH_MASK_HEADER + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//AZCONTROLLER0_CORB_WRITE_POINTER +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER0_CORB_READ_POINTER +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_CORB_CONTROL +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER0_CORB_STATUS +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER0_CORB_SIZE +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_RIRB_WRITE_POINTER +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER0_RIRB_CONTROL +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER0_RIRB_STATUS +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER0_RIRB_SIZE +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dc_perfmon_dc_perfmondebugind +//PERFMON_DEBUG_ID +#define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID__SHIFT 0x0 +#define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID_MASK 0xFFFFFFFFL +//PERFMON_DEBUG01 +#define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG02 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG03 +#define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG04 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG05 +#define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG06 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG07 +#define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG08 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG09 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_START__SHIFT 0x0 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP__SHIFT 0x1 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_START_MASK 0x00000001L +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP_MASK 0x00000002L +//PERFMON_DEBUG0A +#define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0B +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG0C +#define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0D +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG0E +#define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0F +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG10 +#define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG11 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG12 +#define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF__SHIFT 0x0 +#define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF__SHIFT 0x1 +#define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF__SHIFT 0x2 +#define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF__SHIFT 0x3 +#define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF__SHIFT 0x4 +#define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF__SHIFT 0x5 +#define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF__SHIFT 0x6 +#define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF__SHIFT 0x7 +#define PERFMON_DEBUG12__PERFCOUNTER_OFF__SHIFT 0x8 +#define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF_MASK 0x00000001L +#define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF_MASK 0x00000002L +#define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF_MASK 0x00000004L +#define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF_MASK 0x00000008L +#define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF_MASK 0x00000010L +#define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF_MASK 0x00000020L +#define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF_MASK 0x00000040L +#define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF_MASK 0x00000080L +#define PERFMON_DEBUG12__PERFCOUNTER_OFF_MASK 0x00000100L + + +// addressBlock: mcif_wb0_mcif_wbdebugind +//MCIF_WB_DEBUG_ID +#define MCIF_WB_DEBUG_ID__MCIF_WB_DEBUG_ID__SHIFT 0x0 +#define MCIF_WB_DEBUG_ID__MCIF_WB_DEBUG_ID_MASK 0xFFFFFFFFL +//ID01_WB_FMT_DBG +#define ID01_WB_FMT_DBG__ID01_WB_FMT_DBG__SHIFT 0x0 +#define ID01_WB_FMT_DBG__ID01_WB_FMT_DBG_MASK 0xFFFFFFFFL +//ID02_WB_FMT_DBG +#define ID02_WB_FMT_DBG__ID02_WB_FMT_DBG__SHIFT 0x0 +#define ID02_WB_FMT_DBG__ID02_WB_FMT_DBG_MASK 0xFFFFFFFFL +//ID03_WB_FMT_DBG +#define ID03_WB_FMT_DBG__ID03_WB_FMT_DBG__SHIFT 0x0 +#define ID03_WB_FMT_DBG__ID03_WB_FMT_DBG_MASK 0xFFFFFFFFL +//ID04_WB_MGR_DBG +#define ID04_WB_MGR_DBG__ID04_WB_MGR_DBG__SHIFT 0x0 +#define ID04_WB_MGR_DBG__ID04_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID05_WB_MGR_DBG +#define ID05_WB_MGR_DBG__ID05_WB_MGR_DBG__SHIFT 0x0 +#define ID05_WB_MGR_DBG__ID05_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID06_WB_MGR_DBG +#define ID06_WB_MGR_DBG__ID06_WB_MGR_DBG__SHIFT 0x0 +#define ID06_WB_MGR_DBG__ID06_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID07_WB_MGR_DBG +#define ID07_WB_MGR_DBG__ID07_WB_MGR_DBG__SHIFT 0x0 +#define ID07_WB_MGR_DBG__ID07_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID08_WB_ARB_DBG +#define ID08_WB_ARB_DBG__ID08_WB_ARB_DBG__SHIFT 0x0 +#define ID08_WB_ARB_DBG__ID08_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID09_WB_ARB_DBG +#define ID09_WB_ARB_DBG__ID09_WB_ARB_DBG__SHIFT 0x0 +#define ID09_WB_ARB_DBG__ID09_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0A_WB_ARB_DBG +#define ID0A_WB_ARB_DBG__ID0A_WB_ARB_DBG__SHIFT 0x0 +#define ID0A_WB_ARB_DBG__ID0A_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0B_WB_ARB_DBG +#define ID0B_WB_ARB_DBG__ID0B_WB_ARB_DBG__SHIFT 0x0 +#define ID0B_WB_ARB_DBG__ID0B_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0C_WB_ARB_DBG +#define ID0C_WB_ARB_DBG__ID0C_WB_ARB_DBG__SHIFT 0x0 +#define ID0C_WB_ARB_DBG__ID0C_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0D_WB_ARB_DBG +#define ID0D_WB_ARB_DBG__ID0D_WB_ARB_DBG__SHIFT 0x0 +#define ID0D_WB_ARB_DBG__ID0D_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0E_WB_ARB_DBG +#define ID0E_WB_ARB_DBG__ID0E_WB_ARB_DBG__SHIFT 0x0 +#define ID0E_WB_ARB_DBG__ID0E_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0F_P010_WB_FMT_DBG_Y +#define ID0F_P010_WB_FMT_DBG_Y__ID0F_P010_WB_FMT_DBG_Y__SHIFT 0x0 +#define ID0F_P010_WB_FMT_DBG_Y__ID0F_P010_WB_FMT_DBG_Y_MASK 0xFFFFFFFFL +//ID10_P010_WB_FMT_DBG_C +#define ID10_P010_WB_FMT_DBG_C__ID10_P010_WB_FMT_DBG_C__SHIFT 0x0 +#define ID10_P010_WB_FMT_DBG_C__ID10_P010_WB_FMT_DBG_C_MASK 0xFFFFFFFFL +//ID11_WB_ARB_P010_DBG +#define ID11_WB_ARB_P010_DBG__ID11_WB_ARB_P010_DBG__SHIFT 0x0 +#define ID11_WB_ARB_P010_DBG__ID11_WB_ARB_P010_DBG_MASK 0xFFFFFFFFL +//ID12_WB_ARB_P010_DBG +#define ID12_WB_ARB_P010_DBG__ID12_WB_ARB_P010_DBG__SHIFT 0x0 +#define ID12_WB_ARB_P010_DBG__ID12_WB_ARB_P010_DBG_MASK 0xFFFFFFFFL + + +// addressBlock: hubbub_dchubbubdebugind +//DCHUBBUB_KEY_STATUS_DEBUG_1 +#define DCHUBBUB_KEY_STATUS_DEBUG_1__DCHUBBUB_KEY_STATUS_DEBUG_1__SHIFT 0x0 +#define DCHUBBUB_KEY_STATUS_DEBUG_1__DCHUBBUB_KEY_STATUS_DEBUG_1_MASK 0xFFFFFFFFL +//DCHUBBUB_KEY_STATUS_DEBUG_2 +#define DCHUBBUB_KEY_STATUS_DEBUG_2__DCHUBBUB_KEY_STATUS_DEBUG_2__SHIFT 0x0 +#define DCHUBBUB_KEY_STATUS_DEBUG_2__DCHUBBUB_KEY_STATUS_DEBUG_2_MASK 0xFFFFFFFFL + + +// addressBlock: odm0_odmdebugind +//ODM0_OPTC_INPUT_DEBUG_ID +#define ODM0_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM0_OPTC_INPUT_DEBUG0 +#define ODM0_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM0_OPTC_INPUT_DEBUG1 +#define ODM0_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM0_OPTC_INPUT_DEBUG2 +#define ODM0_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: odm1_odmdebugind +//ODM1_OPTC_INPUT_DEBUG_ID +#define ODM1_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM1_OPTC_INPUT_DEBUG0 +#define ODM1_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM1_OPTC_INPUT_DEBUG1 +#define ODM1_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM1_OPTC_INPUT_DEBUG2 +#define ODM1_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: odm2_odmdebugind +//ODM2_OPTC_INPUT_DEBUG_ID +#define ODM2_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM2_OPTC_INPUT_DEBUG0 +#define ODM2_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM2_OPTC_INPUT_DEBUG1 +#define ODM2_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM2_OPTC_INPUT_DEBUG2 +#define ODM2_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: odm3_odmdebugind +//ODM3_OPTC_INPUT_DEBUG_ID +#define ODM3_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM3_OPTC_INPUT_DEBUG0 +#define ODM3_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM3_OPTC_INPUT_DEBUG1 +#define ODM3_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM3_OPTC_INPUT_DEBUG2 +#define ODM3_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: rbbmif_rbbmifdebugind +//RBBMIF_DEBUG_ID +#define RBBMIF_DEBUG_ID__RBBMIF_DEBUG_ID__SHIFT 0x0 +#define RBBMIF_DEBUG_ID__RBBMIF_DEBUG_ID_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_0 +#define RBBMIF_DEBUG_0__RBBMIF_DEBUG_0__SHIFT 0x0 +#define RBBMIF_DEBUG_0__RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_1 +#define RBBMIF_DEBUG_1__RBBMIF_DEBUG_1__SHIFT 0x0 +#define RBBMIF_DEBUG_1__RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_2 +#define RBBMIF_DEBUG_2__RBBMIF_DEBUG_2__SHIFT 0x0 +#define RBBMIF_DEBUG_2__RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_3 +#define RBBMIF_DEBUG_3__RBBMIF_DEBUG_3__SHIFT 0x0 +#define RBBMIF_DEBUG_3__RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_4 +#define RBBMIF_DEBUG_4__RBBMIF_DEBUG_4__SHIFT 0x0 +#define RBBMIF_DEBUG_4__RBBMIF_DEBUG_4_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_5 +#define RBBMIF_DEBUG_5__DBG_RBBMIF_DC_0__SHIFT 0x0 +#define RBBMIF_DEBUG_5__DBG_RBBMIF_DC_0_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_6 +#define RBBMIF_DEBUG_6__DBG_RBBMIF_DC_1__SHIFT 0x0 +#define RBBMIF_DEBUG_6__DBG_RBBMIF_DC_1_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_7 +#define RBBMIF_DEBUG_7__DBG_RBBMIF_DC_2__SHIFT 0x0 +#define RBBMIF_DEBUG_7__DBG_RBBMIF_DC_2_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_8 +#define RBBMIF_DEBUG_8__DBG_RBBMIF_DC_3__SHIFT 0x0 +#define RBBMIF_DEBUG_8__DBG_RBBMIF_DC_3_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_9 +#define RBBMIF_DEBUG_9__DBG_RBBMIF_DC_4__SHIFT 0x0 +#define RBBMIF_DEBUG_9__DBG_RBBMIF_DC_4_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_10 +#define RBBMIF_DEBUG_10__DBG_RBBMIF_DC_5__SHIFT 0x0 +#define RBBMIF_DEBUG_10__DBG_RBBMIF_DC_5_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_11 +#define RBBMIF_DEBUG_11__DBG_RBBMIF_DC_6__SHIFT 0x0 +#define RBBMIF_DEBUG_11__DBG_RBBMIF_DC_6_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_12 +#define RBBMIF_DEBUG_12__DBG_RBBMIF_DC_7__SHIFT 0x0 +#define RBBMIF_DEBUG_12__DBG_RBBMIF_DC_7_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_13 +#define RBBMIF_DEBUG_13__DBG_RBBMIF_DC_8__SHIFT 0x0 +#define RBBMIF_DEBUG_13__DBG_RBBMIF_DC_8_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_14 +#define RBBMIF_DEBUG_14__DBG_RBBMIF_DC_9__SHIFT 0x0 +#define RBBMIF_DEBUG_14__DBG_RBBMIF_DC_9_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_15 +#define RBBMIF_DEBUG_15__DBG_RBBMIF_DC_10__SHIFT 0x0 +#define RBBMIF_DEBUG_15__DBG_RBBMIF_DC_10_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_16 +#define RBBMIF_DEBUG_16__DBG_RBBMIF_DC_11__SHIFT 0x0 +#define RBBMIF_DEBUG_16__DBG_RBBMIF_DC_11_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_17 +#define RBBMIF_DEBUG_17__DBG_RBBMIF_DC_12__SHIFT 0x0 +#define RBBMIF_DEBUG_17__DBG_RBBMIF_DC_12_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_18 +#define RBBMIF_DEBUG_18__DBG_RBBMIF_DC_13__SHIFT 0x0 +#define RBBMIF_DEBUG_18__DBG_RBBMIF_DC_13_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_19 +#define RBBMIF_DEBUG_19__DBG_RBBMIF_DC_14__SHIFT 0x0 +#define RBBMIF_DEBUG_19__DBG_RBBMIF_DC_14_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_20 +#define RBBMIF_DEBUG_20__DBG_RBBMIF_DC_15__SHIFT 0x0 +#define RBBMIF_DEBUG_20__DBG_RBBMIF_DC_15_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_21 +#define RBBMIF_DEBUG_21__DBG_RBBMIF_DC_16__SHIFT 0x0 +#define RBBMIF_DEBUG_21__DBG_RBBMIF_DC_16_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_22 +#define RBBMIF_DEBUG_22__DBG_RBBMIF_DC_17__SHIFT 0x0 +#define RBBMIF_DEBUG_22__DBG_RBBMIF_DC_17_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_23 +#define RBBMIF_DEBUG_23__DBG_RBBMIF_DC_18__SHIFT 0x0 +#define RBBMIF_DEBUG_23__DBG_RBBMIF_DC_18_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_24 +#define RBBMIF_DEBUG_24__DBG_RBBMIF_DC_19__SHIFT 0x0 +#define RBBMIF_DEBUG_24__DBG_RBBMIF_DC_19_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_25 +#define RBBMIF_DEBUG_25__DBG_RBBMIF_DC_20__SHIFT 0x0 +#define RBBMIF_DEBUG_25__DBG_RBBMIF_DC_20_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_26 +#define RBBMIF_DEBUG_26__DBG_RBBMIF_DC_21__SHIFT 0x0 +#define RBBMIF_DEBUG_26__DBG_RBBMIF_DC_21_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_27 +#define RBBMIF_DEBUG_27__DBG_RBBMIF_DC_22__SHIFT 0x0 +#define RBBMIF_DEBUG_27__DBG_RBBMIF_DC_22_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_28 +#define RBBMIF_DEBUG_28__DBG_RBBMIF_DC_23__SHIFT 0x0 +#define RBBMIF_DEBUG_28__DBG_RBBMIF_DC_23_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_29 +#define RBBMIF_DEBUG_29__DBG_RBBMIF_DC_24__SHIFT 0x0 +#define RBBMIF_DEBUG_29__DBG_RBBMIF_DC_24_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_30 +#define RBBMIF_DEBUG_30__DBG_RBBMIF_DC_25__SHIFT 0x0 +#define RBBMIF_DEBUG_30__DBG_RBBMIF_DC_25_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_31 +#define RBBMIF_DEBUG_31__DBG_RBBMIF_DC_26__SHIFT 0x0 +#define RBBMIF_DEBUG_31__DBG_RBBMIF_DC_26_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_32 +#define RBBMIF_DEBUG_32__DBG_RBBMIF_DC_27__SHIFT 0x0 +#define RBBMIF_DEBUG_32__DBG_RBBMIF_DC_27_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_33 +#define RBBMIF_DEBUG_33__DBG_RBBMIF_DC_28__SHIFT 0x0 +#define RBBMIF_DEBUG_33__DBG_RBBMIF_DC_28_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_34 +#define RBBMIF_DEBUG_34__DBG_RBBMIF_DC_29__SHIFT 0x0 +#define RBBMIF_DEBUG_34__DBG_RBBMIF_DC_29_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_35 +#define RBBMIF_DEBUG_35__DBG_RBBMIF_DC_30__SHIFT 0x0 +#define RBBMIF_DEBUG_35__DBG_RBBMIF_DC_30_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_36 +#define RBBMIF_DEBUG_36__DBG_RBBMIF_DC_31__SHIFT 0x0 +#define RBBMIF_DEBUG_36__DBG_RBBMIF_DC_31_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_37 +#define RBBMIF_DEBUG_37__DBG_RBBMIF_DC_32__SHIFT 0x0 +#define RBBMIF_DEBUG_37__DBG_RBBMIF_DC_32_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_38 +#define RBBMIF_DEBUG_38__DBG_RBBMIF_DC_33__SHIFT 0x0 +#define RBBMIF_DEBUG_38__DBG_RBBMIF_DC_33_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_39 +#define RBBMIF_DEBUG_39__DBG_RBBMIF_DC_34__SHIFT 0x0 +#define RBBMIF_DEBUG_39__DBG_RBBMIF_DC_34_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_40 +#define RBBMIF_DEBUG_40__DBG_RBBMIF_DC_35__SHIFT 0x0 +#define RBBMIF_DEBUG_40__DBG_RBBMIF_DC_35_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_41 +#define RBBMIF_DEBUG_41__DBG_RBBMIF_DC_36__SHIFT 0x0 +#define RBBMIF_DEBUG_41__DBG_RBBMIF_DC_36_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_42 +#define RBBMIF_DEBUG_42__DBG_RBBMIF_DC_37__SHIFT 0x0 +#define RBBMIF_DEBUG_42__DBG_RBBMIF_DC_37_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_43 +#define RBBMIF_DEBUG_43__DBG_RBBMIF_DC_38__SHIFT 0x0 +#define RBBMIF_DEBUG_43__DBG_RBBMIF_DC_38_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_44 +#define RBBMIF_DEBUG_44__DBG_RBBMIF_DC_39__SHIFT 0x0 +#define RBBMIF_DEBUG_44__DBG_RBBMIF_DC_39_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_45 +#define RBBMIF_DEBUG_45__DBG_RBBMIF_DC_40__SHIFT 0x0 +#define RBBMIF_DEBUG_45__DBG_RBBMIF_DC_40_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_46 +#define RBBMIF_DEBUG_46__DBG_RBBMIF_DC_41__SHIFT 0x0 +#define RBBMIF_DEBUG_46__DBG_RBBMIF_DC_41_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_47 +#define RBBMIF_DEBUG_47__DBG_RBBMIF_DC_42__SHIFT 0x0 +#define RBBMIF_DEBUG_47__DBG_RBBMIF_DC_42_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_48 +#define RBBMIF_DEBUG_48__DBG_RBBMIF_DC_43__SHIFT 0x0 +#define RBBMIF_DEBUG_48__DBG_RBBMIF_DC_43_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_49 +#define RBBMIF_DEBUG_49__DBG_RBBMIF_DC_44__SHIFT 0x0 +#define RBBMIF_DEBUG_49__DBG_RBBMIF_DC_44_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_50 +#define RBBMIF_DEBUG_50__DBG_RBBMIF_DC_45__SHIFT 0x0 +#define RBBMIF_DEBUG_50__DBG_RBBMIF_DC_45_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_51 +#define RBBMIF_DEBUG_51__DBG_RBBMIF_DC_46__SHIFT 0x0 +#define RBBMIF_DEBUG_51__DBG_RBBMIF_DC_46_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_52 +#define RBBMIF_DEBUG_52__DBG_RBBMIF_DC_47__SHIFT 0x0 +#define RBBMIF_DEBUG_52__DBG_RBBMIF_DC_47_MASK 0xFFFFFFFFL + + +// addressBlock: ihc_ihcdebugind +//IHC_DEBUG_ID +#define IHC_DEBUG_ID__IHC_DEBUG_ID__SHIFT 0x0 +#define IHC_DEBUG_ID__IHC_DEBUG_ID_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_A +#define IHC_CLIENT_DEBUG_A__IHC_TEST_DEBUG_A__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_A__IHC_TEST_DEBUG_A_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_B +#define IHC_CLIENT_DEBUG_B__IHC_TEST_DEBUG_B__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_B__IHC_TEST_DEBUG_B_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_C +#define IHC_CLIENT_DEBUG_C__IHC_TEST_DEBUG_C__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_C__IHC_TEST_DEBUG_C_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_D +#define IHC_CLIENT_DEBUG_D__IHC_TEST_DEBUG_D__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_D__IHC_TEST_DEBUG_D_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_E +#define IHC_CLIENT_DEBUG_E__IHC_TEST_DEBUG_E__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_E__IHC_TEST_DEBUG_E_MASK 0xFFFFFFFFL + + +// addressBlock: dmu_misc_dmumiscdebugind +//DMU_MISC_DEBUG_ID +#define DMU_MISC_DEBUG_ID__DMU_MISC_DEBUG_ID__SHIFT 0x0 +#define DMU_MISC_DEBUG_ID__DMU_MISC_DEBUG_ID_MASK 0xFFFFFFFFL +//DMU_MISC_DEBUG_1 +#define DMU_MISC_DEBUG_1__DMU_MISC_DEBUG_1__SHIFT 0x0 +#define DMU_MISC_DEBUG_1__DMU_MISC_DEBUG_1_MASK 0xFFFFFFFFL +//DMU_ZSC_TEST_DEBUG1_DATA +#define DMU_ZSC_TEST_DEBUG1_DATA__DMU_ZSC_TEST_DEBUG1_DATA__SHIFT 0x0 +#define DMU_ZSC_TEST_DEBUG1_DATA__DMU_ZSC_TEST_DEBUG1_DATA_MASK 0xFFFFFFFFL +//DMU_ZSC_TEST_DEBUG2_DATA +#define DMU_ZSC_TEST_DEBUG2_DATA__DMU_ZSC_TEST_DEBUG2_DATA__SHIFT 0x0 +#define DMU_ZSC_TEST_DEBUG2_DATA__DMU_ZSC_TEST_DEBUG2_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dc_pg_dc_pgdebugind +//DCPG_DEBUG_ID +#define DCPG_DEBUG_ID__DCPG_DEBUG_ID__SHIFT 0x0 +#define DCPG_DEBUG_ID__DCPG_DEBUG_ID_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS0 +#define DCPG_CONTROL_DEBUG_BUS0__DCPG_CONTROL_DEBUG_BUS0__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS0__DCPG_CONTROL_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS1 +#define DCPG_CONTROL_DEBUG_BUS1__DCPG_CONTROL_DEBUG_BUS1__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS1__DCPG_CONTROL_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS2 +#define DCPG_CONTROL_DEBUG_BUS2__DCPG_CONTROL_DEBUG_BUS2__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS2__DCPG_CONTROL_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS3 +#define DCPG_CONTROL_DEBUG_BUS3__DCPG_CONTROL_DEBUG_BUS3__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS3__DCPG_CONTROL_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS16 +#define DCPG_CONTROL_DEBUG_BUS16__DCPG_CONTROL_DEBUG_BUS16__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS16__DCPG_CONTROL_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS17 +#define DCPG_CONTROL_DEBUG_BUS17__DCPG_CONTROL_DEBUG_BUS17__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS17__DCPG_CONTROL_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS18 +#define DCPG_CONTROL_DEBUG_BUS18__DCPG_CONTROL_DEBUG_BUS18__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS18__DCPG_CONTROL_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS19 +#define DCPG_CONTROL_DEBUG_BUS19__DCPG_CONTROL_DEBUG_BUS19__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS19__DCPG_CONTROL_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS22 +#define DCPG_CONTROL_DEBUG_BUS22__DCPG_CONTROL_DEBUG_BUS22__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS22__DCPG_CONTROL_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS23 +#define DCPG_CONTROL_DEBUG_BUS23__DCPG_CONTROL_DEBUG_BUS23__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS23__DCPG_CONTROL_DEBUG_BUS23_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS24 +#define DCPG_CONTROL_DEBUG_BUS24__DCPG_CONTROL_DEBUG_BUS24__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS24__DCPG_CONTROL_DEBUG_BUS24_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS25 +#define DCPG_CONTROL_DEBUG_BUS25__DCPG_CONTROL_DEBUG_BUS25__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS25__DCPG_CONTROL_DEBUG_BUS25_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS26 +#define DCPG_CONTROL_DEBUG_BUS26__DCPG_CONTROL_DEBUG_BUS26__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS26__DCPG_CONTROL_DEBUG_BUS26_MASK 0xFFFFFFFFL + + +// addressBlock: dp0_dpdebugind +//DP0_DP_DEBUG_ID +#define DP0_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP0_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_K +#define DP0_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP0_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_L +#define DP0_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP0_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_M +#define DP0_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP0_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_G +#define DP0_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP0_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_O +#define DP0_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP0_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_P +#define DP0_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP0_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_Q +#define DP0_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP0_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_R +#define DP0_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP0_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_S +#define DP0_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP0_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp0_dpfedebugind +//DP0_DP_FE_DEBUG_ID +#define DP0_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP0_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_T +#define DP0_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP0_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_U +#define DP0_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP0_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_V +#define DP0_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP0_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_W +#define DP0_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP0_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_X +#define DP0_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP0_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_Y +#define DP0_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP0_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_Z +#define DP0_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP0_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_1A +#define DP0_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP0_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_1B +#define DP0_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP0_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_I +#define DP0_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP0_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_J +#define DP0_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP0_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_N +#define DP0_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP0_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_H +#define DP0_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP0_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_A +#define DP0_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP0_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_B +#define DP0_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP0_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_C +#define DP0_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP0_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_D +#define DP0_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP0_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_E +#define DP0_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP0_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_F +#define DP0_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP0_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp0_dpfe_dprefclk_debugind +//DP0_DP_FE_DPREFCLK_DEBUG_ID +#define DP0_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig0_digdebugind +//DIG0_DIG_BE_CLKGEN_DEBUG0 +#define DIG0_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG0_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig0_digfedebugind +//DIG0_DIG_FE_DEBUG_ID +#define DIG0_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG0_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG0 +#define DIG0_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG1 +#define DIG0_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG2 +#define DIG0_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG3 +#define DIG0_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp1_dpdebugind +//DP1_DP_DEBUG_ID +#define DP1_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP1_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_K +#define DP1_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP1_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_L +#define DP1_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP1_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_M +#define DP1_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP1_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_G +#define DP1_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP1_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_O +#define DP1_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP1_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_P +#define DP1_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP1_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_Q +#define DP1_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP1_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_R +#define DP1_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP1_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_S +#define DP1_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP1_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp1_dpfedebugind +//DP1_DP_FE_DEBUG_ID +#define DP1_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP1_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_T +#define DP1_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP1_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_U +#define DP1_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP1_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_V +#define DP1_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP1_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_W +#define DP1_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP1_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_X +#define DP1_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP1_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_Y +#define DP1_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP1_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_Z +#define DP1_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP1_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_1A +#define DP1_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP1_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_1B +#define DP1_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP1_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_I +#define DP1_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP1_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_J +#define DP1_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP1_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_N +#define DP1_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP1_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_H +#define DP1_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP1_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_A +#define DP1_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP1_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_B +#define DP1_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP1_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_C +#define DP1_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP1_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_D +#define DP1_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP1_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_E +#define DP1_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP1_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_F +#define DP1_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP1_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp1_dpfe_dprefclk_debugind +//DP1_DP_FE_DPREFCLK_DEBUG_ID +#define DP1_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig1_digdebugind +//DIG1_DIG_BE_CLKGEN_DEBUG0 +#define DIG1_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG1_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig1_digfedebugind +//DIG1_DIG_FE_DEBUG_ID +#define DIG1_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG1_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG0 +#define DIG1_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG1 +#define DIG1_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG2 +#define DIG1_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG3 +#define DIG1_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp2_dpdebugind +//DP2_DP_DEBUG_ID +#define DP2_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP2_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_K +#define DP2_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP2_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_L +#define DP2_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP2_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_M +#define DP2_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP2_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_G +#define DP2_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP2_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_O +#define DP2_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP2_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_P +#define DP2_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP2_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_Q +#define DP2_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP2_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_R +#define DP2_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP2_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_S +#define DP2_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP2_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp2_dpfedebugind +//DP2_DP_FE_DEBUG_ID +#define DP2_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP2_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_T +#define DP2_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP2_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_U +#define DP2_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP2_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_V +#define DP2_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP2_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_W +#define DP2_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP2_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_X +#define DP2_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP2_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_Y +#define DP2_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP2_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_Z +#define DP2_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP2_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_1A +#define DP2_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP2_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_1B +#define DP2_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP2_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_I +#define DP2_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP2_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_J +#define DP2_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP2_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_N +#define DP2_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP2_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_H +#define DP2_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP2_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_A +#define DP2_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP2_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_B +#define DP2_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP2_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_C +#define DP2_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP2_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_D +#define DP2_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP2_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_E +#define DP2_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP2_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_F +#define DP2_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP2_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp2_dpfe_dprefclk_debugind +//DP2_DP_FE_DPREFCLK_DEBUG_ID +#define DP2_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig2_digdebugind +//DIG2_DIG_BE_CLKGEN_DEBUG0 +#define DIG2_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG2_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig2_digfedebugind +//DIG2_DIG_FE_DEBUG_ID +#define DIG2_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG2_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG0 +#define DIG2_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG1 +#define DIG2_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG2 +#define DIG2_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG3 +#define DIG2_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp3_dpdebugind +//DP3_DP_DEBUG_ID +#define DP3_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP3_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_K +#define DP3_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP3_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_L +#define DP3_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP3_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_M +#define DP3_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP3_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_G +#define DP3_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP3_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_O +#define DP3_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP3_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_P +#define DP3_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP3_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_Q +#define DP3_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP3_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_R +#define DP3_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP3_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_S +#define DP3_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP3_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp3_dpfedebugind +//DP3_DP_FE_DEBUG_ID +#define DP3_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP3_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_T +#define DP3_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP3_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_U +#define DP3_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP3_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_V +#define DP3_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP3_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_W +#define DP3_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP3_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_X +#define DP3_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP3_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_Y +#define DP3_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP3_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_Z +#define DP3_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP3_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_1A +#define DP3_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP3_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_1B +#define DP3_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP3_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_I +#define DP3_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP3_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_J +#define DP3_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP3_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_N +#define DP3_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP3_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_H +#define DP3_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP3_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_A +#define DP3_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP3_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_B +#define DP3_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP3_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_C +#define DP3_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP3_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_D +#define DP3_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP3_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_E +#define DP3_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP3_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_F +#define DP3_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP3_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp3_dpfe_dprefclk_debugind +//DP3_DP_FE_DPREFCLK_DEBUG_ID +#define DP3_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig3_digdebugind +//DIG3_DIG_BE_CLKGEN_DEBUG0 +#define DIG3_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG3_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig3_digfedebugind +//DIG3_DIG_FE_DEBUG_ID +#define DIG3_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG3_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG0 +#define DIG3_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG1 +#define DIG3_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG2 +#define DIG3_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG3 +#define DIG3_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp4_dpdebugind +//DP4_DP_DEBUG_ID +#define DP4_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP4_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_K +#define DP4_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP4_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_L +#define DP4_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP4_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_M +#define DP4_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP4_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_G +#define DP4_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP4_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_O +#define DP4_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP4_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_P +#define DP4_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP4_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_Q +#define DP4_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP4_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_R +#define DP4_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP4_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_S +#define DP4_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP4_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp4_dpfedebugind +//DP4_DP_FE_DEBUG_ID +#define DP4_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP4_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_T +#define DP4_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP4_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_U +#define DP4_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP4_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_V +#define DP4_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP4_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_W +#define DP4_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP4_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_X +#define DP4_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP4_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_Y +#define DP4_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP4_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_Z +#define DP4_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP4_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_1A +#define DP4_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP4_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_1B +#define DP4_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP4_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_I +#define DP4_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP4_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_J +#define DP4_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP4_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_N +#define DP4_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP4_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_H +#define DP4_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP4_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_A +#define DP4_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP4_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_B +#define DP4_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP4_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_C +#define DP4_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP4_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_D +#define DP4_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP4_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_E +#define DP4_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP4_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_F +#define DP4_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP4_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp4_dpfe_dprefclk_debugind +//DP4_DP_FE_DPREFCLK_DEBUG_ID +#define DP4_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig4_digdebugind +//DIG4_DIG_BE_CLKGEN_DEBUG0 +#define DIG4_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG4_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig4_digfedebugind +//DIG4_DIG_FE_DEBUG_ID +#define DIG4_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG4_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG0 +#define DIG4_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG1 +#define DIG4_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG2 +#define DIG4_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG3 +#define DIG4_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dio_misc_dio_miscdebugind +//I2C_DEBUG_BUS +#define I2C_DEBUG_BUS__I2C_DEBUG_BUS__SHIFT 0x12 +#define I2C_DEBUG_BUS__I2C_DEBUG_BUS_MASK 0xFFFC0000L +//DIO_RBBMIF_DEBUG_0 +#define DIO_RBBMIF_DEBUG_0__DIO_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_0__DIO_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIO_RBBMIF_DEBUG_1 +#define DIO_RBBMIF_DEBUG_1__DIO_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_1__DIO_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIO_RBBMIF_DEBUG_2 +#define DIO_RBBMIF_DEBUG_2__DIO_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_2__DIO_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIO_RBBMIF_DEBUG_3 +#define DIO_RBBMIF_DEBUG_3__DIO_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_3__DIO_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_0 +#define DIGA_RBBMIF_DEBUG_0__DIGA_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_0__DIGA_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_1 +#define DIGA_RBBMIF_DEBUG_1__DIGA_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_1__DIGA_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_2 +#define DIGA_RBBMIF_DEBUG_2__DIGA_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_2__DIGA_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_3 +#define DIGA_RBBMIF_DEBUG_3__DIGA_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_3__DIGA_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_0 +#define DIGB_RBBMIF_DEBUG_0__DIGB_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_0__DIGB_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_1 +#define DIGB_RBBMIF_DEBUG_1__DIGB_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_1__DIGB_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_2 +#define DIGB_RBBMIF_DEBUG_2__DIGB_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_2__DIGB_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_3 +#define DIGB_RBBMIF_DEBUG_3__DIGB_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_3__DIGB_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_0 +#define DIGC_RBBMIF_DEBUG_0__DIGC_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_0__DIGC_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_1 +#define DIGC_RBBMIF_DEBUG_1__DIGC_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_1__DIGC_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_2 +#define DIGC_RBBMIF_DEBUG_2__DIGC_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_2__DIGC_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_3 +#define DIGC_RBBMIF_DEBUG_3__DIGC_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_3__DIGC_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_0 +#define DIGD_RBBMIF_DEBUG_0__DIGD_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_0__DIGD_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_1 +#define DIGD_RBBMIF_DEBUG_1__DIGD_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_1__DIGD_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_2 +#define DIGD_RBBMIF_DEBUG_2__DIGD_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_2__DIGD_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_3 +#define DIGD_RBBMIF_DEBUG_3__DIGD_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_3__DIGD_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_0 +#define DIGE_RBBMIF_DEBUG_0__DIGE_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_0__DIGE_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_1 +#define DIGE_RBBMIF_DEBUG_1__DIGE_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_1__DIGE_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_2 +#define DIGE_RBBMIF_DEBUG_2__DIGE_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_2__DIGE_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_3 +#define DIGE_RBBMIF_DEBUG_3__DIGE_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_3__DIGE_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGA_DME_DEBUG +#define DIGA_DME_DEBUG__DIGA_DME_DEBUG__SHIFT 0x0 +#define DIGA_DME_DEBUG__DIGA_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGB_DME_DEBUG +#define DIGB_DME_DEBUG__DIGB_DME_DEBUG__SHIFT 0x0 +#define DIGB_DME_DEBUG__DIGB_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGC_DME_DEBUG +#define DIGC_DME_DEBUG__DIGC_DME_DEBUG__SHIFT 0x0 +#define DIGC_DME_DEBUG__DIGC_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGD_DME_DEBUG +#define DIGD_DME_DEBUG__DIGD_DME_DEBUG__SHIFT 0x0 +#define DIGD_DME_DEBUG__DIGD_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGE_DME_DEBUG +#define DIGE_DME_DEBUG__DIGE_DME_DEBUG__SHIFT 0x0 +#define DIGE_DME_DEBUG__DIGE_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGA_RESYNC_FIFO_DEBUG +#define DIGA_RESYNC_FIFO_DEBUG__DIGA_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGA_RESYNC_FIFO_DEBUG__DIGA_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGB_RESYNC_FIFO_DEBUG +#define DIGB_RESYNC_FIFO_DEBUG__DIGB_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGB_RESYNC_FIFO_DEBUG__DIGB_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGC_RESYNC_FIFO_DEBUG +#define DIGC_RESYNC_FIFO_DEBUG__DIGC_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGC_RESYNC_FIFO_DEBUG__DIGC_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGD_RESYNC_FIFO_DEBUG +#define DIGD_RESYNC_FIFO_DEBUG__DIGD_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGD_RESYNC_FIFO_DEBUG__DIGD_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGE_RESYNC_FIFO_DEBUG +#define DIGE_RESYNC_FIFO_DEBUG__DIGE_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGE_RESYNC_FIFO_DEBUG__DIGE_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL + + +// addressBlock: apg_apg_socclk_debugind +//APG_SOCCLK_DEBUG_ID +#define APG_SOCCLK_DEBUG_ID__APG_SOCCLK_DEBUG_ID__SHIFT 0x0 +#define APG_SOCCLK_DEBUG_ID__APG_SOCCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//APG_SOCCLK_DEBUG0 +#define APG_SOCCLK_DEBUG0__APG_SOCCLK_DEBUG0__SHIFT 0x0 +#define APG_SOCCLK_DEBUG0__APG_SOCCLK_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: apg_apg_encclk_debugind +//APG_ENCCLK_DEBUG_ID +#define APG_ENCCLK_DEBUG_ID__APG_ENCCLK_DEBUG_ID__SHIFT 0x0 +#define APG_ENCCLK_DEBUG_ID__APG_ENCCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG0 +#define APG_ENCCLK_DEBUG0__APG_ENCCLK_DEBUG0__SHIFT 0x0 +#define APG_ENCCLK_DEBUG0__APG_ENCCLK_DEBUG0_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG1 +#define APG_ENCCLK_DEBUG1__APG_ENCCLK_DEBUG1__SHIFT 0x0 +#define APG_ENCCLK_DEBUG1__APG_ENCCLK_DEBUG1_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG2 +#define APG_ENCCLK_DEBUG2__APG_ENCCLK_DEBUG2__SHIFT 0x0 +#define APG_ENCCLK_DEBUG2__APG_ENCCLK_DEBUG2_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG3 +#define APG_ENCCLK_DEBUG3__APG_ENCCLK_DEBUG3__SHIFT 0x0 +#define APG_ENCCLK_DEBUG3__APG_ENCCLK_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dcoh_top_dcoh_topdebugind +//DCOH_TOP_DEBUG_ID +#define DCOH_TOP_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define DCOH_TOP_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux0_auxdebugdispclkind +//DP_AUX0_AUX_DEBUG_DISPCLK_ID +#define DP_AUX0_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX0_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_H +#define DP_AUX0_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_I +#define DP_AUX0_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux0_auxdebugrefclkind +//DP_AUX0_AUX_DEBUG_REFCLK_ID +#define DP_AUX0_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX0_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_A +#define DP_AUX0_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_B +#define DP_AUX0_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_C +#define DP_AUX0_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_D +#define DP_AUX0_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_E +#define DP_AUX0_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_F +#define DP_AUX0_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_G +#define DP_AUX0_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_J +#define DP_AUX0_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux1_auxdebugdispclkind +//DP_AUX1_AUX_DEBUG_DISPCLK_ID +#define DP_AUX1_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX1_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_H +#define DP_AUX1_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_I +#define DP_AUX1_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux1_auxdebugrefclkind +//DP_AUX1_AUX_DEBUG_REFCLK_ID +#define DP_AUX1_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX1_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_A +#define DP_AUX1_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_B +#define DP_AUX1_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_C +#define DP_AUX1_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_D +#define DP_AUX1_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_E +#define DP_AUX1_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_F +#define DP_AUX1_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_G +#define DP_AUX1_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_J +#define DP_AUX1_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux2_auxdebugdispclkind +//DP_AUX2_AUX_DEBUG_DISPCLK_ID +#define DP_AUX2_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX2_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_H +#define DP_AUX2_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_I +#define DP_AUX2_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux2_auxdebugrefclkind +//DP_AUX2_AUX_DEBUG_REFCLK_ID +#define DP_AUX2_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX2_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_A +#define DP_AUX2_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_B +#define DP_AUX2_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_C +#define DP_AUX2_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_D +#define DP_AUX2_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_E +#define DP_AUX2_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_F +#define DP_AUX2_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_G +#define DP_AUX2_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_J +#define DP_AUX2_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux3_auxdebugdispclkind +//DP_AUX3_AUX_DEBUG_DISPCLK_ID +#define DP_AUX3_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX3_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_H +#define DP_AUX3_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_I +#define DP_AUX3_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux3_auxdebugrefclkind +//DP_AUX3_AUX_DEBUG_REFCLK_ID +#define DP_AUX3_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX3_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_A +#define DP_AUX3_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_B +#define DP_AUX3_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_C +#define DP_AUX3_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_D +#define DP_AUX3_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_E +#define DP_AUX3_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_F +#define DP_AUX3_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_G +#define DP_AUX3_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_J +#define DP_AUX3_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux4_auxdebugdispclkind +//DP_AUX4_AUX_DEBUG_DISPCLK_ID +#define DP_AUX4_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX4_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_H +#define DP_AUX4_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_I +#define DP_AUX4_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux4_auxdebugrefclkind +//DP_AUX4_AUX_DEBUG_REFCLK_ID +#define DP_AUX4_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX4_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_A +#define DP_AUX4_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_B +#define DP_AUX4_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_C +#define DP_AUX4_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_D +#define DP_AUX4_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_E +#define DP_AUX4_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_F +#define DP_AUX4_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_G +#define DP_AUX4_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_J +#define DP_AUX4_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: hpd0_hpddebugind +//HPD0_HPD_DEBUG_ID +#define HPD0_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD0_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD0_HPD_DEBUG_0 +#define HPD0_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD0_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd1_hpddebugind +//HPD1_HPD_DEBUG_ID +#define HPD1_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD1_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD1_HPD_DEBUG_0 +#define HPD1_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD1_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd2_hpddebugind +//HPD2_HPD_DEBUG_ID +#define HPD2_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD2_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD2_HPD_DEBUG_0 +#define HPD2_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD2_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd3_hpddebugind +//HPD3_HPD_DEBUG_ID +#define HPD3_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD3_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD3_HPD_DEBUG_0 +#define HPD3_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD3_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd4_hpddebugind +//HPD4_HPD_DEBUG_ID +#define HPD4_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD4_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD4_HPD_DEBUG_0 +#define HPD4_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD4_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpo_top_hpo_topdebugind +//HPO_TOP_DEBUG_ID +#define HPO_TOP_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPO_TOP_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_link_enc0_linkencdebugind +//HDMI_LINK_ENC_DEBUG_ID +#define HDMI_LINK_ENC_DEBUG_ID__HDMI_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define HDMI_LINK_ENC_DEBUG_ID__HDMI_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_frl_enc0_frldebugind +//HDMI_FRL_ENC_DEBUG_ID +#define HDMI_FRL_ENC_DEBUG_ID__HDMI_FRL_ENC_DEBUG_ID__SHIFT 0x0 +#define HDMI_FRL_ENC_DEBUG_ID__HDMI_FRL_ENC_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_hdmistreamclk_debugind +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_dispclk_debugind +//HDMI_STREAM_ENC_DISPCLK_DEBUG_ID +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_ID__HDMI_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_ID__HDMI_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_0__HDMI_STREAM_ENC_DISPCLK_DEBUG_0__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_0__HDMI_STREAM_ENC_DISPCLK_DEBUG_0_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_1 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_1__HDMI_STREAM_ENC_DISPCLK_DEBUG_1__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_1__HDMI_STREAM_ENC_DISPCLK_DEBUG_1_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_2 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_2__HDMI_STREAM_ENC_DISPCLK_DEBUG_2__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_2__HDMI_STREAM_ENC_DISPCLK_DEBUG_2_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_3 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_3__HDMI_STREAM_ENC_DISPCLK_DEBUG_3__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_3__HDMI_STREAM_ENC_DISPCLK_DEBUG_3_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_4 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_4__HDMI_STREAM_ENC_DISPCLK_DEBUG_4__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_4__HDMI_STREAM_ENC_DISPCLK_DEBUG_4_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc0_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc1_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc2_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc3_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc0_dplinkencdebugind +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym320_dpdphysym32debugind +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc1_dplinkencdebugind +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym321_dpdphysym32debugind +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc2_dplinkencdebugind +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym322_dpdphysym32debugind +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc3_dplinkencdebugind +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym323_dpdphysym32debugind +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_STREAM_DEBUG +#define AZF0STREAM0_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_STREAM_DEBUG +#define AZF0STREAM1_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_STREAM_DEBUG +#define AZF0STREAM2_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_STREAM_DEBUG +#define AZF0STREAM3_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_STREAM_DEBUG +#define AZF0STREAM4_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_STREAM_DEBUG +#define AZF0STREAM5_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_STREAM_DEBUG +#define AZF0STREAM6_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_STREAM_DEBUG +#define AZF0STREAM7_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_STREAM_DEBUG +#define AZF0STREAM8_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_STREAM_DEBUG +#define AZF0STREAM9_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_STREAM_DEBUG +#define AZF0STREAM10_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_STREAM_DEBUG +#define AZF0STREAM11_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_STREAM_DEBUG +#define AZF0STREAM12_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_STREAM_DEBUG +#define AZF0STREAM13_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_STREAM_DEBUG +#define AZF0STREAM14_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_STREAM_DEBUG +#define AZF0STREAM15_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: dscc_dsccdebugind0 +//DSCC_DEBUG_ID +#define DSCC_DEBUG_ID__DSCC_DEBUG_ID__SHIFT 0x0 +#define DSCC_DEBUG_ID__DSCC_DEBUG_ID_MASK 0xFFFFFFFFL +//DSCC_DEBUG_0 +#define DSCC_DEBUG_0__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC_DEBUG_0__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC_DEBUG_1 +#define DSCC_DEBUG_1__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC_DEBUG_1__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC_DEBUG_2 +#define DSCC_DEBUG_2__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC_DEBUG_2__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC_DEBUG_3 +#define DSCC_DEBUG_3__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC_DEBUG_3__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC_DEBUG_4 +#define DSCC_DEBUG_4__DSCC_DEBUG_4__SHIFT 0x0 +#define DSCC_DEBUG_4__DSCC_DEBUG_4_MASK 0xFFFFFFFFL +//DSCC_DEBUG_5 +#define DSCC_DEBUG_5__DSCC_DEBUG_5__SHIFT 0x0 +#define DSCC_DEBUG_5__DSCC_DEBUG_5_MASK 0xFFFFFFFFL +//DSCC_DEBUG_6 +#define DSCC_DEBUG_6__DSCC_DEBUG_6__SHIFT 0x0 +#define DSCC_DEBUG_6__DSCC_DEBUG_6_MASK 0xFFFFFFFFL +//DSCC_DEBUG_7 +#define DSCC_DEBUG_7__DSCC_DEBUG_7__SHIFT 0x0 +#define DSCC_DEBUG_7__DSCC_DEBUG_7_MASK 0xFFFFFFFFL +//DSCC_DEBUG_8 +#define DSCC_DEBUG_8__DSCC_DEBUG_8__SHIFT 0x0 +#define DSCC_DEBUG_8__DSCC_DEBUG_8_MASK 0xFFFFFFFFL +//DSCC_DEBUG_9 +#define DSCC_DEBUG_9__DSCC_DEBUG_9__SHIFT 0x0 +#define DSCC_DEBUG_9__DSCC_DEBUG_9_MASK 0xFFFFFFFFL +//DSCC_DEBUG_10 +#define DSCC_DEBUG_10__DSCC_DEBUG_10__SHIFT 0x0 +#define DSCC_DEBUG_10__DSCC_DEBUG_10_MASK 0xFFFFFFFFL +//DSCC_DEBUG_11 +#define DSCC_DEBUG_11__DSCC_DEBUG_11__SHIFT 0x0 +#define DSCC_DEBUG_11__DSCC_DEBUG_11_MASK 0xFFFFFFFFL +//DSCC_DEBUG_12 +#define DSCC_DEBUG_12__DSCC_DEBUG_12__SHIFT 0x0 +#define DSCC_DEBUG_12__DSCC_DEBUG_12_MASK 0xFFFFFFFFL +//DSCC_DEBUG_13 +#define DSCC_DEBUG_13__DSCC_DEBUG_13__SHIFT 0x0 +#define DSCC_DEBUG_13__DSCC_DEBUG_13_MASK 0xFFFFFFFFL +//DSCC_DEBUG_14 +#define DSCC_DEBUG_14__DSCC_DEBUG_14__SHIFT 0x0 +#define DSCC_DEBUG_14__DSCC_DEBUG_14_MASK 0xFFFFFFFFL +//DSCC_DEBUG_15 +#define DSCC_DEBUG_15__DSCC_DEBUG_15__SHIFT 0x0 +#define DSCC_DEBUG_15__DSCC_DEBUG_15_MASK 0xFFFFFFFFL +//DSCC_DEBUG_16 +#define DSCC_DEBUG_16__DSCC_DEBUG_16__SHIFT 0x0 +#define DSCC_DEBUG_16__DSCC_DEBUG_16_MASK 0xFFFFFFFFL +//DSCC_DEBUG_17 +#define DSCC_DEBUG_17__DSCC_DEBUG_17__SHIFT 0x0 +#define DSCC_DEBUG_17__DSCC_DEBUG_17_MASK 0xFFFFFFFFL +//DSCC_DEBUG_18 +#define DSCC_DEBUG_18__DSCC_DEBUG_18__SHIFT 0x0 +#define DSCC_DEBUG_18__DSCC_DEBUG_18_MASK 0xFFFFFFFFL +//DSCC_DEBUG_19 +#define DSCC_DEBUG_19__DSCC_DEBUG_19__SHIFT 0x0 +#define DSCC_DEBUG_19__DSCC_DEBUG_19_MASK 0xFFFFFFFFL +//DSCC_DEBUG_20 +#define DSCC_DEBUG_20__DSCC_DEBUG_20__SHIFT 0x0 +#define DSCC_DEBUG_20__DSCC_DEBUG_20_MASK 0xFFFFFFFFL +//DSCC_DEBUG_21 +#define DSCC_DEBUG_21__DSCC_DEBUG_21__SHIFT 0x0 +#define DSCC_DEBUG_21__DSCC_DEBUG_21_MASK 0xFFFFFFFFL +//DSCC_DEBUG_22 +#define DSCC_DEBUG_22__DSCC_DEBUG_22__SHIFT 0x0 +#define DSCC_DEBUG_22__DSCC_DEBUG_22_MASK 0xFFFFFFFFL +//DSCC_DEBUG_23 +#define DSCC_DEBUG_23__DSCC_DEBUG_23__SHIFT 0x0 +#define DSCC_DEBUG_23__DSCC_DEBUG_23_MASK 0xFFFFFFFFL +//DSCC_DEBUG_24 +#define DSCC_DEBUG_24__DSCC_DEBUG_24__SHIFT 0x0 +#define DSCC_DEBUG_24__DSCC_DEBUG_24_MASK 0xFFFFFFFFL +//DSCC_DEBUG_25 +#define DSCC_DEBUG_25__DSCC_DEBUG_25__SHIFT 0x0 +#define DSCC_DEBUG_25__DSCC_DEBUG_25_MASK 0xFFFFFFFFL +//DSCC_DEBUG_26 +#define DSCC_DEBUG_26__DSCC_DEBUG_26__SHIFT 0x0 +#define DSCC_DEBUG_26__DSCC_DEBUG_26_MASK 0xFFFFFFFFL +//DSCC_DEBUG_27 +#define DSCC_DEBUG_27__DSCC_DEBUG_27__SHIFT 0x0 +#define DSCC_DEBUG_27__DSCC_DEBUG_27_MASK 0xFFFFFFFFL +//DSCC_DEBUG_28 +#define DSCC_DEBUG_28__DSCC_DEBUG_28__SHIFT 0x0 +#define DSCC_DEBUG_28__DSCC_DEBUG_28_MASK 0xFFFFFFFFL + + +// addressBlock: dscc_dscc_dispclk_debugind0 +//DSCC_DISPCLK_DEBUG_ID +#define DSCC_DISPCLK_DEBUG_ID__DSCC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_ID__DSCC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_0 +#define DSCC_DISPCLK_DEBUG_0__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_0__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_1 +#define DSCC_DISPCLK_DEBUG_1__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_1__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_2 +#define DSCC_DISPCLK_DEBUG_2__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_2__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_3 +#define DSCC_DISPCLK_DEBUG_3__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_3__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_4 +#define DSCC_DISPCLK_DEBUG_4__DSCC_INITIAL_XMIT_DELAY_REACHED__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_4__DSCC_LAST_SLICE_PIXEL_COUNT_AT_INITIAL_XMIT_DELAY__SHIFT 0x4 +#define DSCC_DISPCLK_DEBUG_4__DSCC_OUTPUT_BUFFER_PIXEL_THRESHOLD_AT_INITIAL_XMIT_DELAY__SHIFT 0x10 +#define DSCC_DISPCLK_DEBUG_4__DSCC_INITIAL_XMIT_DELAY_REACHED_MASK 0x00000001L +#define DSCC_DISPCLK_DEBUG_4__DSCC_LAST_SLICE_PIXEL_COUNT_AT_INITIAL_XMIT_DELAY_MASK 0x00007FF0L +#define DSCC_DISPCLK_DEBUG_4__DSCC_OUTPUT_BUFFER_PIXEL_THRESHOLD_AT_INITIAL_XMIT_DELAY_MASK 0xFFFF0000L +//DSCC_DISPCLK_DEBUG_5 +#define DSCC_DISPCLK_DEBUG_5__DSCC_TOTAL_PIXEL_COUNT_IN_OUTPUT_BUFFER__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_5__DSCC_TOTAL_PIXEL_COUNT_IN_OUTPUT_BUFFER_MASK 0x0000FFFFL +//DSCC_DISPCLK_DEBUG_6 +#define DSCC_DISPCLK_DEBUG_6__DSCC_DISPCLK_DEBUG_6__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_6__DSCC_DISPCLK_DEBUG_6_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_7 +#define DSCC_DISPCLK_DEBUG_7__DSCC_DISPCLK_DEBUG_7__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_7__DSCC_DISPCLK_DEBUG_7_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_8 +#define DSCC_DISPCLK_DEBUG_8__DSCC_DISPCLK_DEBUG_8__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_8__DSCC_DISPCLK_DEBUG_8_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_9 +#define DSCC_DISPCLK_DEBUG_9__DSCC_DISPCLK_DEBUG_9__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_9__DSCC_DISPCLK_DEBUG_9_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_10 +#define DSCC_DISPCLK_DEBUG_10__DSCC_DISPCLK_DEBUG_10__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_10__DSCC_DISPCLK_DEBUG_10_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_11 +#define DSCC_DISPCLK_DEBUG_11__DSCC_DISPCLK_DEBUG_11__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_11__DSCC_DISPCLK_DEBUG_11_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_12 +#define DSCC_DISPCLK_DEBUG_12__DSCC_DISPCLK_DEBUG_12__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_12__DSCC_DISPCLK_DEBUG_12_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_13 +#define DSCC_DISPCLK_DEBUG_13__DSCC_DISPCLK_DEBUG_13__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_13__DSCC_DISPCLK_DEBUG_13_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_14 +#define DSCC_DISPCLK_DEBUG_14__DSCC_DISPCLK_DEBUG_14__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_14__DSCC_DISPCLK_DEBUG_14_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_15 +#define DSCC_DISPCLK_DEBUG_15__DSCC_DISPCLK_DEBUG_15__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_15__DSCC_DISPCLK_DEBUG_15_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_16 +#define DSCC_DISPCLK_DEBUG_16__DSCC_DISPCLK_DEBUG_16__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_16__DSCC_DISPCLK_DEBUG_16_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_17 +#define DSCC_DISPCLK_DEBUG_17__DSCC_DISPCLK_DEBUG_17__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_17__DSCC_DISPCLK_DEBUG_17_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_18 +#define DSCC_DISPCLK_DEBUG_18__DSCC_DISPCLK_DEBUG_18__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_18__DSCC_DISPCLK_DEBUG_18_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_19 +#define DSCC_DISPCLK_DEBUG_19__DSCC_DISPCLK_DEBUG_19__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_19__DSCC_DISPCLK_DEBUG_19_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_20 +#define DSCC_DISPCLK_DEBUG_20__DSCC_DISPCLK_DEBUG_20__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_20__DSCC_DISPCLK_DEBUG_20_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_21 +#define DSCC_DISPCLK_DEBUG_21__DSCC_DISPCLK_DEBUG_21__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_21__DSCC_DISPCLK_DEBUG_21_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_22 +#define DSCC_DISPCLK_DEBUG_22__DSCC_DISPCLK_DEBUG_22__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_22__DSCC_DISPCLK_DEBUG_22_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_23 +#define DSCC_DISPCLK_DEBUG_23__DSCC_DISPCLK_DEBUG_23__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_23__DSCC_DISPCLK_DEBUG_23_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_24 +#define DSCC_DISPCLK_DEBUG_24__DSCC_DISPCLK_DEBUG_24__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_24__DSCC_DISPCLK_DEBUG_24_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_25 +#define DSCC_DISPCLK_DEBUG_25__DSCC_DISPCLK_DEBUG_25__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_25__DSCC_DISPCLK_DEBUG_25_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_26 +#define DSCC_DISPCLK_DEBUG_26__DSCC_DISPCLK_DEBUG_26__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_26__DSCC_DISPCLK_DEBUG_26_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_27 +#define DSCC_DISPCLK_DEBUG_27__DSCC_DISPCLK_DEBUG_27__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_27__DSCC_DISPCLK_DEBUG_27_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_28 +#define DSCC_DISPCLK_DEBUG_28__DSCC_DISPCLK_DEBUG_28__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_28__DSCC_DISPCLK_DEBUG_28_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_29 +#define DSCC_DISPCLK_DEBUG_29__DSCC_DISPCLK_DEBUG_29__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_29__DSCC_DISPCLK_DEBUG_29_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_30 +#define DSCC_DISPCLK_DEBUG_30__DSCC_DISPCLK_DEBUG_30__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_30__DSCC_DISPCLK_DEBUG_30_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_31 +#define DSCC_DISPCLK_DEBUG_31__DSCC_DISPCLK_DEBUG_31__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_31__DSCC_DISPCLK_DEBUG_31_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_32 +#define DSCC_DISPCLK_DEBUG_32__DSCC_DISPCLK_DEBUG_32__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_32__DSCC_DISPCLK_DEBUG_32_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_33 +#define DSCC_DISPCLK_DEBUG_33__DSCC_DISPCLK_DEBUG_33__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_33__DSCC_DISPCLK_DEBUG_33_MASK 0xFFFFFFFFL + + +// addressBlock: dsccif_dsccifdebugind +//DSCCIF_DEBUG_ID +#define DSCCIF_DEBUG_ID__DSCCIF_DEBUG_ID__SHIFT 0x0 +#define DSCCIF_DEBUG_ID__DSCCIF_DEBUG_ID_MASK 0xFFFFFFFFL +//DSCCIF_DEBUG_0 +#define DSCCIF_DEBUG_0__DSCCIF_DEBUG_0__SHIFT 0x0 +#define DSCCIF_DEBUG_0__DSCCIF_DEBUG_0_MASK 0xFFFFFFFFL +//DSCCIF_DEBUG_1 +#define DSCCIF_DEBUG_1__DSCCIF_DEBUG_1__SHIFT 0x0 +#define DSCCIF_DEBUG_1__DSCCIF_DEBUG_1_MASK 0xFFFFFFFFL + + +// addressBlock: dsc_top_dsc_topdebugind +//DSC_TOP_DEBUG_ID +#define DSC_TOP_DEBUG_ID__DSC_TOP_DEBUG_ID__SHIFT 0x0 +#define DSC_TOP_DEBUG_ID__DSC_TOP_DEBUG_ID_MASK 0xFFFFFFFFL +//DSC_TOP_DEBUG_0 +#define DSC_TOP_DEBUG_0__DSC_TOP_DEBUG_0__SHIFT 0x0 +#define DSC_TOP_DEBUG_0__DSC_TOP_DEBUG_0_MASK 0xFFFFFFFFL +//DSC_TOP_DEBUG_1 +#define DSC_TOP_DEBUG_1__DSC_TOP_DEBUG_1__SHIFT 0x0 +#define DSC_TOP_DEBUG_1__DSC_TOP_DEBUG_1_MASK 0xFFFFFFFFL +//DSC_TOP_DEBUG_2 +#define DSC_TOP_DEBUG_2__DSC_TOP_DEBUG_2__SHIFT 0x0 +#define DSC_TOP_DEBUG_2__DSC_TOP_DEBUG_2_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port0_dpiaportdebugind +//DPIA_PORT0_DPIA_PORT_DEBUG_ID +#define DPIA_PORT0_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT0_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT0_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT0_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT0_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port1_dpiaportdebugind +//DPIA_PORT1_DPIA_PORT_DEBUG_ID +#define DPIA_PORT1_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT1_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT1_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT1_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT1_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port2_dpiaportdebugind +//DPIA_PORT2_DPIA_PORT_DEBUG_ID +#define DPIA_PORT2_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT2_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT2_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT2_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT2_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port3_dpiaportdebugind +//DPIA_PORT3_DPIA_PORT_DEBUG_ID +#define DPIA_PORT3_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT3_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT3_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT3_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT3_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port4_dpiaportdebugind +//DPIA_PORT4_DPIA_PORT_DEBUG_ID +#define DPIA_PORT4_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT4_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT4_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT4_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT4_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port5_dpiaportdebugind +//DPIA_PORT5_DPIA_PORT_DEBUG_ID +#define DPIA_PORT5_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT5_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT5_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT5_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT5_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml0_dpiaportmldebugind +//DPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml1_dpiaportmldebugind +//DPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml2_dpiaportmldebugind +//DPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml3_dpiaportmldebugind +//DPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml4_dpiaportmldebugind +//DPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml5_dpiaportmldebugind +//DPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux0_dpiaportauxdebugind +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux1_dpiaportauxdebugind +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux2_dpiaportauxdebugind +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux3_dpiaportauxdebugind +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux4_dpiaportauxdebugind +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux5_dpiaportauxdebugind +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_mu0_dpia_mu_debugind +//DPIA_MU_DEBUG_ID +#define DPIA_MU_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define DPIA_MU_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DSCCLK3_DTO_PARAM +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT 0x0 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT 0x10 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK 0x00FF0000L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_GATE_DISABLE_CNTL4 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_ROOT_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_ROOT_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_ROOT_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_ROOT_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_ROOT_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_ROOT_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_ROOT_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_ROOT_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE_MASK 0x00800000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_GATE_DISABLE_MASK 0x10000000L +//DPSTREAMCLK_CNTL +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT 0x3 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT 0x4 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT 0x7 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT 0x8 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT 0xb +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT 0xc +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT 0xf +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK 0x00000008L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK 0x00000070L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK 0x00000080L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK 0x00000700L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK 0x00000800L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK 0x00007000L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK 0x00008000L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_PERFMON_CNTL2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT 0x9 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK 0x00000200L +//DPIASYMCLK_CNTL +#define DPIASYMCLK_CNTL__DPIASYMCLK0_SRC_SEL__SHIFT 0x0 +#define DPIASYMCLK_CNTL__DPIASYMCLK0_EN__SHIFT 0x3 +#define DPIASYMCLK_CNTL__DPIASYMCLK1_SRC_SEL__SHIFT 0x4 +#define DPIASYMCLK_CNTL__DPIASYMCLK1_EN__SHIFT 0x7 +#define DPIASYMCLK_CNTL__DPIASYMCLK2_SRC_SEL__SHIFT 0x8 +#define DPIASYMCLK_CNTL__DPIASYMCLK2_EN__SHIFT 0xb +#define DPIASYMCLK_CNTL__DPIASYMCLK3_SRC_SEL__SHIFT 0xc +#define DPIASYMCLK_CNTL__DPIASYMCLK3_EN__SHIFT 0xf +#define DPIASYMCLK_CNTL__DPIASYMCLK4_SRC_SEL__SHIFT 0x10 +#define DPIASYMCLK_CNTL__DPIASYMCLK4_EN__SHIFT 0x13 +#define DPIASYMCLK_CNTL__DPIASYMCLK5_SRC_SEL__SHIFT 0x14 +#define DPIASYMCLK_CNTL__DPIASYMCLK5_EN__SHIFT 0x17 +#define DPIASYMCLK_CNTL__DPIASYMCLK0_SRC_SEL_MASK 0x00000007L +#define DPIASYMCLK_CNTL__DPIASYMCLK0_EN_MASK 0x00000008L +#define DPIASYMCLK_CNTL__DPIASYMCLK1_SRC_SEL_MASK 0x00000070L +#define DPIASYMCLK_CNTL__DPIASYMCLK1_EN_MASK 0x00000080L +#define DPIASYMCLK_CNTL__DPIASYMCLK2_SRC_SEL_MASK 0x00000700L +#define DPIASYMCLK_CNTL__DPIASYMCLK2_EN_MASK 0x00000800L +#define DPIASYMCLK_CNTL__DPIASYMCLK3_SRC_SEL_MASK 0x00007000L +#define DPIASYMCLK_CNTL__DPIASYMCLK3_EN_MASK 0x00008000L +#define DPIASYMCLK_CNTL__DPIASYMCLK4_SRC_SEL_MASK 0x00070000L +#define DPIASYMCLK_CNTL__DPIASYMCLK4_EN_MASK 0x00080000L +#define DPIASYMCLK_CNTL__DPIASYMCLK5_SRC_SEL_MASK 0x00700000L +#define DPIASYMCLK_CNTL__DPIASYMCLK5_EN_MASK 0x00800000L +//DCCG_GLOBAL_FGCG_REP_CNTL +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT 0x0 +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK 0x00000001L +//OTG_ADD_DROP_PIXEL_CNTL +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_ADD_PIXEL__SHIFT 0x0 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_ADD_PIXEL__SHIFT 0x1 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_ADD_PIXEL__SHIFT 0x2 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_ADD_PIXEL__SHIFT 0x3 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_DROP_PIXEL__SHIFT 0x8 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_DROP_PIXEL__SHIFT 0xa +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_DROP_PIXEL__SHIFT 0xb +#define OTG_ADD_DROP_PIXEL_CNTL__OTG_ADD_DROP_PIXEL_DONE__SHIFT 0x1f +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_ADD_PIXEL_MASK 0x00000001L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_ADD_PIXEL_MASK 0x00000002L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_ADD_PIXEL_MASK 0x00000004L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_ADD_PIXEL_MASK 0x00000008L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_DROP_PIXEL_MASK 0x00000100L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_DROP_PIXEL_MASK 0x00000400L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_DROP_PIXEL_MASK 0x00000800L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG_ADD_DROP_PIXEL_DONE_MASK 0x80000000L +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//SYMCLK32_SE_CNTL +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT 0x3 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT 0x7 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT 0xb +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT 0xf +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK 0x00000008L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK 0x00000080L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK 0x00000800L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK 0x00008000L +//SYMCLK32_LE_CNTL +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT 0x3 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT 0x7 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_EN__SHIFT 0xb +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_EN__SHIFT 0xf +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK 0x00000008L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK 0x00000080L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_EN_MASK 0x00000800L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_EN_MASK 0x00008000L +//DTBCLK_P_CNTL +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT 0x0 +#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT 0x2 +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT 0x3 +#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT 0x5 +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT 0x6 +#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT 0x8 +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT 0x9 +#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT 0xb +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK 0x00000003L +#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK 0x00000004L +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK 0x00000018L +#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK 0x00000020L +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK 0x000000C0L +#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK 0x00000100L +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK 0x00000600L +#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK 0x00000800L +//DCCG_GATE_DISABLE_CNTL5 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE_MASK 0x10000000L +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK2_DTO_PARAM +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L +//OTG_PIXEL_RATE_DIV +#define OTG_PIXEL_RATE_DIV__OTG0_TMDS_PIXEL_RATE_DIV__SHIFT 0x0 +#define OTG_PIXEL_RATE_DIV__DPDTO0_INT__SHIFT 0x1 +#define OTG_PIXEL_RATE_DIV__OTG1_TMDS_PIXEL_RATE_DIV__SHIFT 0x5 +#define OTG_PIXEL_RATE_DIV__DPDTO1_INT__SHIFT 0x6 +#define OTG_PIXEL_RATE_DIV__OTG2_TMDS_PIXEL_RATE_DIV__SHIFT 0xa +#define OTG_PIXEL_RATE_DIV__DPDTO2_INT__SHIFT 0xb +#define OTG_PIXEL_RATE_DIV__OTG3_TMDS_PIXEL_RATE_DIV__SHIFT 0xf +#define OTG_PIXEL_RATE_DIV__DPDTO3_INT__SHIFT 0x10 +#define OTG_PIXEL_RATE_DIV__OTG0_TMDS_PIXEL_RATE_DIV_MASK 0x00000001L +#define OTG_PIXEL_RATE_DIV__DPDTO0_INT_MASK 0x0000001EL +#define OTG_PIXEL_RATE_DIV__OTG1_TMDS_PIXEL_RATE_DIV_MASK 0x00000020L +#define OTG_PIXEL_RATE_DIV__DPDTO1_INT_MASK 0x000003C0L +#define OTG_PIXEL_RATE_DIV__OTG2_TMDS_PIXEL_RATE_DIV_MASK 0x00000400L +#define OTG_PIXEL_RATE_DIV__DPDTO2_INT_MASK 0x00007800L +#define OTG_PIXEL_RATE_DIV__OTG3_TMDS_PIXEL_RATE_DIV_MASK 0x00008000L +#define OTG_PIXEL_RATE_DIV__DPDTO3_INT_MASK 0x000F0000L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__RESYNC_FIFO_LEVEL_ADJUST_EN__SHIFT 0x15 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x16 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x18 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__RESYNC_FIFO_LEVEL_ADJUST_EN_MASK 0x00200000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x00400000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x1F000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_PERFMON_CNTL +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_TEST_CLK_ENABLE__SHIFT 0xb +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_TEST_CLK_ENABLE_MASK 0x00000800L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE_MASK 0x10000000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT 0x7 +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT 0xc +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK 0x00000080L +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK 0x00001000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT 0x7 +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT 0xc +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK 0x00000080L +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK 0x00001000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT 0x7 +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT 0xc +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK 0x00000080L +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK 0x00001000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT 0x7 +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT 0xc +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK 0x00000080L +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK 0x00001000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK2_DTO_PARAM +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK3_DTO_PARAM +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0007FFFFL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL__SHIFT 0x5 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL_MASK 0x000000E0L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL__SHIFT 0x5 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL_MASK 0x000000E0L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL__SHIFT 0x5 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL_MASK 0x000000E0L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL__SHIFT 0x5 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL_MASK 0x000000E0L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL__SHIFT 0x5 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL_MASK 0x000000E0L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_EN__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_EN__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_EN__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_EN__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_EN__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_EN__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK0_EN_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_EN_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_EN_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_EN_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_EN_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_EN_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +//DPPCLK_CTRL +#define DPPCLK_CTRL__DPPCLK0_EN__SHIFT 0x0 +#define DPPCLK_CTRL__DPPCLK1_EN__SHIFT 0x3 +#define DPPCLK_CTRL__DPPCLK2_EN__SHIFT 0x6 +#define DPPCLK_CTRL__DPPCLK3_EN__SHIFT 0x9 +#define DPPCLK_CTRL__DPPCLK0_EN_MASK 0x00000001L +#define DPPCLK_CTRL__DPPCLK1_EN_MASK 0x00000008L +#define DPPCLK_CTRL__DPPCLK2_EN_MASK 0x00000040L +#define DPPCLK_CTRL__DPPCLK3_EN_MASK 0x00000200L +//DCCG_GATE_DISABLE_CNTL6 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL6__DPREFCLK_DIO_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL6__DPREFCLK_DIO_GATE_DISABLE_MASK 0x01000000L +//SYMCLK_PSP_CNTL +#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON__SHIFT 0x0 +#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON_MASK 0x00000001L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x10 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x11 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0x12 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0x13 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0x14 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0x15 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00002000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00010000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00020000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00040000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00080000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00100000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00200000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//DCCG_TEST_CLK_SEL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_OR_DATA_GENERICA__SHIFT 0x9 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_OR_DATA_GENERICA_MASK 0x00000200L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L +//HDMICHARCLK0_CLOCK_CNTL +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT 0x0 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT 0x4 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK 0x00000001L +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK 0x00000070L +//PHYASYMCLK_CLOCK_CNTL +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN__SHIFT 0x0 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN_MASK 0x00000001L +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL_MASK 0x00000030L +//PHYBSYMCLK_CLOCK_CNTL +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN__SHIFT 0x0 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN_MASK 0x00000001L +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL_MASK 0x00000030L +//PHYCSYMCLK_CLOCK_CNTL +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN__SHIFT 0x0 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN_MASK 0x00000001L +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL_MASK 0x00000030L +//PHYDSYMCLK_CLOCK_CNTL +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN__SHIFT 0x0 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN_MASK 0x00000001L +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL_MASK 0x00000030L +//PHYESYMCLK_CLOCK_CNTL +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN__SHIFT 0x0 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN_MASK 0x00000001L +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL_MASK 0x00000030L +//HDMISTREAMCLK_CNTL +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT 0x3 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK 0x00000008L +//DCCG_GATE_DISABLE_CNTL3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT 0xe +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE2_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE2_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE3_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE3_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK 0x00004000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK 0x00800000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE2_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE2_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE3_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE3_GATE_DISABLE_MASK 0x08000000L +//HDMISTREAMCLK0_DTO_PARAM +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT 0x0 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT 0x8 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT 0x10 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK 0x000000FFL +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK 0x0000FF00L +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK 0x00010000L +//DPIACLK_810M_DTO_PHASE +#define DPIACLK_810M_DTO_PHASE__DPIACLK_810M_DTO_PHASE__SHIFT 0x0 +#define DPIACLK_810M_DTO_PHASE__DPIACLK_810M_DTO_PHASE_MASK 0xFFFFFFFFL +//DPIACLK_540M_DTO_PHASE +#define DPIACLK_540M_DTO_PHASE__DPIACLK_540M_DTO_PHASE__SHIFT 0x0 +#define DPIACLK_540M_DTO_PHASE__DPIACLK_540M_DTO_PHASE_MASK 0xFFFFFFFFL +//DPIACLK_DTO_CNTL +#define DPIACLK_DTO_CNTL__DPIACLK_810M_DTO_ENABLE__SHIFT 0x0 +#define DPIACLK_DTO_CNTL__DPIACLK_540M_DTO_ENABLE__SHIFT 0x1 +#define DPIACLK_DTO_CNTL__DPIACLK_810M_DTO_ENABLE_MASK 0x00000001L +#define DPIACLK_DTO_CNTL__DPIACLK_540M_DTO_ENABLE_MASK 0x00000002L +//DPIACLK_810M_DTO_MODULO +#define DPIACLK_810M_DTO_MODULO__DPIACLK_810M_DTO_MODULO__SHIFT 0x0 +#define DPIACLK_810M_DTO_MODULO__DPIACLK_810M_DTO_MODULO_MASK 0xFFFFFFFFL +//DPIACLK_540M_DTO_MODULO +#define DPIACLK_540M_DTO_MODULO__DPIACLK_540M_DTO_MODULO__SHIFT 0x0 +#define DPIACLK_540M_DTO_MODULO__DPIACLK_540M_DTO_MODULO_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +//DC_PERFMON0_PERFCOUNTER_CNTL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_CNTL2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_STATE +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON0_PERFMON_CNTL +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON0_PERFMON_CNTL2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON0_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON0_PERFMON_CVALUE_LOW +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON0_PERFMON_HI +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFMON_LOW +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +//DC_PERFMON1_PERFCOUNTER_CNTL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_CNTL2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_STATE +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON1_PERFMON_CNTL +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON1_PERFMON_CNTL2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON1_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON1_PERFMON_CVALUE_LOW +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON1_PERFMON_HI +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFMON_LOW +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN16_PG_CONFIG +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN16_PG_STATUS +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN17_PG_CONFIG +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN17_PG_STATUS +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN18_PG_CONFIG +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN18_PG_STATUS +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN19_PG_CONFIG +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN19_PG_STATUS +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN22_PG_CONFIG +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN22_PG_STATUS +#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN23_PG_CONFIG +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN23_PG_STATUS +#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN24_PG_CONFIG +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN24_PG_STATUS +#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN25_PG_CONFIG +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN25_PG_STATUS +#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN26_PG_CONFIG +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN26_PG_STATUS +#define DOMAIN26_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN26_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN26_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN26_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_3 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L +//LONO_MEM_PWR_REQ_CNTL +#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS__SHIFT 0x0 +#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS_MASK 0x00000001L + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON2_PERFCOUNTER_CNTL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_CNTL2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_STATE +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON2_PERFMON_CNTL +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON2_PERFMON_CNTL2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON2_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON2_PERFMON_CVALUE_LOW +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON2_PERFMON_HI +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFMON_LOW +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT 0xc +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK 0x00001000L +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x5 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0x7 +#define DMU_CLK_CNTL__RIOMMU_CLK_SEL__SHIFT 0x8 +#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS__SHIFT 0xc +#define DMU_CLK_CNTL__IHC_FGCG_REP_DIS__SHIFT 0xd +#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL__SHIFT 0xe +#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP__SHIFT 0x10 +#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP__SHIFT 0x12 +#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP__SHIFT 0x14 +#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP__SHIFT 0x16 +#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP__SHIFT 0x18 +#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP__SHIFT 0x1a +#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS__SHIFT 0x1c +#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE__SHIFT 0x1d +#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE__SHIFT 0x1e +#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE__SHIFT 0x1f +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000020L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000080L +#define DMU_CLK_CNTL__RIOMMU_CLK_SEL_MASK 0x00000100L +#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS_MASK 0x00001000L +#define DMU_CLK_CNTL__IHC_FGCG_REP_DIS_MASK 0x00002000L +#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL_MASK 0x0000C000L +#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP_MASK 0x00030000L +#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP_MASK 0x000C0000L +#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP_MASK 0x00300000L +#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP_MASK 0x00C00000L +#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP_MASK 0x03000000L +#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP_MASK 0x0C000000L +#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS_MASK 0x10000000L +#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE_MASK 0x20000000L +#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE_MASK 0x40000000L +#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE_MASK 0x80000000L +//DMCUB_SMU_INTERRUPT_CNTL +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT 0x0 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT 0x10 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK 0x00000001L +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//ZSC_CNTL +#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT 0x0 +#define ZSC_CNTL__LONO_PWR_DN__SHIFT 0x8 +#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK 0x00000003L +#define ZSC_CNTL__LONO_PWR_DN_MASK 0x00000100L +//ZSC_CNTL2 +#define ZSC_CNTL2__ALLOW_Z10__SHIFT 0x0 +#define ZSC_CNTL2__ALLOW_Z10_MASK 0x00000001L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L +//ZSC_STATUS +#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0 +#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT 0x4 +#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT 0x8 +#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT 0x9 +#define ZSC_STATUS__FENCE_STATUS__SHIFT 0xa +#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK 0x00000007L +#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK 0x00000070L +#define ZSC_STATUS__FENCE_REQ_STATUS_MASK 0x00000100L +#define ZSC_STATUS__FENCE_ACK_STATUS_MASK 0x00000200L +#define ZSC_STATUS__FENCE_STATUS_MASK 0x00000C00L +//DMU_DISPCLK_CGTT_BLK_CTRL_REG +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DMU_SOCCLK_CGTT_BLK_CTRL_REG +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//ZPR_CLK_UNGATE_DELAY +#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY__SHIFT 0x0 +#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY_MASK 0x000000FFL + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP0_HIST_RDY_IHC_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP1_HIST_RDY_IHC_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP2_HIST_RDY_IHC_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_HIST_RDY_IHC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_HIST_RDY_IHC_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_HIST_RDY_IHC_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP6_HIST_RDY_IHC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP7_HIST_RDY_IHC_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP0_HIST_RDY_IHC_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP1_HIST_RDY_IHC_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP2_HIST_RDY_IHC_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_HIST_RDY_IHC_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_HIST_RDY_IHC_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_HIST_RDY_IHC_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP6_HIST_RDY_IHC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP7_HIST_RDY_IHC_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE25 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX0_RDY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX1_RDY_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX2_RDY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX3_RDY_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX4_RDY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_OUTBOX0_RSP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_INBOX0_RSP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_OUTBOX0_RDY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX0_RDY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX1_RDY_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX2_RDY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX3_RDY_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX4_RDY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_OUTBOX0_RSP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_INBOX0_RSP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_OUTBOX0_RDY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK 0x40000000L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +//DMU_INTERRUPT_DEST2 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX0_RDY_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX1_RDY_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX2_RDY_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX3_RDY_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX4_RDY_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_OUTBOX0_RSP_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_INBOX0_RSP_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_OUTBOX0_RDY_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX0_RDY_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX1_RDY_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX2_RDY_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX3_RDY_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX4_RDY_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_OUTBOX0_RSP_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_INBOX0_RSP_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_OUTBOX0_RDY_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK 0x00002000L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x18 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x19 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1a +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST_MASK 0x01000000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST_MASK 0x02000000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT_DEST_MASK 0x04000000L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT 0x8 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK 0x00000100L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK 0x04000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPP_INTERRUPT_DEST +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT 0x4 +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK 0x00000010L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +//HPO_INTERRUPT_DEST +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x4 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x5 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x6 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x7 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x8 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x9 +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000010L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000020L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000040L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000080L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000100L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000200L +//DPP_INTERRUPT_DEST +#define DPP_INTERRUPT_DEST__DPP0_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x0 +#define DPP_INTERRUPT_DEST__DPP1_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x1 +#define DPP_INTERRUPT_DEST__DPP2_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x2 +#define DPP_INTERRUPT_DEST__DPP3_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x3 +#define DPP_INTERRUPT_DEST__DPP4_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x4 +#define DPP_INTERRUPT_DEST__DPP5_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x5 +#define DPP_INTERRUPT_DEST__DPP6_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x6 +#define DPP_INTERRUPT_DEST__DPP7_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x7 +#define DPP_INTERRUPT_DEST__DPP0_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000001L +#define DPP_INTERRUPT_DEST__DPP1_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000002L +#define DPP_INTERRUPT_DEST__DPP2_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000004L +#define DPP_INTERRUPT_DEST__DPP3_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000008L +#define DPP_INTERRUPT_DEST__DPP4_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000010L +#define DPP_INTERRUPT_DEST__DPP5_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000020L +#define DPP_INTERRUPT_DEST__DPP6_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000040L +#define DPP_INTERRUPT_DEST__DPP7_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000080L + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +//DMCUB_RBBMIF_SEC_CNTL +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL__SHIFT 0x0 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT 0x4 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT 0x8 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL_MASK 0x00000007L +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK 0x000000F0L +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK 0x01FFFF00L + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL +//RBBMIF_STATUS_2 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x000000FFL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS_2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT39_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT39_TIMEOUT_DIS_MASK 0x00000080L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT 0xe +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT 0xf +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT 0x10 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT 0x11 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0x12 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX0_RDY_INT_EN__SHIFT 0x13 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX2_RDY_INT_EN__SHIFT 0x15 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX3_RDY_INT_EN__SHIFT 0x16 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX4_RDY_INT_EN__SHIFT 0x17 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_OUTBOX0_RSP_INT_EN__SHIFT 0x18 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK 0x00002000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK 0x00004000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK 0x00008000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK 0x00010000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK 0x00020000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00040000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX0_RDY_INT_EN_MASK 0x00080000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX2_RDY_INT_EN_MASK 0x00200000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX3_RDY_INT_EN_MASK 0x00400000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX4_RDY_INT_EN_MASK 0x00800000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_OUTBOX0_RSP_INT_EN_MASK 0x01000000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT 0xe +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT 0xf +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT 0x10 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT 0x11 +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0x12 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX0_RDY_INT_ACK__SHIFT 0x13 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX2_RDY_INT_ACK__SHIFT 0x15 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX3_RDY_INT_ACK__SHIFT 0x16 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX4_RDY_INT_ACK__SHIFT 0x17 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_OUTBOX0_RSP_INT_ACK__SHIFT 0x18 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK 0x00002000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK 0x00004000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK 0x00008000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK 0x00010000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK 0x00020000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00040000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX0_RDY_INT_ACK_MASK 0x00080000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX2_RDY_INT_ACK_MASK 0x00200000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX3_RDY_INT_ACK_MASK 0x00400000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX4_RDY_INT_ACK_MASK 0x00800000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_OUTBOX0_RSP_INT_ACK_MASK 0x01000000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT 0x10 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT 0x11 +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0x12 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0x13 +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0x14 +#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT__SHIFT 0x15 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT__SHIFT 0x16 +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX0_RDY_INT_STAT__SHIFT 0x17 +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX2_RDY_INT_STAT__SHIFT 0x19 +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX3_RDY_INT_STAT__SHIFT 0x1a +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX4_RDY_INT_STAT__SHIFT 0x1b +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_OUTBOX0_RSP_INT_STAT__SHIFT 0x1c +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK 0x00008000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK 0x00010000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK 0x00020000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00040000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00080000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00100000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT_MASK 0x00200000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT_MASK 0x00400000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX0_RDY_INT_STAT_MASK 0x00800000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX2_RDY_INT_STAT_MASK 0x02000000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX3_RDY_INT_STAT_MASK 0x04000000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX4_RDY_INT_STAT_MASK 0x08000000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_OUTBOX0_RSP_INT_STAT_MASK 0x10000000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT 0xe +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT 0xf +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT 0x10 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT 0x11 +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0x12 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK 0x00002000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK 0x00004000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK 0x00008000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK 0x00010000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK 0x00020000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00040000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH16 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT 0x0 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH17 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT 0x0 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH18 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT 0x0 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL +//DMCUB_CNTL2 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT 0x0 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK 0x00000001L +//DMCUB_GPINT_DATAIN2 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN3 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN4 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN5 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN6 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK 0xFFFFFFFFL +//DMCUB_REGION3_TMR_AXI_SPACE +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT 0x0 +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK 0x07L +//DMCUB_SCRATCH19 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT 0x0 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH20 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT 0x0 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH21 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT 0x0 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH22 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT 0x0 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH23 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT 0x0 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK 0xFFFFFFFFL +//HOST_INTERRUPT_CSR +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_EN__SHIFT 0x0 +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_EN__SHIFT 0x1 +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_ACK__SHIFT 0x8 +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_ACK__SHIFT 0x9 +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_STAT__SHIFT 0xc +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_STAT__SHIFT 0xd +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_EN_MASK 0x00000001L +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_EN_MASK 0x00000002L +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_ACK_MASK 0x00000100L +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_ACK_MASK 0x00000200L +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_STAT_MASK 0x00001000L +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_STAT_MASK 0x00002000L +//DMCUB_REG_INBOX0_RDY +#define DMCUB_REG_INBOX0_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG0 +#define DMCUB_REG_INBOX0_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG1 +#define DMCUB_REG_INBOX0_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG2 +#define DMCUB_REG_INBOX0_MSG2__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG2__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG3 +#define DMCUB_REG_INBOX0_MSG3__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG3__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG4 +#define DMCUB_REG_INBOX0_MSG4__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG4__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG5 +#define DMCUB_REG_INBOX0_MSG5__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG5__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG6 +#define DMCUB_REG_INBOX0_MSG6__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG6__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG7 +#define DMCUB_REG_INBOX0_MSG7__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG7__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG8 +#define DMCUB_REG_INBOX0_MSG8__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG8__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG9 +#define DMCUB_REG_INBOX0_MSG9__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG9__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG10 +#define DMCUB_REG_INBOX0_MSG10__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG10__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG11 +#define DMCUB_REG_INBOX0_MSG11__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG11__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG12 +#define DMCUB_REG_INBOX0_MSG12__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG12__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG13 +#define DMCUB_REG_INBOX0_MSG13__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG13__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG14 +#define DMCUB_REG_INBOX0_MSG14__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG14__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_RSP +#define DMCUB_REG_INBOX0_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_OUTBOX0_RDY +#define DMCUB_REG_OUTBOX0_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_OUTBOX0_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_OUTBOX0_MSG0 +#define DMCUB_REG_OUTBOX0_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_OUTBOX0_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_OUTBOX0_RSP +#define DMCUB_REG_OUTBOX0_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_OUTBOX0_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_RDY +#define DMCUB_REG_INBOX1_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_MSG0 +#define DMCUB_REG_INBOX1_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_MSG1 +#define DMCUB_REG_INBOX1_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_RSP +#define DMCUB_REG_INBOX1_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_INTERRUPT_CSR +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_EN__SHIFT 0x0 +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_ACK__SHIFT 0x1 +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_STAT__SHIFT 0x2 +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_EN_MASK 0x00000001L +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_ACK_MASK 0x00000002L +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_STAT_MASK 0x00000004L +//DMCUB_REG_INBOX2_RDY +#define DMCUB_REG_INBOX2_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX2_MSG0 +#define DMCUB_REG_INBOX2_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX2_MSG1 +#define DMCUB_REG_INBOX2_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX2_RSP +#define DMCUB_REG_INBOX2_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_RDY +#define DMCUB_REG_INBOX3_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_MSG0 +#define DMCUB_REG_INBOX3_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_MSG1 +#define DMCUB_REG_INBOX3_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_RSP +#define DMCUB_REG_INBOX3_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_RDY +#define DMCUB_REG_INBOX4_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_MSG0 +#define DMCUB_REG_INBOX4_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_MSG1 +#define DMCUB_REG_INBOX4_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_RSP +#define DMCUB_REG_INBOX4_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_IDLE_HYSTERESIS_CSR +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_ENABLE__SHIFT 0x0 +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_STATE__SHIFT 0x1 +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_THRESHOLD__SHIFT 0x10 +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_ENABLE_MASK 0x00000001L +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_STATE_MASK 0x00000002L +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_THRESHOLD_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB_BUFMGR_STATUS +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000001L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000002L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB_BUF_PITCH +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB_BUF_1_STATUS +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_BUF_2_STATUS +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_BUF_3_STATUS +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_BUF_4_STATUS +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x14 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFF00000L +//MCIF_WB_SCLK_CHANGE +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +//MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +//MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MULTI_LEVEL_QOS_CTRL +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB_SECURITY_LEVEL +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT 0x4 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK 0x00000070L +//MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_PSTATE_CHANGE_DURATION_VBI +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x0 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x10 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0x0000FFFFL +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0xFFFF0000L +//MCIF_WB_VMID_CONTROL +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT 0x0 +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK 0x0000000FL +//MCIF_WB_MIN_TTO +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT 0x0 +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK 0x0007FFFFL +//MCIF_WB_TMZ +#define MCIF_WB_TMZ__MCIF_WB_TMZ__SHIFT 0x0 +#define MCIF_WB_TMZ__MCIF_WB_TMZ_MASK 0x0000000FL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT 0x1f +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x07000000L +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK 0x80000000L +//MCIF_WB_WATERMARK +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x07000000L +//MMHUBBUB_WARMUP_CONFIG +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT 0x10 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT 0x14 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK 0x000F0000L +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK 0x00F00000L +//MMHUBBUB_WARMUP_CONTROL_STATUS +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT 0x0 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT 0x4 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT 0x5 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT 0x6 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT 0x8 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK 0x00000001L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK 0x00000010L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK 0x00000020L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK 0x00000040L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK 0x03FFFF00L +//MMHUBBUB_WARMUP_BASE_ADDR_LOW +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK 0xFFFFFFFFL +//MMHUBBUB_WARMUP_BASE_ADDR_HIGH +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK 0x000007FFL +//MMHUBBUB_WARMUP_ADDR_REGION +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT 0x0 +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK 0x07FFFFFFL +//MMHUBBUB_MIN_TTO +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT 0x0 +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK 0x0007FFFFL +//MMHUBBUB_CTRL +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT 0x0 +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK 0x00000003L +//WBIF_SMU_WM_CONTROL +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT 0x11 +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK 0x00020000L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L +//MMHUBBUB_WARMUP_SECURITY_CFG +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_UNITID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SECURE_LVL__SHIFT 0x8 +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SPACE__SHIFT 0x10 +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_UNITID_MASK 0x0000003FL +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SECURE_LVL_MASK 0x00000700L +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SPACE_MASK 0x00070000L +//MMHUBBUB_WARMUP_VMID_CONTROL +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK 0x0000000FL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON3_PERFCOUNTER_CNTL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_CNTL2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_STATE +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON3_PERFMON_CNTL +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON3_PERFMON_CNTL2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON3_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON3_PERFMON_CVALUE_LOW +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON3_PERFMON_HI +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFMON_LOW +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS__SHIFT 0x1 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x4 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0xc +#define AZ_CLOCK_CNTL__SCLK_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY__SHIFT 0x14 +#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS_MASK 0x00000002L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000010L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x0000F000L +#define AZ_CLOCK_CNTL__SCLK_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY_MASK 0x00F00000L +#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY_MASK 0xFF000000L +//AZ_MEM_GLOBAL_PWR_REQ_CNTL +#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//AZ_STRAPS +#define AZ_STRAPS__AUDIO_PORT_CONNECTIVITY__SHIFT 0x0 +#define AZ_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x4 +#define AZ_STRAPS__AUDIO_PORT_CONNECTIVITY_MASK 0x00000007L +#define AZ_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x00000070L + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON4_PERFCOUNTER_CNTL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_CNTL2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_STATE +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON4_PERFMON_CNTL +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON4_PERFMON_CNTL2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON4_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON4_PERFMON_CVALUE_LOW +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON4_PERFMON_HI +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFMON_LOW +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW_MASK 0x00010000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT 0x9 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK 0x00000200L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_NOALLOC +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT 0x1 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT 0x2 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK 0x00000001L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK 0x00000002L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK 0x00000004L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK 0x00000008L +//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE0_3DLUT_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE1_3DLUT_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE2_3DLUT_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE3_3DLUT_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE0_3DLUT_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE1_3DLUT_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE2_3DLUT_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE3_3DLUT_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK 0x0000F000L +//SDPIF_REQUEST_RATE_LIMIT +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT 0x0 +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK 0x00000FFFL +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00001000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R +#define DCHUBBUB_CRC0_VAL_R__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R__DCHUBBUB_CRC0_R_CR_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC0_VAL_G +#define DCHUBBUB_CRC0_VAL_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC0_VAL_B +#define DCHUBBUB_CRC0_VAL_B__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B__DCHUBBUB_CRC0_B_CB_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC0_VAL_A +#define DCHUBBUB_CRC0_VAL_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_R +#define DCHUBBUB_CRC1_VAL_R__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R__DCHUBBUB_CRC1_R_CR_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_G +#define DCHUBBUB_CRC1_VAL_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_B +#define DCHUBBUB_CRC1_VAL_B__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B__DCHUBBUB_CRC1_B_CB_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_A +#define DCHUBBUB_CRC1_VAL_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT_CNTL +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT 0x1 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT 0x2 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT 0x4 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT 0x10 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK 0x00000001L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK 0x00000002L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK 0x00000004L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK 0x000000F0L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT1 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT2 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_COMPBUF_CTRL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT 0x0 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT 0x10 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT 0x12 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT 0x13 +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT 0x1f +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK 0x0000001FL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK 0x00001F00L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK 0x00010000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK 0x00040000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK 0x00080000L +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK 0x80000000L +//DCHUBBUB_DET0_CTRL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET1_CTRL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET2_CTRL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET3_CTRL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_MEM_PWR_MODE_CTRL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x10 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT 0x12 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x14 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT 0x18 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT 0x19 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT 0x1a +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK 0x00030000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK 0x000C0000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00300000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK 0x01000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK 0x02000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK 0x04000000L +//COMPBUF_MEM_PWR_CTRL_1 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT 0x10 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT 0x18 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK 0x0000FF00L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK 0x00FF0000L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK 0xFF000000L +//COMPBUF_MEM_PWR_CTRL_2 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY__SHIFT 0xc +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY_MASK 0x00000F00L +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY_MASK 0x0000F000L +//DCHUBBUB_MEM_PWR_STATUS +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT 0xc +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT 0xe +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK 0x00003000L +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK 0x0000C000L +//COMPBUF_RESERVED_SPACE +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT 0x0 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT 0x10 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L +//DCHUBBUB_DEBUG_CTRL_0 +#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH__SHIFT 0x0 +#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH__SHIFT 0x8 +#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH__SHIFT 0xc +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 +#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE__SHIFT 0x1b +#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE__SHIFT 0x1c +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE__SHIFT 0x1d +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE__SHIFT 0x1e +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE__SHIFT 0x1f +#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH_MASK 0x000000FFL +#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH_MASK 0x00000F00L +#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH_MASK 0x0000F000L +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x07FF0000L +#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE_MASK 0x08000000L +#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE_MASK 0x10000000L +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE_MASK 0x20000000L +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE_MASK 0x40000000L +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE_MASK 0x80000000L +//DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX +#define DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_MASK 0x000000FFL +//DCHUBBUB_RET_PATH_TEST_DEBUG_DATA +#define DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__DCHUBBUB_RET_PATH_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xa +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT 0x16 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x0007FC00L +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK 0x7FC00000L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x9 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT 0xc +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000200L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK 0x0000F000L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x2 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT 0x7 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT 0xc +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE__SHIFT 0xd +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DISABL_EXIT_DEEPSLEEP_WHEN_PREFETCH_START_PENDING__SHIFT 0xe +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP__SHIFT 0xf +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE__SHIFT 0x10 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE__SHIFT 0x11 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY__SHIFT 0x12 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS__SHIFT 0x18 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000004L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK 0x00000080L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK 0x00001000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE_MASK 0x00002000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DISABL_EXIT_DEEPSLEEP_WHEN_PREFETCH_START_PENDING_MASK 0x00004000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP_MASK 0x00008000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE_MASK 0x00010000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE_MASK 0x00020000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY_MASK 0x00040000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS_MASK 0xFF000000L +//DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_NO_PENDING_HVM_REQ_BEFORE_ENTER_CSTATE_HYSTERESIS__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL_RESERVED__SHIFT 0x10 +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_NO_PENDING_HVM_REQ_BEFORE_ENTER_CSTATE_HYSTERESIS_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL_RESERVED_MASK 0xFFFF0000L +//DCHUBBUB_ARB_USR_RETRAINING_CNTL +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT 0x1 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT 0x8 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT 0x9 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0xa +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT 0xb +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK 0x00000001L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK 0x00000002L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK 0x00000100L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK 0x00000200L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000400L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK 0x00000800L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//DCHUBBUB_ARB_HOSTVM_CNTL +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT 0x0 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT 0x1 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING__SHIFT 0x2 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT 0x3 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT 0x4 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT 0x6 +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT 0x7 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT 0x8 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT 0x10 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT 0x18 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT 0x1c +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK 0x00000001L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK 0x00000002L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING_MASK 0x00000004L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK 0x00000008L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK 0x00000010L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK 0x00000040L +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK 0x00000080L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK 0x00003F00L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK 0x00FF0000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK 0x0F000000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK 0xF0000000L +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT 0x10 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT 0x18 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK 0x00010000L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK 0x01000000L +//DCHUBBUB_ARB_MALL_CNTL +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT 0x0 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT 0x4 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK 0x00000001L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK 0x00000010L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT 0x7 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK 0x00000080L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT 0x2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK 0x00000002L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK 0x00000004L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x003FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_DEBUG_SEL__SHIFT 0xf +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x14 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_DEBUG_SEL_MASK 0x00008000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF00000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 +#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG__SHIFT 0x4 +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L +#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG_MASK 0x3FFFFFF0L +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L +//DCHUBBUB_TEST_DEBUG_INDEX +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK 0x000000FFL +//DCHUBBUB_TEST_DEBUG_DATA +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON5_PERFCOUNTER_CNTL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_CNTL2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_STATE +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON5_PERFMON_CNTL +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON5_PERFMON_CNTL2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON5_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON5_PERFMON_CVALUE_LOW +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON5_PERFMON_HI +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFMON_LOW +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x1a +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK 0x00F00000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x03000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x3C000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP0_DCHUBP_MALL_CONFIG +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP0_DCHUBP_MALL_SUB_VP +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP0_HUBPREQ_DEBUG_DB +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP0_HUBPREQ_DEBUG +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP0_HUBP_DEBUG_CTRL +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP0_HUBP_DEBUG_MUX_DCFCLK +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP0_HUBP_DEBUG_MUX_DPPCLK +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP0_HUBP_MALL_STATUS +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_DMDATA_VM_CNTL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_UCLK_PSTATE_FORCE +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ0_HUBPREQ_STATUS_REG0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG1 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_0_HUBP_3DLUT_CONTROL +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_0_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON6_PERFCOUNTER_CNTL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_CNTL2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_STATE +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON6_PERFMON_CNTL +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON6_PERFMON_CNTL2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON6_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON6_PERFMON_CVALUE_LOW +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON6_PERFMON_HI +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFMON_LOW +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP1_DCHUBP_MALL_CONFIG +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP1_DCHUBP_MALL_SUB_VP +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP1_HUBPREQ_DEBUG_DB +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP1_HUBPREQ_DEBUG +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP1_HUBP_DEBUG_CTRL +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP1_HUBP_DEBUG_MUX_DCFCLK +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP1_HUBP_DEBUG_MUX_DPPCLK +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP1_HUBP_MALL_STATUS +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_DMDATA_VM_CNTL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_UCLK_PSTATE_FORCE +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ1_HUBPREQ_STATUS_REG0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG1 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_1_HUBP_3DLUT_CONTROL +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_1_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON7_PERFCOUNTER_CNTL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_CNTL2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_STATE +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON7_PERFMON_CNTL +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON7_PERFMON_CNTL2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON7_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON7_PERFMON_CVALUE_LOW +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON7_PERFMON_HI +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFMON_LOW +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP2_DCHUBP_MALL_CONFIG +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP2_DCHUBP_MALL_SUB_VP +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP2_HUBPREQ_DEBUG_DB +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP2_HUBPREQ_DEBUG +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP2_HUBP_DEBUG_CTRL +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP2_HUBP_DEBUG_MUX_DCFCLK +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP2_HUBP_DEBUG_MUX_DPPCLK +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP2_HUBP_MALL_STATUS +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_VMID_SETTINGS_0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_DMDATA_VM_CNTL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINGS +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINGS_C +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ2_FLIP_PARAMETERS_1 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_2 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINGS +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ2_VBLANK_PARAMETERS_5 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_6 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_3 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_4 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_5 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_6 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_UCLK_PSTATE_FORCE +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ2_HUBPREQ_STATUS_REG0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG1 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +//CURSOR0_2_CURSOR_CONTROL +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_2_CURSOR_SURFACE_ADDRESS +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_CURSOR_SIZE +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_2_CURSOR_POSITION +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_2_CURSOR_HOT_SPOT +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_2_CURSOR_STEREO_CONTROL +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_2_CURSOR_DST_OFFSET +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_2_CURSOR_MEM_PWR_CTRL +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_2_CURSOR_MEM_PWR_STATUS +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_2_DMDATA_ADDRESS_HIGH +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_2_DMDATA_ADDRESS_LOW +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_DMDATA_CNTL +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_QOS_CNTL +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_2_DMDATA_STATUS +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_2_DMDATA_SW_CNTL +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_SW_DATA +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_2_HUBP_3DLUT_CONTROL +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_2_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON8_PERFCOUNTER_CNTL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_CNTL2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_STATE +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON8_PERFMON_CNTL +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON8_PERFMON_CNTL2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON8_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON8_PERFMON_CVALUE_LOW +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON8_PERFMON_HI +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFMON_LOW +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP3_DCHUBP_MALL_CONFIG +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP3_DCHUBP_MALL_SUB_VP +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP3_HUBPREQ_DEBUG_DB +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP3_HUBPREQ_DEBUG +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP3_HUBP_DEBUG_CTRL +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP3_HUBP_DEBUG_MUX_DCFCLK +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP3_HUBP_DEBUG_MUX_DPPCLK +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP3_HUBP_MALL_STATUS +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_VMID_SETTINGS_0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_DMDATA_VM_CNTL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINGS +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINGS_C +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ3_FLIP_PARAMETERS_1 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_2 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINGS +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ3_VBLANK_PARAMETERS_5 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_6 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_3 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_4 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_5 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_6 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_UCLK_PSTATE_FORCE +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ3_HUBPREQ_STATUS_REG0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG1 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +//CURSOR0_3_CURSOR_CONTROL +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_3_CURSOR_SURFACE_ADDRESS +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_CURSOR_SIZE +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_3_CURSOR_POSITION +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_3_CURSOR_HOT_SPOT +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_3_CURSOR_STEREO_CONTROL +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_3_CURSOR_DST_OFFSET +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_3_CURSOR_MEM_PWR_CTRL +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_3_CURSOR_MEM_PWR_STATUS +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_3_DMDATA_ADDRESS_HIGH +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_3_DMDATA_ADDRESS_LOW +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_DMDATA_CNTL +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_QOS_CNTL +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_3_DMDATA_STATUS +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_3_DMDATA_SW_CNTL +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_SW_DATA +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_3_HUBP_3DLUT_CONTROL +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_3_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON9_PERFCOUNTER_CNTL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_CNTL2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_STATE +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON9_PERFMON_CNTL +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON9_PERFMON_CNTL2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON9_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON9_PERFMON_CVALUE_LOW +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON9_PERFMON_HI +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFMON_LOW +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP0_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP0_DPP_CRC_VAL_R +#define DPP_TOP0_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_VAL_G +#define DPP_TOP0_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_VAL_B +#define DPP_TOP0_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_VAL_A +#define DPP_TOP0_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT01 +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT23 +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG0_PRE_DEALPHA +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG0_PRE_CSC_MODE +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG0_PRE_CSC_C11_C12 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C13_C14 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C21_C22 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C23_C24 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C31_C32 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C33_C34 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C11_C12 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C13_C14 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C21_C22 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C23_C24 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C31_C32 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C33_C34 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG0_CNVC_COEF_FORMAT +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG0_PRE_DEGAM +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG0_PRE_REALPHA +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_cur_dispdec +//CM_CUR0_CURSOR0_CONTROL +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR0_CURSOR0_COLOR0 +#define CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR0_CURSOR0_COLOR1 +#define CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_MODE +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR0_CUR0_MATRIX_C11_C12_A +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C13_C14_A +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C21_C22_A +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C23_C24_A +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C31_C32_A +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C33_C34_A +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C11_C12_B +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C13_C14_B +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C21_C22_B +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C23_C24_B +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C31_C32_B +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C33_C34_B +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_COLOR +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL0_DSCL_EASF_H_MODE +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL0_DSCL_EASF_V_MODE +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL0_DSCL_SC_MODE +#define DSCL0_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL0_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL0_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL0_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL0_DSCL_SC_MATRIX_C0C1 +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL0_DSCL_SC_MATRIX_C2C3 +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_RINGEST_FORCE +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_H_BF_CNTL +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL0_DSCL_EASF_V_BF_CNTL +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL0_ISHARP_MODE +#define DSCL0_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL0_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL0_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL0_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL0_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL0_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL0_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL0_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL0_ISHARP_DELTA_CTRL +#define DSCL0_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL0_ISHARP_DELTA_INDEX +#define DSCL0_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL0_ISHARP_DELTA_DATA +#define DSCL0_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL0_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL0_ISHARP_NOISEDET_THRESHOLD +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL0_ISHARP_NOISE_GAIN_PWL +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL0_ISHARP_LBA_PWL_SEG0 +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG1 +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG2 +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG3 +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG4 +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG5 +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_POST_CSC_CONTROL +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_POST_CSC_C11_C12 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C13_C14 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C21_C22 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C23_C24 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C31_C32 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C33_C34 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C11_C12 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C13_C14 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C21_C22 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C23_C24 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C31_C32 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C33_C34 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_CONTROL +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_GAMCOR_LUT_INDEX +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_GAMCOR_LUT_DATA +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_LUT_CONTROL +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_GAMCOR_RAMA_START_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_OFFSET_B +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_G +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_R +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_REGION_0_1 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_2_3 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_4_5 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_6_7 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_8_9 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_10_11 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_12_13 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_14_15 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_16_17 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_18_19 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_20_21 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_22_23 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_24_25 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_26_27 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_28_29 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_30_31 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_32_33 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_OFFSET_B +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_G +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_R +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_REGION_0_1 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_2_3 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_4_5 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_6_7 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_8_9 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_10_11 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_12_13 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_14_15 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_16_17 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_18_19 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_20_21 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_22_23 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_24_25 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_26_27 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_28_29 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_30_31 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_32_33 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM0_CM_TEST_DEBUG_INDEX +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM0_CM_TEST_DEBUG_DATA +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM0_CM_HIST_CNTL +#define CM0_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM0_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM0_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM0_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM0_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM0_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM0_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM0_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM0_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM0_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM0_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM0_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM0_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM0_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM0_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM0_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM0_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM0_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM0_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM0_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM0_CM_HIST_SCALE_SRC1 +#define CM0_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM0_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM0_CM_HIST_COEFA_SRC2 +#define CM0_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_COEFB_SRC2 +#define CM0_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_COEFC_SRC2 +#define CM0_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_SCALE_SRC3 +#define CM0_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM0_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM0_CM_HIST_BIAS_SRC1 +#define CM0_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM0_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM0_CM_HIST_BIAS_SRC2 +#define CM0_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_BIAS_SRC3 +#define CM0_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM0_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM0_CM_HIST_LOCK +#define CM0_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM0_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM0_CM_HIST_INDEX +#define CM0_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM0_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM0_CM_HIST_DATA +#define CM0_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM0_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM0_CM_HIST_STATUS +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM0_CM_HIST_INT_CONTROL +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON10_PERFCOUNTER_CNTL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_CNTL2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_STATE +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON10_PERFMON_CNTL +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON10_PERFMON_CNTL2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON10_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON10_PERFMON_CVALUE_LOW +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON10_PERFMON_HI +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFMON_LOW +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP1_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP1_DPP_CRC_VAL_R +#define DPP_TOP1_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_VAL_G +#define DPP_TOP1_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_VAL_B +#define DPP_TOP1_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_VAL_A +#define DPP_TOP1_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT01 +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT23 +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG1_PRE_DEALPHA +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG1_PRE_CSC_MODE +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG1_PRE_CSC_C11_C12 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C13_C14 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C21_C22 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C23_C24 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C31_C32 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C33_C34 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C11_C12 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C13_C14 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C21_C22 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C23_C24 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C31_C32 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C33_C34 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG1_CNVC_COEF_FORMAT +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG1_PRE_DEGAM +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG1_PRE_REALPHA +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_cur_dispdec +//CM_CUR1_CURSOR0_CONTROL +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR1_CURSOR0_COLOR0 +#define CM_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR1_CURSOR0_COLOR1 +#define CM_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_MODE +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR1_CUR0_MATRIX_C11_C12_A +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C13_C14_A +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C21_C22_A +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C23_C24_A +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C31_C32_A +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C33_C34_A +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C11_C12_B +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C13_C14_B +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C21_C22_B +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C23_C24_B +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C31_C32_B +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C33_C34_B +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_COLOR +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL1_DSCL_EASF_H_MODE +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL1_DSCL_EASF_V_MODE +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL1_DSCL_SC_MODE +#define DSCL1_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL1_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL1_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL1_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL1_DSCL_SC_MATRIX_C0C1 +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL1_DSCL_SC_MATRIX_C2C3 +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_RINGEST_FORCE +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_H_BF_CNTL +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL1_DSCL_EASF_V_BF_CNTL +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL1_ISHARP_MODE +#define DSCL1_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL1_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL1_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL1_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL1_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL1_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL1_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL1_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL1_ISHARP_DELTA_CTRL +#define DSCL1_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL1_ISHARP_DELTA_INDEX +#define DSCL1_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL1_ISHARP_DELTA_DATA +#define DSCL1_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL1_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL1_ISHARP_NOISEDET_THRESHOLD +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL1_ISHARP_NOISE_GAIN_PWL +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL1_ISHARP_LBA_PWL_SEG0 +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG1 +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG2 +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG3 +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG4 +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG5 +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_POST_CSC_CONTROL +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_POST_CSC_C11_C12 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C13_C14 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C21_C22 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C23_C24 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C31_C32 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C33_C34 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C11_C12 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C13_C14 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C21_C22 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C23_C24 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C31_C32 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C33_C34 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_CONTROL +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_GAMCOR_LUT_INDEX +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_GAMCOR_LUT_DATA +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_LUT_CONTROL +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_GAMCOR_RAMA_START_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_OFFSET_B +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_G +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_R +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_REGION_0_1 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_2_3 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_4_5 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_6_7 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_8_9 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_10_11 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_12_13 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_14_15 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_16_17 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_18_19 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_20_21 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_22_23 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_24_25 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_26_27 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_28_29 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_30_31 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_32_33 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_OFFSET_B +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_G +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_R +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_REGION_0_1 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_2_3 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_4_5 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_6_7 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_8_9 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_10_11 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_12_13 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_14_15 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_16_17 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_18_19 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_20_21 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_22_23 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_24_25 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_26_27 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_28_29 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_30_31 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_32_33 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM1_CM_TEST_DEBUG_INDEX +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM1_CM_TEST_DEBUG_DATA +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM1_CM_HIST_CNTL +#define CM1_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM1_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM1_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM1_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM1_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM1_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM1_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM1_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM1_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM1_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM1_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM1_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM1_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM1_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM1_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM1_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM1_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM1_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM1_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM1_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM1_CM_HIST_SCALE_SRC1 +#define CM1_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM1_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM1_CM_HIST_COEFA_SRC2 +#define CM1_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_COEFB_SRC2 +#define CM1_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_COEFC_SRC2 +#define CM1_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_SCALE_SRC3 +#define CM1_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM1_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM1_CM_HIST_BIAS_SRC1 +#define CM1_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM1_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM1_CM_HIST_BIAS_SRC2 +#define CM1_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_BIAS_SRC3 +#define CM1_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM1_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM1_CM_HIST_LOCK +#define CM1_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM1_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM1_CM_HIST_INDEX +#define CM1_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM1_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM1_CM_HIST_DATA +#define CM1_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM1_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM1_CM_HIST_STATUS +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM1_CM_HIST_INT_CONTROL +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON11_PERFCOUNTER_CNTL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_CNTL2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_STATE +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON11_PERFMON_CNTL +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON11_PERFMON_CNTL2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON11_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON11_PERFMON_CVALUE_LOW +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON11_PERFMON_HI +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFMON_LOW +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP2_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP2_DPP_CRC_VAL_R +#define DPP_TOP2_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_VAL_G +#define DPP_TOP2_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_VAL_B +#define DPP_TOP2_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_VAL_A +#define DPP_TOP2_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG2_FCNV_FP_BIAS_R +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_G +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_B +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_R +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_G +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_B +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT01 +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT23 +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG2_PRE_DEALPHA +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG2_PRE_CSC_MODE +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG2_PRE_CSC_C11_C12 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C13_C14 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C21_C22 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C23_C24 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C31_C32 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C33_C34 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C11_C12 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C13_C14 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C21_C22 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C23_C24 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C31_C32 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C33_C34 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG2_CNVC_COEF_FORMAT +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG2_PRE_DEGAM +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG2_PRE_REALPHA +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_cur_dispdec +//CM_CUR2_CURSOR0_CONTROL +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR2_CURSOR0_COLOR0 +#define CM_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR2_CURSOR0_COLOR1 +#define CM_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_MODE +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR2_CUR0_MATRIX_C11_C12_A +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C13_C14_A +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C21_C22_A +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C23_C24_A +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C31_C32_A +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C33_C34_A +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C11_C12_B +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C13_C14_B +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C21_C22_B +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C23_C24_B +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C31_C32_B +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C33_C34_B +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_COLOR +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL2_DSCL_EASF_H_MODE +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL2_DSCL_EASF_V_MODE +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL2_DSCL_SC_MODE +#define DSCL2_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL2_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL2_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL2_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL2_DSCL_SC_MATRIX_C0C1 +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL2_DSCL_SC_MATRIX_C2C3 +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_RINGEST_FORCE +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_H_BF_CNTL +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL2_DSCL_EASF_V_BF_CNTL +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL2_ISHARP_MODE +#define DSCL2_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL2_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL2_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL2_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL2_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL2_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL2_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL2_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL2_ISHARP_DELTA_CTRL +#define DSCL2_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL2_ISHARP_DELTA_INDEX +#define DSCL2_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL2_ISHARP_DELTA_DATA +#define DSCL2_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL2_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL2_ISHARP_NOISEDET_THRESHOLD +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL2_ISHARP_NOISE_GAIN_PWL +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL2_ISHARP_LBA_PWL_SEG0 +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG1 +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG2 +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG3 +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG4 +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG5 +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_POST_CSC_CONTROL +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_POST_CSC_C11_C12 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C13_C14 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C21_C22 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C23_C24 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C31_C32 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C33_C34 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C11_C12 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C13_C14 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C21_C22 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C23_C24 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C31_C32 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C33_C34 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM2_CM_BIAS_CR_R +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM2_CM_BIAS_Y_G_CB_B +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_CONTROL +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM2_CM_GAMCOR_LUT_INDEX +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_GAMCOR_LUT_DATA +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_LUT_CONTROL +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM2_CM_GAMCOR_RAMA_START_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_OFFSET_B +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_G +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_R +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_REGION_0_1 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_2_3 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_4_5 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_6_7 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_8_9 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_10_11 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_12_13 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_14_15 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_16_17 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_18_19 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_20_21 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_22_23 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_24_25 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_26_27 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_28_29 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_30_31 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_32_33 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_OFFSET_B +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_G +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_R +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_REGION_0_1 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_2_3 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_4_5 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_6_7 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_8_9 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_10_11 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_12_13 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_14_15 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_16_17 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_18_19 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_20_21 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_22_23 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_24_25 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_26_27 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_28_29 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_30_31 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_32_33 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM2_CM_DEALPHA +#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM2_CM_COEF_FORMAT +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM2_CM_TEST_DEBUG_INDEX +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM2_CM_TEST_DEBUG_DATA +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM2_CM_HIST_CNTL +#define CM2_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM2_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM2_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM2_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM2_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM2_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM2_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM2_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM2_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM2_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM2_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM2_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM2_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM2_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM2_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM2_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM2_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM2_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM2_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM2_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM2_CM_HIST_SCALE_SRC1 +#define CM2_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM2_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM2_CM_HIST_COEFA_SRC2 +#define CM2_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_COEFB_SRC2 +#define CM2_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_COEFC_SRC2 +#define CM2_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_SCALE_SRC3 +#define CM2_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM2_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM2_CM_HIST_BIAS_SRC1 +#define CM2_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM2_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM2_CM_HIST_BIAS_SRC2 +#define CM2_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_BIAS_SRC3 +#define CM2_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM2_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM2_CM_HIST_LOCK +#define CM2_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM2_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM2_CM_HIST_INDEX +#define CM2_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM2_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM2_CM_HIST_DATA +#define CM2_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM2_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM2_CM_HIST_STATUS +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM2_CM_HIST_INT_CONTROL +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON12_PERFCOUNTER_CNTL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_CNTL2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_STATE +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON12_PERFMON_CNTL +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON12_PERFMON_CNTL2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON12_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON12_PERFMON_CVALUE_LOW +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON12_PERFMON_HI +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFMON_LOW +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP3_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP3_DPP_CRC_VAL_R +#define DPP_TOP3_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_VAL_G +#define DPP_TOP3_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_VAL_B +#define DPP_TOP3_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_VAL_A +#define DPP_TOP3_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG3_FCNV_FP_BIAS_R +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_G +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_B +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_R +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_G +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_B +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT01 +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT23 +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG3_PRE_DEALPHA +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG3_PRE_CSC_MODE +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG3_PRE_CSC_C11_C12 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C13_C14 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C21_C22 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C23_C24 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C31_C32 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C33_C34 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C11_C12 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C13_C14 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C21_C22 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C23_C24 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C31_C32 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C33_C34 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG3_CNVC_COEF_FORMAT +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG3_PRE_DEGAM +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG3_PRE_REALPHA +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_cur_dispdec +//CM_CUR3_CURSOR0_CONTROL +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR3_CURSOR0_COLOR0 +#define CM_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR3_CURSOR0_COLOR1 +#define CM_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_MODE +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR3_CUR0_MATRIX_C11_C12_A +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C13_C14_A +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C21_C22_A +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C23_C24_A +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C31_C32_A +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C33_C34_A +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C11_C12_B +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C13_C14_B +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C21_C22_B +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C23_C24_B +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C31_C32_B +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C33_C34_B +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_COLOR +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL3_DSCL_EASF_H_MODE +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL3_DSCL_EASF_V_MODE +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL3_DSCL_SC_MODE +#define DSCL3_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL3_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL3_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL3_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL3_DSCL_SC_MATRIX_C0C1 +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL3_DSCL_SC_MATRIX_C2C3 +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_RINGEST_FORCE +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_H_BF_CNTL +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL3_DSCL_EASF_V_BF_CNTL +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL3_ISHARP_MODE +#define DSCL3_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL3_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL3_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL3_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL3_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL3_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL3_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL3_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL3_ISHARP_DELTA_CTRL +#define DSCL3_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL3_ISHARP_DELTA_INDEX +#define DSCL3_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL3_ISHARP_DELTA_DATA +#define DSCL3_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL3_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL3_ISHARP_NOISEDET_THRESHOLD +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL3_ISHARP_NOISE_GAIN_PWL +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL3_ISHARP_LBA_PWL_SEG0 +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG1 +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG2 +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG3 +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG4 +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG5 +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_POST_CSC_CONTROL +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_POST_CSC_C11_C12 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C13_C14 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C21_C22 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C23_C24 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C31_C32 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C33_C34 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C11_C12 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C13_C14 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C21_C22 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C23_C24 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C31_C32 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C33_C34 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM3_CM_BIAS_CR_R +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM3_CM_BIAS_Y_G_CB_B +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_CONTROL +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM3_CM_GAMCOR_LUT_INDEX +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_GAMCOR_LUT_DATA +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_LUT_CONTROL +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM3_CM_GAMCOR_RAMA_START_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_OFFSET_B +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_G +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_R +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_REGION_0_1 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_2_3 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_4_5 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_6_7 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_8_9 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_10_11 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_12_13 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_14_15 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_16_17 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_18_19 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_20_21 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_22_23 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_24_25 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_26_27 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_28_29 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_30_31 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_32_33 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_OFFSET_B +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_G +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_R +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_REGION_0_1 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_2_3 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_4_5 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_6_7 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_8_9 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_10_11 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_12_13 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_14_15 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_16_17 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_18_19 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_20_21 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_22_23 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_24_25 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_26_27 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_28_29 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_30_31 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_32_33 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM3_CM_DEALPHA +#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM3_CM_COEF_FORMAT +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM3_CM_TEST_DEBUG_INDEX +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM3_CM_TEST_DEBUG_DATA +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM3_CM_HIST_CNTL +#define CM3_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM3_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM3_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM3_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM3_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM3_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM3_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM3_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM3_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM3_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM3_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM3_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM3_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM3_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM3_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM3_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM3_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM3_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM3_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM3_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM3_CM_HIST_SCALE_SRC1 +#define CM3_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM3_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM3_CM_HIST_COEFA_SRC2 +#define CM3_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_COEFB_SRC2 +#define CM3_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_COEFC_SRC2 +#define CM3_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_SCALE_SRC3 +#define CM3_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM3_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM3_CM_HIST_BIAS_SRC1 +#define CM3_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM3_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM3_CM_HIST_BIAS_SRC2 +#define CM3_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_BIAS_SRC3 +#define CM3_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM3_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM3_CM_HIST_LOCK +#define CM3_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM3_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM3_CM_HIST_INDEX +#define CM3_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM3_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM3_CM_HIST_DATA +#define CM3_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM3_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM3_CM_HIST_STATUS +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM3_CM_HIST_INT_CONTROL +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON13_PERFCOUNTER_CNTL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_CNTL2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_STATE +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON13_PERFMON_CNTL +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON13_PERFMON_CNTL2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON13_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON13_PERFMON_CVALUE_LOW +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON13_PERFMON_HI +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFMON_LOW +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcoh_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX0_AUX_PHY_WAKE_STATUS +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX1_AUX_PHY_WAKE_STATUS +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_PHY_WAKE_CNTL +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX2_AUX_PHY_WAKE_STATUS +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_PHY_WAKE_CNTL +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX3_AUX_PHY_WAKE_STATUS +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_PHY_WAKE_CNTL +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX4_AUX_PHY_WAKE_STATUS +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_dpia_mux0_dispdec +//DPIA_MUX0_DPIA_MUX_CONTROL +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX0_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX0_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX0_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX0_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux1_dispdec +//DPIA_MUX1_DPIA_MUX_CONTROL +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX1_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX1_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX1_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX1_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux2_dispdec +//DPIA_MUX2_DPIA_MUX_CONTROL +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX2_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX2_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX2_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX2_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux3_dispdec +//DPIA_MUX3_DPIA_MUX_CONTROL +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX3_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX3_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX3_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX3_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux4_dispdec +//DPIA_MUX4_DPIA_MUX_CONTROL +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX4_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX4_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX4_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX4_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux5_dispdec +//DPIA_MUX5_DPIA_MUX_CONTROL +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX5_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX5_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX5_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX5_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_phy_mux0_dispdec +//PHY_MUX0_PHY_MUX_CONTROL +#define PHY_MUX0_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX0_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX0_PORT_TYPE +#define PHY_MUX0_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX0_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux1_dispdec +//PHY_MUX1_PHY_MUX_CONTROL +#define PHY_MUX1_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX1_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX1_PORT_TYPE +#define PHY_MUX1_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX1_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux2_dispdec +//PHY_MUX2_PHY_MUX_CONTROL +#define PHY_MUX2_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX2_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX2_PORT_TYPE +#define PHY_MUX2_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX2_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux3_dispdec +//PHY_MUX3_PHY_MUX_CONTROL +#define PHY_MUX3_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX3_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX3_PORT_TYPE +#define PHY_MUX3_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX3_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux4_dispdec +//PHY_MUX4_PHY_MUX_CONTROL +#define PHY_MUX4_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX4_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX4_PORT_TYPE +#define PHY_MUX4_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX4_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_dcoh_top_dispdec +//DCOH_TOP_CLOCK_CONTROL +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_G_GATE_DIS__SHIFT 0x0 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_G_GATE_DIS__SHIFT 0x8 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_R_GATE_DIS__SHIFT 0xc +#define DCOH_TOP_CLOCK_CONTROL__DCOH_FGCG_REP_DIS__SHIFT 0x10 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_G_GATE_DIS_MASK 0x00000001L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_G_GATE_DIS_MASK 0x00000100L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_R_GATE_DIS_MASK 0x00001000L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_FGCG_REP_DIS_MASK 0x00010000L +//DCOH_DCN_STATUS +#define DCOH_DCN_STATUS__DCN_ACTIVE__SHIFT 0x0 +#define DCOH_DCN_STATUS__DCN_ACTIVE_MASK 0x00000001L +//DCOH_TOP_SPARE +#define DCOH_TOP_SPARE__DCOH_TOP_SPARE__SHIFT 0x0 +#define DCOH_TOP_SPARE__DCOH_TOP_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT2_FMT_422_CONTROL +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg2_dispdec +//DPG2_DPG_CONTROL +#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG2_DPG_RAMP_CONTROL +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG2_DPG_DIMENSIONS +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_COLOUR_R_CR +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_G_Y +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_B_CB +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG2_DPG_OFFSET_SEGMENT +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_STATUS +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF2_OPPBUF_CONTROL1 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT3_FMT_422_CONTROL +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg3_dispdec +//DPG3_DPG_CONTROL +#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG3_DPG_RAMP_CONTROL +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG3_DPG_DIMENSIONS +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_COLOUR_R_CR +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_G_Y +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_B_CB +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG3_DPG_OFFSET_SEGMENT +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_STATUS +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF3_OPPBUF_CONTROL1 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT 0xe +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT 0xf +#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS__SHIFT 0x18 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK 0x00004000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK 0x00008000L +#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS_MASK 0x01000000L +//OPP_ABM_CONTROL +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT 0x0 +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +//DSCRM2_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +//DSCRM3_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON14_PERFCOUNTER_CNTL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_CNTL2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_STATE +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON14_PERFMON_CNTL +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON14_PERFMON_CNTL2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON14_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON14_PERFMON_CVALUE_LOW +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON14_PERFMON_HI +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFMON_LOW +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_UNDERFLOW_THRESHOLD +#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_WIDTH_CONTROL2 +#define ODM0_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_UNDERFLOW_THRESHOLD +#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_WIDTH_CONTROL2 +#define ODM1_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM2_OPTC_UNDERFLOW_THRESHOLD +#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM2_OPTC_DATA_FORMAT_CONTROL +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM2_OPTC_BYTES_PER_PIXEL +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM2_OPTC_WIDTH_CONTROL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM2_OPTC_WIDTH_CONTROL2 +#define ODM2_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_MEMORY_CONFIG +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM3_OPTC_UNDERFLOW_THRESHOLD +#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM3_OPTC_DATA_FORMAT_CONTROL +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM3_OPTC_BYTES_PER_PIXEL +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM3_OPTC_WIDTH_CONTROL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM3_OPTC_WIDTH_CONTROL2 +#define ODM3_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_MEMORY_CONFIG +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_COUNT_STOP_CONTROL +#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG0_OTG_V_COUNT_STOP_CONTROL2 +#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG0_OTG_DLPC_CONTROL +#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG0_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_LONG_VBLANK_STATUS +#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_R +#define OTG0_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_G +#define OTG0_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_C +#define OTG0_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_R +#define OTG0_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_DATA_G +#define OTG0_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_DATA_C +#define OTG0_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_R +#define OTG0_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_G +#define OTG0_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_C +#define OTG0_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_R +#define OTG0_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_G +#define OTG0_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_C +#define OTG0_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_AES +#define OTG0_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG0_OTG_GLOBAL_CONTROL4 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_DRR_TIMING_INT_STATUS +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG0_OTG_DRR_V_TOTAL_CHANGE +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG0_OTG_DRR_TRIGGER_WINDOW +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTOL2 +#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO1 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_PSTATE_REGISTER +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG0_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG0_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG0_OTG_ENCRYPTION +#define OTG0_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG0_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_COUNT_STOP_CONTROL +#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG1_OTG_V_COUNT_STOP_CONTROL2 +#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG1_OTG_DLPC_CONTROL +#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG1_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_LONG_VBLANK_STATUS +#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_R +#define OTG1_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_G +#define OTG1_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_C +#define OTG1_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_R +#define OTG1_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_DATA_G +#define OTG1_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_DATA_C +#define OTG1_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_R +#define OTG1_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_G +#define OTG1_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_C +#define OTG1_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_R +#define OTG1_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_G +#define OTG1_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_C +#define OTG1_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_AES +#define OTG1_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG1_OTG_GLOBAL_CONTROL4 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_DRR_TIMING_INT_STATUS +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG1_OTG_DRR_V_TOTAL_CHANGE +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG1_OTG_DRR_TRIGGER_WINDOW +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTOL2 +#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO1 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_PSTATE_REGISTER +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG1_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG1_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG1_OTG_ENCRYPTION +#define OTG1_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG1_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_COUNT_STOP_CONTROL +#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG2_OTG_V_COUNT_STOP_CONTROL2 +#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG2_OTG_DLPC_CONTROL +#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG2_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_LONG_VBLANK_STATUS +#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_R +#define OTG2_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_G +#define OTG2_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_C +#define OTG2_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_R +#define OTG2_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_DATA_G +#define OTG2_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_DATA_C +#define OTG2_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_R +#define OTG2_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_G +#define OTG2_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_C +#define OTG2_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_R +#define OTG2_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_G +#define OTG2_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_C +#define OTG2_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_AES +#define OTG2_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG2_OTG_GLOBAL_CONTROL4 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_DRR_TIMING_INT_STATUS +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG2_OTG_DRR_V_TOTAL_CHANGE +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG2_OTG_DRR_TRIGGER_WINDOW +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTOL2 +#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO1 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_PIPE_UPDATE_STATUS +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG2_OTG_PSTATE_REGISTER +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG2_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG2_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG2_OTG_ENCRYPTION +#define OTG2_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG2_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_COUNT_STOP_CONTROL +#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG3_OTG_V_COUNT_STOP_CONTROL2 +#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG3_OTG_DLPC_CONTROL +#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG3_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_LONG_VBLANK_STATUS +#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_R +#define OTG3_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_G +#define OTG3_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_C +#define OTG3_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_R +#define OTG3_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_DATA_G +#define OTG3_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_DATA_C +#define OTG3_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_R +#define OTG3_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_G +#define OTG3_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_C +#define OTG3_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_R +#define OTG3_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_G +#define OTG3_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_C +#define OTG3_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_AES +#define OTG3_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG3_OTG_GLOBAL_CONTROL4 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_DRR_TIMING_INT_STATUS +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG3_OTG_DRR_V_TOTAL_CHANGE +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG3_OTG_DRR_TRIGGER_WINDOW +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTOL2 +#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO1 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_PIPE_UPDATE_STATUS +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG3_OTG_PSTATE_REGISTER +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG3_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG3_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG3_OTG_ENCRYPTION +#define OTG3_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG3_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_DLPC_CONTROL +#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX__SHIFT 0x0 +#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX_MASK 0x00000007L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT 0xf +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK 0x00008000L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON15_PERFCOUNTER_CNTL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_CNTL2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_STATE +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON15_PERFMON_CNTL +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON15_PERFMON_CNTL2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON15_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON15_PERFMON_CVALUE_LOW +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON15_PERFMON_HI +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFMON_LOW +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x1 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x3 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x4 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x5 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x6 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000002L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000008L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000010L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000020L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000040L +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL__DPREFCLK_R_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL__DPREFCLK_G_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__SOCCLK_R_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS_MASK 0x00010000L +#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL__DPREFCLK_R_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL__DPREFCLK_G_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS_MASK 0x00800000L +#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__SOCCLK_R_GATE_DIS_MASK 0x20000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_PSP_INTERRUPT_STATUS +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_PSP_INTERRUPT_CLEAR +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L +//DIO_STATUS +#define DIO_STATUS__DIO_EN__SHIFT 0x0 +#define DIO_STATUS__DIO_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec +//DIG0_STREAM_MAPPER_CONTROL +#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG1_STREAM_MAPPER_CONTROL +#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG2_STREAM_MAPPER_CONTROL +#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG3_STREAM_MAPPER_CONTROL +#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG4_STREAM_MAPPER_CONTROL +#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON16_PERFCOUNTER_CNTL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_CNTL2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_STATE +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON16_PERFMON_CNTL +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON16_PERFMON_CNTL2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON16_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON16_PERFMON_CVALUE_LOW +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON16_PERFMON_HI +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFMON_LOW +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG0_VPG_GENERIC_PACKET_DATA +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GENERIC_STATUS +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG0_VPG_MEM_PWR +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG0_VPG_ISRC1_2_ACCESS_CTRL +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG0_VPG_ISRC1_2_DATA +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig0_apg_apg_dispdec +//APG0_APG_CONTROL +#define APG0_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG0_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG0_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG0_APG_CONTROL2 +#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG0_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG0_APG_DBG_GEN_CONTROL +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG0_APG_PACKET_CONTROL +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG0_APG_DBG_ACP +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG0_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG0_APG_DBG_AUDIO_INFO +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG0_APG_DBG_60958_0 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG0_APG_DBG_60958_1 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG0_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG0_APG_DBG_60958_2 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG0_APG_AUDIO_CRC_CONTROL +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG0_APG_AUDIO_CRC_CONTROL2 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG0_APG_AUDIO_CRC_RESULT +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG0_APG_DBG_RAMP_CONTROL0 +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG0_APG_DBG_RAMP_CONTROL1 +#define APG0_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG0_APG_DBG_RAMP_CONTROL2 +#define APG0_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG0_APG_DBG_RAMP_CONTROL3 +#define APG0_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG0_APG_STATUS +#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG0_APG_STATUS2 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG0_APG_DBG_AUDIO_DTO_CNTL +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG0_APG_MEM_PWR +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG0_APG_SPARE +#define APG0_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG0_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +//DME0_DME_CONTROL +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME0_DME_MEMORY_CONTROL +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG0_DIG_FE_CLK_CNTL +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG0_DIG_FE_EN_CNTL +#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_CTRL0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG0_DIG_FIFO_CTRL1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_DIG_FE_AUDIO_CNTL +#define DIG0_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG0_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG0_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG0_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG0_DIG_BE_CLK_CNTL +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT 0x6 +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON__SHIFT 0xc +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK 0x00000040L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON_MASK 0x00001000L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP0_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP0_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP0_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_DPHY_INTERNAL_CTRL +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_CONTROL0 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CONTROL1 +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_RESULT0 +#define DP0_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_RESULT1 +#define DP0_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_RESULT2 +#define DP0_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_RESULT3 +#define DP0_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_STATUS +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_TU_CNTL +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP0_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP0_DP_PIXEL_FORMAT_DB_CNTL +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_HBLANK_CONTROL +#define DP0_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP0_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_STEER_FIFO_CNTL +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP0_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP0_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP8_CNTL +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP9_CNTL +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP10_CNTL +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP11_CNTL +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP_EN_DB_STATUS +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP0_DP_AUXLESS_ALPM_CNTL1 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP0_DP_AUXLESS_ALPM_CNTL2 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP0_DP_AUXLESS_ALPM_CNTL3 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_AUXLESS_ALPM_CNTL4 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP0_DP_AUXLESS_ALPM_CNTL5 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP0_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP0_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP0_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP0_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG1_VPG_GENERIC_PACKET_DATA +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GENERIC_STATUS +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG1_VPG_MEM_PWR +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG1_VPG_ISRC1_2_ACCESS_CTRL +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG1_VPG_ISRC1_2_DATA +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig1_apg_apg_dispdec +//APG1_APG_CONTROL +#define APG1_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG1_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG1_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG1_APG_CONTROL2 +#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG1_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG1_APG_DBG_GEN_CONTROL +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG1_APG_PACKET_CONTROL +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG1_APG_DBG_ACP +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG1_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG1_APG_DBG_AUDIO_INFO +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG1_APG_DBG_60958_0 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG1_APG_DBG_60958_1 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG1_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG1_APG_DBG_60958_2 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG1_APG_AUDIO_CRC_CONTROL +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG1_APG_AUDIO_CRC_CONTROL2 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG1_APG_AUDIO_CRC_RESULT +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG1_APG_DBG_RAMP_CONTROL0 +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG1_APG_DBG_RAMP_CONTROL1 +#define APG1_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG1_APG_DBG_RAMP_CONTROL2 +#define APG1_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG1_APG_DBG_RAMP_CONTROL3 +#define APG1_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG1_APG_STATUS +#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG1_APG_STATUS2 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG1_APG_DBG_AUDIO_DTO_CNTL +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG1_APG_MEM_PWR +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG1_APG_SPARE +#define APG1_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG1_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +//DME1_DME_CONTROL +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME1_DME_MEMORY_CONTROL +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG1_DIG_FE_CLK_CNTL +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG1_DIG_FE_EN_CNTL +#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_CTRL0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG1_DIG_FIFO_CTRL1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_DIG_FE_AUDIO_CNTL +#define DIG1_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG1_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG1_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG1_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG1_DIG_BE_CLK_CNTL +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP1_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP1_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP1_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_DPHY_INTERNAL_CTRL +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_CONTROL0 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CONTROL1 +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_RESULT0 +#define DP1_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_RESULT1 +#define DP1_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_RESULT2 +#define DP1_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_RESULT3 +#define DP1_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_STATUS +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_TU_CNTL +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP1_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP1_DP_PIXEL_FORMAT_DB_CNTL +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_HBLANK_CONTROL +#define DP1_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP1_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_STEER_FIFO_CNTL +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP1_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP1_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP8_CNTL +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP9_CNTL +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP10_CNTL +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP11_CNTL +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP_EN_DB_STATUS +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP1_DP_AUXLESS_ALPM_CNTL1 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP1_DP_AUXLESS_ALPM_CNTL2 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP1_DP_AUXLESS_ALPM_CNTL3 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_AUXLESS_ALPM_CNTL4 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP1_DP_AUXLESS_ALPM_CNTL5 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP1_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP1_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP1_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP1_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig2_apg_apg_dispdec +//APG2_APG_CONTROL +#define APG2_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG2_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG2_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG2_APG_CONTROL2 +#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG2_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG2_APG_DBG_GEN_CONTROL +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG2_APG_PACKET_CONTROL +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG2_APG_DBG_ACP +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG2_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG2_APG_DBG_AUDIO_INFO +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG2_APG_DBG_60958_0 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG2_APG_DBG_60958_1 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG2_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG2_APG_DBG_60958_2 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG2_APG_AUDIO_CRC_CONTROL +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG2_APG_AUDIO_CRC_CONTROL2 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG2_APG_AUDIO_CRC_RESULT +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG2_APG_DBG_RAMP_CONTROL0 +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG2_APG_DBG_RAMP_CONTROL1 +#define APG2_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG2_APG_DBG_RAMP_CONTROL2 +#define APG2_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG2_APG_DBG_RAMP_CONTROL3 +#define APG2_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG2_APG_STATUS +#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG2_APG_STATUS2 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG2_APG_DBG_AUDIO_DTO_CNTL +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG2_APG_MEM_PWR +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG2_APG_SPARE +#define APG2_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG2_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG2_DIG_FE_CLK_CNTL +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG2_DIG_FE_EN_CNTL +#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_CTRL0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG2_DIG_FIFO_CTRL1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_METADATA_PACKET_CONTROL +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_DIG_FE_AUDIO_CNTL +#define DIG2_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG2_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG2_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG2_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG2_DIG_BE_CLK_CNTL +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_SYNC_DCBALANCE_CHAR +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP2_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP2_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP2_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_DPHY_INTERNAL_CTRL +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_CONTROL0 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CONTROL1 +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_RESULT0 +#define DP2_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_RESULT1 +#define DP2_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_RESULT2 +#define DP2_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_RESULT3 +#define DP2_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_STATUS +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_TU_CNTL +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP2_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP2_DP_PIXEL_FORMAT_DB_CNTL +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_HBLANK_CONTROL +#define DP2_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP2_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_STEER_FIFO_CNTL +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_METADATA_TRANSMISSION +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP2_DP_ALPM_CNTL +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP2_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP2_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP8_CNTL +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP9_CNTL +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP10_CNTL +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP11_CNTL +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP_EN_DB_STATUS +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP2_DP_AUXLESS_ALPM_CNTL1 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP2_DP_AUXLESS_ALPM_CNTL2 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP2_DP_AUXLESS_ALPM_CNTL3 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_AUXLESS_ALPM_CNTL4 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP2_DP_AUXLESS_ALPM_CNTL5 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP2_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP2_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP2_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP2_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG3_VPG_GENERIC_PACKET_DATA +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GENERIC_STATUS +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG3_VPG_MEM_PWR +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG3_VPG_ISRC1_2_ACCESS_CTRL +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG3_VPG_ISRC1_2_DATA +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig3_apg_apg_dispdec +//APG3_APG_CONTROL +#define APG3_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG3_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG3_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG3_APG_CONTROL2 +#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG3_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG3_APG_DBG_GEN_CONTROL +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG3_APG_PACKET_CONTROL +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG3_APG_DBG_ACP +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG3_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG3_APG_DBG_AUDIO_INFO +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG3_APG_DBG_60958_0 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG3_APG_DBG_60958_1 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG3_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG3_APG_DBG_60958_2 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG3_APG_AUDIO_CRC_CONTROL +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG3_APG_AUDIO_CRC_CONTROL2 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG3_APG_AUDIO_CRC_RESULT +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG3_APG_DBG_RAMP_CONTROL0 +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG3_APG_DBG_RAMP_CONTROL1 +#define APG3_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG3_APG_DBG_RAMP_CONTROL2 +#define APG3_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG3_APG_DBG_RAMP_CONTROL3 +#define APG3_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG3_APG_STATUS +#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG3_APG_STATUS2 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG3_APG_DBG_AUDIO_DTO_CNTL +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG3_APG_MEM_PWR +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG3_APG_SPARE +#define APG3_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG3_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +//DME3_DME_CONTROL +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME3_DME_MEMORY_CONTROL +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG3_DIG_FE_CLK_CNTL +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG3_DIG_FE_EN_CNTL +#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_CTRL0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG3_DIG_FIFO_CTRL1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_METADATA_PACKET_CONTROL +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_DIG_FE_AUDIO_CNTL +#define DIG3_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG3_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG3_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG3_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG3_DIG_BE_CLK_CNTL +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_SYNC_DCBALANCE_CHAR +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP3_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP3_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP3_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_DPHY_INTERNAL_CTRL +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_CONTROL0 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CONTROL1 +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_RESULT0 +#define DP3_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_RESULT1 +#define DP3_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_RESULT2 +#define DP3_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_RESULT3 +#define DP3_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_STATUS +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_TU_CNTL +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP3_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP3_DP_PIXEL_FORMAT_DB_CNTL +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_HBLANK_CONTROL +#define DP3_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP3_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_STEER_FIFO_CNTL +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_METADATA_TRANSMISSION +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP3_DP_ALPM_CNTL +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP3_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP3_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP8_CNTL +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP9_CNTL +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP10_CNTL +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP11_CNTL +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP_EN_DB_STATUS +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP3_DP_AUXLESS_ALPM_CNTL1 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP3_DP_AUXLESS_ALPM_CNTL2 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP3_DP_AUXLESS_ALPM_CNTL3 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_AUXLESS_ALPM_CNTL4 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP3_DP_AUXLESS_ALPM_CNTL5 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP3_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP3_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP3_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP3_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG4_VPG_GENERIC_PACKET_DATA +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GENERIC_STATUS +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG4_VPG_MEM_PWR +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG4_VPG_ISRC1_2_ACCESS_CTRL +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG4_VPG_ISRC1_2_DATA +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig4_apg_apg_dispdec +//APG4_APG_DBG_GEN_CONTROL +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG4_APG_MEM_PWR +#define APG4_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG4_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG4_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG4_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG4_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG4_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG4_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG4_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +//DME4_DME_CONTROL +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME4_DME_MEMORY_CONTROL +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG4_DIG_FE_CLK_CNTL +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG4_DIG_FE_EN_CNTL +#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_CTRL0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG4_DIG_FIFO_CTRL1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_METADATA_PACKET_CONTROL +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_DIG_FE_AUDIO_CNTL +#define DIG4_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG4_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG4_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG4_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG4_DIG_BE_CLK_CNTL +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_SYNC_DCBALANCE_CHAR +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP4_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP4_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP4_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_DPHY_INTERNAL_CTRL +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_CONTROL0 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CONTROL1 +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_RESULT0 +#define DP4_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_RESULT1 +#define DP4_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_RESULT2 +#define DP4_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_RESULT3 +#define DP4_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_STATUS +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_TU_CNTL +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP4_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP4_DP_PIXEL_FORMAT_DB_CNTL +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_HBLANK_CONTROL +#define DP4_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP4_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_STEER_FIFO_CNTL +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_METADATA_TRANSMISSION +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP4_DP_ALPM_CNTL +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP4_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP4_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP8_CNTL +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP9_CNTL +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP10_CNTL +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP11_CNTL +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP_EN_DB_STATUS +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP4_DP_AUXLESS_ALPM_CNTL1 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP4_DP_AUXLESS_ALPM_CNTL2 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP4_DP_AUXLESS_ALPM_CNTL3 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_AUXLESS_ALPM_CNTL4 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP4_DP_AUXLESS_ALPM_CNTL5 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP4_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP4_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP4_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP4_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP0_DSC_SPARE_DEBUG +#define DSC_TOP0_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP0_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC0_DSCC_CONFIG2 +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL0 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC0_DSCC_INTERRUPT_CONTROL1 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC0_DSCC_INTERRUPT_STATUS0 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC0_DSCC_INTERRUPT_STATUS1 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL0 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC0_DSCC_MEM_POWER_CONTROL1 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC0_DSCC_TEST_DEBUG_INDEX0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_INDEX1 +#define DSCC0_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_INDEX2 +#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_INDEX3 +#define DSCC0_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC0_DSCC_TEST_DEBUG_DATA0 +#define DSCC0_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC0_DSCC_TEST_DEBUG_DATA1 +#define DSCC0_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC0_DSCC_TEST_DEBUG_DATA2 +#define DSCC0_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC0_DSCC_TEST_DEBUG_DATA3 +#define DSCC0_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON17_PERFCOUNTER_CNTL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_CNTL2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_STATE +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON17_PERFMON_CNTL +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON17_PERFMON_CNTL2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON17_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON17_PERFMON_CVALUE_LOW +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON17_PERFMON_HI +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFMON_LOW +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP1_DSC_DEBUG_CONTROL +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP1_DSC_SPARE_DEBUG +#define DSC_TOP1_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP1_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP1_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC1_DSCC_CONFIG2 +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL0 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC1_DSCC_INTERRUPT_CONTROL1 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC1_DSCC_INTERRUPT_STATUS0 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC1_DSCC_INTERRUPT_STATUS1 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL0 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC1_DSCC_MEM_POWER_CONTROL1 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC1_DSCC_TEST_DEBUG_INDEX0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_INDEX1 +#define DSCC1_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_INDEX2 +#define DSCC1_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_INDEX3 +#define DSCC1_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC1_DSCC_TEST_DEBUG_DATA0 +#define DSCC1_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC1_DSCC_TEST_DEBUG_DATA1 +#define DSCC1_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC1_DSCC_TEST_DEBUG_DATA2 +#define DSCC1_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC1_DSCC_TEST_DEBUG_DATA3 +#define DSCC1_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON18_PERFCOUNTER_CNTL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_CNTL2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_STATE +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON18_PERFMON_CNTL +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON18_PERFMON_CNTL2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON18_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON18_PERFMON_CVALUE_LOW +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON18_PERFMON_HI +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFMON_LOW +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +//DSC_TOP2_DSC_TOP_CONTROL +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP2_DSC_DEBUG_CONTROL +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP2_DSC_SPARE_DEBUG +#define DSC_TOP2_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP2_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP2_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +//DSCCIF2_DSCCIF_CONFIG0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +//DSCC2_DSCC_CONFIG0 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC2_DSCC_CONFIG1 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC2_DSCC_CONFIG2 +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC2_DSCC_STATUS +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC2_DSCC_INTERRUPT_CONTROL0 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC2_DSCC_INTERRUPT_CONTROL1 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC2_DSCC_INTERRUPT_STATUS0 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC2_DSCC_INTERRUPT_STATUS1 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC2_DSCC_PPS_CONFIG0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG1 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG2 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG3 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG4 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG5 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG6 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC2_DSCC_PPS_CONFIG7 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG8 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG9 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG11 +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG12 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG13 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG14 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG15 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG16 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG17 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG18 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG19 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG20 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG21 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG22 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC2_DSCC_MEM_POWER_CONTROL0 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC2_DSCC_MEM_POWER_CONTROL1 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_MAX_ABS_ERROR0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC2_DSCC_MAX_ABS_ERROR1 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC2_DSCC_TEST_DEBUG_INDEX0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_INDEX1 +#define DSCC2_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_INDEX2 +#define DSCC2_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_INDEX3 +#define DSCC2_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC2_DSCC_TEST_DEBUG_DATA0 +#define DSCC2_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC2_DSCC_TEST_DEBUG_DATA1 +#define DSCC2_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC2_DSCC_TEST_DEBUG_DATA2 +#define DSCC2_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC2_DSCC_TEST_DEBUG_DATA3 +#define DSCC2_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON19_PERFCOUNTER_CNTL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_CNTL2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_STATE +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON19_PERFMON_CNTL +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON19_PERFMON_CNTL2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON19_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON19_PERFMON_CVALUE_LOW +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON19_PERFMON_HI +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFMON_LOW +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +//DSC_TOP3_DSC_TOP_CONTROL +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP3_DSC_DEBUG_CONTROL +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP3_DSC_SPARE_DEBUG +#define DSC_TOP3_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP3_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP3_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +//DSCCIF3_DSCCIF_CONFIG0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +//DSCC3_DSCC_CONFIG0 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC3_DSCC_CONFIG1 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC3_DSCC_CONFIG2 +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC3_DSCC_STATUS +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC3_DSCC_INTERRUPT_CONTROL0 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC3_DSCC_INTERRUPT_CONTROL1 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC3_DSCC_INTERRUPT_STATUS0 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC3_DSCC_INTERRUPT_STATUS1 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC3_DSCC_PPS_CONFIG0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG1 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG2 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG3 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG4 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG5 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG6 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC3_DSCC_PPS_CONFIG7 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG8 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG9 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG11 +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG12 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG13 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG14 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG15 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG16 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG17 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG18 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG19 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG20 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG21 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG22 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC3_DSCC_MEM_POWER_CONTROL0 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC3_DSCC_MEM_POWER_CONTROL1 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_MAX_ABS_ERROR0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC3_DSCC_MAX_ABS_ERROR1 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC3_DSCC_TEST_DEBUG_INDEX0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_INDEX1 +#define DSCC3_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_INDEX2 +#define DSCC3_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_INDEX3 +#define DSCC3_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC3_DSCC_TEST_DEBUG_DATA0 +#define DSCC3_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC3_DSCC_TEST_DEBUG_DATA1 +#define DSCC3_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC3_DSCC_TEST_DEBUG_DATA2 +#define DSCC3_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC3_DSCC_TEST_DEBUG_DATA3 +#define DSCC3_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON20_PERFCOUNTER_CNTL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_CNTL2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_STATE +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON20_PERFMON_CNTL +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON20_PERFMON_CNTL2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON20_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON20_PERFMON_CVALUE_LOW +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON20_PERFMON_HI +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFMON_LOW +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +//DWB_ENABLE_CLK_CTRL +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT 0x0 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT 0x4 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT 0x8 +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT 0xc +#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS__SHIFT 0x18 +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK 0x00000001L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK 0x00000010L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK 0x00000100L +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK 0x00003000L +#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS_MASK 0x01000000L +//DWB_MEM_PWR_CTRL +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT 0x8 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT 0xa +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT 0xc +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT 0x10 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT 0x12 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK 0x00000300L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK 0x00000400L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK 0x00003000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK 0x00030000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK 0x00040000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK 0x00300000L +//FC_MODE_CTRL +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT 0x0 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT 0x4 +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT 0x8 +#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT 0xc +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT 0x10 +#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT 0x14 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1f +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK 0x00000001L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK 0x00000030L +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK 0x00000100L +#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK 0x00003000L +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK 0x00010000L +#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK 0x00100000L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK 0x80000000L +//FC_FLOW_CTRL +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT 0x0 +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK 0x00000FFFL +//FC_WINDOW_START +#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT 0x0 +#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT 0x10 +#define FC_WINDOW_START__FC_WINDOW_START_X_MASK 0x00001FFFL +#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK 0x1FFF0000L +//FC_WINDOW_SIZE +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT 0x0 +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT 0x10 +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK 0x00000FFFL +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK 0x0FFF0000L +//FC_SOURCE_SIZE +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT 0x0 +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT 0x10 +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK 0x00007FFFL +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK 0x7FFF0000L +//DWB_UPDATE_CTRL +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT 0x0 +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT 0x4 +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK 0x00000001L +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK 0x00000010L +//DWB_CRC_CTRL +#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT 0x0 +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT 0x4 +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT 0x8 +#define DWB_CRC_CTRL__DWB_CRC_EN_MASK 0x00000001L +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK 0x00000010L +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK 0x00000300L +//DWB_CRC_MASK_R_G +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK 0xFFFF0000L +//DWB_CRC_MASK_B_A +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK 0xFFFF0000L +//DWB_CRC_VAL_R_G +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT 0x0 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT 0x10 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK 0x0000FFFFL +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK 0xFFFF0000L +//DWB_CRC_VAL_B_A +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT 0x0 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT 0x10 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK 0x0000FFFFL +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK 0xFFFF0000L +//DWB_OUT_CTRL +#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT 0x0 +#define DWB_OUT_CTRL__OUT_DENORM__SHIFT 0x4 +#define DWB_OUT_CTRL__OUT_MAX__SHIFT 0x8 +#define DWB_OUT_CTRL__OUT_MIN__SHIFT 0x14 +#define DWB_OUT_CTRL__OUT_FORMAT_MASK 0x00000003L +#define DWB_OUT_CTRL__OUT_DENORM_MASK 0x00000030L +#define DWB_OUT_CTRL__OUT_MAX_MASK 0x0003FF00L +#define DWB_OUT_CTRL__OUT_MIN_MASK 0x3FF00000L +//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//DWB_MMHUBBUB_BACKPRESSURE_CNT +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK 0x0000FFFFL +//DWB_HOST_READ_CONTROL +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//DWB_OVERFLOW_STATUS +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT 0xc +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//DWB_OVERFLOW_COUNTER +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT 0x0 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT 0x4 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT 0x10 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK 0x00000003L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK 0x0000FFF0L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK 0x0FFF0000L +//DWB_SOFT_RESET +#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT 0x0 +#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK 0x00000001L +//DWB_DEBUG_CTRL +#define DWB_DEBUG_CTRL__DWB_DEBUG_EN__SHIFT 0x0 +#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL__SHIFT 0x6 +#define DWB_DEBUG_CTRL__DWB_DEBUG_EN_MASK 0x00000001L +#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL_MASK 0x000000C0L +//DWB_DEBUG +#define DWB_DEBUG__DWB_DEBUG__SHIFT 0x0 +#define DWB_DEBUG__DWB_DEBUG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON21_PERFCOUNTER_CNTL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_CNTL2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_STATE +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON21_PERFMON_CNTL +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON21_PERFMON_CNTL2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON21_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON21_PERFMON_CVALUE_LOW +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON21_PERFMON_HI +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFMON_LOW +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +//DWB_HDR_MULT_COEF +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT 0x0 +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK 0x0007FFFFL +//DWB_GAMUT_REMAP_MODE +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT 0x0 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x18 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK 0x00000003L +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK 0x03000000L +//DWB_GAMUT_REMAP_COEF_FORMAT +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//DWB_GAMUT_REMAPA_C11_C12 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C13_C14 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C21_C22 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C23_C24 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C31_C32 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C33_C34 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C11_C12 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C13_C14 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C21_C22 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C23_C24 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C31_C32 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C33_C34 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK 0xFFFF0000L +//DWB_OGAM_CONTROL +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT 0x0 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT 0x4 +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT 0x8 +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT 0x18 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT 0x1c +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK 0x00000003L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK 0x00000010L +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK 0x00000100L +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK 0x03000000L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK 0x10000000L +//DWB_OGAM_LUT_INDEX +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT 0x0 +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK 0x000001FFL +//DWB_OGAM_LUT_DATA +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT 0x0 +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK 0x0003FFFFL +//DWB_OGAM_LUT_CONTROL +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x4 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT 0x8 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT 0xc +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT 0x10 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000030L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK 0x00000100L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK 0x00001000L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK 0x00010000L +//DWB_OGAM_RAMA_START_CNTL_B +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_G +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_R +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_BASE_CNTL_B +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_G +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_R +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL1_B +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_B +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_G +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_G +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_R +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_R +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_OFFSET_B +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_G +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_R +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_REGION_0_1 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_2_3 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_4_5 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_6_7 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_8_9 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_10_11 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_12_13 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_14_15 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_16_17 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_18_19 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_20_21 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_22_23 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_24_25 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_26_27 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_28_29 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_30_31 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_32_33 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_START_CNTL_B +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_G +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_R +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_BASE_CNTL_B +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_G +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_R +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL1_B +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_B +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_G +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_G +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_R +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_R +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_OFFSET_B +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_G +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_R +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_REGION_0_1 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_2_3 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_4_5 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_6_7 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_8_9 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_10_11 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_12_13 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_14_15 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_16_17 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_18_19 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_20_21 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_22_23 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_24_25 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_26_27 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_28_29 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_30_31 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_32_33 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +//DCHVM_CTRL0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT 0x0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK 0x00000001L +//DCHVM_CTRL1 +#define DCHVM_CTRL1__DUMMY1__SHIFT 0x0 +#define DCHVM_CTRL1__DUMMY1_MASK 0xFFFFFFFFL +//DCHVM_CLK_CTRL +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT 0x1 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT 0x4 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT 0x5 +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT 0x8 +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT 0xa +#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS__SHIFT 0xc +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKCTL_MODE__SHIFT 0xf +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK 0x00000002L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK 0x00000010L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK 0x00000020L +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK 0x00000300L +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK 0x00000C00L +#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS_MASK 0x00001000L +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKCTL_MODE_MASK 0x00008000L +//DCHVM_MEM_CTRL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT 0x0 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT 0x2 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT 0x4 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK 0x00000001L +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK 0x0000000CL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK 0x00000030L +//DCHVM_RIOMMU_CTRL0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT 0x0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT 0x1 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK 0x00000001L +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK 0x00000002L +//DCHVM_RIOMMU_STAT0 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT 0x0 +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT 0x1 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK 0x00000001L +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +//APG5_APG_DBG_GEN_CONTROL +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG5_APG_MEM_PWR +#define APG5_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG5_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG5_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG5_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG5_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG5_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG5_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG5_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC0_DP_LINK_ENC_SPARE +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +//APG6_APG_DBG_GEN_CONTROL +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG6_APG_MEM_PWR +#define APG6_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG6_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG6_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG6_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG6_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG6_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG6_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG6_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +//DME6_DME_CONTROL +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME6_DME_MEMORY_CONTROL +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG6_VPG_GENERIC_PACKET_DATA +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GENERIC_STATUS +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG6_VPG_MEM_PWR +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG6_VPG_ISRC1_2_ACCESS_CTRL +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG6_VPG_ISRC1_2_DATA +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC1_DP_LINK_ENC_SPARE +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +//APG7_APG_DBG_GEN_CONTROL +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG7_APG_MEM_PWR +#define APG7_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG7_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG7_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG7_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG7_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG7_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG7_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG7_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +//DME7_DME_CONTROL +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME7_DME_MEMORY_CONTROL +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG7_VPG_GENERIC_PACKET_DATA +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GENERIC_STATUS +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG7_VPG_MEM_PWR +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG7_VPG_ISRC1_2_ACCESS_CTRL +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG7_VPG_ISRC1_2_DATA +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc2_dispdec +//DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC2_DP_LINK_ENC_SPARE +#define DP_LINK_ENC2_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym322_dispdec +//DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +//APG8_APG_DBG_GEN_CONTROL +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG8_APG_MEM_PWR +#define APG8_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG8_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG8_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG8_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG8_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG8_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG8_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG8_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +//DME8_DME_CONTROL +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME8_DME_MEMORY_CONTROL +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG8_VPG_GENERIC_PACKET_DATA +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GENERIC_STATUS +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG8_VPG_MEM_PWR +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG8_VPG_ISRC1_2_ACCESS_CTRL +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG8_VPG_ISRC1_2_DATA +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc3_dispdec +//DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC3_DP_LINK_ENC_SPARE +#define DP_LINK_ENC3_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym323_dispdec +//DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC0_MPCC_CONTROL2 +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC1_MPCC_CONTROL2 +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC2_MPCC_CONTROL2 +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC2_MPCC_TOP_GAIN +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_INSIDE +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_OUTSIDE +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_MEM_PWR_CTRL +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC3_MPCC_CONTROL2 +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC3_MPCC_TOP_GAIN +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_INSIDE +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_OUTSIDE +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_MEM_PWR_CTRL +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +//MPCC_OGAM2_MPCC_OGAM_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM2_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +//MPCC_OGAM3_MPCC_OGAM_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM3_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT2_DENORM_CONTROL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT2_DENORM_CLAMP_G_Y +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT2_DENORM_CLAMP_B_CB +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT3_DENORM_CONTROL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT3_DENORM_CLAMP_G_Y +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT3_DENORM_CLAMP_B_CB +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_MODE +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT2_CSC_C11_C12_A +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_A +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_A +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_A +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_A +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_A +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C11_C12_B +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_B +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_B +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_B +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_B +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_B +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_MODE +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT3_CSC_C11_C12_A +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_A +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_A +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_A +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_A +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_A +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C11_C12_B +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_B +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_B +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_B +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_B +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_B +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OCSC_TEST_DEBUG_INDEX +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MPC_OCSC_TEST_DEBUG_DATA +#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA__SHIFT 0x0 +#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpc_rmcm0_dispdec +//MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_3DLUT_MODE +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE_MASK 0x00000030L +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMCM0_MPC_RMCM_3DLUT_INDEX +#define MPC_RMCM0_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX_MASK 0x00003FFFL +//MPC_RMCM0_MPC_RMCM_3DLUT_DATA +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +//MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L +//MPC_RMCM0_MPC_RMCM_CNTL +#define MPC_RMCM0_MPC_RMCM_CNTL__MPC_RMCM_CNTL__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_CNTL__MPC_RMCM_CNTL_MASK 0x0000000FL +//MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA__MPC_RMCM_TEST_DEBUG_DATA__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA__MPC_RMCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpc_rmcm1_dispdec +//MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_3DLUT_MODE +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE_MASK 0x00000030L +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMCM1_MPC_RMCM_3DLUT_INDEX +#define MPC_RMCM1_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX_MASK 0x00003FFFL +//MPC_RMCM1_MPC_RMCM_3DLUT_DATA +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +//MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L +//MPC_RMCM1_MPC_RMCM_CNTL +#define MPC_RMCM1_MPC_RMCM_CNTL__MPC_RMCM_CNTL__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_CNTL__MPC_RMCM_CNTL_MASK 0x0000000FL + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON22_PERFCOUNTER_CNTL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_CNTL2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_STATE +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON22_PERFMON_CNTL +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON22_PERFMON_CNTL2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON22_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON22_PERFMON_CVALUE_LOW +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON22_PERFMON_HI +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFMON_LOW +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec +//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec +//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec +//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec +//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE0_GATE_DISABLE__SHIFT 0x0 +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE1_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE2_GATE_DISABLE__SHIFT 0x2 +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE3_GATE_DISABLE__SHIFT 0x3 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x8 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0xc +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE0_GATE_DISABLE_MASK 0x00000001L +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE1_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE2_GATE_DISABLE_MASK 0x00000004L +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE3_GATE_DISABLE_MASK 0x00000008L +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000100L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x0000F000L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT 0x8 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK 0x00000300L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_A +#define MPC_CRC_RESULT_A__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_A__MPC_CRC_RESULT_A_MASK 0xFFFFFFFFL +//MPC_CRC_RESULT_R +#define MPC_CRC_RESULT_R__MPC_CRC_RESULT_R__SHIFT 0x0 +#define MPC_CRC_RESULT_R__MPC_CRC_RESULT_R_MASK 0xFFFFFFFFL +//MPC_CRC_RESULT_G +#define MPC_CRC_RESULT_G__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_G__MPC_CRC_RESULT_G_MASK 0xFFFFFFFFL +//MPC_CRC_RESULT_B +#define MPC_CRC_RESULT_B__MPC_CRC_RESULT_B__SHIFT 0x0 +#define MPC_CRC_RESULT_B__MPC_CRC_RESULT_B_MASK 0xFFFFFFFFL +//MPC_PERFMON_EVENT_CTRL +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_DPP_PENDING_STATUS +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x2 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x4 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x5 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0x6 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0x8 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0xa +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0xc +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0xd +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0xe +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000004L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000010L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000020L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000040L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00000100L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00000400L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00001000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00002000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00004000L +//MPC_PENDING_STATUS_MISC +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x3 +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0xa +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0xb +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000008L +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00000400L +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00000800L +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK 0x00010000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET2 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET2 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET2 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET3 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET3 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET3 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//HUBP0_3DLUT_FL_CONFIG +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP0_3DLUT_FL_BIAS_SCALE +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//HUBP1_3DLUT_FL_CONFIG +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP1_3DLUT_FL_BIAS_SCALE +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//HUBP2_3DLUT_FL_CONFIG +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP2_3DLUT_FL_BIAS_SCALE +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//HUBP3_3DLUT_FL_CONFIG +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP3_3DLUT_FL_BIAS_SCALE +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//MPC_DWB0_MUX +#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT 0x0 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT 0x4 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK 0x0000000FL +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK 0x000000F0L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xd +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_HDMISTREAMCLK_MASK 0x00002000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00001000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x6 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000003FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000040L +//HDMI_STREAM_ENC_AUDIO_CONTROL +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_ACTIVE_AVMUTE__SHIFT 0x8 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_ACTIVE_AVMUTE_MASK 0x00000100L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_ENCRYPTION_CONTROL +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_apg_apg_dispdec +//APG9_APG_DBG_GEN_CONTROL +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG9_APG_MEM_PWR +#define APG9_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG9_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG9_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG9_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG9_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG9_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG9_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG9_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG9_VPG_GENERIC_PACKET_DATA +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GENERIC_STATUS +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG9_VPG_MEM_PWR +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG9_VPG_ISRC1_2_ACCESS_CTRL +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG9_VPG_ISRC1_2_DATA +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME9_DME_CONTROL +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME9_DME_MEMORY_CONTROL +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT 0x11 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT 0x12 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT 0x13 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT 0x14 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT 0x15 +#define HPO_TOP_CLOCK_CONTROL__HPO_FGCG_REP_DIS__SHIFT 0x17 +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x18 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK 0x00010000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK 0x00020000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK 0x00040000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK 0x00080000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK 0x00100000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK 0x00200000L +#define HPO_TOP_CLOCK_CONTROL__HPO_FGCG_REP_DIS_MASK 0x00800000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0xFF000000L +//HPO_TOP_HW_CONTROL +#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT 0x0 +#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +//DP_STREAM_MAPPER_CONTROL0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL1 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL2 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL3 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON23_PERFCOUNTER_CNTL +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFCOUNTER_CNTL2 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFCOUNTER_STATE +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON23_PERFMON_CNTL +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON23_PERFMON_CNTL2 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON23_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON23_PERFMON_CVALUE_LOW +#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON23_PERFMON_HI +#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFMON_LOW +#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM0_DC_ABM1_ACE_PWL_CNTL +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_INDEX +#define ABM0_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM0_DC_ABM1_HG_RESULT_DATA +#define ABM0_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM1_DC_ABM1_ACE_PWL_CNTL +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_INDEX +#define ABM1_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM1_DC_ABM1_HG_RESULT_DATA +#define ABM1_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm2_dispdec +//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_USER_LEVEL +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_TARGET_ABM_LEVEL +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_ABM_CNTL +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM2_DC_ABM1_CNTL +#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM2_DC_ABM1_IPCSC_COEFF_SEL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM2_DC_ABM1_ACE_PWL_CNTL +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM2_DC_ABM1_ACE_CNTL_MISC +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM2_DC_ABM1_HG_MISC_CTRL +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM2_DC_ABM1_LS_SUM_OF_LUMA +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM2_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM2_DC_ABM1_LS_PIXEL_COUNT +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_HG_SAMPLE_RATE +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM2_DC_ABM1_LS_SAMPLE_RATE +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_INDEX +#define ABM2_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM2_DC_ABM1_HG_RESULT_DATA +#define ABM2_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_BL_MASTER_LOCK +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm3_dispdec +//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_USER_LEVEL +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_TARGET_ABM_LEVEL +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_ABM_CNTL +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM3_DC_ABM1_CNTL +#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM3_DC_ABM1_IPCSC_COEFF_SEL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM3_DC_ABM1_ACE_PWL_CNTL +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM3_DC_ABM1_ACE_CNTL_MISC +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM3_DC_ABM1_HG_MISC_CTRL +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM3_DC_ABM1_LS_SUM_OF_LUMA +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM3_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM3_DC_ABM1_LS_PIXEL_COUNT +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_HG_SAMPLE_RATE +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM3_DC_ABM1_LS_SAMPLE_RATE +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_INDEX +#define ABM3_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM3_DC_ABM1_HG_RESULT_DATA +#define ABM3_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_BL_MASTER_LOCK +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dpia_dpia_mu0_dpiadec +//DPIA_MU_CLOCK_CTRL +#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL__DPIA_DPIASYMCLK_GATE_DIS__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_G_GATE_DIS__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_R_GATE_DIS__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS__SHIFT 0xb +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS__SHIFT 0xc +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS__SHIFT 0xd +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS__SHIFT 0xe +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL__SHIFT 0x18 +#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL__DPIA_DPIASYMCLK_GATE_DIS_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_G_GATE_DIS_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_R_GATE_DIS_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS_MASK 0x00000800L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS_MASK 0x00001000L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS_MASK 0x00002000L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS_MASK 0x00004000L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL_MASK 0xFF000000L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT3 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_TPI_STATUS_DPIA_PORT0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_STATUS_DPIA_PORT1 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_STATUS_DPIA_PORT2 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_STATUS_DPIA_PORT3 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_MAX_CREDIT_COUNT +#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT_MASK 0x0000003FL +//DPIA_MU_INTERRUPT_STATUS +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS__SHIFT 0x0 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS__SHIFT 0x3 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS__SHIFT 0x6 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS__SHIFT 0x9 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT4_INT_STATUS__SHIFT 0xc +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT5_INT_STATUS__SHIFT 0xf +#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS__SHIFT 0x1f +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS_MASK 0x00000007L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS_MASK 0x00000038L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS_MASK 0x000001C0L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS_MASK 0x00000E00L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT4_INT_STATUS_MASK 0x00007000L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT5_INT_STATUS_MASK 0x00038000L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS_MASK 0x80000000L +//DPIA_MU_INTERRUPT_CTRL +#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN__SHIFT 0x0 +#define DPIA_MU_INTERRUPT_CTRL__DPIA_PORT_INT_MASK__SHIFT 0x8 +#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK__SHIFT 0x18 +#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN_MASK 0x00000001L +#define DPIA_MU_INTERRUPT_CTRL__DPIA_PORT_INT_MASK_MASK 0x0000FF00L +#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK_MASK 0x01000000L +//DPIA_MU_LOCAL_INTERRUPT_CTRL +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS__SHIFT 0x0 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP__SHIFT 0x14 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS__SHIFT 0x18 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS_MASK 0x00000001L +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR_MASK 0x000FFFFCL +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP_MASK 0x00100000L +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS_MASK 0x01000000L +//DPIA_MU_LOCAL_INTERRUPT_ACK +#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK__SHIFT 0x0 +#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK__SHIFT 0x1 +#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK_MASK 0x00000001L +#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK_MASK 0x00000002L +//DPIA_MU_RBBMIF_TIMEOUT_CTRL +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD__SHIFT 0x14 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD_MASK 0xFFF00000L +//DPIA_MU_RBBMIF_TIMEOUT_CTRL2 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS__SHIFT 0x0 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS_MASK 0x00000001L +//DPIA_MU_RBBMIF_STATUS +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x0 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x1 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x5 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK__SHIFT 0x18 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR__SHIFT 0x1f +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000001L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000006L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR_MASK 0x007FFFE0L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK_MASK 0x01000000L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR_MASK 0x80000000L +//DPIA_MU_MICROSECOND_REF_CTRL +#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +//DPIA_MU_PORT_ADP_STATUS +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS__SHIFT 0x0 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS__SHIFT 0x1 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS__SHIFT 0x2 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS__SHIFT 0x3 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT4_HIDDEN_STATUS__SHIFT 0x4 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT5_HIDDEN_STATUS__SHIFT 0x5 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS_MASK 0x00000001L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS_MASK 0x00000002L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS_MASK 0x00000004L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS_MASK 0x00000008L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT4_HIDDEN_STATUS_MASK 0x00000010L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT5_HIDDEN_STATUS_MASK 0x00000020L +//DPIA_GLUE_CTRL +#define DPIA_GLUE_CTRL__DPIA_IO_EN__SHIFT 0x0 +#define DPIA_GLUE_CTRL__DPIA_GLUE_ML_SSCLK_DBG_BUS_SEL__SHIFT 0x4 +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXOUT_SSCLK_DBG_BUS_SEL__SHIFT 0x8 +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXIN_SSCLK_DBG_BUS_SEL__SHIFT 0xa +#define DPIA_GLUE_CTRL__DPIA_IO_EN_MASK 0x00000001L +#define DPIA_GLUE_CTRL__DPIA_GLUE_ML_SSCLK_DBG_BUS_SEL_MASK 0x00000030L +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXOUT_SSCLK_DBG_BUS_SEL_MASK 0x00000300L +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXIN_SSCLK_DBG_BUS_SEL_MASK 0x00000C00L +//DPIA_PERF_COUNT_CONTROL0 +#define DPIA_PERF_COUNT_CONTROL0__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL0__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL0__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL0__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL0__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL0__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL1 +#define DPIA_PERF_COUNT_CONTROL1__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL1__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL1__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL1__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL1__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL1__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL2 +#define DPIA_PERF_COUNT_CONTROL2__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL2__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL2__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL2__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL2__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL2__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL3 +#define DPIA_PERF_COUNT_CONTROL3__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL3__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL3__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL3__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL3__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL3__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL4 +#define DPIA_PERF_COUNT_CONTROL4__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL4__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL4__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL4__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL4__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL4__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL5 +#define DPIA_PERF_COUNT_CONTROL5__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL5__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL5__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL5__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL5__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL5__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_INDEX +#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT__SHIFT 0x0 +#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT__SHIFT 0x4 +#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT_MASK 0x00000007L +#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT_MASK 0x00000070L +//DPIA_PERF_COUNT_DATA_LO +#define DPIA_PERF_COUNT_DATA_LO__VALUE__SHIFT 0x0 +#define DPIA_PERF_COUNT_DATA_LO__VALUE_MASK 0xFFFFFFFFL +//DPIA_MU_SPARE +#define DPIA_MU_SPARE__DPIA_MU_SPARE__SHIFT 0x0 +#define DPIA_MU_SPARE__DPIA_MU_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//GLOBAL_CAPABILITIES +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L +//MINOR_VERSION +#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define MINOR_VERSION__MINOR_VERSION_MASK 0xFFL +//MAJOR_VERSION +#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xFFL +//OUTPUT_PAYLOAD_CAPABILITY +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//INPUT_PAYLOAD_CAPABILITY +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//GLOBAL_CONTROL +#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x00000001L +#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x00000002L +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000100L +//WAKE_ENABLE +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x0001L +//STATE_CHANGE_STATUS +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x0001L +//GLOBAL_STATUS +#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x00000002L +//OUTPUT_STREAM_PAYLOAD_CAPABILITY +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFFL +//INPUT_STREAM_PAYLOAD_CAPABILITY +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFFL +//INTERRUPT_CONTROL +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x00000001L +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x00000002L +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x00000004L +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x00000008L +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x00000010L +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x00000020L +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x00000040L +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x00000080L +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x00000100L +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x00000200L +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x00000400L +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x00000800L +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x00001000L +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x00002000L +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x00004000L +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x00008000L +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000L +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000L +//INTERRUPT_STATUS +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x00000001L +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x00000002L +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x00000004L +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x00000008L +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x00000010L +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x00000020L +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x00000040L +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x00000080L +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x00000100L +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x00000200L +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x00000400L +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x00000800L +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x00001000L +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x00002000L +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x00004000L +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x00008000L +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000L +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000L +//WALL_CLOCK_COUNTER +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xFFFFFFFFL +//STREAM_SYNCHRONIZATION +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x00000001L +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x00000002L +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x00000004L +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x00000008L +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x00000010L +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x00000020L +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x00000040L +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x00000080L +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x00000100L +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x00000200L +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x00000400L +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x00000800L +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x00001000L +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x00002000L +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x00004000L +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x00008000L +//CORB_LOWER_BASE_ADDRESS +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//CORB_UPPER_BASE_ADDRESS +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_CORB_WRITE_POINTER +#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER1_CORB_READ_POINTER +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER1_CORB_CONTROL +#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER1_CORB_STATUS +#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER1_CORB_SIZE +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_RIRB_WRITE_POINTER +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER1_RIRB_CONTROL +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER1_RIRB_STATUS +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER1_RIRB_SIZE +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h new file mode 100644 index 0000000000000..5e99515fbf64a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dpcs_4_0_0_OFFSET_HEADER +#define _dpcs_4_0_0_OFFSET_HEADER + +// addressBlock: dpcssys_dcio_dcio_dispdec +// base address: 0x0 +#define regDC_GENERICA 0x2868 +#define regDC_GENERICA_BASE_IDX 2 +#define regDC_GENERICB 0x2869 +#define regDC_GENERICB_BASE_IDX 2 +#define regDCIO_CLOCK_CNTL 0x286a +#define regDCIO_CLOCK_CNTL_BASE_IDX 2 +#define regDC_REF_CLK_CNTL 0x286b +#define regDC_REF_CLK_CNTL_BASE_IDX 2 +#define regUNIPHYA_LINK_CNTL 0x286d +#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYB_LINK_CNTL 0x286f +#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYC_LINK_CNTL 0x2871 +#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYD_LINK_CNTL 0x2873 +#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYE_LINK_CNTL 0x2875 +#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regDCIO_WRCMD_DELAY 0x287e +#define regDCIO_WRCMD_DELAY_BASE_IDX 2 +#define regDC_PINSTRAPS 0x2880 +#define regDC_PINSTRAPS_BASE_IDX 2 +#define regDCIO_SPARE 0x2882 +#define regDCIO_SPARE_BASE_IDX 2 +#define regINTERCEPT_STATE 0x2884 +#define regINTERCEPT_STATE_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_PAT 0x2886 +#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_EN 0x2887 +#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 +#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define regDPCS_DCIO_TEST_CLK_SRC 0x2890 +#define regDPCS_DCIO_TEST_CLK_SRC_BASE_IDX 2 +#define regDCIO_DEBUG 0x2897 +#define regDCIO_DEBUG_BASE_IDX 2 +#define regDCIO_TEST_DEBUG_INDEX 0x2899 +#define regDCIO_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCIO_TEST_DEBUG_DATA 0x289a +#define regDCIO_TEST_DEBUG_DATA_BASE_IDX 2 +#define regDBG_OUT_CNTL 0x289c +#define regDBG_OUT_CNTL_BASE_IDX 2 +#define regDCIO_DEBUG_CONFIG 0x289d +#define regDCIO_DEBUG_CONFIG_BASE_IDX 2 +#define regDCIO_SOFT_RESET 0x289e +#define regDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_chip_dispdec +// base address: 0x0 +#define regDC_GPIO_DDC1_MASK 0x28d0 +#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC1_A 0x28d1 +#define regDC_GPIO_DDC1_A_BASE_IDX 2 +#define regDC_GPIO_DDC1_EN 0x28d2 +#define regDC_GPIO_DDC1_EN_BASE_IDX 2 +#define regDC_GPIO_DDC1_Y 0x28d3 +#define regDC_GPIO_DDC1_Y_BASE_IDX 2 +#define regDC_GPIO_DDC2_MASK 0x28d4 +#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC2_A 0x28d5 +#define regDC_GPIO_DDC2_A_BASE_IDX 2 +#define regDC_GPIO_DDC2_EN 0x28d6 +#define regDC_GPIO_DDC2_EN_BASE_IDX 2 +#define regDC_GPIO_DDC2_Y 0x28d7 +#define regDC_GPIO_DDC2_Y_BASE_IDX 2 +#define regDC_GPIO_DDC3_MASK 0x28d8 +#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC3_A 0x28d9 +#define regDC_GPIO_DDC3_A_BASE_IDX 2 +#define regDC_GPIO_DDC3_EN 0x28da +#define regDC_GPIO_DDC3_EN_BASE_IDX 2 +#define regDC_GPIO_DDC3_Y 0x28db +#define regDC_GPIO_DDC3_Y_BASE_IDX 2 +#define regDC_GPIO_DDC4_MASK 0x28dc +#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC4_A 0x28dd +#define regDC_GPIO_DDC4_A_BASE_IDX 2 +#define regDC_GPIO_DDC4_EN 0x28de +#define regDC_GPIO_DDC4_EN_BASE_IDX 2 +#define regDC_GPIO_DDC4_Y 0x28df +#define regDC_GPIO_DDC4_Y_BASE_IDX 2 +#define regDC_GPIO_DDC5_MASK 0x28e0 +#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC5_A 0x28e1 +#define regDC_GPIO_DDC5_A_BASE_IDX 2 +#define regDC_GPIO_DDC5_EN 0x28e2 +#define regDC_GPIO_DDC5_EN_BASE_IDX 2 +#define regDC_GPIO_DDC5_Y 0x28e3 +#define regDC_GPIO_DDC5_Y_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_MASK 0x28e8 +#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_A 0x28e9 +#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_EN 0x28ea +#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_Y 0x28eb +#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ0_EN 0x28fa +#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_1 0x28fc +#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define regPHY_AUX_CNTL 0x28ff +#define regPHY_AUX_CNTL_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ1_EN 0x2902 +#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_0 0x2916 +#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_1 0x2917 +#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_3 0x291b +#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_4 0x291c +#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_5 0x291d +#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define regAUXI2C_PAD_ALL_PWR_OK 0x291e +#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h new file mode 100644 index 0000000000000..e124cc13bfa64 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h @@ -0,0 +1,688 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dpcs_4_0_0_SH_MASK_HEADER +#define _dpcs_4_0_0_SH_MASK_HEADER + +// addressBlock: dpcssys_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +//DC_GENERICB +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +//DCIO_SPARE +#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0 +#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL +//INTERCEPT_STATE +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0 +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1 +#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT 0x2 +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4 +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5 +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6 +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7 +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8 +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT 0x9 +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT 0xa +#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE__SHIFT 0x10 +#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE__SHIFT 0x11 +#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE__SHIFT 0x12 +#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE__SHIFT 0x13 +#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE__SHIFT 0x14 +#define INTERCEPT_STATE__DPCS5_DC_INTERCEPTB_STATE__SHIFT 0x15 +#define INTERCEPT_STATE__DPCS6_DC_INTERCEPTB_STATE__SHIFT 0x16 +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L +#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK 0x00000004L +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK 0x00000200L +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK 0x00000400L +#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE_MASK 0x00010000L +#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE_MASK 0x00020000L +#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE_MASK 0x00040000L +#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE_MASK 0x00080000L +#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE_MASK 0x00100000L +#define INTERCEPT_STATE__DPCS5_DC_INTERCEPTB_STATE_MASK 0x00200000L +#define INTERCEPT_STATE__DPCS6_DC_INTERCEPTB_STATE_MASK 0x00400000L +//DCIO_PATTERN_GEN_PAT +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0 +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL +//DCIO_PATTERN_GEN_EN +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0 +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L +//DCIO_BL_PWM_FRAME_START_DISP_SEL +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DPCS_DCIO_TEST_CLK_SRC +#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL__SHIFT 0x0 +#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL_MASK 0x00000007L +//DCIO_DEBUG +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xFFFFFFFFL +//DCIO_TEST_DEBUG_INDEX +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//DCIO_TEST_DEBUG_DATA +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//DBG_OUT_CNTL +#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL__SHIFT 0x0 +#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL__SHIFT 0x5 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA__SHIFT 0xc +#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL_MASK 0x00000003L +#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL_MASK 0x000000E0L +#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA_MASK 0x00FFF000L +//DCIO_DEBUG_CONFIG +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x00000001L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11 +#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L +#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK 0x00100000L + + +// addressBlock: dpcssys_dcio_dcio_chip_dispdec +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_AUX1_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_AUX1_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_AUX2_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_AUX2_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_AUX3_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_AUX3_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_AUX4_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_AUX4_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_AUX5_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_AUX5_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_PWRSEQ0_EN +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +//DC_GPIO_PWRSEQ1_EN +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + +#endif From a03b527b9d14aeae4c41d6ea55081560a9882ade Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 18:06:17 -0500 Subject: [PATCH 0228/2070] drm/amd/display: Add dcn42 DC resources Display Core resources for DCN 4.2: - CLK_MGR - DCCG - DIO - DPP - GPIO - HPO - HUBBUB - HUBP - HWSS - IRQ - MMHUBBUB - MPC - OPTC - PG Signed-off-by: Roman Li Acked-by: Harry Wentland --- .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 1152 ++++++++ .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h | 79 + .../amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 431 +++ .../amd/display/dc/clk_mgr/dcn42/dcn42_smu.h | 190 ++ .../amd/display/dc/dccg/dcn42/dcn42_dccg.c | 278 ++ .../amd/display/dc/dccg/dcn42/dcn42_dccg.h | 263 ++ .../dc/dio/dcn42/dcn42_dio_link_encoder.c | 205 ++ .../dc/dio/dcn42/dcn42_dio_link_encoder.h | 140 + .../dc/dio/dcn42/dcn42_dio_stream_encoder.c | 522 ++++ .../dc/dio/dcn42/dcn42_dio_stream_encoder.h | 206 ++ .../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c | 338 +++ .../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h | 469 ++++ .../display/dc/gpio/dcn42/hw_factory_dcn42.c | 254 ++ .../display/dc/gpio/dcn42/hw_factory_dcn42.h | 31 + .../dc/gpio/dcn42/hw_translate_dcn42.c | 205 ++ .../dc/gpio/dcn42/hw_translate_dcn42.h | 36 + .../dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c | 93 + .../dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h | 17 + .../display/dc/hubbub/dcn42/dcn42_hubbub.c | 539 ++++ .../display/dc/hubbub/dcn42/dcn42_hubbub.h | 268 ++ .../amd/display/dc/hubp/dcn42/dcn42_hubp.c | 643 +++++ .../amd/display/dc/hubp/dcn42/dcn42_hubp.h | 79 + .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 1476 +++++++++++ .../amd/display/dc/hwss/dcn42/dcn42_hwseq.h | 53 + .../amd/display/dc/hwss/dcn42/dcn42_init.c | 167 ++ .../amd/display/dc/hwss/dcn42/dcn42_init.h | 11 + .../display/dc/irq/dcn42/irq_service_dcn42.c | 412 +++ .../display/dc/irq/dcn42/irq_service_dcn42.h | 15 + .../dc/mmhubbub/dcn42/dcn42_mmhubbub.c | 25 + .../dc/mmhubbub/dcn42/dcn42_mmhubbub.h | 13 + .../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c | 1121 ++++++++ .../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h | 1006 +++++++ .../amd/display/dc/optc/dcn42/dcn42_optc.c | 198 ++ .../amd/display/dc/optc/dcn42/dcn42_optc.h | 211 ++ .../amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 648 +++++ .../amd/display/dc/pg/dcn42/dcn42_pg_cntl.h | 175 ++ .../dc/resource/dcn42/dcn42_resource.c | 2337 +++++++++++++++++ .../dc/resource/dcn42/dcn42_resource.h | 588 +++++ .../dc/resource/dcn42/dcn42_resource_fpu.c | 47 + .../dc/resource/dcn42/dcn42_resource_fpu.h | 33 + 40 files changed, 14974 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h create mode 100644 drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c create mode 100644 drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h create mode 100644 drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c create mode 100644 drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c create mode 100644 drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h create mode 100644 drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c create mode 100644 drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h create mode 100644 drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c create mode 100644 drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c new file mode 100644 index 0000000000000..55434f046fa29 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -0,0 +1,1152 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn42_clk_mgr.h" + +#include "dccg.h" +#include "clk_mgr_internal.h" + +// For dce12_get_dp_ref_freq_khz +#include "dce100/dce_clk_mgr.h" + +// For dcn20_update_clocks_update_dpp_dto +#include "dcn20/dcn20_clk_mgr.h" + + + + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn42_smu.h" +#include "dm_helpers.h" + +/* TODO: remove this include once we ported over remaining clk mgr functions*/ +#include "dcn30/dcn30_clk_mgr.h" +#include "dcn31/dcn31_clk_mgr.h" + +#include "dcn35/dcn35_clk_mgr.h" + +#include "dc_dmub_srv.h" +#include "link_service.h" +#include "logger_types.h" + + +#undef DC_LOGGER +#define DC_LOGGER \ + clk_mgr->base.base.ctx->logger + + +#define DCN_BASE__INST0_SEG1 0x000000C0 + +#define regCLK8_CLK2_BYPASS_CNTL 0x4c2a +#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX 0 +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L + +#define regDENTIST_DISPCLK_CNTL 0x0064 +#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 + +// DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L +#define mmDENTIST_DISPCLK_CNTL 0x0124 +#define mmCLK8_CLK_TICK_CNT_CONFIG_REG 0x1B851 +#define mmCLK8_CLK0_CURRENT_CNT 0x1B853 +#define mmCLK8_CLK1_CURRENT_CNT 0x1B854 +#define mmCLK8_CLK2_CURRENT_CNT 0x1B855 +#define mmCLK8_CLK3_CURRENT_CNT 0x1B856 +#define mmCLK8_CLK4_CURRENT_CNT 0x1B857 + + +#define mmCLK8_CLK0_BYPASS_CNTL 0x1B81A +#define mmCLK8_CLK1_BYPASS_CNTL 0x1B822 +#define mmCLK8_CLK2_BYPASS_CNTL 0x1B82A +#define mmCLK8_CLK3_BYPASS_CNTL 0x1B832 +#define mmCLK8_CLK4_BYPASS_CNTL 0x1B83A + + +#define mmCLK8_CLK0_DS_CNTL 0x1B814 +#define mmCLK8_CLK1_DS_CNTL 0x1B81C +#define mmCLK8_CLK2_DS_CNTL 0x1B824 +#define mmCLK8_CLK3_DS_CNTL 0x1B82C +#define mmCLK8_CLK4_DS_CNTL 0x1B834 + + + + +#undef FN +#define FN(reg_name, field_name) \ + clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name + +#define REG(reg) \ + (clk_mgr->regs->reg) + +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name)\ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name + +#define CLK_SR_DCN42(reg_name)\ + .reg_name = mm ## reg_name + +static const struct clk_mgr_registers clk_mgr_regs_dcn42 = { + CLK_REG_LIST_DCN42() +}; + +static const struct clk_mgr_shift clk_mgr_shift_dcn42 = { + CLK_COMMON_MASK_SH_LIST_DCN42(__SHIFT) +}; + +static const struct clk_mgr_mask clk_mgr_mask_dcn42 = { + CLK_COMMON_MASK_SH_LIST_DCN42(_MASK) +}; + + + +#define TO_CLK_MGR_DCN42(clk_mgr_int)\ + container_of(clk_mgr_int, struct clk_mgr_dcn42, base) + +int dcn42_get_active_display_cnt_wa( + struct dc *dc, + struct dc_state *context, + int *all_active_disps) +{ + int i, display_count = 0; + bool tmds_present = false; + + for (i = 0; i < context->stream_count; i++) { + const struct dc_stream_state *stream = context->streams[i]; + + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || + stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || + stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) + tmds_present = true; + } + + for (i = 0; i < dc->link_count; i++) { + const struct dc_link *link = dc->links[i]; + + /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ + if (link->link_enc && link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) + display_count++; + } + if (all_active_disps != NULL) + *all_active_disps = display_count; + /* WA for hang on HDMI after display off back on*/ + if (display_count == 0 && tmds_present) + display_count = 1; + + return display_count; +} + +void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, + struct dc_state *context, + int ref_dtbclk_khz) +{ + /* DCN42 does not implement set_dtbclk_dto function, so this is a no-op */ +} + +void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, + struct dc_state *context, bool safe_to_lower) +{ + int i; + bool dppclk_active[MAX_PIPES] = {0}; + + + clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; + + dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; + + if (context->res_ctx.pipe_ctx[i].plane_res.dpp) + dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; + else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { + /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting. + * In this case just continue in loop + */ + continue; + } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { + /* The software state is not valid if dpp resource is NULL and + * dppclk_khz > 0. + */ + ASSERT(false); + continue; + } + + prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; + + if (safe_to_lower || prev_dppclk_khz < dppclk_khz) + clk_mgr->dccg->funcs->update_dpp_dto( + clk_mgr->dccg, dpp_inst, dppclk_khz); + dppclk_active[dpp_inst] = true; + } + if (safe_to_lower) + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp; + + if (old_dpp && !dppclk_active[old_dpp->inst]) + clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0); + } +} + +void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower) +{ + union dmub_rb_cmd cmd; + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + struct dc *dc = clk_mgr_base->ctx->dc; + int display_count = 0; + bool update_dppclk = false; + bool update_dispclk = false; + bool dpp_clock_lowered = false; + int all_active_disps = 0; + + if (dc->work_arounds.skip_clock_update) + return; + + display_count = dcn42_get_active_display_cnt_wa(dc, context, &all_active_disps); + + /*dml21 issue*/ + ASSERT(new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000); //remove this section if assert is hit + if (new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz < 590000) + new_clocks->ref_dtbclk_khz = 600000; + + /* + * if it is safe to lower, but we are already in the lower state, we don't have to do anything + * also if safe to lower is false, we just go in the higher state + */ + if (safe_to_lower) { + if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && + new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { + dcn42_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); + clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; + } + + if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { + if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk) + dcn42_smu_set_dtbclk(clk_mgr, false); + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } + /* check that we're not already in lower */ + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { + /* if we can go lower, go lower */ + if (display_count == 0) + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; + } + } else { + if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && + new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { + dcn42_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); + clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; + } + if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { + int actual_dtbclk = 0; + + dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); + dcn42_smu_set_dtbclk(clk_mgr, true); + if (clk_mgr_base->boot_snapshot.timer_threhold) + actual_dtbclk = REG_READ(CLK8_CLK4_CURRENT_CNT) / (clk_mgr_base->boot_snapshot.timer_threhold / 48000); + + + if (actual_dtbclk > 590000) { + clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } + } + + /* check that we're not already in D0 */ + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { + union display_idle_optimization_u idle_info = { 0 }; + + dcn42_smu_set_display_idle_optimization(clk_mgr, idle_info.data); + /* update power state */ + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; + } + } + if (dc->debug.force_min_dcfclk_mhz > 0) + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? + new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { + clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; + clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; + clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; + dcn42_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); + } + + if (should_set_clock(safe_to_lower, + new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { + clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); + } + + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { + if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) + dpp_clock_lowered = true; + clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; + update_dppclk = true; + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && + (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { + int requested_dispclk_khz = new_clocks->dispclk_khz; + + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); + + /* Clamp the requested clock to PMFW based on their limit. */ + if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz) + requested_dispclk_khz = dc->debug.min_disp_clk_khz; + + dcn42_smu_set_dispclk(clk_mgr, requested_dispclk_khz); + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); + + update_dispclk = true; + } + + /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */ + if (!dc->debug.disable_dtb_ref_clk_switch && + should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, + clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { + dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); + clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; + } + + if (dpp_clock_lowered) { + // increase per DPP DTO before lowering global dppclk + dcn42_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); + dcn42_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + } else { + // increase global DPPCLK before lowering per DPP DTO + if (update_dppclk || update_dispclk) + dcn42_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + dcn42_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); + } + // notify DMCUB of latest clocks + memset(&cmd, 0, sizeof(cmd)); + cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; + cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; + cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; + cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = + clk_mgr_base->clks.dcfclk_deep_sleep_khz; + cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; + cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); +} + + +void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + dcn42_smu_enable_pme_wa(clk_mgr); +} + + +bool dcn42_are_clock_states_equal(struct dc_clocks *a, + struct dc_clocks *b) +{ + if (a->dispclk_khz != b->dispclk_khz) + return false; + else if (a->dppclk_khz != b->dppclk_khz) + return false; + else if (a->dcfclk_khz != b->dcfclk_khz) + return false; + else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) + return false; + else if (a->zstate_support != b->zstate_support) + return false; + else if (a->dtbclk_en != b->dtbclk_en) + return false; + + return true; +} + +static void dcn42_dump_clk_registers_internal(struct dcn42_clk_internal *internal, struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + uint32_t ratio = 1; + + internal->CLK8_CLK_TICK_CNT__TIMER_THRESHOLD = REG_READ(CLK8_CLK_TICK_CNT_CONFIG_REG) & 0xFFFFFF; + + ratio = internal->CLK8_CLK_TICK_CNT__TIMER_THRESHOLD / 48000; + ASSERT(ratio != 0); + + if (ratio) { + // read dcf deep sleep divider + internal->CLK8_CLK0_DS_CNTL = REG_READ(CLK8_CLK0_DS_CNTL); + internal->CLK8_CLK3_DS_CNTL = REG_READ(CLK8_CLK3_DS_CNTL); + // read dispclk + internal->CLK8_CLK0_CURRENT_CNT = REG_READ(CLK8_CLK0_CURRENT_CNT) / ratio; + internal->CLK8_CLK0_BYPASS_CNTL = REG_READ(CLK8_CLK0_BYPASS_CNTL); + // read dppclk + internal->CLK8_CLK1_CURRENT_CNT = REG_READ(CLK8_CLK1_CURRENT_CNT) / ratio; + internal->CLK8_CLK1_BYPASS_CNTL = REG_READ(CLK8_CLK1_BYPASS_CNTL); + // read dprefclk + internal->CLK8_CLK2_CURRENT_CNT = REG_READ(CLK8_CLK2_CURRENT_CNT) / ratio; + internal->CLK8_CLK2_BYPASS_CNTL = REG_READ(CLK8_CLK2_BYPASS_CNTL); + // read dcfclk + internal->CLK8_CLK3_CURRENT_CNT = REG_READ(CLK8_CLK3_CURRENT_CNT) / ratio; + internal->CLK8_CLK3_BYPASS_CNTL = REG_READ(CLK8_CLK3_BYPASS_CNTL); + // read dtbclk + internal->CLK8_CLK4_CURRENT_CNT = REG_READ(CLK8_CLK4_CURRENT_CNT) / ratio; + internal->CLK8_CLK4_BYPASS_CNTL = REG_READ(CLK8_CLK4_BYPASS_CNTL); + } + +} + +static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr_dcn42 *clk_mgr) +{ + struct dcn42_clk_internal internal = {0}; + char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; + + dcn42_dump_clk_registers_internal(&internal, &clk_mgr->base.base); + regs_and_bypass->timer_threhold = internal.CLK8_CLK_TICK_CNT__TIMER_THRESHOLD; + regs_and_bypass->dcfclk = internal.CLK8_CLK3_CURRENT_CNT / 10; + regs_and_bypass->dcf_deep_sleep_divider = internal.CLK8_CLK3_DS_CNTL / 10; + regs_and_bypass->dcf_deep_sleep_allow = internal.CLK8_CLK3_DS_CNTL & 0x10; /*bit 4: CLK0_ALLOW_DS*/ + regs_and_bypass->dprefclk = internal.CLK8_CLK2_CURRENT_CNT / 10; + regs_and_bypass->dispclk = internal.CLK8_CLK0_CURRENT_CNT / 10; + regs_and_bypass->dppclk = internal.CLK8_CLK1_CURRENT_CNT / 10; + regs_and_bypass->dtbclk = internal.CLK8_CLK4_CURRENT_CNT / 10; + + regs_and_bypass->dppclk_bypass = internal.CLK8_CLK1_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dppclk_bypass > 4) + regs_and_bypass->dppclk_bypass = 0; + regs_and_bypass->dcfclk_bypass = internal.CLK8_CLK3_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dcfclk_bypass > 4) + regs_and_bypass->dcfclk_bypass = 0; + regs_and_bypass->dispclk_bypass = internal.CLK8_CLK0_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dispclk_bypass > 4) + regs_and_bypass->dispclk_bypass = 0; + regs_and_bypass->dprefclk_bypass = internal.CLK8_CLK2_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dprefclk_bypass > 4) + regs_and_bypass->dprefclk_bypass = 0; + + if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { + DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); + + DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n", + regs_and_bypass->dcfclk, + regs_and_bypass->dcf_deep_sleep_divider, + regs_and_bypass->dcf_deep_sleep_allow, + bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); + + DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n", + regs_and_bypass->dprefclk, + bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); + + DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n", + regs_and_bypass->dispclk, + bypass_clks[(int) regs_and_bypass->dispclk_bypass]); + + //split + DC_LOG_SMU("SPLIT\n"); + + // REGISTER VALUES + DC_LOG_SMU("reg_name,value,clk_type\n"); + + DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", + internal.CLK8_CLK3_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", + internal.CLK8_CLK3_DS_CNTL); + + DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", + (internal.CLK8_CLK3_DS_CNTL & 0x10)); + + DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", + internal.CLK8_CLK2_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", + internal.CLK8_CLK0_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", + internal.CLK8_CLK1_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", + internal.CLK8_CLK3_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", + internal.CLK8_CLK2_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", + internal.CLK8_CLK0_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", + internal.CLK8_CLK1_BYPASS_CNTL); + } +} + +bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_context *ctx = clk_mgr->base.ctx; + + + if (ctx->dc->config.ignore_dpref_ss) { + /*revert bios's ss info for test only*/ + return (clk_mgr->dprefclk_ss_percentage == 0); + } + /*need to update after BU*/ + return false; +} + +static void init_clk_states(struct clk_mgr *clk_mgr) +{ + uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; + + memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); + + clk_mgr->clks.dtbclk_en = true; // request DTBCLK disable on first commit + clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk + clk_mgr->clks.p_state_change_support = true; + clk_mgr->clks.prev_p_state_change_support = true; + clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; + clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; +} + +static void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, + struct dcn42_smu_dpm_clks *smu_dpm_clks) +{ + DpmClocks_t_dcn42 *table = smu_dpm_clks->dpm_clks; + + if (!clk_mgr->smu_ver) + return; + + if (!table || smu_dpm_clks->mc_address.quad_part == 0) + return; + + memset(table, 0, sizeof(*table)); + + dcn42_smu_set_dram_addr_high(clk_mgr, + smu_dpm_clks->mc_address.high_part); + dcn42_smu_set_dram_addr_low(clk_mgr, + smu_dpm_clks->mc_address.low_part); + dcn42_smu_transfer_dpm_table_smu_2_dram(clk_mgr); +} + +void dcn42_init_single_clock(unsigned int *entry_0, + uint32_t *smu_entry_0, + uint8_t num_levels) +{ + int i; + char *entry_i = (char *)entry_0; + + ASSERT(num_levels <= MAX_NUM_DPM_LVL); + if (num_levels > MAX_NUM_DPM_LVL) + num_levels = MAX_NUM_DPM_LVL; + + + for (i = 0; i < num_levels; i++) { + *((unsigned int *)entry_i) = smu_entry_0[i]; + entry_i += sizeof(struct clk_limit_table_entry); + } +} + +unsigned int dcn42_convert_wck_ratio(uint8_t wck_ratio) +{ + switch (wck_ratio) { + case WCK_RATIO_1_2: + return 2; + + case WCK_RATIO_1_4: + return 4; + + default: + break; + } + + return 1; +} + +void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); + struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 }; + + init_clk_states(clk_mgr_base); + + // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk + if (dcn42_is_spll_ssc_enabled(clk_mgr_base)) + clk_mgr_base->dp_dto_source_clock_in_khz = + dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr_base->dprefclk_khz); + else + clk_mgr_base->dp_dto_source_clock_in_khz = clk_mgr_base->dprefclk_khz; + + dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); + + clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; + if (clk_mgr_base->boot_snapshot.dtbclk > 59000) { + /*dtbclk enabled based on*/ + clk_mgr_base->clks.dtbclk_en = true; + } + + smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem( + clk_mgr_base->ctx, + DC_MEM_ALLOC_TYPE_GART, + sizeof(DpmClocks_t_dcn42), + &smu_dpm_clks.mc_address.quad_part); + + ASSERT(smu_dpm_clks.dpm_clks); + if (clk_mgr_base->ctx->dc->debug.pstate_enabled && clk_mgr_int->smu_present && smu_dpm_clks.mc_address.quad_part != 0) { + int i; + DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks; + + dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks); + DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" + "NumDispClkLevelsEnabled: %d\n" + "NumSocClkLevelsEnabled: %d\n" + "VcnClkLevelsEnabled: %d\n" + "FClkLevelsEnabled: %d\n" + "NumMemPstatesEnabled: %d\n" + "MinGfxClk: %d\n" + "MaxGfxClk: %d\n", + dpm_clks->NumDcfClkLevelsEnabled, + dpm_clks->NumDispClkLevelsEnabled, + dpm_clks->NumSocClkLevelsEnabled, + dpm_clks->VcnClkLevelsEnabled, + dpm_clks->NumFclkLevelsEnabled, + dpm_clks->NumMemPstatesEnabled, + dpm_clks->MinGfxClk, + dpm_clks->MaxGfxClk); + + for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n", + i, + dpm_clks->DcfClocks[i]); + } + for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n", + i, dpm_clks->DispClocks[i]); + } + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n", + i, dpm_clks->SocClocks[i]); + } + for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n", + i, dpm_clks->FclkClocks_Freq[i]); + DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n", + i, dpm_clks->FclkClocks_Voltage[i]); + } + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) + DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n", + i, dpm_clks->SocVoltage[i]); + + for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) { + DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d\n" + "dpm_clks->MemPstateTable[%d].MemClk= %d\n" + "dpm_clks->MemPstateTable[%d].Voltage = %d\n", + i, dpm_clks->MemPstateTable[i].UClk, + i, dpm_clks->MemPstateTable[i].MemClk, + i, dpm_clks->MemPstateTable[i].Voltage); + } + + if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) { + /* DCFCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, + dpm_clks->DcfClocks, + dpm_clks->NumDcfClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled; + + /* SOCCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, + dpm_clks->SocClocks, + dpm_clks->NumSocClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled; + + /* DISPCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, + dpm_clks->DispClocks, + dpm_clks->NumDispClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled; + + /* DPPCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, + dpm_clks->DppClocks, + dpm_clks->NumDispClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled; + + /* FCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, + dpm_clks->FclkClocks_Freq, + NUM_FCLK_DPM_LEVELS); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled; + clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled; + + /* Memory Pstate table is in reverse order*/ + ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS); + if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) + dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS; + for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) { + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].UClk; + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ; + } + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; + + /* DTBCLK*/ + clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; + + /* Refresh bounding box */ + clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( + clk_mgr_base->ctx->dc, clk_mgr_base->bw_params); + } + } + if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART, + smu_dpm_clks.dpm_clks); +} + +static struct clk_bw_params dcn42_bw_params = { + .vram_type = Ddr4MemType, + .num_channels = 1, + .clk_table = { + .num_entries = 4, + }, + +}; + +static struct wm_table ddr5_wm_table = { + .entries = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + } +}; + +static struct wm_table lpddr5_wm_table = { + .entries = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + } +}; + +struct dcn42_ss_info_table dcn42_ss_info_table = { + .ss_divider = 1000, + .ss_percentage = {0, 0, 375, 375, 375} +}; + +static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) +{ + uint32_t clock_source; + + clock_source = (REG_READ(CLK8_CLK2_BYPASS_CNTL) & CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK); + // If it's DFS mode, clock_source is 0. + if (dcn42_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(dcn42_ss_info_table.ss_percentage))) { + clk_mgr->dprefclk_ss_percentage = dcn42_ss_info_table.ss_percentage[clock_source]; + + if (clk_mgr->dprefclk_ss_percentage != 0) { + clk_mgr->ss_on_dprefclk = true; + clk_mgr->dprefclk_ss_divider = dcn42_ss_info_table.ss_divider; + } + } +} + +/* Exposed for dcn42b reuse */ +void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) +{ + int i, num_valid_sets; + + num_valid_sets = 0; + + for (i = 0; i < WM_SET_COUNT; i++) { + /* skip empty entries, the smu array has no holes*/ + if (!bw_params->wm_table.entries[i].valid) + continue; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + /* We will not select WM based on fclk, so leave it as unconstrained */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; + + if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { + if (i == 0) + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; + else { + /* add 1 to make it non-overlapping with next lvl */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = + bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + } + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = + bw_params->clk_table.entries[i].dcfclk_mhz; + + } else { + /* unconstrained for memory retraining */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; + + /* Modify previous watermark range to cover up to max */ + if (num_valid_sets > 0) + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + } + num_valid_sets++; + } + + ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ + + /* modify the min and max to make sure we cover the whole range*/ + table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; + table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + + /* This is for writeback only, does not matter currently as no writeback support*/ + table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; + table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; + table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; + table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; + table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; +} + +void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct clk_mgr_dcn42 *clk_mgr_dcn42 = TO_CLK_MGR_DCN42(clk_mgr); + struct dcn42_watermarks *table = clk_mgr_dcn42->smu_wm_set.wm_set; + + if (!clk_mgr->smu_ver) + return; + + if (!table || clk_mgr_dcn42->smu_wm_set.mc_address.quad_part == 0) + return; + + memset(table, 0, sizeof(*table)); + + dcn42_build_watermark_ranges(clk_mgr_base->bw_params, table); + + dcn42_smu_set_dram_addr_high(clk_mgr, + clk_mgr_dcn42->smu_wm_set.mc_address.high_part); + dcn42_smu_set_dram_addr_low(clk_mgr, + clk_mgr_dcn42->smu_wm_set.mc_address.low_part); + dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr); +} + +void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base) +{ + int display_count; + struct dc *dc = clk_mgr_base->ctx->dc; + struct dc_state *context = dc->current_state; + + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { + display_count = dcn42_get_active_display_cnt_wa(dc, context, NULL); + /* if we can go lower, go lower */ + if (display_count == 0) + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; + } + + if (clk_mgr_base->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) { + union display_idle_optimization_u idle_info = { 0 }; + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + idle_info.idle_info.df_request_disabled = 1; + idle_info.idle_info.phy_ref_clk_off = 1; + idle_info.idle_info.s0i2_rdy = 1; + dcn42_smu_set_display_idle_optimization(clk_mgr, idle_info.data); + } +} + +void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base) +{ + +} + +static void dcn42_init_clocks_fpga(struct clk_mgr *clk_mgr) +{ + init_clk_states(clk_mgr); + +} + +static void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr, + struct dc_state *context, + bool safe_to_lower) +{ + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + int fclk_adj = new_clocks->fclk_khz; + + /* TODO: remove this after correctly set by DML */ + new_clocks->dcfclk_khz = 400000; + new_clocks->socclk_khz = 400000; + + /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ + //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; + new_clocks->fclk_khz = 4320000; + + if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) + clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) + clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; + + if (should_set_clock(safe_to_lower, + new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) + clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + + if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) + clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; + + if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) + clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) + clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; + + if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) + clk_mgr->clks.fclk_khz = fclk_adj; + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) + clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; + + /* Both fclk and ref_dppclk run on the same scemi clock. + * So take the higher value since the DPP DTO is typically programmed + * such that max dppclk is 1:1 with ref_dppclk. + */ + if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) + clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; + if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) + clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; + + // Both fclk and ref_dppclk run on the same scemi clock. + clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; + + /* TODO: set dtbclk in correct place */ + clk_mgr->clks.dtbclk_en = true; + + dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); + dcn42_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower); + + dcn42_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz); +} + +unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + unsigned int num_clk_levels; + + switch (clk_type) { + case CLK_TYPE_DISPCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 : + clk_mgr->base.boot_snapshot.dispclk; + case CLK_TYPE_DPPCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 : + clk_mgr->base.boot_snapshot.dppclk; + case CLK_TYPE_DSCCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 : + clk_mgr->base.boot_snapshot.dispclk / 3; + default: + break; + } + + return 0; +} + +static int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + uint32_t dispclk_wdivider; + int disp_divider; + + REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); + disp_divider = dentist_get_divider_from_did(dispclk_wdivider); + + /* Return DISPCLK freq in Khz */ + if (disp_divider) + return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; + + return 0; +} +bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + return clk_mgr->smu_present; +} + +static struct clk_mgr_funcs dcn42_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, + .update_clocks = dcn42_update_clocks, + .init_clocks = dcn42_init_clocks, + .enable_pme_wa = dcn42_enable_pme_wa, + .are_clock_states_equal = dcn42_are_clock_states_equal, + .notify_wm_ranges = dcn42_notify_wm_ranges, + .set_low_power_state = dcn42_set_low_power_state, + .exit_low_power_state = dcn42_exit_low_power_state, + .get_max_clock_khz = dcn42_get_max_clock_khz, + .get_dispclk_from_dentist = dcn42_get_dispclk_from_dentist, + .is_smu_present = dcn42_is_smu_present, +}; + +struct clk_mgr_funcs dcn42_fpga_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .update_clocks = dcn42_update_clocks_fpga, + .init_clocks = dcn42_init_clocks_fpga, + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, +}; + +void dcn42_clk_mgr_construct( + struct dc_context *ctx, + struct clk_mgr_dcn42 *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg) +{ + clk_mgr->base.base.ctx = ctx; + clk_mgr->base.base.funcs = &dcn42_funcs; + clk_mgr->base.regs = &clk_mgr_regs_dcn42; + clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn42; + clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42; + + clk_mgr->base.pp_smu = pp_smu; + + clk_mgr->base.dccg = dccg; + clk_mgr->base.dfs_bypass_disp_clk = 0; + + clk_mgr->base.dprefclk_ss_percentage = 0; + clk_mgr->base.dprefclk_ss_divider = 1000; + clk_mgr->base.ss_on_dprefclk = false; + clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/ + + clk_mgr->smu_wm_set.wm_set = (struct dcn42_watermarks *)dm_helpers_allocate_gpu_mem( + clk_mgr->base.base.ctx, + DC_MEM_ALLOC_TYPE_GART, + sizeof(struct dcn42_watermarks), + &clk_mgr->smu_wm_set.mc_address.quad_part); + + ASSERT(clk_mgr->smu_wm_set.wm_set); + + /* Changed from DCN3.2_clock_frequency doc to match + * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz / + * dprefclk DID divider + */ + clk_mgr->base.base.dprefclk_khz = 600000; + + clk_mgr->base.smu_present = false; + + if (ctx->dc_bios->integrated_info) { + clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; + + if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) + dcn42_bw_params.wm_table = lpddr5_wm_table; + else + dcn42_bw_params.wm_table = ddr5_wm_table; + dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; + dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; + dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 4; + } + /* in case we don't get a value from the BIOS, use default */ + if (clk_mgr->base.base.dentist_vco_freq_khz == 0) + clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */ + + /* Saved clocks configured at boot for debug purposes */ + dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); + + if (clk_mgr->base.smu_present) + clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); + clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; + dce_clock_read_ss_info(&clk_mgr->base); + /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ + + dcn42_read_ss_info_from_lut(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; +} + +void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) +{ + struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); + + if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_GART, + clk_mgr->smu_wm_set.wm_set); +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h new file mode 100644 index 0000000000000..99fcdb602c621 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DCN42_CLK_MGR_H__ +#define __DCN42_CLK_MGR_H__ +#include "clk_mgr_internal.h" + +#define NUM_CLOCK_SOURCES 5 + +struct dcn42_watermarks; + +struct dcn42_smu_watermark_set { + struct dcn42_watermarks *wm_set; + union large_integer mc_address; +}; + +struct dcn42_ss_info_table { + uint32_t ss_divider; + uint32_t ss_percentage[NUM_CLOCK_SOURCES]; +}; + +struct clk_mgr_dcn42 { + struct clk_mgr_internal base; + struct dcn42_smu_watermark_set smu_wm_set; +}; + +bool dcn42_are_clock_states_equal(struct dc_clocks *a, + struct dc_clocks *b); +void dcn42_init_clocks(struct clk_mgr *clk_mgr); +void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower); + +void dcn42_clk_mgr_construct(struct dc_context *ctx, + struct clk_mgr_dcn42 *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg); + +void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); + +/* Exposed for dcn42b reuse */ +void dcn42_init_single_clock(unsigned int *entry_0, + uint32_t *smu_entry_0, + uint8_t num_levels); +unsigned int dcn42_convert_wck_ratio(uint8_t wck_ratio); +extern struct dcn42_ss_info_table dcn42_ss_info_table; +void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table); +void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base); +void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base); +void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base); +void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base); +unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type); +bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base); +int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int *all_active_disps); +void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower); +void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz); +bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base); +#endif //__DCN42_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c new file mode 100644 index 0000000000000..19df8b47248b1 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + + + +#include "core_types.h" +#include "clk_mgr_internal.h" +#include "reg_helper.h" +#include "dm_helpers.h" +#include "dcn42_smu.h" + +#include "mp/mp_15_0_0_offset.h" +#include "mp/mp_15_0_0_sh_mask.h" + +#ifdef BASE_INNER +#undef BASE_INNER +#endif + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x00016200 +#define MP1_BASE__INST0_SEG2 0x00E00000 +#define MP1_BASE__INST0_SEG3 0x00E80000 +#define MP1_BASE__INST0_SEG4 0x00EC0000 +#define MP1_BASE__INST0_SEG5 0x00F00000 +#define MP1_BASE__INST0_SEG6 0x02400400 +#define MP1_BASE__INST0_SEG7 0x0243F400 +#define MP1_BASE__INST0_SEG8 0x3C004000 +#define MP1_BASE__INST0_SEG9 0x3C3F4000 + +#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) + +#define FN(reg_name, field) \ + FD(reg_name##__##field) + +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + +// VBIOS and DAL to PMFW Interface + +// DAL to PMFW interface registers +#define DAL_MSG_REG MP1_SMN_C2PMSG_71 +#define DAL_RESP_REG MP1_SMN_C2PMSG_72 +#define DAL_ARG_REG MP1_SMN_C2PMSG_73 + +/** @defgroup ResponseCodes PMFW Response Codes +* @{ +*/ +// SMU Response Codes: +#define DALSMC_Result_OK 0x01 ///< Message Response OK +#define DALSMC_Result_Failed 0xFF ///< Message Response Failed +#define DALSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command +#define DALSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite +#define DALSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message +/** @}*/ + +// Message Definitions: +/** @defgroup definitions Message definitions +* @{ +*/ +#define DALSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team +#define DALSMC_MSG_GetPmfwVersion 0x02 ///< Get version +#define DALSMC_MSG_SetDispclkFreq 0x03 ///< Set display clock frequency in MHZ +#define DALSMC_MSG_SetDppclkFreq 0x04 ///< Set DPP clock frequency in MHZ +#define DALSMC_MSG_SetHardMinDcfclkByFreq 0x05 ///< Set DCF clock frequency hard min in MHZ +#define DALSMC_MSG_SetMinDeepSleepDcfclk 0x06 ///< Set DCF clock minimum frequency in deep sleep in MHZ +#define DALSMC_MSG_UpdatePmeRestore 0x07 ///< To ask PMFW to write into Azalia for PME wake up event +#define DALSMC_MSG_SetDramAddrHigh 0x08 ///< Set DRAM address high 32 bits for WM table transfer +#define DALSMC_MSG_SetDramAddrLow 0x09 ///< Set DRAM address low 32 bits for WM table transfer + +#define DALSMC_MSG_TransferTableSmu2Dram 0x0A ///< Transfer table from PMFW SRAM to system DRAM +#define DALSMC_MSG_TransferTableDram2Smu 0x0B ///< Transfer table from system DRAM to PMFW +#define DALSMC_MSG_SetDisplayIdleOptimizations 0x0C ///< Set Idle state optimization for display off +#define DALSMC_MSG_GetDprefclkFreq 0x0D ///< Get DPREF clock frequency. Return in MHZ +#define DALSMC_MSG_GetDtbclkFreq 0x0E ///< Get DTB clock frequency. Return in MHZ +#define DALSMC_MSG_AllowZstatesEntry 0x0F ///< Inform PMFW of display allowing Zstate entry +#define DALSMC_MSG_SetDtbClk 0x10 ///< Inform PMFW to turn of/off DTB cl0ck. arg = 1: turn DTB on with 600MHZ; arg = 0: turn DTB clk off +#define DALSMC_MSG_DispIPS2Exit 0x11 ///< Display IPS2 exit + +#define DALSMC_MSG_QueryIPS2Support 0x12 ///< Return 1: support; else not supported +#define DALSMC_Message_Count 0x13 ///< Total number of VBIS and DAL messages +/** @}*/ + + +union dcn42_dpia_host_router_bw { + struct { + uint32_t hr_id : 16; + uint32_t bw_mbps : 16; + } bits; + uint32_t all; +}; + +/* + * Function to be used instead of REG_WAIT macro because the wait ends when + * the register is NOT EQUAL to zero, and because `the translation in msg_if.h + * won't work with REG_WAIT. + */ +static uint32_t dcn42_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, + unsigned int delay_us, unsigned int max_retries) +{ + uint32_t res_val = DALSMC_Result_CmdRejectedBusy; + + do { + res_val = REG_READ(DAL_RESP_REG); + if (res_val != DALSMC_Result_CmdRejectedBusy) + break; + + if (delay_us >= 1000) + msleep(delay_us/1000); + else if (delay_us > 0) + udelay(delay_us); + + if (clk_mgr->base.ctx->dc->debug.disable_timeout) + max_retries++; + } while (max_retries--); + + return res_val; +} + +static int dcn42_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, + unsigned int msg_id, + unsigned int param) +{ + uint32_t result; + + result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000); + + if (result != DALSMC_Result_OK) { + DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id); + + if (result == DALSMC_Result_CmdRejectedBusy) + return -1; + } + + /* First clear response register */ + REG_WRITE(DAL_RESP_REG, DALSMC_Result_CmdRejectedBusy); + + /* Set the parameter register for the SMU message, unit is Mhz */ + REG_WRITE(DAL_ARG_REG, param); + + /* Trigger the message transaction by writing the message ID */ + REG_WRITE(DAL_MSG_REG, msg_id); + + result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000); + + if (result == DALSMC_Result_Failed) { + if (msg_id == DALSMC_MSG_TransferTableDram2Smu && + param == TABLE_WATERMARKS) + DC_LOG_WARNING("Watermarks table not configured properly by SMU"); + REG_WRITE(DAL_RESP_REG, DALSMC_Result_OK); + DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id); + return -1; + } + + if (IS_SMU_TIMEOUT(result)) { + ASSERT(0); + result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000); + //dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); + DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id); + } + + return REG_READ(DAL_ARG_REG); +} + +int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr) +{ + return dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_GetPmfwVersion, + 0); +} + + +int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) +{ + int actual_dispclk_set_mhz = -1; + + if (!clk_mgr->smu_present) + return requested_dispclk_khz; + + /* Unit of SMU msg parameter is Mhz */ + actual_dispclk_set_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDispclkFreq, + khz_to_mhz_ceil(requested_dispclk_khz)); + + smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", + requested_dispclk_khz, actual_dispclk_set_mhz); + return actual_dispclk_set_mhz * 1000; +} + + +int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) +{ + int actual_dcfclk_set_mhz = -1; + + if (!clk_mgr->smu_present) + return requested_dcfclk_khz; + + actual_dcfclk_set_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetHardMinDcfclkByFreq, + khz_to_mhz_ceil(requested_dcfclk_khz)); + + smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", + requested_dcfclk_khz, actual_dcfclk_set_mhz); + + return actual_dcfclk_set_mhz * 1000; +} + +int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) +{ + int actual_min_ds_dcfclk_mhz = -1; + + if (!clk_mgr->smu_present) + return requested_min_ds_dcfclk_khz; + + actual_min_ds_dcfclk_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetMinDeepSleepDcfclk, + khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); + + smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", + requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz); + + return actual_min_ds_dcfclk_mhz * 1000; +} + +int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) +{ + int actual_dppclk_set_mhz = -1; + + if (!clk_mgr->smu_present) + return requested_dpp_khz; + + actual_dppclk_set_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDppclkFreq, + khz_to_mhz_ceil(requested_dpp_khz)); + + smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", + requested_dpp_khz, actual_dppclk_set_mhz); + + return actual_dppclk_set_mhz * 1000; +} + +void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) +{ + if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) + return; + + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDisplayIdleOptimizations, + idle_info); + smu_print("%s: SMC_MSG_SetDisplayIdleOptimizations idle_info = %x\n", __func__, idle_info); +} + +void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) +{ + union display_idle_optimization_u idle_info = { 0 }; + + if (!clk_mgr->smu_present) + return; + + if (enable) { + idle_info.idle_info.df_request_disabled = 1; + idle_info.idle_info.phy_ref_clk_off = 1; + } + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDisplayIdleOptimizations, + idle_info.data); + smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0); +} + +void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_UpdatePmeRestore, + 0); + smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__); +} + +void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetDramAddrHigh, addr_high); +} + +void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetDramAddrLow, addr_low); +} + +void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS); +} + +void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS); +} + +void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support) +{ + unsigned int msg_id, param, retv; + + if (!clk_mgr->smu_present) + return; + + switch (support) { + + case DCN_ZSTATE_SUPPORT_ALLOW: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 10) | (1 << 9) | (1 << 8); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param); + break; + + case DCN_ZSTATE_SUPPORT_DISALLOW: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = 0; + smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n", __func__, param); + break; + + + case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 10); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = 0x%x\n", __func__, param); + break; + + case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 10) | (1 << 8); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = 0x%x\n", __func__, param); + break; + + case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 8); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = 0x%x\n", __func__, param); + break; + + default: //DCN_ZSTATE_SUPPORT_UNKNOWN + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = 0; + break; + } + + + retv = dcn42_smu_send_msg_with_param( + clk_mgr, + msg_id, + param); + smu_print("%s: msg_id = %d, param = 0x%x, return = 0x%x\n", __func__, msg_id, param, retv); +} + +int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) +{ + int dprefclk; + + if (!clk_mgr->smu_present) + return 0; + + dprefclk = dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDprefclkFreq, + 0); + + smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk); + return dprefclk * 1000; +} + +int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) +{ + int dtbclk; + + if (!clk_mgr->smu_present) + return 0; + + dtbclk = dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDtbclkFreq, + 0); + + smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); + return dtbclk * 1000; +} +/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ +void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDtbClk, + enable); + smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0); +} + diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h new file mode 100644 index 0000000000000..8ba7ff04dc05a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef DAL_DC_42_SMU_H_ +#define DAL_DC_42_SMU_H_ + +#include "os_types.h" + +#ifndef PMFW_DRIVER_IF_H +#define PMFW_DRIVER_IF_H +#define PMFW_DRIVER_IF_VERSION 7 + +typedef enum { + DSPCLK_DCFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; // in MHz + uint16_t Vid; // min voltage in SVI3 VID +} DisplayClockTable_t; + +typedef struct { + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t WmType; // Used for normal pstate change or memory retraining + uint8_t Padding[2]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 +#define WM_PSTATE_CHG 0 +#define WM_RETRAINING 1 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + + uint32_t MmHubPadding[7]; // SMU internal use +} Watermarks_t; + +#define NUM_DCFCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS 8 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_VCN_DPM_LEVELS 8 +#define NUM_SOC_VOLTAGE_LEVELS 8 +#define NUM_VPE_DPM_LEVELS 8 +#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_MEM_PSTATE_LEVELS 4 + +typedef enum { + WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1; + WCK_RATIO_1_2, + WCK_RATIO_1_4, + WCK_RATIO_MAX +} WCK_RATIO_e; + +typedef struct { + uint32_t UClk; + uint32_t MemClk; + uint32_t Voltage; + uint8_t WckRatio; + uint8_t Spare[3]; +} MemPstateTable_t; + + + // Watermarks + + +// Freq in MHz +// Voltage in milli volts with 2 fractional bits +typedef struct { + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + uint32_t VClocks[NUM_VCN_DPM_LEVELS]; + uint32_t DClocks[NUM_VCN_DPM_LEVELS]; + uint32_t VPEClocks[NUM_VPE_DPM_LEVELS]; + uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS]; + uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS]; + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; + MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS]; + + uint8_t NumDcfClkLevelsEnabled; + uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk + uint8_t NumSocClkLevelsEnabled; + uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk + + uint8_t VpeClkLevelsEnabled; + uint8_t NumMemPstatesEnabled; + uint8_t NumFclkLevelsEnabled; + uint8_t spare; + + uint32_t MinGfxClk; + uint32_t MaxGfxClk; +} DpmClocks_t_dcn42; + +// Throttler Status Bitmask + + +#define TABLE_BIOS_IF 0 // Called by BIOS +#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS +#define TABLE_CUSTOM_DPM 2 // Called by Driver +#define TABLE_SPARE1 3 +#define TABLE_DPMCLOCKS 4 // Called by Driver +#define TABLE_MOMENTARY_PM 5 // Called by Tools +#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log +#define TABLE_SMU_METRICS 7 // Called by Driver +#define TABLE_COUNT 8 + +#endif + +struct dcn42_watermarks { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + uint32_t MmHubPadding[7]; // SMU internal use +}; + +struct dcn42_smu_dpm_clks { + DpmClocks_t_dcn42 *dpm_clks; + union large_integer mc_address; +}; + +struct display_idle_optimization { + unsigned int df_request_disabled : 1; + unsigned int phy_ref_clk_off : 1; + unsigned int s0i2_rdy : 1; + unsigned int reserved : 29; +}; + +union display_idle_optimization_u { + struct display_idle_optimization idle_info; + uint32_t data; +}; + +int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr); +int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); +int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); +int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); +int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); +void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); +void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); +void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); +void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); +void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); +void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); +void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); + +void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support); +void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); +void dcn42_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); + +int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr); +int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr); + +#endif /* DAL_DC_42_SMU_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c new file mode 100644 index 0000000000000..d1593dc68e361 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn35/dcn35_dccg.h" +#include "dcn42_dccg.h" + +#define TO_DCN_DCCG(dccg)\ + container_of(dccg, struct dcn_dccg, base) + +#define REG(reg) \ + (dccg_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name + +#define CTX \ + dccg_dcn->base.ctx +#define DC_LOGGER \ + dccg->ctx->logger + +void dccg42_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (otg_inst) { + case 0: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG0_ADD_PIXEL, 1); + break; + case 1: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG1_ADD_PIXEL, 1); + break; + case 2: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG2_ADD_PIXEL, 1); + break; + case 3: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG3_ADD_PIXEL, 1); + break; + default: + ASSERT(0); + } +} + +void dccg42_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (otg_inst) { + case 0: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG0_DROP_PIXEL, 1); + break; + case 1: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG1_DROP_PIXEL, 1); + break; + case 2: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG2_DROP_PIXEL, 1); + break; + case 3: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG3_DROP_PIXEL, 1); + break; + default: + ASSERT(0); + } +} + +void dccg42_enable_global_fgcg(struct dccg *dccg, bool value) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (dccg->ctx->dc->debug.disable_clock_gate) + value = false; + REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); +} + +void dccg42_set_physymclk( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (phy_inst) { + case 0: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYASYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, + PHYASYMCLK_EN, 1, + PHYASYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, + PHYASYMCLK_EN, 0, + PHYASYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYASYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 1: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYBSYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, + PHYBSYMCLK_EN, 1, + PHYBSYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, + PHYBSYMCLK_EN, 0, + PHYBSYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYBSYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 2: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYCSYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, + PHYCSYMCLK_EN, 1, + PHYCSYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, + PHYCSYMCLK_EN, 0, + PHYCSYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYCSYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 3: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYDSYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, + PHYDSYMCLK_EN, 1, + PHYDSYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, + PHYDSYMCLK_EN, 0, + PHYDSYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYDSYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 4: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYESYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, + PHYESYMCLK_EN, 1, + PHYESYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, + PHYESYMCLK_EN, 0, + PHYESYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYESYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +static void dccg42_init(struct dccg *dccg) +{ + int otg_inst; + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* Set HPO stream encoder to use refclk to avoid case where PHY is + * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which + * will cause DCN to hang. + */ + for (otg_inst = 0; otg_inst < 4; otg_inst++) + dccg35_disable_symclk32_se(dccg, otg_inst); + + if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) { + dccg401_disable_symclk32_le(dccg, 0); + dccg401_disable_symclk32_le(dccg, 1); + dccg401_disable_symclk32_le(dccg, 2); + dccg401_disable_symclk32_le(dccg, 3); + } + + if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) { + dccg401_disable_dpstreamclk(dccg, 0); + dccg401_disable_dpstreamclk(dccg, 1); + dccg401_disable_dpstreamclk(dccg, 2); + dccg401_disable_dpstreamclk(dccg, 3); + } + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) { + REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, + PHYASYMCLK_ROOT_GATE_DISABLE, 1, + PHYBSYMCLK_ROOT_GATE_DISABLE, 1, + PHYCSYMCLK_ROOT_GATE_DISABLE, 1, + PHYDSYMCLK_ROOT_GATE_DISABLE, 1, + PHYESYMCLK_ROOT_GATE_DISABLE, 1); + } +} + + +static const struct dccg_funcs dccg42_funcs = { + .update_dpp_dto = dccg35_update_dpp_dto, + .dpp_root_clock_control = dccg35_dpp_root_clock_control, + .get_dccg_ref_freq = dccg401_get_dccg_ref_freq, + .dccg_init = dccg42_init, + .set_dpstreamclk = dccg401_set_dpstreamclk, + /* Redundant with above^ */ + /* .set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating, */ + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg35_disable_symclk32_se, + .enable_symclk32_le = dccg401_enable_symclk32_le, + .disable_symclk32_le = dccg401_disable_symclk32_le, + .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating, + .set_physymclk = dccg42_set_physymclk, + .set_dtbclk_dto = NULL, + .set_dto_dscclk = dccg401_set_dto_dscclk, + .set_ref_dscclk = dccg401_set_ref_dscclk, + .set_valid_pixel_rate = NULL, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .set_audio_dtbclk_dto = NULL, + .otg_add_pixel = dccg42_otg_add_pixel, + .otg_drop_pixel = dccg42_otg_drop_pixel, + .disable_dsc = dccg35_disable_dscclk, + .enable_dsc = dccg35_enable_dscclk, + .set_pixel_rate_div = dccg401_set_pixel_rate_div, + .get_pixel_rate_div = dccg401_get_pixel_rate_div, + .trigger_dio_fifo_resync = dccg35_trigger_dio_fifo_resync, + .set_dp_dto = dccg401_set_dp_dto, + .enable_symclk_se = dccg35_enable_symclk_se, + .disable_symclk_se = dccg35_disable_symclk_se, + .set_dtbclk_p_src = dccg401_set_dtbclk_p_src, + .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, + .dccg_read_reg_state = dccg31_read_reg_state, + .dccg_enable_global_fgcg = dccg42_enable_global_fgcg, +}; + +struct dccg *dccg42_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask) +{ + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); + struct dccg *base; + + if (dccg_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &dccg_dcn->base; + base->ctx = ctx; + base->funcs = &dccg42_funcs; + + dccg_dcn->regs = regs; + dccg_dcn->dccg_shift = dccg_shift; + dccg_dcn->dccg_mask = dccg_mask; + + return &dccg_dcn->base; +} diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h new file mode 100644 index 0000000000000..96eae0003f439 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024-2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN42_DCCG_H__ +#define __DCN42_DCCG_H__ + +#include "dcn401/dcn401_dccg.h" + +#define DCCG_MASK_SH_LIST_DCN42_COMMON(mask_sh) \ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE2_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE3_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE2_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE3_EN, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG0_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG1_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG2_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG3_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG0_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG1_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG2_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG3_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO0_INT, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO1_INT, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO2_INT, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO3_INT, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\ + DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\ + DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh) + +#define DCCG_MASK_SH_LIST_DCN42(mask_sh) \ + DCCG_MASK_SH_LIST_DCN42_COMMON(mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh) + + +void dccg42_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst); + +void dccg42_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst); +void dccg42_enable_global_fgcg(struct dccg *dccg, bool value); + +void dccg42_set_physymclk( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable); + +struct dccg *dccg42_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask); + +#endif //__DCN42_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c new file mode 100644 index 0000000000000..35dfe3bb0c555 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" + +#include "core_types.h" +#include "link_encoder.h" +#include "dcn35/dcn35_dio_link_encoder.h" +#include "dcn42_dio_link_encoder.h" + +#ifndef MIN +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#endif + +#define CTX \ + enc10->base.ctx +#define DC_LOGGER \ + enc10->base.ctx->logger + +#define REG(reg)\ + (enc10->link_regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc10->link_shift->field_name, enc10->link_mask->field_name + +#define HPD_REG(reg)\ + (enc10->hpd_regs->reg) + +#define HPD_REG_GET(reg_name, field, val) \ + generic_reg_get(CTX, HPD_REG(reg_name), \ + FN(reg_name, field), val) + +#define HPD_REG_SET_N(reg_name, n, initial_val, ...) \ + generic_reg_set_ex(CTX, \ + HPD_REG(reg_name), \ + initial_val, \ + n, __VA_ARGS__) + +#define HPD_REG_SET_2(reg, init_value, f1, v1, f2, v2) \ + HPD_REG_SET_N(reg, 2, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2) + +bool dcn42_get_hpd_state(struct link_encoder *enc) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + uint32_t state; + + HPD_REG_GET(DC_HPD_INT_STATUS, DC_HPD_SENSE, &state); + + return state; +} + +bool dcn42_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + + HPD_REG_SET_2(DC_HPD_TOGGLE_FILT_CNTL, 0, + DC_HPD_CONNECT_INT_DELAY, delay_on_connect_in_ms, + DC_HPD_DISCONNECT_INT_DELAY, delay_on_disconnect_in_ms); + + return true; +} + +static const struct link_encoder_funcs dcn42_link_enc_funcs = { + .read_state = link_enc2_read_state, + .validate_output_with_stream = + dcn30_link_encoder_validate_output_with_stream, + .hw_init = dcn35_link_encoder_init, + .setup = dcn35_link_encoder_setup, + .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, + .enable_dp_output = dcn35_link_encoder_enable_dp_output, + .enable_dp_mst_output = dcn35_link_encoder_enable_dp_mst_output, + .disable_output = dcn35_link_encoder_disable_output, + .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dcn10_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dcn10_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, + .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, + .enable_hpd = dcn10_link_encoder_enable_hpd, + .disable_hpd = dcn10_link_encoder_disable_hpd, + .is_dig_enabled = dcn35_is_dig_enabled, + .destroy = dcn10_link_encoder_destroy, + .fec_set_enable = enc2_fec_set_enable, + .fec_set_ready = enc2_fec_set_ready, + .fec_is_active = enc2_fec_is_active, + .get_dig_frontend = dcn10_get_dig_frontend, + .get_dig_mode = dcn401_get_dig_mode, + .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, + .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, + .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .enable_dpia_output = dcn35_link_encoder_enable_dpia_output, + .disable_dpia_output = dcn35_link_encoder_disable_dpia_output, + .get_hpd_state = dcn42_get_hpd_state, + .program_hpd_filter = dcn42_program_hpd_filter, +}; + +void dcn42_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask) +{ + struct bp_connector_speed_cap_info bp_cap_info = {0}; + const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; + enum bp_result result = BP_RESULT_OK; + struct dcn10_link_encoder *enc10 = &enc20->enc10; + + enc10->base.funcs = &dcn42_link_enc_funcs; + enc10->base.ctx = init_data->ctx; + enc10->base.id = init_data->encoder; + + enc10->base.hpd_source = init_data->hpd_source; + enc10->base.connector = init_data->connector; + + + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + + enc10->base.features = *enc_features; + if (enc10->base.connector.id == CONNECTOR_ID_USBC) + enc10->base.features.flags.bits.DP_IS_USB_C = 1; + + enc10->base.transmitter = init_data->transmitter; + + /* set the flag to indicate whether driver poll the I2C data pin + * while doing the DP sink detect + */ + +/* if (dal_adapter_service_is_feature_supported(as, + FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) + enc10->base.features.flags.bits. + DP_SINK_DETECT_POLL_DATA_PIN = true;*/ + + enc10->base.output_signals = + SIGNAL_TYPE_DVI_SINGLE_LINK | + SIGNAL_TYPE_DVI_DUAL_LINK | + SIGNAL_TYPE_LVDS | + SIGNAL_TYPE_DISPLAY_PORT | + SIGNAL_TYPE_DISPLAY_PORT_MST | + SIGNAL_TYPE_EDP | + SIGNAL_TYPE_HDMI_TYPE_A; + + enc10->link_regs = link_regs; + enc10->aux_regs = aux_regs; + enc10->hpd_regs = hpd_regs; + enc10->link_shift = link_shift; + enc10->link_mask = link_mask; + + switch (enc10->base.transmitter) { + case TRANSMITTER_UNIPHY_A: + enc10->base.preferred_engine = ENGINE_ID_DIGA; + break; + case TRANSMITTER_UNIPHY_B: + enc10->base.preferred_engine = ENGINE_ID_DIGB; + break; + case TRANSMITTER_UNIPHY_C: + enc10->base.preferred_engine = ENGINE_ID_DIGC; + break; + case TRANSMITTER_UNIPHY_D: + enc10->base.preferred_engine = ENGINE_ID_DIGD; + break; + case TRANSMITTER_UNIPHY_E: + enc10->base.preferred_engine = ENGINE_ID_DIGE; + break; + default: + ASSERT_CRITICAL(false); + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + } + + /* default to one to mirror Windows behavior */ + enc10->base.features.flags.bits.HDMI_6GB_EN = 1; + + if (bp_funcs->get_connector_speed_cap_info) + result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, + enc10->base.connector, &bp_cap_info); + + /* Override features with DCE-specific values */ + if (result == BP_RESULT_OK) { + enc10->base.features.flags.bits.IS_HBR2_CAPABLE = + bp_cap_info.DP_HBR2_EN; + enc10->base.features.flags.bits.IS_HBR3_CAPABLE = + bp_cap_info.DP_HBR3_EN; + enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; + enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, + result); + } + if (enc10->base.ctx->dc->debug.hdmi20_disable) { + enc10->base.features.flags.bits.HDMI_6GB_EN = 0; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h new file mode 100644 index 0000000000000..4b5a9594f2790 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DC_LINK_ENCODER__DCN42_H__ +#define __DC_LINK_ENCODER__DCN42_H__ + +#include "dcn401/dcn401_dio_link_encoder.h" + +#define LINK_ENCODER_MASK_SH_LIST_DCN42(mask_sh) \ + LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\ + LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\ + LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ + LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, HDCP_SOFT_RESET, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_HDCP_CLOCK_ON, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\ + LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ + LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ + LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ + LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ + LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ + LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ + LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ + LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ + LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ + LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ + LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ + LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ + LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ + LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ + LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ + LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ + LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ + LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ + LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ + LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\ + LE_SF(HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\ + LE_SF(HPD0_DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\ + LE_SF(HPD0_DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ + LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DISPCLK_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DISPCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, REFCLK_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, REFCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SOCCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_FE_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_FE_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DISPCLK_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKA_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKB_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh) + +void dcn42_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask); + +bool dcn42_get_hpd_state(struct link_encoder *enc); +bool dcn42_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); + +#endif /* __DC_LINK_ENCODER__DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c new file mode 100644 index 0000000000000..65afbfcaa96b0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dc_bios_types.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn32/dcn32_dio_stream_encoder.h" +#include "dcn35/dcn35_dio_stream_encoder.h" +#include "dcn401/dcn401_dio_stream_encoder.h" +#include "dcn31/dcn31_apg.h" + +#include "dcn42_dio_stream_encoder.h" +#include "reg_helper.h" +#include "hw_shared.h" +#include "link_service.h" +#include "dpcd_defs.h" + +#define DC_LOGGER \ + enc1->base.ctx->logger + +#define REG(reg)\ + (enc1->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc1->se_shift->field_name, enc1->se_mask->field_name + +#define VBI_LINE_0 0 +#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 + +#define CTX \ + enc1->base.ctx + +/* setup stream encoder in hdmi mode */ +static void enc42_stream_encoder_hdmi_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + int actual_pix_clk_khz, + bool enable_audio) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { + struct bp_encoder_control cntl = {0}; + + cntl.action = ENCODER_CONTROL_SETUP; + cntl.engine_id = enc1->base.id; + cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; + cntl.enable_dp_audio = enable_audio; + cntl.pixel_clock = actual_pix_clk_khz; + cntl.lanes_number = LANE_COUNT_FOUR; + + if (enc1->base.bp->funcs->encoder_control( + enc1->base.bp, &cntl) != BP_RESULT_OK) + return; + + } else { + + //Set pattern for clock channel, default vlue 0x63 does not work + REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); + + //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup + + //DIG_SOURCE_SELECT is already set in dig_connect_to_otg + + /* DIG_START is removed from the register spec */ + } + + /* Configure pixel encoding */ + enc401_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); + + /* setup HDMI engine */ + REG_UPDATE_4(HDMI_CONTROL, + HDMI_DEEP_COLOR_ENABLE, 0, + HDMI_DATA_SCRAMBLE_EN, 0, + HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, + HDMI_CLOCK_CHANNEL_RATE, 0); + + /* Configure color depth */ + switch (crtc_timing->display_color_depth) { + case COLOR_DEPTH_888: + REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); + break; + case COLOR_DEPTH_101010: + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 1); + } + break; + case COLOR_DEPTH_121212: + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 1); + } + break; + case COLOR_DEPTH_161616: + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 3, + HDMI_DEEP_COLOR_ENABLE, 1); + break; + default: + break; + } + + if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { + /* enable HDMI data scrambler + * HDMI_CLOCK_CHANNEL_RATE_MORE_340M + * Clock channel frequency is 1/4 of character rate. + */ + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DATA_SCRAMBLE_EN, 1, + HDMI_CLOCK_CHANNEL_RATE, 1); + } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { + + /* TODO: New feature for DCE11, still need to implement */ + + /* enable HDMI data scrambler + * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE + * Clock channel frequency is the same + * as character rate + */ + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DATA_SCRAMBLE_EN, 1, + HDMI_CLOCK_CHANNEL_RATE, 0); + } + + /* Enable transmission of General Control packet on every frame */ + REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, + HDMI_GC_CONT, 1, + HDMI_GC_SEND, 1, + HDMI_NULL_SEND, 1); + + /* Disable Audio Content Protection packet transmission */ + REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); + /* following belongs to audio */ + /* Enable Audio InfoFrame packet transmission. */ + REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); + + /* Select line number on which to send Audio InfoFrame packets */ + REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_LINE, + VBI_LINE_0 + 2); + + /* set HDMI GC AVMUTE */ + REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); +} + +static void enc42_stream_encoder_stop_dp_info_packets( + struct stream_encoder *enc) +{ + /* stop generic packets on DP */ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t value = 0; + + REG_SET_9(DP_SEC_CNTL, 0, + DP_SEC_GSP0_ENABLE, 0, + DP_SEC_GSP1_ENABLE, 0, + DP_SEC_GSP2_ENABLE, 0, + DP_SEC_GSP3_ENABLE, 0, + DP_SEC_GSP4_ENABLE, 0, + DP_SEC_GSP5_ENABLE, 0, + DP_SEC_GSP6_ENABLE, 0, + DP_SEC_GSP7_ENABLE, 0, + DP_SEC_STREAM_ENABLE, 0); + + /* this register shared with audio info frame. + * therefore we need to keep master enabled + * if at least one of the fields is not 0 + */ + value = REG_READ(DP_SEC_CNTL); + if (value) + REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); +} + +static void enc42_stream_encoder_update_hdmi_info_packets( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); + REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, 1); + + /*Always add mandatory packets first followed by optional ones*/ + enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi); + enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif); + enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); + enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); + enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd); + enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); + enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem); +} + +static void enc42_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps, + bool immediate_update) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (enable) { + struct dc_info_packet pps_sdp; + int i; + + /* Configure for PPS packet size (128 bytes) */ + REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1); + + /* Load PPS into infoframe (SDP) registers */ + pps_sdp.valid = true; + pps_sdp.hb0 = 0; + pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; + pps_sdp.hb2 = 127; + pps_sdp.hb3 = 0; + + for (i = 0; i < 4; i++) { + memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32); + enc1->base.vpg->funcs->update_generic_info_packet( + enc1->base.vpg, + 11 + i, + &pps_sdp, + immediate_update); + } + + /* SW should make sure VBID[6] update line number is bigger + * than PPS transmit line number + */ + REG_UPDATE(DP_GSP11_CNTL, + DP_SEC_GSP11_LINE_NUM, 2); + REG_UPDATE_2(DP_MSA_VBID_MISC, + DP_VBID6_LINE_REFERENCE, 0, + DP_VBID6_LINE_NUM, 3); + + /* Send PPS data at the line number specified above. + * DP spec requires PPS to be sent only when it changes, however since + * decoder has to be able to handle its change on every frame, we're + * sending it always (i.e. on every frame) to reduce the chance it'd be + * missed by decoder. If it turns out required to send PPS only when it + * changes, we can use DP_SEC_GSP11_SEND register. + */ + REG_UPDATE(DP_GSP11_CNTL, + DP_SEC_GSP11_ENABLE, 1); + REG_UPDATE(DP_SEC_CNTL, + DP_SEC_STREAM_ENABLE, 1); + } else { + /* Disable Generic Stream Packet 11 (GSP) transmission */ + REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0); + REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0); + } +} + +static void enc42_se_dp_audio_setup( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + enc42_se_enable_audio_clock(enc, true); + + REG_UPDATE(DIG_FE_AUDIO_CNTL, + DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst); + + enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info); +} + +#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 + +static void enc42_se_setup_dp_audio( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + /* --- DP Audio packet configurations --- */ + + /* ATP Configuration */ + REG_SET(DP_SEC_AUD_N, 0, + DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); + + /* Async/auto-calc timestamp mode */ + REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, + DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); +} + +static void enc42_se_dp_audio_enable( + struct stream_encoder *enc) +{ + ASSERT (enc->apg); + enc42_se_enable_audio_clock(enc, true); + /*APG_CONTROL2 for DP*/ + enc42_se_setup_dp_audio(enc); + /*DP_SEC_CNTL programming*/ + enc1_se_enable_dp_audio(enc); + /*APG_en*/ + enc->apg->funcs->enable_apg(enc->apg); + +} + +static void enc42_se_disable_dp_audio( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t value = 0; + + /* Disable Audio packets */ + REG_UPDATE_5(DP_SEC_CNTL, + DP_SEC_ASP_ENABLE, 0, + DP_SEC_ATP_ENABLE, 0, + DP_SEC_AIP_ENABLE, 0, + DP_SEC_ACM_ENABLE, 0, + DP_SEC_STREAM_ENABLE, 0); + + /* This register shared with encoder info frame. Therefore we need to + * keep master enabled if at least on of the fields is not 0 + */ + value = REG_READ(DP_SEC_CNTL); + if (value != 0) + REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); +} + +static void enc42_se_dp_audio_disable( + struct stream_encoder *enc) +{ + + enc->apg->funcs->disable_apg(enc->apg); + enc42_se_disable_dp_audio(enc); + enc42_se_enable_audio_clock(enc, false); +} + +static void enc42_se_setup_hdmi_audio( + struct stream_encoder *enc, + const struct audio_crtc_info *crtc_info) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + struct audio_clock_info audio_clock_info = {0}; + + /* HDMI_AUDIO_PACKET_CONTROL */ + REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, + HDMI_AUDIO_DELAY_EN, 1); + + /* HDMI_ACR_PACKET_CONTROL */ + REG_UPDATE_2(HDMI_ACR_PACKET_CONTROL, + HDMI_ACR_AUTO_SEND, 1, + HDMI_ACR_SOURCE, 0); + + /* Program audio clock sample/regeneration parameters */ + get_audio_clock_info(crtc_info->color_depth, + crtc_info->requested_pixel_clock_100Hz, + crtc_info->calculated_pixel_clock_100Hz, + &audio_clock_info); + DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d" \ + "calculated_pixel_clock_100Hz = %d\n", __func__,\ + crtc_info->requested_pixel_clock_100Hz, \ + crtc_info->calculated_pixel_clock_100Hz); + + /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ + REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); + + /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ + REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); + + /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ + REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); + + /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ + REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); + + /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ + REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); + + /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ + REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); + + /* Video driver cannot know in advance which sample rate will + * be used by HD Audio driver + * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is + * programmed below in interruppt callback + */ +} + +static void enc42_se_hdmi_audio_disable( + struct stream_encoder *enc) +{ + ASSERT (enc->apg); + enc->apg->funcs->disable_apg(enc->apg); + enc42_se_enable_audio_clock(enc, false); +} + +void enc42_se_enable_audio_clock( + struct stream_encoder *enc, + bool enable) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, !!enable); +} + + +static void enc42_se_hdmi_audio_setup( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info, + struct audio_crtc_info *audio_crtc_info) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + ASSERT (enc->apg); + enc42_se_enable_audio_clock(enc, true); + /*ACR setup*/ + enc42_se_setup_hdmi_audio(enc, audio_crtc_info); + + REG_UPDATE(DIG_FE_AUDIO_CNTL, + DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst); + + /*APG_DBG_GEN_CONTROL*/ + enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info); + /*APG enable*/ + enc->apg->funcs->enable_apg(enc->apg); +} + +static void enc42_audio_mute_control( + struct stream_encoder *enc, + bool mute) +{ + if (mute) + enc->apg->funcs->disable_apg(enc->apg); + else + enc->apg->funcs->enable_apg(enc->apg); +} +void enc42_reset_hdmi_stream_attribute( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE_3(HDMI_CONTROL, + HDMI_DEEP_COLOR_ENABLE, 0, + HDMI_DATA_SCRAMBLE_EN, 0, + HDMI_CLOCK_CHANNEL_RATE, 0); +} + +static const struct stream_encoder_funcs dcn42_str_enc_funcs = { + .dp_set_stream_attribute = + enc401_stream_encoder_dp_set_stream_attribute, + .hdmi_set_stream_attribute = + enc42_stream_encoder_hdmi_set_stream_attribute, + .dvi_set_stream_attribute = + enc401_stream_encoder_dvi_set_stream_attribute, + .set_throttled_vcp_size = + enc1_stream_encoder_set_throttled_vcp_size, + .update_hdmi_info_packets = + enc42_stream_encoder_update_hdmi_info_packets, + .stop_hdmi_info_packets = + enc3_stream_encoder_stop_hdmi_info_packets, + .update_dp_info_packets_sdp_line_num = + enc3_stream_encoder_update_dp_info_packets_sdp_line_num, + .update_dp_info_packets = + enc3_stream_encoder_update_dp_info_packets, + .stop_dp_info_packets = + enc42_stream_encoder_stop_dp_info_packets, + .dp_blank = + enc1_stream_encoder_dp_blank, + .dp_unblank = + enc401_stream_encoder_dp_unblank, + .audio_mute_control = enc42_audio_mute_control, + + .dp_audio_setup = enc42_se_dp_audio_setup, + .dp_audio_enable = enc42_se_dp_audio_enable, + .dp_audio_disable = enc42_se_dp_audio_disable, + + .hdmi_audio_setup = enc42_se_hdmi_audio_setup, + .hdmi_audio_disable = enc42_se_hdmi_audio_disable, + .setup_stereo_sync = enc1_setup_stereo_sync, + .set_avmute = enc1_stream_encoder_set_avmute, + .dig_connect_to_otg = enc1_dig_connect_to_otg, + .dig_source_otg = enc1_dig_source_otg, + + .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, + + .enc_read_state = enc401_read_state, + .dp_set_dsc_config = NULL, + .dp_set_dsc_pps_info_packet = enc42_dp_set_dsc_pps_info_packet, + .set_dynamic_metadata = enc401_set_dynamic_metadata, + .hdmi_reset_stream_attribute = enc42_reset_hdmi_stream_attribute, + .enable_stream = enc401_stream_encoder_enable, + + .set_input_mode = enc401_set_dig_input_mode, + .enable_fifo = enc35_enable_fifo, + .disable_fifo = enc35_disable_fifo, + .map_stream_to_link = enc401_stream_encoder_map_to_link, +}; + +void dcn42_dio_stream_encoder_construct( + struct dcn10_stream_encoder *enc1, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id, + struct vpg *vpg, + struct apg *apg, + const struct dcn10_stream_enc_registers *regs, + const struct dcn10_stream_encoder_shift *se_shift, + const struct dcn10_stream_encoder_mask *se_mask) +{ + enc1->base.funcs = &dcn42_str_enc_funcs; + enc1->base.ctx = ctx; + enc1->base.id = eng_id; + enc1->base.bp = bp; + enc1->base.vpg = vpg; + enc1->base.apg = apg; + enc1->regs = regs; + enc1->se_shift = se_shift; + enc1->se_mask = se_mask; + enc1->base.stream_enc_inst = vpg->inst; +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h new file mode 100644 index 0000000000000..7a98fee46081f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 - Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DIO_STREAM_ENCODER_DCN42_H__ +#define __DC_DIO_STREAM_ENCODER_DCN42_H__ + +#include "dcn30/dcn30_vpg.h" +#include "stream_encoder.h" +#include "dcn20/dcn20_stream_encoder.h" + +#define SE_COMMON_MASK_SH_LIST_DCN42(mask_sh)\ + SE_SF(DP0_DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_FORMAT, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, COMPRESSED_PIXEL_FORMAT, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ + SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ + SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ + SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ + SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(DIG1_HDMI_CONTROL, TMDS_PIXEL_ENCODING, mask_sh),\ + SE_SF(DIG1_HDMI_CONTROL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\ + SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\ + SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ + SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_N_INTERVAL, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\ + SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, DOLBY_VISION_EN, mask_sh),\ + SE_SF(DIG0_DIG_FE_EN_CNTL, DIG_FE_ENABLE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_MODE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, mask_sh),\ + SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SOFT_RESET, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\ + SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\ + SE_SF(DIG0_STREAM_MAPPER_CONTROL, DIG_STREAM_LINK_TARGET, mask_sh),\ + SE_SF(DIG0_DIG_FE_AUDIO_CNTL, DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, mask_sh),\ + SE_SF(DIG0_DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, mask_sh) + +void dcn42_dio_stream_encoder_construct( + struct dcn10_stream_encoder *enc1, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id, + struct vpg *vpg, + struct apg *apg, + const struct dcn10_stream_enc_registers *regs, + const struct dcn10_stream_encoder_shift *se_shift, + const struct dcn10_stream_encoder_mask *se_mask); + +void enc42_se_enable_audio_clock( + struct stream_encoder *enc, + bool enable); + +void enc42_reset_hdmi_stream_attribute( + struct stream_encoder *enc); +#endif /* __DC_DIO_STREAM_ENCODER_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c new file mode 100644 index 0000000000000..244c91b762b06 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "core_types.h" +#include "reg_helper.h" +#include "dcn42_dpp.h" +#include "dcn35/dcn35_dpp.h" + +#define REG(reg)\ + dpp->tf_regs->reg + +#define CTX \ + dpp->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + dpp->tf_shift->field_name, dpp->tf_mask->field_name + +static const uint32_t *get_hist_rgb_luma_coefs(enum dc_color_space color_space) +{ + // Coefs in s.6.12. + // Y = 0.2126R + 0.7152G + 0.0722B + static const uint32_t luma_transform_bt_709[] = {0x1cb36, 0x1e6e2, 0x1b27b}; + // Y = 0.2627R + 0.678G + 0.0593B + static const uint32_t luma_transform_bt_2020[] = {0x1d0d0, 0x1e5b2, 0x1ae5c}; + + switch (color_space) { + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + return luma_transform_bt_2020; + default: + return luma_transform_bt_709; + } +} + +static void dpp42_dpp_cm_hist_control( + struct dpp *dpp_base, + struct cm_hist_control cntl, + enum dc_color_space color_space) +{ + struct dcn42_dpp *dpp = TO_DCN42_DPP(dpp_base); + + REG_UPDATE_10( + CM_HIST_CNTL, + CM_HIST_SEL, cntl.tap_point, + CM_HIST_CH_EN, cntl.channels_enabled, + CM_HIST_SRC1_SEL, cntl.src_1_select, + CM_HIST_SRC2_SEL, cntl.src_2_select, + CM_HIST_SRC3_SEL, cntl.src_3_select, + CM_HIST_CH1_XBAR, cntl.ch1_src, + CM_HIST_CH2_XBAR, cntl.ch2_src, + CM_HIST_CH3_XBAR, cntl.ch3_src, + CM_HIST_FORMAT, cntl.format, + CM_HIST_READ_CHANNEL_MASK, cntl.read_channel_mask); + + if (cntl.src_2_select == CM_HIST_SRC2_MODE_RGB_TO_Y) { + const uint32_t *luma_transform = get_hist_rgb_luma_coefs(color_space); + + REG_UPDATE(CM_HIST_COEFA_SRC2, CM_HIST_COEFA_SRC2, luma_transform[0]); + REG_UPDATE(CM_HIST_COEFB_SRC2, CM_HIST_COEFB_SRC2, luma_transform[1]); + REG_UPDATE(CM_HIST_COEFC_SRC2, CM_HIST_COEFC_SRC2, luma_transform[2]); + } else { + REG_UPDATE(CM_HIST_COEFA_SRC2, CM_HIST_COEFA_SRC2, 0); + REG_UPDATE(CM_HIST_COEFB_SRC2, CM_HIST_COEFB_SRC2, 0x1f000); // 1 in s.6.12 + REG_UPDATE(CM_HIST_COEFC_SRC2, CM_HIST_COEFC_SRC2, 0); + } +} + +static bool dpp42_dpp_cm_hist_read(struct dpp *dpp_base, struct cm_hist *hist_out) +{ + struct dcn42_dpp *dpp = TO_DCN42_DPP(dpp_base); + uint32_t channel_mask = 0; + uint32_t rdy_status = 0, rdy_status_a = 0, rdy_status_b = 0; + bool ch1, ch2, ch3; + + if (hist_out == NULL) + return false; + + + REG_GET(CM_HIST_CNTL, CM_HIST_READ_CHANNEL_MASK, &channel_mask); + ch1 = (channel_mask & 1) > 0; + ch2 = (channel_mask & 2) > 0; + ch3 = (channel_mask & 4) > 0; + + REG_GET(CM_HIST_STATUS, CM_HIST_BUFA_RDY_STATUS, &rdy_status_a); + REG_GET(CM_HIST_STATUS, CM_HIST_BUFB_RDY_STATUS, &rdy_status_b); + + rdy_status = rdy_status_a || rdy_status_b; + + if (rdy_status) { + REG_UPDATE(CM_HIST_LOCK, CM_HIST_LOCK, 1); + REG_UPDATE(CM_HIST_INDEX, CM_HIST_INDEX, 0); + for (int i = 0; i < 256; i++) { + uint32_t temp; + + if (ch1) { + REG_GET(CM_HIST_DATA, CM_HIST_DATA, &temp); + hist_out->ch1[i] += temp; + } + if (ch2) { + REG_GET(CM_HIST_DATA, CM_HIST_DATA, &temp); + hist_out->ch2[i] += temp; + } + if (ch3) { + REG_GET(CM_HIST_DATA, CM_HIST_DATA, &temp); + hist_out->ch3[i] += temp; + } + } + REG_UPDATE(CM_HIST_LOCK, CM_HIST_LOCK, 0); + return true; + } else { + return false; + } +} + +static void dpp42_dpp_setup( + struct dpp *dpp_base, + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + uint32_t pixel_format = 0; + uint32_t alpha_en = 1; + enum dc_color_space color_space = COLOR_SPACE_SRGB; + enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; + uint32_t is_2bit = 0; + uint32_t alpha_plane_enable = 0; + uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; + uint32_t realpha_en = 0, realpha_ablnd_en = 0; + uint32_t program_prealpha_dealpha = 0; + struct out_csc_color_matrix tbl_entry; + int i; + + REG_SET_2(FORMAT_CONTROL, 0, + CNVC_BYPASS, 0, + FORMAT_EXPANSION_MODE, mode); + + REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); + REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); + REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); + REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); + + REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); + + switch (format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + pixel_format = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + pixel_format = 3; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + pixel_format = 8; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + pixel_format = 10; + is_2bit = 1; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + pixel_format = 65; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + pixel_format = 64; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + pixel_format = 67; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + pixel_format = 66; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + pixel_format = 26; /* ARGB16161616_UNORM */ + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + pixel_format = 24; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + pixel_format = 25; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + pixel_format = 12; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + pixel_format = 112; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + pixel_format = 113; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + pixel_format = 114; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + is_2bit = 1; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + pixel_format = 115; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + is_2bit = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE: + pixel_format = 116; + alpha_plane_enable = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + pixel_format = 116; + alpha_plane_enable = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + pixel_format = 118; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + pixel_format = 119; + alpha_en = 0; + break; + default: + break; + } + + /* Set default color space based on format if none is given. */ + color_space = input_color_space ? input_color_space : color_space; + + if (is_2bit == 1 && alpha_2bit_lut != NULL) { + REG_UPDATE(ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); + REG_UPDATE(ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); + REG_UPDATE(ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); + REG_UPDATE(ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); + } + + REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, + CNVC_SURFACE_PIXEL_FORMAT, pixel_format, + CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); + + if (program_prealpha_dealpha) { + dealpha_en = 1; + realpha_en = 1; + } + REG_SET_2(PRE_DEALPHA, 0, + PRE_DEALPHA_EN, dealpha_en, + PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); + REG_SET_2(PRE_REALPHA, 0, + PRE_REALPHA_EN, realpha_en, + PRE_REALPHA_ABLND_EN, realpha_ablnd_en); + + /* If input adjustment exists, program the ICSC with those values. */ + if (input_csc_color_matrix.enable_adjustment == true) { + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; + + tbl_entry.color_space = input_color_space; + + if (color_space >= COLOR_SPACE_YCBCR601) + select = INPUT_CSC_SELECT_ICSC; + else + select = INPUT_CSC_SELECT_BYPASS; + + dpp3_program_post_csc(dpp_base, color_space, select, + &tbl_entry); + } else { + dpp3_program_post_csc(dpp_base, color_space, select, NULL); + } +} + +static struct dpp_funcs dcn42_dpp_funcs = { + .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, + .dpp_read_state = dpp401_read_state, + .dpp_reset = dpp_reset, + .dpp_set_scaler = dpp401_dscl_set_scaler_manual_scale, + .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, + .dpp_set_pre_degam = dpp3_set_pre_degam, + .dpp_setup = dpp42_dpp_setup, + .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, + .dpp_program_cm_bias = dpp3_program_cm_bias, + .dpp_program_bias_and_scale = dpp35_program_bias_and_scale_fcnv, + .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, + .set_cursor_attributes = dpp401_set_cursor_attributes, + .set_cursor_position = dpp401_set_cursor_position, + .set_optional_cursor_attributes = dpp401_set_optional_cursor_attributes, + .dpp_dppclk_control = dpp35_dppclk_control, + .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, + .set_cursor_matrix = dpp401_set_cursor_matrix, + .dpp_cm_hist_control = dpp42_dpp_cm_hist_control, + .dpp_cm_hist_read = dpp42_dpp_cm_hist_read, + .dpp_read_reg_state = dpp30_read_reg_state, +}; + + +static struct dpp_caps dcn42_dpp_cap = { + .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, + .max_lb_partitions = 63, + .dscl_calc_lb_num_partitions = dscl401_calc_lb_num_partitions, +}; + +bool dpp42_construct( + struct dcn42_dpp *dpp, + struct dc_context *ctx, + uint32_t inst, + const struct dcn42_dpp_registers *tf_regs, + const struct dcn42_dpp_shift *tf_shift, + const struct dcn42_dpp_mask *tf_mask) +{ + dpp->base.ctx = ctx; + + dpp->base.inst = inst; + dpp->base.funcs = &dcn42_dpp_funcs; + dpp->base.caps = &dcn42_dpp_cap; + + dpp->tf_regs = tf_regs; + dpp->tf_shift = tf_shift; + dpp->tf_mask = tf_mask; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h new file mode 100644 index 0000000000000..f4ee419eabf77 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DCN42_DPP_H__ +#define __DCN42_DPP_H__ + +#include "dcn401/dcn401_dpp.h" + +#define TO_DCN42_DPP(dpp)\ + container_of(dpp, struct dcn42_dpp, base) + +#define DPP_REG_LIST_SH_MASK_DCN42_COMMON(mask_sh)\ + TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\ + TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\ + TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\ + TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\ + TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\ + TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\ + TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\ + TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\ + TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\ + TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\ + TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ + TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ + TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ + TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\ + TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ + TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ + TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\ + TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ + TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ + TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ + TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\ + TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\ + TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\ + TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \ + TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ + TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ + TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_COEF_FORMAT, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C11_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C12_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C13_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C14_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C21_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C22_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C23_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C24_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C31_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C32_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C33_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C34_A, mask_sh), \ + TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ + TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \ + TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH_EN, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SRC1_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SRC2_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SRC3_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH1_XBAR, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH2_XBAR, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH3_XBAR, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_FORMAT, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_READ_CHANNEL_MASK, mask_sh), \ + TF_SF(CM0_CM_HIST_LOCK, CM_HIST_LOCK, mask_sh), \ + TF_SF(CM0_CM_HIST_INDEX, CM_HIST_INDEX, mask_sh), \ + TF_SF(CM0_CM_HIST_DATA, CM_HIST_DATA, mask_sh), \ + TF_SF(CM0_CM_HIST_DATA, CM_HIST_DATA, mask_sh), \ + TF_SF(CM0_CM_HIST_STATUS, CM_HIST_BUFA_RDY_STATUS, mask_sh), \ + TF_SF(CM0_CM_HIST_STATUS, CM_HIST_BUFB_RDY_STATUS, mask_sh), \ + TF_SF(CM0_CM_HIST_SCALE_SRC1, CM_HIST_SCALE_SRC1, mask_sh), \ + TF_SF(CM0_CM_HIST_COEFA_SRC2, CM_HIST_COEFA_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_COEFB_SRC2, CM_HIST_COEFB_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_COEFC_SRC2, CM_HIST_COEFC_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_SCALE_SRC3, CM_HIST_SCALE_SRC3, mask_sh), \ + TF_SF(CM0_CM_HIST_BIAS_SRC1, CM_HIST_BIAS_SRC1, mask_sh), \ + TF_SF(CM0_CM_HIST_BIAS_SRC2, CM_HIST_BIAS_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_BIAS_SRC3, CM_HIST_BIAS_SRC3, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT0, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT1, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT2, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT3, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, LUMA_KEYER_EN, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ + TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_RINGEST_FORCE_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF1_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF3_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT1_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT2_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_ROC_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_SLOPE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_IN_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_BASE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_SLOPE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_IN_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_BASE_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_RINGEST_FORCE_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF1_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF3_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT1_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT2_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_ROC_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_SLOPE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_IN_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_BASE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_SLOPE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_IN_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_BASE_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C0, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C1, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_DIS, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_STATE, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_EN, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_MODE, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_LBA_MODE, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_MODE, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_NORM, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT_CURRENT, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_SLOPE_SEG0, mask_sh), \ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_UTHRE, mask_sh),\ + TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_DTHRE, mask_sh), \ + TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_START_IN, mask_sh), \ + TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_END_IN, mask_sh), \ + TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_SLOPE, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_P, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_P, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_P, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_N, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_N, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_N, mask_sh), \ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh) + +#define DPP_REG_FIELD_LIST_DCN42(type) \ + DPP_REG_FIELD_LIST_DCN401(type); \ + type CM_HIST_SEL; \ + type CM_HIST_CH_EN; \ + type CM_HIST_SRC1_SEL; \ + type CM_HIST_SRC2_SEL; \ + type CM_HIST_SRC3_SEL; \ + type CM_HIST_CH1_XBAR; \ + type CM_HIST_CH2_XBAR; \ + type CM_HIST_CH3_XBAR; \ + type CM_HIST_FORMAT; \ + type CM_HIST_READ_CHANNEL_MASK; \ + type CM_HIST_LOCK; \ + type CM_HIST_INDEX; \ + type CM_HIST_DATA; \ + type CM_HIST_BUFA_RDY_STATUS; \ + type CM_HIST_BUFB_RDY_STATUS; \ + type CM_HIST_SCALE_SRC1; \ + type CM_HIST_COEFA_SRC2; \ + type CM_HIST_COEFB_SRC2; \ + type CM_HIST_COEFC_SRC2; \ + type CM_HIST_SCALE_SRC3; \ + type CM_HIST_BIAS_SRC1; \ + type CM_HIST_BIAS_SRC2; \ + type CM_HIST_BIAS_SRC3 + + +#define DPP_REG_VARIABLE_LIST_DCN42 \ + DPP_REG_VARIABLE_LIST_DCN401; \ + uint32_t ALPHA_2BIT_LUT01; \ + uint32_t ALPHA_2BIT_LUT23; \ + uint32_t CM_HIST_CNTL; \ + uint32_t CM_HIST_INDEX; \ + uint32_t CM_HIST_LOCK; \ + uint32_t CM_HIST_DATA; \ + uint32_t CM_HIST_STATUS; \ + uint32_t CM_HIST_SCALE_SRC1; \ + uint32_t CM_HIST_COEFA_SRC2; \ + uint32_t CM_HIST_COEFB_SRC2; \ + uint32_t CM_HIST_COEFC_SRC2; \ + uint32_t CM_HIST_SCALE_SRC3; \ + uint32_t CM_HIST_BIAS_SRC1; \ + uint32_t CM_HIST_BIAS_SRC2; \ + uint32_t CM_HIST_BIAS_SRC3 + +struct dcn42_dpp_registers { + DPP_REG_VARIABLE_LIST_DCN42; +}; + +struct dcn42_dpp_shift { + DPP_REG_FIELD_LIST_DCN42(uint8_t); +}; + +struct dcn42_dpp_mask { + DPP_REG_FIELD_LIST_DCN42(uint32_t); +}; +struct dcn42_dpp { + struct dpp base; + const struct dcn42_dpp_registers *tf_regs; + const struct dcn42_dpp_shift *tf_shift; + const struct dcn42_dpp_mask *tf_mask; + const uint16_t *filter_v; + const uint16_t *filter_h; + const uint16_t *filter_v_c; + const uint16_t *filter_h_c; + int lb_pixel_depth_supported; + int lb_memory_size; + int lb_bits_per_entry; + bool is_write_to_ram_a_safe; + struct scaler_data scl_data; + struct pwl_params pwl_data; +}; + +bool dpp42_construct(struct dcn42_dpp *dpp42, + struct dc_context *ctx, + uint32_t inst, + const struct dcn42_dpp_registers *tf_regs, + const struct dcn42_dpp_shift *tf_shift, + const struct dcn42_dpp_mask *tf_mask); + + +#endif /* __DCN42_DPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c new file mode 100644 index 0000000000000..7d2090c7870e6 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "include/gpio_types.h" +#include "../hw_factory.h" + + +#include "../hw_gpio.h" +#include "../hw_ddc.h" +#include "../hw_hpd.h" +#include "../hw_generic.h" + + + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" +#include "dpcs/dpcs_4_0_0_offset.h" +#include "dpcs/dpcs_4_0_0_sh_mask.h" + +#include "reg_helper.h" +#include "../hpd_regs.h" +#include "hw_factory_dcn42.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +/* begin ********************* + * macros to expend register list macro defined in HW object header file */ + +/* DCN */ +#define block HPD +#define reg_num 0 + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + + + +#define REG(reg_name)\ + (BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name) + +#define SF_HPD(reg_name, field_name, post_fix)\ + .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix + +#define REGI(reg_name, block, id)\ + (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name) + +#define SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +/* macros to expend register list macro defined in HW object header file + * end *********************/ + +// DC_GPIO_HPD_* registers are gone. +#undef HPD_REG_LIST +#define HPD_REG_LIST(id) \ + .int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\ + .toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id) + +#define hpd_regs(id) \ +{\ + HPD_REG_LIST(id)\ +} + +static const struct hpd_registers hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4), +}; + +static const struct hpd_sh_mask hpd_shift = { + HPD_MASK_SH_LIST(__SHIFT) +}; + +static const struct hpd_sh_mask hpd_mask = { + HPD_MASK_SH_LIST(_MASK) +}; + +#include "../ddc_regs.h" + + /* set field name */ +#define SF_DDC(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +static const struct ddc_registers ddc_data_regs_dcn[] = { + ddc_data_regs_dcn2(1), + ddc_data_regs_dcn2(2), + ddc_data_regs_dcn2(3), + ddc_data_regs_dcn2(4), + ddc_data_regs_dcn2(5), + { + // add a dummy entry for cases no such port + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + }, + { + DDC_GPIO_VGA_REG_LIST(DATA), + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + } +}; + +static const struct ddc_registers ddc_clk_regs_dcn[] = { + ddc_clk_regs_dcn2(1), + ddc_clk_regs_dcn2(2), + ddc_clk_regs_dcn2(3), + ddc_clk_regs_dcn2(4), + ddc_clk_regs_dcn2(5), + { + // add a dummy entry for cases no such port + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + }, + { + DDC_GPIO_VGA_REG_LIST(CLK), + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + } +}; + +static const struct ddc_sh_mask ddc_shift[] = { + DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 6), + DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT) +}; + +static const struct ddc_sh_mask ddc_mask[] = { + DDC_MASK_SH_LIST_DCN2(_MASK, 1), + DDC_MASK_SH_LIST_DCN2(_MASK, 2), + DDC_MASK_SH_LIST_DCN2(_MASK, 3), + DDC_MASK_SH_LIST_DCN2(_MASK, 4), + DDC_MASK_SH_LIST_DCN2(_MASK, 5), + DDC_MASK_SH_LIST_DCN2(_MASK, 6), + DDC_MASK_SH_LIST_DCN2_VGA(_MASK) +}; + +#include "../generic_regs.h" + +/* set field name */ +#define SF_GENERIC(reg_name, field_name, post_fix)\ + .field_name = 0 + +static const struct generic_registers generic_regs[] = { + {{ 0 }}, + {{ 0 }}, +}; + +static const struct generic_sh_mask generic_shift[] = { + { 0 }, + { 0 }, +}; + +static const struct generic_sh_mask generic_mask[] = { + { 0 }, + { 0 }, +}; + +static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) +{ + struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); + + generic->regs = &generic_regs[en]; + generic->shifts = &generic_shift[en]; + generic->masks = &generic_mask[en]; + generic->base.regs = &generic_regs[en].gpio; +} + +static void define_ddc_registers( + struct hw_gpio_pin *pin, + uint32_t en) +{ + struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); + + switch (pin->id) { + case GPIO_ID_DDC_DATA: + ddc->regs = &ddc_data_regs_dcn[en]; + ddc->base.regs = &ddc_data_regs_dcn[en].gpio; + break; + case GPIO_ID_DDC_CLOCK: + ddc->regs = &ddc_clk_regs_dcn[en]; + ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; + break; + default: + ASSERT_CRITICAL(false); + return; + } + + ddc->shifts = &ddc_shift[en]; + ddc->masks = &ddc_mask[en]; + +} + +static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) +{ + struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); + + hpd->regs = &hpd_regs[en]; + hpd->shifts = &hpd_shift; + hpd->masks = &hpd_mask; + hpd->base.regs = &hpd_regs[en].gpio; +} + + +/* function table */ +static const struct hw_factory_funcs funcs = { + .init_ddc_data = dal_hw_ddc_init, + .init_generic = dal_hw_generic_init, + .init_hpd = dal_hw_hpd_init, + .get_ddc_pin = dal_hw_ddc_get_pin, + .get_hpd_pin = dal_hw_hpd_get_pin, + .get_generic_pin = dal_hw_generic_get_pin, + .define_hpd_registers = define_hpd_registers, + .define_ddc_registers = define_ddc_registers, + .define_generic_registers = define_generic_registers +}; + +/* + * dal_hw_factory_dcn42_init + * + * @brief + * Initialize HW factory function pointers and pin info + * + * @param + * struct hw_factory *factory - [out] struct of function pointers + */ +void dal_hw_factory_dcn42_init(struct hw_factory *factory) +{ + factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; + factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; + factory->number_of_pins[GPIO_ID_GENERIC] = 4; + factory->number_of_pins[GPIO_ID_HPD] = 5; + factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; + factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; + factory->number_of_pins[GPIO_ID_SYNC] = 0; + factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ + + factory->funcs = &funcs; +} diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h new file mode 100644 index 0000000000000..b723380eb17f5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DAL_HW_FACTORY_DCN42_H__ +#define __DAL_HW_FACTORY_DCN42_H__ + +/* Initialize HW factory function pointers and pin info */ +void dal_hw_factory_dcn42_init(struct hw_factory *factory); + +#endif /* __DAL_HW_FACTORY_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c new file mode 100644 index 0000000000000..dcbcf6b85abff --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "hw_translate_dcn42.h" + +#include "dm_services.h" +#include "include/gpio_types.h" +#include "../hw_translate.h" + + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" +#include "dpcs/dpcs_4_0_0_offset.h" +#include "dpcs/dpcs_4_0_0_sh_mask.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +/* begin ********************* + * macros to expend register list macro defined in HW object header file */ + +/* DCN */ +#define block HPD +#define reg_num 0 + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#undef REG +#define REG(reg_name)\ + (BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name) +#define SF_HPD(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + + +/* macros to expend register list macro defined in HW object header file + * end *********************/ + + +static bool offset_to_id( + uint32_t offset, + uint32_t mask, + enum gpio_id *id, + uint32_t *en) +{ + switch (offset) { + /* HPD */ + case REG(HPD0_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_1; + return true; + case REG(HPD1_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_2; + return true; + case REG(HPD2_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_3; + return true; + case REG(HPD3_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_4; + return true; + case REG(HPD4_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_5; + return true; + /* DDC */ + /* we don't care about the GPIO_ID for DDC + * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK + * directly in the create method + */ + case REG(DC_GPIO_DDC1_A): + *en = GPIO_DDC_LINE_DDC1; + return true; + case REG(DC_GPIO_DDC2_A): + *en = GPIO_DDC_LINE_DDC2; + return true; + case REG(DC_GPIO_DDC3_A): + *en = GPIO_DDC_LINE_DDC3; + return true; + case REG(DC_GPIO_DDC4_A): + *en = GPIO_DDC_LINE_DDC4; + return true; + case REG(DC_GPIO_DDC5_A): + *en = GPIO_DDC_LINE_DDC5; + return true; + case REG(DC_GPIO_DDCVGA_A): + *en = GPIO_DDC_LINE_DDC_VGA; + return true; + default: + ASSERT_CRITICAL(false); + return false; + } +} + + +static bool id_to_offset( + enum gpio_id id, + uint32_t en, + struct gpio_pin_info *info) +{ + bool result = true; + + switch (id) { + case GPIO_ID_DDC_DATA: + info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK; + switch (en) { + case GPIO_DDC_LINE_DDC1: + info->offset = REG(DC_GPIO_DDC1_A); + break; + case GPIO_DDC_LINE_DDC2: + info->offset = REG(DC_GPIO_DDC2_A); + break; + case GPIO_DDC_LINE_DDC3: + info->offset = REG(DC_GPIO_DDC3_A); + break; + case GPIO_DDC_LINE_DDC4: + info->offset = REG(DC_GPIO_DDC4_A); + break; + case GPIO_DDC_LINE_DDC5: + info->offset = REG(DC_GPIO_DDC5_A); + break; + case GPIO_DDC_LINE_DDC_VGA: + info->offset = REG(DC_GPIO_DDCVGA_A); + break; + case GPIO_DDC_LINE_I2C_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_DDC_CLOCK: + info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK; + switch (en) { + case GPIO_DDC_LINE_DDC1: + info->offset = REG(DC_GPIO_DDC1_A); + break; + case GPIO_DDC_LINE_DDC2: + info->offset = REG(DC_GPIO_DDC2_A); + break; + case GPIO_DDC_LINE_DDC3: + info->offset = REG(DC_GPIO_DDC3_A); + break; + case GPIO_DDC_LINE_DDC4: + info->offset = REG(DC_GPIO_DDC4_A); + break; + case GPIO_DDC_LINE_DDC5: + info->offset = REG(DC_GPIO_DDC5_A); + break; + case GPIO_DDC_LINE_DDC_VGA: + info->offset = REG(DC_GPIO_DDCVGA_A); + break; + case GPIO_DDC_LINE_I2C_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_SYNC: + case GPIO_ID_VIP_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + + if (result) { + info->offset_y = info->offset + 2; + info->offset_en = info->offset + 1; + info->offset_mask = info->offset - 1; + + info->mask_y = info->mask; + info->mask_en = info->mask; + info->mask_mask = info->mask; + } + + return result; +} + + +/* function table */ +static const struct hw_translate_funcs funcs = { + .offset_to_id = offset_to_id, + .id_to_offset = id_to_offset, +}; + + +/* + * dal_hw_translate_dcn42_init + * + * @brief + * Initialize Hw translate function pointers. + * + * @param + * struct hw_translate *tr - [out] struct of function pointers + * + */ +void dal_hw_translate_dcn42_init(struct hw_translate *tr) +{ + tr->funcs = &funcs; +} + + diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h new file mode 100644 index 0000000000000..007b4d55fef1f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DAL_HW_TRANSLATE_DCN42_H__ +#define __DAL_HW_TRANSLATE_DCN42_H__ + +struct hw_translate; + +/* Initialize Hw translate function pointers */ +void dal_hw_translate_dcn42_init(struct hw_translate *tr); +#ifdef DAL_EMULATION_SUPPORTED +void dal_emulated_hw_translate_dcn42_init(struct hw_translate *tr); +#endif + +#endif /* __DAL_HW_TRANSLATE_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c new file mode 100644 index 0000000000000..4b86b1bf6503f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dc_bios_types.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32/dcn32_hpo_dp_link_encoder.h" +#include "dcn42_hpo_dp_link_encoder.h" +#include "reg_helper.h" +#include "stream_encoder.h" + +#define DC_LOGGER \ + enc3->base.ctx->logger + +#define REG(reg)\ + (enc3->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name + + +#define CTX \ + enc3->base.ctx + + +static void dcn42_hpo_dp_link_enc_read_state( + struct hpo_dp_link_encoder *enc, + struct hpo_dp_link_enc_state *state) +{ + struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc); + + ASSERT(state); + + REG_GET(DP_DPHY_SYM32_STATUS, + STATUS, &state->link_enc_enabled); + REG_GET(DP_DPHY_SYM32_CONTROL, + NUM_LANES, &state->lane_count); + REG_GET(DP_DPHY_SYM32_CONTROL, + MODE, (uint32_t *)&state->link_mode); + + REG_GET_2(DP_DPHY_SYM32_SAT_VC0, + SAT_STREAM_SOURCE, &state->stream_src[0], + SAT_SLOT_COUNT, &state->slot_count[0]); + REG_GET_2(DP_DPHY_SYM32_SAT_VC1, + SAT_STREAM_SOURCE, &state->stream_src[1], + SAT_SLOT_COUNT, &state->slot_count[1]); + REG_GET_2(DP_DPHY_SYM32_SAT_VC2, + SAT_STREAM_SOURCE, &state->stream_src[2], + SAT_SLOT_COUNT, &state->slot_count[2]); + + REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, + STREAM_VC_RATE_X, &state->vc_rate_x[0], + STREAM_VC_RATE_Y, &state->vc_rate_y[0]); + REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1, + STREAM_VC_RATE_X, &state->vc_rate_x[1], + STREAM_VC_RATE_Y, &state->vc_rate_y[1]); + REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2, + STREAM_VC_RATE_X, &state->vc_rate_x[2], + STREAM_VC_RATE_Y, &state->vc_rate_y[2]); +} + +static struct hpo_dp_link_encoder_funcs dcn42_hpo_dp_link_encoder_funcs = { + .enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output, + .disable_link_phy = dcn31_hpo_dp_link_enc_disable_output, + .link_enable = dcn31_hpo_dp_link_enc_enable, + .link_disable = dcn31_hpo_dp_link_enc_disable, + .set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern, + .update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table, + .set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size, + .is_in_alt_mode = dcn32_hpo_dp_link_enc_is_in_alt_mode, + .read_state = dcn42_hpo_dp_link_enc_read_state, + .set_ffe = dcn31_hpo_dp_link_enc_set_ffe, +}; + +void hpo_dp_link_encoder42_construct(struct dcn31_hpo_dp_link_encoder *enc31, + struct dc_context *ctx, + uint32_t inst, + const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, + const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, + const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask) +{ + enc31->base.ctx = ctx; + + enc31->base.inst = inst; + enc31->base.funcs = &dcn42_hpo_dp_link_encoder_funcs; + enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN; + enc31->base.transmitter = TRANSMITTER_UNKNOWN; + + enc31->regs = hpo_le_regs; + enc31->hpo_le_shift = hpo_le_shift; + enc31->hpo_le_mask = hpo_le_mask; +} diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h new file mode 100644 index 0000000000000..3e84d016507cf --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + + +#ifndef __DAL_DCN42_HPO_DP_LINK_ENCODER_H__ +#define __DAL_DCN42_HPO_DP_LINK_ENCODER_H__ + +#include "link_encoder.h" + +void hpo_dp_link_encoder42_construct(struct dcn31_hpo_dp_link_encoder *enc31, + struct dc_context *ctx, + uint32_t inst, + const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, + const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, + const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask); + +#endif // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c new file mode 100644 index 0000000000000..d6e6fbaa041b3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn30/dcn30_hubbub.h" +#include "dcn31/dcn31_hubbub.h" +#include "dcn32/dcn32_hubbub.h" +#include "dcn35/dcn35_hubbub.h" +#include "dcn42/dcn42_hubbub.h" +#include "dm_services.h" +#include "reg_helper.h" + +#define DCN42_CRB_SEGMENT_SIZE_KB 64 + +#define CTX \ + hubbub2->base.ctx +#define DC_LOGGER \ + hubbub2->base.ctx->logger +#define REG(reg)\ + hubbub2->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hubbub2->shifts->field_name, hubbub2->masks->field_name + +static bool hubbub42_program_urgent_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.urgent > hubbub2->watermarks.dcn4x.a.urgent) { + hubbub2->watermarks.dcn4x.a.urgent = watermarks->dcn4x.a.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, watermarks->dcn4x.a.urgent); + } else if (watermarks->dcn4x.a.urgent < hubbub2->watermarks.dcn4x.a.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip = watermarks->dcn4x.a.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->dcn4x.a.frac_urg_bw_flip); + } else if (watermarks->dcn4x.a.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.a.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.a.frac_urg_bw_nom = watermarks->dcn4x.a.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->dcn4x.a.frac_urg_bw_nom); + } else if (watermarks->dcn4x.a.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.a.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.a.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.a.refcyc_per_trip_to_mem = watermarks->dcn4x.a.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, watermarks->dcn4x.a.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.a.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.a.refcyc_per_trip_to_mem) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.urgent > hubbub2->watermarks.dcn4x.b.urgent) { + hubbub2->watermarks.dcn4x.b.urgent = watermarks->dcn4x.b.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, watermarks->dcn4x.b.urgent); + } else if (watermarks->dcn4x.b.urgent < hubbub2->watermarks.dcn4x.b.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.b.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.b.frac_urg_bw_flip = watermarks->dcn4x.b.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->dcn4x.b.frac_urg_bw_flip); + } else if (watermarks->dcn4x.b.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.b.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.b.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.b.frac_urg_bw_nom = watermarks->dcn4x.b.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->dcn4x.b.frac_urg_bw_nom); + } else if (watermarks->dcn4x.b.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.b.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.b.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.b.refcyc_per_trip_to_mem = watermarks->dcn4x.b.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, watermarks->dcn4x.b.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.b.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.b.refcyc_per_trip_to_mem) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.urgent > hubbub2->watermarks.dcn4x.c.urgent) { + hubbub2->watermarks.dcn4x.c.urgent = watermarks->dcn4x.c.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, watermarks->dcn4x.c.urgent); + } else if (watermarks->dcn4x.c.urgent < hubbub2->watermarks.dcn4x.c.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.c.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.c.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.c.frac_urg_bw_flip = watermarks->dcn4x.c.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->dcn4x.c.frac_urg_bw_flip); + } else if (watermarks->dcn4x.c.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.c.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.c.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.c.frac_urg_bw_nom = watermarks->dcn4x.c.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->dcn4x.c.frac_urg_bw_nom); + } else if (watermarks->dcn4x.c.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.c.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.c.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.c.refcyc_per_trip_to_mem = watermarks->dcn4x.c.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, watermarks->dcn4x.c.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.c.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.c.refcyc_per_trip_to_mem) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.urgent > hubbub2->watermarks.dcn4x.d.urgent) { + hubbub2->watermarks.dcn4x.d.urgent = watermarks->dcn4x.d.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, watermarks->dcn4x.d.urgent); + } else if (watermarks->dcn4x.d.urgent < hubbub2->watermarks.dcn4x.d.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.d.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.d.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.d.frac_urg_bw_flip = watermarks->dcn4x.d.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->dcn4x.d.frac_urg_bw_flip); + } else if (watermarks->dcn4x.d.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.d.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.d.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.d.frac_urg_bw_nom = watermarks->dcn4x.d.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->dcn4x.d.frac_urg_bw_nom); + } else if (watermarks->dcn4x.d.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.d.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.d.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.d.refcyc_per_trip_to_mem = watermarks->dcn4x.d.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, watermarks->dcn4x.d.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.d.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.d.refcyc_per_trip_to_mem) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_stutter_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.sr_enter > hubbub2->watermarks.dcn4x.a.sr_enter) { + hubbub2->watermarks.dcn4x.a.sr_enter = watermarks->dcn4x.a.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, watermarks->dcn4x.a.sr_enter); + } else if (watermarks->dcn4x.a.sr_enter < hubbub2->watermarks.dcn4x.a.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.sr_exit > hubbub2->watermarks.dcn4x.a.sr_exit) { + hubbub2->watermarks.dcn4x.a.sr_exit = watermarks->dcn4x.a.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, watermarks->dcn4x.a.sr_exit); + } else if (watermarks->dcn4x.a.sr_exit < hubbub2->watermarks.dcn4x.a.sr_exit) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.sr_enter > hubbub2->watermarks.dcn4x.b.sr_enter) { + hubbub2->watermarks.dcn4x.b.sr_enter = watermarks->dcn4x.b.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, watermarks->dcn4x.b.sr_enter); + } else if (watermarks->dcn4x.b.sr_enter < hubbub2->watermarks.dcn4x.b.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.sr_exit > hubbub2->watermarks.dcn4x.b.sr_exit) { + hubbub2->watermarks.dcn4x.b.sr_exit = watermarks->dcn4x.b.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, watermarks->dcn4x.b.sr_exit); + } else if (watermarks->dcn4x.b.sr_exit < hubbub2->watermarks.dcn4x.b.sr_exit) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.sr_enter > hubbub2->watermarks.dcn4x.c.sr_enter) { + hubbub2->watermarks.dcn4x.c.sr_enter = watermarks->dcn4x.c.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, watermarks->dcn4x.c.sr_enter); + } else if (watermarks->dcn4x.c.sr_enter < hubbub2->watermarks.dcn4x.c.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.sr_exit > hubbub2->watermarks.dcn4x.c.sr_exit) { + hubbub2->watermarks.dcn4x.c.sr_exit = watermarks->dcn4x.c.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, watermarks->dcn4x.c.sr_exit); + } else if (watermarks->dcn4x.c.sr_exit < hubbub2->watermarks.dcn4x.c.sr_exit) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.sr_enter > hubbub2->watermarks.dcn4x.d.sr_enter) { + hubbub2->watermarks.dcn4x.d.sr_enter = watermarks->dcn4x.d.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, watermarks->dcn4x.d.sr_enter); + } else if (watermarks->dcn4x.d.sr_enter < hubbub2->watermarks.dcn4x.d.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.sr_exit > hubbub2->watermarks.dcn4x.d.sr_exit) { + hubbub2->watermarks.dcn4x.d.sr_exit = watermarks->dcn4x.d.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, watermarks->dcn4x.d.sr_exit); + } else if (watermarks->dcn4x.d.sr_exit < hubbub2->watermarks.dcn4x.d.sr_exit) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_pstate_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* Section for UCLK_PSTATE_CHANGE_WATERMARKS */ + /* UCLK state A */ + if (safe_to_lower || watermarks->dcn4x.a.uclk_pstate > hubbub2->watermarks.dcn4x.a.uclk_pstate) { + hubbub2->watermarks.dcn4x.a.uclk_pstate = watermarks->dcn4x.a.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, watermarks->dcn4x.a.uclk_pstate); + } else if (watermarks->dcn4x.a.uclk_pstate < hubbub2->watermarks.dcn4x.a.uclk_pstate) + wm_pending = true; + + /* UCLK state B */ + if (safe_to_lower || watermarks->dcn4x.b.uclk_pstate > hubbub2->watermarks.dcn4x.b.uclk_pstate) { + hubbub2->watermarks.dcn4x.b.uclk_pstate = watermarks->dcn4x.b.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, watermarks->dcn4x.b.uclk_pstate); + } else if (watermarks->dcn4x.b.uclk_pstate < hubbub2->watermarks.dcn4x.b.uclk_pstate) + wm_pending = true; + + /* UCLK state C */ + if (safe_to_lower || watermarks->dcn4x.c.uclk_pstate > hubbub2->watermarks.dcn4x.c.uclk_pstate) { + hubbub2->watermarks.dcn4x.c.uclk_pstate = watermarks->dcn4x.c.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, watermarks->dcn4x.c.uclk_pstate); + } else if (watermarks->dcn4x.c.uclk_pstate < hubbub2->watermarks.dcn4x.c.uclk_pstate) + wm_pending = true; + + /* UCLK state D */ + if (safe_to_lower || watermarks->dcn4x.d.uclk_pstate > hubbub2->watermarks.dcn4x.d.uclk_pstate) { + hubbub2->watermarks.dcn4x.d.uclk_pstate = watermarks->dcn4x.d.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, watermarks->dcn4x.d.uclk_pstate); + } else if (watermarks->dcn4x.d.uclk_pstate < hubbub2->watermarks.dcn4x.d.uclk_pstate) + wm_pending = true; + + /* Section for FCLK_PSTATE_CHANGE_WATERMARKS */ + /* FCLK state A */ + if (safe_to_lower || watermarks->dcn4x.a.fclk_pstate > hubbub2->watermarks.dcn4x.a.fclk_pstate) { + hubbub2->watermarks.dcn4x.a.fclk_pstate = watermarks->dcn4x.a.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, watermarks->dcn4x.a.fclk_pstate); + } else if (watermarks->dcn4x.a.fclk_pstate < hubbub2->watermarks.dcn4x.a.fclk_pstate) + wm_pending = true; + + /* FCLK state B */ + if (safe_to_lower || watermarks->dcn4x.b.fclk_pstate > hubbub2->watermarks.dcn4x.b.fclk_pstate) { + hubbub2->watermarks.dcn4x.b.fclk_pstate = watermarks->dcn4x.b.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, watermarks->dcn4x.b.fclk_pstate); + } else if (watermarks->dcn4x.b.fclk_pstate < hubbub2->watermarks.dcn4x.b.fclk_pstate) + wm_pending = true; + + /* FCLK state C */ + if (safe_to_lower || watermarks->dcn4x.c.fclk_pstate > hubbub2->watermarks.dcn4x.c.fclk_pstate) { + hubbub2->watermarks.dcn4x.c.fclk_pstate = watermarks->dcn4x.c.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, watermarks->dcn4x.c.fclk_pstate); + } else if (watermarks->dcn4x.c.fclk_pstate < hubbub2->watermarks.dcn4x.c.fclk_pstate) + wm_pending = true; + + /* FCLK state D */ + if (safe_to_lower || watermarks->dcn4x.d.fclk_pstate > hubbub2->watermarks.dcn4x.d.fclk_pstate) { + hubbub2->watermarks.dcn4x.d.fclk_pstate = watermarks->dcn4x.d.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, watermarks->dcn4x.d.fclk_pstate); + } else if (watermarks->dcn4x.d.fclk_pstate < hubbub2->watermarks.dcn4x.d.fclk_pstate) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_usr_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.usr > hubbub2->watermarks.dcn4x.a.usr) { + hubbub2->watermarks.dcn4x.a.usr = watermarks->dcn4x.a.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, watermarks->dcn4x.a.usr); + } else if (watermarks->dcn4x.a.usr < hubbub2->watermarks.dcn4x.a.usr) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.usr > hubbub2->watermarks.dcn4x.b.usr) { + hubbub2->watermarks.dcn4x.b.usr = watermarks->dcn4x.b.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, watermarks->dcn4x.b.usr); + } else if (watermarks->dcn4x.b.usr < hubbub2->watermarks.dcn4x.b.usr) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.usr > hubbub2->watermarks.dcn4x.c.usr) { + hubbub2->watermarks.dcn4x.c.usr = watermarks->dcn4x.c.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, watermarks->dcn4x.c.usr); + } else if (watermarks->dcn4x.c.usr < hubbub2->watermarks.dcn4x.c.usr) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.usr > hubbub2->watermarks.dcn4x.d.usr) { + hubbub2->watermarks.dcn4x.d.usr = watermarks->dcn4x.d.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, watermarks->dcn4x.d.usr); + } else if (watermarks->dcn4x.d.usr < hubbub2->watermarks.dcn4x.d.usr) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_stutter_z8_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.sr_enter_z8 > hubbub2->watermarks.dcn4x.a.sr_enter_z8) { + hubbub2->watermarks.dcn4x.a.sr_enter_z8 = watermarks->dcn4x.a.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, watermarks->dcn4x.a.sr_enter_z8); + } else if (watermarks->dcn4x.a.sr_enter_z8 < hubbub2->watermarks.dcn4x.a.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.sr_exit_z8 > hubbub2->watermarks.dcn4x.a.sr_exit_z8) { + hubbub2->watermarks.dcn4x.a.sr_exit_z8 = watermarks->dcn4x.a.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, watermarks->dcn4x.a.sr_exit_z8); + } else if (watermarks->dcn4x.a.sr_exit_z8 < hubbub2->watermarks.dcn4x.a.sr_exit_z8) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.sr_enter_z8 > hubbub2->watermarks.dcn4x.b.sr_enter_z8) { + hubbub2->watermarks.dcn4x.b.sr_enter_z8 = watermarks->dcn4x.b.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, watermarks->dcn4x.b.sr_enter_z8); + } else if (watermarks->dcn4x.b.sr_enter_z8 < hubbub2->watermarks.dcn4x.b.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.sr_exit_z8 > hubbub2->watermarks.dcn4x.b.sr_exit_z8) { + hubbub2->watermarks.dcn4x.b.sr_exit_z8 = watermarks->dcn4x.b.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, watermarks->dcn4x.b.sr_exit_z8); + } else if (watermarks->dcn4x.b.sr_exit_z8 < hubbub2->watermarks.dcn4x.b.sr_exit_z8) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.sr_enter_z8 > hubbub2->watermarks.dcn4x.c.sr_enter_z8) { + hubbub2->watermarks.dcn4x.c.sr_enter_z8 = watermarks->dcn4x.c.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, watermarks->dcn4x.c.sr_enter_z8); + } else if (watermarks->dcn4x.c.sr_enter_z8 < hubbub2->watermarks.dcn4x.c.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.sr_exit_z8 > hubbub2->watermarks.dcn4x.c.sr_exit_z8) { + hubbub2->watermarks.dcn4x.c.sr_exit_z8 = watermarks->dcn4x.c.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, watermarks->dcn4x.c.sr_exit_z8); + } else if (watermarks->dcn4x.c.sr_exit_z8 < hubbub2->watermarks.dcn4x.c.sr_exit_z8) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.sr_enter_z8 > hubbub2->watermarks.dcn4x.d.sr_enter_z8) { + hubbub2->watermarks.dcn4x.d.sr_enter_z8 = watermarks->dcn4x.d.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, watermarks->dcn4x.d.sr_enter_z8); + } else if (watermarks->dcn4x.d.sr_enter_z8 < hubbub2->watermarks.dcn4x.d.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.sr_exit_z8 > hubbub2->watermarks.dcn4x.d.sr_exit_z8) { + hubbub2->watermarks.dcn4x.d.sr_exit_z8 = watermarks->dcn4x.d.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, watermarks->dcn4x.d.sr_exit_z8); + } else if (watermarks->dcn4x.d.sr_exit_z8 < hubbub2->watermarks.dcn4x.d.sr_exit_z8) + wm_pending = true; + + return wm_pending; +} + +static void hubbub42_allow_self_refresh_control(struct hubbub *hubbub, bool allow) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + /* + * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter + * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter + */ + + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow); + + if (!allow && hubbub->ctx->dc->debug.disable_stutter) {/*controlled by registry key*/ + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE, 1); + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); + } +} +static void hubbub42_set_sdp_control(struct hubbub *hubbub, bool dc_control) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + REG_UPDATE(DCHUBBUB_SDPIF_CFG0, + SDPIF_PORT_CONTROL, dc_control); +} + +static bool hubbub42_program_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + bool wm_pending = false; + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + if (!safe_to_lower && hubbub->ctx->dc->debug.disable_stutter_for_wm_program) { + /* before raising watermarks, SDP control give to DF, stutter must be disabled */ + wm_pending = true; + hubbub42_set_sdp_control(hubbub, false); + hubbub42_allow_self_refresh_control(hubbub, false); + } + if (hubbub42_program_urgent_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_stutter_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_pstate_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_usr_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_stutter_z8_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0xFF, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/ + REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); + + if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter) + hubbub42_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); + if (safe_to_lower && hubbub->ctx->dc->debug.disable_stutter_for_wm_program) { + hubbub42_set_sdp_control(hubbub, true); + } + hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); + + return wm_pending; +} + +static const struct hubbub_funcs hubbub42_funcs = { + .update_dchub = hubbub2_update_dchub, + .init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx, + .init_vm_ctx = hubbub2_init_vm_ctx, + .dcc_support_swizzle = hubbub3_dcc_support_swizzle, + .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, + .get_dcc_compression_cap = hubbub3_get_dcc_compression_cap, + .wm_read_state = hubbub35_wm_read_state, + .get_dchub_ref_freq = hubbub35_get_dchub_ref_freq, + .program_watermarks = hubbub42_program_watermarks, + .allow_self_refresh_control = hubbub42_allow_self_refresh_control, + .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, + .force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes, + .force_pstate_change_control = hubbub3_force_pstate_change_control, + .init_watermarks = hubbub35_init_watermarks, + .program_det_size = dcn32_program_det_size, + .program_compbuf_size = dcn35_program_compbuf_size, + .init_crb = dcn35_init_crb, + .hubbub_read_state = hubbub2_read_state, + .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, + .dchubbub_init = hubbub35_init, + .dchvm_init = dcn35_dchvm_init, +}; + +void hubbub42_construct(struct dcn20_hubbub *hubbub2, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb) +{ + hubbub2->base.ctx = ctx; + hubbub2->base.funcs = &hubbub42_funcs; + hubbub2->regs = hubbub_regs; + hubbub2->shifts = hubbub_shift; + hubbub2->masks = hubbub_mask; + + hubbub2->detile_buf_size = det_size_kb * 1024; + hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024; + hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN42_CRB_SEGMENT_SIZE_KB; +} diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h new file mode 100644 index 0000000000000..926ddc156a2b3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h @@ -0,0 +1,268 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBBUB_DCN42_H__ +#define __DC_HUBBUB_DCN42_H__ + +#include "dcn32/dcn32_hubbub.h" + +#define DCN42_CRB_SIZE_KB 1792 +#define DCN42_DEFAULT_DET_SIZE 320 +#define DCN42_CRB_SEGMENT_SIZE_KB 64 + +#define HUBBUB_REG_LIST_DCN42(id)\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ + SR(DCHUBBUB_ARB_SAT_LEVEL),\ + SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_SOFT_RESET),\ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DCN_VM_FB_LOCATION_BASE),\ + SR(DCN_VM_FB_LOCATION_TOP),\ + SR(DCN_VM_FB_OFFSET),\ + SR(DCN_VM_AGP_BOT),\ + SR(DCN_VM_AGP_TOP),\ + SR(DCN_VM_AGP_BASE),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ + SR(DCHUBBUB_DET0_CTRL),\ + SR(DCHUBBUB_DET1_CTRL),\ + SR(DCHUBBUB_DET2_CTRL),\ + SR(DCHUBBUB_DET3_CTRL),\ + SR(DCHUBBUB_COMPBUF_CTRL),\ + SR(COMPBUF_RESERVED_SPACE),\ + SR(DCHUBBUB_DEBUG_CTRL_0),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ + SR(DCN_VM_FAULT_ADDR_MSB),\ + SR(DCN_VM_FAULT_ADDR_LSB),\ + SR(DCN_VM_FAULT_CNTL),\ + SR(DCN_VM_FAULT_STATUS),\ + SR(SDPIF_REQUEST_RATE_LIMIT),\ + SR(DCHUBBUB_CLOCK_CNTL),\ + SR(DCHUBBUB_SDPIF_CFG0),\ + SR(DCHUBBUB_SDPIF_CFG1),\ + SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\ + SR(DCHUBBUB_ARB_HOSTVM_CNTL),\ + SR(DCHVM_CTRL0),\ + SR(DCHVM_MEM_CTRL),\ + SR(DCHVM_CLK_CTRL),\ + SR(DCHVM_RIOMMU_CTRL0),\ + SR(DCHVM_RIOMMU_STAT0),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ + SR(DCHUBBUB_ARB_QOS_FORCE) + +#define HUBBUB_MASK_SH_LIST_DCN4_2(mask_sh)\ + HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \ + HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MAX_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MAX_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh),\ + HUBBUB_SF(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DISPCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\ + HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\ + HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_ERROR_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_CLEAR, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, URGENT_ZERO_SIZE_REQ_EN, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, CSTATE_SWATH_CHK_GOOD_MODE, mask_sh) + +void hubbub42_construct(struct dcn20_hubbub *hubbub2, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb); +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c new file mode 100644 index 0000000000000..07c38dc039600 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn401/dcn401_hubp.h" +#include "dcn42_hubp.h" +#include "reg_helper.h" + +#define REG(reg) \ + hubp2->hubp_regs->reg + +#define CTX \ + hubp2->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name + +static void hubp42_set_fgcg(struct hubp *hubp, bool enable) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable); +} + +static void hubp42_init(struct hubp *hubp) +{ + hubp3_init(hubp); + + hubp42_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub); + + /*do nothing for now for dcn3.5 or later*/ +} + +static void hubp42_program_pixel_format( + struct hubp *hubp, + enum surface_pixel_format format) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + uint32_t green_bar = 1; + uint32_t red_bar = 3; + uint32_t blue_bar = 2; + + /* swap for ABGR format */ + if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { + red_bar = 2; + blue_bar = 3; + } + + REG_UPDATE_3(HUBPRET_CONTROL, + CROSSBAR_SRC_Y_G, green_bar, + CROSSBAR_SRC_CB_B, blue_bar, + CROSSBAR_SRC_CR_R, red_bar); + + /* Mapping is same as ipp programming (cnvc) */ + + switch (format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 1); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 3); + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 8); + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 10); + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */ + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 24); + break; + + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 65); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 64); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 67); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 66); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 12); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 112); + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 113); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 114); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 118); + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 119); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE: + REG_UPDATE_2(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 116, + ALPHA_PLANE_EN, 0); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + REG_UPDATE_2(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 116, + ALPHA_PLANE_EN, 1); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + /* don't see the need of program the xbar in DCN 1.0 */ +} + +void hubp42_program_deadline( + struct hubp *hubp, + struct dml2_display_dlg_regs *dlg_attr, + struct dml2_display_ttu_regs *ttu_attr) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + /* DLG - Per hubp */ + REG_SET_2(BLANK_OFFSET_0, 0, + REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, + DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); + + REG_SET(BLANK_OFFSET_1, 0, + MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); + + REG_SET(DST_DIMENSIONS, 0, + REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); + + REG_SET_2(DST_AFTER_SCALER, 0, + REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, + DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); + + REG_SET(REF_FREQ_TO_PIX_FREQ, 0, + REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); + + /* DLG - Per luma/chroma */ + REG_SET(VBLANK_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); + + if (REG(NOM_PARAMETERS_0)) + REG_SET(NOM_PARAMETERS_0, 0, + DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); + + if (REG(NOM_PARAMETERS_1)) + REG_SET(NOM_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); + + REG_SET(NOM_PARAMETERS_4, 0, + DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); + + REG_SET(NOM_PARAMETERS_5, 0, + REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); + + REG_SET_2(PER_LINE_DELIVERY, 0, + REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, + REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); + + REG_SET(VBLANK_PARAMETERS_2, 0, + REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); + + if (REG(NOM_PARAMETERS_2)) + REG_SET(NOM_PARAMETERS_2, 0, + DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); + + if (REG(NOM_PARAMETERS_3)) + REG_SET(NOM_PARAMETERS_3, 0, + REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); + + REG_SET(NOM_PARAMETERS_6, 0, + DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); + + REG_SET(NOM_PARAMETERS_7, 0, + REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); + + /* TTU - per hubp */ + REG_SET_2(DCN_TTU_QOS_WM, 0, + QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, + QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); + + /* TTU - per luma/chroma */ + /* Assumed surf0 is luma and 1 is chroma */ + + REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); + + REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); + + REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); + + REG_SET(FLIP_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); + REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group); + + REG_UPDATE(DCN_DMDATA_VM_CNTL, + REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata); +} + +void hubp42_setup( + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *pipe_regs, + union dml2_global_sync_programming *pipe_global_sync, + struct dc_crtc_timing *timing) +{ + /* otg is locked when this func is called. Register are double buffered. + * disable the requestors is not needed + */ + hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing); + hubp401_program_requestor(hubp, &pipe_regs->rq_regs); + hubp42_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); +} +static void hubp42_program_surface_config( + struct hubp *hubp, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + struct plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror, + unsigned int compat_level) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + hubp3_dcc_control_sienna_cichlid(hubp, dcc); + hubp3_program_tiling(hubp2, tiling_info, format); + hubp2_program_size(hubp, format, plane_size, dcc); + hubp2_program_rotation(hubp, rotation, horizontal_mirror); + hubp42_program_pixel_format(hubp, format); +} + +void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE_3(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_CROSSBAR_SEL_R, bit_slice_r, + HUBP_3DLUT_CROSSBAR_SEL_G, bit_slice_g, + HUBP_3DLUT_CROSSBAR_SEL_B, bit_slice_b); +} + +static bool hubp42_program_surface_flip_and_addr( + struct hubp *hubp, + const struct dc_plane_address *address, + bool flip_immediate) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + //program flip type + REG_UPDATE(DCSURF_FLIP_CONTROL, + SURFACE_FLIP_TYPE, flip_immediate); + + // Program VMID reg + if (flip_immediate == 0) + REG_UPDATE(VMID_SETTINGS_0, + VMID, address->vmid); + + if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0); + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); + + } else { + // turn off stereo if not in stereo + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); + } + + /* HW automatically latch rest of address register on write to + * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used + * + * program high first and then the low addr, order matters! + */ + switch (address->type) { + case PLN_ADDR_TYPE_GRAPHICS: + /* DCN1.0 does not support const color + * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 + * base on address->grph.dcc_const_color + * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma + * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma + */ + + if (address->grph.addr.quad_part == 0) + break; + + REG_UPDATE_2(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface); + + if (address->grph.meta_addr.quad_part != 0) { + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->grph.meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->grph.meta_addr.low_part); + } + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->grph.addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->grph.addr.low_part); + break; + case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: + if (address->video_progressive.luma_addr.quad_part == 0 + || address->video_progressive.chroma_addr.quad_part == 0) + break; + + REG_UPDATE_4(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); + + if (address->video_progressive.luma_meta_addr.quad_part != 0) { + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, + address->video_progressive.chroma_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, + PRIMARY_META_SURFACE_ADDRESS_C, + address->video_progressive.chroma_meta_addr.low_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->video_progressive.luma_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->video_progressive.luma_meta_addr.low_part); + } + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_SURFACE_ADDRESS_HIGH_C, + address->video_progressive.chroma_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, + PRIMARY_SURFACE_ADDRESS_C, + address->video_progressive.chroma_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->video_progressive.luma_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->video_progressive.luma_addr.low_part); + break; + case PLN_ADDR_TYPE_GRPH_STEREO: + if (address->grph_stereo.left_addr.quad_part == 0) + break; + if (address->grph_stereo.right_addr.quad_part == 0) + break; + + REG_UPDATE_8(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, + SECONDARY_SURFACE_TMZ, address->tmz_surface, + SECONDARY_SURFACE_TMZ_C, address->tmz_surface, + SECONDARY_META_SURFACE_TMZ, address->tmz_surface, + SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); + + if (address->grph_stereo.right_meta_addr.quad_part != 0) { + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0, + SECONDARY_META_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.right_alpha_meta_addr.high_part); + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0, + SECONDARY_META_SURFACE_ADDRESS_C, + address->grph_stereo.right_alpha_meta_addr.low_part); + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, + SECONDARY_META_SURFACE_ADDRESS_HIGH, + address->grph_stereo.right_meta_addr.high_part); + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, + SECONDARY_META_SURFACE_ADDRESS, + address->grph_stereo.right_meta_addr.low_part); + } + if (address->grph_stereo.left_meta_addr.quad_part != 0) { + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.left_alpha_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, + PRIMARY_META_SURFACE_ADDRESS_C, + address->grph_stereo.left_alpha_meta_addr.low_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->grph_stereo.left_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->grph_stereo.left_meta_addr.low_part); + } + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0, + SECONDARY_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.right_alpha_addr.high_part); + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0, + SECONDARY_SURFACE_ADDRESS_C, + address->grph_stereo.right_alpha_addr.low_part); + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, + SECONDARY_SURFACE_ADDRESS_HIGH, + address->grph_stereo.right_addr.high_part); + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, + SECONDARY_SURFACE_ADDRESS, + address->grph_stereo.right_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.left_alpha_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, + PRIMARY_SURFACE_ADDRESS_C, + address->grph_stereo.left_alpha_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->grph_stereo.left_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->grph_stereo.left_addr.low_part); + break; + case PLN_ADDR_TYPE_RGBEA: + if (address->rgbea.addr.quad_part == 0 + || address->rgbea.alpha_addr.quad_part == 0) + break; + + REG_UPDATE_4(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); + + if (address->rgbea.meta_addr.quad_part != 0) { + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, + address->rgbea.alpha_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, + PRIMARY_META_SURFACE_ADDRESS_C, + address->rgbea.alpha_meta_addr.low_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->rgbea.meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->rgbea.meta_addr.low_part); + } + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_SURFACE_ADDRESS_HIGH_C, + address->rgbea.alpha_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, + PRIMARY_SURFACE_ADDRESS_C, + address->rgbea.alpha_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->rgbea.addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->rgbea.addr.low_part); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + hubp->request_address = *address; + + return true; +} + +struct hubp_funcs dcn42_hubp_funcs = { + .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, + .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, + .hubp_program_surface_flip_and_addr = hubp42_program_surface_flip_and_addr, + .hubp_program_surface_config = hubp42_program_surface_config, + .hubp_is_flip_pending = hubp2_is_flip_pending, + .hubp_setup2 = hubp42_setup, + .hubp_setup_interdependent2 = hubp401_setup_interdependent, + .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, + .set_blank = hubp2_set_blank, + .dcc_control = hubp3_dcc_control, + .hubp_reset = hubp_reset, + .mem_program_viewport = min_set_viewport, + .set_cursor_attributes = hubp32_cursor_set_attributes, + .set_cursor_position = hubp401_cursor_set_position, + .hubp_clk_cntl = hubp2_clk_cntl, + .hubp_vtg_sel = hubp2_vtg_sel, + .dmdata_set_attributes = hubp3_dmdata_set_attributes, + .dmdata_load = hubp2_dmdata_load, + .dmdata_status_done = hubp2_dmdata_status_done, + .hubp_read_state = hubp42_read_state, + .hubp_clear_underflow = hubp2_clear_underflow, + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp42_init, + .set_unbounded_requesting = hubp31_set_unbounded_requesting, + .hubp_soft_reset = hubp31_soft_reset, + .hubp_set_flip_int = hubp1_set_flip_int, + .hubp_in_blank = hubp1_in_blank, + .program_extended_blank = hubp31_program_extended_blank_value, + .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, + .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, + .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, + .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, + .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, + .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, + .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, + .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, + .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, + .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, + .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, + .hubp_read_reg_state = hubp3_read_reg_state +}; + +bool hubp42_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask) +{ + hubp2->base.funcs = &dcn42_hubp_funcs; + hubp2->base.ctx = ctx; + hubp2->hubp_regs = hubp_regs; + hubp2->hubp_shift = hubp_shift; + hubp2->hubp_mask = hubp_mask; + hubp2->base.inst = inst; + hubp2->base.opp_id = OPP_ID_INVALID; + hubp2->base.mpcc_id = 0xf; + + return true; +} + + +void hubp42_read_state(struct hubp *hubp) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + struct dcn_hubp_state *s = &hubp2->state; + struct dcn_fl_regs_st *fl_regs = &s->fl_regs; + + hubp401_read_state(hubp); + + /* CONTROL */ + REG_GET_5(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_ENABLE, &fl_regs->lut_enable, + HUBP_3DLUT_DONE, &fl_regs->lut_done, + HUBP_3DLUT_ADDRESSING_MODE, &fl_regs->lut_addr_mode, + HUBP_3DLUT_WIDTH, &fl_regs->lut_width, + HUBP_3DLUT_MPC_WIDTH, &fl_regs->lut_mpc_width); + + REG_GET_4(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_TMZ, &fl_regs->lut_tmz, + HUBP_3DLUT_CROSSBAR_SEL_R, &fl_regs->lut_crossbar_sel_r, + HUBP_3DLUT_CROSSBAR_SEL_G, &fl_regs->lut_crossbar_sel_g, + HUBP_3DLUT_CROSSBAR_SEL_B, &fl_regs->lut_crossbar_sel_b); + + /* ADDR */ + REG_GET(HUBP_3DLUT_ADDRESS_HIGH, + HUBP_3DLUT_ADDRESS_HIGH, &fl_regs->lut_addr_hi); + REG_GET(HUBP_3DLUT_ADDRESS_LOW, + HUBP_3DLUT_ADDRESS_LOW, &fl_regs->lut_addr_lo); + /* CLK */ + REG_GET(HUBP_3DLUT_DLG_PARAM, + REFCYC_PER_3DLUT_GROUP, &fl_regs->refcyc_3dlut_group); + /* FL */ + REG_GET_2(_3DLUT_FL_BIAS_SCALE, + HUBP0_3DLUT_FL_BIAS, &fl_regs->lut_fl_bias, + HUBP0_3DLUT_FL_SCALE, &fl_regs->lut_fl_scale); + REG_GET_2(_3DLUT_FL_CONFIG, + HUBP0_3DLUT_FL_MODE, &fl_regs->lut_fl_mode, + HUBP0_3DLUT_FL_FORMAT, &fl_regs->lut_fl_format); +} diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h new file mode 100644 index 0000000000000..976614f389814 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBP_DCN42_H__ +#define __DC_HUBP_DCN42_H__ + +#include "dcn35/dcn35_hubp.h" + +#define HUBP_MASK_SH_LIST_DCN42(mask_sh)\ + HUBP_MASK_SH_LIST_DCN35(mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_SCALE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_MPC_WIDTH, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_B, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_G, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_R, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW, HUBP_3DLUT_ADDRESS_LOW, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, mask_sh) + +bool hubp42_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask); + +void hubp42_program_3dlut_fl_crossbar( + struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b); + +void hubp42_read_state(struct hubp *hubp); + +void hubp42_setup( + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *pipe_regs, + union dml2_global_sync_programming *pipe_global_sync, + struct dc_crtc_timing *timing); + +void hubp42_program_deadline( + struct hubp *hubp, + struct dml2_display_dlg_regs *dlg_attr, + struct dml2_display_ttu_regs *ttu_attr); + + +#endif /* __DC_HUBP_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c new file mode 100644 index 0000000000000..c9c6ef8236ed8 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -0,0 +1,1476 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dm_helpers.h" +#include "core_types.h" +#include "resource.h" +#include "dccg.h" +#include "dce/dce_hwseq.h" +#include "dcn30/dcn30_cm_common.h" +#include "reg_helper.h" +#include "abm.h" +#include "hubp.h" +#include "dchubbub.h" +#include "timing_generator.h" +#include "opp.h" +#include "ipp.h" +#include "mpc.h" +#include "mcif_wb.h" +#include "dc_dmub_srv.h" +#include "link_hwss.h" +#include "dpcd_defs.h" +#include "dcn401/dcn401_hwseq.h" +#include "dcn42_hwseq.h" +#include "clk_mgr.h" +#include "dsc.h" +#include "dcn20/dcn20_optc.h" +#include "dce/dmub_hw_lock_mgr.h" +#include "dcn42/dcn42_resource.h" +#include "link_service.h" +#include "../dcn10/dcn10_hwseq.h" +#include "../dcn20/dcn20_hwseq.h" +#include "dc_state_priv.h" +#include "dc_stream_priv.h" +#include "dcn35/dcn35_hwseq.h" +#include "dcn42/dcn42_hwseq.h" +#include "dce/dmub_hw_lock_mgr.h" +#include "dio/dcn10/dcn10_dio.h" + +#define DC_LOGGER \ + ctx->logger + +#define CTX \ + hws->ctx + +#define REG(reg)\ + hws->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + + +static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log) +{ + if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) { + if (dc->res_pool->pg_cntl->funcs->print_pg_status) + dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log); + } +} +void dcn42_init_hw(struct dc *dc) +{ + struct abm **abms = dc->res_pool->multiple_abms; + struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct resource_pool *res_pool = dc->res_pool; + int i; + int edp_num; + uint32_t backlight = MAX_BACKLIGHT_LEVEL; + uint32_t user_level = MAX_BACKLIGHT_LEVEL; + int current_dchub_ref_freq = 0; + + if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) { + dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); + + // mark dcmode limits present if any clock has distinct AC and DC values from SMU + dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present && + dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr); + } + + // Initialize the dccg + if (res_pool->dccg->funcs->dccg_init) + res_pool->dccg->funcs->dccg_init(res_pool->dccg); + + // Disable DMUB Initialization until IPS state programming is finalized + //if (!dcb->funcs->is_accelerated_mode(dcb)) { + // hws->funcs.bios_golden_init(dc); + //} + + // Set default OPTC memory power states + if (dc->debug.enable_mem_low_power.bits.optc) { + // Shutdown when unassigned and light sleep in VBLANK + REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); + } + + if (dc->debug.enable_mem_low_power.bits.vga) { + // Power down VGA memory + REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); + } + + if (dc->ctx->dc_bios->fw_info_valid) { + res_pool->ref_clocks.xtalin_clock_inKhz = + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; + + if (res_pool->hubbub) { + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + current_dchub_ref_freq = res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } + } else + ASSERT_CRITICAL(false); + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). + */ + struct dc_link *link = dc->links[i]; + + if (link->ep_type != DISPLAY_ENDPOINT_PHY) + continue; + + link->link_enc->funcs->hw_init(link->link_enc); + + /* Check for enabled DIG to identify enabled display */ + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) { + link->link_status.link_active = true; + link->phy_state.symclk_state = SYMCLK_ON_TX_ON; + if (link->link_enc->funcs->fec_is_active && + link->link_enc->funcs->fec_is_active(link->link_enc)) + link->fec_state = dc_link_fec_enabled; + } + } + + /* enable_power_gating_plane before dsc_pg_control because + * FORCEON = 1 with hw default value on bootup, resume from s3 + */ + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(dc->hwseq, true); + + /* we want to turn off all dp displays before doing detection */ + dc->link_srv->blank_all_dp_displays(dc); + + /* If taking control over from VBIOS, we may want to optimize our first + * mode set, so we need to skip powering down pipes until we know which + * pipes we want to use. + * Otherwise, if taking control is not possible, we need to power + * everything down. + */ + if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { + /* Disable boot optimizations means power down everything including PHY, DIG, + * and OTG (i.e. the boot is not optimized because we do a full power down). + */ + if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations) + dc->hwss.enable_accelerated_mode(dc, dc->current_state); + else + hws->funcs.init_pipes(dc, dc->current_state); + + if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) + dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, + !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); + + } + + /* In headless boot cases, DIG may be turned + * on which causes HW/SW discrepancies. + * To avoid this, power down hardware on boot + * if DIG is turned on and seamless boot not enabled + */ + if (!dc->config.seamless_boot_edp_requested) { + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link; + + dc_get_edp_links(dc, edp_links, &edp_num); + if (edp_num) { + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwss.edp_backlight_control && + hws->funcs.power_down && + dc->hwss.edp_power_control) { + dc->hwss.edp_backlight_control(edp_link, false); + hws->funcs.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } + } + } else { + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc) && + hws->funcs.power_down) { + hws->funcs.power_down(dc); + break; + } + + } + } + } + + for (i = 0; i < res_pool->audio_count; i++) { + struct audio *audio = res_pool->audios[i]; + + audio->funcs->hw_init(audio); + } + + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->panel_cntl) { + backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); + user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL; + } + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (abms[i] != NULL && abms[i]->funcs != NULL) + abms[i]->funcs->abm_init(abms[i], backlight, user_level); + } + + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + + dcn401_setup_hpo_hw_control(hws, true); + + if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) + dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); + + if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges) + dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); + + if (dc->res_pool->hubbub->funcs->force_pstate_change_control) + dc->res_pool->hubbub->funcs->force_pstate_change_control( + dc->res_pool->hubbub, false, false); + + if (dc->res_pool->hubbub->funcs->init_crb) + dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); + + if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) + dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); + + // Get DMCUB capabilities + if (dc->ctx->dmub_srv) { + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); + dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; + dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0; + dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; + dc->debug.fams2_config.bits.enable &= + dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; // sw & fw fams versions must match for support + if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box) + || res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq) { + /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ + if (dc->clk_mgr) + dc->res_pool->funcs->update_bw_bounding_box(dc, + dc->clk_mgr->bw_params); + } + } + if (dc->res_pool->pg_cntl) { + if (dc->res_pool->pg_cntl->funcs->init_pg_status) + dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl); + } + print_pg_status(dc, __func__, ": after init_pg_status"); +} + +void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct mpcc_blnd_cfg blnd_cfg = {0}; + bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; + int mpcc_id; + struct mpcc *new_mpcc; + struct mpc *mpc = dc->res_pool->mpc; + struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); + + + blnd_cfg.overlap_only = false; + blnd_cfg.global_gain = 0xfff; + + if (per_pixel_alpha) { + blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; + if (pipe_ctx->plane_state->global_alpha) { + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; + } else { + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; + } + } else { + blnd_cfg.pre_multiplied_alpha = false; + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + } + + if (pipe_ctx->plane_state->global_alpha) + blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; + else + blnd_cfg.global_alpha = 0xfff; + + blnd_cfg.background_color_bpc = 4; + blnd_cfg.bottom_gain_mode = 0; + blnd_cfg.top_gain = 0x1f000; + blnd_cfg.bottom_inside_gain = 0x1f000; + blnd_cfg.bottom_outside_gain = 0x1f000; + + if (pipe_ctx->plane_state->format + == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) + blnd_cfg.pre_multiplied_alpha = false; + + /* + * TODO: remove hack + * Note: currently there is a bug in init_hw such that + * on resume from hibernate, BIOS sets up MPCC0, and + * we do mpcc_remove but the mpcc cannot go to idle + * after remove. This cause us to pick mpcc1 here, + * which causes a pstate hang for yet unknown reason. + */ + mpcc_id = hubp->inst; + + /* If there is no full update, don't need to touch MPC tree*/ + if (!pipe_ctx->plane_state->update_flags.bits.full_update && + !pipe_ctx->update_flags.bits.mpcc) { + mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); + return; + } + + /* check if this MPCC is already being used */ + new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); + /* remove MPCC if being used */ + if (new_mpcc != NULL) + mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); + else + if (dc->debug.sanity_checks) + mpc->funcs->assert_mpcc_idle_before_connect( + dc->res_pool->mpc, mpcc_id); + + /* Call MPC to insert new plane */ + new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, + mpc_tree_params, + &blnd_cfg, + NULL, + NULL, + hubp->inst, + mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); + + ASSERT(new_mpcc != NULL); + hubp->opp_id = pipe_ctx->stream_res.opp->inst; + hubp->mpcc_id = mpcc_id; +} + +void dcn42_program_cm_hist( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) +{ + struct dpp *dpp = pipe_ctx->plane_res.dpp; + + if (dpp && dpp->funcs->dpp_cm_hist_control) + dpp->funcs->dpp_cm_hist_control(dpp, + plane_state->cm_hist_control, plane_state->color_space); +} + +static void dc_get_lut_xbar( + enum dc_cm2_gpu_mem_pixel_component_order order, + enum hubp_3dlut_fl_crossbar_bit_slice *cr_r, + enum hubp_3dlut_fl_crossbar_bit_slice *y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *cb_b) +{ + switch (order) { + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: + *cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA: + *cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } +} + +static void dc_get_lut_mode( + enum dc_cm2_gpu_mem_layout layout, + enum hubp_3dlut_fl_mode *mode, + enum hubp_3dlut_fl_addressing_mode *addr_mode) +{ + switch (layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + *mode = hubp_3dlut_fl_mode_native_1; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + *mode = hubp_3dlut_fl_mode_native_2; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + *mode = hubp_3dlut_fl_mode_transform; + *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + *mode = hubp_3dlut_fl_mode_disable; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } +} + +static void dc_get_lut_format( + enum dc_cm2_gpu_mem_format dc_format, + enum hubp_3dlut_fl_format *format) +{ + switch (dc_format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + *format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + *format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + *format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } +} + +static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) +{ + if (mpc->funcs->rmcm.power_on_shaper_3dlut && + mpc->funcs->rmcm.fl_3dlut_configure && + hubp->funcs->hubp_program_3dlut_fl_config) + return true; + + return false; +} + +static bool is_rmcm_3dlut_fl_supported(struct dc *dc, enum dc_cm2_gpu_mem_size size) +{ + if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut) + return false; + if (size == DC_CM2_GPU_MEM_SIZE_171717) + return (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17); + else if (size == DC_CM2_GPU_MEM_SIZE_333333) + return (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33); + return false; +} + +static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend) +{ + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = (bPostBlend) ? + MPCC_MOVABLE_CM_LOCATION_AFTER : + MPCC_MOVABLE_CM_LOCATION_BEFORE; +} + +static void dcn42_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, + enum MCM_LUT_XABLE *shaper_xable, + enum MCM_LUT_XABLE *lut3d_xable, + enum MCM_LUT_XABLE *lut1d_xable) +{ + enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; + bool lut1d_enable = false; + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + + if (!pipe_ctx->plane_state) + return; + shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; + lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + + *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; + + switch (shaper_3dlut_setting) { + case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: + *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: + *lut3d_xable = MCM_LUT_DISABLE; + *shaper_xable = MCM_LUT_ENABLE; + break; + case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: + *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; + break; + } +} + +static void fl_get_lut_mode( + enum dc_cm2_gpu_mem_layout layout, + enum dc_cm2_gpu_mem_size size, + enum hubp_3dlut_fl_mode *mode, + enum hubp_3dlut_fl_addressing_mode *addr_mode, + enum hubp_3dlut_fl_width *width) +{ + *width = hubp_3dlut_fl_width_17; + + if (size == DC_CM2_GPU_MEM_SIZE_333333) + *width = hubp_3dlut_fl_width_33; + + switch (layout) { + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: + *mode = hubp_3dlut_fl_mode_native_1; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + *mode = hubp_3dlut_fl_mode_native_2; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + *mode = hubp_3dlut_fl_mode_transform; + *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + default: + *mode = hubp_3dlut_fl_mode_disable; + *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } +} + +bool dcn42_program_rmcm_luts( + struct hubp *hubp, + struct pipe_ctx *pipe_ctx, + enum dc_cm2_transfer_func_source lut3d_src, + struct dc_cm2_func_luts *mcm_luts, + struct mpc *mpc, + bool lut_bank_a, + int mpcc_id) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + union mcm_lut_params m_lut_params = {0}; + enum MCM_LUT_XABLE shaper_xable, lut3d_xable = MCM_LUT_DISABLE, lut1d_xable; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_format format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + enum hubp_3dlut_fl_width width = hubp_3dlut_fl_width_17; + + + struct dc *dc = hubp->ctx->dc; + struct hubp_fl_3dlut_config fl_config; + struct mpc_fl_3dlut_config mpc_fl_config; + + struct dc_stream_state *stream = pipe_ctx->stream; + bool bypass_rmcm_shaper = false; + // true->false when it can be allocated at DI time + struct dc_rmcm_3dlut *rmcm_3dlut = dc_stream_get_3dlut_for_stream(dc, stream, false); + + //check to see current pipe is part of a stream with allocated rmcm 3dlut + if (!rmcm_3dlut) + return false; + + rmcm_3dlut->protection_bits = mcm_luts->lut3d_data.rmcm_tmz; + + dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + + /* Shaper */ + if (mcm_luts->shaper) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + + if (mcm_luts->shaper->type == TF_TYPE_HWPWL) { + m_lut_params.pwl = &mcm_luts->shaper->pwl; + } else if (mcm_luts->shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + cm_helper_translate_curve_to_hw_format( + dc->ctx, + mcm_luts->shaper, + &dpp_base->shaper_params, true); + m_lut_params.pwl = &dpp_base->shaper_params; + } + if (m_lut_params.pwl) { + if (mpc->funcs->rmcm.populate_lut) + mpc->funcs->rmcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->rmcm.program_lut_mode) + mpc->funcs->rmcm.program_lut_mode(mpc, !bypass_rmcm_shaper, lut_bank_a, mpcc_id); + } else { + //RMCM 3dlut won't work without its shaper + return false; + } + } + + /* 3DLUT */ + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + memset(&m_lut_params, 0, sizeof(m_lut_params)); + // Don't know what to do in this case. + //case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + fl_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, + mcm_luts->lut3d_data.gpu_mem_params.size, + &mode, + &addr_mode, + &width); + + if (!dc_is_rmcm_3dlut_supported(hubp, mpc) || + !mpc->funcs->rmcm.is_config_supported( + (width == hubp_3dlut_fl_width_17 || + width == hubp_3dlut_fl_width_transformed) ? 17 : 33)) + return false; + + // setting native or transformed mode, + dc_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); + + //seems to be only for the MCM + dc_get_lut_format(mcm_luts->lut3d_data.gpu_mem_params.format_params.format, &format); + + dc_get_lut_xbar( + mcm_luts->lut3d_data.gpu_mem_params.component_order, + &crossbar_bit_slice_cr_r, + &crossbar_bit_slice_y_g, + &crossbar_bit_slice_cb_b); + + fl_config.mode = mode; + fl_config.enabled = lut3d_xable != MCM_LUT_DISABLE; + fl_config.address = mcm_luts->lut3d_data.gpu_mem_params.addr; + fl_config.format = format; + fl_config.crossbar_bit_slice_y_g = crossbar_bit_slice_y_g; + fl_config.crossbar_bit_slice_cb_b = crossbar_bit_slice_cb_b; + fl_config.crossbar_bit_slice_cr_r = crossbar_bit_slice_cr_r; + fl_config.width = width; + fl_config.protection_bits = rmcm_3dlut->protection_bits; + fl_config.addr_mode = addr_mode; + fl_config.layout = mcm_luts->lut3d_data.gpu_mem_params.layout; + fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; + fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; + + mpc_fl_config.enabled = fl_config.enabled; + mpc_fl_config.width = width; + mpc_fl_config.select_lut_bank_a = lut_bank_a; + mpc_fl_config.bit_depth = mcm_luts->lut3d_data.gpu_mem_params.bit_depth; + mpc_fl_config.hubp_index = hubp->inst; + mpc_fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; + mpc_fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; + + //1. power down the block + mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, false); + + //2. program RMCM - 3dlut reg programming + mpc->funcs->rmcm.fl_3dlut_configure(mpc, &mpc_fl_config, mpcc_id); + + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &fl_config); + + //3. power on the block + mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, true); + + break; + default: + return false; + } + + return true; +} + +void dcn42_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + int mpcc_id = hubp->inst; + struct mpc *mpc = dc->res_pool->mpc; + union mcm_lut_params m_lut_params; + enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; + enum hubp_3dlut_fl_format format = 0; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_width width = 0; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; + enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; + enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + bool rval; + + dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + + //MCM - setting its location (Before/After) blender + //set to post blend (true) + dcn42_set_mcm_location_post_blend( + dc, + pipe_ctx, + mcm_luts.lut3d_data.mpc_mcm_post_blend); + + //RMCM - 3dLUT+Shaper + if (mcm_luts.lut3d_data.rmcm_3dlut_enable && + is_rmcm_3dlut_fl_supported(dc, mcm_luts.lut3d_data.gpu_mem_params.size)) { + dcn42_program_rmcm_luts( + hubp, + pipe_ctx, + lut3d_src, + &mcm_luts, + mpc, + lut_bank_a, + mpcc_id); + } + + /* 1D LUT */ + if (mcm_luts.lut1d_func) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; + else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.lut1d_func, + &dpp_base->regamma_params, false); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } + + /* Shaper */ + if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (mcm_luts.shaper->type == TF_TYPE_HWPWL) + m_lut_params.pwl = &mcm_luts.shaper->pwl; + else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, + mcm_luts.shaper, + &dpp_base->regamma_params, true); + m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + } + if (m_lut_params.pwl) { + if (mpc->funcs->mcm.populate_lut) + mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + } + } + + /* 3DLUT */ + switch (lut3d_src) { + case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); + + if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { + m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, + mpcc_id); + } + break; + case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: + switch (mcm_luts.lut3d_data.gpu_mem_params.size) { + case DC_CM2_GPU_MEM_SIZE_333333: + width = hubp_3dlut_fl_width_33; + break; + case DC_CM2_GPU_MEM_SIZE_171717: + width = hubp_3dlut_fl_width_17; + break; + case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + width = hubp_3dlut_fl_width_transformed; + break; + default: + //TODO: Handle default case + break; + } + + //check for support + if (mpc->funcs->mcm.is_config_supported && + !mpc->funcs->mcm.is_config_supported(width)) + break; + + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); + + if (mpc->funcs->mcm.program_bit_depth) + mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); + + dc_get_lut_mode(mcm_luts.lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); + if (hubp->funcs->hubp_program_3dlut_fl_mode) + hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + + if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) + hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + + switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: + format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: + format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: + format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + } + if (hubp->funcs->hubp_program_3dlut_fl_format) + hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); + if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && + mpc->funcs->mcm.program_bias_scale) { + mpc->funcs->mcm.program_bias_scale(mpc, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, + mpcc_id); + hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, + mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); + } + + //navi 4x has a bug and r and blue are swapped and need to be worked around here in + //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x + dc_get_lut_xbar( + mcm_luts.lut3d_data.gpu_mem_params.component_order, + &crossbar_bit_slice_cr_r, + &crossbar_bit_slice_y_g, + &crossbar_bit_slice_cb_b); + + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, + crossbar_bit_slice_cr_r, + crossbar_bit_slice_y_g, + crossbar_bit_slice_cb_b); + + if (mpc->funcs->mcm.program_lut_read_write_control) + mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + + if (mpc->funcs->mcm.program_3dlut_size) + mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); + + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + else { + if (mpc->funcs->program_lut_mode) { + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); + } + } + break; + } +} + +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + int mpcc_id = pipe_ctx->plane_res.hubp->inst; + struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; + struct mpc *mpc = dc->res_pool->mpc; + bool result; + const struct pwl_params *lut_params = NULL; + bool rval; + + if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); + return true; + } + + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); + pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; + // 1D LUT + if (plane_state->blend_tf.type == TF_TYPE_HWPWL) + lut_params = &plane_state->blend_tf.pwl; + else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->blend_tf, + &dpp_base->regamma_params, false); + lut_params = rval ? &dpp_base->regamma_params : NULL; + } + result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); + lut_params = NULL; + + // Shaper + if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) + lut_params = &plane_state->in_shaper_func.pwl; + else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + // TODO: dpp_base replace + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &plane_state->in_shaper_func, + &dpp_base->shaper_params, true); + lut_params = rval ? &dpp_base->shaper_params : NULL; + } + result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); + + // 3D + if (mpc->funcs->program_3dlut) { + if (plane_state->lut3d_func.state.bits.initialized == 1) + result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); + else + result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); + } + + return result; +} +void dcn42_hardware_release(struct dc *dc) +{ + dcn35_hardware_release(dc); + +} +static int count_active_streams(const struct dc *dc) +{ + int i, count = 0; + + for (i = 0; i < dc->current_state->stream_count; ++i) { + struct dc_stream_state *stream = dc->current_state->streams[i]; + + if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off)) + count += 1; + } + + return count; +} + +void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state) +{ + bool hpo_frl_stream_enc_acquired = false; + bool hpo_dp_stream_enc_acquired = false; + int i = 0, j = 0; + + memset(update_state, 0, sizeof(struct pg_block_update)); + + update_state->pg_res_update[PG_DIO] = true; + + for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && + dc->res_pool->hpo_dp_stream_enc[i]) { + hpo_dp_stream_enc_acquired = true; + break; + } + } + + if (!hpo_frl_stream_enc_acquired && !hpo_dp_stream_enc_acquired) + update_state->pg_res_update[PG_HPO] = true; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) + update_state->pg_pipe_res_update[j][i] = true; + + if (!pipe_ctx) + continue; + + if (pipe_ctx->plane_res.hubp) + update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false; + + if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp) + update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false; + + if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp) + update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false; + + if (pipe_ctx->stream_res.dsc) { + update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false; + if (dc->caps.sequential_ono) { + update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false; + update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false; + } + } + if (pipe_ctx->stream_res.opp) + update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false; + + if (pipe_ctx->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false; + + if (pipe_ctx->link_res.dio_link_enc) { + update_state->pg_res_update[PG_DIO] = false; + } + if (pipe_ctx->link_res.hpo_dp_link_enc) { + update_state->pg_res_update[PG_HPO] = false; + } + } + + + for (i = 0; i < dc->link_count; i++) { + update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; + if (dc->links[i]->type != dc_connection_none) + update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false; + } + + /*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/ + for (i = 0; i < dc->res_pool->timing_generator_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + if (tg && tg->funcs->is_tg_enabled(tg)) { + update_state->pg_pipe_res_update[PG_OPTC][i] = false; + } else { + // Update pg_pipe_res_enable state + if (dc->res_pool->pg_cntl->funcs->optc_pg_control) + dc->res_pool->pg_cntl->funcs->optc_pg_control(dc->res_pool->pg_cntl, i, false); + } + } + +} + +void dcn42_prepare_bandwidth( + struct dc *dc, + struct dc_state *context) +{ + + struct pg_block_update pg_update_state; + + if (dc->hwss.calc_blocks_to_ungate) { + dc->hwss.calc_blocks_to_ungate(dc, context, &pg_update_state); + + if (dc->hwss.root_clock_control) + dc->hwss.root_clock_control(dc, &pg_update_state, true); + /*power up required HW block*/ + if (dc->hwss.hw_block_power_up) + dc->hwss.hw_block_power_up(dc, &pg_update_state); + } + + dcn20_prepare_bandwidth(dc, context); +} + +void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context) +{ + struct pg_block_update pg_update_state; + + print_pg_status(dc, __func__, ": before rcg and power up"); + + dcn401_optimize_bandwidth(dc, context); + + if (dc->hwss.calc_blocks_to_gate) { + dc->hwss.calc_blocks_to_gate(dc, context, &pg_update_state); + /*try to power down unused block*/ + if (dc->hwss.hw_block_power_down) + dc->hwss.hw_block_power_down(dc, &pg_update_state); + + if (dc->hwss.root_clock_control) + dc->hwss.root_clock_control(dc, &pg_update_state, false); + } + + print_pg_status(dc, __func__, ": after rcg and power up"); + +} + +void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state) +{ + bool hpo_frl_stream_enc_acquired = false; + bool hpo_dp_stream_enc_acquired = false; + int i = 0, j = 0; + + memset(update_state, 0, sizeof(struct pg_block_update)); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; + + if (cur_pipe == NULL || new_pipe == NULL) + continue; + + if ((!cur_pipe->plane_state && new_pipe->plane_state) || + (!cur_pipe->stream && new_pipe->stream) || + (cur_pipe->stream != new_pipe->stream && new_pipe->stream)) { + // New pipe addition + for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) { + if (j == PG_HUBP && new_pipe->plane_res.hubp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true; + + if (j == PG_DPP && new_pipe->plane_res.dpp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true; + + if (j == PG_MPCC && new_pipe->plane_res.dpp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true; + + if (j == PG_DSC && new_pipe->stream_res.dsc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true; + + if (j == PG_OPP && new_pipe->stream_res.opp) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true; + + if (j == PG_OPTC && new_pipe->stream_res.tg) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true; + + if (j == PG_DPSTREAM && new_pipe->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true; + } + } else if (cur_pipe->plane_state == new_pipe->plane_state || + cur_pipe == new_pipe) { + //unchanged pipes + for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) { + if (j == PG_HUBP && + cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp && + new_pipe->plane_res.hubp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true; + + if (j == PG_DPP && + cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp && + new_pipe->plane_res.dpp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true; + + if (j == PG_OPP && + cur_pipe->stream_res.opp != new_pipe->stream_res.opp && + new_pipe->stream_res.opp) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true; + + if (j == PG_DSC && + cur_pipe->stream_res.dsc != new_pipe->stream_res.dsc && + new_pipe->stream_res.dsc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true; + + if (j == PG_OPTC && + cur_pipe->stream_res.tg != new_pipe->stream_res.tg && + new_pipe->stream_res.tg) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true; + + if (j == PG_DPSTREAM && + cur_pipe->stream_res.hpo_dp_stream_enc != new_pipe->stream_res.hpo_dp_stream_enc && + new_pipe->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true; + } + } + } + + for (i = 0; i < dc->link_count; i++) + if (dc->links[i]->type != dc_connection_none) + update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; + + for (i = 0; i < dc->res_pool->stream_enc_count; i++) { + if (dc->current_state->res_ctx.is_stream_enc_acquired[i]) { + update_state->pg_res_update[PG_DIO] = true; + break; + } + } + for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && + dc->res_pool->hpo_dp_stream_enc[i]) { + hpo_dp_stream_enc_acquired = true; + break; + } + } + + if (hpo_frl_stream_enc_acquired || hpo_dp_stream_enc_acquired) + update_state->pg_res_update[PG_HPO] = true; + + if (hpo_frl_stream_enc_acquired) + update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true; + + if (count_active_streams(dc) > 0) { + update_state->pg_res_update[PG_DCCG] = true; + update_state->pg_res_update[PG_DCIO] = true; + update_state->pg_res_update[PG_DCHUBBUB] = true; + update_state->pg_res_update[PG_DCHVM] = true; + update_state->pg_res_update[PG_DCOH] = true; + } +} +/** + * dcn42_hw_block_power_down() - power down sequence + * + * The following sequence describes the ON-OFF (ONO) for power down: + * + * ONO Region 4, DCPG 25: hpo + * ONO Region 11, DCPG 3: dchubp3, dpp3 + * ONO Region 9, DCPG 2: dchubp2, dpp2 + * ONO Region 7, DCPG 1: dchubp1, dpp1 + * ONO Region 5, DCPG 0: dchubp0, dpp0 + * ONO Region 2, DCPG 23: dchubbub, dchububmem, dchvm + * ONO Region 12, DCPG 19: dsc3 + * ONO Region 10, DCPG 18: dsc2 + * ONO Region 8, DCPG 17: dsc1 + * ONO Region 6, DCPG 16: dsc0 + * ONO Region 3, DCPG 24: mpc, opp, optc, dwb + * ONO Region 1, DCPG 26: dio + * ONO Region 0, DCPG 22: dccg dcio dcoh - SKIPPED + * + * No seuential ONO power up/down order for DCN42 + * Driver PG should only be limited to DCHUBP/DPP, DSC, HPO and DIO, so further optimization can be done + * + * @dc: Current DC state + * @update_state: update PG sequence states for HW block + */ + void dcn42_hw_block_power_down(struct dc *dc, + struct pg_block_update *update_state) +{ + int i = 0; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + bool block_disabled = true; + + if (!pg_cntl) + return; + if (dc->debug.ignore_pg) + return; + + if (update_state->pg_res_update[PG_HPO]) { + if (pg_cntl->funcs->hpo_pg_control) + pg_cntl->funcs->hpo_pg_control(pg_cntl, false); + } + + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (pg_cntl->funcs->hubp_dpp_pg_control) + pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false); + } + } + + if (update_state->pg_res_update[PG_DCHUBBUB]) { + if (pg_cntl->funcs->mem_pg_control) + pg_cntl->funcs->mem_pg_control(pg_cntl, false); + } + + for (i = dc->res_pool->res_cap->num_dsc-1; i >= 0; i--) { + if (update_state->pg_pipe_res_update[PG_DSC][i]) { + if (pg_cntl->funcs->dsc_pg_control) + pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false); + } + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!update_state->pg_pipe_res_update[PG_MPCC][i] || + !update_state->pg_pipe_res_update[PG_OPP][i] || + !update_state->pg_pipe_res_update[PG_OPTC][i]) { + block_disabled = false; + break; + } + } + + if (block_disabled) { + if (pg_cntl->funcs->plane_otg_pg_control) + pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false); + } + + if (update_state->pg_res_update[PG_DIO]) { + if (pg_cntl->funcs->dio_pg_control) + pg_cntl->funcs->dio_pg_control(pg_cntl, false); + } + + if (update_state->pg_res_update[PG_DCCG] && + update_state->pg_res_update[PG_DCIO] && + update_state->pg_res_update[PG_DCOH]) { + // Driver PG should not power down DCCG, DCIO, DCOH. This is handled by IPS. + if (pg_cntl->funcs->io_clk_pg_control) + pg_cntl->funcs->io_clk_pg_control(pg_cntl, false); + } +} + +/** + * dcn42_hw_block_power_up() - power up sequence + * + * The following sequence describes the ON-OFF (ONO) for power up: + * + * ONO Region 0, DCPG 22: dccg dcio dcoh + * ONO Region 1, DCPG 26: dio + * ONO Region 3, DCPG 24: mpc, opp, optc, dwb + * ONO Region 6, DCPG 16: dsc0 + * ONO Region 8, DCPG 17: dsc1 + * ONO Region 10, DCPG 18: dsc2 + * ONO Region 12, DCPG 19: dsc3 + * ONO Region 2, DCPG 23: dchubbub, dchububmem, dchvm + * ONO Region 5, DCPG 0: dchubp0, dpp0 + * ONO Region 7, DCPG 1: dchubp1, dpp1 + * ONO Region 9, DCPG 2: dchubp2, dpp2 + * ONO Region 11, DCPG 3: dchubp3, dpp3 + * ONO Region 4, DCPG 25: hpo + + * No sequential power up/down ordering for DCN42 + * + * @dc: Current DC state + * @update_state: update PG sequence states for HW block + */ +void dcn42_hw_block_power_up(struct dc *dc, + struct pg_block_update *update_state) +{ + int i = 0; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + bool block_enabled = false; + + if (!pg_cntl) + return; + if (dc->debug.ignore_pg) + return; + + if (update_state->pg_res_update[PG_DCCG] || + update_state->pg_res_update[PG_DCIO] || + update_state->pg_res_update[PG_DCOH]) { + if (pg_cntl->funcs->io_clk_pg_control) + pg_cntl->funcs->io_clk_pg_control(pg_cntl, true); + } + + if (update_state->pg_res_update[PG_DIO]) { + if (pg_cntl->funcs->dio_pg_control) + pg_cntl->funcs->dio_pg_control(pg_cntl, true); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_MPCC][i] || + update_state->pg_pipe_res_update[PG_OPP][i] || + update_state->pg_pipe_res_update[PG_OPTC][i]) { + block_enabled = true; + break; + } + } + if (block_enabled) { + if (pg_cntl->funcs->plane_otg_pg_control) + pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true); + } + + for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + if (update_state->pg_pipe_res_update[PG_DSC][i]) { + if (pg_cntl->funcs->dsc_pg_control) + pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true); + } + } + + if (update_state->pg_res_update[PG_DCHUBBUB]) { + if (pg_cntl->funcs->mem_pg_control) + pg_cntl->funcs->mem_pg_control(pg_cntl, true); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (pg_cntl->funcs->hubp_dpp_pg_control) + pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true); + } + } + if (update_state->pg_res_update[PG_HPO]) { + if (pg_cntl->funcs->hpo_pg_control) + pg_cntl->funcs->hpo_pg_control(pg_cntl, true); + } +} +void dcn42_root_clock_control(struct dc *dc, + struct pg_block_update *update_state, bool power_on) +{ + int i = 0; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + + if (!pg_cntl) + return; + /*enable root clock first when power up*/ + if (power_on) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (dc->hwseq->funcs.dpp_root_clock_control) + dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on); + } + if (update_state->pg_pipe_res_update[PG_DPSTREAM][i]) + if (dc->hwseq->funcs.dpstream_root_clock_control) + dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on); + } + + for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) + if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i]) + if (dc->hwseq->funcs.physymclk_root_clock_control) + dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); + + } + for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + if (update_state->pg_pipe_res_update[PG_DSC][i]) { + if (power_on) { + if (dc->res_pool->dccg->funcs->enable_dsc) + dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i); + } else { + if (dc->res_pool->dccg->funcs->disable_dsc) + dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i); + } + } + } + /*disable root clock first when power down*/ + if (!power_on) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (dc->hwseq->funcs.dpp_root_clock_control) + dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on); + } + if (update_state->pg_pipe_res_update[PG_DPSTREAM][i]) + if (dc->hwseq->funcs.dpstream_root_clock_control) + dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on); + } + + for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) + if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i]) + if (dc->hwseq->funcs.physymclk_root_clock_control) + dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); + + } +} +void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) +{ + struct crtc_stereo_flags flags = { 0 }; + struct dc_stream_state *stream = pipe_ctx->stream; + + dcn10_config_stereo_parameters(stream, &flags); + + pipe_ctx->stream_res.opp->funcs->opp_program_stereo( + pipe_ctx->stream_res.opp, + flags.PROGRAM_STEREO == 1, + &stream->timing); + + pipe_ctx->stream_res.tg->funcs->program_stereo( + pipe_ctx->stream_res.tg, + &stream->timing, + &flags); + + return; +} +void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock) +{ + + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + + if (!dc->ctx || !dc->ctx->dmub_srv) + return; + + /* Use helper to check PSR/Replay for all streams in context */ + + if (!dc->debug.fams2_config.bits.enable && !dc_dmub_srv_is_cursor_offload_enabled(dc) + && !dmub_hw_lock_mgr_does_context_require_lock(dc, context)) + return; + + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); +} + +void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params) +{ + struct dc *dc = params->dmub_hw_control_lock_fast_params.dc; + bool lock = params->dmub_hw_control_lock_fast_params.lock; + + /* Use helper to check PSR/Replay for the given stream in fast path */ + if (params->dmub_hw_control_lock_fast_params.is_required) { + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h new file mode 100644 index 0000000000000..89ebb6520eaf5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DC_HWSS_DCN42_H__ +#define __DC_HWSS_DCN42_H__ + +#include "dc.h" +#include "hw_sequencer_private.h" + +void dcn42_init_hw(struct dc *dc); +void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx); + +void dcn42_program_cm_hist( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); + +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); + +void dcn42_populate_mcm_luts(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_cm2_func_luts mcm_luts, + bool lut_bank_a); + +bool dcn42_program_rmcm_luts( + struct hubp *hubp, + struct pipe_ctx *pipe_ctx, + enum dc_cm2_transfer_func_source lut3d_src, + struct dc_cm2_func_luts *mcm_luts, + struct mpc *mpc, + bool lut_bank_a, + int mpcc_id); +void dcn42_hardware_release(struct dc *dc); + +void dcn42_prepare_bandwidth( + struct dc *dc, + struct dc_state *context); +void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context); +void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state); +void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state); +void dcn42_hw_block_power_down(struct dc *dc, + struct pg_block_update *update_state); +void dcn42_hw_block_power_up(struct dc *dc, + struct pg_block_update *update_state); +void dcn42_root_clock_control(struct dc *dc, + struct pg_block_update *update_state, bool power_on); +void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock); +void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params); +void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc); +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c new file mode 100644 index 0000000000000..a8e2f59d5e505 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dce110/dce110_hwseq.h" +#include "dcn10/dcn10_hwseq.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn21/dcn21_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dcn31/dcn31_hwseq.h" +#include "dcn32/dcn32_hwseq.h" +#include "dcn314/dcn314_hwseq.h" +#include "dcn35/dcn35_hwseq.h" +#include "dcn401/dcn401_hwseq.h" +#include "dcn42/dcn42_hwseq.h" +#include "dcn42_init.h" + +static const struct hw_sequencer_funcs dcn42_funcs = { + .program_gamut_remap = dcn401_program_gamut_remap, + .init_hw = dcn42_init_hw, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .power_down_on_boot = dcn35_power_down_on_boot, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn401_program_front_end_for_ctx, + .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling, + .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, + .post_unlock_program_front_end = dcn401_post_unlock_program_front_end, + .update_plane_addr = dcn20_update_plane_addr, + .update_dchub = dcn10_update_dchub, + .update_pending_status = dcn10_update_pending_status, + .program_output_csc = dcn20_program_output_csc, + .trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, + .update_info_frame = dcn31_update_info_frame, + .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, + .enable_stream = dcn401_enable_stream, + .disable_stream = dce110_disable_stream, + .unblank_stream = dcn401_unblank_stream, + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, + .disable_plane = dcn35_disable_plane, + .pipe_control_lock = dcn20_pipe_control_lock, + .interdependent_update_lock = dcn401_interdependent_update_lock, + .cursor_lock = dcn10_cursor_lock, + .prepare_bandwidth = dcn42_prepare_bandwidth, + .optimize_bandwidth = dcn42_optimize_bandwidth, + .update_bandwidth = dcn401_update_bandwidth, + .set_drr = dcn35_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn35_set_static_screen_control, + .setup_stereo = dcn42_setup_stereo, + .set_avmute = dcn30_set_avmute, + .log_hw_state = dcn10_log_hw_state, + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .edp_wait_for_T12 = dce110_edp_wait_for_T12, + .set_cursor_position = dcn401_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, + .program_triplebuffer = dcn20_program_triple_buffer, + .enable_writeback = dcn30_enable_writeback, + .disable_writeback = dcn30_disable_writeback, + .update_writeback = dcn30_update_writeback, + .dmdata_status_done = dcn20_dmdata_status_done, + .program_dmdata_engine = dcn30_program_dmdata_engine, + .set_dmdata_attributes = dcn20_set_dmdata_attributes, + .init_sys_ctx = dcn31_init_sys_ctx, + .init_vm_ctx = dcn20_init_vm_ctx, + .set_flip_control_gsl = dcn20_set_flip_control_gsl, + .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + .calc_vupdate_position = dcn10_calc_vupdate_position, + .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, + .does_plane_fit_in_mall = NULL, + .set_backlight_level = dcn31_set_backlight_level, + .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, + .hardware_release = dcn42_hardware_release, + .set_pipe = dcn21_set_pipe, + .enable_lvds_link_output = dce110_enable_lvds_link_output, + .enable_tmds_link_output = dce110_enable_tmds_link_output, + .enable_dp_link_output = dce110_enable_dp_link_output, + .disable_link_output = dcn401_disable_link_output, + .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, + .optimize_pwr_state = dcn21_optimize_pwr_state, + .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, + .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .enable_phantom_streams = dcn32_enable_phantom_streams, + .disable_phantom_streams = dcn32_disable_phantom_streams, + .update_visual_confirm_color = dcn10_update_visual_confirm_color, + .update_phantom_vp_position = dcn32_update_phantom_vp_position, + .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, + .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation, + .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, + .dmub_hw_control_lock = dcn42_dmub_hw_control_lock, + .fams2_update_config = dcn401_fams2_update_config, + .dmub_hw_control_lock_fast = dcn42_dmub_hw_control_lock_fast, + .program_outstanding_updates = dcn401_program_outstanding_updates, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, + .detect_pipe_changes = dcn401_detect_pipe_changes, + .enable_plane = dcn35_enable_plane, + .update_dchubp_dpp = dcn20_update_dchubp_dpp, + .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, + // Driver PG + .hw_block_power_up = dcn42_hw_block_power_up, + .hw_block_power_down = dcn42_hw_block_power_down, + .root_clock_control = dcn42_root_clock_control, + .calc_blocks_to_gate = dcn42_calc_blocks_to_gate, + .calc_blocks_to_ungate = dcn42_calc_blocks_to_ungate, + +}; + +static const struct hwseq_private_funcs dcn42_private_funcs = { + .init_pipes = dcn35_init_pipes, + .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .update_mpcc = dcn42_update_mpcc, + .set_input_transfer_func = dcn32_set_input_transfer_func, + .set_output_transfer_func = dcn401_set_output_transfer_func, + .power_down = dce110_power_down, + .enable_display_power_gating = dcn10_dummy_display_power_gating, + .blank_pixel_data = dcn20_blank_pixel_data, + .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap, + .enable_stream_timing = dcn401_enable_stream_timing, + .edp_backlight_control = dce110_edp_backlight_control, + .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = dcn32_init_blank, + .disable_vga = dcn20_disable_vga, + .bios_golden_init = dcn10_bios_golden_init, + .plane_atomic_disable = dcn35_plane_atomic_disable, + .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, + .update_odm = dcn401_update_odm, + .dsc_pg_status = dcn32_dsc_pg_status, + .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .wait_for_blank_complete = dcn20_wait_for_blank_complete, + .set_mcm_luts = dcn42_set_mcm_luts, + .program_mall_pipe_config = dcn32_program_mall_pipe_config, + .update_mall_sel = dcn32_update_mall_sel, + .calculate_dccg_k1_k2_values = NULL, + .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, + .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe, + .populate_mcm_luts = NULL, + .perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock, + .program_cm_hist = dcn42_program_cm_hist, + .dpp_root_clock_control = dcn35_dpp_root_clock_control, + .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, + .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, + .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, +}; + +void dcn42_hw_sequencer_init_functions(struct dc *dc) +{ + dc->hwss = dcn42_funcs; + dc->hwseq->funcs = dcn42_private_funcs; + +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h new file mode 100644 index 0000000000000..f66eb752eeebf --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DC_DCN42_INIT_H__ +#define __DC_DCN42_INIT_H__ + +struct dc; + +void dcn42_hw_sequencer_init_functions(struct dc *dc); + +#endif /* __DC_DCN401_INIT_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c new file mode 100644 index 0000000000000..19e0741c62cda --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "include/logger_interface.h" +#include "../dce110/irq_service_dce110.h" + +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" + +#include "irq_service_dcn42.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +static enum dc_irq_source to_dal_irq_source_dcn42( + struct irq_service *irq_service, + uint32_t src_id, + uint32_t ext_id) +{ + switch (src_id) { + case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK1; + case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK2; + case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK3; + case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK4; + case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK5; + case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; + case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP1; + case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP2; + case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP3; + case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP4; + case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP5; + case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP6; + case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE1; + case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE2; + case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE3; + case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE4; + case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE5; + case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE6; + case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX; + case DCN_1_0__SRCID__DC_HPD1_INT: + /* generic src_id for all HPD and HPDRX interrupts */ + switch (ext_id) { + case DCN_1_0__CTXID__DC_HPD1_INT: + return DC_IRQ_SOURCE_HPD1; + case DCN_1_0__CTXID__DC_HPD2_INT: + return DC_IRQ_SOURCE_HPD2; + case DCN_1_0__CTXID__DC_HPD3_INT: + return DC_IRQ_SOURCE_HPD3; + case DCN_1_0__CTXID__DC_HPD4_INT: + return DC_IRQ_SOURCE_HPD4; + case DCN_1_0__CTXID__DC_HPD5_INT: + return DC_IRQ_SOURCE_HPD5; + case DCN_1_0__CTXID__DC_HPD6_INT: + return DC_IRQ_SOURCE_HPD6; + case DCN_1_0__CTXID__DC_HPD1_RX_INT: + return DC_IRQ_SOURCE_HPD1RX; + case DCN_1_0__CTXID__DC_HPD2_RX_INT: + return DC_IRQ_SOURCE_HPD2RX; + case DCN_1_0__CTXID__DC_HPD3_RX_INT: + return DC_IRQ_SOURCE_HPD3RX; + case DCN_1_0__CTXID__DC_HPD4_RX_INT: + return DC_IRQ_SOURCE_HPD4RX; + case DCN_1_0__CTXID__DC_HPD5_RX_INT: + return DC_IRQ_SOURCE_HPD5RX; + case DCN_1_0__CTXID__DC_HPD6_RX_INT: + return DC_IRQ_SOURCE_HPD6RX; + default: + return DC_IRQ_SOURCE_INVALID; + } + break; + default: + return DC_IRQ_SOURCE_INVALID; + } + +} + +static struct irq_source_info_funcs hpd_irq_info_funcs = { + .set = NULL, + .ack = hpd0_ack +}; + +static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs pflip_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vblank_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs outbox_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vline1_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vline2_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +/* compile time expand base address. */ +#define BASE(seg) \ + BASE_INNER(seg) + +#define SRI(reg_name, block, id)\ + (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name) + +#define SRI_DMUB(reg_name)\ + (BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name) + +#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ + .enable_reg = SRI(reg1, block, reg_num),\ + .enable_mask = \ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI(reg2, block, reg_num),\ + .ack_mask = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ + +#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ + .enable_reg = SRI_DMUB(reg1),\ + .enable_mask = \ + reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + reg1 ## __ ## mask1 ## _MASK,\ + ~reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI_DMUB(reg2),\ + .ack_mask = \ + reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + reg2 ## __ ## mask2 ## _MASK \ + +#define hpd_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_irq_info_funcs\ + } + +#define hpd_rx_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_rx_irq_info_funcs\ + } +#define pflip_int_entry(reg_num)\ + [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ + IRQ_REG_ENTRY(HUBPREQ, reg_num,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ + .funcs = &pflip_irq_info_funcs\ + } + +#define vblank_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ + .funcs = &vblank_irq_info_funcs\ + } + +#define vupdate_no_lock_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ + .funcs = &vupdate_no_lock_irq_info_funcs\ + } + +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } +#define vline1_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\ + .funcs = &vline1_irq_info_funcs\ + } +#define vline2_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\ + .funcs = &vline2_irq_info_funcs\ + } +#define dmub_outbox_int_entry()\ + [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ + IRQ_REG_ENTRY_DMUB(\ + DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ + DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ + .funcs = &outbox_irq_info_funcs\ + } + +#define dummy_irq_entry() \ + {\ + .funcs = &dummy_irq_info_funcs\ + } + +#define i2c_int_entry(reg_num) \ + [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() + +#define dp_sink_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() + +#define gpio_pad_int_entry(reg_num) \ + [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() + +#define dc_underflow_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() + +static struct irq_source_info_funcs dummy_irq_info_funcs = { + .set = dal_irq_service_dummy_set, + .ack = dal_irq_service_dummy_ack +}; + +static const struct irq_source_info irq_source_info_dcn42[DAL_IRQ_SOURCES_NUMBER] = { + [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), + /* HPD (1-4) */ + hpd_int_entry(0), + hpd_int_entry(1), + hpd_int_entry(2), + hpd_int_entry(3), + /* HPD RX (1-4) */ + hpd_rx_int_entry(0), + hpd_rx_int_entry(1), + hpd_rx_int_entry(2), + hpd_rx_int_entry(3), + /* I2C (1-6) */ + i2c_int_entry(1), + i2c_int_entry(2), + i2c_int_entry(3), + i2c_int_entry(4), + i2c_int_entry(5), + i2c_int_entry(6), + /* DP sink (1-6) keep table shape */ + dp_sink_int_entry(1), + dp_sink_int_entry(2), + dp_sink_int_entry(3), + dp_sink_int_entry(4), + dp_sink_int_entry(5), + dp_sink_int_entry(6), + [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), + /* PFLIP (1-4) */ + pflip_int_entry(0), + pflip_int_entry(1), + pflip_int_entry(2), + pflip_int_entry(3), + [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), + /* GPIO pads */ + gpio_pad_int_entry(0), + gpio_pad_int_entry(1), + gpio_pad_int_entry(2), + gpio_pad_int_entry(3), + gpio_pad_int_entry(4), + gpio_pad_int_entry(5), + gpio_pad_int_entry(6), + gpio_pad_int_entry(7), + gpio_pad_int_entry(8), + gpio_pad_int_entry(9), + gpio_pad_int_entry(10), + gpio_pad_int_entry(11), + gpio_pad_int_entry(12), + gpio_pad_int_entry(13), + gpio_pad_int_entry(14), + gpio_pad_int_entry(15), + gpio_pad_int_entry(16), + gpio_pad_int_entry(17), + gpio_pad_int_entry(18), + gpio_pad_int_entry(19), + gpio_pad_int_entry(20), + gpio_pad_int_entry(21), + gpio_pad_int_entry(22), + gpio_pad_int_entry(23), + gpio_pad_int_entry(24), + gpio_pad_int_entry(25), + gpio_pad_int_entry(26), + gpio_pad_int_entry(27), + gpio_pad_int_entry(28), + gpio_pad_int_entry(29), + gpio_pad_int_entry(30), + /* Underflow (1-4 active, keep 5-6 dummy) */ + dc_underflow_int_entry(1), + dc_underflow_int_entry(2), + dc_underflow_int_entry(3), + dc_underflow_int_entry(4), + dc_underflow_int_entry(5), + dc_underflow_int_entry(6), + [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), + [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), + vblank_int_entry(0), + vblank_int_entry(1), + vblank_int_entry(2), + vblank_int_entry(3), + [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(), + [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(), + dmub_outbox_int_entry(), + vupdate_no_lock_int_entry(0), + vupdate_no_lock_int_entry(1), + vupdate_no_lock_int_entry(2), + vupdate_no_lock_int_entry(3), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline1_int_entry(0), + vline1_int_entry(1), + vline1_int_entry(2), + vline1_int_entry(3), + vline2_int_entry(0), + vline2_int_entry(1), + vline2_int_entry(2), + vline2_int_entry(3), +}; + +static const struct irq_service_funcs irq_service_funcs_dcn42 = { + .to_dal_irq_source = to_dal_irq_source_dcn42 +}; + +static void dcn42_irq_construct(struct irq_service *irq_service, + struct irq_service_init_data *init_data) +{ + dal_irq_service_construct(irq_service, init_data); + irq_service->info = irq_source_info_dcn42; + irq_service->funcs = &irq_service_funcs_dcn42; +} + +struct irq_service *dal_irq_service_dcn42_create(struct irq_service_init_data *init_data) +{ + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL); + + if (!irq_service) + return NULL; + + dcn42_irq_construct(irq_service, init_data); + return irq_service; +} diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h new file mode 100644 index 0000000000000..a3f70bce3a618 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * DCN4.2 IRQ service interface (dal-dev only) + */ +#ifndef __IRQ_SERVICE_DCN42_H__ +#define __IRQ_SERVICE_DCN42_H__ + +#include "../dce110/irq_service_dce110.h" + +struct irq_service *dal_irq_service_dcn42_create( + struct irq_service_init_data *init_data); + +#endif /* __IRQ_SERVICE_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c new file mode 100644 index 0000000000000..4700bdc8701df --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn35/dcn35_mmhubbub.h" +#include "dcn42_mmhubbub.h" +#include "reg_helper.h" + +#define REG(reg) \ + ((const struct dcn35_mmhubbub_registers *)(mcif_wb30->mcif_wb_regs)) \ + ->reg + +#define CTX mcif_wb30->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + ((const struct dcn35_mmhubbub_shift *)(mcif_wb30->mcif_wb_shift)) \ + ->field_name, \ + ((const struct dcn35_mmhubbub_mask *)(mcif_wb30->mcif_wb_mask)) \ + ->field_name + +void dcn42_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled) +{ + REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled); +} diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h new file mode 100644 index 0000000000000..0dd1f0d2eb889 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + + +#ifndef __DCN42_MMHUBBUB_H +#define __DCN42_MMHUBBUB_H + +#include "mcif_wb.h" +#include "dcn32/dcn32_mmhubbub.h" +#include "dcn35/dcn35_mmhubbub.h" + +void dcn42_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled); +#endif // __DCN42_MMHUBBUB_H diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c new file mode 100644 index 0000000000000..304b23109fb0f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c @@ -0,0 +1,1121 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" +#include "dc.h" +#include "dcn42_mpc.h" +#include "dcn10/dcn10_cm_common.h" +#include "basics/conversion.h" +#include "mpc.h" + +#define REG(reg)\ + mpc42->mpc_regs->reg + +#define CTX \ + mpc42->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + mpc42->mpc_shift->field_name, mpc42->mpc_mask->field_name + + +static void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst) +{ + mpcc->mpcc_id = mpcc_inst; + mpcc->dpp_id = 0xf; + mpcc->mpcc_bot = NULL; + mpcc->blnd_cfg.overlap_only = false; + mpcc->blnd_cfg.global_alpha = 0xfff; + mpcc->blnd_cfg.global_gain = 0xfff; + mpcc->blnd_cfg.background_color_bpc = 4; + mpcc->blnd_cfg.bottom_gain_mode = 0; + mpcc->blnd_cfg.top_gain = 0x1f000; + mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; + mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; + mpcc->sm_cfg.enable = false; + mpcc->shared_bottom = false; +} + +void mpc42_update_blending( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); + + REG_UPDATE_5(MPCC_CONTROL[mpcc_id], + MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, + MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, + MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, + MPCC_BG_BPC, blnd_cfg->background_color_bpc, + MPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); + REG_UPDATE_2(MPCC_CONTROL2[mpcc_id], + MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, + MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); + + REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); + REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); + REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); + + mpcc->blnd_cfg = *blnd_cfg; +} + +/* Shaper functions */ +void mpc42_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on) +{ + uint32_t power_status_shaper = 2; + uint32_t power_status_3dlut = 2; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + int max_retries = 10; + + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0); + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, + MPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1:0); + /* wait for memory to fully power up */ + if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } + + /*read status is not mandatory, it is just for debugging*/ + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); + REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); + + if (power_status_shaper != 0 && power_on == true) + BREAK_TO_DEBUGGER(); + + if (power_status_3dlut != 0 && power_on == true) + BREAK_TO_DEBUGGER(); +} + +void mpc42_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], + MPCC_MCM_SHAPER_SCALE_B, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], + MPCC_MCM_SHAPER_SCALE_G, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_SCALE_R[mpcc_id], + MPCC_MCM_SHAPER_SCALE_R, 0x7000); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); +} + + +void mpc42_program_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + uint32_t size = 0xff; + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); + + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, + (width == 33) ? 2 : + (width == 17) ? 0 : 2); + + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); +} + +void mpc42_program_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_R, bias, + MPCC_MCM_3DLUT_OUT_SCALE_R, scale); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_G, bias, + MPCC_MCM_3DLUT_OUT_SCALE_G, scale); + + REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPCC_MCM_3DLUT_OUT_OFFSET_B, bias, + MPCC_MCM_3DLUT_OUT_SCALE_B, scale); +} + +void mpc42_program_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, + (bit_depth == 10) ? 1 : 0); +} + +bool mpc42_is_config_supported(uint32_t width) +{ + if (width == 17) + return true; + + return false; +} + +void mpc42_populate_lut(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id) +{ + const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; + const struct pwl_params *lut_shaper = params.pwl; + + if (lut_shaper == NULL) + return; + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc42_power_on_shaper_3dlut(mpc, mpcc_id, true); + + mpc42_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); + + if (next_mode == LUT_RAM_A) + mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id); + else + mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); + + mpc32_program_shaper_lut( + mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); + + mpc42_power_on_shaper_3dlut(mpc, mpcc_id, false); +} + +void mpc42_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + switch (id) { + case MCM_LUT_3DLUT: + REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, + (!enabled) ? 0 : + (lut_bank_a) ? 1 : 2); + REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + break; + case MCM_LUT_SHAPER: + mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); + break; + default: + break; + } +} + +/* RMCM Shaper functions */ +void mpc42_power_on_rmcm_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on) +{ + uint32_t power_status_shaper = 2; + uint32_t power_status_3dlut = 2; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + int max_retries = 10; + + REG_SET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], 0, + MPC_RMCM_3DLUT_MEM_PWR_DIS, power_on == true ? 0 : 1); + REG_SET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], 0, + MPC_RMCM_SHAPER_MEM_PWR_DIS, power_on == true ? 0 : 1); + /* wait for memory to fully power up */ + if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + REG_WAIT(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + REG_WAIT(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } + + /*read status is not mandatory, it is just for debugging*/ + REG_GET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); + REG_GET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); + + if (power_status_shaper != 0 && power_on == true) + BREAK_TO_DEBUGGER(); + + if (power_status_3dlut != 0 && power_on == true) + BREAK_TO_DEBUGGER(); +} + +void mpc42_configure_rmcm_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_id], + MPC_RMCM_SHAPER_SCALE_B, 0x7000); + REG_UPDATE(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_id], + MPC_RMCM_SHAPER_SCALE_G, 0x7000); + REG_UPDATE(MPC_RMCM_SHAPER_SCALE_R[mpcc_id], + MPC_RMCM_SHAPER_SCALE_R, 0x7000); + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(MPC_RMCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_INDEX, 0); +} + +void mpc42_program_rmcm_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + const struct gamma_curve *curve; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); + + curve = params->arr_curve_points; + if (curve) { + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } +} + + +void mpc42_program_rmcm_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + const struct gamma_curve *curve; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); + + curve = params->arr_curve_points; + if (curve) { + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } +} + +void mpc42_program_rmcm_shaper_lut( + struct mpc *mpc, + const struct pwl_result_data *rgb, + uint32_t num, + uint32_t mpcc_id) +{ + uint32_t i, red, green, blue; + uint32_t red_delta, green_delta, blue_delta; + uint32_t red_value, green_value, blue_value; + + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + for (i = 0; i < num; i++) { + + red = rgb[i].red_reg; + green = rgb[i].green_reg; + blue = rgb[i].blue_reg; + + red_delta = rgb[i].delta_red_reg; + green_delta = rgb[i].delta_green_reg; + blue_delta = rgb[i].delta_blue_reg; + + red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); + green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); + blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); + + REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, red_value); + REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, green_value); + REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, blue_value); + } +} + +void mpc42_enable_3dlut_fl(struct mpc *mpc, bool enable, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + //if enabled cho0se mpc 0, else: off (default value) + REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, enable ? 0 : 0xF); //0xF is not connected + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPC_RMCM_3DLUT_WRITE_EN_MASK, 0); + + REG_UPDATE(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_DIS, enable ? 0 : 3); +} + +void mpc42_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_SET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, + MPC_RMCM_3DLUT_FL_SEL, + hubp_idx); +} + +void mpc42_populate_rmcm_lut(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id) +{ + const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; + const struct pwl_params *lut_shaper = params.pwl; + + if (lut_shaper == NULL) + return; + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, true); + + mpc42_configure_rmcm_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); + + if (next_mode == LUT_RAM_A) + mpc42_program_rmcm_shaper_luta_settings(mpc, lut_shaper, mpcc_id); + else + mpc42_program_rmcm_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); + + mpc42_program_rmcm_shaper_lut( + mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); + + mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, false); +} + +void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + switch (id) { + case MCM_LUT_3DLUT: + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_MODE, + (!enabled) ? 0 : + (lut_bank_a) ? 1 : 2); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_RAM_SEL, + (lut_bank_a) ? 0 : 1); + break; + case MCM_LUT_SHAPER: + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7); + + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_SEL, + lut_bank_a == true ? 0:1); + + REG_SET(MPC_RMCM_SHAPER_LUT_INDEX[mpcc_id], 0, + MPC_RMCM_SHAPER_LUT_INDEX, 0); + break; + default: + break; + } +} + +void mpc42_program_lut_mode(struct mpc *mpc, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + switch (xable) { + case MCM_LUT_DISABLE: + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, 0); + break; + case MCM_LUT_ENABLE: + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + break; + } +} + +void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + uint32_t size = 0xff; + + REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); + + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, + (width == 33) ? 2 : 0); + + REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); +} + +void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_R, bias, + MPC_RMCM_3DLUT_OUT_SCALE_R, scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_G, bias, + MPC_RMCM_3DLUT_OUT_SCALE_G, scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_B, bias, + MPC_RMCM_3DLUT_OUT_SCALE_B, scale); +} + +void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPC_RMCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_30BIT_EN, + (bit_depth == 10) ? 1 : 0); +} + +bool mpc42_is_rmcm_config_supported(uint32_t width) +{ + if (width == 17 || width == 33) + return true; + + return false; +} + +void mpc42_set_fl_config( + struct mpc *mpc, + struct mpc_fl_3dlut_config *cfg, + int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + /* + From: Jie Zhou + + To program any of the memories content. The following sequence is used. + Set the MPCC_OGAM/SHAPER/3DLUT/1DLUT_PWR_DIS to 1 (Only need to set the one + that is being programmed) Set DISPCLK_G_PIPE_GATE_DISABLE to 1 for the + MPCC pipe that’s being used, so the memory’s clock is ungated. Program the + target memory. Set the MPCC_OGAM/SHAPER/3DLUT/1DLUT_PWR_DIS back to 0. + Set DISPCLK_G_PIPE_GATE_DISABLE back to 0 + */ + + //disconnect fl from mpc + REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, + MPCC_MCM_3DLUT_FL_SEL, 0xF); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_30BIT_EN, (cfg->bit_depth == 10) ? 1 : 0); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_RAM_SEL, (cfg->select_lut_bank_a) ? 0 : 1); + + //bias and scale + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_R, cfg->bias, + MPC_RMCM_3DLUT_OUT_SCALE_R, cfg->scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_G, cfg->bias, + MPC_RMCM_3DLUT_OUT_SCALE_G, cfg->scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_B, cfg->bias, + MPC_RMCM_3DLUT_OUT_SCALE_B, cfg->scale); + + //width + REG_UPDATE_2(MPC_RMCM_3DLUT_MODE[mpcc_id], + MPC_RMCM_3DLUT_SIZE, (cfg->width == 33) ? 2 : 0, + MPC_RMCM_3DLUT_MODE, (!cfg->enabled) ? 0 : (cfg->select_lut_bank_a) ? 1 : 2); + + //connect to hubp + REG_SET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, + MPC_RMCM_3DLUT_FL_SEL, cfg->hubp_index); + + //ENABLE + //if enabled pick mpc 0, else: off (0xF) + //in future we'll select specific MPC + REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, cfg->enabled ? 0 : 0xF); +} + +//static void rmcm_program_gamut_remap( +// struct mpc *mpc, +// unsigned int mpcc_id, +// const uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// enum mpcc_gamut_remap_mode_select mode_select) +//{ +// struct color_matrices_reg gamut_regs; +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { +// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// return; +// } +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP) { +// +// if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, +// MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// return; +// } +// +// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; +// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; +// +// switch (mode_select) { +// case MPCC_GAMUT_REMAP_MODE_SELECT_1: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); +// break; +// case MPCC_GAMUT_REMAP_MODE_SELECT_2: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); +// break; +// default: +// break; +// } +// +// cm_helper_program_color_matrices( +// mpc->ctx, +// regval, +// &gamut_regs); +// +// //select coefficient set to use, set A (MODE_1) or set B (MODE_2) +// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// } +//} + +//static bool is_mpc_legacy_gamut_id(enum mpcc_gamut_remap_id gamut_remap_block_id) +//{ +// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || +// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { +// return true; +// } +// return false; +//} +//static void program_gamut_remap( +// struct mpc *mpc, +// unsigned int mpcc_id, +// const uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// enum mpcc_gamut_remap_mode_select mode_select) +//{ +// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) +// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// else +// rmcm_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +//} + +//void mpc42_set_gamut_remap( +// struct mpc *mpc, +// int mpcc_id, +// const struct mpc_grph_gamut_adjustment *adjust) +//{ +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// unsigned int i = 0; +// uint32_t mode_select = 0; +// +// if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) { +// /* Bypass / Disable if type is bypass or hw */ +// program_gamut_remap(mpc, mpcc_id, NULL, +// adjust->mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0); +// } else { +// struct fixed31_32 arr_matrix[12]; +// uint16_t arr_reg_val[12]; +// +// for (i = 0; i < 12; i++) +// arr_matrix[i] = adjust->temperature_matrix[i]; +// +// convert_float_matrix(arr_reg_val, arr_matrix, 12); +// +// if (is_mpc_legacy_gamut_id(adjust->mpcc_gamut_remap_block_id)) +// REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], +// MPCC_GAMUT_REMAP_MODE_CURRENT, &mode_select); +// else +// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], +// MPC_RMCM_GAMUT_REMAP_MODE_CURRENT, &mode_select); +// +// //If current set in use not set A (MODE_1), then use set A, otherwise use set B +// if (mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_1) +// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_1; +// else +// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_2; +// +// program_gamut_remap(mpc, mpcc_id, arr_reg_val, +// adjust->mpcc_gamut_remap_block_id, mode_select); +// } +//} + +//static void read_gamut_remap(struct mpc *mpc, +// int mpcc_id, +// uint16_t *regval, +// enum mpcc_gamut_remap_id gamut_remap_block_id, +// uint32_t *mode_select) +//{ +// struct color_matrices_reg gamut_regs = {0}; +// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); +// +// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) { +// mpc_read_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); +// } +// if (gamut_remap_block_id == MPCC_RMCM_GAMUT_REMAP) { +// //current coefficient set in use +// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], MPC_RMCM_GAMUT_REMAP_MODE, mode_select); +// +// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; +// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; +// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; +// +// switch (*mode_select) { +// case MPCC_GAMUT_REMAP_MODE_SELECT_1: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); +// break; +// case MPCC_GAMUT_REMAP_MODE_SELECT_2: +// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); +// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); +// break; +// default: +// break; +// } +// } +// +// if (*mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// cm_helper_read_color_matrices( +// mpc42->base.ctx, +// regval, +// &gamut_regs); +// } +//} + +//void mpc42_get_gamut_remap(struct mpc *mpc, +// int mpcc_id, +// struct mpc_grph_gamut_adjustment *adjust) +//{ +// uint16_t arr_reg_val[12] = {0}; +// uint32_t mode_select; +// +// read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select); +// +// if (mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { +// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; +// return; +// } +// +// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; +// convert_hw_matrix(adjust->temperature_matrix, +// arr_reg_val, ARRAY_SIZE(arr_reg_val)); +//} + +void mpc42_read_mpcc_state( + struct mpc *mpc, + int mpcc_inst, + struct mpcc_state *s) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + mpc1_read_mpcc_state(mpc, mpcc_inst, s); + + if (mpcc_inst < 2) { + /* RMCM 3DLUT Status */ + REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_3DLUT_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_force, + MPC_RMCM_3DLUT_MEM_PWR_DIS, &s->rmcm_regs.rmcm_3dlut_mem_pwr_dis, + MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_mode, + MPC_RMCM_3DLUT_MEM_PWR_STATE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_state); + + REG_GET_3(MPC_RMCM_3DLUT_MODE[mpcc_inst], MPC_RMCM_3DLUT_SIZE, &s->rmcm_regs.rmcm_3dlut_size, + MPC_RMCM_3DLUT_MODE, &s->rmcm_regs.rmcm_3dlut_mode, + MPC_RMCM_3DLUT_MODE_CURRENT, &s->rmcm_regs.rmcm_3dlut_mode_cur); + + REG_GET_4(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_inst], MPC_RMCM_3DLUT_READ_SEL, &s->rmcm_regs.rmcm_3dlut_read_sel, + MPC_RMCM_3DLUT_30BIT_EN, &s->rmcm_regs.rmcm_3dlut_30bit_en, + MPC_RMCM_3DLUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_3dlut_wr_en_mask, + MPC_RMCM_3DLUT_RAM_SEL, &s->rmcm_regs.rmcm_3dlut_ram_sel); + + REG_GET(MPC_RMCM_3DLUT_OUT_NORM_FACTOR[mpcc_inst], MPC_RMCM_3DLUT_OUT_NORM_FACTOR, &s->rmcm_regs.rmcm_3dlut_out_norm_factor); + + REG_GET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_inst], MPC_RMCM_3DLUT_FL_SEL, &s->rmcm_regs.rmcm_3dlut_fl_sel); + + REG_GET_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_inst], MPC_RMCM_3DLUT_OUT_OFFSET_R, &s->rmcm_regs.rmcm_3dlut_out_offset_r, + MPC_RMCM_3DLUT_OUT_SCALE_R, &s->rmcm_regs.rmcm_3dlut_out_scale_r); + + REG_GET_3(MPC_RMCM_3DLUT_FAST_LOAD_STATUS[mpcc_inst], MPC_RMCM_3DLUT_FL_DONE, &s->rmcm_regs.rmcm_3dlut_fl_done, + MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW, &s->rmcm_regs.rmcm_3dlut_fl_soft_underflow, + MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW, &s->rmcm_regs.rmcm_3dlut_fl_hard_underflow); + + /* RMCM Shaper Status */ + REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_SHAPER_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_shaper_mem_pwr_force, + MPC_RMCM_SHAPER_MEM_PWR_DIS, &s->rmcm_regs.rmcm_shaper_mem_pwr_dis, + MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE, &s->rmcm_regs.rmcm_shaper_mem_pwr_mode, + MPC_RMCM_SHAPER_MEM_PWR_STATE, &s->rmcm_regs.rmcm_shaper_mem_pwr_state); + + REG_GET_2(MPC_RMCM_SHAPER_CONTROL[mpcc_inst], MPC_RMCM_SHAPER_LUT_MODE, &s->rmcm_regs.rmcm_shaper_lut_mode, + MPC_RMCM_SHAPER_MODE_CURRENT, &s->rmcm_regs.rmcm_shaper_mode_cur); + + REG_GET_2(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_inst], MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_shaper_lut_write_en_mask, + MPC_RMCM_SHAPER_LUT_WRITE_SEL, &s->rmcm_regs.rmcm_shaper_lut_write_sel); + + REG_GET(MPC_RMCM_SHAPER_OFFSET_B[mpcc_inst], MPC_RMCM_SHAPER_OFFSET_B, &s->rmcm_regs.rmcm_shaper_offset_b); + + REG_GET(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_inst], MPC_RMCM_SHAPER_SCALE_B, &s->rmcm_regs.rmcm_shaper_scale_b); + + REG_GET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b); + + REG_GET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b); + + REG_GET(MPC_RMCM_CNTL[mpcc_inst], MPC_RMCM_CNTL, &s->rmcm_regs.rmcm_cntl); + } +} + +static const struct mpc_funcs dcn42_mpc_funcs = { + .read_mpcc_state = mpc42_read_mpcc_state, + .insert_plane = mpc1_insert_plane, + .remove_mpcc = mpc1_remove_mpcc, + .mpc_init = mpc32_mpc_init, + .mpc_init_single_inst = mpc3_mpc_init_single_inst, + .update_blending = mpc42_update_blending, + .cursor_lock = mpc1_cursor_lock, + .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, + .wait_for_idle = mpc2_assert_idle_mpcc, + .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, + .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, + .set_denorm = mpc3_set_denorm, + .set_denorm_clamp = mpc3_set_denorm_clamp, + .set_output_csc = mpc3_set_output_csc, + .set_ocsc_default = mpc3_set_ocsc_default, + .set_output_gamma = mpc3_set_output_gamma, + .set_dwb_mux = mpc3_set_dwb_mux, + .disable_dwb_mux = mpc3_disable_dwb_mux, + .is_dwb_idle = mpc3_is_dwb_idle, + .set_gamut_remap = mpc401_set_gamut_remap, + .program_shaper = mpc32_program_shaper, + .program_3dlut = mpc32_program_3dlut, + .program_1dlut = mpc32_program_post1dlut, + .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, + .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .mpc_read_reg_state = mpc3_read_reg_state, + .set_bg_color = mpc1_set_bg_color, + .set_movable_cm_location = mpc401_set_movable_cm_location, + .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select, + .get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status, + .populate_lut = mpc401_populate_lut, + .program_lut_read_write_control = mpc401_program_lut_read_write_control, + .program_lut_mode = mpc401_program_lut_mode, + .mcm = { + .program_lut_read_write_control = mpc42_program_lut_read_write_control, + .program_3dlut_size = mpc42_program_3dlut_size, + .program_bias_scale = mpc42_program_3dlut_fl_bias_scale, + .program_bit_depth = mpc42_program_bit_depth, + .is_config_supported = mpc42_is_config_supported, + .populate_lut = mpc42_populate_lut, + }, + .rmcm = { + .enable_3dlut_fl = mpc42_enable_3dlut_fl, + .update_3dlut_fast_load_select = mpc42_update_3dlut_fast_load_select, + .program_lut_read_write_control = mpc42_program_rmcm_lut_read_write_control, + .program_lut_mode = mpc42_program_lut_mode, + .program_3dlut_size = mpc42_program_rmcm_3dlut_size, + .program_bias_scale = mpc42_program_rmcm_3dlut_fast_load_bias_scale, + .program_bit_depth = mpc42_program_rmcm_bit_depth, + .is_config_supported = mpc42_is_rmcm_config_supported, + .power_on_shaper_3dlut = mpc42_power_on_rmcm_shaper_3dlut, + .populate_lut = mpc42_populate_rmcm_lut, + .fl_3dlut_configure = mpc42_set_fl_config, + }, +}; + +void dcn42_mpc_construct(struct dcn42_mpc *mpc42, + struct dc_context *ctx, + const struct dcn42_mpc_registers *mpc_regs, + const struct dcn42_mpc_shift *mpc_shift, + const struct dcn42_mpc_mask *mpc_mask, + int num_mpcc, + int num_rmu) +{ + int i; + + mpc42->base.ctx = ctx; + + mpc42->base.funcs = &dcn42_mpc_funcs; + + mpc42->mpc_regs = mpc_regs; + mpc42->mpc_shift = mpc_shift; + mpc42->mpc_mask = mpc_mask; + + mpc42->mpcc_in_use_mask = 0; + mpc42->num_mpcc = num_mpcc; + mpc42->num_rmu = num_rmu; + + for (i = 0; i < MAX_MPCC; i++) + mpc42_init_mpcc(&mpc42->base.mpcc_array[i], i); +} diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h new file mode 100644 index 0000000000000..9b87fd2be904c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h @@ -0,0 +1,1006 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DC_MPCC_DCN42_H__ +#define __DC_MPCC_DCN42_H__ + +#include "dcn401/dcn401_mpc.h" + +#define TO_DCN42_MPC(mpc_base) \ + container_of(mpc_base, struct dcn42_mpc, base) + +#define MPC_COMMON_MASK_SH_LIST_DCN42(mask_sh) \ + SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ + SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ + SF(MPCC0_MPCC_CONTROL2, MPCC_GLOBAL_ALPHA, mask_sh),\ + SF(MPCC0_MPCC_CONTROL2, MPCC_GLOBAL_GAIN, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ + SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ + SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ + SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ + SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\ + SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ + SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ + SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL, mask_sh),\ + SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, mask_sh),\ + SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_SIZE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_WRITE_EN_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_30BIT_EN, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_READ_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_INDEX, MPCC_MCM_3DLUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA0, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA1, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM_3DLUT_DATA_30BIT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_LUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM_SHAPER_OFFSET_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM_SHAPER_OFFSET_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM_SHAPER_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM_SHAPER_SCALE_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM_SHAPER_LUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM_SHAPER_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_SELECT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_PWL_DISABLE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_SELECT_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM_1DLUT_LUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM_1DLUT_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_HOST_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_CONFIG_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM_1DLUT_RAMA_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_STATE, mask_sh),\ + SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C24_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C31_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C32_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C33_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C34_A, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C11_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C12_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C13_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C14_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C21_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C22_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C23_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C24_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C31_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C32_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C33_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C34_A, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM_3DLUT_OUT_OFFSET_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM_3DLUT_OUT_SCALE_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM_3DLUT_OUT_OFFSET_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM_3DLUT_OUT_SCALE_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM_3DLUT_OUT_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM_3DLUT_OUT_SCALE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL, MPC_RMCM_SHAPER_LUT_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL, MPC_RMCM_SHAPER_MODE_CURRENT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R, MPC_RMCM_SHAPER_OFFSET_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G, MPC_RMCM_SHAPER_OFFSET_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B, MPC_RMCM_SHAPER_OFFSET_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R, MPC_RMCM_SHAPER_SCALE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM_SHAPER_SCALE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM_SHAPER_SCALE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX, MPC_RMCM_SHAPER_LUT_INDEX, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA, MPC_RMCM_SHAPER_LUT_DATA, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM_SHAPER_LUT_WRITE_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_MODE, MPC_RMCM_3DLUT_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_MODE, MPC_RMCM_3DLUT_SIZE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_MODE, MPC_RMCM_3DLUT_MODE_CURRENT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_INDEX, MPC_RMCM_3DLUT_INDEX, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_DATA, MPC_RMCM_3DLUT_DATA0, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_DATA, MPC_RMCM_3DLUT_DATA1, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT, MPC_RMCM_3DLUT_DATA_30BIT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_WRITE_EN_MASK, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_RAM_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_30BIT_EN, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_READ_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR, MPC_RMCM_3DLUT_OUT_NORM_FACTOR, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM_3DLUT_OUT_OFFSET_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM_3DLUT_OUT_SCALE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM_3DLUT_OUT_OFFSET_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM_3DLUT_OUT_SCALE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM_3DLUT_OUT_OFFSET_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM_3DLUT_OUT_SCALE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM_GAMUT_REMAP_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM_GAMUT_REMAP_C11_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM_GAMUT_REMAP_C12_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM_GAMUT_REMAP_C13_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM_GAMUT_REMAP_C14_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM_GAMUT_REMAP_C21_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM_GAMUT_REMAP_C22_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM_GAMUT_REMAP_C23_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM_GAMUT_REMAP_C24_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM_GAMUT_REMAP_C31_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM_GAMUT_REMAP_C32_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM_GAMUT_REMAP_C33_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM_GAMUT_REMAP_C34_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM_GAMUT_REMAP_C11_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM_GAMUT_REMAP_C12_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM_GAMUT_REMAP_C13_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM_GAMUT_REMAP_C14_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM_GAMUT_REMAP_C21_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM_GAMUT_REMAP_C22_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM_GAMUT_REMAP_C23_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM_GAMUT_REMAP_C24_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM_GAMUT_REMAP_C31_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM_GAMUT_REMAP_C32_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM_GAMUT_REMAP_C33_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM_GAMUT_REMAP_C34_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_PWR_FORCE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_PWR_DIS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_PWR_STATE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT, MPC_RMCM_3DLUT_FL_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM_3DLUT_FL_DONE, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_CNTL, MPC_RMCM_CNTL, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM_TEST_DEBUG_INDEX, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM_TEST_DEBUG_WRITE_EN, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA, MPC_RMCM_TEST_DEBUG_DATA, mask_sh) + +#define MPC_RMCM_REG_LIST_DCN42(inst)\ + SRII(MPC_RMCM_SHAPER_CONTROL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_OFFSET_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_OFFSET_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_OFFSET_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_SCALE_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_LUT_INDEX, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_LUT_DATA, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_MODE, MPC_RMCM, inst), /*TODO: may need to add other 3DLUT regs*/\ + SRII(MPC_RMCM_3DLUT_INDEX, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_DATA, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_DATA_30BIT, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_NORM_FACTOR, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_FAST_LOAD_SELECT, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM, inst),\ + SRII(MPC_RMCM_CNTL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM, inst),\ + SRII(MPC_RMCM_TEST_DEBUG_DATA, MPC_RMCM, inst) + + +#define MPC_REG_LIST_DCN42(inst) \ + MPC_REG_LIST_DCN4_01_RI(inst),\ + SRII(MPCC_CONTROL2, MPCC, inst) + +#define MPC_REG_FIELD_LIST_DCN42(type) \ + MPC_REG_FIELD_LIST_DCN4_01(type); \ + type MPCC_MCM_3DLUT_OUT_OFFSET_R;\ + type MPCC_MCM_3DLUT_OUT_SCALE_R;\ + type MPCC_MCM_3DLUT_OUT_OFFSET_G;\ + type MPCC_MCM_3DLUT_OUT_SCALE_G;\ + type MPCC_MCM_3DLUT_OUT_OFFSET_B;\ + type MPCC_MCM_3DLUT_OUT_SCALE_B;\ + type MPC_RMCM_SHAPER_LUT_MODE;\ + type MPC_RMCM_SHAPER_MODE_CURRENT;\ + type MPC_RMCM_SHAPER_OFFSET_R;\ + type MPC_RMCM_SHAPER_OFFSET_G;\ + type MPC_RMCM_SHAPER_OFFSET_B;\ + type MPC_RMCM_SHAPER_SCALE_R;\ + type MPC_RMCM_SHAPER_SCALE_G;\ + type MPC_RMCM_SHAPER_SCALE_B;\ + type MPC_RMCM_SHAPER_LUT_INDEX;\ + type MPC_RMCM_SHAPER_LUT_DATA;\ + type MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK;\ + type MPC_RMCM_SHAPER_LUT_WRITE_SEL; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS;\ + type MPC_RMCM_3DLUT_MODE;\ + type MPC_RMCM_3DLUT_SIZE;\ + type MPC_RMCM_3DLUT_MODE_CURRENT;\ + type MPC_RMCM_3DLUT_INDEX; \ + type MPC_RMCM_3DLUT_DATA0; \ + type MPC_RMCM_3DLUT_DATA1; \ + type MPC_RMCM_3DLUT_DATA_30BIT; \ + type MPC_RMCM_3DLUT_WRITE_EN_MASK;\ + type MPC_RMCM_3DLUT_RAM_SEL;\ + type MPC_RMCM_3DLUT_30BIT_EN;\ + type MPC_RMCM_3DLUT_READ_SEL;\ + type MPC_RMCM_3DLUT_OUT_NORM_FACTOR;\ + type MPC_RMCM_3DLUT_OUT_OFFSET_R;\ + type MPC_RMCM_3DLUT_OUT_SCALE_R; \ + type MPC_RMCM_3DLUT_OUT_OFFSET_G; \ + type MPC_RMCM_3DLUT_OUT_SCALE_G; \ + type MPC_RMCM_3DLUT_OUT_OFFSET_B; \ + type MPC_RMCM_3DLUT_OUT_SCALE_B;\ + type MPC_RMCM_GAMUT_REMAP_COEF_FORMAT;\ + type MPC_RMCM_GAMUT_REMAP_MODE;\ + type MPC_RMCM_GAMUT_REMAP_MODE_CURRENT;\ + type MPC_RMCM_GAMUT_REMAP_C11_A;\ + type MPC_RMCM_GAMUT_REMAP_C12_A;\ + type MPC_RMCM_GAMUT_REMAP_C13_A; \ + type MPC_RMCM_GAMUT_REMAP_C14_A; \ + type MPC_RMCM_GAMUT_REMAP_C21_A; \ + type MPC_RMCM_GAMUT_REMAP_C22_A; \ + type MPC_RMCM_GAMUT_REMAP_C23_A;\ + type MPC_RMCM_GAMUT_REMAP_C24_A;\ + type MPC_RMCM_GAMUT_REMAP_C31_A;\ + type MPC_RMCM_GAMUT_REMAP_C32_A;\ + type MPC_RMCM_GAMUT_REMAP_C33_A;\ + type MPC_RMCM_GAMUT_REMAP_C34_A;\ + type MPC_RMCM_GAMUT_REMAP_C11_B;\ + type MPC_RMCM_GAMUT_REMAP_C12_B;\ + type MPC_RMCM_GAMUT_REMAP_C13_B; \ + type MPC_RMCM_GAMUT_REMAP_C14_B; \ + type MPC_RMCM_GAMUT_REMAP_C21_B; \ + type MPC_RMCM_GAMUT_REMAP_C22_B; \ + type MPC_RMCM_GAMUT_REMAP_C23_B;\ + type MPC_RMCM_GAMUT_REMAP_C24_B;\ + type MPC_RMCM_GAMUT_REMAP_C31_B;\ + type MPC_RMCM_GAMUT_REMAP_C32_B;\ + type MPC_RMCM_GAMUT_REMAP_C33_B;\ + type MPC_RMCM_GAMUT_REMAP_C34_B;\ + type MPC_RMCM_SHAPER_MEM_PWR_FORCE; \ + type MPC_RMCM_SHAPER_MEM_PWR_DIS; \ + type MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE; \ + type MPC_RMCM_3DLUT_MEM_PWR_FORCE;\ + type MPC_RMCM_3DLUT_MEM_PWR_DIS;\ + type MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE;\ + type MPC_RMCM_SHAPER_MEM_PWR_STATE;\ + type MPC_RMCM_3DLUT_MEM_PWR_STATE;\ + type MPC_RMCM_3DLUT_FL_SEL;\ + type MPC_RMCM_3DLUT_FL_DONE; \ + type MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW; \ + type MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW; \ + type MPC_RMCM_CNTL; \ + type MPC_RMCM_TEST_DEBUG_INDEX;\ + type MPC_RMCM_TEST_DEBUG_WRITE_EN;\ + type MPC_RMCM_TEST_DEBUG_DATA + +#define MPC_REG_VARIABLE_LIST_DCN42 \ + MPC_REG_VARIABLE_LIST_DCN4_01 \ + uint32_t MPCC_CONTROL2[MAX_MPCC];\ + uint32_t MPC_RMCM_SHAPER_CONTROL[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_OFFSET_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_OFFSET_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_OFFSET_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_SCALE_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_SCALE_G_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_LUT_INDEX[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_LUT_DATA[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_MODE[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_INDEX[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_DATA[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_DATA_30BIT[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_MODE[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_MEM_PWR_CTRL[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_FAST_LOAD_STATUS[MAX_MPCC]; \ + uint32_t MPC_RMCM_CNTL[MAX_MPCC]; \ + uint32_t MPC_RMCM_TEST_DEBUG_INDEX[MAX_MPCC]; \ + uint32_t MPC_RMCM_TEST_DEBUG_DATA[MAX_MPCC] + +struct dcn42_mpc_shift { + MPC_REG_FIELD_LIST_DCN42(uint8_t); +}; + +struct dcn42_mpc_mask { + MPC_REG_FIELD_LIST_DCN42(uint32_t); +}; + +struct dcn42_mpc_registers { + MPC_REG_VARIABLE_LIST_DCN42; +}; + +struct dcn42_mpc { + struct mpc base; + + int mpcc_in_use_mask; + int num_mpcc; + const struct dcn42_mpc_registers *mpc_regs; + const struct dcn42_mpc_shift *mpc_shift; + const struct dcn42_mpc_mask *mpc_mask; + int num_rmu; +}; +void dcn42_mpc_construct(struct dcn42_mpc *mpc401, + struct dc_context *ctx, + const struct dcn42_mpc_registers *mpc_regs, + const struct dcn42_mpc_shift *mpc_shift, + const struct dcn42_mpc_mask *mpc_mask, + int num_mpcc, + int num_rmu); + + +void mpc42_program_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_program_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_configure_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id); +void mpc42_power_on_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on); +void mpc42_program_3dlut_size( + struct mpc *mpc, + uint32_t width, + int mpcc_id); +void mpc42_program_3dlut_fl_bias_scale( + struct mpc *mpc, + uint16_t bias, + uint16_t scale, + int mpcc_id); +void mpc42_program_bit_depth( + struct mpc *mpc, + uint16_t bit_depth, + int mpcc_id); +void mpc42_populate_lut( + struct mpc *mpc, + const union mcm_lut_params params, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_lut_read_write_control( + struct mpc *mpc, + const enum MCM_LUT_ID id, + bool lut_bank_a, + bool enabled, + int mpcc_id); + +bool mpc42_is_config_supported(uint32_t width); + +/* RMCM */ +void mpc42_program_rmcm_shaper_lut( + struct mpc *mpc, + const struct pwl_result_data *rgb, + uint32_t num, + uint32_t mpcc_id); +void mpc42_program_rmcm_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_program_rmcm_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_configure_rmcm_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id); +void mpc42_power_on_rmcm_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on); +void mpc42_enable_3dlut_fl( + struct mpc *mpc, + bool enable, + int mpcc_id); +void mpc42_update_3dlut_fast_load_select( + struct mpc *mpc, + int mpcc_id, + int hubp_idx); +void mpc42_populate_rmcm_lut( + struct mpc *mpc, + const union mcm_lut_params params, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_rmcm_lut_read_write_control( + struct mpc *mpc, + const enum MCM_LUT_ID id, + bool lut_bank_a, + bool enabled, + int mpcc_id); +void mpc42_program_lut_mode( + struct mpc *mpc, + const enum MCM_LUT_XABLE xable, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_rmcm_3dlut_size( + struct mpc *mpc, + uint32_t width, + int mpcc_id); +void mpc42_program_rmcm_3dlut_fast_load_bias_scale( + struct mpc *mpc, + uint16_t bias, + uint16_t scale, + int mpcc_id); +void mpc42_program_rmcm_bit_depth( + struct mpc *mpc, + uint16_t bit_depth, + int mpcc_id); + +bool mpc42_is_rmcm_config_supported(uint32_t width); + +void mpc42_set_fl_config( + struct mpc *mpc, + struct mpc_fl_3dlut_config *cfg, + int mpcc_id); + +void mpc42_read_mpcc_state( + struct mpc *mpc, + int mpcc_inst, + struct mpcc_state *s); + +void mpc42_update_blending( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c new file mode 100644 index 0000000000000..effd05b3685f5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn42_optc.h" +#include "dcn30/dcn30_optc.h" +#include "dcn31/dcn31_optc.h" +#include "dcn32/dcn32_optc.h" +#include "dcn401/dcn401_optc.h" +#include "reg_helper.h" +#include "dc.h" +#include "dcn_calc_math.h" +#include "dc_dmub_srv.h" + +#define REG(reg)\ + optc1->tg_regs->reg + +#define CTX \ + optc1->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + optc1->tg_shift->field_name, optc1->tg_mask->field_name + +/* + * optc42_get_crc - Capture CRC result per component + * + * @optc: timing_generator instance. + * @r_cr: 16-bit primary CRC signature for red data. + * @g_y: 16-bit primary CRC signature for green data. + * @b_cb: 16-bit primary CRC signature for blue data. + * + * This function reads the CRC signature from the OPTC registers. Notice that + * we have three registers to keep the CRC result per color component (RGB). + * + * Returns: + * If CRC is disabled, return false; otherwise, return true, and the CRC + * results in the parameters. + */ + +static bool optc42_get_crc(struct timing_generator *optc, uint8_t idx, + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) +{ + uint32_t field = 0; + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + + /* Early return if CRC is not enabled for this CRTC */ + if (!field) + return false; + + + switch (idx) { + case 0: + /* OTG_CRC0_DATA_RG has the CRC16 results for the red component */ + REG_GET(OTG_CRC0_DATA_R, + CRC0_R_CR, r_cr); + + /* OTG_CRC0_DATA_RG has the CRC16 results for the green component */ + REG_GET(OTG_CRC0_DATA_G, + CRC0_G_Y, g_y); + + /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC0_DATA_B, + CRC0_B_CB, b_cb); + break; + case 1: + /* OTG_CRC1_DATA_RG has the CRC16 results for the red component */ + REG_GET(OTG_CRC1_DATA_R, + CRC0_R_CR, r_cr); + + /* OTG_CRC1_DATA_RG has the CRC16 results for the green component */ + REG_GET(OTG_CRC1_DATA_G, + CRC0_G_Y, g_y); + + /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC1_DATA_B, + CRC0_B_CB, b_cb); + break; + default: + return false; + } + return true; +} + +void optc42_enable_pwa(struct timing_generator *optc, struct otc_pwa_frame_sync *pwa_sync_param) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + /*VCOUNT_MODE : + 00 OTG_PWA_FRAME_SYNC_VCOUNT_0 Vcount counting from VSYNC. + 01 OTG_PWA_FRAME_SYNC_VCOUNT_1 Vcount counting from VSTARTUP.*/ + + if (pwa_sync_param == NULL) + return; + if (optc1->base.ctx->dc->debug.enable_otg_frame_sync_pwa) { + /*take mode 1, use line number from vstartup to get output frame as earlier as possible*/ + REG_UPDATE_3(OTG_PWA_FRAME_SYNC_CONTROL, + OTG_PWA_FRAME_SYNC_EN, 1, + OTG_PWA_FRAME_SYNC_VCOUNT_MODE, pwa_sync_param->pwa_sync_mode, + OTG_PWA_FRAME_SYNC_LINE, pwa_sync_param->pwa_frame_sync_line_offset); + } +} +void optc42_disable_pwa(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_UPDATE(OTG_PWA_FRAME_SYNC_CONTROL, + OTG_PWA_FRAME_SYNC_EN, 0); +} + +static struct timing_generator_funcs dcn42_tg_funcs = { + .validate_timing = optc1_validate_timing, + .program_timing = optc1_program_timing, + .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, + .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, + .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, + .program_global_sync = optc401_program_global_sync, + .enable_crtc = optc401_enable_crtc, + .disable_crtc = optc401_disable_crtc, + .phantom_crtc_post_enable = optc401_phantom_crtc_post_enable, + .disable_phantom_crtc = optc401_disable_phantom_otg, + /* used by enable_timing_synchronization. Not need for FPGA */ + .is_counter_moving = optc1_is_counter_moving, + .get_position = optc1_get_position, + .get_frame_count = optc1_get_vblank_counter, + .get_scanoutpos = optc1_get_crtc_scanoutpos, + .get_otg_active_size = optc1_get_otg_active_size, + .set_early_control = optc1_set_early_control, + /* used by enable_timing_synchronization. Not need for FPGA */ + .wait_for_state = optc1_wait_for_state, + .set_blank_color = optc3_program_blank_color, + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, + .triplebuffer_lock = optc3_triplebuffer_lock, + .triplebuffer_unlock = optc2_triplebuffer_unlock, + .enable_reset_trigger = optc1_enable_reset_trigger, + .enable_crtc_reset = optc1_enable_crtc_reset, + .disable_reset_trigger = optc1_disable_reset_trigger, + .lock = optc3_lock, + .unlock = optc1_unlock, + .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, + .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, + .enable_optc_clock = optc1_enable_optc_clock, + .set_drr = optc401_set_drr, + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, + .set_vtotal_min_max = optc401_set_vtotal_min_max, + .set_static_screen_control = optc1_set_static_screen_control, + .program_stereo = optc1_program_stereo, + .is_stereo_left_eye = optc1_is_stereo_left_eye, + .tg_init = optc3_tg_init, + .is_tg_enabled = optc1_is_tg_enabled, + .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, + .clear_optc_underflow = optc1_clear_optc_underflow, + .setup_global_swap_lock = NULL, + .get_crc = optc42_get_crc, + .configure_crc = optc1_configure_crc, + .set_dsc_config = optc3_set_dsc_config, + .get_dsc_status = optc2_get_dsc_status, + .set_dwb_source = NULL, + .set_odm_bypass = optc401_set_odm_bypass, + .set_odm_combine = optc401_set_odm_combine, + .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear, + .set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode, + .get_optc_source = optc2_get_optc_source, + .set_out_mux = optc401_set_out_mux, + .set_drr_trigger_window = optc3_set_drr_trigger_window, + .set_vtotal_change_limit = optc3_set_vtotal_change_limit, + .set_gsl = optc2_set_gsl, + .set_gsl_source_select = optc2_set_gsl_source_select, + .set_vtg_params = optc1_set_vtg_params, + .program_manual_trigger = optc2_program_manual_trigger, + .setup_manual_trigger = optc2_setup_manual_trigger, + .get_hw_timing = optc1_get_hw_timing, + .is_two_pixels_per_container = optc1_is_two_pixels_per_container, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, + .set_vupdate_keepout = optc401_set_vupdate_keepout, + .wait_update_lock_status = optc401_wait_update_lock_status, + .optc_read_reg_state = optc31_read_reg_state, + .enable_otg_pwa = optc42_enable_pwa, + .disable_otg_pwa = optc42_disable_pwa, +}; + +void dcn42_timing_generator_init(struct optc *optc1) +{ + optc1->base.funcs = &dcn42_tg_funcs; + + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; + + optc1->min_h_blank = 32; + optc1->min_v_blank = 3; + optc1->min_v_blank_interlace = 5; + optc1->min_h_sync_width = 4; + optc1->min_v_sync_width = 1; +} + diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h new file mode 100644 index 0000000000000..45d2187efaca0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPTC_DCN42_H__ +#define __DC_OPTC_DCN42_H__ + +#include "dcn10/dcn10_optc.h" + +#define OPTC_COMMON_MASK_SH_LIST_DCN42(mask_sh)\ + SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ + SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ + SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ + SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ + SF(OTG0_OTG_CRC1_DATA_R, CRC1_R_CR, mask_sh),\ + SF(OTG0_OTG_CRC1_DATA_G, CRC1_G_Y, mask_sh),\ + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\ + SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ + SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ + SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ + SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL2, OPTC_SEGMENT_WIDTH_LAST, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ + SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ + SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_EN, mask_sh),\ + SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_VCOUNT_MODE, mask_sh),\ + SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_LINE, mask_sh),\ + SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh) + +void dcn42_timing_generator_init(struct optc *optc1); +void optc42_enable_pwa(struct timing_generator *optc, struct otc_pwa_frame_sync *pwa_sync_param); +void optc42_disable_pwa(struct timing_generator *optc); + +#endif /* __DC_OPTC_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c new file mode 100644 index 0000000000000..3685080ce9dc4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: MIT + +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn42_pg_cntl.h" +#include "dccg.h" + +#define TO_DCN_PG_CNTL(pg_cntl)\ + container_of(pg_cntl, struct dcn_pg_cntl, base) + +#define REG(reg) \ + (pg_cntl_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name + +#define CTX \ + pg_cntl_dcn->base.ctx +#define DC_LOGGER \ + pg_cntl->ctx->logger + +static bool pg_cntl42_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + if (pg_cntl->ctx->dc->debug.ignore_pg) + return true; + + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 1: /* DSC1 */ + REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 2: /* DSC2 */ + REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 3: /* DSC3 */ + REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + return pwr_status == 0; +} + +void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl = 0; + bool block_enabled; + + /*need to enable dscclk regardless DSC_PG*/ + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) + pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( + pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_dsc_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, dsc_inst); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DSC3 */ + REG_UPDATE(DOMAIN19_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN19_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + + if (dsc_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on; + + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { + /*this is to disable dscclk*/ + pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( + pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); + } +} + +static bool pg_cntl42_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + switch (hubp_dpp_inst) { + case 0: + /* DPP0 & HUBP0 */ + REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 1: + /* DPP1 & HUBP1 */ + REG_GET(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 2: + /* DPP2 & HUBP2 */ + REG_GET(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 3: + /* DPP3 & HUBP3 */ + REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + return pwr_status == 0; +} + +void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hubp_power_gate || + pg_cntl->ctx->dc->debug.disable_dpp_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + + switch (hubp_dpp_inst) { + case 0: + /* DPP0 & HUBP0 */ + REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 1: + /* DPP1 & HUBP1 */ + REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 2: + /* DPP2 & HUBP2 */ + REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 3: + /* DPP3 & HUBP3 */ + REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + DC_LOG_DEBUG("HUBP DPP instance %d, power %s", hubp_dpp_inst, + power_on ? "ON" : "OFF"); + + if (hubp_dpp_inst < MAX_PIPES) { + pg_cntl->pg_pipe_res_enable[PG_HUBP][hubp_dpp_inst] = power_on; + pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on; + } +} + +static bool pg_cntl42_hpo_pg_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN25_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + uint32_t power_forceon; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hpo_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_hpo_pg_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); + if (power_forceon) + return; + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + REG_UPDATE(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + pg_cntl->pg_res_enable[PG_HPO] = power_on; +} + +static bool pg_cntl42_io_clk_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN22_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + uint32_t power_forceon; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_io_clk_power_gate) + return; + + block_enabled = pg_cntl42_io_clk_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); + if (power_forceon) + return; + + if (!power_on) { + if (!pg_cntl->pg_res_enable[PG_DCCG] || !pg_cntl->pg_res_enable[PG_DCIO] || !pg_cntl->pg_res_enable[PG_DCOH]) + return; + } + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + /* DCCG, DCOH, DCIO */ + REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + pg_cntl->pg_res_enable[PG_DCCG] = power_on; + pg_cntl->pg_res_enable[PG_DCOH] = power_on; + pg_cntl->pg_res_enable[PG_DCIO] = power_on; +} + +static bool pg_cntl42_plane_otg_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN24_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl, + unsigned int mpcc_inst, bool power_on) +{ + if (pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + if (mpcc_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; +} + +void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl, + unsigned int opp_inst, bool power_on) +{ + if (pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + if (opp_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on; +} + +void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl, + unsigned int optc_inst, bool power_on) +{ + // Defer the ONO domain power up/down to plane_otg_pg_control + if (pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + if (optc_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on; +} +static bool pg_cntl42_mem_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN23_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + uint32_t power_forceon; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_mem_power_gate) + return; + + block_enabled = pg_cntl42_mem_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); + if (power_forceon) + return; + + if (!power_on) { + if (!pg_cntl->pg_res_enable[PG_DCHUBBUB] || !pg_cntl->pg_res_enable[PG_DCHVM]) + return; + } + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + /* DCHUBBUB, DCHUBBUBMEMn, DCHVM */ + REG_UPDATE(DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + pg_cntl->pg_res_enable[PG_DCHUBBUB] = power_on; + pg_cntl->pg_res_enable[PG_DCHVM] = power_on; +} +static bool pg_cntl42_dio_pg_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN26_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_dio_power_gate) + return; + + block_enabled = pg_cntl42_dio_pg_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + /* DIO */ + REG_UPDATE(DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + pg_cntl->pg_res_enable[PG_DIO] = power_on; + +} + +void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + int i; + bool block_enabled; + bool all_mpcc_disabled = true, all_opp_disabled = true; + bool all_optc_disabled = true, all_stream_disabled = true; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_optc_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_plane_otg_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx) { + if (pipe_ctx->stream) + all_stream_disabled = false; + } + + if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i]) + all_mpcc_disabled = false; + + if (pg_cntl->pg_pipe_res_enable[PG_OPP][i]) + all_opp_disabled = false; + + if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i]) + all_optc_disabled = false; + } + + if (!power_on) { + if (!all_mpcc_disabled || !all_opp_disabled || !all_optc_disabled + || !all_stream_disabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + /* MPC, OPP, OPTC, DWB */ + REG_UPDATE(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on; + pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on; + pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on; + } +} + + +void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl) +{ + int i = 0; + bool block_enabled; + + pg_cntl->pg_res_enable[PG_HPO] = pg_cntl42_hpo_pg_status(pg_cntl); + + block_enabled = pg_cntl42_io_clk_status(pg_cntl); + pg_cntl->pg_res_enable[PG_DCCG] = block_enabled; + pg_cntl->pg_res_enable[PG_DCIO] = block_enabled; + pg_cntl->pg_res_enable[PG_DCOH] = block_enabled; + + block_enabled = pg_cntl42_dio_pg_status(pg_cntl); + pg_cntl->pg_res_enable[PG_DIO] = block_enabled; + + block_enabled = pg_cntl42_mem_status(pg_cntl); + pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled; + pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled; + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, i); + pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled; + pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled; + + block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, i); + pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled; + } + + block_enabled = pg_cntl42_plane_otg_status(pg_cntl); + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled; + pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled; + pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled; + } +} + +static const struct pg_cntl_funcs pg_cntl42_funcs = { + .init_pg_status = pg_cntl42_init_pg_status, + .dsc_pg_control = pg_cntl42_dsc_pg_control, + .hubp_dpp_pg_control = pg_cntl42_hubp_dpp_pg_control, + .hpo_pg_control = pg_cntl42_hpo_pg_control, + .io_clk_pg_control = pg_cntl42_io_clk_pg_control, + .plane_otg_pg_control = pg_cntl42_plane_otg_pg_control, + .mpcc_pg_control = pg_cntl42_mpcc_pg_control, + .opp_pg_control = pg_cntl42_opp_pg_control, + .optc_pg_control = pg_cntl42_optc_pg_control, + .mem_pg_control = pg_cntl42_mem_pg_control, + .dio_pg_control = pg_cntl42_dio_pg_control +}; + +struct pg_cntl *pg_cntl42_create( + struct dc_context *ctx, + const struct pg_cntl_registers *regs, + const struct pg_cntl_shift *pg_cntl_shift, + const struct pg_cntl_mask *pg_cntl_mask) +{ + struct dcn_pg_cntl *pg_cntl_dcn = kzalloc(sizeof(*pg_cntl_dcn), GFP_KERNEL); + struct pg_cntl *base; + + if (pg_cntl_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &pg_cntl_dcn->base; + base->ctx = ctx; + base->funcs = &pg_cntl42_funcs; + + pg_cntl_dcn->regs = regs; + pg_cntl_dcn->pg_cntl_shift = pg_cntl_shift; + pg_cntl_dcn->pg_cntl_mask = pg_cntl_mask; + + memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); + memset(base->pg_res_enable, 0, PG_HW_RESOURCES_NUM_ELEMENT * sizeof(bool)); + + return &pg_cntl_dcn->base; +} + +void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(*pg_cntl); + + kfree(pg_cntl_dcn); + *pg_cntl = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h new file mode 100644 index 0000000000000..a0aa14a796f4c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2026 Advanced Micro Devices, Inc.*/ + +#ifndef __DCN42_PG_CNTL_H__ +#define __DCN42_PG_CNTL_H__ + +#include "pg_cntl.h" + +#define PG_CNTL_REG_LIST_DCN42()\ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN19_PG_CONFIG), \ + SR(DOMAIN22_PG_CONFIG), \ + SR(DOMAIN23_PG_CONFIG), \ + SR(DOMAIN24_PG_CONFIG), \ + SR(DOMAIN25_PG_CONFIG), \ + SR(DOMAIN26_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(DOMAIN19_PG_STATUS), \ + SR(DOMAIN22_PG_STATUS), \ + SR(DOMAIN23_PG_STATUS), \ + SR(DOMAIN24_PG_STATUS), \ + SR(DOMAIN25_PG_STATUS), \ + SR(DOMAIN26_PG_STATUS), \ + SR(DC_IP_REQUEST_CNTL) + +#define PG_CNTL_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define PG_CNTL_MASK_SH_LIST_DCN42(mask_sh) \ + PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) + +struct pg_cntl_shift { + uint8_t IP_REQUEST_EN; + uint8_t DOMAIN_POWER_FORCEON; + uint8_t DOMAIN_POWER_GATE; + uint8_t DOMAIN_DESIRED_PWR_STATE; + uint8_t DOMAIN_PGFSM_PWR_STATUS; +}; +struct pg_cntl_mask { + uint32_t IP_REQUEST_EN; + uint32_t DOMAIN_POWER_FORCEON; + uint32_t DOMAIN_POWER_GATE; + uint32_t DOMAIN_DESIRED_PWR_STATE; + uint32_t DOMAIN_PGFSM_PWR_STATUS; +}; + +struct pg_cntl_registers { + uint32_t LONO_STATE; + uint32_t DC_IP_REQUEST_CNTL; + uint32_t DOMAIN0_PG_CONFIG; + uint32_t DOMAIN1_PG_CONFIG; + uint32_t DOMAIN2_PG_CONFIG; + uint32_t DOMAIN3_PG_CONFIG; + uint32_t DOMAIN16_PG_CONFIG; + uint32_t DOMAIN17_PG_CONFIG; + uint32_t DOMAIN18_PG_CONFIG; + uint32_t DOMAIN19_PG_CONFIG; + uint32_t DOMAIN22_PG_CONFIG; + uint32_t DOMAIN23_PG_CONFIG; + uint32_t DOMAIN24_PG_CONFIG; + uint32_t DOMAIN25_PG_CONFIG; + uint32_t DOMAIN26_PG_CONFIG; + uint32_t DOMAIN0_PG_STATUS; + uint32_t DOMAIN1_PG_STATUS; + uint32_t DOMAIN2_PG_STATUS; + uint32_t DOMAIN3_PG_STATUS; + uint32_t DOMAIN16_PG_STATUS; + uint32_t DOMAIN17_PG_STATUS; + uint32_t DOMAIN18_PG_STATUS; + uint32_t DOMAIN19_PG_STATUS; + uint32_t DOMAIN22_PG_STATUS; + uint32_t DOMAIN23_PG_STATUS; + uint32_t DOMAIN24_PG_STATUS; + uint32_t DOMAIN25_PG_STATUS; + uint32_t DOMAIN26_PG_STATUS; +}; + +struct dcn_pg_cntl { + struct pg_cntl base; + const struct pg_cntl_registers *regs; + const struct pg_cntl_shift *pg_cntl_shift; + const struct pg_cntl_mask *pg_cntl_mask; +}; + +void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); +void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, + unsigned int hubp_dpp_inst, bool power_on); +void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl, + unsigned int mpcc_inst, bool power_on); +void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl, + unsigned int opp_inst, bool power_on); +void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl, + unsigned int optc_inst, bool power_on); +void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl); +void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl); + +struct pg_cntl *pg_cntl42_create( + struct dc_context *ctx, + const struct pg_cntl_registers *regs, + const struct pg_cntl_shift *pg_cntl_shift, + const struct pg_cntl_mask *pg_cntl_mask); + +void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl); + +#endif /* DCN42_PG_CNTL */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c new file mode 100644 index 0000000000000..9f2f4d61d3233 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -0,0 +1,2337 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dc.h" + +#include "dcn32/dcn32_init.h" +#include "dcn42/dcn42_init.h" + +#include "resource.h" +#include "include/irq_service_interface.h" + +#include "dcn42_resource.h" +#include "dcn42_resource_fpu.h" +#include "dcn20/dcn20_resource.h" +#include "dcn30/dcn30_resource.h" +#include "dcn31/dcn31_resource.h" +#include "dcn32/dcn32_resource.h" +#include "dcn35/dcn35_resource.h" +#include "dcn321/dcn321_resource.h" +#include "dcn401/dcn401_resource.h" + +#include "dcn10/dcn10_ipp.h" +#include "dcn35/dcn35_hubbub.h" +#include "dcn42/dcn42_hubbub.h" +#include "dcn401/dcn401_mpc.h" +#include "dcn42/dcn42_mpc.h" +#include "dcn35/dcn35_hubp.h" +#include "dcn42/dcn42_hubp.h" +#include "irq/dcn42/irq_service_dcn42.h" +#include "dcn42/dcn42_dpp.h" +#include "dcn401/dcn401_dsc.h" +#include "dcn42/dcn42_optc.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dce110/dce110_hwseq.h" +#include "dcn35/dcn35_opp.h" +#include "dcn30/dcn30_vpg.h" +#include "dcn31/dcn31_vpg.h" +#include "dcn42/dcn42_dio_stream_encoder.h" +#include "dcn42/dcn42_pg_cntl.h" +#include "dcn31/dcn31_hpo_dp_stream_encoder.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32/dcn32_hpo_dp_link_encoder.h" +#include "dcn42/dcn42_hpo_dp_link_encoder.h" +#include "dcn31/dcn31_apg.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "dcn401/dcn401_dio_link_encoder.h" +#include "dcn10/dcn10_link_encoder.h" +#include "dcn321/dcn321_dio_link_encoder.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_audio.h" +#include "dce/dce_hwseq.h" +#include "clk_mgr.h" +#include "virtual/virtual_stream_encoder.h" +#include "dml/display_mode_vba.h" +#include "dcn42/dcn42_dccg.h" +#include "dcn10/dcn10_resource.h" +#include "link_service.h" +#include "dcn31/dcn31_panel_cntl.h" + +#include "dcn30/dcn30_dwb.h" +#include "dcn42/dcn42_mmhubbub.h" +#include "dcn42/dcn42_dio_link_encoder.h" + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" +#include "dpcs/dpcs_4_0_0_offset.h" +#include "dpcs/dpcs_4_0_0_sh_mask.h" + +#include "reg_helper.h" +#include "dce/dmub_abm.h" +#include "dce/dmub_psr.h" +#include "dce/dmub_replay.h" +#include "dce/dce_aux.h" +#include "dce/dce_i2c.h" + +#include "dml/dcn30/display_mode_vba_30.h" +#include "vm_helper.h" +#include "dcn20/dcn20_vmid.h" + +#include "dc_state_priv.h" +#include "link_enc_cfg.h" + +#include "dml2_0/dml2_wrapper.h" + +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 + +#define DC_LOGGER_INIT(logger) + +enum dcn401_clk_src_array_id { + DCN401_CLK_SRC_PLL0, + DCN401_CLK_SRC_PLL1, + DCN401_CLK_SRC_PLL2, + DCN401_CLK_SRC_PLL3, + DCN401_CLK_SRC_PLL4, + DCN401_CLK_SRC_TOTAL +}; + +/* begin + * macros to expend register list macro defined in HW object header file + */ + +/* DCN */ +#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name) \ + REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name +#define SR_ARR(reg_name, id) \ + REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name +#define SR_ARR_INIT(reg_name, id, value) \ + REG_STRUCT[id].reg_name = value + +#define SRI(reg_name, block, id) \ + REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRI_ARR(reg_name, block, id) \ + REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +/* + * Used when a reg_name would otherwise begin with an integer + */ +#define SRI_ARR_US(reg_name, block, id) \ + REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \ + reg##block##id##reg_name +#define SR_ARR_I2C(reg_name, id) \ + REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name + +#define SRI_ARR_I2C(reg_name, block, id) \ + REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + + +#define SRI_ARR_ALPHABET(reg_name, block, index, id) \ + REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRI2(reg_name, block, id) \ + .reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name +#define SRI2_ARR(reg_name, block, id) \ + REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name + +#define SRIR(var_name, reg_name, block, id) \ + .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII(reg_name, block, id) \ + REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII_ARR_2(reg_name, block, id, inst) \ + REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII_MPC_RMU(reg_name, block, id) \ + .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII_DWB(reg_name, temp_name, block, id) \ + REG_STRUCT.reg_name[id] = \ + BASE(reg##block##id##_##temp_name##_BASE_IDX) + \ + reg##block##id##_##temp_name + +#define DCCG_SRII(reg_name, block, id) \ + REG_STRUCT.block##_##reg_name[id] = \ + BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ + .field_name = reg_name##__##field_name##post_fix + +#define VUPDATE_SRII(reg_name, block, id) \ + REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \ + reg##reg_name##_##block##id + +/* NBIO */ +#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] + +#define NBIO_BASE(seg) \ + NBIO_BASE_INNER(seg) + +#define NBIO_SR(reg_name) \ + REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ + regBIF_BX0_##reg_name +#define NBIO_SR_ARR(reg_name, id) \ + REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ + regBIF_BX0_##reg_name + +#define CTX ctx +#define REG(reg_name) \ + (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name) + +static struct bios_registers bios_regs; + +#define bios_regs_init() \ + NBIO_SR(BIOS_SCRATCH_3), \ + NBIO_SR(BIOS_SCRATCH_6) + +#define clk_src_regs_init(index, pllid) \ + CS_COMMON_REG_LIST_DCN42_RI(index, pllid) + +static struct dce110_clk_src_regs clk_src_regs[5]; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) +}; +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) +}; +#define abm_regs_init(id) \ + ABM_DCN42_REG_LIST_RI(id) + +static struct dce_abm_registers abm_regs[4]; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCN42(_MASK)}; + +#define audio_regs_init(id) \ + AUD_COMMON_REG_LIST_RI(id) + +static struct dce_audio_registers audio_regs[5]; + +static const struct dce_audio_shift audio_shift = { + DCN42_AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_audio_mask audio_mask = { + DCN42_AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +#define vpg_regs_init(id) \ + VPG_DCN401_REG_LIST_RI(id) + +static struct dcn31_vpg_registers vpg_regs[10]; + +static const struct dcn31_vpg_shift vpg_shift = { + DCN31_VPG_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_vpg_mask vpg_mask = { + DCN31_VPG_MASK_SH_LIST(_MASK)}; + +#define apg_regs_init(id) \ + APG_DCN31_REG_LIST_RI(id) + +static struct dcn31_apg_registers apg_regs[10]; + +static const struct dcn31_apg_shift apg_shift = { + DCN31_APG_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_apg_mask apg_mask = { + DCN31_APG_MASK_SH_LIST(_MASK)}; + +#define stream_enc_regs_init(id) \ + SE_DCN42_REG_LIST_RI(id) + +static struct dcn10_stream_enc_registers stream_enc_regs[5]; + +static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN42(_MASK)}; + +#define aux_regs_init(id) \ + DCN2_AUX_REG_LIST_RI(id) + +static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; + +#define hpd_regs_init(id) \ + HPD_REG_LIST_RI(id) + +static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; + +#define link_regs_init(id, phyid) \ + LE_DCN401_REG_LIST_RI(id) + +static struct dcn10_link_enc_registers link_enc_regs[5]; + +static const struct dcn10_link_enc_shift le_shift = { + LINK_ENCODER_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN42(_MASK)}; + +#define hpo_dp_stream_encoder_reg_init(id) \ + DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) + +static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; + +static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { + DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)}; + +#define hpo_dp_link_encoder_reg_init(id) \ + DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) + +static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4]; + +static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)}; + +#define dpp_regs_init(id) \ + DPP_REG_LIST_DCN42_COMMON_RI(id) + +static struct dcn42_dpp_registers dpp_regs[4]; + +static const struct dcn42_dpp_shift tf_shift = { + DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)}; + +static const struct dcn42_dpp_mask tf_mask = { + DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)}; + +#define opp_regs_init(id) \ + OPP_REG_LIST_DCN401_RI(id) + +static struct dcn20_opp_registers opp_regs[4]; + +static const struct dcn20_opp_shift opp_shift = { + OPP_MASK_SH_LIST_DCN20(__SHIFT)}; + +static const struct dcn20_opp_mask opp_mask = { + OPP_MASK_SH_LIST_DCN20(_MASK)}; + +#define aux_engine_regs_init(id) \ + AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ + SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ + SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ + SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) + +static struct dce110_aux_registers aux_engine_regs[5]; + +static const struct dce110_aux_registers_shift aux_shift = { + DCN_AUX_MASK_SH_LIST(__SHIFT)}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCN_AUX_MASK_SH_LIST(_MASK)}; + +#define dwbc_regs_dcn401_init(id) \ + DWBC_COMMON_REG_LIST_DCN30_RI(id) + +static struct dcn30_dwbc_registers dwbc401_regs[1]; + +static const struct dcn30_dwbc_shift dwbc401_shift = { + DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)}; + +static const struct dcn30_dwbc_mask dwbc401_mask = { + DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)}; + +#define mcif_wb_regs_dcn3_init(id) \ + MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) + +static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; + +static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)}; + +static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)}; + +#define dsc_regs_init(id) \ + DSC_REG_LIST_DCN401_RI(id) + +static struct dcn401_dsc_registers dsc_regs[4]; + +static const struct dcn401_dsc_shift dsc_shift = { + DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)}; + +static const struct dcn401_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN401(_MASK)}; + +static struct dcn42_mpc_registers mpc_regs; + +#define dcn_mpc_regs_init() \ + MPC_REG_LIST_DCN42(0), \ + MPC_REG_LIST_DCN42(1), \ + MPC_REG_LIST_DCN42(2), \ + MPC_REG_LIST_DCN42(3), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \ + MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \ + MPC_RMCM_REG_LIST_DCN42(0), \ + MPC_RMCM_REG_LIST_DCN42(1) + +static const struct dcn42_mpc_shift mpc_shift = { + MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn42_mpc_mask mpc_mask = { + MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; + +#define optc_regs_init(id) \ + OPTC_COMMON_REG_LIST_DCN42_RI(id) + +static struct dcn_optc_registers optc_regs[4]; + +static const struct dcn_optc_shift optc_shift = { + OPTC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn_optc_mask optc_mask = { + OPTC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; + +#define hubp_regs_init(id) \ + HUBP_REG_LIST_DCN42_RI(id) + +static struct dcn_hubp2_registers hubp_regs[4]; + +static const struct dcn_hubp2_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn_hubp2_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN42(_MASK)}; + +static struct dcn_hubbub_registers hubbub_reg; + +#define hubbub_reg_init() \ + HUBBUB_REG_LIST_DCN42(0) + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN4_2(__SHIFT)}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN4_2(_MASK)}; + +static struct dccg_registers dccg_regs; + +#define dccg_regs_init() \ + DCCG_REG_LIST_DCN42_RI() + +static const struct dccg_shift dccg_shift = { + DCCG_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dccg_mask dccg_mask = { + DCCG_MASK_SH_LIST_DCN42(_MASK)}; + +static struct pg_cntl_registers pg_cntl_regs; + +#define pg_cntl_dcn42_regs_init() \ + PG_CNTL_REG_LIST_DCN42() + +static const struct pg_cntl_shift pg_cntl_shift = { + PG_CNTL_MASK_SH_LIST_DCN42(__SHIFT) +}; + +static const struct pg_cntl_mask pg_cntl_mask = { + PG_CNTL_MASK_SH_LIST_DCN42(_MASK) +}; +#define SRII2(reg_name_pre, reg_name_post, id) \ + .reg_name_pre##_##reg_name_post[id] = \ + BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \ + reg##reg_name_pre##id##_##reg_name_post + +#define HWSEQ_DCN42_REG_LIST() \ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DIO_MEM_PWR_CTRL), \ + SR(ODM_MEM_PWR_CTRL3), \ + SR(MMHUBBUB_MEM_PWR_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCFCLK_CNTL), \ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1), \ + SRII(PIXEL_RATE_CNTL, OTG, 2), \ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(RBBMIF_TIMEOUT_DIS), \ + SR(RBBMIF_TIMEOUT_DIS_2), \ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_VAL_R), \ + SR(DPP_TOP0_DPP_CRC_VAL_G), \ + SR(DPP_TOP0_DPP_CRC_VAL_B), \ + SR(MPC_CRC_CTRL), \ + SR(MPC_CRC_RESULT_R), \ + SR(MPC_CRC_RESULT_G), \ + SR(MPC_CRC_RESULT_B), \ + SR(MPC_CRC_RESULT_A), \ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN19_PG_CONFIG), \ + SR(DOMAIN22_PG_CONFIG), \ + SR(DOMAIN23_PG_CONFIG), \ + SR(DOMAIN24_PG_CONFIG), \ + SR(DOMAIN25_PG_CONFIG), \ + SR(DOMAIN26_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(DOMAIN19_PG_STATUS), \ + SR(DOMAIN22_PG_STATUS), \ + SR(DOMAIN23_PG_STATUS), \ + SR(DOMAIN24_PG_STATUS), \ + SR(DOMAIN25_PG_STATUS), \ + SR(DOMAIN26_PG_STATUS), \ + SR(DC_IP_REQUEST_CNTL), \ + SR(AZALIA_AUDIO_DTO), \ + SR(HPO_TOP_HW_CONTROL), \ + SR(AZALIA_CONTROLLER_CLOCK_GATING) + +static struct dce_hwseq_registers hwseq_reg; + +#define hwseq_reg_init() \ + HWSEQ_DCN42_REG_LIST() + +#define HWSEQ_DCN42_MASK_SH_LIST(mask_sh) \ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ + HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ + HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh) + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCN42_MASK_SH_LIST(__SHIFT)}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCN42_MASK_SH_LIST(_MASK)}; + +#define vmid_regs_init(id) \ + DCN20_VMID_REG_LIST_RI(id) + +static struct dcn_vmid_registers vmid_regs[16]; + +static const struct dcn20_vmid_shift vmid_shifts = { + DCN20_VMID_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK)}; + +static const struct resource_caps res_cap_dcn42 = { + .num_timing_generator = 4, + .num_opp = 4, + .num_dpp = 4, + .num_video_plane = 4, + .num_audio = 5, + .num_stream_encoder = 5, + .num_dig_link_enc = 5, + .num_usb4_dpia = 6, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 4, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, + .num_vmid = 16, + .num_mpc_3dlut = 2, + .num_dsc = 4, +}; + +static const struct dc_plane_cap plane_cap = { + .type = DC_PLANE_TYPE_DCN_UNIVERSAL, + .per_pixel_alpha = true, + + .pixel_format_support = { + .argb8888 = true, + .nv12 = true, + .fp16 = true, + .p010 = true, + .ayuv = false, + }, + + .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000}, + + // 6:1 downscaling ratio: 1000/6 = 166.666 + .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167}, + + .min_width = 64, + .min_height = 64}; + +static const struct dc_debug_options debug_defaults_drv = { + .disable_dmcu = true, + .force_abm_enable = false, + .clock_trace = true, + .disable_pplib_clock_request = false, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_optc_power_gate = true, + .pipe_split_policy = MPC_SPLIT_AVOID, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, + .performance_trace = false, + .max_downscale_src_width = 4096, /*up to 4K for APU*/ + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = false, + .underflow_assert_delay_us = 0xFFFFFFFF, + .dwb_fi_phase = -1, // -1 = disable, + .dmub_command_table = true, + .pstate_enabled = true, + .enable_mem_low_power = { + .bits = { + .vga = false, + .i2c = true, + .dscl = true, + .cm = true, + .mpc = true, + .optc = true, + .vpg = true, + }}, + .root_clock_optimization = { + .bits = { + .dpp = true, + .dsc = true,/*dscclk and dsc pg*/ + .hdmistream = false, + .hdmichar = true, + .dpstream = true, + .symclk32_se = true, + .symclk32_le = true, + .symclk_fe = true, + .physymclk = false, + .dpiasymclk = true, + } + }, + .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, + .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ + .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ + .support_eDP1_5 = true, + .use_max_lb = true, + .force_disable_subvp = false, + .exit_idle_opt_for_cursor_updates = true, + .using_dml2 = true, + .using_dml21 = true, + .enable_single_display_2to1_odm_policy = true, + + // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions + .enable_double_buffered_dsc_pg_support = true, + .enable_dp_dig_pixel_rate_div_policy = 1, + .allow_sw_cursor_fallback = false, + .psp_disabled_wa = true, + .alloc_extra_way_for_cursor = true, + .min_prefetch_in_strobe_ns = 60000, // 60us + .disable_unbounded_requesting = false, + .dcc_meta_propagation_delay_us = 10, + .disable_timeout = true, + .min_disp_clk_khz = 50000, + .disable_z10 = false, + .ignore_pg = true, + .disable_stutter_for_wm_program = true, +}; + +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + +static struct dce_aux *dcn42_aux_engine_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct aux_engine_dce110 *aux_engine = + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); + + if (!aux_engine) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT aux_engine_regs + aux_engine_regs_init(0), + aux_engine_regs_init(1), + aux_engine_regs_init(2), + aux_engine_regs_init(3), + aux_engine_regs_init(4); + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, + &aux_shift, + ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; +} + +#define i2c_inst_regs_init(id) \ + I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) + +static struct dce_i2c_registers i2c_hw_regs[5]; + +static const struct dce_i2c_shift i2c_shifts = { + I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) +}; +static const struct dce_i2c_mask i2c_masks = { + I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) +}; + +/* ========================================================== */ + +/* + * DPIA index | Preferred Encoder | Host Router + * 0 | C | 0 + * 1 | First Available | 0 + * 2 | D | 1 + * 3 | First Available | 1 + * 4 | E | 2 + * 5 | First Available | 2 + */ +/* ========================================================== */ +static const enum engine_id dpia_to_preferred_enc_id_table[] = { + ENGINE_ID_DIGC, + ENGINE_ID_DIGC, + ENGINE_ID_DIGD, + ENGINE_ID_DIGD, + ENGINE_ID_DIGE, + ENGINE_ID_DIGE +}; + +static enum engine_id dcn42_get_preferred_eng_id_dpia(unsigned int dpia_index) +{ + return dpia_to_preferred_enc_id_table[dpia_index]; +} + +static struct dce_i2c_hw *dcn42_i2c_hw_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce_i2c_hw *dce_i2c_hw = + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); + + if (!dce_i2c_hw) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT i2c_hw_regs + i2c_inst_regs_init(1), + i2c_inst_regs_init(2), + i2c_inst_regs_init(3), + i2c_inst_regs_init(4), + i2c_inst_regs_init(5); + dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, + &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); + + return dce_i2c_hw; +} + +static struct clock_source *dcn42_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn401_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + kfree(clk_src); + BREAK_TO_DEBUGGER(); + return NULL; +} + +static struct hubbub *dcn42_hubbub_create(struct dc_context *ctx) +{ + int i; + + struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), + GFP_KERNEL); + + if (!hubbub3) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT hubbub_reg + hubbub_reg_init(); + +#undef REG_STRUCT +#define REG_STRUCT vmid_regs + vmid_regs_init(0), + vmid_regs_init(1), + vmid_regs_init(2), + vmid_regs_init(3), + vmid_regs_init(4), + vmid_regs_init(5), + vmid_regs_init(6), + vmid_regs_init(7), + vmid_regs_init(8), + vmid_regs_init(9), + vmid_regs_init(10), + vmid_regs_init(11), + vmid_regs_init(12), + vmid_regs_init(13), + vmid_regs_init(14), + vmid_regs_init(15); + + hubbub42_construct(hubbub3, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask, + DCN42_DEFAULT_DET_SIZE, + 8, + DCN42_CRB_SIZE_KB); + for (i = 0; i < res_cap_dcn42.num_vmid; i++) { + struct dcn20_vmid *vmid = &hubbub3->vmid[i]; + + vmid->ctx = ctx; + + vmid->regs = &vmid_regs[i]; + vmid->shifts = &vmid_shifts; + vmid->masks = &vmid_masks; + } + + return &hubbub3->base; +} + +static struct hubp *dcn42_hubp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn20_hubp *hubp2 = + kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); + + if (!hubp2) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT hubp_regs + hubp_regs_init(0), + hubp_regs_init(1), + hubp_regs_init(2), + hubp_regs_init(3); + + if (hubp42_construct(hubp2, ctx, inst, + &hubp_regs[inst], &hubp_shift, &hubp_mask)) + return &hubp2->base; + + BREAK_TO_DEBUGGER(); + kfree(hubp2); + return NULL; +} +static const struct dc_panel_config dcn42_panel_config_defaults = { + .psr = { + .disable_psr = false, + .disallow_psrsu = false, + .disallow_replay = false, + }, + .ilr = { + .optimize_edp_link_rate = true, + }, +}; + +static void dcn42_dpp_destroy(struct dpp **dpp) +{ + kfree(TO_DCN42_DPP(*dpp)); + *dpp = NULL; +} + +static struct dpp *dcn42_dpp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn42_dpp *dpp42 = + kzalloc(sizeof(struct dcn42_dpp), GFP_KERNEL); + + if (!dpp42) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT dpp_regs + dpp_regs_init(0), + dpp_regs_init(1), + dpp_regs_init(2), + dpp_regs_init(3); + + if (dpp42_construct(dpp42, ctx, inst, + &dpp_regs[inst], &tf_shift, &tf_mask)) + return &dpp42->base; + + BREAK_TO_DEBUGGER(); + kfree(dpp42); + return NULL; +} + +static struct mpc *dcn42_mpc_create( + struct dc_context *ctx, + int num_mpcc, + int num_rmu) +{ + struct dcn42_mpc *mpc401 = kzalloc(sizeof(struct dcn42_mpc), + GFP_KERNEL); + + if (!mpc401) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT mpc_regs + dcn_mpc_regs_init(); + + dcn42_mpc_construct(mpc401, ctx, + &mpc_regs, + &mpc_shift, + &mpc_mask, + num_mpcc, + num_rmu); + + return &mpc401->base; +} + +static struct output_pixel_processor *dcn42_opp_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_opp *opp4 = + kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); + + if (!opp4) { + BREAK_TO_DEBUGGER(); + return NULL; + } + +#undef REG_STRUCT +#define REG_STRUCT opp_regs + opp_regs_init(0), + opp_regs_init(1), + opp_regs_init(2), + opp_regs_init(3); + dcn20_opp_construct(opp4, ctx, inst, + &opp_regs[inst], &opp_shift, &opp_mask); + return &opp4->base; +} + +static struct timing_generator *dcn42_timing_generator_create( + struct dc_context *ctx, + uint32_t instance) +{ + struct optc *tgn10 = + kzalloc(sizeof(struct optc), GFP_KERNEL); + + if (!tgn10) + return NULL; +#undef REG_STRUCT +#define REG_STRUCT optc_regs + optc_regs_init(0), + optc_regs_init(1), + optc_regs_init(2), + optc_regs_init(3); + tgn10->base.inst = instance; + tgn10->base.ctx = ctx; + + tgn10->tg_regs = &optc_regs[instance]; + tgn10->tg_shift = &optc_shift; + tgn10->tg_mask = &optc_mask; + + dcn42_timing_generator_init(tgn10); + + return &tgn10->base; +} + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .hdmi_ycbcr420_supported = true, + .dp_ycbcr420_supported = true, + .fec_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true}; + +static struct link_encoder *dcn42_link_encoder_create( + struct dc_context *ctx, + const struct encoder_init_data *enc_init_data) +{ + struct dcn20_link_encoder *enc20 = + kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + + if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT link_enc_aux_regs + aux_regs_init(0), + aux_regs_init(1), + aux_regs_init(2), + aux_regs_init(3), + aux_regs_init(4); +#undef REG_STRUCT +#define REG_STRUCT link_enc_hpd_regs + hpd_regs_init(0), + hpd_regs_init(1), + hpd_regs_init(2), + hpd_regs_init(3), + hpd_regs_init(4); +#undef REG_STRUCT +#define REG_STRUCT link_enc_regs + link_regs_init(0, A), + link_regs_init(1, B), + link_regs_init(2, C), + link_regs_init(3, D), + link_regs_init(4, E); + + dcn42_link_encoder_construct(enc20, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source], + &le_shift, + &le_mask); + return &enc20->enc10.base; +} + +static void read_dce_straps( + struct dc_context *ctx, + struct resource_straps *straps) +{ + generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), + FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); +} + +static struct audio *dcn42_create_audio( + struct dc_context *ctx, unsigned int inst) +{ + +#undef REG_STRUCT +#define REG_STRUCT audio_regs + audio_regs_init(0), + audio_regs_init(1), + audio_regs_init(2), + audio_regs_init(3), + audio_regs_init(4); + + return dce_audio_create(ctx, inst, + &audio_regs[inst], &audio_shift, &audio_mask); +} + +static struct vpg *dcn42_vpg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); + + if (!vpg4) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT vpg_regs + vpg_regs_init(0), + vpg_regs_init(1), + vpg_regs_init(2), + vpg_regs_init(3), + vpg_regs_init(4), + vpg_regs_init(5), + vpg_regs_init(6), + vpg_regs_init(7), + vpg_regs_init(8), + vpg_regs_init(9); + vpg31_construct(vpg4, ctx, inst, + &vpg_regs[inst], + &vpg_shift, + &vpg_mask); + + return &vpg4->base; +} + +static struct apg *dcn42_apg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); + + if (!apg31) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT apg_regs + apg_regs_init(0), + apg_regs_init(1), + apg_regs_init(2), + apg_regs_init(3), + apg_regs_init(4), + apg_regs_init(5), + apg_regs_init(6), + apg_regs_init(7), + apg_regs_init(8), + apg_regs_init(9); + + apg31_construct(apg31, ctx, inst, + &apg_regs[inst], + &apg_shift, + &apg_mask); + + return &apg31->base; +} + +static struct stream_encoder *dcn42_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn10_stream_encoder *enc1; + struct vpg *vpg; + struct apg *apg; + + uint32_t vpg_inst; + uint32_t apg_inst; + + /* Mapping of VPG, DME register blocks to DIO block instance */ + if (eng_id <= ENGINE_ID_DIGE) { + vpg_inst = eng_id; + apg_inst = eng_id; + } else + return NULL; + + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); + vpg = dcn42_vpg_create(ctx, vpg_inst); + apg = dcn42_apg_create(ctx, apg_inst); + + if (!enc1 || !vpg || !apg) { + kfree(enc1); + kfree(vpg); + kfree(apg); + return NULL; + } +#undef REG_STRUCT +#define REG_STRUCT stream_enc_regs + stream_enc_regs_init(0), + stream_enc_regs_init(1), + stream_enc_regs_init(2), + stream_enc_regs_init(3), + stream_enc_regs_init(4); + + dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, + eng_id, vpg, apg, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc1->base; +} + +static struct hpo_dp_stream_encoder *dcn42_hpo_dp_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; + struct vpg *vpg; + struct apg *apg; + uint32_t hpo_dp_inst; + uint32_t vpg_inst; + uint32_t apg_inst; + + ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); + hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; + + /* Mapping of VPG register blocks to HPO DP block instance: + * VPG[5] -> HPO_DP[0] + * VPG[6] -> HPO_DP[1] + * VPG[7] -> HPO_DP[2] + * VPG[8] -> HPO_DP[3] + */ + vpg_inst = hpo_dp_inst + 5; + + /* Mapping of APG register blocks to HPO DP block instance: + * APG[6] -> HPO_DP[0] + * APG[7] -> HPO_DP[1] + * APG[8] -> HPO_DP[2] + * APG[9] -> HPO_DP[3] + */ + apg_inst = hpo_dp_inst + 5; + + /* allocate HPO stream encoder and create VPG sub-block */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); + vpg = dcn42_vpg_create(ctx, vpg_inst); + apg = dcn42_apg_create(ctx, apg_inst); + + if (!hpo_dp_enc31 || !vpg || !apg) { + kfree(hpo_dp_enc31); + kfree(vpg); + kfree(apg); + return NULL; + } + +#undef REG_STRUCT +#define REG_STRUCT hpo_dp_stream_enc_regs + hpo_dp_stream_encoder_reg_init(0), + hpo_dp_stream_encoder_reg_init(1), + hpo_dp_stream_encoder_reg_init(2), + hpo_dp_stream_encoder_reg_init(3); + + dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, + hpo_dp_inst, eng_id, vpg, apg, + &hpo_dp_stream_enc_regs[hpo_dp_inst], + &hpo_dp_se_shift, &hpo_dp_se_mask); + + return &hpo_dp_enc31->base; +} + +static struct hpo_dp_link_encoder *dcn42_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; + + /* allocate HPO link encoder */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); + if (!hpo_dp_enc31) + return NULL; /* out of memory */ + +#undef REG_STRUCT +#define REG_STRUCT hpo_dp_link_enc_regs + hpo_dp_link_encoder_reg_init(0), + hpo_dp_link_encoder_reg_init(1), + hpo_dp_link_encoder_reg_init(2), + hpo_dp_link_encoder_reg_init(3); + + hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst, + &hpo_dp_link_enc_regs[inst], + &hpo_dp_le_shift, &hpo_dp_le_mask); + + return &hpo_dp_enc31->base; +} + +static struct dce_hwseq *dcn42_hwseq_create( + struct dc_context *ctx) +{ + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); + +#undef REG_STRUCT +#define REG_STRUCT hwseq_reg + hwseq_reg_init(); + + if (hws) { + hws->ctx = ctx; + hws->regs = &hwseq_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + } + + return hws; +} + +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = dcn42_create_audio, + .create_stream_encoder = dcn42_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn42_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn42_hpo_dp_link_encoder_create, + .create_hwseq = dcn42_hwseq_create, +}; + +static void dcn42_dsc_destroy(struct display_stream_compressor **dsc) +{ + kfree(container_of(*dsc, struct dcn401_dsc, base)); + *dsc = NULL; +} + +static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->base.stream_enc_count; i++) { + if (pool->base.stream_enc[i] != NULL) { + if (pool->base.stream_enc[i]->vpg != NULL) { + kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); + pool->base.stream_enc[i]->vpg = NULL; + } + if (pool->base.stream_enc[i]->apg != NULL) { + kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); + pool->base.stream_enc[i]->apg = NULL; + } + kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); + pool->base.stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { + if (pool->base.hpo_dp_stream_enc[i] != NULL) { + if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { + kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); + pool->base.hpo_dp_stream_enc[i]->vpg = NULL; + } + if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { + kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); + pool->base.hpo_dp_stream_enc[i]->apg = NULL; + } + kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); + pool->base.hpo_dp_stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { + if (pool->base.hpo_dp_link_enc[i] != NULL) { + kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); + pool->base.hpo_dp_link_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn42_dsc_destroy(&pool->base.dscs[i]); + } + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); + pool->base.mpc = NULL; + } + if (pool->base.hubbub != NULL) { + kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { + if (pool->base.dpps[i] != NULL) + dcn42_dpp_destroy(&pool->base.dpps[i]); + + if (pool->base.ipps[i] != NULL) + pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); + + if (pool->base.hubps[i] != NULL) { + kfree(TO_DCN20_HUBP(pool->base.hubps[i])); + pool->base.hubps[i] = NULL; + } + + if (pool->base.irqs != NULL) + dal_irq_service_destroy(&pool->base.irqs); + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + if (pool->base.engines[i] != NULL) + dce110_engine_destroy(&pool->base.engines[i]); + if (pool->base.hw_i2cs[i] != NULL) { + kfree(pool->base.hw_i2cs[i]); + pool->base.hw_i2cs[i] = NULL; + } + if (pool->base.sw_i2cs[i] != NULL) { + kfree(pool->base.sw_i2cs[i]); + pool->base.sw_i2cs[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_opp; i++) { + if (pool->base.opps[i] != NULL) + pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.timing_generators[i] != NULL) { + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + pool->base.timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + if (pool->base.dwbc[i] != NULL) { + kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); + pool->base.dwbc[i] = NULL; + } + if (pool->base.mcif_wb[i] != NULL) { + kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); + pool->base.mcif_wb[i] = NULL; + } + } + + for (i = 0; i < pool->base.audio_count; i++) { + if (pool->base.audios[i]) + dce_aud_destroy(&pool->base.audios[i]); + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] != NULL) { + dcn20_clock_source_destroy(&pool->base.clock_sources[i]); + pool->base.clock_sources[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + if (pool->base.mpc_lut[i] != NULL) { + dc_3dlut_func_release(pool->base.mpc_lut[i]); + pool->base.mpc_lut[i] = NULL; + } + if (pool->base.mpc_shaper[i] != NULL) { + dc_transfer_func_release(pool->base.mpc_shaper[i]); + pool->base.mpc_shaper[i] = NULL; + } + } + + if (pool->base.dp_clock_source != NULL) { + dcn20_clock_source_destroy(&pool->base.dp_clock_source); + pool->base.dp_clock_source = NULL; + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.multiple_abms[i] != NULL) + dce_abm_destroy(&pool->base.multiple_abms[i]); + } + + if (pool->base.psr != NULL) + dmub_psr_destroy(&pool->base.psr); + + if (pool->base.pg_cntl != NULL) + dcn_pg_cntl_destroy(&pool->base.pg_cntl); + if (pool->base.dccg != NULL) + dcn_dccg_destroy(&pool->base.dccg); + + if (pool->base.oem_device != NULL) { + struct dc *dc = pool->base.oem_device->ctx->dc; + + dc->link_srv->destroy_ddc_service(&pool->base.oem_device); + } +} + +static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) +{ + const struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; + struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; + struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; + + pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; + + if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) + pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; + + if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) + link_enc = link_enc_cfg_get_link_enc(link); + if (link_enc) + pixel_clk_params->encoder_object_id = link_enc->id; + + pixel_clk_params->signal_type = pipe_ctx->stream->signal; + pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; + /* TODO: un-hardcode*/ + + /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ + + pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * + LINK_RATE_REF_FREQ_IN_KHZ; + pixel_clk_params->flags.ENABLE_SS = 0; + pixel_clk_params->color_depth = + stream->timing.display_color_depth; + pixel_clk_params->flags.DISPLAY_BLANKED = 1; + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; + + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + pixel_clk_params->color_depth = COLOR_DEPTH_888; + + if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) + pixel_clk_params->requested_pix_clk_100hz *= 2; + if (dc_is_tmds_signal(stream->signal) && + stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + pixel_clk_params->requested_pix_clk_100hz /= 2; + + pipe_ctx->clock_source->funcs->get_pix_clk_dividers( + pipe_ctx->clock_source, + &pipe_ctx->stream_res.pix_clk_params, + &pipe_ctx->pll_settings); + + pixel_clk_params->dio_se_pix_per_cycle = 1; + if (dc_is_tmds_signal(stream->signal) && + stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + pixel_clk_params->dio_se_pix_per_cycle = 2; + } else if (dc_is_dp_signal(stream->signal)) { + /* round up to nearest power of 2, or max at 8 pixels per cycle */ + if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + pixel_clk_params->dio_se_pix_per_cycle = 8; + } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + pixel_clk_params->dio_se_pix_per_cycle = 4; + } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + pixel_clk_params->dio_se_pix_per_cycle = 2; + } else { + pixel_clk_params->dio_se_pix_per_cycle = 1; + } + } +} + +static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t dwb_count = pool->res_cap->num_dwb; + + for (i = 0; i < dwb_count; i++) { + struct dcn30_dwbc *dwbc42 = kzalloc(sizeof(struct dcn30_dwbc), + GFP_KERNEL); + + if (!dwbc42) { + dm_error("DC: failed to create dwbc42!\n"); + return false; + } + +#undef REG_STRUCT +#define REG_STRUCT dwbc401_regs + dwbc_regs_dcn401_init(0); + + dcn30_dwbc_construct(dwbc42, ctx, + &dwbc401_regs[i], + &dwbc401_shift, + &dwbc401_mask, + i); + + pool->dwbc[i] = &dwbc42->base; + } + return true; +} + +static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, + struct dc_context *ctx) +{ + dcn42_mmhubbub_set_fgcg( + mcif_wb30, + ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); +} + +static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t pipe_count = pool->res_cap->num_dwb; + + for (i = 0; i < pipe_count; i++) { + struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), + GFP_KERNEL); + + if (!mcif_wb30) { + dm_error("DC: failed to create mcif_wb30!\n"); + return false; + } + +#undef REG_STRUCT +#define REG_STRUCT mcif_wb35_regs + mcif_wb_regs_dcn3_init(0); + + dcn35_mmhubbub_construct(mcif_wb30, ctx, + &mcif_wb35_regs[i], + &mcif_wb35_shift, + &mcif_wb35_mask, + i); + + dcn42_mmhubbub_init(mcif_wb30, ctx); + + pool->mcif_wb[i] = &mcif_wb30->base; + } + return true; +} + +static struct display_stream_compressor *dcn42_dsc_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn401_dsc *dsc = + kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL); + + if (!dsc) { + BREAK_TO_DEBUGGER(); + return NULL; + } + +#undef REG_STRUCT +#define REG_STRUCT dsc_regs + dsc_regs_init(0), + dsc_regs_init(1), + dsc_regs_init(2), + dsc_regs_init(3); + + dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); + + dsc->max_image_width = 5760; + + return &dsc->base; +} + +static void dcn42_destroy_resource_pool(struct resource_pool **pool) +{ + struct dcn42_resource_pool *dcn42_pool = TO_DCN42_RES_POOL(*pool); + + dcn42_resource_destruct(dcn42_pool); + kfree(dcn42_pool); + *pool = NULL; +} + +static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; + +static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + DC_FP_START(); + if (dc->current_state && dc->current_state->bw_ctx.dml2) + dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); + DC_FP_END(); +} + +enum dc_status dcn42_validate_bandwidth(struct dc *dc, + struct dc_state *context, + enum dc_validate_mode validate_mode) +{ + bool out = false; + + out = dml2_validate(dc, context, context->bw_ctx.dml2, + validate_mode); + DC_FP_START(); + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { + /*not required for mode enumeration*/ + dcn42_decide_zstate_support(dc, context); + } + DC_FP_END(); + return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; +} +void dcn42_prepare_mcache_programming(struct dc *dc, + struct dc_state *context) +{ + if (dc->debug.using_dml21) + dml2_prepare_mcache_programming(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? + context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); +} +/* Create a minimal link encoder object not associated with a particular + * physical connector. + * resource_funcs.link_enc_create_minimal + */ +static struct link_encoder *dcn42_link_enc_create_minimal( + struct dc_context *ctx, enum engine_id eng_id) +{ + struct dcn20_link_encoder *enc20; + + if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + return NULL; + + enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + if (!enc20) + return NULL; + + dcn31_link_encoder_construct_minimal( + enc20, + ctx, + &link_enc_feature, + &link_enc_regs[eng_id - ENGINE_ID_DIGA], + eng_id); + + return &enc20->enc10.base; +} +static void dcn42_get_panel_config_defaults(struct dc_panel_config *panel_config) +{ + *panel_config = dcn42_panel_config_defaults; +} +static unsigned int dcn42_get_max_hw_cursor_size(const struct dc *dc, + struct dc_state *state, + const struct dc_stream_state *stream) +{ + return dc->caps.max_cursor_size; +} +static struct resource_funcs dcn42_res_pool_funcs = { + .destroy = dcn42_destroy_resource_pool, + .link_enc_create = dcn42_link_encoder_create, + .link_enc_create_minimal = dcn42_link_enc_create_minimal, + .link_encs_assign = link_enc_cfg_link_encs_assign, + .link_enc_unassign = link_enc_cfg_link_enc_unassign, + .panel_cntl_create = dcn32_panel_cntl_create, + .validate_bandwidth = dcn42_validate_bandwidth, + .calculate_wm_and_dlg = NULL, + .populate_dml_pipes = NULL, + .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, + .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, + .release_pipe = dcn20_release_pipe, + .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, + .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, + .set_mcif_arb_params = dcn30_set_mcif_arb_params, + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, + .update_bw_bounding_box = dcn42_update_bw_bounding_box, + .patch_unknown_plane_state = dcn401_patch_unknown_plane_state, + .get_panel_config_defaults = dcn42_get_panel_config_defaults, + .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, + .add_phantom_pipes = dcn32_add_phantom_pipes, + .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, + .prepare_mcache_programming = dcn42_prepare_mcache_programming, + .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, + .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, + .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, +}; + +static uint32_t read_pipe_fuses(struct dc_context *ctx) +{ + uint32_t value = REG_READ(CC_DC_PIPE_DIS); + + if (value == 0 && ctx->dce_environment == DCE_ENV_DIAG) + value = 0xF; + /* DCN401 support max 4 pipes */ + value = value & 0xf; + return value; +} + +static bool dcn42_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, + struct dcn42_resource_pool *pool) +{ + int i, j; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; + uint32_t pipe_fuses = 0; + uint32_t num_pipes = 4; + +#undef REG_STRUCT +#define REG_STRUCT bios_regs + bios_regs_init(); + +#undef REG_STRUCT +#define REG_STRUCT clk_src_regs + clk_src_regs_init(0, A), + clk_src_regs_init(1, B), + clk_src_regs_init(2, C), + clk_src_regs_init(3, D), + clk_src_regs_init(4, E); + +#undef REG_STRUCT +#define REG_STRUCT abm_regs + abm_regs_init(0), + abm_regs_init(1), + abm_regs_init(2), + abm_regs_init(3); +#undef REG_STRUCT +#define REG_STRUCT dccg_regs + dccg_regs_init(); + + ctx->dc_bios->regs = &bios_regs; + + pool->base.res_cap = &res_cap_dcn42; + + /* max number of pipes for ASIC before checking for pipe fuses */ + num_pipes = pool->base.res_cap->num_dpp; + pipe_fuses = read_pipe_fuses(ctx); + + for (i = 0; i < pool->base.res_cap->num_dpp; i++) + if (pipe_fuses & 1 << i) + num_pipes--; + + if (pipe_fuses & 1) + ASSERT(0); // Unexpected - Pipe 0 should always be fully functional! + + if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) + ASSERT(0); // Entire DCN is harvested! + + pool->base.funcs = &dcn42_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; + pool->base.pipe_count = num_pipes; + pool->base.mpcc_count = num_pipes; + dc->caps.ips_v2_support = true; + dc->caps.max_downscale_ratio = 600; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ + /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ + dc->caps.max_cursor_size = 64; + dc->caps.max_buffered_cursor_size = 64; + dc->caps.cursor_not_scaled = true; + dc->caps.min_horizontal_blanking_period = 80; + dc->caps.dmdata_alloc_size = 2048; + dc->caps.mall_size_per_mem_channel = 4; + /* total size = mall per channel * num channels * 1024 * 1024 */ + dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * + dc->ctx->dc_bios->vram_info.num_chans * 1048576; + dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; + dc->caps.cache_line_size = 64; + dc->caps.cache_num_ways = 16; + + /* Calculate the available MALL space */ + dc->caps.max_cab_allocation_bytes = + dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * + dc->caps.mall_size_per_mem_channel * 1024 * 1024; + dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; + + dc->caps.subvp_fw_processing_delay_us = 15; + dc->caps.subvp_drr_max_vblank_margin_us = 40; + dc->caps.subvp_prefetch_end_to_mall_start_us = 15; + dc->caps.subvp_swath_height_margin_lines = 16; + dc->caps.subvp_pstate_allow_width_us = 20; + dc->caps.subvp_vertical_int_margin_us = 30; + dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin + + dc->caps.max_slave_planes = 2; + dc->caps.max_slave_yuv_planes = 2; + dc->caps.max_slave_rgb_planes = 2; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + if (dc->config.forceHBR2CP2520) + dc->caps.force_dp_tps4_for_cp2520 = false; + dc->caps.dp_hdmi21_pcon_support = true; + dc->caps.dp_hpo = true; + dc->caps.edp_dsc_support = true; + dc->caps.extended_aux_timeout_support = true; + dc->caps.dmcub_support = true; + dc->caps.is_apu = true; + dc->caps.seamless_odm = true; + dc->caps.zstate_support = true; + dc->caps.ips_support = true; + dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; + + dc->caps.seamless_odm = true; + dc->caps.zstate_support = true; + dc->caps.ips_support = true; + dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; + + /* Color pipeline capabilities */ + dc->caps.color.dpp.dcn_arch = 1; + dc->caps.color.dpp.input_lut_shared = 0; + dc->caps.color.dpp.icsc = 1; + dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr + dc->caps.color.dpp.dgam_rom_caps.srgb = 1; + dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; + dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; + dc->caps.color.dpp.dgam_rom_caps.pq = 1; + dc->caps.color.dpp.dgam_rom_caps.hlg = 1; + dc->caps.color.dpp.post_csc = 1; + dc->caps.color.dpp.gamma_corr = 1; + dc->caps.color.dpp.dgam_rom_for_yuv = 0; + + dc->caps.color.dpp.hw_3d_lut = 0; + dc->caps.color.dpp.ogam_ram = 0; + // no OGAM ROM on DCN2 and later ASICs + dc->caps.color.dpp.ogam_rom_caps.srgb = 0; + dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; + dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.dpp.ogam_rom_caps.pq = 0; + dc->caps.color.dpp.ogam_rom_caps.hlg = 0; + dc->caps.color.dpp.ocsc = 0; + + dc->caps.color.mpc.gamut_remap = 1; + //configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; + dc->caps.color.mpc.num_rmcm_3dluts = 2; + dc->caps.color.mpc.ogam_ram = 1; + dc->caps.color.mpc.ogam_rom_caps.srgb = 0; + dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; + dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.mpc.ogam_rom_caps.pq = 0; + dc->caps.color.mpc.ogam_rom_caps.hlg = 0; + dc->caps.color.mpc.ocsc = 1; + dc->caps.color.mpc.preblend = true; + dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; + + dc->caps.num_of_host_routers = 3; + dc->caps.num_of_dpias_per_host_router = 2; + + /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order + * to provide some margin. + * It's expected for furture ASIC to have equal or higher value, in order to + * have determinstic power improvement from generate to genration. + * (i.e., we should not expect new ASIC generation with lower vmin rate) + */ + dc->caps.max_disp_clock_khz_at_vmin = 650000; + dc->config.use_spl = true; + dc->config.prefer_easf = true; + + dc->config.dcn_sharpness_range.sdr_rgb_min = 0; + dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; + dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; + dc->config.dcn_sharpness_range.sdr_yuv_min = 0; + dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; + dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; + dc->config.dcn_sharpness_range.hdr_rgb_min = 0; + dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; + dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; + + dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; + dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; + dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; + dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; + dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; + dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; + dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; + dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; + dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; + + dc->config.use_pipe_ctx_sync_logic = true; + dc->config.dc_mode_clk_limit_support = true; + dc->config.enable_windowed_mpo_odm = true; + /* Use psp mailbox to enable assr */ + dc->config.use_assr_psp_message = true; + /* dcn42 and afterward always support external panel replay */ + dc->config.frame_update_cmd_version2 = true; + + /* read VBIOS LTTPR caps */ + { + if (ctx->dc_bios->funcs->get_lttpr_caps) { + enum bp_result bp_query_result; + uint8_t is_vbios_lttpr_enable = 0; + + bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); + dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; + } + + dc->caps.vbios_lttpr_aware = true; + } + dc->check_config = config_defaults; + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; + + /*HW default is to have all the FGCG enabled, SW no need to program them*/ + dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; + // Init the vm_helper + if (dc->vm_helper) + vm_helper_init(dc->vm_helper, 16); + + /************************************************* + * Create resources * + *************************************************/ + + /* Clock Sources for Pixel Clock*/ + pool->base.clock_sources[DCN401_CLK_SRC_PLL0] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL0, + &clk_src_regs[0], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL1] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL1, + &clk_src_regs[1], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL2] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL2, + &clk_src_regs[2], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL3] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL3, + &clk_src_regs[3], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL4] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL4, + &clk_src_regs[4], false); + + pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL; + + /* todo: not reuse phy_pll registers */ + pool->base.dp_clock_source = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_ID_DP_DTO, + &clk_src_regs[0], true); + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* DCCG */ + pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); + if (pool->base.dccg == NULL) { + dm_error("DC: failed to create dccg!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + +#undef REG_STRUCT +#define REG_STRUCT pg_cntl_regs + pg_cntl_dcn42_regs_init(); + + pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); + if (pool->base.pg_cntl == NULL) { + dm_error("DC: failed to create power gate control!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + /* IRQ Service */ + init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dcn42_create(&init_data); + if (!pool->base.irqs) + goto create_fail; + + /* HUBBUB */ + pool->base.hubbub = dcn42_hubbub_create(ctx); + if (pool->base.hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto create_fail; + } + + /* HUBPs, DPPs, OPPs, TGs, ABMs */ + for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { + /* if pipe is disabled, skip instance of HW pipe, + * i.e, skip ASIC register instance + */ + if (pipe_fuses & 1 << i) + continue; + + pool->base.hubps[j] = dcn42_hubp_create(ctx, i); + if (pool->base.hubps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create hubps!\n"); + goto create_fail; + } + + pool->base.dpps[j] = dcn42_dpp_create(ctx, i); + if (pool->base.dpps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create dpps!\n"); + goto create_fail; + } + + pool->base.opps[j] = dcn42_opp_create(ctx, i); + if (pool->base.opps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create output pixel processor!\n"); + goto create_fail; + } + + pool->base.timing_generators[j] = dcn42_timing_generator_create( + ctx, i); + if (pool->base.timing_generators[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto create_fail; + } + + pool->base.multiple_abms[j] = dmub_abm_create(ctx, + &abm_regs[i], + &abm_shift, + &abm_mask); + if (pool->base.multiple_abms[j] == NULL) { + dm_error("DC: failed to create abm for pipe %d!\n", i); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* index for resource pool arrays for next valid pipe */ + j++; + } + + /* PSR */ + pool->base.psr = dmub_psr_create(ctx); + if (pool->base.psr == NULL) { + dm_error("DC: failed to create psr obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* Replay */ + pool->base.replay = dmub_replay_create(ctx); + if (pool->base.replay == NULL) { + dm_error("DC: failed to create replay obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* MPCCs */ + pool->base.mpc = dcn42_mpc_create(ctx, pool->base.res_cap->num_timing_generator, + pool->base.res_cap->num_mpc_3dlut); + if (pool->base.mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto create_fail; + } + + /* DSCs */ + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn42_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create display stream compressor %d!\n", i); + goto create_fail; + } + } + + /* DWB */ + if (!dcn42_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dwbc!\n"); + goto create_fail; + } + + /* MMHUBBUB */ + if (!dcn42_mmhubbub_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mcif_wb!\n"); + goto create_fail; + } + + /* AUX and I2C */ + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); + + if (pool->base.engines[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create aux engine!!\n"); + goto create_fail; + } + pool->base.hw_i2cs[i] = dcn42_i2c_hw_create(ctx, i); + if (pool->base.hw_i2cs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create hw i2c!!\n"); + goto create_fail; + } + pool->base.sw_i2cs[i] = NULL; + } + /* DCN4.2 has 6 DPIA */ + pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router; + if (dc->debug.dpia_debug.bits.disable_dpia) + pool->base.usb4_dpia_count = 0; + + /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ + if (!resource_construct(num_virtual_links, dc, &pool->base, + &res_create_funcs)) + goto create_fail; + + /* HW Sequencer init functions and Plane caps */ + dcn42_hw_sequencer_init_functions(dc); + + dc->caps.max_planes = pool->base.pipe_count; + + for (i = 0; i < dc->caps.max_planes; ++i) + dc->caps.planes[i] = plane_cap; + + dc->caps.max_odm_combine_factor = 4; + + dc->cap_funcs = cap_funcs; + dc->dcn_ip->max_num_dpp = pool->base.pipe_count; + + // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided + if (dc->config.sdpif_request_limit_words_per_umc == 0) + dc->config.sdpif_request_limit_words_per_umc = 16; + + dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; + /*this will use real soc clock table*/ + dc->dml2_options.use_native_soc_bb_construction = true; + dc->dml2_options.minimize_dispclk_using_odm = false; + if (dc->config.EnableMinDispClkODM) + dc->dml2_options.minimize_dispclk_using_odm = true; + dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; + dc->dml2_options.map_dc_pipes_with_callbacks = true; + dc->dml2_options.force_tdlut_enable = true; + + resource_init_common_dml2_callbacks(dc, &dc->dml2_options); + dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = + &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; + dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; + dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = + pool->base.funcs->calculate_mall_ways_from_bytes; + + dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; + dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; + dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; + dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; + + dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; + dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; + + dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; + dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; + dc->dml2_options.mall_cfg.max_cab_allocation_bytes = + dc->caps.max_cab_allocation_bytes; + dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; + dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; + dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; + dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; + + dc->dml2_options.max_segments_per_hubp = 24; + dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; + + /* SPL */ + dc->caps.scl_caps.sharpener_support = true; + + /* init DC limited DML2 options */ + memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options)); + dc->dml2_dc_power_options.use_clock_dc_limits = true; + + return true; + +create_fail: + + dcn42_resource_destruct(pool); + + return false; +} +struct resource_pool *dcn42_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc) +{ + struct dcn42_resource_pool *pool = + kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL); + + if (!pool) + return NULL; + + if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) + return &pool->base; + + BREAK_TO_DEBUGGER(); + kfree(pool); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h new file mode 100644 index 0000000000000..a9b26df14520a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h @@ -0,0 +1,588 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCN42_RESOURCE_H_ +#define _DCN42_RESOURCE_H_ + +#include "core_types.h" + +#define TO_DCN42_RES_POOL(pool) \ + container_of(pool, struct dcn42_resource_pool, base) + +/* DPP */ +#define DPP_REG_LIST_DCN42_COMMON_RI(id) \ + SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \ + SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \ + SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \ + SRI_ARR(CM_HIST_CNTL, CM, id), \ + SRI_ARR(CM_HIST_LOCK, CM, id), \ + SRI_ARR(CM_HIST_INDEX, CM, id), \ + SRI_ARR(CM_HIST_DATA, CM, id), \ + SRI_ARR(CM_HIST_STATUS, CM, id), \ + SRI_ARR(CM_HIST_SCALE_SRC1, CM, id), \ + SRI_ARR(CM_HIST_COEFA_SRC2, CM, id), \ + SRI_ARR(CM_HIST_COEFB_SRC2, CM, id), \ + SRI_ARR(CM_HIST_COEFC_SRC2, CM, id), \ + SRI_ARR(CM_HIST_SCALE_SRC3, CM, id), \ + SRI_ARR(CM_HIST_BIAS_SRC1, CM, id), \ + SRI_ARR(CM_HIST_BIAS_SRC2, CM, id), \ + SRI_ARR(CM_HIST_BIAS_SRC3, CM, id), \ + SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ + SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ + SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \ + SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \ + SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \ + SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \ + SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ + SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ + SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \ + SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \ + SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \ + SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \ + SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \ + SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \ + SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \ + SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \ + SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \ + SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \ + SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \ + SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \ + SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ + SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \ + SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \ + SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \ + SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \ + SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \ + SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \ + SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ + SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id), \ + SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \ + SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \ + SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \ + SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \ + SRI_ARR(DSCL_CONTROL, DSCL, id), \ + SRI_ARR(DSCL_SC_MODE, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \ + SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \ + SRI_ARR(ISHARP_MODE, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \ + SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \ + SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \ + SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id) + +/* Stream encoder */ +#define SE_DCN42_REG_LIST_RI(id) \ + SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \ + SRI_ARR(HDMI_GC, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ + SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \ + SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \ + SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \ + SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \ + SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \ + SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \ + SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \ + SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \ + SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \ + SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \ + SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \ + SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \ + SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \ + SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \ + SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ + SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \ + SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \ + SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ + SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ + SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \ + SRI_ARR(DME_CONTROL, DME, id), \ + SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ + SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ + SRI_ARR(DIG_FE_CNTL, DIG, id), \ + SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \ + SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \ + SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \ + SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \ + SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\ + SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id) + +/* HPO DP stream encoder */ +#define DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) \ + SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \ + SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \ + SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \ + SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \ + SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \ + SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \ + SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \ + SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id) + +/*HPO DP link encoder regs */ +#define DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) \ + SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \ + SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id) + +#define VPG_DCN42_REG_LIST_RI(id) \ + SRI(VPG_GENERIC_STATUS, VPG, id), \ + SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \ + SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \ + SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \ + SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \ + SRI(VPG_MEM_PWR, VPG, id) + +/* DCCG */ +#define DCCG_REG_LIST_DCN42_RI() \ + SR(DPPCLK_DTO_CTRL), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 0), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 1), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 2), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 3), \ + DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ + SR(HDMISTREAMCLK0_DTO_PARAM),\ + SR(DCCG_GLOBAL_FGCG_REP_CNTL),\ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(PHYASYMCLK_CLOCK_CNTL), \ + SR(PHYBSYMCLK_CLOCK_CNTL), \ + SR(PHYCSYMCLK_CLOCK_CNTL), \ + SR(PHYDSYMCLK_CLOCK_CNTL), \ + SR(PHYESYMCLK_CLOCK_CNTL), \ + SR(DPSTREAMCLK_CNTL), \ + SR(HDMISTREAMCLK_CNTL), \ + SR(SYMCLK32_SE_CNTL), \ + SR(SYMCLK32_LE_CNTL), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \ + SR(OTG_PIXEL_RATE_DIV), \ + SR(DTBCLK_P_CNTL), \ + SR(DCCG_AUDIO_DTO_SOURCE), \ + SR(DENTIST_DISPCLK_CNTL), \ + SR(DPPCLK_CTRL), \ + DCCG_SRII(MODULO, DP_DTO, 0), \ + DCCG_SRII(MODULO, DP_DTO, 1), \ + DCCG_SRII(MODULO, DP_DTO, 2), \ + DCCG_SRII(MODULO, DP_DTO, 3), \ + DCCG_SRII(PHASE, DP_DTO, 0), \ + DCCG_SRII(PHASE, DP_DTO, 1), \ + DCCG_SRII(PHASE, DP_DTO, 2), \ + DCCG_SRII(PHASE, DP_DTO, 3), \ + SR(OTG_ADD_DROP_PIXEL_CNTL), \ + SR(DSCCLK0_DTO_PARAM), \ + SR(DSCCLK1_DTO_PARAM), \ + SR(DSCCLK2_DTO_PARAM), \ + SR(DSCCLK3_DTO_PARAM), \ + SR(DSCCLK_DTO_CTRL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCCG_GATE_DISABLE_CNTL3), \ + SR(DCCG_GATE_DISABLE_CNTL4), \ + SR(DCCG_GATE_DISABLE_CNTL5), \ + SR(DCCG_GATE_DISABLE_CNTL6), \ + SR(SYMCLKA_CLOCK_ENABLE), \ + SR(SYMCLKB_CLOCK_ENABLE), \ + SR(SYMCLKC_CLOCK_ENABLE), \ + SR(SYMCLKD_CLOCK_ENABLE), \ + SR(SYMCLKE_CLOCK_ENABLE) + +#define DCN42_AUD_COMMON_MASK_SH_LIST(mask_sh) \ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh), \ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\ + SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ + SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ + SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ + SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\ + SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\ + SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\ + SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) + + /* HPO FRL stream encoder */ +#define DCN42_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) \ + DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id), \ + SR_ARR(HDMI_STREAM_ENC_AUDIO_CONTROL, id),\ + SR_ARR(HDMI_TB_ENC_MEM_CTRL, id),\ + SR_ARR(HDMI_FRL_ENC_MEM_CTRL, id) +/* OPTC */ +#define OPTC_COMMON_REG_LIST_DCN42_RI(inst) \ + SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \ + SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \ + SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \ + SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \ + SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst), \ + SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst), \ + SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst), \ + SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ + SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\ + SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \ + SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \ + SRI_ARR(OTG_H_TOTAL, OTG, inst), \ + SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \ + SRI_ARR(OTG_H_SYNC_A, OTG, inst),\ + SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \ + SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL, OTG, inst), \ + SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \ + SRI_ARR(OTG_V_SYNC_A, OTG, inst), \ + SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \ + SRI_ARR(OTG_CONTROL, OTG, inst), \ + SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \ + SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \ + SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \ + SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \ + SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \ + SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \ + SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \ + SRI_ARR(OTG_STATUS, OTG, inst), \ + SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \ + SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \ + SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \ + SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \ + SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \ + SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \ + SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \ + SRI_ARR(CONTROL, VTG, inst), \ + SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \ + SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC_CNTL, OTG, inst), \ + SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \ + SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \ + SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \ + SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \ + SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \ + SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ + SR_ARR(GSL_SOURCE_SELECT, inst), \ + SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ + SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \ + SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \ + SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \ + SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \ + SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \ + SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ + SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ + SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ + SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\ + SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\ + SRI_ARR(INTERRUPT_DEST, OTG, inst) + +/* CLK SRC */ +#define CS_COMMON_REG_LIST_DCN42_RI(index, pllid) \ + SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \ + SRII_ARR_2(PHASE, DP_DTO, 0, index), \ + SRII_ARR_2(PHASE, DP_DTO, 1, index), \ + SRII_ARR_2(PHASE, DP_DTO, 2, index), \ + SRII_ARR_2(PHASE, DP_DTO, 3, index), \ + SRII_ARR_2(MODULO, DP_DTO, 0, index), \ + SRII_ARR_2(MODULO, DP_DTO, 1, index), \ + SRII_ARR_2(MODULO, DP_DTO, 2, index), \ + SRII_ARR_2(MODULO, DP_DTO, 3, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) + +/* ABM */ +#define ABM_DCN42_REG_LIST_RI(id) \ + SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ + SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ + SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \ + SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ + SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ + SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ + SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ + SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \ + SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ + SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id), \ + SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \ + SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id) + +/* HUBP */ +#define HUBP_REG_LIST_DCN42_RI(id) \ + HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ + SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ + SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ + SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id), \ + HUBP_3DLUT_FL_REG_LIST_DCN401(id) +struct dcn42_resource_pool { + struct resource_pool base; +}; +struct resource_pool *dcn42_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc); + +enum dc_status dcn42_validate_bandwidth(struct dc *dc, + struct dc_state *context, + enum dc_validate_mode validate_mode); + +void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context); + +#endif /* _DCN42_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c new file mode 100644 index 0000000000000..33b9775420d3d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + + + +#include "dc.h" +#include "dcn42_resource_fpu.h" + +#define DC_LOGGER_INIT(logger) + + +void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context) +{ + enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW; + unsigned int i, plane_count = 0; + + DC_LOGGER_INIT(dc->ctx->logger); + + dc_assert_fp_enabled(); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (context->res_ctx.pipe_ctx[i].plane_state) + plane_count++; + } + /*dcn42 has no z10*/ + if (context->stream_count == 0 || plane_count == 0) { + support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY; + } else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + struct dc_link *link = context->streams[0]->sink->link; + bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 || + link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr); + bool is_replay = link && link->replay_settings.replay_feature_enabled; + + if (is_psr || is_replay) + support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY; + else { + /*here we allow z8 for eDP based on dml21 output*/ + support = context->bw_ctx.bw.dcn.clk.zstate_support ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW; + } + + DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n, z8_stutter_efficiency: %d\n", + support, (int)context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period, + (int)context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency); + } + context->bw_ctx.bw.dcn.clk.zstate_support = support; + +} diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h new file mode 100644 index 0000000000000..e321032205073 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#ifndef _DCN42_RESOURCE_FPU_H_ +#define _DCN42_RESOURCE_FPU_H_ + +#include "core_types.h" + +void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context); + +#endif /* _DCN42_RESOURCE_FPU_H_ */ From 8e10294f16f5bfda7979a4071dc173b618929b95 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 18:35:37 -0500 Subject: [PATCH 0229/2070] drm/amd/display: Add DMUB support for dcn42 DMUB support for DCN 4.2 Signed-off-by: Roman Li Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dmub/src/dmub_dcn42.c | 752 ++++++++++++++++++ .../gpu/drm/amd/display/dmub/src/dmub_dcn42.h | 171 ++++ 2 files changed, 923 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c new file mode 100644 index 0000000000000..4d274b7034e89 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "../dmub_srv.h" +#include "dmub_reg.h" +#include "dmub_dcn35.h" +#include "dmub_dcn401.h" +#include "dmub_dcn42.h" + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" + +#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] +#define CTX dmub +#define REGS dmub->regs_dcn42 +#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) + +void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) +{ + struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42; +#define REG_STRUCT regs + +#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); + DMUB_DCN42_REGS() + DMCUB_INTERNAL_REGS() +#undef DMUB_SR + +#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); + DMUB_DCN42_FIELDS() +#undef DMUB_SF + +#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); + DMUB_DCN42_FIELDS() +#undef DMUB_SF +#undef REG_STRUCT +} + +void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) +{ + union dmub_fw_boot_options boot_options = {0}; + union dmub_fw_boot_options cur_boot_options = {0}; + + cur_boot_options = dmub_dcn42_get_fw_boot_option(dmub); + + boot_options.bits.z10_disable = params->disable_z10; + boot_options.bits.dpia_supported = params->dpia_supported; + boot_options.bits.enable_dpia = cur_boot_options.bits.enable_dpia && !params->disable_dpia; + boot_options.bits.usb4_cm_version = params->usb4_cm_version; + boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; + boot_options.bits.power_optimization = params->power_optimization; + boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds; + boot_options.bits.disable_clk_gate = params->disable_clock_gate; + boot_options.bits.ips_disable = params->disable_ips; + boot_options.bits.ips_sequential_ono = params->ips_sequential_ono; + boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; + boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; + boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; + boot_options.bits.skip_phy_access = params->disallow_phy_access; + boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; + + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +static void dmub_dcn42_get_fb_base_offset(struct dmub_srv *dmub, + uint64_t *fb_base, + uint64_t *fb_offset) +{ + uint32_t tmp; + + /* + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; + return; + } + */ + + REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); + *fb_base = (uint64_t)tmp << 24; + + REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); + *fb_offset = (uint64_t)tmp << 24; +} + +static inline void dmub_dcn42_translate_addr(const union dmub_addr *addr_in, + uint64_t fb_base, + uint64_t fb_offset, + union dmub_addr *addr_out) +{ + addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; +} + +void dmub_dcn42_reset(struct dmub_srv *dmub) +{ + union dmub_gpint_data_register cmd; + const uint32_t timeout = 100000; + uint32_t in_reset, is_enabled, scratch, i, pwait_mode; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); + + if (in_reset == 0 && is_enabled != 0) { + cmd.bits.status = 1; + cmd.bits.command_code = DMUB_GPINT__STOP_FW; + cmd.bits.param = 0; + + dmub->hw_funcs.set_gpint(dmub, cmd); + + for (i = 0; i < timeout; ++i) { + if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) + break; + + udelay(1); + } + + for (i = 0; i < timeout; ++i) { + scratch = REG_READ(DMCUB_SCRATCH7); + if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) + break; + + udelay(1); + } + + for (i = 0; i < timeout; ++i) { + REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); + if (pwait_mode & (1 << 0)) + break; + + udelay(1); + } + /* Force reset in case we timed out, DMCUB is likely hung. */ + } + + if (is_enabled) { + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); + udelay(1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); + } + + REG_WRITE(DMCUB_INBOX1_RPTR, 0); + REG_WRITE(DMCUB_INBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); + REG_WRITE(DMCUB_SCRATCH0, 0); + + /* Clear the GPINT command manually so we don't send anything during boot. */ + cmd.all = 0; + dmub->hw_funcs.set_gpint(dmub, cmd); +} + +void dmub_dcn42_reset_release(struct dmub_srv *dmub) +{ + REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); + + REG_UPDATE_3(DMU_CLK_CNTL, + LONO_DISPCLK_GATE_DISABLE, 1, + LONO_SOCCLK_GATE_DISABLE, 1, + LONO_DMCUBCLK_GATE_DISABLE, 1); + + REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); + REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); +} + +void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + uint64_t fb_base, fb_offset; + + dmub_dcn42_get_fb_base_offset(dmub, &fb_base, &fb_offset); + + dmub_dcn42_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + + dmub_dcn42_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + + /* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */ + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0); +} + +void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + offset = cw0->offset; + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + offset = cw1->offset; + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, + 0x20); +} +void dmub_dcn42_setup_windows(struct dmub_srv *dmub, + const struct dmub_window *cw2, + const struct dmub_window *cw3, + const struct dmub_window *cw4, + const struct dmub_window *cw5, + const struct dmub_window *cw6, + const struct dmub_window *region6) +{ + union dmub_addr offset; + + offset = cw3->offset; + + REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); + REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, + DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, + DMCUB_REGION3_CW3_ENABLE, 1); + + offset = cw4->offset; + + REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); + REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, + DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, + DMCUB_REGION3_CW4_ENABLE, 1); + + offset = cw5->offset; + + REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); + REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, + DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, + DMCUB_REGION3_CW5_ENABLE, 1); + + REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, + DMCUB_REGION5_TOP_ADDRESS, + cw5->region.top - cw5->region.base - 1, + DMCUB_REGION5_ENABLE, 1); + + offset = cw6->offset; + + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); + REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, + DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, + DMCUB_REGION3_CW6_ENABLE, 1); + + offset = region6->offset; + + REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, + DMCUB_REGION6_TOP_ADDRESS, + region6->region.top - region6->region.base - 1, + DMCUB_REGION6_ENABLE, 1); +} + +uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_INBOX1_WPTR); +} + +uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_INBOX1_RPTR); +} + +void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1) +{ + REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); + REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); +} + +uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub) +{ + /** + * outbox1 wptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + return REG_READ(DMCUB_OUTBOX1_WPTR); +} + +void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + /** + * outbox1 rptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); +} + +bool dmub_dcn42_is_supported(struct dmub_srv *dmub) +{ + uint32_t supported = 0; + + REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); + + return supported; +} + +union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub) +{ + union dmub_fw_boot_options option; + + option.all = REG_READ(DMCUB_SCRATCH14); + return option; +} + +void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0) +{ + REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); + + REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); +} + +bool dmub_dcn42_should_detect(struct dmub_srv *dmub) +{ + uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0); + bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0; + return should_detect; +} + +void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) +{ + REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); +} + +uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH17); +} + +bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + uint32_t is_enable; + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); + if (is_enable == 0) + return false; + + status.all = REG_READ(DMCUB_SCRATCH0); + + return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) || + (!status.bits.dal_fw && status.bits.mailbox_rdy); +} + +void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) +{ + REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); +} + +bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + uint32_t is_hw_init; + + status.all = REG_READ(DMCUB_SCRATCH0); + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); + + return is_hw_init != 0 && status.bits.dal_fw; +} + +union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + + status.all = REG_READ(DMCUB_SCRATCH0); + return status; +} + +void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) +{ + union dmub_fw_boot_options boot_options; + boot_options.all = REG_READ(DMCUB_SCRATCH14); + boot_options.bits.skip_phy_init_panel_sequence = skip; + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub) +{ + /* DMCUB_REGION3_TMR_AXI_SPACE values: + * 0b011 (0x3) - FB physical address + * 0b100 (0x4) - GPU virtual address + * + * Default value is 0x3 (FB Physical address for TMR). When programming + * DMUB to be in system memory, change to 0x4. The system memory allocated + * is accessible by both GPU and CPU, so we use GPU virtual address. + */ + REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); +} + +void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub) +{ + REG_WRITE(DMCUB_SCRATCH17, 0); +} + +void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, + union dmub_rb_cmd *cmd) +{ + uint32_t *dwords = (uint32_t *)cmd; + int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; + uint32_t msg_index; + static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); + + /* read remaining data based on payload size */ + for (msg_index = 0; msg_index < 15; msg_index++) { + if (payload_size_bytes <= msg_index * 4) { + break; + } + + switch (msg_index) { + case 0: + REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]); + break; + case 1: + REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]); + break; + case 2: + REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]); + break; + case 3: + REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]); + break; + case 4: + REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]); + break; + case 5: + REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]); + break; + case 6: + REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]); + break; + case 7: + REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]); + break; + case 8: + REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]); + break; + case 9: + REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]); + break; + case 10: + REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]); + break; + case 11: + REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]); + break; + case 12: + REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]); + break; + case 13: + REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]); + break; + case 14: + REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]); + break; + } + } + + /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY + * interrupt. + */ + REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]); +} + +uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub) +{ + uint32_t status; + + REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status); + return status; +} + +void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, + union dmub_rb_cmd *cmd) +{ + uint32_t *dwords = (uint32_t *)cmd; + + static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); + + dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP); + dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0); + dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1); + dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2); + dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3); + dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4); + dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5); + dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6); + dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7); + dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8); + dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9); + dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10); + dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11); + dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12); + dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13); + dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14); +} + +void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1); +} + +void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0); +} + +void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0); +} + +void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1); + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0); +} + +void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg) +{ + *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0); +} + + +void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0); +} + +uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub) +{ + uint32_t status; + + REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status); + return status; +} + +void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1) +{ + REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); +} + +void dmub_dcn42_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); +} + +bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + union dmub_gpint_data_register test; + + reg.bits.status = 0; + test.all = REG_READ(DMCUB_GPINT_DATAIN1); + + return test.all == reg.all; +} + +uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH7); +} + +uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub) +{ + uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); + + REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); + + REG_WRITE(DMCUB_GPINT_DATAOUT, 0); + REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); + REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); + + REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); + + return dataout; +} + +uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_OUTBOX0_WPTR); +} + +void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); +} + +uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_TIMER_CURRENT); +} + +void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub) +{ + uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait; + uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; + struct dmub_timeout_info timeout = {0}; + + if (!dmub) + return; + + /* timeout data filled externally, cache before resetting memory */ + timeout = dmub->debug.timeout_info; + memset(&dmub->debug, 0, sizeof(dmub->debug)); + dmub->debug.timeout_info = timeout; + + dmub->debug.dmcub_version = dmub->fw_version; + + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); + dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); + + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); + + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); + + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); + + dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); + dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); + dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); + dmub->debug.is_dmcub_enabled = is_dmub_enabled; + + REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); + dmub->debug.is_pwait = is_pwait; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); + dmub->debug.is_dmcub_soft_reset = is_soft_reset; + + REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); + dmub->debug.is_dmcub_secure_reset = is_sec_reset; + + REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); + dmub->debug.is_traceport_en = is_traceport_enabled; + + REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); + dmub->debug.is_cw0_enabled = is_cw0_enabled; + + REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); + dmub->debug.is_cw6_enabled = is_cw6_enabled; + + dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); +} + +bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub) +{ + uint64_t region3_cw5_offset; + uint32_t top_addr, top_addr_enable, offset_low; + uint32_t offset_high, base_addr, fw_version; + bool is_vbios_fw = false; + + memset(&dmub->preos_info, 0, sizeof(dmub->preos_info)); + + fw_version = REG_READ(DMCUB_SCRATCH1); + is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false; + if (!is_vbios_fw) + return false; + + dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0); + dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1); + dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14); + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, + DMCUB_REGION3_CW5_ENABLE, &top_addr_enable); + if (top_addr_enable) { + dmub_dcn42_get_fb_base_offset(dmub, + &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset); + offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET); + offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH); + region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low; + dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset + - dmub->preos_info.fb_base + dmub->preos_info.fb_offset; + + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, + DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr); + base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF; + dmub->preos_info.trace_buffer_size = + (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0; + } + + return true; +} + +void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp) +{ + REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp); +} + +uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub) +{ + uint32_t status; + + REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status); + return status; +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h new file mode 100644 index 0000000000000..a49d88ab0455f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _DMUB_DCN42_H_ +#define _DMUB_DCN42_H_ + +#include "dmub_dcn35.h" +#include "dmub_dcn401.h" + + +struct dmub_srv; + +/* DCN42 register definitions. */ + +#define DMUB_DCN42_REGS() \ + DMUB_DCN35_REGS() \ + DMUB_SR(DMCUB_INTERRUPT_STATUS) \ + DMUB_SR(DMCUB_REG_INBOX0_RDY) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG0) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG1) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG2) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG3) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG4) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG5) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG6) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG7) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG8) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG9) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG10) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG11) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG12) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG13) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG14) \ + DMUB_SR(DMCUB_REG_INBOX0_RSP) \ + DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \ + DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \ + DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \ + DMUB_SR(HOST_INTERRUPT_CSR) + +#define DMUB_DCN42_FIELDS() \ + DMUB_DCN35_FIELDS() \ + DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN) + +struct dmub_srv_dcn42_reg_offset { +#define DMUB_SR(reg) uint32_t reg; + DMUB_DCN42_REGS() + DMCUB_INTERNAL_REGS() +#undef DMUB_SR +}; + +struct dmub_srv_dcn42_reg_shift { +#define DMUB_SF(reg, field) uint8_t reg##__##field; + DMUB_DCN42_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn42_reg_mask { +#define DMUB_SF(reg, field) uint32_t reg##__##field; + DMUB_DCN42_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn42_regs { + struct dmub_srv_dcn42_reg_offset offset; + struct dmub_srv_dcn42_reg_mask mask; + struct dmub_srv_dcn42_reg_shift shift; +}; + +/* Function declarations */ + +/* Initialization and configuration */ +void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); +void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); +void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); +void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub); + +/* Reset and control */ +void dmub_dcn42_reset(struct dmub_srv *dmub); +void dmub_dcn42_reset_release(struct dmub_srv *dmub); + +/* Firmware loading */ +void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); +void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); +void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6); + +/* Mailbox operations - Inbox1 */ +void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1); +uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub); +uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub); +void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); + +/* Mailbox operations - Outbox1 */ +void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1); +uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub); +void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +/* Mailbox operations - Outbox0 */ +void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0); +uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub); +void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +/* Mailbox operations - Inbox0 */ +void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); +void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub); +uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub); + +/* REG Inbox0/Outbox0 operations */ +void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); +uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub); +void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); +void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); +void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); +void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable); + +void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub); +void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg); +void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp); +uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub); +void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable); +uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub); + +/* GPINT operations */ +void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg); +bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg); +uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub); +uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub); + +/* Status and detection */ +bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub); +bool dmub_dcn42_is_supported(struct dmub_srv *dmub); +bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub); +bool dmub_dcn42_should_detect(struct dmub_srv *dmub); + + +/* Firmware boot status and options */ +union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub); +union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub); + +/* Timing and diagnostics */ +uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub); +void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub); +bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub); + +#endif /* _DMUB_DCN42_H_ */ From b6d70f882cb98bc297de9285cdca049683a9b882 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 18:40:41 -0500 Subject: [PATCH 0230/2070] drm/amd/display: Enable dcn42 DMUB Enable DMUB support for DCN 4.2 Signed-off-by: Roman Li Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 5 +- drivers/gpu/drm/amd/display/dmub/src/Makefile | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 64 ++++++++++++++++++- 3 files changed, 68 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 3b6bba0170406..c18ff8f00bb85 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2019-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -119,6 +120,7 @@ enum dmub_asic { DMUB_ASIC_DCN351, DMUB_ASIC_DCN36, DMUB_ASIC_DCN401, + DMUB_ASIC_DCN42, DMUB_ASIC_MAX, }; @@ -602,6 +604,7 @@ struct dmub_srv { struct dmub_srv_dcn32_regs *regs_dcn32; struct dmub_srv_dcn35_regs *regs_dcn35; const struct dmub_srv_dcn401_regs *regs_dcn401; + struct dmub_srv_dcn42_regs *regs_dcn42; struct dmub_srv_base_funcs funcs; struct dmub_srv_hw_funcs hw_funcs; struct dmub_srv_inbox inbox1; diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile index 468b768c11aeb..ac7b17d8fb0fd 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/Makefile +++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Advanced Micro Devices, Inc. +# Copyright 2019-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -28,6 +28,7 @@ DMUB += dmub_dcn35.o DMUB += dmub_dcn351.o DMUB += dmub_dcn36.o DMUB += dmub_dcn401.o +DMUB += dmub_dcn42.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 83cf4888fb540..3bba256a288d7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -1,5 +1,6 @@ +// SPDX-License-Identifier: MIT /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2019-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -22,7 +23,6 @@ * Authors: AMD * */ - #include "../dmub_srv.h" #include "dmub_dcn20.h" #include "dmub_dcn21.h" @@ -40,6 +40,7 @@ #include "dmub_dcn351.h" #include "dmub_dcn36.h" #include "dmub_dcn401.h" +#include "dmub_dcn42.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be @@ -87,6 +88,7 @@ static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; +struct dmub_srv_dcn42_regs dmub_srv_dcn42_regs; static inline uint32_t dmub_align(uint32_t val, uint32_t factor) { @@ -410,6 +412,64 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; funcs->should_detect = dmub_dcn35_should_detect; break; + case DMUB_ASIC_DCN42: + dmub->regs_dcn42 = &dmub_srv_dcn42_regs; + funcs->configure_dmub_in_system_memory = dmub_dcn42_configure_dmub_in_system_memory; + funcs->send_inbox0_cmd = dmub_dcn42_send_inbox0_cmd; + funcs->clear_inbox0_ack_register = dmub_dcn42_clear_inbox0_ack_register; + funcs->read_inbox0_ack_register = dmub_dcn42_read_inbox0_ack_register; + funcs->reset = dmub_dcn42_reset; + funcs->reset_release = dmub_dcn42_reset_release; + funcs->backdoor_load = dmub_dcn42_backdoor_load; + funcs->backdoor_load_zfb_mode = dmub_dcn42_backdoor_load_zfb_mode; + funcs->setup_windows = dmub_dcn42_setup_windows; + funcs->setup_mailbox = dmub_dcn42_setup_mailbox; + funcs->get_inbox1_wptr = dmub_dcn42_get_inbox1_wptr; + funcs->get_inbox1_rptr = dmub_dcn42_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn42_set_inbox1_wptr; + funcs->setup_out_mailbox = dmub_dcn42_setup_out_mailbox; + funcs->get_outbox1_wptr = dmub_dcn42_get_outbox1_wptr; + funcs->set_outbox1_rptr = dmub_dcn42_set_outbox1_rptr; + funcs->is_supported = dmub_dcn42_is_supported; + funcs->is_hw_init = dmub_dcn42_is_hw_init; + funcs->set_gpint = dmub_dcn42_set_gpint; + funcs->is_gpint_acked = dmub_dcn42_is_gpint_acked; + funcs->get_gpint_response = dmub_dcn42_get_gpint_response; + funcs->get_gpint_dataout = dmub_dcn42_get_gpint_dataout; + funcs->get_fw_status = dmub_dcn42_get_fw_boot_status; + funcs->get_fw_boot_option = dmub_dcn42_get_fw_boot_option; + funcs->enable_dmub_boot_options = dmub_dcn42_enable_dmub_boot_options; + funcs->skip_dmub_panel_power_sequence = dmub_dcn42_skip_dmub_panel_power_sequence; + /*outbox0 call stacks*/ + funcs->setup_outbox0 = dmub_dcn42_setup_outbox0; + funcs->get_outbox0_wptr = dmub_dcn42_get_outbox0_wptr; + funcs->set_outbox0_rptr = dmub_dcn42_set_outbox0_rptr; + + funcs->get_current_time = dmub_dcn42_get_current_time; + funcs->get_diagnostic_data = dmub_dcn42_get_diagnostic_data; + funcs->get_preos_fw_info = dmub_dcn42_get_preos_fw_info; + + /*carried from dcn401*/ + funcs->send_reg_inbox0_cmd_msg = dmub_dcn42_send_reg_inbox0_cmd_msg; + funcs->read_reg_inbox0_rsp_int_status = dmub_dcn42_read_reg_inbox0_rsp_int_status; + funcs->read_reg_inbox0_cmd_rsp = dmub_dcn42_read_reg_inbox0_cmd_rsp; + funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn42_write_reg_inbox0_rsp_int_ack; + funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn42_clear_reg_inbox0_rsp_int_ack; + funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; + default_inbox_type = DMUB_CMD_INTERFACE_FB; /*still default to FB for now*/ + + funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn42_write_reg_outbox0_rdy_int_ack; + funcs->read_reg_outbox0_msg = dmub_dcn42_read_reg_outbox0_msg; + funcs->write_reg_outbox0_rsp = dmub_dcn42_write_reg_outbox0_rsp; + funcs->read_reg_outbox0_rdy_int_status = dmub_dcn42_read_reg_outbox0_rdy_int_status; + funcs->read_reg_outbox0_rsp_int_status = dmub_dcn42_read_reg_outbox0_rsp_int_status; + funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; + funcs->enable_reg_outbox0_rdy_int = dmub_dcn42_enable_reg_outbox0_rdy_int; + funcs->init_reg_offsets = dmub_srv_dcn42_regs_init; + + funcs->is_hw_powered_up = dmub_dcn42_is_hw_powered_up; + funcs->should_detect = dmub_dcn42_should_detect; + break; case DMUB_ASIC_DCN401: dmub->regs_dcn401 = &dmub_srv_dcn401_regs; From c6dbea344ca75d96d7fa4c15647629ddb62c1f5c Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 18:47:34 -0500 Subject: [PATCH 0231/2070] drm/amd/display: Enable dcn42 DC Add support for DCN 4.2 in Display Core Signed-off-by: Roman Li Acked-by: Harry Wentland --- .../display/dc/bios/command_table_helper2.c | 1 + .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 11 ++- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 39 +++++++++- .../gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++ drivers/gpu/drm/amd/display/dc/dc.h | 10 ++- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 73 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc_types.h | 6 +- drivers/gpu/drm/amd/display/dc/dccg/Makefile | 11 ++- .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 15 +++- drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 60 ++++++++++++++- drivers/gpu/drm/amd/display/dc/dio/Makefile | 11 ++- .../dc/dio/dcn10/dcn10_stream_encoder.h | 10 ++- drivers/gpu/drm/amd/display/dc/dpp/Makefile | 10 ++- .../amd/display/dc/dpp/dcn401/dcn401_dpp.h | 5 +- drivers/gpu/drm/amd/display/dc/gpio/Makefile | 13 +++- .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 + .../drm/amd/display/dc/gpio/hw_translate.c | 4 + drivers/gpu/drm/amd/display/dc/hpo/Makefile | 11 ++- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.h | 10 ++- .../gpu/drm/amd/display/dc/hubbub/Makefile | 10 ++- .../display/dc/hubbub/dcn10/dcn10_hubbub.h | 6 +- drivers/gpu/drm/amd/display/dc/hubp/Makefile | 10 ++- .../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 8 +- drivers/gpu/drm/amd/display/dc/hwss/Makefile | 12 ++- .../drm/amd/display/dc/hwss/dce/dce_hwseq.h | 13 +++- .../drm/amd/display/dc/hwss/hw_sequencer.h | 17 ++++- .../display/dc/hwss/hw_sequencer_private.h | 5 +- .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 24 +++++- .../amd/display/dc/inc/hw/clk_mgr_internal.h | 42 ++++++++++- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 10 ++- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 20 ++++- .../amd/display/dc/inc/hw/timing_generator.h | 4 +- drivers/gpu/drm/amd/display/dc/irq/Makefile | 9 +++ .../gpu/drm/amd/display/dc/mmhubbub/Makefile | 10 ++- drivers/gpu/drm/amd/display/dc/mpc/Makefile | 10 ++- .../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 13 +++- .../amd/display/dc/mpc/dcn401/dcn401_mpc.h | 10 ++- drivers/gpu/drm/amd/display/dc/optc/Makefile | 10 ++- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 20 ++++- drivers/gpu/drm/amd/display/dc/pg/Makefile | 10 ++- .../gpu/drm/amd/display/dc/resource/Makefile | 18 +++++ 42 files changed, 568 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 268e2414b34f0..a93a8860535a1 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -84,6 +84,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCN_VERSION_3_51: case DCN_VERSION_3_6: case DCN_VERSION_4_01: + case DCN_VERSION_4_2: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index 612a30a03fca5..98911ef56c2ed 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2017-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -176,4 +176,13 @@ CLK_MGR_DCN401 = dcn401_clk_mgr.o dcn401_clk_mgr_smu_msg.o AMD_DAL_CLK_MGR_DCN401 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn401/,$(CLK_MGR_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN401) + +############################################################################### +# DCN42 +############################################################################### +CLK_MGR_DCN42 = dcn42_smu.o dcn42_clk_mgr.o + +AMD_DAL_CLK_MGR_DCN42 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn42/,$(CLK_MGR_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 052d573408c3e..b380044416164 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -846,6 +846,16 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; (*num_steps)++; } + if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) { + block_sequence[*num_steps].params.control_cm_hist_params.dpp + = current_mpc_pipe->plane_res.dpp; + block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control + = current_mpc_pipe->plane_state->cm_hist_control; + block_sequence[*num_steps].params.control_cm_hist_params.color_space + = current_mpc_pipe->plane_state->color_space; + block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST; + (*num_steps)++; + } } if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc; @@ -1029,6 +1039,9 @@ void hwss_execute_sequence(struct dc *dc, case HUBP_PROGRAM_MCACHE_ID: hwss_program_mcache_id_and_split_coordinate(params); break; + case DPP_PROGRAM_CM_HIST: + hwss_program_cm_hist(params); + break; case PROGRAM_CURSOR_UPDATE_NOW: dc->hwss.program_cursor_offload_now( params->program_cursor_update_now_params.dc, @@ -2054,6 +2067,16 @@ void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *pa } +void hwss_program_cm_hist(union block_sequence_params *params) +{ + struct dpp *dpp = params->control_cm_hist_params.dpp; + + if (dpp && dpp->funcs->dpp_cm_hist_control) + dpp->funcs->dpp_cm_hist_control(dpp, + params->control_cm_hist_params.cm_hist_control, + params->control_cm_hist_params.color_space); +} + void get_surface_tile_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color) @@ -3370,6 +3393,20 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s } } +void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct cm_hist_control cm_hist_control, + enum dc_color_space color_space) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST; + seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control; + seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space; + (*seq_state->num_steps)++; + } +} + void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, struct dc *dc, bool enable) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 03d125f794b05..c9fbb64d706a2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -78,6 +78,7 @@ #include "dcn351/dcn351_resource.h" #include "dcn36/dcn36_resource.h" #include "dcn401/dcn401_resource.h" +#include "dcn42/dcn42_resource.h" #if defined(CONFIG_DRM_AMD_DC_FP) #include "dc_spl_translate.h" #endif @@ -252,6 +253,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_4_01; break; + case AMDGPU_FAMILY_GC_11_5_4: + dc_version = DCN_VERSION_4_2; + break; default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -368,6 +372,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, case DCN_VERSION_4_01: res_pool = dcn401_create_resource_pool(init_data, dc); break; + case DCN_VERSION_4_2: + res_pool = dcn42_create_resource_pool(init_data, dc); + break; #endif /* CONFIG_DRM_AMD_DC_FP */ default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index eb9de0e48c63c..d2ea4e03c963a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-2023 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -733,6 +733,8 @@ struct dc_clocks { struct { uint8_t base_efficiency; //LP1 uint8_t low_power_efficiency; //LP2 + uint8_t z8_stutter_efficiency; + int z8_stutter_period; } stutter_efficiency; }; @@ -1211,6 +1213,7 @@ struct dc_debug_options { unsigned int num_fast_flips_to_steady_state_override; bool enable_dmu_recovery; unsigned int force_vmin_threshold; + bool enable_otg_frame_sync_pwa; }; @@ -1419,6 +1422,7 @@ struct dc_plane_status { struct dc_plane_address current_address; bool is_flip_pending; bool is_right_eye; + struct cm_hist cm_hist; }; union surface_update_flags { @@ -1455,6 +1459,7 @@ union surface_update_flags { uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ uint32_t full_update:1; uint32_t sdr_white_level_nits:1; + uint32_t cm_hist_change:1; } bits; uint32_t raw; @@ -1539,6 +1544,7 @@ struct dc_plane_state { int sharpness_level; enum linear_light_scaling linear_light_scaling; unsigned int sdr_white_level_nits; + struct cm_hist_control cm_hist_control; struct spl_sharpness_range sharpness_range; enum sharpness_range_source sharpness_source; }; @@ -1847,6 +1853,7 @@ struct dc_fast_update { struct dc_transfer_func *out_transfer_func; struct dc_csc_transform *output_csc_transform; const struct dc_csc_transform *cursor_csc_color_matrix; + struct cm_hist_control *cm_hist_control; }; struct dc_surface_update { @@ -1879,6 +1886,7 @@ struct dc_surface_update { const struct dc_csc_transform *cursor_csc_color_matrix; unsigned int sdr_white_level_nits; struct dc_bias_and_scale bias_and_scale; + struct cm_hist_control *cm_hist_control; }; struct dc_underflow_debug_data { diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 5a365bd19933f..04b8b798dfff6 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -751,6 +751,8 @@ char *dce_version_to_string(const int version) return "DCN 3.6"; case DCN_VERSION_4_01: return "DCN 4.0.1"; + case DCN_VERSION_4_2: + return "DCN 4.2"; default: return "Unknown"; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index cfa569a7bff1b..9bf853edc46fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -271,6 +271,15 @@ enum tile_split_values_new { DC_SURF_TILE_SPLIT_1KB = 0x4, }; +enum otg_pwa_sync_mode { + DC_OTG_PWA_FRAME_SYNC_MODE_VSYNC = 0x0, + DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP = 0x1, +}; +struct otc_pwa_frame_sync { + enum otg_pwa_sync_mode pwa_sync_mode; + uint32_t pwa_frame_sync_line_offset; +}; + /* TODO: These values come from hardware spec. We need to readdress this * if they ever change. */ @@ -1137,6 +1146,7 @@ struct mcif_buf_params { unsigned int warmup_pitch; unsigned int swlock; unsigned int p_vmid; + uint8_t tmz_id; }; @@ -1162,5 +1172,68 @@ struct phy_state { enum symclk_state symclk_state; }; +enum cm_hist_tap_point { + CM_HIST_TAP_POINT_1, + CM_HIST_TAP_POINT_2, + CM_HIST_TAP_POINT_3, + CM_HIST_TAP_POINT_4, +}; + +enum cm_hist_src { + CM_HIST_SRC1, + CM_HIST_SRC2, + CM_HIST_SRC3, +}; + +enum cm_hist_format { + CM_HIST_FORMAT_FIXED_POINT, + CM_HIST_FORMAT_FP16_POS, + CM_HIST_FORMAT_FP16_POS_AND_NEG, +}; + +enum cm_hist_read_channel_mask { + CM_HIST_READ_DISABLED, + CM_HIST_READ_CH1, + CM_HIST_READ_CH2, + CM_HIST_READ_CH1_CH2, + CM_HIST_READ_CH3, + CM_HIST_READ_CH1_CH3, + CM_HIST_READ_CH2_CH3, + CM_HIST_READ_ALL, +}; + +enum cm_hist_src1_mode { + CM_HIST_SRC1_MODE_R_OR_CR, + CM_HIST_SRC1_MODE_MAX_RGB, +}; + +enum cm_hist_src2_mode { + CM_HIST_SRC2_MODE_G_OR_Y, + CM_HIST_SRC2_MODE_RGB_TO_Y, +}; + +enum cm_hist_src3_mode { + CM_HIST_SRC3_MODE_B_OR_CB, + CM_HIST_SRC3_MODE_MIN_RGB, +}; + +struct cm_hist_control { + enum cm_hist_tap_point tap_point; + uint32_t channels_enabled; + enum cm_hist_src1_mode src_1_select; + enum cm_hist_src2_mode src_2_select; + enum cm_hist_src3_mode src_3_select; + enum cm_hist_src ch1_src; + enum cm_hist_src ch2_src; + enum cm_hist_src ch3_src; + enum cm_hist_format format; + enum cm_hist_read_channel_mask read_channel_mask; +}; + +struct cm_hist { + uint32_t ch1[256]; + uint32_t ch2[256]; + uint32_t ch3[256]; +}; #endif /* DC_HW_TYPES_H */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index bddb16bb76d41..d2e60480fb2be 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1346,6 +1346,7 @@ enum dc_cm2_gpu_mem_layout { enum dc_cm2_gpu_mem_pixel_component_order { DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, + DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA }; enum dc_cm2_gpu_mem_format { @@ -1367,6 +1368,9 @@ struct dc_cm2_gpu_mem_format_parameters { enum dc_cm2_gpu_mem_size { DC_CM2_GPU_MEM_SIZE_171717, + DC_CM2_GPU_MEM_SIZE_333333, + DC_CM2_GPU_MEM_SIZE_454545, + DC_CM2_GPU_MEM_SIZE_656565, DC_CM2_GPU_MEM_SIZE_TRANSFORMED, }; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/Makefile b/drivers/gpu/drm/amd/display/dc/dccg/Makefile index 1d5cf0f8e79d6..bf7e71166b5ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dccg/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -100,4 +100,13 @@ DCCG_DCN401 = dcn401_dccg.o AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401) + +############################################################################### +# DCN42 +############################################################################### +DCCG_DCN42 = dcn42_dccg.o + +AMD_DAL_DCCG_DCN42 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn42/,$(DCCG_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 3711d400773af..ffcd2e139e764 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 Advanced Micro Devices, Inc. + * Copyright 2018-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -362,6 +362,16 @@ type SYMCLK32_LE3_EN;\ type DP_DTO_ENABLE[MAX_PIPES]; +#define DCCG42_REG_FIELD_LIST(type) \ + type OTG0_ADD_PIXEL;\ + type OTG1_ADD_PIXEL;\ + type OTG2_ADD_PIXEL;\ + type OTG0_DROP_PIXEL;\ + type OTG1_DROP_PIXEL;\ + type OTG2_DROP_PIXEL;\ + type OTG3_ADD_PIXEL;\ + type OTG3_DROP_PIXEL; + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) @@ -370,6 +380,7 @@ struct dccg_shift { DCCG32_REG_FIELD_LIST(uint8_t) DCCG35_REG_FIELD_LIST(uint8_t) DCCG401_REG_FIELD_LIST(uint8_t) + DCCG42_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { @@ -380,6 +391,7 @@ struct dccg_mask { DCCG32_REG_FIELD_LIST(uint32_t) DCCG35_REG_FIELD_LIST(uint32_t) DCCG401_REG_FIELD_LIST(uint32_t) + DCCG42_REG_FIELD_LIST(uint32_t) }; #define DCCG_REG_VARIABLE_LIST \ @@ -493,6 +505,7 @@ struct dccg_mask { struct dccg_registers { DCCG_REG_VARIABLE_LIST; + uint32_t OTG_ADD_DROP_PIXEL_CNTL; }; struct dcn_dccg { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 3d819fc5654cd..1e9ab5ff3a31e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-16 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -300,6 +300,64 @@ ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \ ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh) +#define ABM_MASK_SH_LIST_DCN42(mask_sh) \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \ + ABM1_ACE_SLOPE_DATA, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \ + ABM1_ACE_OFFSET_DATA, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_LOCK, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \ + ABM1_HG_RESULT_DATA, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \ + ABM1_HG_RESULT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \ + ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \ + ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \ + ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \ + ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \ + ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh) + #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ type ABM1_HG_VMAX_SEL; \ diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile b/drivers/gpu/drm/amd/display/dc/dio/Makefile index 2f5619078e1f9..4832533b9514a 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dio/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -123,4 +123,13 @@ DIO_DCN401 = dcn401_dio_link_encoder.o dcn401_dio_stream_encoder.o AMD_DAL_DIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/dio/dcn401/,$(DIO_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN401) + +############################################################################### +# DCN42 +############################################################################### +DIO_DCN42 = dcn42_dio_link_encoder.o dcn42_dio_stream_encoder.o + +AMD_DAL_DIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/dio/dcn42/,$(DIO_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h index 54a6a4ebd6363..7553675065563 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -190,6 +190,7 @@ struct dcn10_stream_enc_registers { uint32_t DIG_FE_CLK_CNTL; uint32_t DIG_FE_EN_CNTL; uint32_t STREAM_MAPPER_CONTROL; + uint32_t DIG_FE_AUDIO_CNTL; }; @@ -598,6 +599,11 @@ struct dcn10_stream_enc_registers { type DP_VID_N_INTERVAL;\ type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;\ type DP_STEER_FIFO_ENABLE + +#define SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(type) \ + type DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\ + type APG_CLOCK_ENABLE + struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN1_0(uint8_t); uint8_t HDMI_ACP_SEND; @@ -606,6 +612,7 @@ struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t); SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t); SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t); + SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t); }; struct dcn10_stream_encoder_mask { @@ -616,6 +623,7 @@ struct dcn10_stream_encoder_mask { SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t); SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t); SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t); + SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t); }; struct dcn10_stream_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dpp/Makefile b/drivers/gpu/drm/amd/display/dc/dpp/Makefile index 8324a56fe7dbf..2595b2504f9d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dpp/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -80,4 +80,12 @@ AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN401) +############################################################################### +# DCN42 +############################################################################### +DPP_DCN42 = dcn42_dpp.o + +AMD_DAL_DPP_DCN42 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn42/,$(DPP_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h index 58b9f1cd08255..debcf308cb3b0 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h @@ -1,4 +1,5 @@ -/* Copyright 2023 Advanced Micro Devices, Inc. +/* SPDX-License-Identifier: MIT */ +/* Copyright 2023-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -653,6 +654,8 @@ struct dcn401_dpp_registers { DPP_REG_VARIABLE_LIST_DCN401; + uint32_t ALPHA_2BIT_LUT01; + uint32_t ALPHA_2BIT_LUT23; }; struct dcn401_dpp_shift { diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index b72e2a9f9a28e..f8142ebf363f3 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2017-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -132,3 +132,14 @@ AMD_DAL_GPIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn401/,$(GPIO_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN401) +############################################################################### +# DCN 4.2 +############################################################################### + +GPIO_DCN42 = hw_translate_dcn42.o hw_factory_dcn42.o + +AMD_DAL_GPIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn42/,$(GPIO_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN42) + + diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 8bc67ca421977..f3d562c8df4c9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -53,6 +53,7 @@ #include "dcn315/hw_factory_dcn315.h" #include "dcn32/hw_factory_dcn32.h" #include "dcn401/hw_factory_dcn401.h" +#include "dcn42/hw_factory_dcn42.h" bool dal_hw_factory_init( struct hw_factory *factory, @@ -118,6 +119,9 @@ bool dal_hw_factory_init( case DCN_VERSION_4_01: dal_hw_factory_dcn401_init(factory); return true; + case DCN_VERSION_4_2: + dal_hw_factory_dcn42_init(factory); + return true; default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index cb79a28322877..1c977fc4d0e36 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -53,6 +53,7 @@ #include "dcn315/hw_translate_dcn315.h" #include "dcn32/hw_translate_dcn32.h" #include "dcn401/hw_translate_dcn401.h" +#include "dcn42/hw_translate_dcn42.h" /* * This unit @@ -119,6 +120,9 @@ bool dal_hw_translate_init( case DCN_VERSION_4_01: dal_hw_translate_dcn401_init(translate); return true; + case DCN_VERSION_4_2: + dal_hw_translate_dcn42_init(translate); + return true; default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/hpo/Makefile b/drivers/gpu/drm/amd/display/dc/hpo/Makefile index 7f2c9ee0dff1d..25b196714bd8c 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hpo/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -47,4 +47,13 @@ HPO_DCN32 = dcn32_hpo_dp_link_encoder.o AMD_DAL_HPO_DCN32 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn32/,$(HPO_DCN32)) AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN32) + +############################################################################### +# DCN42 +############################################################################### +HPO_DCN42 = dcn42_hpo_dp_link_encoder.o + +AMD_DAL_HPO_DCN42 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn42/,$(HPO_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h index 82c3b3ac1f0d0..d96fcc59cc0ee 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2019-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -208,17 +208,24 @@ type CRC_CONT_MODE_ENABLE;\ type HBLANK_MINIMUM_SYMBOL_WIDTH +#define DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \ + type DP_STREAM_ENC_APG_CLOCK_EN +#define DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\ + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh),\ + SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_APG_CLOCK_EN, mask_sh) struct dcn31_hpo_dp_stream_encoder_registers { DCN3_1_HPO_DP_STREAM_ENC_REGS; }; struct dcn31_hpo_dp_stream_encoder_shift { DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t); + DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t); }; struct dcn31_hpo_dp_stream_encoder_mask { DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t); + DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t); }; struct dcn31_hpo_dp_stream_encoder { @@ -241,5 +248,4 @@ void dcn31_hpo_dp_stream_encoder_construct( const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift, const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask); - #endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile index 66ca5a6a0415e..29c8e2651442b 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -101,4 +101,12 @@ AMD_DAL_HUBBUB_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn401/,$(HUBBUB_DCN AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN401) ############################################################################### +# DCN42 +############################################################################### +HUBBUB_DCN42 = dcn42_hubbub.o + +AMD_DAL_HUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn42/,$(HUBBUB_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index 990d3cd8e0505..ff9a1ae29474f 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -1,5 +1,5 @@ /* - * Copyright 2016 Advanced Micro Devices, Inc. + * Copyright 2016-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -441,6 +441,8 @@ struct dcn_hubbub_registers { type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE;\ type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE +#define HUBBUB_REG_FIELD_LIST_DCN4_2(type) \ + type URGENT_ZERO_SIZE_REQ_EN struct dcn_hubbub_shift { DCN_HUBBUB_REG_FIELD_LIST(uint8_t); HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); @@ -449,6 +451,7 @@ struct dcn_hubbub_shift { HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); HUBBUB_REG_FIELD_LIST_DCN35(uint8_t); HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t); + HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t); }; @@ -460,6 +463,7 @@ struct dcn_hubbub_mask { HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); HUBBUB_REG_FIELD_LIST_DCN35(uint32_t); HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t); + HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t); }; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/Makefile b/drivers/gpu/drm/amd/display/dc/hubp/Makefile index a2d1128de7a18..e0799bb873e69 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hubp/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -94,4 +94,12 @@ AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN401) +############################################################################### + +HUBP_DCN42 = dcn42_hubp.o + +AMD_DAL_HUBP_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn42/,$(HUBP_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h index 7062e6653062a..80be394a8852d 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-17 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -288,16 +288,22 @@ type MCACHEID_MALL_PREF_2H_P1;\ type HUBP_FGCG_REP_DIS +#define DCN42_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + type HUBP_3DLUT_CROSSBAR_SEL_G;\ + type HUBP_3DLUT_CROSSBAR_SEL_B;\ + type HUBP_3DLUT_CROSSBAR_SEL_R struct dcn_hubp2_registers { DCN401_HUBP_REG_COMMON_VARIABLE_LIST; }; struct dcn_hubp2_shift { DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); + DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); }; struct dcn_hubp2_mask { DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); + DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); }; struct dcn20_hubp { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile index bee617ca0838c..08cbbf87a19fa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hwss/Makefile @@ -1,5 +1,4 @@ - -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -199,4 +198,13 @@ HWSS_DCN401 = dcn401_hwseq.o dcn401_init.o AMD_DAL_HWSS_DCN401 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn401/,$(HWSS_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN401) + +############################################################################### + +HWSS_DCN42 = dcn42_hwseq.o dcn42_init.o + +AMD_DAL_HWSS_DCN42 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn42/,$(HWSS_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h index f66a38f43a091..dc8feca578c5b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h @@ -1,5 +1,5 @@ /* - * Copyright 2016 Advanced Micro Devices, Inc. + * Copyright 2016, 2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -700,6 +700,8 @@ struct dce_hwseq_registers { uint32_t DOMAIN23_PG_STATUS; uint32_t DOMAIN24_PG_STATUS; uint32_t DOMAIN25_PG_STATUS; + uint32_t DOMAIN26_PG_CONFIG; + uint32_t DOMAIN26_PG_STATUS; }; /* set field name */ #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ @@ -1245,6 +1247,13 @@ struct dce_hwseq_registers { type DOMAIN25_PGFSM_PWR_STATUS; \ type DOMAIN_DESIRED_PWR_STATE; +#define HWSEQ_DCN42_REG_FIELD_LIST(type) \ + type DPIASYMCLK4_GATE_DISABLE;\ + type DPIASYMCLK5_GATE_DISABLE;\ + type DOMAIN26_POWER_FORCEON; \ + type DOMAIN26_POWER_GATE; \ + type DOMAIN26_PGFSM_PWR_STATUS; + struct dce_hwseq_shift { HWSEQ_REG_FIELD_LIST(uint8_t) HWSEQ_DCN_REG_FIELD_LIST(uint8_t) @@ -1253,6 +1262,7 @@ struct dce_hwseq_shift { HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) HWSEQ_DCN35_REG_FIELD_LIST(uint8_t) HWSEQ_DCN401_REG_FIELD_LIST(uint8_t) + HWSEQ_DCN42_REG_FIELD_LIST(uint8_t) }; struct dce_hwseq_mask { @@ -1263,6 +1273,7 @@ struct dce_hwseq_mask { HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) HWSEQ_DCN35_REG_FIELD_LIST(uint32_t) HWSEQ_DCN401_REG_FIELD_LIST(uint32_t) + HWSEQ_DCN42_REG_FIELD_LIST(uint32_t) }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 93e171c3a179e..bd6101f712168 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -174,6 +174,12 @@ struct program_mcache_id_and_split_coordinate { struct dml2_hubp_pipe_mcache_regs *mcache_regs; }; +struct control_cm_hist_params { + struct dpp *dpp; + struct cm_hist_control cm_hist_control; + enum dc_color_space color_space; +}; + struct program_cursor_update_now_params { struct dc *dc; struct pipe_ctx *pipe_ctx; @@ -755,6 +761,7 @@ union block_sequence_params { struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; struct program_surface_config_params program_surface_config_params; struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; + struct control_cm_hist_params control_cm_hist_params; struct program_cursor_update_now_params program_cursor_update_now_params; struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; @@ -879,6 +886,7 @@ enum block_sequence_func { DMUB_HW_CONTROL_LOCK_FAST, HUBP_PROGRAM_SURFACE_CONFIG, HUBP_PROGRAM_MCACHE_ID, + DPP_PROGRAM_CM_HIST, PROGRAM_CURSOR_UPDATE_NOW, HUBP_WAIT_PIPE_READ_START, HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, @@ -1413,6 +1421,8 @@ void hwss_program_surface_config(union block_sequence_params *params); void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); +void hwss_program_cm_hist(union block_sequence_params *params); + void hwss_set_odm_combine(union block_sequence_params *params); void hwss_set_odm_bypass(union block_sequence_params *params); @@ -1763,6 +1773,11 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s bool use_default_params, struct pipe_ctx *pipe_ctx); +void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct cm_hist_control cm_hist_control, + enum dc_color_space color_space); + void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, struct dc *dc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h index 406db231bc72a..8e3f54fb53fd6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -222,6 +222,9 @@ struct hwseq_private_funcs { void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only); void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx); void (*dc_ip_request_cntl)(struct dc *dc, bool enable); + void (*program_cm_hist)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); }; struct dce_hwseq { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 2c9a4a12bd8a7..91eba1985bab1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2012-16 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -95,6 +96,26 @@ struct dcn301_clk_internal { uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass }; +struct dcn42_clk_internal { + int dummy; + uint32_t CLK8_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK8_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK8_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK8_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK8_CLK4_CURRENT_CNT; //dtbclk + uint32_t CLK8_CLK0_DS_CNTL; //dispclk deep_sleep_divider + uint32_t CLK8_CLK1_DS_CNTL; //dppclk deep_sleep_divider + uint32_t CLK8_CLK2_DS_CNTL; //dprefclk deep_sleep_divider + uint32_t CLK8_CLK3_DS_CNTL; //dcfclk deep_sleep_divider + uint32_t CLK8_CLK4_DS_CNTL; //dtbclk deep_sleep_divider + uint32_t CLK8_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK8_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK8_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK8_CLK3_BYPASS_CNTL; //dcfclk bypass + uint32_t CLK8_CLK4_BYPASS_CNTL; //dtbclk bypass + uint32_t CLK8_CLK_TICK_CNT__TIMER_THRESHOLD; +}; + /* Will these bw structures be ASIC specific? */ #define MAX_NUM_DPM_LVL 8 @@ -194,6 +215,7 @@ struct clk_state_registers_and_bypass { uint32_t dcfclk_bypass; uint32_t dprefclk_bypass; uint32_t dispclk_bypass; + uint32_t timer_threhold; }; struct rv1_clk_internal { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 836a28134d415..8d694a3a7e07a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2018 Advanced Micro Devices, Inc. + * Copyright 2018-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -223,6 +224,29 @@ enum dentist_divider_range { #define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \ CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) +#define CLK_REG_LIST_DCN42() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN42(CLK8_CLK_TICK_CNT_CONFIG_REG), \ + CLK_SR_DCN42(CLK8_CLK0_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK1_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK2_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK3_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK4_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK0_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK1_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK2_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK3_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK4_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK0_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK1_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK2_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK3_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK4_DS_CNTL) + +#define CLK_COMMON_MASK_SH_LIST_DCN42(mask_sh) 0 + + + #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ type DENTIST_DPREFCLK_WDIVIDER; \ @@ -298,6 +322,22 @@ struct clk_mgr_registers { uint32_t CLK1_CLK5_ALLOW_DS; uint32_t CLK5_spll_field_8; uint32_t CLK6_spll_field_8; + uint32_t CLK8_CLK0_CURRENT_CNT; + uint32_t CLK8_CLK1_CURRENT_CNT; + uint32_t CLK8_CLK2_CURRENT_CNT; + uint32_t CLK8_CLK3_CURRENT_CNT; + uint32_t CLK8_CLK4_CURRENT_CNT; + uint32_t CLK8_CLK0_DS_CNTL; + uint32_t CLK8_CLK1_DS_CNTL; + uint32_t CLK8_CLK2_DS_CNTL; + uint32_t CLK8_CLK3_DS_CNTL; + uint32_t CLK8_CLK4_DS_CNTL; + uint32_t CLK8_CLK0_BYPASS_CNTL; + uint32_t CLK8_CLK1_BYPASS_CNTL; + uint32_t CLK8_CLK2_BYPASS_CNTL; + uint32_t CLK8_CLK3_BYPASS_CNTL; + uint32_t CLK8_CLK4_BYPASS_CNTL; + uint32_t CLK8_CLK_TICK_CNT_CONFIG_REG; }; struct clk_mgr_shift { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index d88b57d4f5125..39215ecb480e4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -367,6 +367,14 @@ struct dpp_funcs { void (*dpp_force_disable_cursor)(struct dpp *dpp_base); + void (*dpp_cm_hist_control)( + struct dpp *dpp_base, + struct cm_hist_control cm_hist_control, + enum dc_color_space color_space); + + bool (*dpp_cm_hist_read)( + struct dpp *dpp_base, + struct cm_hist *cm_hist); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index a8d1abe20f62c..0db607f2a4105 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1042,6 +1042,24 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); +/** + * @get_3dlut_fast_load_status: + * + * Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id + * - [in/out] done + * - [in/out] soft_underflow + * - [in/out] hard_underflow + * + * Return: + * + * void + */ + void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); + /** * @populate_lut: * diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 671ab1fc73207..2f70bb476c97b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -518,6 +518,8 @@ struct timing_generator_funcs { bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state); + void (*enable_otg_pwa)(struct timing_generator *tg, struct otc_pwa_frame_sync *pwa_param); + void (*disable_otg_pwa)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index b5e14d7923784..807b73c2a758b 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -198,3 +198,12 @@ IRQ_DCN401 = irq_service_dcn401.o AMD_DAL_IRQ_DCN401= $(addprefix $(AMDDALPATH)/dc/irq/dcn401/,$(IRQ_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN401) + +############################################################################### +# DCN 42 +############################################################################### +IRQ_DCN42 = irq_service_dcn42.o + +AMD_DAL_IRQ_DCN42= $(addprefix $(AMDDALPATH)/dc/irq/dcn42/,$(IRQ_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN42) diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile index 2d4b7a85847de..afc376defa0b0 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -52,3 +52,11 @@ AMD_DAL_MMHUBBUB_DCN35 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn35/,$(MMHUBBUB AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN35) endif +############################################################################### +# DCN42 +############################################################################### +MMHUBBUB_DCN42 = dcn42_mmhubbub.o + +AMD_DAL_MMHUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn42/,$(MMHUBBUB_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN42) diff --git a/drivers/gpu/drm/amd/display/dc/mpc/Makefile b/drivers/gpu/drm/amd/display/dc/mpc/Makefile index 5402c3529f5ee..cc23aae3728a1 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/mpc/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -69,4 +69,12 @@ AMD_DAL_MPC_DCN401 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn401/,$(MPC_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN401) +############################################################################### +# DCN42 +############################################################################### +MPC_DCN42 = dcn42_mpc.o + +AMD_DAL_MPC_DCN42 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn42/,$(MPC_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index eeac13fdd6f55..ce1ee2062e41d 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 Advanced Micro Devices, Inc. + * Copyright 2023-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -47,6 +47,16 @@ void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx); } +void mpc401_get_3dlut_fast_load_status(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow) +{ + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + REG_GET_3(MPCC_MCM_3DLUT_FAST_LOAD_STATUS[mpcc_id], + MPCC_MCM_3DLUT_FL_DONE, done, + MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, soft_underflow, + MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, hard_underflow); +} + void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id) { struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); @@ -602,6 +612,7 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .set_bg_color = mpc1_set_bg_color, .set_movable_cm_location = mpc401_set_movable_cm_location, .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select, + .get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status, .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h index fdc42f8ab3ff5..6d842d7b95c7e 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 Advanced Micro Devices, Inc. + * Copyright 2023-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -184,6 +184,7 @@ struct dcn401_mpc_mask { struct dcn401_mpc_registers { MPC_REG_VARIABLE_LIST_DCN4_01 + uint32_t MPCC_CONTROL2[MAX_MPCC]; }; struct dcn401_mpc { @@ -249,6 +250,13 @@ void mpc_read_gamut_remap(struct mpc *mpc, enum mpcc_gamut_remap_id gamut_remap_block_id, uint32_t *mode_select); +void mpc401_get_3dlut_fast_load_status( + struct mpc *mpc, + int mpcc_id, + uint32_t *done, + uint32_t *soft_underflow, + uint32_t *hard_underflow); + void mpc401_update_3dlut_fast_load_select( struct mpc *mpc, int mpcc_id, diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile index 29fb610c8660f..06c98d70eabcc 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/optc/Makefile @@ -104,11 +104,19 @@ AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35) ############################################################################### -############################################################################### OPTC_DCN401 = dcn401_optc.o AMD_DAL_OPTC_DCN401 = $(addprefix $(AMDDALPATH)/dc/optc/dcn401/,$(OPTC_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN401) + +############################################################################### + +OPTC_DCN42 = dcn42_optc.o + +AMD_DAL_OPTC_DCN42 = $(addprefix $(AMDDALPATH)/dc/optc/dcn42/,$(OPTC_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 0b3f974f452e5..cf05620fd8f53 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -253,8 +253,20 @@ uint32_t OTG_CRC1_DATA_B32 +#define OPTC_REG_VARIABLE_LIST_DCN42 \ + uint32_t OTG_PWA_FRAME_SYNC_CONTROL; \ + uint32_t OTG_CRC0_DATA_R; \ + uint32_t OTG_CRC1_DATA_R; \ + uint32_t OTG_CRC2_DATA_R; \ + uint32_t OTG_CRC3_DATA_R; \ + uint32_t OTG_CRC0_DATA_G; \ + uint32_t OTG_CRC1_DATA_G; \ + uint32_t OTG_CRC2_DATA_G; \ + uint32_t OTG_CRC3_DATA_G + struct dcn_optc_registers { OPTC_REG_VARIABLE_LIST_DCN; + OPTC_REG_VARIABLE_LIST_DCN42; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -679,6 +691,10 @@ struct dcn_optc_registers { type OTG_UNBLANK;\ type OTG_PSTATE_ALLOW_WIDTH_MIN; +#define TG_REG_FIELD_LIST_DCN42(type) \ + type OTG_PWA_FRAME_SYNC_EN;\ + type OTG_PWA_FRAME_SYNC_VCOUNT_MODE;\ + type OTG_PWA_FRAME_SYNC_LINE; struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) @@ -687,6 +703,7 @@ struct dcn_optc_shift { TG_REG_FIELD_LIST_DCN3_5(uint8_t) TG_REG_FIELD_LIST_DCN3_6(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) + TG_REG_FIELD_LIST_DCN42(uint8_t) }; struct dcn_optc_mask { @@ -696,6 +713,7 @@ struct dcn_optc_mask { TG_REG_FIELD_LIST_DCN3_5(uint32_t) TG_REG_FIELD_LIST_DCN3_6(uint32_t) TG_REG_FIELD_LIST_DCN401(uint32_t) + TG_REG_FIELD_LIST_DCN42(uint32_t) }; void dcn10_timing_generator_init(struct optc *optc); diff --git a/drivers/gpu/drm/amd/display/dc/pg/Makefile b/drivers/gpu/drm/amd/display/dc/pg/Makefile index ec11d3157a57f..56f610cc84065 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/Makefile +++ b/drivers/gpu/drm/amd/display/dc/pg/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020, 2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -32,4 +32,12 @@ PG_DCN35 = dcn35_pg_cntl.o AMD_DAL_PG_DCN35 = $(addprefix $(AMDDALPATH)/dc/pg/dcn35/,$(PG_DCN35)) AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN35) +############################################################################### +# DCN42 +############################################################################### +PG_DCN42 = dcn42_pg_cntl.o + +AMD_DAL_PG_DCN42 = $(addprefix $(AMDDALPATH)/dc/pg/dcn42/,$(PG_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/resource/Makefile b/drivers/gpu/drm/amd/display/dc/resource/Makefile index 5b42da8b79c2e..1a17a885fe84b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/Makefile +++ b/drivers/gpu/drm/amd/display/dc/resource/Makefile @@ -222,4 +222,22 @@ AMD_DAL_RESOURCE_DCN401 = $(addprefix $(AMDDALPATH)/dc/resource/dcn401/,$(RESOUR AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN401) +############################################################################### +# DCN42 +############################################################################### +RESOURCE_DCN42 = dcn42_resource.o dcn42_resource_fpu.o + +AMD_DAL_RESOURCE_DCN42 = $(addprefix $(AMDDALPATH)/dc/resource/dcn42/,$(RESOURCE_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN42) + +# FPU Compile Flags for FPU files +resource_ccflags := $(CC_FLAGS_FPU) +resource_rcflags := $(CC_FLAGS_NO_FPU) + +CFLAGS_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_ccflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_rcflags) + +############################################################################### endif + From 8f170f401b1921e944456f2b42acd7d5178e2478 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 2 Feb 2026 19:45:35 -0500 Subject: [PATCH 0232/2070] drm/amd/display: Enable dcn42 in DM Add support for DCN 4.2 in Display Manager Signed-off-by: Roman Li Acked-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 ++++++++++++++++--- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 06200d0ea805c..1c53c904b832f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -152,6 +152,9 @@ MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB); #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); +#define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB); + /** * DOC: overview * @@ -1365,6 +1368,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) case IP_VERSION(3, 5, 0): case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): + case IP_VERSION(4, 2, 0): hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; hw_params.lower_hbr3_phy_ssc = true; break; @@ -1812,6 +1816,9 @@ static void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) case IP_VERSION(4, 0, 1): bb_size = sizeof(struct dml2_soc_bb); break; + case IP_VERSION(4, 2, 0): + bb_size = sizeof(struct dml2_soc_bb); + break; default: return NULL; } @@ -1856,6 +1863,9 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( case IP_VERSION(3, 5, 1): ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; break; + case IP_VERSION(4, 2, 0): + ret = DMUB_IPS_DISABLE_ALL; + break; default: /* ASICs older than DCN35 do not have IPSs */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0)) @@ -1999,6 +2009,13 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) init_data.num_virtual_links = 1; + /* DCN42 and above dpia switch to unified link training path */ + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { + init_data.flags.consolidated_dpia_dp_lt = true; + init_data.flags.enable_dpia_pre_training = true; + init_data.flags.unify_link_enc_assignment = true; + init_data.flags.usb4_bw_alloc_support = true; + } retrieve_dmi_info(&adev->dm); if (adev->dm.edp0_on_dp1_quirk) init_data.flags.support_edp0_on_dp1 = true; @@ -2366,6 +2383,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): return 0; default: break; @@ -2499,7 +2517,9 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) case IP_VERSION(4, 0, 1): dmub_asic = DMUB_ASIC_DCN401; break; - + case IP_VERSION(4, 2, 0): + dmub_asic = DMUB_ASIC_DCN42; + break; default: /* ASIC doesn't support DMUB. */ return 0; @@ -5448,6 +5468,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): if (register_outbox_irq_handlers(dm->adev)) { drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); goto fail; @@ -5472,6 +5493,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): psr_feature_enabled = true; break; default: @@ -5649,6 +5671,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): if (dcn10_register_irq_handlers(dm->adev)) { drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); goto fail; @@ -5797,6 +5820,9 @@ static int dm_init_microcode(struct amdgpu_device *adev) case IP_VERSION(4, 0, 1): fw_name_dmub = FIRMWARE_DCN_401_DMUB; break; + case IP_VERSION(4, 2, 0): + fw_name_dmub = FIRMWARE_DCN_42_DMUB; + break; default: /* ASIC doesn't support DMUB. */ return 0; @@ -5924,6 +5950,7 @@ static int dm_early_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): adev->mode_info.num_crtc = 4; adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; @@ -12222,10 +12249,11 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, int i; /* Overlay cursor not supported on HW before DCN - * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions - * as previous DCN generations, so enable native mode on DCN401 + * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions + * as previous DCN generations, so enable native mode on DCN401/420 */ - if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || + amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0)) { *cursor_mode = DM_CURSOR_NATIVE_MODE; return 0; } @@ -12645,7 +12673,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, /* Check if rotation or scaling is enabled on DCN401 */ if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && - amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { + (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || + amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); is_rotated = new_cursor_state && diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 198064acf9f6f..091fa7c151f58 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright 2022 Advanced Micro Devices, Inc. + * Copyright 2022-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -759,6 +759,7 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig case AMDGPU_FAMILY_GC_11_0_0: case AMDGPU_FAMILY_GC_11_0_1: case AMDGPU_FAMILY_GC_11_5_0: + case AMDGPU_FAMILY_GC_11_5_4: amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); break; case AMDGPU_FAMILY_GC_12_0_0: From 90ff4995a47c3285b1d1858fbcdafcd55801f5f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 2 Feb 2026 12:25:03 +0100 Subject: [PATCH 0233/2070] drm/amd/display: Don't call find_analog_engine() twice MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The analog engine is already there in the link_analog_engine variable and assigned to enc_init_data.analog_engine already. I suspect this was a rebase mistake. Fixes: 740aa093701c ("drm/amd/display: Pass proper DAC encoder ID to VBIOS") Signed-off-by: Timur Kristóf Tested-by: Mauro Rossi Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/link/link_factory.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 7b84bf2e845bc..9912615d742f8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -580,7 +580,6 @@ static bool construct_phy(struct dc_link *link, enc_init_data.connector = link->link_id; enc_init_data.channel = get_ddc_line(link); enc_init_data.transmitter = transmitter_from_encoder; - enc_init_data.analog_engine = find_analog_engine(link, &enc_init_data.analog_encoder); enc_init_data.encoder = link_encoder; enc_init_data.analog_engine = link_analog_engine; if (link->ctx->dce_version <= DCN_VERSION_4_01) From b4deb823fab4f6250247a22518ebe95d1324d87a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 2 Feb 2026 12:25:04 +0100 Subject: [PATCH 0234/2070] drm/amd/display: Turn off DAC in DCE link encoder using VBIOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apparently, the VBIOS DAC1EncoderControl function is much more graceful about turning off the DAC. It writes various DAC registers in a specific sequence. Use that instead of just clearing the DAC_ENABLE register. Do this in just the dce110_link_encoder_disable_output function and remove it from the HWSS. Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)") Signed-off-by: Timur Kristóf Tested-by: Mauro Rossi Suggested-by: Alex Deucher Reviewed-by: Alex Hung --- .../drm/amd/display/dc/dce/dce_link_encoder.c | 30 +++++++++++-------- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 3 -- 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 7f0766b5fa3d5..f8fcf8d1a4dd6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -133,6 +133,21 @@ static enum bp_result link_transmitter_control( return result; } +static enum bp_result link_dac_encoder_control( + struct dce110_link_encoder *link_enc, + enum bp_encoder_control_action action, + uint32_t pix_clk_100hz) +{ + struct dc_bios *bios = link_enc->base.ctx->dc_bios; + struct bp_encoder_control encoder_control = {0}; + + encoder_control.action = action; + encoder_control.engine_id = link_enc->base.analog_engine; + encoder_control.pixel_clock = pix_clk_100hz / 10; + + return bios->funcs->encoder_control(bios, &encoder_control); +} + static void enable_phy_bypass_mode( struct dce110_link_encoder *enc110, bool enable) @@ -1345,19 +1360,8 @@ void dce110_link_encoder_disable_output( struct bp_transmitter_control cntl = { 0 }; enum bp_result result; - switch (enc->analog_engine) { - case ENGINE_ID_DACA: - REG_UPDATE(DAC_ENABLE, DAC_ENABLE, 0); - break; - case ENGINE_ID_DACB: - /* DACB doesn't seem to be present on DCE6+, - * although there are references to it in the register file. - */ - DC_LOG_ERROR("%s DACB is unsupported\n", __func__); - break; - default: - break; - } + if (enc->analog_engine != ENGINE_ID_UNKNOWN) + link_dac_encoder_control(enc110, ENCODER_CONTROL_DISABLE, 0); /* The code below only applies to connectors that support digital signals. */ if (enc->transmitter == TRANSMITTER_UNKNOWN) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 6e6430909bbaa..9ccad11821cd2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1257,9 +1257,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) link_enc->transmitter - TRANSMITTER_UNIPHY_A); } - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - dce110_dac_encoder_control(pipe_ctx, false); - if (link->ext_enc_id.id) dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL); } From e83d647191fb5bbd77321e87384fbb0b04826959 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 2 Feb 2026 12:25:05 +0100 Subject: [PATCH 0235/2070] drm/amd/display: Initialize DAC in DCE link encoder using VBIOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VBIOS DAC1EncoderControl() function can initialize the DAC, by writing board-specific values to certain registers. Call this at link encoder hardware initialization time similarly to how the equivalent UNIPHYTransmitterControl initialization is done. This fixes DAC output on the Radeon HD 7790. Also remove the ENCODER_CONTROL_SETUP enum from the dac_encoder_control_prepare_params function which is actually not a supported operation for DAC encoders. Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)") Signed-off-by: Timur Kristóf Tested-by: Mauro Rossi Suggested-by: Alex Deucher Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/bios/command_table.c | 3 +-- drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index d2d59732d338b..f6e22dcecf29e 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -1825,8 +1825,7 @@ static void dac_encoder_control_prepare_params( uint8_t dac_standard) { params->ucDacStandard = dac_standard; - if (action == ENCODER_CONTROL_SETUP || - action == ENCODER_CONTROL_INIT) + if (action == ENCODER_CONTROL_INIT) params->ucAction = ATOM_ENCODER_INIT; else if (action == ENCODER_CONTROL_ENABLE) params->ucAction = ATOM_ENABLE; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index f8fcf8d1a4dd6..8903bdb89c661 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1036,6 +1036,16 @@ void dce110_link_encoder_hw_init( cntl.coherent = false; cntl.hpd_sel = enc110->base.hpd_source; + if (enc110->base.analog_engine != ENGINE_ID_UNKNOWN) { + result = link_dac_encoder_control(enc110, ENCODER_CONTROL_INIT, 0); + if (result != BP_RESULT_OK) { + DC_LOG_ERROR("%s: Failed to execute VBIOS command table for DAC!\n", + __func__); + BREAK_TO_DEBUGGER(); + return; + } + } + /* The code below is only applicable to encoders with a digital transmitter. */ if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) return; From d07d24a0bfb44ceb10b7b33ecfccd468979348f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 2 Feb 2026 12:25:06 +0100 Subject: [PATCH 0236/2070] drm/amd/display: Set CRTC source for DAC using registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apparently the VBIOS SelectCRTC_Source function overwrites a few registers (such as FMT_*) which DC writes in a different place, which can cause problems. Instead of using the SelectCRTC_Source function from the VBIOS, use the DAC_SOURCE_SELECT register directly, similarly to how it is done for digital link encoders. Fixes: 3be26d81b150 ("drm/amd/display: Support DAC in dce110_hwseq") Signed-off-by: Timur Kristóf Tested-by: Mauro Rossi Reviewed-by: Alex Hung --- .../amd/display/dc/dce/dce_stream_encoder.c | 23 +++++++++++++--- .../amd/display/dc/dce/dce_stream_encoder.h | 12 +++++++-- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 26 +------------------ .../dc/resource/dce100/dce100_resource.c | 6 +++-- .../dc/resource/dce60/dce60_resource.c | 7 +++-- .../dc/resource/dce80/dce80_resource.c | 6 +++-- 6 files changed, 43 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 574618d5d4a4e..87c19f17c799f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -1498,7 +1498,10 @@ static void dig_connect_to_otg( { struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); - REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); + if (enc->id == ENGINE_ID_DACA || enc->id == ENGINE_ID_DACB) + REG_UPDATE(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, tg_inst); + else + REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); } static unsigned int dig_source_otg( @@ -1507,7 +1510,10 @@ static unsigned int dig_source_otg( uint32_t tg_inst = 0; struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); - REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); + if (enc->id == ENGINE_ID_DACA || enc->id == ENGINE_ID_DACB) + REG_GET(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, &tg_inst); + else + REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); return tg_inst; } @@ -1568,16 +1574,25 @@ void dce110_stream_encoder_construct( enc110->se_mask = se_mask; } -static const struct stream_encoder_funcs dce110_an_str_enc_funcs = {}; +static const struct stream_encoder_funcs dce110_an_str_enc_funcs = { + .dig_connect_to_otg = dig_connect_to_otg, + .dig_source_otg = dig_source_otg, +}; void dce110_analog_stream_encoder_construct( struct dce110_stream_encoder *enc110, struct dc_context *ctx, struct dc_bios *bp, - enum engine_id eng_id) + enum engine_id eng_id, + const struct dce110_stream_enc_registers *regs, + const struct dce_stream_encoder_shift *se_shift, + const struct dce_stream_encoder_mask *se_mask) { enc110->base.funcs = &dce110_an_str_enc_funcs; enc110->base.ctx = ctx; enc110->base.id = eng_id; enc110->base.bp = bp; + enc110->regs = regs; + enc110->se_shift = se_shift; + enc110->se_mask = se_mask; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index 068de1392121e..342c0afe6a949 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -65,6 +65,7 @@ SRI(AFMT_60958_1, DIG, id), \ SRI(AFMT_60958_2, DIG, id), \ SRI(DIG_FE_CNTL, DIG, id), \ + SR(DAC_SOURCE_SELECT), \ SRI(HDMI_CONTROL, DIG, id), \ SRI(HDMI_GC, DIG, id), \ SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ @@ -290,7 +291,8 @@ #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ - SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh) + SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, mask_sh) #define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ @@ -494,6 +496,7 @@ struct dce_stream_encoder_shift { uint8_t DP_VID_N_MUL; uint8_t DP_VID_M_DOUBLE_VALUE_EN; uint8_t DIG_SOURCE_SELECT; + uint8_t DAC_SOURCE_SELECT; }; struct dce_stream_encoder_mask { @@ -626,6 +629,7 @@ struct dce_stream_encoder_mask { uint32_t DP_VID_N_MUL; uint32_t DP_VID_M_DOUBLE_VALUE_EN; uint32_t DIG_SOURCE_SELECT; + uint32_t DAC_SOURCE_SELECT; }; struct dce110_stream_enc_registers { @@ -653,6 +657,7 @@ struct dce110_stream_enc_registers { uint32_t AFMT_60958_1; uint32_t AFMT_60958_2; uint32_t DIG_FE_CNTL; + uint32_t DAC_SOURCE_SELECT; uint32_t DP_MSE_RATE_CNTL; uint32_t DP_MSE_RATE_UPDATE; uint32_t DP_PIXEL_FORMAT; @@ -712,7 +717,10 @@ void dce110_analog_stream_encoder_construct( struct dce110_stream_encoder *enc110, struct dc_context *ctx, struct dc_bios *bp, - enum engine_id eng_id); + enum engine_id eng_id, + const struct dce110_stream_enc_registers *regs, + const struct dce_stream_encoder_shift *se_shift, + const struct dce_stream_encoder_mask *se_mask); void dce110_se_audio_mute_control( struct stream_encoder *enc, bool mute); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 9ccad11821cd2..9513aa1c85277 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1641,25 +1641,6 @@ static enum dc_status dce110_enable_stream_timing( return DC_OK; } -static void -dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) -{ - struct dc_link *link = pipe_ctx->stream->link; - struct dc_bios *bios = link->ctx->dc_bios; - struct bp_crtc_source_select crtc_source_select = {0}; - enum engine_id engine_id = link->link_enc->preferred_engine; - - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - engine_id = link->link_enc->analog_engine; - - crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; - crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth; - crtc_source_select.engine_id = engine_id; - crtc_source_select.sink_signal = pipe_ctx->stream->signal; - - bios->funcs->select_crtc_source(bios, &crtc_source_select); -} - enum dc_status dce110_apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, struct dc_state *context, @@ -1679,10 +1660,6 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( hws->funcs.disable_stream_gating(dc, pipe_ctx); } - if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) { - dce110_select_crtc_source(pipe_ctx); - } - if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output = {0}; @@ -1762,8 +1739,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx->stream_res.tg, event_triggers, 2); - if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && - !dc_is_rgb_signal(pipe_ctx->stream->signal)) + if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.tg->inst); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index f49d67fcafe0a..dfb64905e1a46 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -242,7 +242,8 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(3), stream_enc_regs(4), stream_enc_regs(5), - stream_enc_regs(6) + stream_enc_regs(6), + {SR(DAC_SOURCE_SELECT),} /* DACA */ }; static const struct dce_stream_encoder_shift se_shift = { @@ -491,7 +492,8 @@ static struct stream_encoder *dce100_stream_encoder_create( return NULL; if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { - dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index d06d4645ab6f1..702732ed6a738 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -258,7 +258,9 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(2), stream_enc_regs(3), stream_enc_regs(4), - stream_enc_regs(5) + stream_enc_regs(5), + {0}, + {SR(DAC_SOURCE_SELECT),} /* DACA */ }; static const struct dce_stream_encoder_shift se_shift = { @@ -607,7 +609,8 @@ static struct stream_encoder *dce60_stream_encoder_create( return NULL; if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { - dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index cde2c2cba1dd6..066dbf8125a87 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -258,7 +258,8 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(3), stream_enc_regs(4), stream_enc_regs(5), - stream_enc_regs(6) + stream_enc_regs(6), + {SR(DAC_SOURCE_SELECT),} /* DACA */ }; static const struct dce_stream_encoder_shift se_shift = { @@ -614,7 +615,8 @@ static struct stream_encoder *dce80_stream_encoder_create( return NULL; if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { - dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; } From 2c0d5a7c37ff835b5acd12e42599a3495a393c97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 2 Feb 2026 12:25:07 +0100 Subject: [PATCH 0237/2070] drm/amd/display: Enable DAC in DCE link encoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ensure that the DAC output is enabled at the correct time by moving it to the DCE link encoder similarly to how digital outputs are enabled. This also removes the call to DAC1EncoderControl from the DCE HWSS, which always felt like it was a hacky solution. Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)") Signed-off-by: Timur Kristóf Tested-by: Mauro Rossi Reviewed-by: Alex Hung --- .../drm/amd/display/dc/dce/dce_link_encoder.c | 18 +++++++++++++ .../drm/amd/display/dc/dce/dce_link_encoder.h | 5 ++++ .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 27 +++++++------------ .../drm/amd/display/dc/hwss/hw_sequencer.h | 2 ++ .../drm/amd/display/dc/inc/hw/link_encoder.h | 2 ++ .../gpu/drm/amd/display/dc/link/link_dpms.c | 14 +++++++++- 6 files changed, 50 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 8903bdb89c661..2ba3d3a3aac58 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -102,6 +102,7 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .enable_dp_output = dce110_link_encoder_enable_dp_output, .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, .disable_output = dce110_link_encoder_disable_output, .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, @@ -1200,6 +1201,22 @@ void dce110_link_encoder_enable_lvds_output( } } +void dce110_link_encoder_enable_analog_output( + struct link_encoder *enc, + uint32_t pixel_clock) +{ + struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); + enum bp_result result; + + result = link_dac_encoder_control(enc110, ENCODER_CONTROL_ENABLE, pixel_clock); + + if (result != BP_RESULT_OK) { + DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", + __func__); + BREAK_TO_DEBUGGER(); + } +} + /* enables DP PHY output */ void dce110_link_encoder_enable_dp_output( struct link_encoder *enc, @@ -1818,6 +1835,7 @@ static const struct link_encoder_funcs dce60_lnk_enc_funcs = { .enable_dp_output = dce60_link_encoder_enable_dp_output, .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, .disable_output = dce110_link_encoder_disable_output, .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 9ba533aa6f88c..f853e3c3fc755 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -268,6 +268,11 @@ void dce110_link_encoder_enable_lvds_output( enum clock_source_id clock_source, uint32_t pixel_clock); +/* enables analog output from the DAC */ +void dce110_link_encoder_enable_analog_output( + struct link_encoder *enc, + uint32_t pixel_clock); + /* disable PHY output */ void dce110_link_encoder_disable_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 9513aa1c85277..8aafd460c36fd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -702,20 +702,6 @@ dce110_prepare_ddc(struct dc_link *link) dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL); } -static void -dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) -{ - struct dc_link *link = pipe_ctx->stream->link; - struct dc_bios *bios = link->ctx->dc_bios; - struct bp_encoder_control encoder_control = {0}; - - encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; - encoder_control.engine_id = link->link_enc->analog_engine; - encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; - - bios->funcs->encoder_control(bios, &encoder_control); -} - static bool dce110_dac_load_detect(struct dc_link *link) { @@ -758,9 +744,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) tg->funcs->set_early_control(tg, early_control); - if (dc_is_rgb_signal(pipe_ctx->stream->signal)) - dce110_dac_encoder_control(pipe_ctx, true); - if (link->ext_enc_id.id) dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing); } @@ -3337,6 +3320,15 @@ void dce110_enable_tmds_link_output(struct dc_link *link, link->phy_state.symclk_state = SYMCLK_ON_TX_ON; } +static void dce110_enable_analog_link_output( + struct dc_link *link, + uint32_t pix_clk_100hz) +{ + link->link_enc->funcs->enable_analog_output( + link->link_enc, + pix_clk_100hz); +} + void dce110_enable_dp_link_output( struct dc_link *link, const struct link_resource *link_res, @@ -3479,6 +3471,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, + .enable_analog_link_output = dce110_enable_analog_link_output, .disable_link_output = dce110_disable_link_output, .dac_load_detect = dce110_dac_load_detect, .prepare_ddc = dce110_prepare_ddc, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index bd6101f712168..d699640ba5b45 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1192,6 +1192,8 @@ struct hw_sequencer_funcs { const struct link_resource *link_res, enum clock_source_id clock_source, uint32_t pixel_clock); + void (*enable_analog_link_output)(struct dc_link *link, + uint32_t pixel_clock); void (*disable_link_output)(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index d795fc43dc9d9..5abbf485d273e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -132,6 +132,8 @@ struct link_encoder_funcs { void (*enable_lvds_output)(struct link_encoder *enc, enum clock_source_id clock_source, uint32_t pixel_clock); + void (*enable_analog_output)(struct link_encoder *enc, + uint32_t pixel_clock); void (*disable_output)(struct link_encoder *link_enc, enum signal_type signal); void (*dp_set_lane_settings)(struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 89c916dbf6575..b4f46408a0005 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2015,6 +2015,18 @@ static enum dc_status enable_link_dp_mst( return enable_link_dp(state, pipe_ctx); } +static enum dc_status enable_link_analog( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) +{ + struct dc_link *link = pipe_ctx->stream->link; + + link->dc->hwss.enable_analog_link_output( + link, pipe_ctx->stream->timing.pix_clk_100hz); + + return DC_OK; +} + static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) { struct dc_link *link = pipe_ctx->stream->link; @@ -2070,7 +2082,7 @@ static enum dc_status enable_link( status = DC_OK; break; case SIGNAL_TYPE_RGB: - status = DC_OK; + status = enable_link_analog(state, pipe_ctx); break; case SIGNAL_TYPE_VIRTUAL: status = enable_link_virtual(pipe_ctx); From f98e964fbb8b7a1975a6a5f42a71fca1c309945e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 2 Feb 2026 12:25:08 +0100 Subject: [PATCH 0238/2070] drm/amd/display: Remove unneeded DAC link encoder register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not needed anymore since we use the VBIOS function. Signed-off-by: Timur Kristóf Tested-by: Mauro Rossi Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 3 +-- .../gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index f853e3c3fc755..8841000361fb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -101,8 +101,7 @@ SRI(DP_SEC_CNTL, DP, id), \ SRI(DP_VID_STREAM_CNTL, DP, id), \ SRI(DP_DPHY_FAST_TRAINING, DP, id), \ - SRI(DP_SEC_CNTL1, DP, id), \ - SR(DAC_ENABLE) + SRI(DP_SEC_CNTL1, DP, id) #endif #define LE_DCE80_REG_LIST(id)\ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index dfb64905e1a46..05f7ff60f8f5a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -226,7 +226,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), link_regs(6), - { .DAC_ENABLE = mmDAC_ENABLE }, + {0} }; #define stream_enc_regs(id)\ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 702732ed6a738..d41d24b76c11f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -243,7 +243,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), {0}, - { .DAC_ENABLE = mmDAC_ENABLE }, + {0} }; #define stream_enc_regs(id)\ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 066dbf8125a87..a68e799d58854 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -242,7 +242,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), link_regs(6), - { .DAC_ENABLE = mmDAC_ENABLE }, + {0} }; #define stream_enc_regs(id)\ From 47ac136f4ed124f442df347d10a96e6f7ec9457b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 11 Feb 2026 13:28:55 +0100 Subject: [PATCH 0239/2070] drm/amdgpu: fix 4-level paging if GMC supports 57-bit VA v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It turned that using 4 level page tables on GMC generations which support 57bit VAs actually doesn't work at all. Background is that the GMC actually can't switch between 4 and 5 levels, but rather just uses a subset of address space when less than 5 levels are selected. Philip already removed the automatically switch to 4levels, now fix it as well should it be enabled by module parameters. v2: fix AMDGPU_GMC_HOLE_MASK as well, fix off by one issue pointed out by Philip Signed-off-by: Christian König Acked-by: Alex Deucher Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index e8e8bfa098c3e..0e8a52d965738 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -33,9 +33,9 @@ #include "amdgpu_ras.h" /* VA hole for 48bit and 57bit addresses */ -#define AMDGPU_GMC_HOLE_START (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\ +#define AMDGPU_GMC_HOLE_START (adev->vm_manager.max_level == 4 ?\ 0x0100000000000000ULL : 0x0000800000000000ULL) -#define AMDGPU_GMC_HOLE_END (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\ +#define AMDGPU_GMC_HOLE_END (adev->vm_manager.max_level == 4 ?\ 0xff00000000000000ULL : 0xffff800000000000ULL) /* @@ -45,8 +45,8 @@ * This mask is used to remove the upper 16bits of the VA and so come up with * the linear addr value. */ -#define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\ - 0x00ffffffffffffffULL : 0x0000ffffffffffffULL) +#define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.max_level == 4 ?\ + 0x01ffffffffffffffULL : 0x0000ffffffffffffULL) /* * Ring size as power of two for the log of recent faults. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 57f87ce5e9297..01fef0e4f4085 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2404,6 +2404,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, } adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; + adev->vm_manager.max_level = max_level; tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); if (amdgpu_vm_block_size != -1) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 322193b97d3cc..dc4b0ec672ec0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -456,6 +456,7 @@ struct amdgpu_vm_manager { bool concurrent_flush; uint64_t max_pfn; + uint32_t max_level; uint32_t num_level; uint32_t block_size; uint32_t fragment_size; From 57e05659529b4f6bcc9e3ea6ae3b21572a9b970e Mon Sep 17 00:00:00 2001 From: Roman Li Date: Wed, 18 Feb 2026 10:29:46 -0500 Subject: [PATCH 0240/2070] drm/amdgpu/discovery: Enable DM for DCN42 Add DM ipblock for DCN 4.2.0 Signed-off-by: Roman Li Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index fc8c1f36be580..2f032a7d8e82b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2301,6 +2301,7 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 1, 0): + case IP_VERSION(4, 2, 0): /* TODO: Fix IP version. DC code expects version 4.0.1 */ if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); From da9fa87ff567cbad48700538bee23938dc163c78 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jan 2026 22:01:15 -0500 Subject: [PATCH 0241/2070] drm/amdgpu: rework ring reset backup and reemit v9 Store the start wptr and ib size in the IB fence. On queue reset, save the ring contents of all IBs. For reemit, reemit the entire IB state for non-guilty contexts. For guilty contexts, replace the IB submission with nops, but reemit the rest. Split the reemit per fence and when we reemit, update the wptr with the new values from reemit. This allows us to reemit jobs repeatedly as the wptrs get properly updated each time. v2: further simplify the logic v3: reemit vm state, not just vm fence v4: just nop the IB and possibly the VM portion of the submission v5: simplify the vm fence check v6: split the vm and ib fences v7: fix commit message v8: use wptr rather than count_dw to calculate offsets v9: fix missing documenation update spotted by the kernel test robot Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 99 +++++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 26 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 46 +++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 20 ++--- 4 files changed, 74 insertions(+), 117 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 07568516c5066..d209591e3710a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -89,16 +89,6 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring) return seq; } -static void amdgpu_fence_save_fence_wptr_start(struct amdgpu_fence *af) -{ - af->fence_wptr_start = af->ring->wptr; -} - -static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af) -{ - af->fence_wptr_end = af->ring->wptr; -} - /** * amdgpu_fence_emit - emit a fence on the requested ring * @@ -124,11 +114,9 @@ void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, &ring->fence_drv.lock, adev->fence_context + ring->idx, seq); - amdgpu_fence_save_fence_wptr_start(af); amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, seq, flags | AMDGPU_FENCE_FLAG_INT); - amdgpu_fence_save_fence_wptr_end(af); - amdgpu_fence_save_wptr(af); + pm_runtime_get_noresume(adev_to_drm(adev)->dev); ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; if (unlikely(rcu_dereference_protected(*ptr, 1))) { @@ -240,7 +228,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) do { struct dma_fence *fence, **ptr; - struct amdgpu_fence *am_fence; ++last_seq; last_seq &= drv->num_fences_mask; @@ -253,12 +240,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) if (!fence) continue; - /* Save the wptr in the fence driver so we know what the last processed - * wptr was. This is required for re-emitting the ring state for - * queues that are reset but are not guilty and thus have no guilty fence. - */ - am_fence = container_of(fence, struct amdgpu_fence, base); - drv->signalled_wptr = am_fence->wptr; dma_fence_signal(fence); dma_fence_put(fence); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -707,25 +688,29 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) */ /** - * amdgpu_fence_driver_update_timedout_fence_state - Update fence state and set errors + * amdgpu_ring_set_fence_errors_and_reemit - Set dma_fence errors and reemit * - * @af: fence of the ring to update + * @ring: the ring to operate on + * @guilty_fence: fence of the ring to update * */ -void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af) +void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring, + struct amdgpu_fence *guilty_fence) { struct dma_fence *unprocessed; struct dma_fence __rcu **ptr; struct amdgpu_fence *fence; - struct amdgpu_ring *ring = af->ring; unsigned long flags; u32 seq, last_seq; - bool reemitted = false; + unsigned int i; + bool is_guilty_fence; + bool is_guilty_context; last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; - /* mark all fences from the guilty context with an error */ + ring->reemit = true; + amdgpu_ring_alloc(ring, ring->ring_backup_entries_to_copy); spin_lock_irqsave(&ring->fence_drv.lock, flags); do { last_seq++; @@ -737,39 +722,45 @@ void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af) if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) { fence = container_of(unprocessed, struct amdgpu_fence, base); + is_guilty_fence = fence == guilty_fence; + is_guilty_context = fence->context == guilty_fence->context; - if (fence->reemitted > 1) - reemitted = true; - else if (fence == af) + /* mark all fences from the guilty context with an error */ + if (is_guilty_fence) dma_fence_set_error(&fence->base, -ETIME); - else if (fence->context == af->context) + else if (is_guilty_context) dma_fence_set_error(&fence->base, -ECANCELED); + + /* reemit the packet stream and update wptrs */ + fence->ib_wptr = ring->wptr; + for (i = 0; i < fence->ib_dw_size; i++) { + /* Skip the IB(s) for the guilty context. */ + if (is_guilty_context && + i >= fence->skip_ib_dw_start_offset && + i < fence->skip_ib_dw_end_offset) + amdgpu_ring_write(ring, ring->funcs->nop); + else + amdgpu_ring_write(ring, + ring->ring_backup[fence->backup_idx + i]); + } } rcu_read_unlock(); } while (last_seq != seq); spin_unlock_irqrestore(&ring->fence_drv.lock, flags); - - if (reemitted) { - /* if we've already reemitted once then just cancel everything */ - amdgpu_fence_driver_force_completion(af->ring); - af->ring->ring_backup_entries_to_copy = 0; - } -} - -void amdgpu_fence_save_wptr(struct amdgpu_fence *af) -{ - af->wptr = af->ring->wptr; + amdgpu_ring_commit(ring); + ring->reemit = false; } static void amdgpu_ring_backup_unprocessed_command(struct amdgpu_ring *ring, - u64 start_wptr, u64 end_wptr) + struct amdgpu_fence *af) { - unsigned int first_idx = start_wptr & ring->buf_mask; - unsigned int last_idx = end_wptr & ring->buf_mask; + unsigned int first_idx = af->ib_wptr & ring->buf_mask; + unsigned int dw_size = af->ib_dw_size; unsigned int i; + af->backup_idx = ring->ring_backup_entries_to_copy; /* Backup the contents of the ring buffer. */ - for (i = first_idx; i != last_idx; ++i, i &= ring->buf_mask) + for (i = first_idx; dw_size > 0; ++i, i &= ring->buf_mask, --dw_size) ring->ring_backup[ring->ring_backup_entries_to_copy++] = ring->ring[i]; } @@ -779,12 +770,10 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, struct dma_fence *unprocessed; struct dma_fence __rcu **ptr; struct amdgpu_fence *fence; - u64 wptr; u32 seq, last_seq; last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; - wptr = ring->fence_drv.signalled_wptr; ring->ring_backup_entries_to_copy = 0; do { @@ -798,21 +787,7 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, if (unprocessed && !dma_fence_is_signaled(unprocessed)) { fence = container_of(unprocessed, struct amdgpu_fence, base); - /* save everything if the ring is not guilty, otherwise - * just save the content from other contexts. - */ - if (!fence->reemitted && - (!guilty_fence || (fence->context != guilty_fence->context))) { - amdgpu_ring_backup_unprocessed_command(ring, wptr, - fence->wptr); - } else if (!fence->reemitted) { - /* always save the fence */ - amdgpu_ring_backup_unprocessed_command(ring, - fence->fence_wptr_start, - fence->fence_wptr_end); - } - wptr = fence->wptr; - fence->reemitted++; + amdgpu_ring_backup_unprocessed_command(ring, fence); } rcu_read_unlock(); } while (last_seq != seq); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index eb92c96d290b6..f1ed4a436f5b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -129,6 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, struct amdgpu_ib *ib = &ibs[0]; struct dma_fence *tmp = NULL; struct amdgpu_fence *af; + struct amdgpu_fence *vm_af; bool need_ctx_switch; struct amdgpu_vm *vm; uint64_t fence_ctx; @@ -215,9 +216,17 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, dma_fence_put(tmp); } - if (job) + if (job) { + vm_af = job->hw_vm_fence; + /* VM sequence */ + vm_af->ib_wptr = ring->wptr; amdgpu_vm_flush(ring, job, need_pipe_sync); + vm_af->ib_dw_size = + amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr); + } + /* IB sequence */ + af->ib_wptr = ring->wptr; amdgpu_ring_ib_begin(ring); if (ring->funcs->insert_start) @@ -238,6 +247,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, cond_exec = amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); + /* Skip the IB for guilty contexts */ + af->skip_ib_dw_start_offset = + amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); amdgpu_device_flush_hdp(adev, ring); if (need_ctx_switch) @@ -276,6 +288,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_emit_frame_cntl(ring, false, secure); amdgpu_device_invalidate_hdp(adev, ring); + /* Skip the IB for guilty contexts */ + af->skip_ib_dw_end_offset = + amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; @@ -312,13 +327,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, ring->funcs->emit_wave_limit(ring, false); amdgpu_ring_ib_end(ring); - /* Save the wptr associated with this fence. - * This must be last for resets to work properly - * as we need to save the wptr associated with this - * fence so we know what rings contents to backup - * after we reset the queue. - */ - amdgpu_fence_save_wptr(af); + + af->ib_dw_size = amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); amdgpu_ring_commit(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 129ad51386535..83750ab4e81b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -90,10 +90,13 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; /* Make sure we aren't trying to allocate more space - * than the maximum for one submission + * than the maximum for one submission. Skip for reemit + * since we may be reemitting several submissions. */ - if (WARN_ON_ONCE(ndw > ring->max_dw)) - return -ENOMEM; + if (!ring->reemit) { + if (WARN_ON_ONCE(ndw > ring->max_dw)) + return -ENOMEM; + } ring->count_dw = ndw; ring->wptr_old = ring->wptr; @@ -104,29 +107,6 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) return 0; } -/** - * amdgpu_ring_alloc_reemit - allocate space on the ring buffer for reemit - * - * @ring: amdgpu_ring structure holding ring information - * @ndw: number of dwords to allocate in the ring buffer - * - * Allocate @ndw dwords in the ring buffer (all asics). - * doesn't check the max_dw limit as we may be reemitting - * several submissions. - */ -static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw) -{ - /* Align requested size with padding so unlock_commit can - * pad safely */ - ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; - - ring->count_dw = ndw; - ring->wptr_old = ring->wptr; - - if (ring->funcs->begin_use) - ring->funcs->begin_use(ring); -} - /** * amdgpu_ring_insert_nop - insert NOP packets * @@ -875,7 +855,6 @@ void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence) { - unsigned int i; int r; /* verify that the ring is functional */ @@ -883,16 +862,9 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, if (r) return r; - /* set an error on all fences from the context */ - if (guilty_fence) - amdgpu_fence_driver_update_timedout_fence_state(guilty_fence); - /* Re-emit the non-guilty commands */ - if (ring->ring_backup_entries_to_copy) { - amdgpu_ring_alloc_reemit(ring, ring->ring_backup_entries_to_copy); - for (i = 0; i < ring->ring_backup_entries_to_copy; i++) - amdgpu_ring_write(ring, ring->ring_backup[i]); - amdgpu_ring_commit(ring); - } + /* set an error on all fences from the context and reemit */ + amdgpu_ring_set_fence_errors_and_reemit(ring, guilty_fence); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 5a82db0888f0a..ce5af137ee400 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -121,7 +121,6 @@ struct amdgpu_fence_driver { /* sync_seq is protected by ring emission lock */ uint32_t sync_seq; atomic_t last_seq; - u64 signalled_wptr; bool initialized; struct amdgpu_irq_src *irq_src; unsigned irq_type; @@ -146,23 +145,23 @@ struct amdgpu_fence { struct amdgpu_ring *ring; ktime_t start_timestamp; - /* wptr for the total submission for resets */ - u64 wptr; + /* location and size of the IB */ + u64 ib_wptr; + unsigned int ib_dw_size; + unsigned int skip_ib_dw_start_offset; + unsigned int skip_ib_dw_end_offset; /* fence context for resets */ u64 context; - /* has this fence been reemitted */ - unsigned int reemitted; - /* wptr for the fence for the submission */ - u64 fence_wptr_start; - u64 fence_wptr_end; + /* idx for ring backups */ + unsigned int backup_idx; }; extern const struct drm_sched_backend_ops amdgpu_sched_ops; void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); -void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af); -void amdgpu_fence_save_wptr(struct amdgpu_fence *af); +void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring, + struct amdgpu_fence *guilty_fence); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, @@ -313,6 +312,7 @@ struct amdgpu_ring { /* backups for resets */ uint32_t *ring_backup; unsigned int ring_backup_entries_to_copy; + bool reemit; unsigned rptr_offs; u64 rptr_gpu_addr; u32 *rptr_cpu_addr; From 08055a526507c1fed64aa497eced3dd98240563e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 18 Feb 2026 16:21:23 +0530 Subject: [PATCH 0242/2070] drm/amdgpu: Print full vbios info Add build number, version and date to the existing part number print. Example: [drm] ATOM BIOS: 113-PN000108-103, build: 00159017, ver: 022.040.003.043.000001, 2025/07/27 Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atom.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 371ee82a89126..cc5b6ea7f6d8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1462,8 +1462,6 @@ static void atom_get_vbios_pn(struct atom_context *ctx) ctx->vbios_pn[count] = 0; } - - drm_info(ctx->card->dev, "ATOM BIOS: %s\n", ctx->vbios_pn); } static void atom_get_vbios_version(struct atom_context *ctx) @@ -1520,6 +1518,30 @@ static void atom_get_vbios_build(struct atom_context *ctx) strscpy(ctx->build_num, str, len); } +static inline void atom_print_vbios_info(struct atom_context *ctx) +{ + char vbios_info[256]; + int off = 0; + + if (ctx->vbios_pn[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%s", ctx->vbios_pn); + if (ctx->build_num[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%sbuild: %s", off ? ", " : "", + ctx->build_num); + if (ctx->vbios_ver_str[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%sver: %s", off ? ", " : "", + ctx->vbios_ver_str); + if (ctx->date[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%s%.10s", off ? ", " : "", + ctx->date); + if (off) + drm_info(ctx->card->dev, "ATOM BIOS: %s\n", vbios_info); +} + struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) { int base; @@ -1582,6 +1604,8 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) atom_get_vbios_version(ctx); atom_get_vbios_build(ctx); + atom_print_vbios_info(ctx); + return ctx; } From 10e4862d9dc7edb58fa3bf10e431a8ffa54eafc0 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 18 Feb 2026 15:42:08 -0500 Subject: [PATCH 0243/2070] drm/amd/display: Add atomfirmware cap for DP++ Type2 Add ATOM_CONNECTOR_CAP_DP_PLUS_PLUS_TYPE2_ONLY in atom connector caps definitions. Signed-off-by: Aurabindo Pillai Signed-off-by: Nevenko Stupar Acked-by: Alex Hung --- drivers/gpu/drm/amd/include/atomfirmware.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 3d083010e734a..18f9642a42eed 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -879,6 +879,7 @@ enum atom_connector_caps_def { ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq + ATOM_CONNECTOR_CAP_DP_PLUS_PLUS_TYPE2_ONLY = 0x10, //a cap bit that indicates connector with DP_PLUS_PLUS_TYPE2_ONLY }; struct atom_disp_connector_caps_record From ea55b3370a137c476e64a9009719d74de586623c Mon Sep 17 00:00:00 2001 From: Simon Louis Date: Tue, 3 Feb 2026 15:42:00 +0000 Subject: [PATCH 0244/2070] drm/amdgpu: Add xgmi link status for VFs Xgmi link status is unavailable in guest. This patch returns AMDGPU_XGMI_LINK_NA for VFs. Signed-off-by: Simon Louis Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 3 +++ drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 0ca6fa40a87c5..08731d4be1776 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -347,6 +347,9 @@ int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num) { u32 xgmi_state_reg_val; + if (amdgpu_sriov_vf(adev)) + return AMDGPU_XGMI_LINK_NA; + if (adev->gmc.xgmi.num_physical_nodes <= 1) return -EINVAL; diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 6683ffd6aa681..bdf8e6ff556cf 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -1832,6 +1832,8 @@ struct amdgpu_partition_metrics_v1_1 { enum amdgpu_xgmi_link_status { AMDGPU_XGMI_LINK_INACTIVE = 0, AMDGPU_XGMI_LINK_ACTIVE = 1, + /* Status not available */ + AMDGPU_XGMI_LINK_NA = 2, }; #endif From d839eba2a9772d14beef00bcaa7f5bf106104fa7 Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Wed, 4 Feb 2026 17:08:01 -0500 Subject: [PATCH 0245/2070] drm/amd/display: Exit IPS w/ DC helper for all dc_set_power_state cases [why & how] On D3 path during dc_set_power_state, we may be in idle_allowed=true, at which point we will exit idle via dc_wake_and_execute_dmub_cmd_list which doesn't update dc->idle_optimizations_allowed to false. This would cause any future attempts to allow idle optimizations via the DC helper to get skipped because the value is stale and not reflective of the actual HW state. Move dc_exit_ips_for_hw_access() to the top of the function. Additionally ensure that dc_power_down_on_boot thread holds the DC lock and only runs if there are 0 streams. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 984b4bc5f53c6..6f39b903947eb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5541,6 +5541,9 @@ void dc_power_down_on_boot(struct dc *dc) { if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW && dc->hwss.power_down_on_boot) { + if (dc->current_state->stream_count > 0) + return; + if (dc->caps.ips_support) dc_exit_ips_for_hw_access(dc); dc->hwss.power_down_on_boot(dc); @@ -5552,12 +5555,12 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state) if (!dc->current_state) return; + dc_exit_ips_for_hw_access(dc); + switch (power_state) { case DC_ACPI_CM_POWER_STATE_D0: dc_state_construct(dc, dc->current_state); - dc_exit_ips_for_hw_access(dc); - dc_z10_restore(dc); dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state); From 0ea8f4cae0c6c5a560296f2d96d40e538ff8e2b5 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Mon, 2 Feb 2026 15:57:19 -0500 Subject: [PATCH 0246/2070] drm/amd/display: Fix cursor pos at overlay plane edges on DCN4 [Why&How] On DCN4, when cursor straddles the left/top edge of an overlay plane, the recout-relative position becomes negative. These negative values wrap to large positive numbers when cast to uint32_t, causing the cursor on the the overlay plane to disappear. Fix by adding hotspot adjustment and position clamping after the recout-relative calculation, matching the existing ODM/MPC slice boundary handling. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index b91517b9fedcf..f604c30e8493f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1202,6 +1202,25 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) x_pos = pos_cpy.x - param.recout.x; y_pos = pos_cpy.y - param.recout.y; + /** + * If the cursor position is negative after recout adjustment, we need + * to shift the hotspot to compensate and clamp position to 0. This + * handles the case where cursor straddles the left/top edge of an + * overlay plane - the cursor is partially visible and needs correct + * hotspot adjustment to render the visible portion. + */ + if (x_pos < 0) { + pos_cpy.x_hotspot -= x_pos; + if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION) + adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy); + x_pos = 0; + } + + if (y_pos < 0) { + pos_cpy.y_hotspot -= y_pos; + y_pos = 0; + } + recout_x_pos = x_pos - pos_cpy.x_hotspot; recout_y_pos = y_pos - pos_cpy.y_hotspot; From c48f4392f708e7c41c607c36db3c53932358a690 Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Tue, 10 Feb 2026 17:40:42 +0800 Subject: [PATCH 0247/2070] drm/amd/display: Fix DPIA number and driver ID field issue [Why] The DPIA number field is 6 bits in the spec. In dp_type, it only defines 5 bits. The driver ID is only 4 bits in the spec. [How] Set DPIA number field size to 6. And only update 4 bits for driver id. Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Cruise Hung Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 4 ++-- drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 5e3646b7550c1..9540f0ead2794 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -947,8 +947,8 @@ union dp_tun_cap_support { /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ union dpia_info { struct { - uint8_t dpia_num :5; - uint8_t rsvd :3; + uint8_t dpia_num :6; + uint8_t rsvd :2; } bits; uint8_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c index 9b2f1a7da1d12..766b54631c798 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c @@ -71,7 +71,7 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link) link->dpcd_caps.usb4_dp_tun_info.dpia_info.raw = dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT]; link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id = - dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT]; + dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT] & 0x0F; if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc) { status = core_link_read_dpcd(link, USB4_DRIVER_BW_CAPABILITY, From db0e0fa21cd811b647eb4a4e8f11a0256c757031 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Mon, 16 Feb 2026 11:26:58 -0500 Subject: [PATCH 0248/2070] drm/amd/display: Silence type mismatch warning [Why&How] Resolve type mismatch warnings by ensuring loop counters and compared values use matching unsigned types (size_t or int) in array iteration. Reviewed-by: Aric Cyr Signed-off-by: Gaghik Khachatrian Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 6f39b903947eb..0421012803b81 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3065,7 +3065,7 @@ struct surface_update_descriptor dc_check_update_surfaces_for_stream( { if (stream_update) stream_update->stream->update_flags.raw = 0; - for (size_t i = 0; i < surface_count; i++) + for (int i = 0; i < surface_count; i++) updates[i].surface->update_flags.raw = 0; return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update); From 94cb871f2a1b5277be7680196814f88ed619a23e Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 11 Feb 2026 16:53:44 -0500 Subject: [PATCH 0249/2070] drm/amd/display: Fix dcn401_optimize_bandwidth [Why&How] We should check for != zstate disallow and programming extend blank from a different struct. Reviewed-by: Leo Chen Reviewed-by: Dmytro Laktyushkin Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index f604c30e8493f..95d9e17a269b3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1483,7 +1483,7 @@ void dcn401_optimize_bandwidth( dc->clk_mgr, context, true); - if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { + if (context->bw_ctx.bw.dcn.clk.zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW) { for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -1491,7 +1491,7 @@ void dcn401_optimize_bandwidth( && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, - pipe_ctx->dlg_regs.min_dst_y_next_start); + pipe_ctx->hubp_regs.dlg_regs.min_dst_y_next_start); } } } From 77ee28727d9c8f0a2b2dca871504c6d8a99349e8 Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Mon, 2 Feb 2026 19:14:23 -0500 Subject: [PATCH 0250/2070] drm/amd/display: Add missing clock types & fix formatting [why & how] Add the missing dprefclk and dtbclk clock types to the enum. Reviewed-by: Dillon Varone Signed-off-by: Ovidiu Bunea Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 8d694a3a7e07a..9e53eacee3f84 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -290,10 +290,10 @@ struct clk_mgr_registers { uint32_t CLK2_CLK2_DFS_CNTL; uint32_t CLK1_CLK0_CURRENT_CNT; - uint32_t CLK1_CLK1_CURRENT_CNT; - uint32_t CLK1_CLK2_CURRENT_CNT; - uint32_t CLK1_CLK3_CURRENT_CNT; - uint32_t CLK1_CLK4_CURRENT_CNT; + uint32_t CLK1_CLK1_CURRENT_CNT; + uint32_t CLK1_CLK2_CURRENT_CNT; + uint32_t CLK1_CLK3_CURRENT_CNT; + uint32_t CLK1_CLK4_CURRENT_CNT; uint32_t CLK1_CLK5_CURRENT_CNT; uint32_t CLK0_CLK0_DFS_CNTL; @@ -362,6 +362,8 @@ enum clock_type { clock_type_dscclk, clock_type_uclk, clock_type_dramclk, + clock_type_dprefclk, + clock_type_dtbclk, }; From 08b65e93364536e925d93ab3ebe79db064a9299f Mon Sep 17 00:00:00 2001 From: Muaaz Nisar Date: Thu, 18 Dec 2025 16:03:44 -0500 Subject: [PATCH 0251/2070] drm/amd/display: Add Visual Confirm Support for Testing [WHY+HOW] Adding visual confirm to visually track changes in refresh rate. Reviewed-by: Aric Cyr Signed-off-by: Muaaz Nisar Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 148 ++++++++++-------- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 21 +++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 4 + 4 files changed, 105 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 0421012803b81..c17f065a88d4f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -442,75 +442,6 @@ static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struc return false; } -/** - * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR - * @dc: dc reference - * @stream: Initial dc stream state - * @adjust: Updated parameters for vertical_total_min and vertical_total_max - * - * Looks up the pipe context of dc_stream_state and updates the - * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh - * Rate, which is a power-saving feature that targets reducing panel - * refresh rate while the screen is static - * - * Return: %true if the pipe context is found and adjusted; - * %false if the pipe context is not found. - */ -bool dc_stream_adjust_vmin_vmax(struct dc *dc, - struct dc_stream_state *stream, - struct dc_crtc_timing_adjust *adjust) -{ - int i; - - /* - * Don't adjust DRR while there's bandwidth optimizations pending to - * avoid conflicting with firmware updates. - */ - if (dc->ctx->dce_version > DCE_VERSION_MAX) { - if (dc->optimized_required && - (stream->adjust.v_total_max != adjust->v_total_max || - stream->adjust.v_total_min != adjust->v_total_min)) { - stream->adjust.timing_adjust_pending = true; - return false; - } - } - - dc_exit_ips_for_hw_access(dc); - - stream->adjust.v_total_max = adjust->v_total_max; - stream->adjust.v_total_mid = adjust->v_total_mid; - stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; - stream->adjust.v_total_min = adjust->v_total_min; - stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt; - - if (dc->caps.max_v_total != 0 && - (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) { - stream->adjust.timing_adjust_pending = false; - if (adjust->allow_otg_v_count_halt) - return set_long_vtotal(dc, stream, adjust); - else - return false; - } - - for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; - - if (pipe->stream == stream && pipe->stream_res.tg) { - dc->hwss.set_drr(&pipe, - 1, - *adjust); - stream->adjust.timing_adjust_pending = false; - - if (dc->hwss.notify_cursor_offload_drr_update) - dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); - - return true; - } - } - - return false; -} - /** * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate) @@ -1274,6 +1205,8 @@ static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *conte get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color)); else if (dc->debug.visual_confirm == VISUAL_CONFIRM_VABC) get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) + get_refresh_rate_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); } } } @@ -1323,6 +1256,83 @@ void dc_get_visual_confirm_for_stream( } } +/** + * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR + * @dc: dc reference + * @stream: Initial dc stream state + * @adjust: Updated parameters for vertical_total_min and vertical_total_max + * + * Looks up the pipe context of dc_stream_state and updates the + * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh + * Rate, which is a power-saving feature that targets reducing panel + * refresh rate while the screen is static + * + * Return: %true if the pipe context is found and adjusted; + * %false if the pipe context is not found. + */ +bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state *stream, + struct dc_crtc_timing_adjust *adjust) +{ + int i; + + /* + * Don't adjust DRR while there's bandwidth optimizations pending to + * avoid conflicting with firmware updates. + */ + if (dc->ctx->dce_version > DCE_VERSION_MAX) { + if (dc->optimized_required && + (stream->adjust.v_total_max != adjust->v_total_max || + stream->adjust.v_total_min != adjust->v_total_min)) { + stream->adjust.timing_adjust_pending = true; + return false; + } + } + + dc_exit_ips_for_hw_access(dc); + + stream->adjust.v_total_max = adjust->v_total_max; + stream->adjust.v_total_mid = adjust->v_total_mid; + stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; + stream->adjust.v_total_min = adjust->v_total_min; + stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt; + + if (dc->caps.max_v_total != 0 && + (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) { + stream->adjust.timing_adjust_pending = false; + if (adjust->allow_otg_v_count_halt) + return set_long_vtotal(dc, stream, adjust); + else + return false; + } + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->stream == stream && pipe->stream_res.tg) { + dc->hwss.set_drr(&pipe, + 1, + *adjust); + stream->adjust.timing_adjust_pending = false; + + if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) { + if (pipe->stream && pipe->plane_state) { + dc_update_visual_confirm_color(dc, dc->current_state, pipe); + dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id); + + } + } + + if (dc->hwss.notify_cursor_offload_drr_update) + dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); + + return true; + } + } + + return false; +} + static void disable_dangling_plane(struct dc *dc, struct dc_state *context) { int i, j; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index b380044416164..5b3695e72e196 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -4108,3 +4108,24 @@ void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, (*seq_state->num_steps)++; } } + + +void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + unsigned int refresh_rate = 0; + uint32_t scaling_factor = 0; + if (pipe_ctx && pipe_ctx->stream && color) { + refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total); + + uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000; + uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000; + + if (max_refresh_rate - min_refresh_rate) + scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate); + + pipe_ctx->visual_confirm_color.color_r_cr = color_value; + pipe_ctx->visual_confirm_color.color_g_y = scaling_factor; + pipe_ctx->visual_confirm_color.color_b_cb = color_value; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d2ea4e03c963a..7126dc278a531 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -581,6 +581,7 @@ enum visual_confirm { VISUAL_CONFIRM_HW_CURSOR = 20, VISUAL_CONFIRM_VABC = 21, VISUAL_CONFIRM_DCC = 22, + VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, VISUAL_CONFIRM_EXPLICIT = 0x80000000, }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index d699640ba5b45..d1dba7ffcd9b3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1365,6 +1365,10 @@ void get_dcc_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); +void get_refresh_rate_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); + void set_p_state_switch_method( struct dc *dc, struct dc_state *context, From bfd1a7a23bacb85ac2c9a7734e2861c66d6a366b Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Thu, 12 Feb 2026 16:49:15 -0500 Subject: [PATCH 0252/2070] drm/amd/display: [FW Promotion] Release 0.1.48.0 [Why&How] Introduce DMUB IHC command. Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 6f388c910e18a..2abbc6c97850a 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1897,6 +1897,10 @@ enum dmub_cmd_type { */ DMUB_CMD__PR = 94, + /** + * Command type used for all IHC commands. + */ + DMUB_CMD__IHC = 95, /** * Command type use for VBIOS shared commands. @@ -4959,6 +4963,52 @@ union dmub_replay_cmd_set { struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; }; +/** + * IHC command sub-types. + */ +enum dmub_cmd_ihc_type { + /** + * Set DIG HDCP interrupt destination. + */ + DMUB_CMD__IHC_SET_DIG_HDCP_INTERRUPT_DEST = 0, +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__IHC command. + */ +struct dmub_cmd_ihc_data { + /** + * DIG engine ID (0-3). + */ + uint8_t dig_id; + /** + * 1 = route to DMU, 0 = route to CPU. + */ + uint8_t to_dmu : 1; + /** + * Reserved bits. + */ + uint8_t reserved : 7; + /** + * Padding. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__IHC command. + */ +struct dmub_rb_cmd_ihc { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * IHC command data. + */ + struct dmub_cmd_ihc_data data; +}; + /** * SMART POWER OLED command sub-types. */ @@ -7142,6 +7192,10 @@ union dmub_rb_cmd { struct dmub_rb_cmd_pr_update_state pr_update_state; struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; + /** + * Definition of a DMUB_CMD__IHC command. + */ + struct dmub_rb_cmd_ihc ihc; }; /** From 014ba8da403b8ab60a9d134fbb8ef941047475c6 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Thu, 12 Feb 2026 18:12:35 -0500 Subject: [PATCH 0253/2070] drm/amd/display: Promote DC to 3.2.371 This version brings along the follwing updates: - Add visualconfirm support for refresh rate change testing. - Fix IPS exit with DC helper for all dc_set_power_state cases. - Fix cursor position at overlay plane edges on DCN4. - Introduce DMUB IHC command. - Add missing dprefclk and dtbclk clock types and fix formatting. - Fix DPIA number and driver ID field sizes per spec. - Minor code fixes. Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7126dc278a531..32fcbedd82d4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.370" +#define DC_VER "3.2.371" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 8a8c26f526f3d453b9a57f144cad5ce2061b5d2e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Sep 2025 10:32:34 -0400 Subject: [PATCH 0254/2070] drm/amdgpu/sdma4.0: adjust SDMA limits SDMA 4.4.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak Reviewed-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index a35d9951e22a9..44f0f23e11484 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2604,18 +2604,31 @@ static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 22, .copy_num_dw = 7, .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 22, + .fill_num_dw = 5, + .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, +}; + +static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = { + .copy_max_bytes = 1 << 30, + .copy_num_dw = 7, + .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, + + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, }; static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; + if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0)) + adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs; + else + adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; if (adev->sdma.has_page_queue) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; else From 70b67e17c2480f54c0035a94e9a46e25ee3699ea Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Sep 2025 10:38:57 -0400 Subject: [PATCH 0255/2070] drm/amdgpu/sdma4.4: adjust SDMA limits SDMA 4.4.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak Reviewed-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 7f77367848d43..78bdfed0a7fd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -2305,11 +2305,11 @@ static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 7, .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, }; From f15aaae743a10cf99d9cd767f73d4db9cdbfd97a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Sep 2025 10:33:39 -0400 Subject: [PATCH 0256/2070] drm/amdgpu/sdma5.2: adjust SDMA limits SDMA 5.2.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious v3: align const fill with PAL limits v4: re-align with hw limits Cc: Vitaly Prosyak Reviewed-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 0a8269795241d..b4fb90cc8f7d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -2045,11 +2045,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 7, .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, /* HW supports 1 << 30, but PAL uses 1 << 22 */ .fill_num_dw = 5, .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, }; From cfb24170ace5a0a5434dbc133eb35c108eeb2e0f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Sep 2025 10:34:11 -0400 Subject: [PATCH 0257/2070] drm/amdgpu/sdma6.0: adjust SDMA limits SDMA 6.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak Reviewed-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 2643364328498..b005672f2f96b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1884,11 +1884,11 @@ static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 7, .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, }; From 81f7b77aeb07565a63a27a1a075a6e2118529790 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Sep 2025 10:34:59 -0400 Subject: [PATCH 0258/2070] drm/amdgpu/sdma7.0: adjust SDMA limits SDMA 7.0 has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak Reviewed-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index f938be0524cd1..5679a94d0815e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1835,10 +1835,10 @@ static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 8, .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v7_0_emit_fill_buffer, }; From b4bccb34b060f24404b4129807775b3d6fa871eb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 19 Feb 2026 10:48:39 -0500 Subject: [PATCH 0259/2070] drm/amdgpu/sdma7.1: adjust SDMA limits SDMA 7.1 has increased transfer limits. Cc: Vitaly Prosyak Reviewed-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 3de76afe3e454..03bf1f86098f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1745,10 +1745,10 @@ static void sdma_v7_1_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v7_1_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 8, .emit_copy_buffer = sdma_v7_1_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v7_1_emit_fill_buffer, }; From db941ce78f04c54330375876bf2527d24458f0ad Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 5 Dec 2025 13:40:29 +0000 Subject: [PATCH 0260/2070] drm/amdgpu/userq: Use memdup_array_user in amdgpu_userq_wait_ioctl Use the existing helper instead of multiplying the size. Signed-off-by: Tvrtko Ursulin Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 212056d4ddf04..e9bccf0179524 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -680,23 +680,24 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, } num_syncobj = wait_info->num_syncobj_handles; - syncobj_handles = memdup_user(u64_to_user_ptr(wait_info->syncobj_handles), - size_mul(sizeof(u32), num_syncobj)); + syncobj_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_handles), + num_syncobj, sizeof(u32)); if (IS_ERR(syncobj_handles)) { r = PTR_ERR(syncobj_handles); goto free_bo_handles_write; } num_points = wait_info->num_syncobj_timeline_handles; - timeline_handles = memdup_user(u64_to_user_ptr(wait_info->syncobj_timeline_handles), - sizeof(u32) * num_points); + timeline_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_timeline_handles), + num_points, sizeof(u32)); if (IS_ERR(timeline_handles)) { r = PTR_ERR(timeline_handles); goto free_syncobj_handles; } - timeline_points = memdup_user(u64_to_user_ptr(wait_info->syncobj_timeline_points), - sizeof(u32) * num_points); + timeline_points = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_timeline_points), + num_points, sizeof(u32)); + if (IS_ERR(timeline_points)) { r = PTR_ERR(timeline_points); goto free_timeline_handles; From 7bae1393d688f68fd185886b2c7a1de437ed418b Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 5 Dec 2025 13:40:30 +0000 Subject: [PATCH 0261/2070] drm/amdgpu/userq: Use memdup_array_user in amdgpu_userq_signal_ioctl Use the existing helper instead of multiplying the size. Signed-off-by: Tvrtko Ursulin Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index e9bccf0179524..3502ca2f595d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -480,8 +480,8 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, return -ENOTSUPP; num_syncobj_handles = args->num_syncobj_handles; - syncobj_handles = memdup_user(u64_to_user_ptr(args->syncobj_handles), - size_mul(sizeof(u32), num_syncobj_handles)); + syncobj_handles = memdup_array_user(u64_to_user_ptr(args->syncobj_handles), + num_syncobj_handles, sizeof(u32)); if (IS_ERR(syncobj_handles)) return PTR_ERR(syncobj_handles); From f30a3f8654b662602a3dd4216dc592329452a6dd Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 23 Feb 2026 19:14:41 +0530 Subject: [PATCH 0262/2070] drm/amd/display: Fix kdoc formatting in dcn42_hwseq.c Kernel-doc requires all lines within a documentation comment to start with " *". The previous empty line caused a "bad line" warning during build. Cc: Harry Wentland Cc: Mario Limonciello Cc: Alex Hung Cc: Aurabindo Pillai Cc: ChiaHsuan Chung Cc: Roman Li Signed-off-by: Srinivasan Shanmugam Reviewed-by: Roman Li Change-Id: I3f856fa5bcd30db542004a4a40c463e41a9e2779 --- drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index c9c6ef8236ed8..0d9871f9864b9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -1294,7 +1294,7 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, * ONO Region 9, DCPG 2: dchubp2, dpp2 * ONO Region 11, DCPG 3: dchubp3, dpp3 * ONO Region 4, DCPG 25: hpo - + * * No sequential power up/down ordering for DCN42 * * @dc: Current DC state From ce37ab6943f7fbcd48c6bc56dbeccd800ccf7cb7 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:12:23 +0800 Subject: [PATCH 0263/2070] drm/amdkcl/dkms: add dkms support It's a squash of 6a2ef7359800 drm/amdkcl: fix include path in schduler 6d5954b6cff6 drm/amdkcl: describe the 'sources' file format 5579697e0041 drm/amdkcl: update sources file 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables d96876c7258e drm/amdkcl: cleanup LINUXINCLUDE in dkms package fdc3c5d4df0e drm/amdkcl: add dkms support Signed-off-by: Junwei Zhang Signed-off-by: Adam Yang Reviewed-by: Qiang Yu Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/symbols | 1 + drivers/gpu/drm/amd/dkms/Makefile | 23 +++++++++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 40 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 48 +++++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/sources | 26 +++++++++++++++ 5 files changed, 138 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/symbols create mode 100644 drivers/gpu/drm/amd/dkms/Makefile create mode 100644 drivers/gpu/drm/amd/dkms/dkms.conf create mode 100755 drivers/gpu/drm/amd/dkms/pre-build.sh create mode 100644 drivers/gpu/drm/amd/dkms/sources diff --git a/drivers/gpu/drm/amd/amdkcl/symbols b/drivers/gpu/drm/amd/amdkcl/symbols new file mode 100644 index 0000000000000..fe167314985be --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/symbols @@ -0,0 +1 @@ +SYMS="" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile new file mode 100644 index 0000000000000..f5d9b8d250ed6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -0,0 +1,23 @@ +LINUXINCLUDE := \ + -I$(src)/include \ + -I$(src)/include/uapi \ + -include $(src)/include/kcl/kcl_version.h \ + -include $(src)/include/rename_symbol.h \ + $(LINUXINCLUDE) + +export CONFIG_DRM_TTM=m +export CONFIG_DRM_AMDGPU=m +export CONFIG_DRM_SCHED=m +export CONFIG_DRM_AMDGPU_CIK=y +export CONFIG_DRM_AMDGPU_SI=y +export CONFIG_DRM_AMDGPU_USERPTR=y +export CONFIG_DRM_AMD_DC=y +export CONFIG_DRM_AMD_DC_DCN1_0=y + +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 + +obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf new file mode 100644 index 0000000000000..e9e8db1bdd64e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -0,0 +1,40 @@ +PACKAGE_NAME="amdgpu" +PACKAGE_VERSION="1.0" +AUTOINSTALL="yes" +REMAKE_INITRD="yes" +PRE_BUILD="pre-build.sh $kernelver" + +# not work with RHEL DKMS +#MODULES_CONF[0]="blacklist radeon" + +BUILT_MODULE_NAME[0]="amdgpu" +BUILT_MODULE_LOCATION[0]="amd/amdgpu" +DEST_MODULE_LOCATION[0]="/updates" + +BUILT_MODULE_NAME[1]="amdttm" +BUILT_MODULE_LOCATION[1]="ttm" +DEST_MODULE_LOCATION[1]="/updates" + +BUILT_MODULE_NAME[2]="amdkcl" +BUILT_MODULE_LOCATION[2]="amd/amdkcl" +DEST_MODULE_LOCATION[2]="/updates" + +BUILT_MODULE_NAME[3]="amd-sched" +BUILT_MODULE_LOCATION[3]="scheduler" +DEST_MODULE_LOCATION[3]="/updates" + +# Find out how many CPU cores can be use if we pass appropriate -j option to make. +# DKMS could use all cores on multicore systems to build the kernel module. +num_cpu_cores() +{ + if [ -x /usr/bin/nproc ]; then + nproc + else + echo "1" + fi +} + +MAKE[0]="make -j$(num_cpu_cores) TTM_NAME=${BUILT_MODULE_NAME[1]} \ + SCHED_NAME=${BUILT_MODULE_NAME[3]} \ + -C $kernel_source_dir \ + M=$dkms_tree/$module/$module_version/build" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh new file mode 100755 index 0000000000000..72929ce8ae064 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -0,0 +1,48 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +source $KCL/symbols + +# lookup symbol address. obsolete. +echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c +for sym in $SYMS; do + addr=$(grep "\<$sym\>" /boot/System.map-$KERNELVER | awk -F' ' '{print $1}') + echo "void *_kcl_$sym = (void *)0x$addr;" >> $KCL/symbols.c +done + +# add amd prefix to exported symbols +find ttm -name '*.c' -exec grep EXPORT_SYMBOL {} + \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h + +find scheduler -name '*.c' -exec grep EXPORT_SYMBOL {} + \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources new file mode 100644 index 0000000000000..b8f2af052e55a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/sources @@ -0,0 +1,26 @@ +# +# The 'sources' file contains source/destination directives to be used +# by the build framework to construct the DKMS source tree +# +# File format: +# source destination +# ------ ----------- +# directory[/file] name directory/[file] name +# must exist at the directory: must have explicit directory name +# source path e.g. dir/ (with '/'). The name without +# slash is treated as a file if it does +# not exist +# the directory will be created if it +# does not exist +# file: optional file name at the destination +# +drivers/gpu/drm/amd . +drivers/gpu/drm/ttm . +include/drm/ttm include/drm/ +include/uapi/drm/amdgpu_drm.h include/uapi/drm/ +include/kcl include/ +drivers/gpu/drm/scheduler . +include/drm/gpu_scheduler.h include/drm/ +include/drm/amd_asic_type.h include/drm/ +include/drm/spsc_queue.h include/drm/ +include/uapi/linux/kfd_ioctl.h include/uapi/linux/ From 02bdef1a0b0ae05ec41549dfad525a90772a5ba9 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 18 Nov 2020 10:13:46 -0500 Subject: [PATCH 0264/2070] drm/amdkcl/dkms: Fix values of DEST_MODULE_LOCATION directives The directive is used for finding original modules and must point to the original module locations. If it points to /updates the original module is placed to /updates after DKMS uninstallation that breaks the /lib/modules/ directory integrity. v2: fix quotation mark typo on dkms.conf. The path string should be enclosed in quotion marks. Signed-off-by: Slava Grigorev Signed-off-by: Rui Teng Reviewed-by: Flora Cui Change-Id: Id48f89a190c0d354147db346a468573775548c9f --- drivers/gpu/drm/amd/dkms/dkms.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index e9e8db1bdd64e..86826daa80072 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -9,19 +9,19 @@ PRE_BUILD="pre-build.sh $kernelver" BUILT_MODULE_NAME[0]="amdgpu" BUILT_MODULE_LOCATION[0]="amd/amdgpu" -DEST_MODULE_LOCATION[0]="/updates" +DEST_MODULE_LOCATION[0]="/kernel/drivers/gpu/drm/amd/amdgpu" BUILT_MODULE_NAME[1]="amdttm" BUILT_MODULE_LOCATION[1]="ttm" -DEST_MODULE_LOCATION[1]="/updates" +DEST_MODULE_LOCATION[1]="/kernel/drivers/gpu/drm/ttm" BUILT_MODULE_NAME[2]="amdkcl" BUILT_MODULE_LOCATION[2]="amd/amdkcl" -DEST_MODULE_LOCATION[2]="/updates" +DEST_MODULE_LOCATION[2]="/kernel/drivers/gpu/drm/amd/amdkcl" BUILT_MODULE_NAME[3]="amd-sched" BUILT_MODULE_LOCATION[3]="scheduler" -DEST_MODULE_LOCATION[3]="/updates" +DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" # Find out how many CPU cores can be use if we pass appropriate -j option to make. # DKMS could use all cores on multicore systems to build the kernel module. From 9e023b04f6946849acb487c007861c0f2ce40c00 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 30 Oct 2019 10:27:35 +0800 Subject: [PATCH 0265/2070] drm/amdkcl/dkms: add amdkcl/files to include all files containing EXPORT_SYMBOL to deal with Signed-off-by: Flora Cui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/amdkcl/files | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 16 +++++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/files diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files new file mode 100644 index 0000000000000..501b9055ad408 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -0,0 +1 @@ +FILES="ttm/*.c scheduler/*.c" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 72929ce8ae064..0970ec311e687 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -28,6 +28,7 @@ version_le () { } source $KCL/symbols +source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c @@ -37,12 +38,9 @@ for sym in $SYMS; do done # add amd prefix to exported symbols -find ttm -name '*.c' -exec grep EXPORT_SYMBOL {} + \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h - -find scheduler -name '*.c' -exec grep EXPORT_SYMBOL {} + \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h +for file in $FILES; do + grep EXPORT_SYMBOL $file \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h +done From f9acfe45b7e18a45b5db3bfcb771955a9dac3bfd Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 16 Mar 2020 10:55:26 -0400 Subject: [PATCH 0266/2070] drm/amdkcl/dkms: simplify pre-build.sh script code Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 0970ec311e687..5e6a61aa8d83e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -33,14 +33,14 @@ source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c for sym in $SYMS; do - addr=$(grep "\<$sym\>" /boot/System.map-$KERNELVER | awk -F' ' '{print $1}') - echo "void *_kcl_$sym = (void *)0x$addr;" >> $KCL/symbols.c + awk -v sym=$sym '/\/ { + print "void *_kcl_" $3 " = (void *)0x" $1 ";" + }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done # add amd prefix to exported symbols for file in $FILES; do - grep EXPORT_SYMBOL $file \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h done From 10c405387d6df323bcbf9badb17f5d2acac13cc9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 22 Jul 2020 11:10:32 +0800 Subject: [PATCH 0267/2070] drm/amdkcl/dkms: rename CONFIG_DRM_xxx & amdgpu configs otherwise kernel config would override dkms package config v2: update ttm/schduler configs, incase ttm/schduler is built-in Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 5e6a61aa8d83e..9fb471b43a708 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -44,3 +44,15 @@ for file in $FILES; do print "#define "$2" amd"$2" //"$0 }' $file | sort -u >>$INC/rename_symbol.h done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile +done From 02dc061f6946a8b5c2dcea7b4a05b80f7af73d48 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 14:23:29 +0800 Subject: [PATCH 0268/2070] drm/amdkcl/dkms: add backport support for amdgpu v2: drop kcl_amdgpu.o It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables 0275f0fd138c drm/amdkcl: fix out of tree build 383595ad14e1 drm/amdkcl: add backport support for amdgpu Signed-off-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Qiang Yu Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 1 + drivers/gpu/drm/amd/backport/Makefile | 8 ++++++++ drivers/gpu/drm/amd/backport/backport.h | 7 +++++++ 3 files changed, 16 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/Makefile create mode 100644 drivers/gpu/drm/amd/backport/backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 8e22882b66aa4..f04a0f7222644 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -340,5 +340,6 @@ AMD_GPU_RAS_PATH := ../ras AMD_GPU_RAS_FULL_PATH := $(FULL_AMD_PATH)/ras include $(AMD_GPU_RAS_FULL_PATH)/Makefile amdgpu-y += $(AMD_GPU_RAS_FILES) +include $(FULL_AMD_PATH)/backport/Makefile obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile new file mode 100644 index 0000000000000..ca667992f6f72 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +BACKPORT_OBJS := + +amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(FULL_AMD_PATH)/backport/include \ + -include ../backport/backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h new file mode 100644 index 0000000000000..89cd9143a9c0a --- /dev/null +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_H +#define AMDGPU_BACKPORT_H + +#include +#include +#endif /* AMDGPU_BACKPORT_H */ From a7cbe519cedd0838ca6e745d669a2eb9a30093b4 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:15:31 +0800 Subject: [PATCH 0269/2070] drm/amdkcl/dkms: add backport support for scheduler It's a squash of 6a2ef7359800 drm/amdkcl: fix include path in schduler 221c1ea7b3dbd drm/amdkcl: fix license 6e5bc9b8e7ea amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables de12801935af drm/amdkcl: add backport support for scheduler Signed-off-by: Le.Ma Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/scheduler/Makefile | 11 +++++++++-- drivers/gpu/drm/scheduler/backport/Makefile | 4 ++++ drivers/gpu/drm/scheduler/backport/backport.h | 7 +++++++ 3 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/scheduler/backport/Makefile create mode 100644 drivers/gpu/drm/scheduler/backport/backport.h diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index 6e13e4c63e9d8..a5ad916153351 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -20,8 +20,15 @@ # OTHER DEALINGS IN THE SOFTWARE. # # -gpu-sched-y := sched_main.o sched_fence.o sched_entity.o +SCHED_NAME = gpu-sched -obj-$(CONFIG_DRM_SCHED) += gpu-sched.o +$(SCHED_NAME)-y := sched_main.o sched_fence.o sched_entity.o +obj-$(CONFIG_DRM_SCHED) += $(SCHED_NAME).o obj-$(CONFIG_DRM_SCHED_KUNIT_TEST) += tests/ + +SCHED_FULL_PATH = $(src) + +ccflags-y := -I$(SCHED_FULL_PATH) + +include $(SCHED_FULL_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/scheduler/backport/Makefile b/drivers/gpu/drm/scheduler/backport/Makefile new file mode 100644 index 0000000000000..5fe7a0b580f33 --- /dev/null +++ b/drivers/gpu/drm/scheduler/backport/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +ccflags-y += \ + -I$(SCHED_FULL_PATH) \ + -include backport/backport.h diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h new file mode 100644 index 0000000000000..b8c8be307a2e7 --- /dev/null +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDSCHED_BACKPORT_H +#define AMDSCHED_BACKPORT_H + +#include + +#endif From a2f6007880fec89b364c3248618fae7ebebc10e5 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:16:11 +0800 Subject: [PATCH 0270/2070] drm/amdkcl/dkms: add backport support for ttm It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 6e5bc9b8e7ea amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables e173231be48f drm/amdkcl: add backport support for ttm Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/ttm/Makefile | 15 ++++++++++++--- drivers/gpu/drm/ttm/backport/Makefile | 4 ++++ drivers/gpu/drm/ttm/backport/backport.h | 7 +++++++ 3 files changed, 23 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/ttm/backport/Makefile create mode 100644 drivers/gpu/drm/ttm/backport/backport.h diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index 40d07a35293a7..e10443408f593 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -2,10 +2,19 @@ # # Makefile for the drm device driver. This driver provides support for the -ttm-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ +# +# In DKMS mode the module can be renamed by passing TTM_NAME as a parameter +# to 'make' if required +# +TTM_NAME = ttm + +$(TTM_NAME)-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ ttm_execbuf_util.o ttm_range_manager.o ttm_resource.o ttm_pool.o \ ttm_device.o ttm_sys_manager.o ttm_backup.o -ttm-$(CONFIG_AGP) += ttm_agp_backend.o +$(TTM_NAME)-$(CONFIG_AGP) += ttm_agp_backend.o -obj-$(CONFIG_DRM_TTM) += ttm.o +obj-$(CONFIG_DRM_TTM) += $(TTM_NAME).o obj-$(CONFIG_DRM_TTM_KUNIT_TEST) += tests/ + +TTM_FULL_PATH = $(src) +include $(TTM_FULL_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/ttm/backport/Makefile b/drivers/gpu/drm/ttm/backport/Makefile new file mode 100644 index 0000000000000..839110332c785 --- /dev/null +++ b/drivers/gpu/drm/ttm/backport/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +ccflags-y += \ + -I$(TTM_FULL_PATH) \ + -include backport/backport.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h new file mode 100644 index 0000000000000..524d2a01b50df --- /dev/null +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDTTM_BACKPORT_H +#define AMDTTM_BACKPORT_H + +#include + +#endif From 8cdf3a3f8cbccc7aeab34e504334f979d77d4f66 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 15 Dec 2016 11:52:56 +0800 Subject: [PATCH 0271/2070] drm/amdkcl/dkms: rename the device name to amdttm v2: fix ttm name to differentia package driver Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index e10443408f593..d01dfb469a208 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -7,6 +7,8 @@ # to 'make' if required # TTM_NAME = ttm +ccflags-y += \ + -DTTM_NAME="\"$(TTM_NAME)\"" $(TTM_NAME)-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ ttm_execbuf_util.o ttm_range_manager.o ttm_resource.o ttm_pool.o \ From 63be2b801a08a441c115c8c845ddfd7efd64931c Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 16 Sep 2019 11:48:05 +0800 Subject: [PATCH 0272/2070] drm/amdkcl/dkms: use $(src) in Makefile when built with dkms v2: Properly define ..._FULL_PATH variables in amdgpu, ttm, and scheduler trees. That fixes 'make -C ... M=... modiles' build to succeed correctly. It's a squash of 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables a5abb9e0c999 drm/amdkcl: use $(src) in Makefile when built with dkms Signed-off-by: Adam Yang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/scheduler/Makefile | 2 +- drivers/gpu/drm/ttm/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index f04a0f7222644..0f88b144e57fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,7 +23,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -FULL_AMD_PATH=$(src)/.. +FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) DISPLAY_FOLDER_NAME=display FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index a5ad916153351..705573ee221aa 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_DRM_SCHED) += $(SCHED_NAME).o obj-$(CONFIG_DRM_SCHED_KUNIT_TEST) += tests/ -SCHED_FULL_PATH = $(src) +SCHED_FULL_PATH := $(src) ccflags-y := -I$(SCHED_FULL_PATH) diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index d01dfb469a208..56d5f0704c155 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -18,5 +18,5 @@ $(TTM_NAME)-$(CONFIG_AGP) += ttm_agp_backend.o obj-$(CONFIG_DRM_TTM) += $(TTM_NAME).o obj-$(CONFIG_DRM_TTM_KUNIT_TEST) += tests/ -TTM_FULL_PATH = $(src) +TTM_FULL_PATH := $(src) include $(TTM_FULL_PATH)/backport/Makefile From 2241395224a471fb30c29c71850c719ae8987159 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Sat, 21 Mar 2020 19:19:35 -0400 Subject: [PATCH 0273/2070] drm/amdkcl/dkms: drop use of BUILD_AS_DKMS in Makefile files Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 0f88b144e57fd..da0b26ac84f70 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -343,3 +343,5 @@ amdgpu-y += $(AMD_GPU_RAS_FILES) include $(FULL_AMD_PATH)/backport/Makefile obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o + +CFLAGS_amdgpu_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index d13e64a69e255..72f13cd5f5407 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -583,5 +583,5 @@ TRACE_EVENT(amdgpu_reset_reg_dumps, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu +#define TRACE_INCLUDE_PATH . #include diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index 261713dd7d5a1..0f965676764f7 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -155,5 +155,5 @@ TRACE_EVENT(drm_sched_job_unschedulable, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/scheduler +#define TRACE_INCLUDE_PATH . #include From c01e36f4ee28ce6cdb35e72c358b1935322141b9 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 8 Nov 2019 12:13:34 +0800 Subject: [PATCH 0274/2070] drm/amdkcl/dkms: add amdkcl support It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables 079a1dd78a42 drm/amdkcl: add amdkcl support Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 ++++ drivers/gpu/drm/amd/amdkcl/main.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/Makefile create mode 100644 drivers/gpu/drm/amd/amdkcl/main.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile new file mode 100644 index 0000000000000..018792c49a249 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +amdkcl-y += main.o + +obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c new file mode 100644 index 0000000000000..59f4520c9a8bd --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include + +int __init amdkcl_init(void) +{ + return 0; +} +module_init(amdkcl_init); + +void __exit amdkcl_exit(void) +{ +} + +module_exit(amdkcl_exit); + +MODULE_AUTHOR("AMD linux driver team"); +MODULE_DESCRIPTION("Module for OS kernel compatible layer"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); From def073d90453574fb79518ebd26391b235bfa150 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Thu, 29 Dec 2016 15:07:05 +0800 Subject: [PATCH 0275/2070] drm/amdkcl/dkms: use system drm header include uapi/drm/drm.h in $(srctree) Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui --- include/uapi/drm/amdgpu_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index ebbd861ef0bc6..6d9c078d7a7e1 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -32,7 +32,7 @@ #ifndef __AMDGPU_DRM_H__ #define __AMDGPU_DRM_H__ -#include "drm.h" +#include #if defined(__cplusplus) extern "C" { From 4fad61ad926ac31fd94e0c0c55ba64a9d18540d8 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 10 Aug 2018 16:36:26 +0800 Subject: [PATCH 0276/2070] drm/amdkcl/dkms: add drm version support (v3) v2: detect building kernel automatically custom kernel build support v3: support specific kbuild path v4: VERSION & PATCHLEVEL are exported in kernel Makefile and can be accessed directly It's a squash of 5eb73682006d drm/amdkcl: refactor dkms/Makefile b3160e09da52 drm/amdkcl: simplify DRM_VER retrieve 225506373f54 drm/amdkcl: add drm version support (v3) Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Reviewed-by: Yang Xiong Signed-off-by: Flora Cui --- Makefile | 7 ++++++- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ include/kcl/kcl_version.h | 8 ++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_version.h diff --git a/Makefile b/Makefile index d3a8482bdbd0d..8d85ccd409d02 100644 --- a/Makefile +++ b/Makefile @@ -1362,7 +1362,12 @@ define filechk_version.h ((c) > 255 ? 255 : (c)))'; \ echo \#define LINUX_VERSION_MAJOR $(VERSION); \ echo \#define LINUX_VERSION_PATCHLEVEL $(PATCHLEVEL); \ - echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL) + echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL); \ + echo '#define DRM_VER $(VERSION)'; \ + echo '#define DRM_PATCH $(PATCHLEVEL)'; \ + echo '#define DRM_SUB $(SUBLEVEL)'; \ + echo \#define DRM_VERSION_CODE LINUX_VERSION_CODE; \ + echo '#define DRM_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))' endef $(version_h): private PATCHLEVEL := $(or $(PATCHLEVEL), 0) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f5d9b8d250ed6..359ad88155b58 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,3 +1,15 @@ +DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) +DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) +ifeq ($(DRM_VER),) +DRM_VER = $(VERSION) +DRM_PATCH = $(PATCHLEVEL) +endif + +subdir-ccflags-y += \ + -DDRM_VER=$(DRM_VER) \ + -DDRM_PATCH=$(DRM_PATCH) \ + -DDRM_SUB="0" + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/include/kcl/kcl_version.h b/include/kcl/kcl_version.h new file mode 100644 index 0000000000000..4a470ef6dbbc7 --- /dev/null +++ b/include/kcl/kcl_version.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_VERSION_H +#define AMDKCL_VERSION_H + +#define DRM_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) +#define DRM_VERSION_CODE DRM_VERSION(DRM_VER, DRM_PATCH, DRM_SUB) + +#endif From b193e9470a54f3149fa3142f3311e4be042b97ab Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 17 Aug 2020 17:05:09 +0800 Subject: [PATCH 0277/2070] drm/amdkcl/dkms: add RHEL_MAJOR/RHEL_MINOR v2: for not generic RHEL OS eg:rhel6 rootfs + rhel7.2 kernel before: define macro OS_NAME_RHEL_6 (error) after: define macro OS_NAME_RHEL_7_2 (ok) It's a squash of 10fee5987c68 drm/amdkcl: refactor get_rhel_version 5eb73682006d drm/amdkcl: refactor dkms/Makefile 2b4eefb780d3 drm/amdkcl: drop kdir in dkms package 01253fdd953b drm/amdkcl: fix RHEL_ version check for rhel8.x 1dbfa0ac3b7f drm/amdkcl: update dkms detect OS method fdc3c5d4df0e drm/amdkcl: add dkms support Signed-off-by: Junwei Zhang Signed-off-by: Adam Yang Reviewed-by: Qiang Yu Reviewed-by: Flora Cui Signed-off-by: Kevin Wang Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 359ad88155b58..37cfe6546b880 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -10,6 +10,12 @@ subdir-ccflags-y += \ -DDRM_PATCH=$(DRM_PATCH) \ -DDRM_SUB="0" +define get_rhel_version +printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) +endef +RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) +RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ From f2b36feed2fcae390dbd7d0367cc91f6654d9782 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 17 Aug 2020 17:12:12 +0800 Subject: [PATCH 0278/2070] drm/amdkcl/dkms: add various os support for RHEL 8.0: (Changfeng.Zhu@amd.com) Both KERNEL VERSION and DRM VERSION of redhat 8.0 are 4.18.0.So it needs some changes in Makefile for redhat 8.0. There is no drm_backport.h for RHEL 8.0.So it doesn't need to include drm_backport.h for customized CentOS/RHEL: (Amber.Lin@amd.com) When RHEL_MAJOR doesn't exist in kernel's Makefile, this is not a standard kernel source distributed from CentOS/RHEL. If /etc/os-release identifies a CentOS/RHEL OS, we should treat it as a customized rhel platform. An example is to install upstream 4.16 kernel from elrepo.org on CentOS 7.5. /etc/centos-release-upstream tells OS version as 7.5 but this is not a 3.10.0-862 kernel. for DEBIAN 9.3 (with kernel-4.19): (yttao@amd.com) Because there are two Makefile path in Debian. One is at xxx-amd64(kernel version is always 2.6) and another is at xxx-common(kernel version is correct). And the real one is actually located at xxx-common. So we need manually specify the Makefile at xxx-common in order to read the correct kernel version. for Debian (custom kernels): (63921018+emollier@users.noreply.github.com) The current rock-dkms Makefile takes properly into account the specificities of the Debian native kernel. However, when a custom upstream kernel is installed, notably through packages obtained via `make deb-pkg`, the driver is not built against that specific kernel. Falling back to the initial kdir value when there is no source/ directory allows to build against such kernels on Debian. for OS_VERSION str: (Flora.Cui@amd.com) simplify OS_VERSION macro handling Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Keivn Wang Reviewed-by: Junwei Zhang Signed-off-by: Amber Lin Acked-by: Felix Kuehling Reviewed-by: Junwei Zhang Signed-off-by: Jeremy Newton Reviewed-by: Slava Abramov Signed-off-by: Yintian Tao Reviewed-by: changzhu Signed-off-by: changzhu Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Reviewed-by: Rui Teng Signed-off-by: Adam Yang Reviewed-by: Flora Cui Reviewed-by: Rui Teng Signed-off-by: Slava Grigorev Signed-off-by: Etienne Mollier Signed-off-by: Kent Russell Signed-off-by: Anatoli Antonovitch Tested-by: Anatoli Antonovitch Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/Makefile | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 37cfe6546b880..cb38a2549c569 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -16,6 +16,84 @@ endef RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) +ifneq (,$(RHEL_MAJOR)) +OS_NAME = "rhel" +OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" +else ifneq (,$(wildcard /etc/os-release)) +OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" +# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL +ifeq ("centos",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("rhel",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("linuxmint",$(OS_NAME)) +OS_NAME="ubuntu" +endif +OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +else +OS_NAME = "unknown" +OS_VERSION = "0.0" +endif + +OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) + +ifeq ("ubuntu",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_UBUNTU +else ifeq ("rhel",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_RHEL +else ifeq ("steamos",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_STEAMOS +else ifeq ("sled",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("sles",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("amzn",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_AMZ +else ifeq ("debian",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_DEBIAN +else +subdir-ccflags-y += -DOS_NAME_UNKNOWN +endif + +subdir-ccflags-y += \ + -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ + -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) + +ifeq ($(OS_NAME),"opensuse-leap") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sled") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sles") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"ubuntu") +OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) +subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) +OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" +ifeq ($(OS_OEM),"oem") +subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM +endif +subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"rhel") +subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) + +ifeq ($(RHEL_MAJOR),7) +subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ + -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h +else ifeq ($(RHEL_MAJOR),8) +subdir-ccflags-y += -DOS_NAME_RHEL_8_X +endif +endif + +export OS_NAME OS_VERSION + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ From c00dd7e42974c623d080472c79747146863819d1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 27 Jul 2020 15:13:05 +0800 Subject: [PATCH 0279/2070] drm/amdkcl/dkms: check the prerequisites first fail early if DRM is disabled or DRM_AMDGPU is built-in. Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index cb38a2549c569..940586b3cebf1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,3 +1,11 @@ +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From bab846a95d7022bfba2ed3c7a38d37d966c9068e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 19 Aug 2020 15:16:19 +0800 Subject: [PATCH 0280/2070] drm/amdkcl/dkms: add dependency for CONFIG_KALLSYMS kallsyms_lookup_name() is a must for legacy kernel support. fail dkms install if CONFIG_KALLSYMS disabled. Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 940586b3cebf1..a23742b01fa26 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -6,6 +6,10 @@ ifeq (y,$(CONFIG_DRM_AMDGPU)) $(error DRM_AMDGPU is built-in, exit...) endif +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 3023dd8b95e710f847b59c41725135ff18b905eb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Oct 2020 13:47:30 +0800 Subject: [PATCH 0281/2070] drm/amdkcl/dkms: extract _is_kcl_macro_defined to check a macro defined in config.h Signed-off-by: Flora Cui Reviewed-by: shiwu.zhang --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a23742b01fa26..509625a2b36e0 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -10,6 +10,8 @@ ifndef CONFIG_KALLSYMS $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 3fd1ec753bdd5417de58ea78d7a880560a9d564a Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 28 Jul 2020 13:22:40 -0400 Subject: [PATCH 0282/2070] drm/amdkcl/dkms: Add warning when GCCs do not match v2 If the GCC used to compile the kernel doesn't match the current GCC on the system, print a warning to let the user know. This can hopefully help to find bugs from differing GCC versions causing unexpected and hard-to-track-down errors v2: Avoid quirks with cc-ifversion, don't hardcode gcc v3: drm/amdkcl: update the func to get gcc version get gcc version the same way with $(srctree)/scripts/gcc-version.sh can't leverage gcc-version.sh/gcc-version as the interface changes. the history for gcc-version.sh/gcc-version is: v5.6-12065-g77342a02ff6e gcc-plugins: drop support for GCC <= 4.7 v5.0-rc4-38-gfa7295ab69a3 kbuild: clean up scripts/gcc-version.sh v4.17-6942-g59f53855babf gcc-plugins: test plugin support in Kconfig and clean up Makefile v4.17-6936-ga4353898980c kconfig: add CC_IS_GCC and GCC_VERSION Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling Reviewed-by: Kent Russell Signed-off-by: Flora Cui Change-Id: Ibf64db43988609d8b48865d1eeee8efdc2ed98e2 --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 509625a2b36e0..8ca4f3cba1457 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,6 +12,18 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifdef CONFIG_CC_IS_GCC +GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) +GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +# CONFIG_GCC_VERSION returns x.xx.xx as the version format +GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) +ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) +$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") +$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") +endif +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 344d7349cb431109319b107abdff5dc3aa790630 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 22 Aug 2018 12:42:06 +0800 Subject: [PATCH 0283/2070] drm/amdkcl/dkms: enable CONFIG_HSA_AMD v1: 05b0848bf51c drm/amdkcl: [KFD] add kfd dkms support v2: 5fb3731bafd8 drm/amdkcl: fix amdkfd module confusion by correcting value of CONFIG_HSA_AMD v3: 77843fb3174f drm/amdkcl: add DKMS support for amdkfd module build in amdgpu. Signed-off-by: Kevin Wang Signed-off-by: changzhu Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Reviewed-by: Tianci Yin Reviewed-by: Xiaojie Yuan --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 8ca4f3cba1457..e147eaa68e72d 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -127,6 +127,7 @@ LINUXINCLUDE := \ -include $(src)/include/rename_symbol.h \ $(LINUXINCLUDE) +export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m @@ -136,6 +137,7 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y +subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From f6967cea296dd3a5cc660b1852251533a6d23c11 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Fri, 26 Jan 2018 10:27:17 +0800 Subject: [PATCH 0284/2070] drm/amdkcl/dkms: enable dcn2_x support in dkms Reviewed-by: Hawking Zhang Signed-off-by: Jack Xiao Signed-off-by: chen gong Reviewed-by: Roman Li Reviewed-by: changzhu Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index e147eaa68e72d..20c23f2ebf2fb 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -136,6 +136,7 @@ export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y +export CONFIG_DRM_AMD_DC_DCN2_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -143,5 +144,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 35b5aede217e0a2051b48c1b220cd0560b032f83 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Jun 2020 13:50:05 +0800 Subject: [PATCH 0285/2070] drm/amdkcl/dkms: enable dcn3_x in dkms package Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 20c23f2ebf2fb..4ed76a92cf2b1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -137,6 +137,7 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y export CONFIG_DRM_AMD_DC_DCN2_x=y +export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -145,5 +146,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 5276d8a9320df874ee92e3090ff5a60a33b08061 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 30 Jul 2020 09:18:22 -0400 Subject: [PATCH 0286/2070] drm/amdkcl/dkms: Guard DCN2/3 with regard to core2 These won't work with core2, so we can guard it for now until code consolidation takes place. This avoids a hack in packaging, and also makes transitioning to removing the DCN guards easier in the future Signed-off-by: Kent Russell Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4ed76a92cf2b1..ce753462ac58c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -136,8 +136,6 @@ export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y -export CONFIG_DRM_AMD_DC_DCN2_x=y -export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -145,7 +143,17 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 + + +# Trying to enable DCN2/3 with core2 optimizations will result in +# older versions of GCC hanging during building/installing. Check +# if the compiler is using core2 optimizations and only build DCN2/3 +# if core2 isn't in the compiler flags +ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) +export CONFIG_DRM_AMD_DC_DCN2_x=y +export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x +endif obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From f4e3d854ca6b0bd1d5c92e58219ee12bed8f740d Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 25 May 2018 16:51:17 -0400 Subject: [PATCH 0287/2070] drm/amdkcl/autoconf: Add initial autoconf framework to DKMS build Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu Change-Id: I6c9a8dd9e6eb51f40ef4c448038654c09372f200 --- drivers/gpu/drm/amd/dkms/Makefile | 2 + drivers/gpu/drm/amd/dkms/autogen.sh | 4 + drivers/gpu/drm/amd/dkms/config/install-sh | 508 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/configure.ac | 7 + drivers/gpu/drm/amd/dkms/pre-build.sh | 3 + 5 files changed, 524 insertions(+) create mode 100755 drivers/gpu/drm/amd/dkms/autogen.sh create mode 100755 drivers/gpu/drm/amd/dkms/config/install-sh create mode 100644 drivers/gpu/drm/amd/dkms/configure.ac diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ce753462ac58c..d628e1b4340ad 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,6 +120,8 @@ endif export OS_NAME OS_VERSION +subdir-ccflags-y += -include $(src)/config/config.h + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh new file mode 100755 index 0000000000000..992eac90a5a18 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +autoreconf -fiv +rm -Rf autom4te.cache diff --git a/drivers/gpu/drm/amd/dkms/config/install-sh b/drivers/gpu/drm/amd/dkms/config/install-sh new file mode 100755 index 0000000000000..59990a1049267 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/install-sh @@ -0,0 +1,508 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2014-09-12.12; # UTC + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# 'make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +tab=' ' +nl=' +' +IFS=" $tab$nl" + +# Set DOITPROG to "echo" to test this script. + +doit=${DOITPROG-} +doit_exec=${doit:-exec} + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +is_target_a_directory=possibly + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve the last data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -s $stripprog installed files. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *"$tab"* | *"$nl"* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -s) stripcmd=$stripprog;; + + -t) + is_target_a_directory=always + dst_arg=$2 + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + shift;; + + -T) is_target_a_directory=never;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +# We allow the use of options -d and -T together, by making -d +# take the precedence; this is for compatibility with GNU install. + +if test -n "$dir_arg"; then + if test -n "$dst_arg"; then + echo "$0: target directory not allowed when installing a directory." >&2 + exit 1 + fi +fi + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call 'install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + if test $# -gt 1 || test "$is_target_a_directory" = always; then + if test ! -d "$dst_arg"; then + echo "$0: $dst_arg: Is not a directory." >&2 + exit 1 + fi + fi +fi + +if test -z "$dir_arg"; then + do_exit='(exit $ret); exit $ret' + trap "ret=129; $do_exit" 1 + trap "ret=130; $do_exit" 2 + trap "ret=141; $do_exit" 13 + trap "ret=143; $do_exit" 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names problematic for 'test' and other utilities. + case $src in + -* | [=\(\)!]) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + dst=$dst_arg + + # If destination is a directory, append the input filename; won't work + # if double slashes aren't ignored. + if test -d "$dst"; then + if test "$is_target_a_directory" = never; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dst=$dstdir/`basename "$src"` + dstdir_status=0 + else + dstdir=`dirname "$dst"` + test -d "$dstdir" + dstdir_status=$? + fi + fi + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # Create intermediate dirs using mode 755 as modified by the umask. + # This is like FreeBSD 'install' as of 1997-10-28. + umask=`umask` + case $stripcmd.$umask in + # Optimize common cases. + *[2367][2367]) mkdir_umask=$umask;; + .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; + + *[0-7]) + mkdir_umask=`expr $umask + 22 \ + - $umask % 100 % 40 + $umask % 20 \ + - $umask % 10 % 4 + $umask % 2 + `;; + *) mkdir_umask=$umask,go-w;; + esac + + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + case $umask in + *[123567][0-7][0-7]) + # POSIX mkdir -p sets u+wx bits regardless of umask, which + # is incompatible with FreeBSD 'install' when (umask & 300) != 0. + ;; + *) + # $RANDOM is not portable (e.g. dash); use it when possible to + # lower collision chance + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + trap 'ret=$?; rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null; exit $ret' 0 + + # As "mkdir -p" follows symlinks and we work in /tmp possibly; so + # create the $tmpdir first (and fail if unsuccessful) to make sure + # that nobody tries to guess the $tmpdir name. + if (umask $mkdir_umask && + $mkdirprog $mkdir_mode "$tmpdir" && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + test_tmpdir="$tmpdir/a" + ls_ld_tmpdir=`ls -ld "$test_tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null + fi + trap '' 0;; + esac;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # The umask is ridiculous, or mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + [-=\(\)!]*) prefix='./';; + *) prefix='';; + esac + + oIFS=$IFS + IFS=/ + set -f + set fnord $dstdir + shift + set +f + IFS=$oIFS + + prefixes= + + for d + do + test X"$d" = X && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask=$mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=$dstdir/_inst.$$_ + rmtmp=$dstdir/_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + set +f && + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd -f "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac new file mode 100644 index 0000000000000..385dda9ac3bfc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -0,0 +1,7 @@ +AC_INIT(amdgpu-dkms, 19.40) +AC_LANG(C) +AC_CONFIG_AUX_DIR([config]) +AC_CONFIG_HEADERS([config/config.h]) +AC_PROG_INSTALL +AC_PROG_CC +AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 9fb471b43a708..070b72aedb1ab 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -56,3 +56,6 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done + +./autogen.sh +./configure From beeb68139f54218d73c5054d1e3fe1704358286d Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 1 Apr 2020 17:55:00 -0400 Subject: [PATCH 0288/2070] drm/amdkcl/autoconf: make autogen.sh script return status on exit Change-Id: I3248f3f121f28ac821802b25ccc0b2faca075ee7 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton --- drivers/gpu/drm/amd/dkms/autogen.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh index 992eac90a5a18..d72f86b5a2f97 100755 --- a/drivers/gpu/drm/amd/dkms/autogen.sh +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -1,4 +1,5 @@ #!/bin/bash autoreconf -fiv +[[ $? -eq 0 ]] || exit $? rm -Rf autom4te.cache From e517509e4ef0b1e7beb29c782fabda5cadc0e601 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 12 Feb 2020 09:56:54 -0500 Subject: [PATCH 0289/2070] drm/amdkcl/autoconf: use AC_CONFIG_MACRO_DIR macro to include m4 files Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/configure.ac | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 385dda9ac3bfc..ed144e0a2a235 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -4,4 +4,6 @@ AC_CONFIG_AUX_DIR([config]) AC_CONFIG_HEADERS([config/config.h]) AC_PROG_INSTALL AC_PROG_CC +AC_CONFIG_MACRO_DIR([m4]) + AC_OUTPUT From 6249784300044248d1c29b91e8f13a6dc4ecfe7a Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 29 May 2018 12:46:20 -0400 Subject: [PATCH 0290/2070] drm/amdkcl/autoconf: Add AC_KERNEL_TRY_COMPILE macro Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/configure.ac | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 212 ++++++++++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel.m4 diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index ed144e0a2a235..20954e53b8326 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,5 @@ AC_INIT(amdgpu-dkms, 19.40) + AC_LANG(C) AC_CONFIG_AUX_DIR([config]) AC_CONFIG_HEADERS([config/config.h]) @@ -6,4 +7,6 @@ AC_PROG_INSTALL AC_PROG_CC AC_CONFIG_MACRO_DIR([m4]) +AC_CONFIG_KERNEL + AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 new file mode 100644 index 0000000000000..50fe3cba42270 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -0,0 +1,212 @@ +dnl # +dnl # Default kernel configuration +dnl # +AC_DEFUN([AC_CONFIG_KERNEL], [ + AC_KERNEL + + AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ + KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" + ]) + + AC_SUBST(KERNEL_MAKE) +]) + +dnl # +dnl # Detect name used for Module.symvers file in kernel +dnl # +AC_DEFUN([AC_MODULE_SYMVERS], [ + modpost=$LINUX/scripts/Makefile.modpost + AC_MSG_CHECKING([kernel file name for module symbols]) + AS_IF([test "x$enable_linux_builtin" != xyes -a -f "$modpost"], [ + AS_IF([grep -q Modules.symvers $modpost], [ + LINUX_SYMBOLS=Modules.symvers + ], [ + LINUX_SYMBOLS=Module.symvers + ]) + + AS_IF([test ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed. If you are building with a custom kernel, make sure the + *** kernel is configured, built, and the '--with-linux=PATH' configure + *** option refers to the location of the kernel source.]) + ]) + ], [ + LINUX_SYMBOLS=NONE + ]) + AC_MSG_RESULT($LINUX_SYMBOLS) + AC_SUBST(LINUX_SYMBOLS) +]) + +dnl # +dnl # Detect the kernel to be built against +dnl # +AC_DEFUN([AC_KERNEL], [ + AC_ARG_WITH([linux], + AS_HELP_STRING([--with-linux=PATH], + [Path to kernel source]), + [kernelsrc="$withval"]) + + AC_ARG_WITH(linux-obj, + AS_HELP_STRING([--with-linux-obj=PATH], + [Path to kernel build objects]), + [kernelbuild="$withval"]) + + AC_MSG_CHECKING([kernel source directory]) + AS_IF([test -z "$kernelsrc"], [ + AS_IF([test -e "/lib/modules/$(uname -r)/source"], [ + headersdir="/lib/modules/$(uname -r)/source" + sourcelink=$(readlink -f "$headersdir") + ], [test -e "/lib/modules/$(uname -r)/build"], [ + headersdir="/lib/modules/$(uname -r)/build" + sourcelink=$(readlink -f "$headersdir") + ], [ + sourcelink=$(ls -1d /usr/src/kernels/* \ + /usr/src/linux-* \ + 2>/dev/null | grep -v obj | tail -1) + ]) + + AS_IF([test -n "$sourcelink" && test -e ${sourcelink}], [ + kernelsrc=`readlink -f ${sourcelink}` + ], [ + kernelsrc="[Not found]" + ]) + ], [ + AS_IF([test "$kernelsrc" = "NONE"], [ + kernsrcver=NONE + ]) + withlinux=yes + ]) + + AC_MSG_RESULT([$kernelsrc]) + AS_IF([test ! -d "$kernelsrc"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed and then try again. If that fails, you can specify the + *** location of the kernel source with the '--with-linux=PATH' option.]) + ]) + + AC_MSG_CHECKING([kernel build directory]) + AS_IF([test -z "$kernelbuild"], [ + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$(uname -r)/build"], [ + kernelbuild=`readlink -f /lib/modules/$(uname -r)/build` + ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} + ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/default + ], [test -d `dirname ${kernelsrc}`/build-${target_cpu}], [ + kernelbuild=`dirname ${kernelsrc}`/build-${target_cpu} + ], [ + kernelbuild=${kernelsrc} + ]) + ]) + AC_MSG_RESULT([$kernelbuild]) + + AC_MSG_CHECKING([kernel source version]) + utsrelease1=$kernelbuild/include/linux/version.h + utsrelease2=$kernelbuild/include/linux/utsrelease.h + utsrelease3=$kernelbuild/include/generated/utsrelease.h + AS_IF([test -r $utsrelease1 && fgrep -q UTS_RELEASE $utsrelease1], [ + utsrelease=linux/version.h + ], [test -r $utsrelease2 && fgrep -q UTS_RELEASE $utsrelease2], [ + utsrelease=linux/utsrelease.h + ], [test -r $utsrelease3 && fgrep -q UTS_RELEASE $utsrelease3], [ + utsrelease=generated/utsrelease.h + ]) + + AS_IF([test "$utsrelease"], [ + kernsrcver=`(echo "#include <$utsrelease>"; + echo "kernsrcver=UTS_RELEASE") | + cpp -I $kernelbuild/include | + grep "^kernsrcver=" | cut -d \" -f 2` + + AS_IF([test -z "$kernsrcver"], [ + AC_MSG_RESULT([Not found]) + AC_MSG_ERROR([*** Cannot determine kernel version.]) + ]) + ], [ + AC_MSG_RESULT([Not found]) + if test "x$enable_linux_builtin" != xyes; then + AC_MSG_ERROR([*** Cannot find UTS_RELEASE definition.]) + else + AC_MSG_ERROR([ + *** Cannot find UTS_RELEASE definition. + *** Please run 'make prepare' inside the kernel source tree.]) + fi + ]) + + AC_MSG_RESULT([$kernsrcver]) + + LINUX=${kernelsrc} + LINUX_OBJ=${kernelbuild} + LINUX_VERSION=${kernsrcver} + + AC_SUBST(LINUX) + AC_SUBST(LINUX_OBJ) + AC_SUBST(LINUX_VERSION) + + AC_MODULE_SYMVERS +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_H +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_H], [ +cat - <<_ACEOF >conftest.h +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_C +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_C], [ +cat confdefs.h - <<_ACEOF >conftest.c +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_LANG_PROGRAM(C)([PROLOGUE], [BODY]) +dnl # +AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ +$1 +int +main (void) +{ +dnl Do *not* indent the following line: there may be CPP directives. +dnl Don't move the `;' right after for the same reason. +$2 + ; + return 0; +} +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) + rm -Rf build && mkdir -p build && touch build/conftest.mod.c + echo "obj-m := conftest.o" >build/Makefile + modpost_flag='' + test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage + AS_IF( + [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror" M=$PWD/build $modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [$4], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] + ) + rm -Rf build +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE], + [AC_KERNEL_COMPILE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [modules], + [test -s build/conftest.o], + [$3], [$4]) +]) From 2b226ba774744315d219a370fbdf81c5c72618e6 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 1 Jun 2018 12:00:42 -0400 Subject: [PATCH 0291/2070] drm/amdkcl/autoconf: Add AC_AMDGPU_CONFIG macro with basic configuration it is a squash of: drm/amdkcl/autoconf: Add AC_AMDGPU_CONFIG macro with basic configuration Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang commit b979e488f77894bb89aee6424cd803f76f6d760d Author: Slava Grigorev Date: Wed Feb 12 09:56:54 2020 -0500 drm/amdkcl: use AC_CONFIG_MACRO_DIR macro to include m4 files Change-Id: I01581d410f6c45d41c40852ed44a0e451bbe8622 Signed-off-by: Slava Grigorev Change-Id: If3a07ed5064cc5cdddeb0abd0ce562be582d32ad --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- drivers/gpu/drm/amd/dkms/m4/config.m4 | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/config.m4 diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 20954e53b8326..b367e452d4cbb 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -7,6 +7,6 @@ AC_PROG_INSTALL AC_PROG_CC AC_CONFIG_MACRO_DIR([m4]) -AC_CONFIG_KERNEL +AC_AMDGPU_CONFIG AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 new file mode 100644 index 0000000000000..e22a4a49a5233 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_CONFIG], [ + AC_ARG_ENABLE([linux-builtin], + [AC_HELP_STRING([--enable-linux-builtin], + [Configure for builtin kernel modules @<:@default=no@:>@])], + [], + [enable_linux_builtin=no]) + + AC_CONFIG_KERNEL +]) From a9529b1d0a3b65f05e21a7bc59f3ebd077fcf487 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 3 Jun 2019 13:32:52 +0800 Subject: [PATCH 0292/2070] drm/amdkcl/autoconf: Add AC_KERNEL_TRY_COMPILE_SYMBOL macro v2: Correct AC_KERNEL_CHECK_SYMBOL_EXPORT macro to handle multiple symbols v3: Make 'AC_KERNEL_CHECK_SYMBOL_EXPORT' applicable to mawk Signed-off-by: Slava Grigorev Signed-off-by: chen gong Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 73 +++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 50fe3cba42270..05612f1db34fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -210,3 +210,76 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE], [test -s build/conftest.o], [$3], [$4]) ]) + +dnl # +dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # check symbol exported or not +dnl # +AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ + awk -v s="$1" ' + BEGIN { + n = 0; + num = split(s, symbols, " ") + } { + for (i in symbols) + if (symbols[[i]] == $[2]) + n++ + } END { + if (num == n) + exit 0; + else + exit 1 + }' $LINUX_OBJ/$LINUX_SYMBOLS 2>/dev/null + rc=$? + if test $rc -ne 0; then + n=0 + export=0 + for file in $2; do + n=$(awk -v s="$1" ' + BEGIN { + n = 0; + split(s, symbols, " ") + } { + for (i in symbols) { + s="EXPORT_SYMBOL.*"symbols[[i]]; + if ($[0] ~ s) + n++ + } + } END { + print n + }' $LINUX/$file 2>/dev/null) + rc=$? + if test $rc -eq 0; then + (( export+=n )) + fi + done + if test $(wc -w <<< "$1") -eq $export; then : + $3 + else : + $4 + fi + else : + $3 + fi +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE_SYMBOL +dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # is called if not compiling for builtin +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ + AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) + if test $rc -ne 0; then : + $6 + else + if test "x$enable_linux_builtin" != xyes; then + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) + fi + if test $rc -ne 0; then : + $6 + else : + $5 + fi + fi +]) From 33c2d5eb736210a551082421cba1ff2455f7c05d Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 5 Jul 2019 15:26:46 -0400 Subject: [PATCH 0293/2070] drm/amdkcl/autoconf: Drop autogen.sh call Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/pre-build.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 070b72aedb1ab..87b972dc63e5e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -57,5 +57,4 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done -./autogen.sh ./configure From 84aecd577a703bcdfade166fe7b6ca8b4333a110 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 8 Aug 2019 09:45:06 +0800 Subject: [PATCH 0294/2070] drm/amdkcl/autoconf: fix in-tree check for exported symbols Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 05612f1db34fa..3f79152c41c8d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,14 +17,14 @@ dnl # AC_DEFUN([AC_MODULE_SYMVERS], [ modpost=$LINUX/scripts/Makefile.modpost AC_MSG_CHECKING([kernel file name for module symbols]) - AS_IF([test "x$enable_linux_builtin" != xyes -a -f "$modpost"], [ + AS_IF([test -f "$modpost"], [ AS_IF([grep -q Modules.symvers $modpost], [ LINUX_SYMBOLS=Modules.symvers ], [ LINUX_SYMBOLS=Module.symvers ]) - AS_IF([test ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AS_IF([test "x$enable_linux_builtin" != xyes -a ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ AC_MSG_ERROR([ *** Please make sure the kernel devel package for your distribution *** is installed. If you are building with a custom kernel, make sure the @@ -273,9 +273,7 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ if test $rc -ne 0; then : $6 else - if test "x$enable_linux_builtin" != xyes; then - AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) - fi + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) if test $rc -ne 0; then : $6 else : From c2f4f6d00ea14e7cc939536724f3f924a18dbb43 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Thu, 8 Aug 2019 09:43:50 +0800 Subject: [PATCH 0295/2070] drm/amdkcl/autoconf: fix awk syntax error this could fix in-tree build error on ubuntu16.04.4 Signed-off-by: Adam Yang Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3f79152c41c8d..b2fb779404579 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -241,7 +241,7 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ split(s, symbols, " ") } { for (i in symbols) { - s="EXPORT_SYMBOL.*"symbols[[i]]; + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\);" if ($[0] ~ s) n++ } From 7347852499872be8058a253b01402c88d02895ef Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 25 Jul 2019 16:10:42 +0800 Subject: [PATCH 0296/2070] drm/amdkcl/autoconf: fix dkms build kernel version check the original behavior install dkms package with the current kernel, which is not expected. Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 12 ++++++------ drivers/gpu/drm/amd/dkms/pre-build.sh | 1 + 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b2fb779404579..fd06f6ee28951 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -54,11 +54,11 @@ AC_DEFUN([AC_KERNEL], [ AC_MSG_CHECKING([kernel source directory]) AS_IF([test -z "$kernelsrc"], [ - AS_IF([test -e "/lib/modules/$(uname -r)/source"], [ - headersdir="/lib/modules/$(uname -r)/source" + AS_IF([test -e "/lib/modules/$KERNELVER/source"], [ + headersdir="/lib/modules/$KERNELVER/source" sourcelink=$(readlink -f "$headersdir") - ], [test -e "/lib/modules/$(uname -r)/build"], [ - headersdir="/lib/modules/$(uname -r)/build" + ], [test -e "/lib/modules/$KERNELVER/build"], [ + headersdir="/lib/modules/$KERNELVER/build" sourcelink=$(readlink -f "$headersdir") ], [ sourcelink=$(ls -1d /usr/src/kernels/* \ @@ -88,8 +88,8 @@ AC_DEFUN([AC_KERNEL], [ AC_MSG_CHECKING([kernel build directory]) AS_IF([test -z "$kernelbuild"], [ - AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$(uname -r)/build"], [ - kernelbuild=`readlink -f /lib/modules/$(uname -r)/build` + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$KERNELVER/build"], [ + kernelbuild=`readlink -f /lib/modules/$KERNELVER/build` ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 87b972dc63e5e..264b42dd2af4d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -57,4 +57,5 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done +export KERNELVER ./configure From ceb13ffba2a0ce48d02f1b2e48b4608ce83611f0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 30 Jul 2019 14:03:13 +0800 Subject: [PATCH 0297/2070] drm/amdkcl/autoconf: add documentation for autoconf macros Add documentation for AC_KERNEL_* macros. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fd06f6ee28951..ea4b86472c6e4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -150,6 +150,7 @@ AC_DEFUN([AC_KERNEL], [ dnl # dnl # AC_KERNEL_CONFTEST_H +dnl # $1: contents to be filled in conftest.h dnl # AC_DEFUN([AC_KERNEL_CONFTEST_H], [ cat - <<_ACEOF >conftest.h @@ -159,6 +160,8 @@ _ACEOF dnl # dnl # AC_KERNEL_CONFTEST_C +dnl # fill in contents of conftest.h and $1 to conftest.c +dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ cat confdefs.h - <<_ACEOF >conftest.c @@ -167,7 +170,7 @@ _ACEOF ]) dnl # -dnl # AC_KERNEL_LANG_PROGRAM(C)([PROLOGUE], [BODY]) +dnl # AC_KERNEL_LANG_PROGRAM([PROLOGUE], [BODY]) dnl # AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ $1 @@ -184,6 +187,12 @@ $2 dnl # dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: make target. "modules" for most case +dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $4: run it if make & $3 pass. +dnl # $5: run it if make & $3 fail. +dnl # $6: contents to be filled in conftest.h. Could be null. dnl # AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) @@ -202,6 +211,10 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ dnl # dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], [AC_KERNEL_COMPILE_IFELSE( @@ -214,6 +227,10 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE], dnl # dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT dnl # check symbol exported or not +dnl # $1: symbol list to look for +dnl # $2: file list to look for $1 +dnl # $3: run it if pass. +dnl # $4: run it if fail. dnl # AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ awk -v s="$1" ' @@ -267,6 +284,12 @@ dnl # dnl # AC_KERNEL_TRY_COMPILE_SYMBOL dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT dnl # is called if not compiling for builtin +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: AC_KERNEL_CHECK_SYMBOL_EXPORT $1 +dnl # $4: AC_KERNEL_CHECK_SYMBOL_EXPORT $2 +dnl # $5: run it if checking pass +dnl # $6: run it if checking fail dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) From aed843d4bba18faf0d3e28971b4219d36ea0cc2e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 26 Jul 2019 11:28:47 +0800 Subject: [PATCH 0298/2070] drm/amdkcl/autoconf: add more flags to compile conftest v1: b1c3905f5703 drm/amdkcl/autoconf: make uninitialized warning not error v2: ab8d6b1a69d6 drm/amdkcl/autoconf: add more flags to compile conftest Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ea4b86472c6e4..d491a3d205ded 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -202,7 +202,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ modpost_flag='' test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage AS_IF( - [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror" M=$PWD/build $modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD/build $modpost_flag $kbuild_src_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From f0414ebc592484630ad6fe2565086f1f7256c34f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 1 Aug 2019 17:27:15 +0800 Subject: [PATCH 0299/2070] drm/amdkcl/autoconf: add AC_KERNEL_TEST_HEADER_FILE_EXIST macro AC_KERNEL_TEST_HEADER_FILE_EXIST is added to detect whether the desired header file is available. It could save dkms install time. and could help to avoid errors that the depent header files missing in conftest.c due to kernel version changes. v1: 77102303c630 drm/amd/autoconf: add AC_KERNEL_TEST_HEADER_FILE_EXIST v2: ecb0feb54350 drm/amd/autoconf: fix test header exists error in SLED15.1 v3: bae172b63d85 drm/amd/autoconf: fix AC_KERNEL_TEST_HEADER_FILE_EXIST() Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Reviewed-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d491a3d205ded..75cf807577c7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -304,3 +304,21 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ fi fi ]) + +dnl # +dnl # AC_KERNEL_TEST_HEADER_FILE_EXIST +dnl # check header file exist +dnl # $1: header file to check +dnl # $2: run it if header file exist +dnl # $3: run it if header file nonexistent +dnl # +AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ + header_file=m4_normalize([$1]) + header_file_obj=$LINUX_OBJ/include/$header_file + header_file_src=$LINUX/include/$header_file + AS_IF([test -e $header_file_obj -o -e $header_file_src], [ + $2 + ], [ + $3 + ]) +]) From 8f40b0cf9dd00e7459558d44f5c7b337bc3e74ec Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Apr 2020 10:55:37 +0800 Subject: [PATCH 0300/2070] drm/amdkcl/autoconf: introduce parallel autoconf tests execution Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 69 +++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 75cf807577c7c..7f07aafc7cc59 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" ]) @@ -164,7 +165,7 @@ dnl # fill in contents of conftest.h and $1 to conftest.c dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ -cat confdefs.h - <<_ACEOF >conftest.c +cat $ac_build_root_dir/confdefs.h - <<_ACEOF >conftest.c $1 _ACEOF ]) @@ -197,16 +198,34 @@ dnl # AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) - rm -Rf build && mkdir -p build && touch build/conftest.mod.c - echo "obj-m := conftest.o" >build/Makefile - modpost_flag='' - test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage + touch conftest.mod.c + echo "obj-m := conftest.o" >Makefile + kbuild_src_flag='' + kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' + kbuild_workaround_flag='' + test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC + test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD/build $modpost_flag $kbuild_src_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) - rm -Rf build +]) + +dnl # +dnl # AC_KERNEL_TMP_BUILD_DIR +dnl # $1: contents to be executed in a temporary directory +dnl # +AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ + local build_dir=$(mktemp -d -t build-XXXXXXXX -p .) + pushd $build_dir >/dev/null + $1 + build_dir=$PWD + popd >/dev/null + AS_IF([test -s $build_dir/confdefs.h], [ + cat $build_dir/confdefs.h >>$ac_build_root_dir/confdefs.h + ]) + rm -rf $build_dir ]) dnl # @@ -217,11 +236,15 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], + target='modules' + test "x$enable_linux_builtin" = xyes && target='conftest.o' + [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [modules], - [test -s build/conftest.o], + [$target], + [test -s conftest.o], [$3], [$4]) + ]) ]) dnl # @@ -322,3 +345,31 @@ AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ $3 ]) ]) + +dnl # +dnl # AC_KERNEL_DO_BACKGROUND +dnl # $1: contents to be executed +dnl # +AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ + do_background() { + $1 + } + do_background & + procs+=( "$!" ) +]) + +dnl # +dnl # AC_KERNEL_WAIT +dnl # wait for all tests to be finished +dnl # +AC_DEFUN([AC_KERNEL_WAIT], [ + AC_MSG_CHECKING([for module configuration]) + wait ${procs[[@]]} + AS_IF([[[ $? -eq 0 ]]], [ + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) + +ac_build_root_dir=$PWD From fa3a142bf414fac5ff2c1f2fb2896d4d6f9d5e74 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 22 Jul 2020 10:39:05 +0800 Subject: [PATCH 0301/2070] drm/amdkcl/autoconf: drop compile target for conftest use the default one Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7f07aafc7cc59..7fd72165bb096 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,7 +189,7 @@ $2 dnl # dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE dnl # $1: contents to be filled in conftest.c -dnl # $2: make target. "modules" for most case +dnl # $2: make target. dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. dnl # $4: run it if make & $3 pass. dnl # $5: run it if make & $3 fail. @@ -236,7 +236,7 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='modules' + target='' test "x$enable_linux_builtin" = xyes && target='conftest.o' [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( From abf662cf258e14493fbaa32fc7a7daf243f91d1e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 13 Feb 2020 12:43:57 -0500 Subject: [PATCH 0302/2070] drm/amdkcl/autoconf: properly define the root of the build directories Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7fd72165bb096..9f789fb192974 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_KERNEL], [ LINUX=${kernelsrc} LINUX_OBJ=${kernelbuild} LINUX_VERSION=${kernsrcver} + build_dir_root=$(cd "${0%/*}" && pwd) AC_SUBST(LINUX) AC_SUBST(LINUX_OBJ) @@ -165,7 +166,7 @@ dnl # fill in contents of conftest.h and $1 to conftest.c dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ -cat $ac_build_root_dir/confdefs.h - <<_ACEOF >conftest.c +cat $build_dir_root/confdefs.h - <<_ACEOF >conftest.c $1 _ACEOF ]) @@ -223,7 +224,7 @@ AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ build_dir=$PWD popd >/dev/null AS_IF([test -s $build_dir/confdefs.h], [ - cat $build_dir/confdefs.h >>$ac_build_root_dir/confdefs.h + cat $build_dir/confdefs.h >>$build_dir_root/confdefs.h ]) rm -rf $build_dir ]) @@ -371,5 +372,3 @@ AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_RESULT([failed]) ]) ]) - -ac_build_root_dir=$PWD From 0b65acadee2c85816730b80f573d3cf064c44081 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 14 Feb 2020 22:28:57 -0500 Subject: [PATCH 0303/2070] drm/amdkcl/autoconf: fix background function execution Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f789fb192974..fc1ec9b67a109 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -239,13 +239,11 @@ dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], target='' test "x$enable_linux_builtin" = xyes && target='conftest.o' - [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], [$target], [test -s conftest.o], [$3], [$4]) - ]) ]) dnl # @@ -353,7 +351,7 @@ dnl # $1: contents to be executed dnl # AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ do_background() { - $1 + AC_KERNEL_TMP_BUILD_DIR([$1]) } do_background & procs+=( "$!" ) From f500c21e8025f5c616bccc7bf6586e6f989e547f Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 2 Dec 2019 10:37:07 +0800 Subject: [PATCH 0304/2070] drm/amdkcl/autoconf: remove bash specific commands squash of 9b50ddbd026a drm/amdkcl/autoconf: remove bash specific commands 4d0397689a82 drm/amdkcl/autoconf: fix in-tree failure for v5.4 Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fc1ec9b67a109..ed40d9a3728a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,14 +218,13 @@ dnl # AC_KERNEL_TMP_BUILD_DIR dnl # $1: contents to be executed in a temporary directory dnl # AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ - local build_dir=$(mktemp -d -t build-XXXXXXXX -p .) - pushd $build_dir >/dev/null + build_dir=$(mktemp -d -t build-XXXXXXXX -p $build_dir_root) + cd $build_dir $1 - build_dir=$PWD - popd >/dev/null - AS_IF([test -s $build_dir/confdefs.h], [ - cat $build_dir/confdefs.h >>$build_dir_root/confdefs.h + AS_IF([test -s confdefs.h], [ + cat confdefs.h >>$build_dir_root/confdefs.h ]) + cd $build_dir_root rm -rf $build_dir ]) @@ -289,10 +288,10 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ }' $LINUX/$file 2>/dev/null) rc=$? if test $rc -eq 0; then - (( export+=n )) + export=$(( $export+$n )) fi done - if test $(wc -w <<< "$1") -eq $export; then : + if test $(echo "$1" | wc -w) -eq $export; then : $3 else : $4 @@ -354,7 +353,7 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ AC_KERNEL_TMP_BUILD_DIR([$1]) } do_background & - procs+=( "$!" ) + procs="$! $procs" ]) dnl # @@ -363,7 +362,7 @@ dnl # wait for all tests to be finished dnl # AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_CHECKING([for module configuration]) - wait ${procs[[@]]} + wait $procs AS_IF([[[ $? -eq 0 ]]], [ AC_MSG_RESULT([done]) ], [ From 56aeafd2b87cfbee4e7fef4c7a046a7014c95a25 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Apr 2020 11:10:41 +0800 Subject: [PATCH 0305/2070] drm/amdkcl/autoconf: add AC_KERNEL_CHECK_HEADERS macro The macro uses autoconf AC_CHECK_HEADER to find kernel header files by using the preprocessor Squash of c1b19bb1c3cd drm/amdkcl: fix SUSE DKMS build a67541030f43 drm/amdkcl/autoconf: add AC_KERNEL_CHECK_HEADERS macro Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 9 +++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 23 ++++++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed40d9a3728a8..0f35e04f1f51c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -344,6 +344,15 @@ AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ ]) ]) +dnl # +dnl # AC_KERNEL_CHECK_HEADERS +dnl # check whether header file(s) is(are) present +dnl # $1: header filei(s) to check +dnl # +AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ + AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) +]) + dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 264b42dd2af4d..7d1dca12d6f33 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,6 +6,21 @@ SRC="amd/dkms" KERNELVER=$1 KERNELVER_BASE=${KERNELVER%%-*} +SRCTREE=/lib/modules/$KERNELVER + +if [ -L $SRCTREE/source ]; then + BLDTREE="$SRCTREE/build" + SRCTREE="$SRCTREE/source" +else + SRCTREE="$SRCTREE/build" + BLDTREE="$SRCTREE" +fi + +SRCARCH=$(uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ + -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ + -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ + -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ + -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") version_lt () { newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) @@ -58,4 +73,10 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -./configure +CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ + -I$BLDTREE/arch/$SRCARCH/include/generated \ + -I$SRCTREE/include \ + -I$BLDTREE/include \ + -I$SRCTREE/include/uapi \ + -include linux/kconfig.h" \ + ./configure From b69f11ae6639a8ae8cb58e22b1b9da3b69352a98 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 10 Mar 2020 13:49:38 -0400 Subject: [PATCH 0306/2070] drm/amdkcl/autoconf: add Makefile.config to DKMS code The Makefile helps developers to regenerate config.h file after changes made to either configure.ac or .m4 files Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/Makefile.config | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.config diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config new file mode 100644 index 0000000000000..2b1a73c63bee3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -0,0 +1,40 @@ +dkmstree := drivers/gpu/drm/amd/dkms +srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) + +srcarch := $(shell uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ + -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ + -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ + -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ + -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") + +userinclude := \ + -I$(srctree)/arch/$(srcarch)/include/uapi \ + -I$(srctree)/arch/$(srcarch)/include/generated/uapi \ + -I$(srctree)/include/uapi \ + -I$(srctree)/include/generated/uapi \ + -include $(srctree)/include/linux/kconfig.h + +linuxinclude := \ + -I$(srctree)/arch/$(srcarch)/include \ + -I$(srctree)/arch/$(srcarch)/include/generated \ + -I$(srctree)/include \ + $(userinclude) + +all: config clean + +config: force + @( \ + cd $(srctree)/$(dkmstree); \ + ./autogen.sh; \ + CPPFLAGS="$(linuxinclude)" ./configure \ + --enable-linux-builtin \ + --with-linux=$(srctree) \ + ) + +clean: force + @( \ + cd $(srctree)/$(dkmstree); \ + rm -f aclocal.m4 config.* configure config/*.in* \ + ) + +.PHONY: all force From 0b217efc65bf49fcdad05ce6788f252a18ee15c4 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 11 Mar 2020 18:13:25 -0400 Subject: [PATCH 0307/2070] drm/amdkcl/autoconf: properly define and initialize Makefile variables 1. Properly define ..._FULL_PATH variables in amdgpu, ttm, and scheduler trees. That fixes 'make -C ... M=... modiles' build to succeed correctly. 2. Cleanup of the DKMS Makefile and modified DKMS pre-build.sh script to execute 'configure' from the original directory location It's a squash of 65727463b0e9 drm/ttm,scheduler,amdgpu: properly define and initialize Makefile variables db30b3d31f5f amd/amdkcl: fix Makefile include paths 08ebd9dfa583 amd/amdkcl: use relative path in DKMS pre-build.sh Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 6 +++--- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms.conf | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index da0b26ac84f70..7d5a4565831c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -24,8 +24,8 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) -DISPLAY_FOLDER_NAME=display -FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) +DISPLAY_FOLDER_NAME := display +FULL_AMD_DISPLAY_PATH := $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ @@ -321,7 +321,7 @@ amdgpu-y += $(AMD_POWERPLAY_FILES) ifneq ($(CONFIG_DRM_AMD_DC),) -RELATIVE_AMD_DISPLAY_PATH = ../$(DISPLAY_FOLDER_NAME) +RELATIVE_AMD_DISPLAY_PATH := ../$(DISPLAY_FOLDER_NAME) include $(FULL_AMD_DISPLAY_PATH)/Makefile amdgpu-y += $(AMD_DISPLAY_FILES) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index d628e1b4340ad..f960a4375859e 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,7 +120,7 @@ endif export OS_NAME OS_VERSION -subdir-ccflags-y += -include $(src)/config/config.h +subdir-ccflags-y += -include $(src)/amd/dkms/config/config.h LINUXINCLUDE := \ -I$(src)/include \ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 86826daa80072..7a6075f32cb5a 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,7 +2,7 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" REMAKE_INITRD="yes" -PRE_BUILD="pre-build.sh $kernelver" +PRE_BUILD="amd/dkms/pre-build.sh $kernelver" # not work with RHEL DKMS #MODULES_CONF[0]="blacklist radeon" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7d1dca12d6f33..a6be48877eec8 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -73,10 +73,10 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ +(cd $SRC && CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ -I$BLDTREE/arch/$SRCARCH/include/generated \ -I$SRCTREE/include \ -I$BLDTREE/include \ -I$SRCTREE/include/uapi \ - -include linux/kconfig.h" \ - ./configure + -include $SRCTREE/include/linux/kconfig.h" \ + ./configure) From 7b80c96f114be42f8f02e258b2ff8c392544abd5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 8 Jan 2021 10:29:46 +0800 Subject: [PATCH 0308/2070] drm/amdkcl/autoconf: build conftest.o directly no need to build a module v2: detect single target build capability in autoconf test instead of grep Makefile directly. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 ++++++-- .../gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f35e04f1f51c..51e88cfc25d17 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -3,6 +3,7 @@ dnl # Default kernel configuration dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL + AC_KERNEL_SINGLE_TARGET AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ @@ -200,6 +201,10 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) touch conftest.mod.c + if test "x$SINGLE_TARGET_BUILD_NO_TMP_VERSIONS" = x1; then + test -d $SINGLE_TARGET_BUILD_MODVERDIR || mkdir $SINGLE_TARGET_BUILD_MODVERDIR + rm -f $SINGLE_TARGET_BUILD_MODVERDIR/* + fi echo "obj-m := conftest.o" >Makefile kbuild_src_flag='' kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' @@ -236,8 +241,7 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='' - test "x$enable_linux_builtin" = xyes && target='conftest.o' + target='conftest.o' [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], [$target], diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 new file mode 100644 index 0000000000000..6793169a5624d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.20-rc2-10-ge07db28eea38 +dnl # kbuild: fix single target build for external module +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ + AC_KERNEL_TMP_BUILD_DIR([ + AC_KERNEL_TRY_COMPILE([], [], [], [ + SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions + AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ + SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 + ], [ + AC_MSG_WARN([compile single target fail expectedly]) + ]) + ]) + ]) +]) From 97bfbb06655be71cfd2da3a5faa0b48c45184f00 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Jan 2021 14:12:52 +0800 Subject: [PATCH 0309/2070] drm/amdkcl/autoconf: extract cc&&cppflags to test header files Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.config | 21 +---------- .../drm/amd/dkms/m4/kernel_single_target.m4 | 36 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 23 +----------- 3 files changed, 38 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config index 2b1a73c63bee3..f6d23defbaae6 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.config +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -1,32 +1,13 @@ dkmstree := drivers/gpu/drm/amd/dkms srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) -srcarch := $(shell uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ - -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ - -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ - -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ - -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") - -userinclude := \ - -I$(srctree)/arch/$(srcarch)/include/uapi \ - -I$(srctree)/arch/$(srcarch)/include/generated/uapi \ - -I$(srctree)/include/uapi \ - -I$(srctree)/include/generated/uapi \ - -include $(srctree)/include/linux/kconfig.h - -linuxinclude := \ - -I$(srctree)/arch/$(srcarch)/include \ - -I$(srctree)/arch/$(srcarch)/include/generated \ - -I$(srctree)/include \ - $(userinclude) - all: config clean config: force @( \ cd $(srctree)/$(dkmstree); \ ./autogen.sh; \ - CPPFLAGS="$(linuxinclude)" ./configure \ + ./configure \ --enable-linux-builtin \ --with-linux=$(srctree) \ ) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 6793169a5624d..ca2404840d5cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -1,3 +1,38 @@ +dnl # +dnl # extract cc, cflags, cppflags +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ + AS_IF([test -s .conftest.o.cmd], [ + _base_cflags="-DKBUILD_BASENAME='\"conftest\"' -DKBUILD_MODNAME='\"conftest\"'" + _base_dir=$(basename $PWD) + _conftest_cmd=$(head -1 .conftest.o.cmd) + + CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CFLAGS=$(echo $_conftest_cmd | \ + sed -e 's| -|\n&|g' | \ + sed -e "s|\./|${LINUX_OBJ}/|" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|" \ + -e '/conftest/d' \ + -e '/KBUILD_/d' \ + -e "/$_base_dir/d" | \ + xargs) + CPPFLAGS=$(echo $CFLAGS | \ + sed 's| -|\n&|g' | \ + sed -n '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + xargs) + + CFLAGS="$CFLAGS $_base_cflags" + CPPFLAGS="$CPPFLAGS $_base_cflags" + + AC_SUBST(CC) + AC_SUBST(CFLAGS) + AC_SUBST(CPPFLAGS) + ], [ + AC_MSG_ERROR([cannot detect CFLAGS...]) + ]) +]) + dnl # dnl # v4.20-rc2-10-ge07db28eea38 dnl # kbuild: fix single target build for external module @@ -12,5 +47,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ AC_MSG_WARN([compile single target fail expectedly]) ]) ]) + AC_KERNEL_SINGLE_TARGET_CFLAGS ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index a6be48877eec8..b87289082387a 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,21 +6,6 @@ SRC="amd/dkms" KERNELVER=$1 KERNELVER_BASE=${KERNELVER%%-*} -SRCTREE=/lib/modules/$KERNELVER - -if [ -L $SRCTREE/source ]; then - BLDTREE="$SRCTREE/build" - SRCTREE="$SRCTREE/source" -else - SRCTREE="$SRCTREE/build" - BLDTREE="$SRCTREE" -fi - -SRCARCH=$(uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ - -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ - -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ - -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ - -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") version_lt () { newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) @@ -73,10 +58,4 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -(cd $SRC && CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ - -I$BLDTREE/arch/$SRCARCH/include/generated \ - -I$SRCTREE/include \ - -I$BLDTREE/include \ - -I$SRCTREE/include/uapi \ - -include $SRCTREE/include/linux/kconfig.h" \ - ./configure) +(cd $SRC && ./configure) From d79dc6978a1a0fa90fd17be10b9779bf5b6b3500 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Jan 2021 14:58:12 +0800 Subject: [PATCH 0310/2070] drm/amdkcl/autoconf: extract cflags to compile contest.o directly Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 39 +++++++++++++++++-- .../drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 51e88cfc25d17..0593e48224aaa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,7 +189,7 @@ $2 ]) dnl # -dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # AC_KERNEL_COMPILE_MODULE_IFELSE / like AC_COMPILE_IFELSE dnl # $1: contents to be filled in conftest.c dnl # $2: make target. dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. @@ -197,7 +197,7 @@ dnl # $4: run it if make & $3 pass. dnl # $5: run it if make & $3 fail. dnl # $6: contents to be filled in conftest.h. Could be null. dnl # -AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ +AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) touch conftest.mod.c @@ -233,6 +233,39 @@ AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ rm -rf $build_dir ]) +dnl # +dnl # AC_KERNEL_TRY_COMPILE_MODULE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_MODULE], + target='conftest.o' + [AC_KERNEL_COMPILE_MODULE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [$target], + [test -s conftest.o], + [$3], [$4]) +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $3: run it if make & $3 pass. +dnl # $4: run it if make & $3 fail. +dnl # $5: contents to be filled in conftest.h. Could be null. +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) + AS_IF( + [AC_TRY_COMMAND($CC $CFLAGS -o conftest.o conftest.c) >/dev/null && AC_TRY_COMMAND([$2])], + [$3], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] + ) +]) dnl # dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE dnl # $1: Prologue for conftest.c. including header files, extends, etc @@ -241,10 +274,8 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='conftest.o' [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [$target], [test -s conftest.o], [$3], [$4]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index ca2404840d5cb..7eb3fe010ee93 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -39,7 +39,7 @@ dnl # kbuild: fix single target build for external module dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ AC_KERNEL_TMP_BUILD_DIR([ - AC_KERNEL_TRY_COMPILE([], [], [], [ + AC_KERNEL_TRY_COMPILE_MODULE([], [], [], [ SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 From 05b6bc194288ef6ae033e9f7e61522708fbb8e21 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 13 Jan 2021 14:18:20 +0800 Subject: [PATCH 0311/2070] drm/amdkcl/autoconf: rework *FLAGS_.o handle of path Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 7eb3fe010ee93..b4af835c8928f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -33,6 +33,17 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ ]) ]) +dnl # +dnl # v5.3-rc4-54-g54b8ae66ae1a +dnl # kbuild: change *FLAGS_.o to take the path relative to $(obj) +dnl # +AC_DEFUN([AC_KERNEL_FLAGS_TAKE_PATH], [ + AS_IF([grep -qsm 1 "target-stem" ${LINUX}/scripts/Makefile.lib], [ + AC_DEFINE(HAVE_AMDKCL_FLAGS_TAKE_PATH, 1, + [*FLAGS_.o support to take the path relative to $(obj)]) + ]) +]) + dnl # dnl # v4.20-rc2-10-ge07db28eea38 dnl # kbuild: fix single target build for external module @@ -48,5 +59,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ ]) ]) AC_KERNEL_SINGLE_TARGET_CFLAGS + AC_KERNEL_FLAGS_TAKE_PATH ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index b87289082387a..745124a028bc7 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -59,3 +59,10 @@ done export KERNELVER (cd $SRC && ./configure) + +# rename CFLAGS_target.o to CFLAGS_target.o +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file + done +fi From 13cb6d385c697fb6c215fc6858b31bb11546b3d8 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Mar 2020 19:24:29 -0400 Subject: [PATCH 0312/2070] drm/amdkcl/autoconf: add includes config.h in Makefile It's a squash of 70619a89cb10 amd/amdkcl: drop BUILD_AS_DKMS compilation flag 9bdcf23b7b68 drm/amdkcl: drop DKMS build when in the source tree 4304e2beb859 amd/amdkcl: clean up includes in backport/Makefile Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 5 +++++ drivers/gpu/drm/amd/backport/Makefile | 7 ++++++- drivers/gpu/drm/amd/dkms/Makefile | 2 -- drivers/gpu/drm/scheduler/backport/Makefile | 2 ++ drivers/gpu/drm/ttm/backport/Makefile | 4 ++++ 5 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 018792c49a249..5dcd2f97fc29b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,4 +1,9 @@ # SPDX-License-Identifier: MIT amdkcl-y += main.o +ccflags-y += \ + -include $(src)/../dkms/config/config.h + +ccflags-y += -DHAVE_CONFIG_H + obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index ca667992f6f72..1ad8a02a4b19f 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -4,5 +4,10 @@ BACKPORT_OBJS := amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) ccflags-y += \ + -I$(FULL_AMD_PATH) \ -I$(FULL_AMD_PATH)/backport/include \ - -include ../backport/backport.h + -I$(FULL_AMD_PATH)/dkms \ + -include config/config.h \ + -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f960a4375859e..ce753462ac58c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,8 +120,6 @@ endif export OS_NAME OS_VERSION -subdir-ccflags-y += -include $(src)/amd/dkms/config/config.h - LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/drivers/gpu/drm/scheduler/backport/Makefile b/drivers/gpu/drm/scheduler/backport/Makefile index 5fe7a0b580f33..01bf391770a05 100644 --- a/drivers/gpu/drm/scheduler/backport/Makefile +++ b/drivers/gpu/drm/scheduler/backport/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: MIT ccflags-y += \ -I$(SCHED_FULL_PATH) \ + -I$(SCHED_FULL_PATH)/../amd/dkms \ + -include config/config.h \ -include backport/backport.h diff --git a/drivers/gpu/drm/ttm/backport/Makefile b/drivers/gpu/drm/ttm/backport/Makefile index 839110332c785..0ccfec344b665 100644 --- a/drivers/gpu/drm/ttm/backport/Makefile +++ b/drivers/gpu/drm/ttm/backport/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: MIT ccflags-y += \ -I$(TTM_FULL_PATH) \ + -I$(TTM_FULL_PATH)/../amd/dkms \ + -include config/config.h \ -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H From 6d87fdb3f359c18a984a0ce55362605e7f9768ba Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 20 Jan 2021 17:58:01 +0800 Subject: [PATCH 0313/2070] drm/amdkcl/dkms: fix include path for dkms package Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ce753462ac58c..7c227452be97c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,12 +120,20 @@ endif export OS_NAME OS_VERSION +LINUX_SRCTREE_INCLUDE := \ + $(filter-out -I%/uapi -include %/kconfig.h,$(LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(LINUXINCLUDE)) + LINUXINCLUDE := \ -I$(src)/include \ - -I$(src)/include/uapi \ + -I$(src)/include/kcl/header \ -include $(src)/include/kcl/kcl_version.h \ -include $(src)/include/rename_symbol.h \ - $(LINUXINCLUDE) + -include $(src)/amd/dkms/config/config.h \ + $(LINUX_SRCTREE_INCLUDE) \ + -I$(src)/include/uapi \ + -I$(src)/include/kcl/header/uapi \ + $(USER_INCLUDE) export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m From c2ae0be561773064362ad45922e819113dc5468f Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Fri, 9 Mar 2018 11:23:15 -0500 Subject: [PATCH 0314/2070] drm/amdkcl/dkms: Add wattman example script Signed-off-by: Jeremy Newton Acked-by: Slava Grigorev --- .../dkms/docs/examples/wattman-example-script | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script diff --git a/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script new file mode 100644 index 0000000000000..90b14faec6dbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script @@ -0,0 +1,74 @@ +## wattman-like functionality +# boot with amdgpu.ppfeaturemask=0xffffffff (make sure PP_OVERDRIVE_MASK bit is set see hwmgr.h) +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 917Mhz 1175 mV +#6: 949Mhz 1175 mV +#7: 973Mhz 1175 mV +#OD_MCLK: +#0: 150Mhz 900 mV +#1: 1375Mhz 975 mV +# change mclk dpm level 0 from 150 to 155Mhz, no change to voltage +# format is "m dpm_level clock_in_mhz voltage_in_mv" +echo "m 0 155 900" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 7 from 973 to 975Mhz, change voltage from 1175 to 1180 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 975 1180" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 5 from 917 to 910Mhz, change voltage from 1175 to 1160 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 910 1160" > /sys/class/drm/card0/device/pp_od_clk_voltage +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 910Mhz 1160 mV +#6: 949Mhz 1175 mV +#7: 975Mhz 1180 mV +#OD_MCLK: +#0: 155Mhz 900 mV +#1: 1375Mhz 975 mV +# commit the changes to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage +# reset to the default dpm states +echo "r" > /sys/class/drm/card0/device/pp_od_clk_voltage +# commit the reset state to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage + +## reading/adjusting hwmon values +# https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface +# see which hwmon device this is +cat /sys/class/hwmon/hwmon0/name +# readback current vddgfx/vddnb voltages +# see which one this is +cat /sys/class/hwmon/hwmon0/in0_label +# read the voltage (mV) +cat /sys/class/hwmon/hwmon0/in0_input +# see current power (microwatts) +cat /sys/class/hwmon/hwmon0/power1_average +# current temp (millidegrees C) +cat /sys/class/hwmon/hwmon0/temp1_input +# see fan speed (rpm) +cat /sys/class/hwmon/hwmon0/fan1_input +# see fan speed pwm (0-255) +cat /sys/class/hwmon/hwmon0/pwm1 +# see min/max pwm limits +cat /sys/class/hwmon/hwmon0/pwm1_min +cat /sys/class/hwmon/hwmon0/pwm1_max +# see current fan control mode (0 none, 1 manual fan control, 2 dynamic fan control) +cat /sys/class/hwmon/hwmon0/pwm1_enable +# enable manual fan control +echo 1 > /sys/class/hwmon/hwmon0/pwm1_enable +# manually set the fan speed (100/255 = 39%) +echo 100 > /sys/class/hwmon/hwmon0/pwm1 +# enable automatic fan control +echo 2 > /sys/class/hwmon/hwmon0/pwm1_enable From 4a518b090304564c1f7babc81ba371b64f7b84fe Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 17 Dec 2020 16:55:26 +0800 Subject: [PATCH 0315/2070] drm/amdkcl/dkms: add prefix for amdkcl log Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_common.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5dcd2f97fc29b..0bed0b09bc09f 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,8 @@ amdkcl-y += main.o ccflags-y += \ - -include $(src)/../dkms/config/config.h + -include $(src)/../dkms/config/config.h \ + -include $(src)/kcl_common.h ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h new file mode 100644 index 0000000000000..d547bd5608e47 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_COMMON_H +#define AMDKCL_COMMON_H + +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "amdkcl: " fmt + +#endif From d5674d136f6dfcbe948bcbacf41a29c1461b36ae Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 8 Nov 2019 12:14:03 +0800 Subject: [PATCH 0316/2070] drm/amdkcl/dkms: add lookpup unexported symbol support v2: test kallsyms_lookup_name() is exported. v3: fix awk syntax to find kallsyms_lookup_name() addr. v4: use kprobe to find out kallsyms_lookup_name() Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_common.c | 49 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_common.h | 5 ++ drivers/gpu/drm/amd/amdkcl/main.c | 3 ++ .../drm/amd/dkms/m4/kallsyms-lookup-name.m4 | 14 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 7 files changed, 74 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_common.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0bed0b09bc09f..a805915aba6b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -amdkcl-y += main.o +amdkcl-y += main.o symbols.o kcl_common.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c new file mode 100644 index 0000000000000..5867b4d1a6c38 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include + +unsigned long (*_kcl_kallsyms_lookup_name)(const char *name); + +void *amdkcl_fp_setup(const char *symbol, void *dummy) +{ + unsigned long addr; + void *fp = dummy; + + addr = _kcl_kallsyms_lookup_name(symbol); + if (addr == 0) { + if (fp) + pr_warn("Warning: fail to get symbol %s, replace it with kcl stub\n", symbol); + else { + pr_err("Error: fail to get symbol %s, abort...\n", symbol); + BUG(); + } + } else { + fp = (void *)addr; + } + + return fp; +} + +void amdkcl_symbol_init(void) +{ +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = "kallsyms_lookup_name"; + r = register_kprobe(&kp); + if (!r) { + _kcl_kallsyms_lookup_name = (void *)kp.addr; + unregister_kprobe(&kp); + } else { + pr_err("fail to get kallsyms_lookup_name, abort...\n"); + BUG(); + } +#else + _kcl_kallsyms_lookup_name = kallsyms_lookup_name; +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h index d547bd5608e47..de8bdd481dc98 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -2,9 +2,14 @@ #ifndef AMDKCL_COMMON_H #define AMDKCL_COMMON_H +#include +#include + #ifdef pr_fmt #undef pr_fmt #endif #define pr_fmt(fmt) "amdkcl: " fmt +void *amdkcl_fp_setup(const char *symbol, void *dummy); + #endif diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 59f4520c9a8bd..4a0f67981e1c4 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -2,8 +2,11 @@ #include #include +extern void amdkcl_symbol_init(void); + int __init amdkcl_init(void) { + amdkcl_symbol_init(); return 0; } module_init(amdkcl_init); diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 new file mode 100644 index 0000000000000..62e540f41a7df --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v5.6-11591-g0bd476e6c671 kallsyms: unexport kallsyms_lookup_name() and kallsyms_on_each_symbol() +dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sample module +dnl # +AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kallsyms_lookup_name], + [kernel/kallsyms.c], + [ + AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, + [kallsyms_lookup_name is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0593e48224aaa..d3555facee09e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 745124a028bc7..698e69b364c03 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -33,7 +33,7 @@ source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c for sym in $SYMS; do - awk -v sym=$sym '/\/ { + awk -v sym=$sym '$3 == sym { print "void *_kcl_" $3 " = (void *)0x" $1 ";" }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done From 90a1c2fcfd32223108e5c0678d7263a1a70f7f4e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 13 May 2020 15:41:04 +0800 Subject: [PATCH 0317/2070] drm/amdkcl/dkms: create dummy func for funcs unavailable Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h index de8bdd481dc98..9c9eca94212b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -12,4 +12,15 @@ void *amdkcl_fp_setup(const char *symbol, void *dummy); +/* + * create dummy func + */ +#define amdkcl_dummy_symbol(name, ret_type, ret, ...) \ +ret_type name(__VA_ARGS__) \ +{ \ + pr_warn_once("%s is not supported\n", #name); \ + ret ;\ +} \ +EXPORT_SYMBOL(name); + #endif From f8631583d0636a3b0d18eb13dc5a662d643e03eb Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 21:51:37 +0800 Subject: [PATCH 0318/2070] drm/amdkcl/dkms: add AC_AMDGPU_LINUX_HEADERS it is a squash of: 5ded515e0816 drm/amdkcl: update test for linux/dma-resv.h 0b63eb175dbb drm/amdkcl: drop individual tests for header files 221c1ea7b3db drm/amdkcl: fix license c444a2fe2e49 drm/amdkcl: move kcl wrapper for linux header to header dir 627af54ab135 drm/amdkcl: add AC_AMDGPU_LINUX_HEADERS Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 69 +++++++++++++++++++ include/kcl/header/asm/set_memory.h | 11 +++ include/kcl/header/linux/bits.h | 11 +++ include/kcl/header/linux/dma-buf-map.h | 9 +++ .../kcl/header/linux/io-64-nonatomic-lo-hi.h | 11 +++ include/kcl/header/linux/pci-p2pdma.h | 9 +++ 7 files changed, 121 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 create mode 100644 include/kcl/header/asm/set_memory.h create mode 100644 include/kcl/header/linux/bits.h create mode 100644 include/kcl/header/linux/dma-buf-map.h create mode 100644 include/kcl/header/linux/io-64-nonatomic-lo-hi.h create mode 100644 include/kcl/header/linux/pci-p2pdma.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3555facee09e..6f85d0821c5f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 new file mode 100644 index 0000000000000..3701b776bd191 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -0,0 +1,69 @@ +AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ + + dnl # + dnl # commit 8bd9cb51daac89337295b6f037b0486911e1b408 + dnl # locking/atomics, asm-generic: Move some macros from + dnl # to a new file + dnl # + AC_KERNEL_CHECK_HEADERS([linux/bits.h]) + + dnl # + dnl # commit v4.3-rc4-1-g2f8e2c877784 + dnl # move io-64-nonatomic*.h out of asm-generic + dnl # + AC_KERNEL_CHECK_HEADERS([linux/io-64-nonatomic-lo-hi.h]) + + dnl # + dnl # commit 299878bac326c890699c696ebba26f56fe93fc75 + dnl # treewide: move set_memory_* functions away from cacheflush.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/set_memory.h]) + + dnl # + dnl # commit df6b35f409af0a8ff1ef62f552b8402f3fef8665 + dnl # x86/fpu: Rename i387.h to fpu/api.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/fpu/api.h]) + + dnl # + dnl # v4.19-rc6-7-ga3f8a30f3f00 + dnl # Compiler Attributes: use feature checks instead of version checks + dnl # + AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) + + dnl # + dnl # v4.9-rc2-299-gf54d1867005c + dnl # dma-buf: Rename struct fence to dma_fence + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence.h]) + + dnl # + dnl # v5.3-rc1-449-g52791eeec1d9 + dnl $ dma-buf: rename reservation_object to dma_resv + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-resv.h]) + + dnl # + dnl # v5.7-13149-g9740ca4e95b4 + dnl # mmap locking API: initial implementation as rwsem wrappers + dnl # + AC_KERNEL_CHECK_HEADERS([linux/mmap_lock.h]) + + dnl # + dnl # v4.19-rc4-1-g52916982af48 + dnl # PCI/P2PDMA: Support peer-to-peer memory + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pci-p2pdma.h]) + + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-attrs.h]) + + dnl # + dnl # 01fd30da0474 + dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) +]) diff --git a/include/kcl/header/asm/set_memory.h b/include/kcl/header/asm/set_memory.h new file mode 100644 index 0000000000000..4614c4c1c4630 --- /dev/null +++ b/include/kcl/header/asm/set_memory.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__ASM_SET_MEMORY_H_H_ +#define _KCL_HEADER__ASM_SET_MEMORY_H_H_ + +#if defined(HAVE_ASM_SET_MEMORY_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/bits.h b/include/kcl/header/linux/bits.h new file mode 100644 index 0000000000000..28a84955dc780 --- /dev/null +++ b/include/kcl/header/linux/bits.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_BITS_H_H_ +#define _KCL_HEADER__LINUX_BITS_H_H_ + +#if defined(HAVE_LINUX_BITS_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/dma-buf-map.h b/include/kcl/header/linux/dma-buf-map.h new file mode 100644 index 0000000000000..523dfcfabda8b --- /dev/null +++ b/include/kcl/header/linux/dma-buf-map.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___DMA_BUF_MAP_H___H_ +#define _KCL_HEADER___DMA_BUF_MAP_H___H_ + +#ifdef HAVE_LINUX_DMA_BUF_MAP_H +#include_next +#endif + +#endif + diff --git a/include/kcl/header/linux/io-64-nonatomic-lo-hi.h b/include/kcl/header/linux/io-64-nonatomic-lo-hi.h new file mode 100644 index 0000000000000..0fa2e108091b7 --- /dev/null +++ b/include/kcl/header/linux/io-64-nonatomic-lo-hi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_IO_64_NONATOMIC_LO_HI_H_H_ +#define _KCL_HEADER_LINUX_IO_64_NONATOMIC_LO_HI_H_H_ + +#ifdef HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/pci-p2pdma.h b/include/kcl/header/linux/pci-p2pdma.h new file mode 100644 index 0000000000000..84ad226012bdc --- /dev/null +++ b/include/kcl/header/linux/pci-p2pdma.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PCI_P2PDMA_H_H_ +#define _KCL_HEADER_LINUX_PCI_P2PDMA_H_H_ + +#ifdef HAVE_LINUX_PCI_P2PDMA_H +#include_next +#endif + +#endif From 3f1f2efa9d89fb1ee7750cd433285a21137c2c73 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 21:53:07 +0800 Subject: [PATCH 0319/2070] drm/amdkcl/dkms: add AC_AMDGPU_DRM_HEADERS v2: test for drm/drm_backport.h (Flora.Cui@amd.com) RHEL 7.x wraps some API in drm/drm_backport.h header file Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Change-Id: I2717f0cfb3caaeb93f409656c6ce7c88fecc36de Reviewed-by: Yang Xiong Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 41 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drmP.h | 9 +++++ include/kcl/header/drm/drm_managed.h | 9 +++++ include/kcl/header/drm/drm_print.h | 10 ++++++ include/kcl/header/drm/drm_probe_helper.h | 11 ++++++ include/kcl/header/drm/task_barrier.h | 9 +++++ 7 files changed, 90 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 create mode 100644 include/kcl/header/drm/drmP.h create mode 100644 include/kcl/header/drm/drm_managed.h create mode 100644 include/kcl/header/drm/drm_print.h create mode 100644 include/kcl/header/drm/drm_probe_helper.h create mode 100644 include/kcl/header/drm/task_barrier.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 new file mode 100644 index 0000000000000..5db23c22d9fe3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -0,0 +1,41 @@ +AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ + dnl # + dnl # RHEL 7.x wrapper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_backport.h]) + + dnl # + dnl # Optional devices ID for amdgpu driver + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) + + dnl # + dnl # commit v4.9-rc2-477-gd8187177b0b1 + dnl # drm: add helper for printing to log or seq_file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_print.h]) + + dnl # + dnl # commit v5.0-rc1-342-gfcd70cd36b9b + dnl # drm: Split out drm_probe_helper.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_probe_helper.h]) + + dnl # + dnl # v5.4-rc1-214-g4e98f871bcff + dnl # drm: delete drmP.h + drm_os_linux.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drmP.h]) + + dnl # + dnl # commit v5.5-rc2-783-g368fd0aad1be + dnl # drm: Add Reusable task barrier. + dnl # + AC_KERNEL_CHECK_HEADERS([drm/task_barrier.h]) + + dnl # + dnl # v5.6-rc5-1258-gc6603c740e0e + dnl # drm: add managed resources tied to drm_device + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f85d0821c5f3..a61ba77924c84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -5,6 +5,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET AC_AMDGPU_LINUX_HEADERS + AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT diff --git a/include/kcl/header/drm/drmP.h b/include/kcl/header/drm/drmP.h new file mode 100644 index 0000000000000..008236685b081 --- /dev/null +++ b/include/kcl/header/drm/drmP.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_managed.h b/include/kcl/header/drm/drm_managed.h new file mode 100644 index 0000000000000..d6f211d64b346 --- /dev/null +++ b/include/kcl/header/drm/drm_managed.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_KCL_DRM_MANAGED_H_H +#define _KCL_HEADER_KCL_DRM_MANAGED_H_H + +#ifdef HAVE_DRM_DRM_MANAGED_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_print.h b/include/kcl/header/drm/drm_print.h new file mode 100644 index 0000000000000..0f1db6376a8a3 --- /dev/null +++ b/include/kcl/header/drm/drm_print.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PRINT_H_H_ +#define _KCL_HEADER_DRM_PRINT_H_H_ + +#if defined(HAVE_DRM_DRM_PRINT_H) +#include_next +#endif +#include + +#endif diff --git a/include/kcl/header/drm/drm_probe_helper.h b/include/kcl/header/drm/drm_probe_helper.h new file mode 100644 index 0000000000000..a454fe92ea203 --- /dev/null +++ b/include/kcl/header/drm/drm_probe_helper.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PROBE_HELPER_H_H_ +#define _KCL_HEADER_DRM_PROBE_HELPER_H_H_ + +#ifdef HAVE_DRM_DRM_PROBE_HELPER_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/drm/task_barrier.h b/include/kcl/header/drm/task_barrier.h new file mode 100644 index 0000000000000..e93315f493f3e --- /dev/null +++ b/include/kcl/header/drm/task_barrier.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_TASK_BARRIER_H_H_ +#define _KCL_HEADER_DRM_TASK_BARRIER_H_H_ + +#ifdef HAVE_DRM_TASK_BARRIER_H +#include_next +#endif + +#endif From fe75b4ced5ddb244c718936b200c13606c0c08fc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:07:04 +0800 Subject: [PATCH 0320/2070] drm/amdkcl: DROPME: include amdgpu_amdkfd.h in kfd_priv.h Change-Id: Ia5f684b21b7cbd3cc98b048cf8a586a6b79c46f1 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9849b54f54ba0..ca25343798cf3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -46,6 +46,7 @@ #include #include +#include "amdgpu_amdkfd.h" #include "amd_shared.h" #include "amdgpu.h" From 03ff998d20ab6e97667d8b3cf3a1342207310a29 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 09:59:48 +0800 Subject: [PATCH 0321/2070] drm/amdkcl: DROPME: include linux/sched/mm.h in ttm_tt.c Change-Id: I3cbc5f6e03c28c7db1895cb8d2015e5f698546ee Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/ttm_tt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index af33fa0202496..026a57874826c 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include #include #include #include From 51d6d536ed5307072fe1123389aec5bf38250350 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 10:14:58 +0800 Subject: [PATCH 0322/2070] drm/amdkcl: REWORKME: config.h Change-Id: I981875bb459ee1d29553b026e33b316e185250cb Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 147 +++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/config/config.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h new file mode 100644 index 0000000000000..5c604c53ed971 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -0,0 +1,147 @@ +/* config/config.h. Generated from config.h.in by configure. */ +/* config/config.h.in. Generated from configure.ac by autoheader. */ + +/* *FLAGS_.o support to take the path relative to $(obj) */ +#define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_FPU_API_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_SET_MEMORY_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_AMDGPU_PCIID_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRMP_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_AUDIO_COMPONENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_AUTH_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_BACKPORT_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CONNECTOR_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DEBUGFS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DEVICE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DRV_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ENCODER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FILE_H 1 + +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_IOCTL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_IRQ_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_MANAGED_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PLANE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PRINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PROBE_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_UTIL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_VBLANK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_TASK_BARRIER_H 1 + +/* kallsyms_lookup_name is available */ +/* #undef HAVE_KALLSYMS_LOOKUP_NAME */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BITS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_DMA_ATTRS_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_RESV_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MEM_ENCRYPT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MMAP_LOCK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_NOSPEC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_OVERFLOW_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PCI_P2PDMA_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_MM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_SIGNAL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_TASK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "amdgpu-dkms" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "amdgpu-dkms 19.40" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "amdgpu-dkms" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "19.40" From b0e02cb0e5a554c5b81364da3c71785d9faf655f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 11:52:01 +0800 Subject: [PATCH 0323/2070] drm/amdkcl: fake hexint support for module_param Change-Id: Ic6b3fd5e2ca1e6e645c658924cc051b6119297b6 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 ++ .../gpu/drm/amd/amdkcl/kcl_kernel_params.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_moduleparam.h | 17 +++++++++++ 4 files changed, 49 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c create mode 100644 include/kcl/kcl_moduleparam.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a805915aba6b9..6d6d62a8e05a1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: MIT amdkcl-y += main.o symbols.o kcl_common.o +amdkcl-y += kcl_kernel_params.o + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c new file mode 100644 index 0000000000000..d350a6bd07769 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Helpers for initial module or kernel cmdline parsing + Copyright (C) 2001 Rusty Russell. + +*/ +#include + +// Copied from kernel/params.c +#define STANDARD_PARAM_DEF(name, type, format, strtolfn) \ + int param_set_##name(const char *val, const struct kernel_param *kp) \ + { \ + return strtolfn(val, 0, (type *)kp->arg); \ + } \ + int param_get_##name(char *buffer, const struct kernel_param *kp) \ + { \ + return scnprintf(buffer, PAGE_SIZE, format "\n", \ + *((type *)kp->arg)); \ + } \ + const struct kernel_param_ops param_ops_##name = { \ + .set = param_set_##name, \ + .get = param_get_##name, \ + }; \ + EXPORT_SYMBOL(param_set_##name); \ + EXPORT_SYMBOL(param_get_##name); \ + EXPORT_SYMBOL(param_ops_##name) + +#ifdef _kcl_param_check_hexint +STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 89cd9143a9c0a..e30fbea884c07 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -4,4 +4,5 @@ #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_moduleparam.h b/include/kcl/kcl_moduleparam.h new file mode 100644 index 0000000000000..427abe45ea8af --- /dev/null +++ b/include/kcl/kcl_moduleparam.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_LINUX_MODULE_PARAMS_H_H +#define _KCL_KCL_LINUX_MODULE_PARAMS_H_H + +#include +#include + +/* Copied from v5.8-rc2-514-g7d8365771ffb include/linux/moduleparam.h */ +#ifndef param_check_hexint +#define _kcl_param_check_hexint +extern const struct kernel_param_ops param_ops_hexint; +extern int param_set_hexint(const char *val, const struct kernel_param *kp); +extern int param_get_hexint(char *buffer, const struct kernel_param *kp); +#define param_check_hexint(name, p) param_check_uint(name, p) +#endif /* param_check_hexint */ + +#endif From acbe2d6112b2063df07c3997c6a90aafb1d292c0 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 18 Nov 2019 16:52:31 +0800 Subject: [PATCH 0324/2070] drm/amdkcl: check whether idr_for_each_entry_continue is avialable it is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part 7b1a9f7a702c drm/amdkcl: fake idr_remove() 41a5a48a1668 drm/amdkcl: check whether idr_for_each_entry_continue is avialable Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 | 19 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_idr.h | 38 +++++++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 create mode 100644 include/kcl/kcl_idr.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e30fbea884c07..cd8ab3c582fb4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,4 +5,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 b/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 new file mode 100644 index 0000000000000..397c76a73ed8e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit d3e709e63e97e5f3f129b639991cfe266da60bae +dnl # Author: Matthew Wilcox +dnl # Date: Thu Dec 22 13:30:22 2016 -0500 +dnl # idr: Return the deleted entry from idr_remove +dnl # +AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void *i; + i = idr_remove(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_REMOVE_RETURN_VOID_POINTER, 1, + [idr_remove return void pointer]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a61ba77924c84..987841f059751 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_AMDGPU_IDR_REMOVE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h new file mode 100644 index 0000000000000..63473317c2ead --- /dev/null +++ b/include/kcl/kcl_idr.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/linux/idr.h + * + * 2002-10-18 written by Jim Houston jim.houston@ccur.com + * Copyright (C) 2002 by Concurrent Computer Corporation + * + * Small id to pointer translation service avoiding fixed sized + * tables. + */ +#ifndef AMDKCL_IDR_H +#define AMDKCL_IDR_H + +#include + +/* Copied from v4.4-rc2-61-ga55bbd375d18 include/linux/idr.h */ +#ifndef idr_for_each_entry_continue +#define idr_for_each_entry_continue(idr, entry, id) \ + for ((entry) = idr_get_next((idr), &(id)); \ + entry; \ + ++id, (entry) = idr_get_next((idr), &(id))) +#endif + +#ifndef HAVE_IDR_REMOVE_RETURN_VOID_POINTER +static inline void *_kcl_idr_remove(struct idr *idr, int id) +{ + void *ptr; + + ptr = idr_find(idr, id); + if (ptr) + idr_remove(idr, id); + + return ptr; +} +#define idr_remove _kcl_idr_remove +#endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ + +#endif /* AMDKCL_IDR_H */ From edce4ba1f9c221f359ca10a012c6effc77791c60 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2019 11:31:51 +0800 Subject: [PATCH 0325/2070] drm/amdkcl: fake DMA_ATTR_NO_WARN if undefined Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test dma_map_sgtable() is available fake a kcl copy of dma_map_sgtable() & dma_unmap_sgtable() Signed-off-by: Flora Cui Change-Id: I277799b85805aefa105c73c88d0ba01ad44c1912 drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 | 21 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 2 +- include/kcl/kcl_dma_mapping.h | 90 +++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 create mode 100644 include/kcl/kcl_dma_mapping.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cd8ab3c582fb4..dbe6c0779acad 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -6,4 +6,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 new file mode 100644 index 0000000000000..09d1275020880 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.7-rc5-32-gd9d200bcebc1 +dnl # dma-mapping: add generic helpers for mapping sgtable objects +dnl # +AC_DEFUN([AC_AMDGPU_DMA_MAP_SGTABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_map_sgtable(NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_MAP_SGTABLE, 1, + [dma_map_sgtable() is enabled]) + ] + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # leverage test for linux/dma-attrs.h + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 987841f059751..4ae1b7f0e856e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -8,6 +8,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_DMA_MAP_SGTABLE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 524d2a01b50df..045c3cfd6e123 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,5 +3,5 @@ #define AMDTTM_BACKPORT_H #include - +#include #endif diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h new file mode 100644 index 0000000000000..c7de48cd9aad7 --- /dev/null +++ b/include/kcl/kcl_dma_mapping.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DMA_MAPPING_H +#define AMDKCL_DMA_MAPPING_H + +#include + +/* + * commit v4.8-11962-ga9a62c938441 + * dma-mapping: introduce the DMA_ATTR_NO_WARN attribute + */ +#ifndef DMA_ATTR_NO_WARN +#define DMA_ATTR_NO_WARN (0UL) +#endif + +#ifdef HAVE_LINUX_DMA_ATTRS_H +static inline +void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, + unsigned long attrs) +{ + int i; + + init_dma_attrs(dma_attrs); + + for (i = 0; i < DMA_ATTR_MAX; i++) { + if (attrs & (1 << i)) + dma_set_attr(i, dma_attrs); + } +} +#endif + +#ifndef HAVE_DMA_MAP_SGTABLE +#ifdef HAVE_LINUX_DMA_ATTRS_H +static inline +int _kcl_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + return dma_map_sg_attrs(dev, sg, nents, dir, &dma_attrs); +} + +static inline +void _kcl_dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + unsigned long attrs) + +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + dma_unmap_sg_attrs(dev, sg, nents, dir, &dma_attrs); +} + +#else +static inline +int _kcl_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, unsigned long attrs) +{ + return dma_map_sg_attrs(dev, sg, nents, dir, attrs); +} +static inline +void _kcl_dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + unsigned long attrs) +{ + dma_unmap_sg_attrs(dev, sg, nents, dir, attrs); +} +#endif /* HAVE_LINUX_DMA_ATTRS_H */ + +static inline int dma_map_sgtable(struct device *dev, struct sg_table *sgt, + enum dma_data_direction dir, unsigned long attrs) +{ + int nents; + + nents = _kcl_dma_map_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); + if (nents <= 0) + return -EINVAL; + sgt->nents = nents; + return 0; +} + +static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, + enum dma_data_direction dir, unsigned long attrs) +{ + _kcl_dma_unmap_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); +} +#endif + +#endif From 115ff6f9a8771ce1d1abfea9aac56e7f9ffb2e0b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 8 Sep 2020 14:17:21 +0800 Subject: [PATCH 0326/2070] drm/amdkcl: test i2c_new_client_device() is available v2: add extern for i2c_new_client_device() available case for phantom kernel forget to declare the func it is a squash of: b677e39b1c70 drm/amdkcl: test i2c_new_client_device() is available c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/i2c_new_client_device.m4 | 13 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_i2c.h | 26 +++++++++++++++++++ 4 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 create mode 100644 include/kcl/kcl_i2c.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index dbe6c0779acad..c320e6690c637 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -7,4 +7,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 new file mode 100644 index 0000000000000..cedd29e0fe70e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.1-12318-g7159dbdae3c5 +dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dummy +dnl # +AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([i2c_new_client_device], [drivers/i2c/i2c-core-base.c], + [ + AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, + [i2c_new_client_device() is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ae1b7f0e856e..22e58b5cb2b2f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -9,6 +9,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_AMDGPU_IDR_REMOVE AC_AMDGPU_DMA_MAP_SGTABLE + AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h new file mode 100644 index 0000000000000..66b3195eff49d --- /dev/null +++ b/include/kcl/kcl_i2c.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * i2c.h - definitions for the Linux i2c bus interface + * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2013-2019 Wolfram Sang + * + * With some changes from Kyösti Mälkki and + * Frodo Looijaard + */ +#ifndef _KCL_KCL_I2C_H +#define _KCL_KCL_I2C_H + +#include + +#ifdef HAVE_I2C_NEW_CLIENT_DEVICE +extern struct i2c_client * +i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *info); +#else +static inline struct i2c_client * +i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *info) +{ + return i2c_new_device(adap, info); +} +#endif + +#endif From 8458b72eaae4e66255fd4c2bde45984b06e76005 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 6 May 2020 17:13:38 +0800 Subject: [PATCH 0327/2070] drm/amdkcl: Test whether backlight_device_set_brightness is available introduced by kernel: v4.7-rc2~9^2^2~5 v2: add kcl copy of backlight_device_set_brightness This is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part f11810210f8a drm/amdkcl: Test whether backlight_device_set_brightness is available Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 ++ drivers/gpu/drm/amd/amdkcl/kcl_backlight.c | 14 ++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 ++ .../dkms/m4/backlight-device-set-brightness.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_backlight.h | 16 ++++++++++++++++ 6 files changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_backlight.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 create mode 100644 include/kcl/kcl_backlight.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6d6d62a8e05a1..4b40eff8ae672 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,6 +3,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o +amdkcl-y += kcl_backlight.o + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c new file mode 100644 index 0000000000000..1e1da40b92c05 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Backlight Lowlevel Control Abstraction + * + * Copyright (C) 2003,2004 Hewlett-Packard Company + * + */ +#include + +#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS +amdkcl_dummy_symbol(backlight_device_set_brightness, int, return 0, + struct backlight_device *bd, unsigned long brightness) +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c320e6690c637..d8609a150e60d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -8,4 +8,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 new file mode 100644 index 0000000000000..b021cbc2ab976 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.6-rc6-1-gf6a4790a5471 +dnl # video / backlight: add two APIs for drivers to use +dnl # +AC_DEFUN([AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + backlight_device_set_brightness(NULL, 0); + ], [backlight_device_set_brightness], [drivers/video/backlight/backlight.c], [ + AC_DEFINE(HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS, 1, + [backlight_device_set_brightness() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 22e58b5cb2b2f..73a147ee4be88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -10,6 +10,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IDR_REMOVE AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE + AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_backlight.h b/include/kcl/kcl_backlight.h new file mode 100644 index 0000000000000..1d06b61502c3c --- /dev/null +++ b/include/kcl/kcl_backlight.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Backlight Lowlevel Control Abstraction + * + * Copyright (C) 2003,2004 Hewlett-Packard Company + * + */ +#ifndef AMDKCL_BACKLIGHT_H +#define AMDKCL_BACKLIGHT_H + +#include +#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS +int backlight_device_set_brightness(struct backlight_device *bd, + unsigned long brightness); +#endif /* HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS */ +#endif From 4ddc4fa7e5d88580402b33c7e5eded4cc38abbf0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 10:31:41 +0800 Subject: [PATCH 0328/2070] drm/amdkcl: fake a kcl copy of compat_ptr_ioctl() This is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part 2011137fd5d7 drm/amdkcl: fake a kcl copy of compat_ptr_ioctl() Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c | 45 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- .../gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 | 17 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fs.h | 22 +++++++++ 6 files changed, 87 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 create mode 100644 include/kcl/kcl_fs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4b40eff8ae672..7bb382f7c3e27 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,8 +2,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o - -amdkcl-y += kcl_backlight.o +amdkcl-y += kcl_backlight.o kcl_ioctl.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c new file mode 100644 index 0000000000000..aef47eda7f4ab --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/ioctl.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b fs/ioctl.c */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +/** + * compat_ptr_ioctl - generic implementation of .compat_ioctl file operation + * + * This is not normally called as a function, but instead set in struct + * file_operations as + * + * .compat_ioctl = compat_ptr_ioctl, + * + * On most architectures, the compat_ptr_ioctl() just passes all arguments + * to the corresponding ->ioctl handler. The exception is arch/s390, where + * compat_ptr() clears the top bit of a 32-bit pointer value, so user space + * pointers to the second 2GB alias the first 2GB, as is the case for + * native 32-bit s390 user space. + * + * The compat_ptr_ioctl() function must therefore be used only with ioctl + * functions that either ignore the argument or pass a pointer to a + * compatible data type. + * + * If any ioctl command handled by fops->unlocked_ioctl passes a plain + * integer instead of a pointer, or any of the passed data types + * is incompatible between 32-bit and 64-bit architectures, a proper + * handler is required instead of compat_ptr_ioctl. + */ +long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + if (!file->f_op->unlocked_ioctl) + return -ENOIOCTLCMD; + + return file->f_op->unlocked_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +EXPORT_SYMBOL(_kcl_compat_ptr_ioctl); +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d8609a150e60d..06c221779f754 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,5 +9,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 new file mode 100644 index 0000000000000..f9c4c12aa4b75 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc2-1-g2952db0fd51b +dnl # compat_ioctl: add compat_ptr_ioctl() +dnl # +AC_DEFUN([AC_AMDGPU_COMPAT_PTR_IOCTL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + compat_ptr_ioctl(NULL, 0, 0); + ],[compat_ptr_ioctl],[fs/ioctl.c],[ + AC_DEFINE(HAVE_COMPAT_PTR_IOCTL, + 1, + [compat_ptr_ioctl() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 73a147ee4be88..1330ded2579c8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -11,6 +11,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS + AC_AMDGPU_COMPAT_PTR_IOCTL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h new file mode 100644 index 0000000000000..4a4c208d833e0 --- /dev/null +++ b/include/kcl/kcl_fs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FS_H +#define AMDKCL_FS_H + +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b linux/fs.h */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +extern long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, + unsigned long arg); +static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return _kcl_compat_ptr_ioctl(file, cmd, arg); +} +#else +#define compat_ptr_ioctl NULL +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ +#endif From fb62ce3444ec0703a66941f719fa3ce6f798aeee Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Tue, 28 Apr 2020 23:22:10 +0800 Subject: [PATCH 0329/2070] drm/amdkcl: Test whether list_rotate_to_front() and list_is_first() is available This is a squash of: b6026ffc104a drm/amdkcl: minor refactor for indent and comment style 588246ddef5a drm/amdkcl: Test whether list_rotate_to_front() and list_is_first() is available Signed-off-by: Yang Xiong Reviewed-by: Yifan Zhang Reviewed-by: Feifei Xu Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 | 18 ++++++++++++++ .../drm/amd/dkms/m4/list-rotate_to_front.m4 | 18 ++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_list.h | 24 +++++++++++++++++++ 6 files changed, 65 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 create mode 100644 include/kcl/kcl_list.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 06c221779f754..dda4aaf9fe024 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -10,4 +10,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1330ded2579c8..c863756bd3d47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -12,6 +12,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_COMPAT_PTR_IOCTL + AC_AMDGPU_LIST_ROTATE_TO_FRONT + AC_AMDGPU_LIST_IS_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 new file mode 100644 index 0000000000000..566de635a47da --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 70b44595eafe9c7c235f076d653a268ca1ab9fdb +dnl # Author: Mel Gorman +dnl # Date: Tue Mar 5 15:44:54 2019 -0800 +dnl # mm, compaction: use free lists to quickly locate a migration source +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_first(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_FIRST, 1, + [list_is_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 new file mode 100644 index 0000000000000..2e914f0314652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit a16b53849913e742d086bb2b6f5e069ea2850c56 +dnl # Author: Tobin C. Harding +dnl # Date: Mon May 13 17:15:59 2019 -0700 +dnl # list: add function list_rotate_to_front() +dnl # +AC_DEFUN([AC_AMDGPU_LIST_ROTATE_TO_FRONT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_rotate_to_front(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_ROTATE_TO_FRONT, 1, + [list_rotate_to_front() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 045c3cfd6e123..fe8d8882b94aa 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -4,4 +4,5 @@ #include #include +#include #endif diff --git a/include/kcl/kcl_list.h b/include/kcl/kcl_list.h new file mode 100644 index 0000000000000..20e2bee6bef61 --- /dev/null +++ b/include/kcl/kcl_list.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LIST_H +#define AMDKCL_LIST_H + +#include + +/* Copied from include/linux/list.h */ +#if !defined(HAVE_LIST_ROTATE_TO_FRONT) +static inline void list_rotate_to_front(struct list_head *list, + struct list_head *head) +{ + list_move_tail(head, list); +} +#endif + +#if !defined(HAVE_LIST_IS_FIRST) +static inline int list_is_first(const struct list_head *list, + const struct list_head *head) +{ + return list->prev == head; +} +#endif + +#endif /*AMDKCL_LIST_H*/ From 584f5c93b9bca692deb06bfd9e096b4f06c615ee Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 26 Dec 2016 13:42:16 +0800 Subject: [PATCH 0330/2070] drm/amdkcl: Test whether arch_io_{reserve/free}_memtype_wc() are available arch_io_reserve_memtype_wc is introduced in v4.9-rc2-1-g8ef4227615e1. rhel < 7.8 adds an inline define to drm_backport.h squash of e07c4960e087 drm/amdkcl: update test for arch_io_reserve_memtype_wc 1943acaa561d drm/amdkcl: Test whether arch_io_{reserve/free}_memtype_wc() are available c1f004d6344b drm/amdkcl: fix license for kcl part caba32ffd8e3 drm/amdkcl: include kcl_common.h in every .c Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Chengming Gui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_io.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 3 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/arch-io-reserve-free-memtype-wc.m4 | 34 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_io_backport.h | 47 ++++++++++++ 7 files changed, 161 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_io.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 create mode 100644 include/kcl/backport/kcl_io_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 7bb382f7c3e27..8bcb40cac88d4 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o -amdkcl-y += kcl_backlight.o kcl_ioctl.o +amdkcl-y += kcl_backlight.o kcl_ioctl.o \ + kcl_io.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_io.c b/drivers/gpu/drm/amd/amdkcl/kcl_io.c new file mode 100644 index 0000000000000..c1f2307557352 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_io.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Page Attribute Table (PAT) support: handle memory caching attributes in page tables. + * + * Authors: Venkatesh Pallipadi + * Suresh B Siddha + * + * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen. + * + * Basic principles: + * + * PAT is a CPU feature supported by all modern x86 CPUs, to allow the firmware and + * the kernel to set one of a handful of 'caching type' attributes for physical + * memory ranges: uncached, write-combining, write-through, write-protected, + * and the most commonly used and default attribute: write-back caching. + * + * PAT support supercedes and augments MTRR support in a compatible fashion: MTRR is + * a hardware interface to enumerate a limited number of physical memory ranges + * and set their caching attributes explicitly, programmed into the CPU via MSRs. + * Even modern CPUs have MTRRs enabled - but these are typically not touched + * by the kernel or by user-space (such as the X server), we rely on PAT for any + * additional cache attribute logic. + * + * PAT doesn't work via explicit memory ranges, but uses page table entries to add + * cache attribute information to the mapped memory range: there's 3 bits used, + * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT), with the 8 possible values mapped by the + * CPU to actual cache attributes via an MSR loaded into the CPU (MSR_IA32_CR_PAT). + * + * ( There's a metric ton of finer details, such as compatibility with CPU quirks + * that only support 4 types of PAT entries, and interaction with MTRRs, see + * below for details. ) + */ +#include +#include + +/* Copied from arch/x86/mm/pat.c and modified for KCL */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) && \ + defined(CONFIG_X86) +#include + +static int (*_kcl_io_reserve_memtype)(resource_size_t start, resource_size_t end, + enum page_cache_mode *type); +static void (*_kcl_io_free_memtype)(resource_size_t start, resource_size_t end); + +int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size) +{ +#ifdef _PAGE_CACHE_WC + unsigned long type = _PAGE_CACHE_WC; +#else + enum page_cache_mode type = _PAGE_CACHE_MODE_WC; +#endif + + return _kcl_io_reserve_memtype(start, start + size, &type); +} +EXPORT_SYMBOL(_kcl_arch_io_reserve_memtype_wc); + +void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size) +{ + _kcl_io_free_memtype(start, start + size); +} +EXPORT_SYMBOL(_kcl_arch_io_free_memtype_wc); + +void amdkcl_io_init(void) +{ + _kcl_io_reserve_memtype = amdkcl_fp_setup("io_reserve_memtype", NULL); + _kcl_io_free_memtype = amdkcl_fp_setup("io_free_memtype", NULL); +} +#else +void amdkcl_io_init(void) +{ + +} +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 4a0f67981e1c4..ad5877b16d5eb 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,10 +3,13 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_io_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_io_init(); + return 0; } module_init(amdkcl_init); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index dda4aaf9fe024..1cf4d41472791 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,5 +11,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 new file mode 100644 index 0000000000000..8245a8d52ee43 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit v4.9-rc2-1-g8ef4227615e1 +dnl # x86/io: add interface to reserve io memtype for a resource range. (v1.1) +dnl # +AC_DEFUN([AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [arch_io_reserve_memtype_wc arch_io_free_memtype_wc], [arch/x86/mm/pat/memtype.c arch/x86/mm/pat.c], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_BACKPORT_H + #include + #endif + #include + ], [ + #ifdef CONFIG_X86 + #error stub arch_io_* functions found + #endif + + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c863756bd3d47..512227f4e8a25 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,6 +14,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST + AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_io_backport.h b/include/kcl/backport/kcl_io_backport.h new file mode 100644 index 0000000000000..8fe78d238e6f4 --- /dev/null +++ b/include/kcl/backport/kcl_io_backport.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2006 PathScale, Inc. All Rights Reserved. + */ +#ifndef AMDKCL_IO_H +#define AMDKCL_IO_H + +#include +#include + +/* Copied from arch/x86/include/asm/io.h + * include/linux/io.h + */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) + +#ifdef CONFIG_X86 +extern int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); +extern void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); +#define arch_io_reserve_memtype_wc _kcl_arch_io_reserve_memtype_wc +#define arch_io_free_memtype_wc _kcl_arch_io_free_memtype_wc +#endif + +#ifndef arch_io_reserve_memtype_wc +/* + * On x86 PAT systems we have memory tracking that keeps track of + * the allowed mappings on memory ranges. This tracking works for + * all the in-kernel mapping APIs (ioremap*), but where the user + * wishes to map a range from a physical device into user memory + * the tracking won't be updated. This API is to be used by + * drivers which remap physical device pages into userspace, + * and wants to make sure they are mapped WC and not UC. + */ +static inline int arch_io_reserve_memtype_wc(resource_size_t base, + resource_size_t size) +{ + return 0; +} + +static inline void arch_io_free_memtype_wc(resource_size_t base, + resource_size_t size) +{ +} +#endif + +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ + +#endif /* AMDKCL_IO_H */ From 26737570cc4411bc4ed90d2e203eceb37ca1bebc Mon Sep 17 00:00:00 2001 From: chen gong Date: Wed, 5 Jun 2019 12:36:47 +0800 Subject: [PATCH 0331/2070] drm/amdkcl: Test whether access_ok(x, x) is available v2: drop kcl_access_ok Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Acked-by: Feifei Xu Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/access-ok.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_uaccess_backport.h | 14 ++++++++++++++ 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/access-ok.m4 create mode 100644 include/kcl/backport/kcl_uaccess_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1cf4d41472791..477357bf9e35a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,5 +12,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 new file mode 100644 index 0000000000000..066bd767ddf78 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + access_ok(1, 1); + ],[ + AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, + [whether access_ok(x, x) is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 512227f4e8a25..a6d2de49956d2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -15,6 +15,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC + AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h new file mode 100644 index 0000000000000..c7466949cad39 --- /dev/null +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_UACCESS_BACKPORT_H +#define AMDKCL_UACCESS_BACKPORT_H +#include + +#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) +static inline int _kcl_access_ok(unsigned long addr, unsigned long size) +{ + return access_ok(VERIFY_WRITE, (addr), (size)); +} +#undef access_ok +#define access_ok _kcl_access_ok +#endif +#endif From 0681edd6a087b094d929db0d2e3e5b6e02b3dc82 Mon Sep 17 00:00:00 2001 From: changzhu Date: Thu, 6 Jun 2019 14:09:09 +0800 Subject: [PATCH 0332/2070] drm/amdkcl: check whether DEFINE_SHOW_ATTRIBUTE is available [Why] DEFINE_SHOW_ATTRIBUTE is not defined until kernel version(4,16,0).So there is build error when using DEFINE_SHOW_ATTRIBUTE before kernel version(4,16,0). This kcl patch is for patch: drm/amd/display: Add connector debugfs for "output_bpc" [How] Supply the definition of DEFINE_SHOW_ATTRIBUTE before kernel version(4.16.0) Change-Id: I2211b55c64e89d0cd17f746ac6b6cf581f42420d Signed-off-by: changzhu Reviewed-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_seq_file.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 include/kcl/kcl_seq_file.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 477357bf9e35a..074fa45d46be4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -13,5 +13,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h new file mode 100644 index 0000000000000..4e7750f341705 --- /dev/null +++ b/include/kcl/kcl_seq_file.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_SEQ_FILE_H +#define AMDKCL_SEQ_FILE_H + +#ifndef DEFINE_SHOW_ATTRIBUTE +#define DEFINE_SHOW_ATTRIBUTE(__name) \ +static int __name ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __name ## _show, inode->i_private); \ +} \ + \ +static const struct file_operations __name ## _fops = { \ + .owner = THIS_MODULE, \ + .open = __name ## _open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} +#endif + +#endif From 7c538c5b432c540b327ef9764ba903159e45b30c Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 11 Oct 2019 18:06:11 +0800 Subject: [PATCH 0333/2070] drm/amdkcl: check whether in_task() is available Signed-off-by: Chengming Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_preempt.h | 56 +++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 include/kcl/kcl_preempt.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 074fa45d46be4..87d0726958c30 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -14,5 +14,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h new file mode 100644 index 0000000000000..d76961463a6e3 --- /dev/null +++ b/include/kcl/kcl_preempt.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_PREEMPT_H +#define AMDKCL_PREEMPT_H +#include + +#ifndef in_task +#ifndef PREEMPT_BITS +/* + * We put the hardirq and softirq counter into the preemption + * counter. The bitmask has the following meaning: + * + * - bits 0-7 are the preemption count (max preemption depth: 256) + * - bits 8-15 are the softirq count (max # of softirqs: 256) + * + * The hardirq count could in theory be the same as the number of + * interrupts in the system, but we run all interrupt handlers with + * interrupts disabled, so we cannot have nesting interrupts. Though + * there are a few palaeontologic drivers which reenable interrupts in + * the handler, so we need more than one bit here. + * + * PREEMPT_MASK: 0x000000ff + * SOFTIRQ_MASK: 0x0000ff00 + * HARDIRQ_MASK: 0x000f0000 + * NMI_MASK: 0x00100000 + * PREEMPT_NEED_RESCHED: 0x80000000 + */ +#define PREEMPT_BITS 8 +#define SOFTIRQ_BITS 8 +#define HARDIRQ_BITS 4 +#define NMI_BITS 1 + +#define PREEMPT_SHIFT 0 +#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) +#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) +#define NMI_SHIFT (HARDIRQ_SHIFT + HARDIRQ_BITS) + +#define __IRQ_MASK(x) ((1UL << (x))-1) + +#define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT) +#define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) +#define HARDIRQ_MASK (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT) +#define NMI_MASK (__IRQ_MASK(NMI_BITS) << NMI_SHIFT) + +#define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT) +#define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT) +#define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT) +#define NMI_OFFSET (1UL << NMI_SHIFT) + +#define SOFTIRQ_DISABLE_OFFSET (2 * SOFTIRQ_OFFSET) +#endif + +#define in_task() (!(preempt_count() & \ + (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET))) +#endif + +#endif /* AMDKCL_PREEMPT_H */ From 39a7b506ff826c70b13a20f59a03a65c4eaaaca5 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 9 Sep 2019 16:26:20 +0800 Subject: [PATCH 0334/2070] drm/amdkcl: Test whether ksys_sync_helper() is available ksys_sync_helper() is used in commit: b17092bf14111fa1a35acd3b70ca72b3209a4abe dmr/amdgpu: Add system auto reboot to RAS. ksys_sync_helper() function is introduced in kernel 5.1-rc3 (b5dee3130bb40) in "kernel/power/main.c" which calls to ksys_sync() to do a filesystem sync. ksys_sync() is a helper function for sync() syscall which was refactored in kernel 4.16-rc5 (70f68ee81e2e) in "fs/sync.c". v2: drm/amd/autoconf: Fix typo and optimize ksys_sync_helper() v3: drm/amd/autoconf: Fix sys_sync() is not found after ksys_sync() exists v4: drm/amdkcl: fix test for ksys_sync() v5: drm/amdkcl: fix test for ksys_sync_helper Change-Id: I779764f65e6b6480c2067e2d817eef2f1cbf8482 Signed-off-by: Adam Yang Reviewed-by: Flora Cui Acked-by: Feifei Xu / Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_suspend.c | 51 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 | 16 ++++++ include/kcl/kcl_suspend.h | 17 +++++++ 8 files changed, 90 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_suspend.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 create mode 100644 include/kcl/kcl_suspend.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index dac849eff52fa..7c57518ba6d93 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8bcb40cac88d4..1f0e647057017 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,6 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o + kcl_suspend.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c new file mode 100644 index 0000000000000..c7f1086ebabd3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * kernel/power/main.c - PM subsystem core functionality. + * + * Copyright (c) 2003 Patrick Mochel + * Copyright (c) 2003 Open Source Development Lab + */ +#include +#include + +#ifndef HAVE_KSYS_SYNC_HELPER +/* Copied from kernel/power/main.c */ +#ifdef CONFIG_PM_SLEEP +long (*_kcl_ksys_sync)(void); + +void _kcl_ksys_sync_helper(void) +{ + pr_info("Syncing filesystems ... "); + _kcl_ksys_sync(); + pr_cont("done.\n"); +} +EXPORT_SYMBOL(_kcl_ksys_sync_helper); + +static bool _kcl_sys_sync_stub(void) +{ + pr_warn_once("kernel symbol [k]sys_sync not found!\n"); + return false; +} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ + +void amdkcl_suspend_init(void) +{ +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP + _kcl_ksys_sync = amdkcl_fp_setup("ksys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + _kcl_ksys_sync = amdkcl_fp_setup("sys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + pr_err_once("Error: fail to get symbol [k]sys_sync!\n"); + BUG(); +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index ad5877b16d5eb..4b24c3a605f99 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,11 +4,13 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); +extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_io_init(); + amdkcl_suspend_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 87d0726958c30..b2967b3646dca 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -15,5 +15,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a6d2de49956d2..aea370c8e652f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -16,6 +16,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_KSYS_SYNC_HELPER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 new file mode 100644 index 0000000000000..039aafc937e0c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b5dee3130bb4014511f5d0dd46855ed843e3fdc8 +dnl # PM / sleep: Refactor filesystems sync to reduce duplication +dnl # +AC_DEFUN([AC_AMDGPU_KSYS_SYNC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_sync_helper(); + ], [ + AC_DEFINE(HAVE_KSYS_SYNC_HELPER, 1, + [ksys_sync_helper() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h new file mode 100644 index 0000000000000..37a3cab923aa5 --- /dev/null +++ b/include/kcl/kcl_suspend.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_SUSPEND_H +#define AMDKCL_SUSPEND_H + +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP +extern void _kcl_ksys_sync_helper(void); + +static inline void ksys_sync_helper(void) +{ + _kcl_ksys_sync_helper(); +} +#else +static inline void ksys_sync_helper(void) {} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +#endif /* AMDKCL_SUSPEND_H */ From e90be2a342e7f6f8b94515cb5b026c7ce4252cf7 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 29 Nov 2018 13:14:08 +0800 Subject: [PATCH 0335/2070] drm/amdkcl: Test whether pcie_get_{speed/width}_cap() are available v2: drm/amdkcl: [4.18] fix pcie speed and width relevant build err v3: drm/amdkcl: [4.17] fix pcie_get_speed_cap and pcie_get_width_cap v4: drm/amdkcl: refactor HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP v5: drm/amdkcl: drop kcl_pcie_get_speed_cap Signed-off-by: Slava Grigorev Reviewed-by:Kevin Wang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: changzhu Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: update check for pcie_get_{speed,width}_cap check symbols exported is enough Change-Id: I13b0ecc561a5651af73e22b7294d93eb629062df Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 99 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pcie-get-speed-width-cap.m4 | 12 +++ include/kcl/backport/kcl_pci_backport.h | 12 +++ include/kcl/kcl_pci.h | 52 ++++++++++ 8 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_pci.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 create mode 100644 include/kcl/backport/kcl_pci_backport.h create mode 100644 include/kcl/kcl_pci.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 1f0e647057017..53d332c9a9bbb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o - kcl_suspend.o + kcl_suspend.o kcl_pci.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c new file mode 100644 index 0000000000000..3068db5234542 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Bus Services, see include/linux/pci.h for further explanation. + * + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang + * + * Copyright 1997 -- 2000 Martin Mares + * For codes copied from drivers/pci/pci.c + * + * (C) Copyright 2002-2004 Greg Kroah-Hartman + * (C) Copyright 2002-2004 IBM Corp. + * (C) Copyright 2003 Matthew Wilcox + * (C) Copyright 2003 Hewlett-Packard + * (C) Copyright 2004 Jon Smirl + * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes + * For codes copied from drivers/pci/pci-sysfs.c + */ + +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +/* + * pcie_get_speed_cap - query for the PCI device's link speed capability + * @dev: PCI device to query + * + * Query the PCI device speed capability. Return the maximum link speed + * supported by the device. + */ +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) +{ + u32 lnkcap2, lnkcap; + + /* + * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link + * Speeds Vector in Link Capabilities 2 when supported, falling + * back to Max Link Speed in Link Capabilities otherwise. + */ + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + if (lnkcap2) { /* PCIe r3.0-compliant */ + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) + return PCIE_SPEED_16_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) + return PCIE_SPEED_8_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) + return PCIE_SPEED_5_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) + return PCIE_SPEED_2_5GT; + return PCI_SPEED_UNKNOWN; + } + + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap) { + if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) + return PCIE_SPEED_16_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) + return PCIE_SPEED_8_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) + return PCIE_SPEED_5_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) + return PCIE_SPEED_2_5GT; + } + + return PCI_SPEED_UNKNOWN; +} + +/** + * pcie_get_width_cap - query for the PCI device's link width capability + * @dev: PCI device to query + * + * Query the PCI device width capability. Return the maximum link width + * supported by the device. + */ +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) +{ + u32 lnkcap; + + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap) + return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; + + return PCIE_LNK_WIDTH_UNKNOWN; +} +#endif + +enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); + +enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_width_cap); + +void amdkcl_pci_init(void) +{ +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); + _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 4b24c3a605f99..fdef0bd722e7a 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,12 +4,14 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); +extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_io_init(); + amdkcl_pci_init(); amdkcl_suspend_init(); return 0; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b2967b3646dca..308ac815e14b8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -16,5 +16,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index aea370c8e652f..44e3a39addc14 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,6 +17,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_KSYS_SYNC_HELPER + AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 new file mode 100644 index 0000000000000..905b62bc15628 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # commit 576c7218a1546e0153480b208b125509cec71470 +dnl # PCI: Export pcie_get_speed_cap and pcie_get_width_cap +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pcie_get_speed_cap pcie_get_width_cap], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP, 1, + [pcie_get_speed_cap() and pcie_get_width_cap() exist]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h new file mode 100644 index 0000000000000..cc2af255e21b5 --- /dev/null +++ b/include/kcl/backport/kcl_pci_backport.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_PCI_BACKPORT_H +#define AMDKCL_PCI_BACKPORT_H + +#include +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +#define pcie_get_speed_cap _kcl_pcie_get_speed_cap +#endif +#endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h new file mode 100644 index 0000000000000..f6f8425cea3b6 --- /dev/null +++ b/include/kcl/kcl_pci.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * pci.h + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997--1999 Martin Mares + * + * PCI Express ASPM defines and function prototypes + * Copyright (c) 2007 Intel Corp. + * Zhang Yanmin (yanmin.zhang@intel.com) + * Shaohua Li (shaohua.li@intel.com) + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI Express Specification + * PCI System Design Guide + */ +#ifndef AMDKCL_PCI_H +#define AMDKCL_PCI_H + +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +#endif + +static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) +{ +#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + return pcie_get_speed_cap(dev); +#else + return _kcl_pcie_get_speed_cap(dev); +#endif +} + +static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) +{ +#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + return pcie_get_width_cap(dev); +#else + return _kcl_pcie_get_width_cap(dev); +#endif +} + +#endif /* AMDKCL_PCI_H */ From addae475d4960b9a45fc4953c679f17272f7e93c Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 20 Dec 2018 10:40:10 +0800 Subject: [PATCH 0336/2070] drm/amdkcl: Test whether ktime_get_{ns/boottime_ns}() is available drm/amdkcl: [3.17] add kcl for ktime_get_ns [why] Below commit introduce the reference to ktime_to_ns, that is not defined on linux version < 3.17, so implement it here. drm/amd/display: Use div_u64 for flip timestamp ns to ms Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui drm/amd/autoconf: Test whether ktime_get_ns() is available ktime_get_ns introduced by kernel v3.17-rc1~109^2~41 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: test whether ktime_get_boottime_ns() is available Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui drm/amdkcl: refactor ktime_xxx in kcl Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/ktime-get-boottime-ns.m4 | 32 +++++++++++++++++++ include/kcl/kcl_timekeeping.h | 30 +++++++++++++++++ 4 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 create mode 100644 include/kcl/kcl_timekeeping.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 308ac815e14b8..46e7e8026aa19 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -17,5 +17,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 44e3a39addc14..2bfb4cbcc85b8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -18,6 +18,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP + AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 new file mode 100644 index 0000000000000..234ef7efa54b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v5.2-rc5-8-g9285ec4c8b61 +dnl # timekeeping: Use proper clock specifier names in functions +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_BOOTTIME_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_boottime_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_BOOTTIME_NS, 1, + [ktime_get_boottime_ns() is available]) + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ],[ + dnl # + dnl # commit v3.16-rc5-76-g897994e32b2b + dnl # timekeeping: Provide ktime_get[*]_ns() helpers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + ktime_get_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h new file mode 100644 index 0000000000000..cddc7d78548af --- /dev/null +++ b/include/kcl/kcl_timekeeping.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_LINUX_TIMEKEEPING_H +#define _KCL_LINUX_TIMEKEEPING_H +#include + +#ifndef HAVE_KTIME_GET_NS +static inline u64 ktime_get_ns(void) +{ + return ktime_to_ns(ktime_get()); +} +#endif + +#if !defined(HAVE_KTIME_GET_BOOTTIME_NS) +#if defined(HAVE_KTIME_GET_NS) +static inline u64 ktime_get_boottime_ns(void) +{ + return ktime_get_boot_ns(); +} +#else +static inline u64 ktime_get_boottime_ns(void) +{ + struct timespec time; + + get_monotonic_boottime(&time); + return (u64)timespec_to_ns(&time); +} +#endif /* HAVE_KTIME_GET_NS */ +#endif /* HAVE_KTIME_GET_BOOTTIME_NS */ + +#endif From 85e95b66bce0153cc90372a20776b2fadbeb973c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 24 Aug 2020 15:35:12 +0800 Subject: [PATCH 0337/2070] drm/amdkcl: add kcl copy of untagged_addr Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_mm.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_mm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 46e7e8026aa19..637d09ea64712 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -18,5 +18,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h new file mode 100644 index 0000000000000..f300ba76bf794 --- /dev/null +++ b/include/kcl/kcl_mm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/ipc/util.c + * Copyright (C) 1992 Krishna Balasubramanian + * For kvmalloc/kvzalloc + */ +#ifndef AMDKCL_MM_H +#define AMDKCL_MM_H + +#include + +#ifndef untagged_addr +/* Copied from include/linux/mm.h */ +#define untagged_addr(addr) (addr) +#endif + +#endif /* AMDKCL_MM_H */ From 1c8c4dfa7bcb4807e0b1f493220edb3dd5e86c37 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 18 Feb 2019 11:00:12 +0800 Subject: [PATCH 0338/2070] drm/amdkcl: Test whether mm_access is available v1: 183d99136d50 - drm/amdkcl: add kcl mm_access funtions v2: 1ef72c2b349f - drm/amd/autoconf: Test whether mm_access is available Signed-off-by: Kevin Wang Reviewed-by: Junwei Zhang Reviewed-by: Felix Kuehling Reviewed-by: Harish Kasiviswanathan Signed-off-by: Chengming Gui Reviewed-by: Flora Cui drm/amdkcl: refactor mm_access() check Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: drop kcl_mm_access Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 11 +++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_mm_backport.h | 8 ++++++++ 5 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mm.c create mode 100644 include/kcl/backport/kcl_mm_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 53d332c9a9bbb..b943ff2fc1dfd 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o - kcl_suspend.o kcl_pci.o + kcl_suspend.o kcl_pci.o kcl_mm.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c new file mode 100644 index 0000000000000..e60ac00cba573 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/kernel/fork.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +void amdkcl_mm_init(void) +{ +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index fdef0bd722e7a..a0826323b9b29 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,6 +4,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); +extern void amdkcl_mm_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); @@ -11,6 +12,7 @@ int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_io_init(); + amdkcl_mm_init(); amdkcl_pci_init(); amdkcl_suspend_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 637d09ea64712..317504a410d22 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -18,6 +18,6 @@ #include #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h new file mode 100644 index 0000000000000..055945c8728ef --- /dev/null +++ b/include/kcl/backport/kcl_mm_backport.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MM_BACKPORT_H +#define AMDKCL_MM_BACKPORT_H +#include +#include +#include + +#endif From c5f6e5dfc48d553a52b7bb5fe9f548bf18d7ff7f Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 19:59:17 +0800 Subject: [PATCH 0339/2070] drm/amdkcl: Test whether mmu_notifier_range_blockable() is available v2: drm/amdkcl: refactor kcl copy of mmu_notifier_range_blockable v3: drm/amdkcl: refactor kcl copy of mmu_notifier_range_blockable Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 | 16 +++++++++++++ include/kcl/kcl_mmu_notifier.h | 25 +++++++++++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 create mode 100644 include/kcl/kcl_mmu_notifier.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 317504a410d22..1e55c5e5d6388 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2bfb4cbcc85b8..4b943fc42e43f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -19,6 +19,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_MMU_NOTIFIER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 new file mode 100644 index 0000000000000..06742541fd0d9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4a83bfe916f3d2100df5bc8389bd182a537ced3e +dnl # mm/mmu_notifier: helper to test if a range invalidation is blockable +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmu_notifier_range_blockable(NULL); + ], [ + AC_DEFINE(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE, 1, + [mmu_notifier_range_blockable() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mmu_notifier.h b/include/kcl/kcl_mmu_notifier.h new file mode 100644 index 0000000000000..1af9433bdbfe5 --- /dev/null +++ b/include/kcl/kcl_mmu_notifier.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MMU_NOTIFIER_H +#define AMDKCL_MMU_NOTIFIER_H + +#include + +#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) && \ + defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/* Copied from v5.1-10225-g4a83bfe916f3 include/linux/mmu_notifier.h */ +#ifdef CONFIG_MMU_NOTIFIER +static inline bool +mmu_notifier_range_blockable(const struct mmu_notifier_range *range) +{ + return range->blockable; +} +#else +static inline bool +mmu_notifier_range_blockable(const struct mmu_notifier_range *range) +{ + return true; +} +#endif +#endif /* HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE */ + +#endif /* AMDKCL_MMU_NOTIFIER_H */ From f79c175f9eb1c49be2ea83a8d87bcaf0d54d0fc6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:23:54 +0800 Subject: [PATCH 0340/2070] drm/amdkcl: add kcl copy of DPM_FLAG_NO_DIRECT_COMPLETE Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_pm.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/kcl/kcl_pm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1e55c5e5d6388..4dd8e95a4b6df 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h new file mode 100644 index 0000000000000..157fc65f14708 --- /dev/null +++ b/include/kcl/kcl_pm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * pm.h - Power management interface + * + * Copyright (C) 2000 Andrew Henroid + */ +#ifndef KCL_KCL_PM_H +#define KCL_KCL_PM_H + +#include + +/* + * v5.7-rc2-7-ge07515563d01 + * PM: sleep: core: Rename DPM_FLAG_NEVER_SKIP + */ +#ifndef DPM_FLAG_NO_DIRECT_COMPLETE +#define DPM_FLAG_NO_DIRECT_COMPLETE DPM_FLAG_NEVER_SKIP +#endif + +#endif From 27a5e1223d51b945156ce93552d0f62ae5b72f8a Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 16:51:26 +0800 Subject: [PATCH 0341/2070] drm/amdkcl: add AC_AMDGPU_DMA_FENCE_HEADERS it is a squash of: commit e1d2e9c077849c7aa9732709870762117e6c435a Author: Slava Grigorev Date: Tue Feb 25 21:30:21 2020 -0500 drm/amdkcl: Fix in-tree build if locate of output files (O=) specified Signed-off-by: Slava Grigorev commit 671508e545e8b7e6fda2209dfb2aae21e9b7ae54 Author: Slava Grigorev Date: Thu Feb 20 15:57:12 2020 -0500 drm/amdkcl: drop AC_KERNEL_TEST_HEADER_FILE_EXIST macro remove AC_KERNEL_TEST_HEADER_FILE_EXIST macro from AC_AMDGPU_DRM_DEV_SUPPORTED test Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui commit 5ebd41454f8a12b84f590c3c68e4333246ce1b53 Author: Slava Grigorev Date: Thu Feb 20 14:55:08 2020 -0500 drm/amdkcl: modify dma-fence-headers test to use AC_KERENEL_CHECK_HERDERS macro Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui commit c1f004d6344bd8c1c04343526b033c2768adfce7 Author: Flora Cui Date: Mon Nov 16 10:46:04 2020 +0800 drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling commit 49e2c50a5557ee4bd46b80c790bcca4db4cd9f3e Author: Ma Jun Date: Tue Feb 7 13:30:10 2023 +0800 drm/amdkcl: kcl-cleanup HAVE_DMA_FENCE_SET_ERROR Change-Id: I596491f1c0408de56017aa069a2211216fb08564 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi commit 42c151d86739eb7be4b3db0ff66f467e6eb1f2ba Author: Ma Jun Date: Tue Feb 7 13:32:58 2023 +0800 drm/amdkcl: kcl-cleanup HAVE_DMA_FENCE_GET_STUB Change-Id: I9ca75886eed67777eb35c3958e763d485a1d9b1f Signed-off-by: Ma Jun Signed-off-by: Flora Cui Change-Id: I2ceeb8dc72f5ed53ebdd507b71faab67c59b56ab Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 244 ++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c | 149 +++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/dma-fence-headers.m4 | 18 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_fence_backport.h | 33 +++ include/kcl/kcl_fence.h | 156 +++++++++++ include/kcl/kcl_fence_array.h | 82 ++++++ 11 files changed, 688 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence.c create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 create mode 100644 include/kcl/backport/kcl_fence_backport.h create mode 100644 include/kcl/kcl_fence.h create mode 100644 include/kcl/kcl_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c new file mode 100644 index 0000000000000..c67cae784f75a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#define CREATE_TRACE_POINTS +#include "kcl_trace.h" + +/* Copied from drivers/dma-buf/dma-fence.c */ +static bool +dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, + uint32_t *idx) +{ + int i; + + for (i = 0; i < count; ++i) { + struct dma_fence *fence = fences[i]; + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { + if (idx) + *idx = i; + return true; + } + } + return false; +} + +struct default_wait_cb { + struct dma_fence_cb base; + struct task_struct *task; +}; + +static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); + +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) +{ + struct default_wait_cb cb; + unsigned long flags; + signed long ret = timeout ? timeout : 1; + bool was_set; + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + return ret; + + spin_lock_irqsave(fence->lock, flags); + + if (intr && signal_pending(current)) { + ret = -ERESTARTSYS; + goto out; + } + + was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &fence->flags); + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + goto out; + + if (!was_set && fence->ops->enable_signaling) { + /* + * Modifications [2017-03-29] (c) [2017] + * Advanced Micro Devices, Inc. + */ + trace_kcl_fence_enable_signal(fence); + + if (!fence->ops->enable_signaling(fence)) { + dma_fence_signal_locked(fence); + goto out; + } + } + + if (!timeout) { + ret = 0; + goto out; + } + + cb.base.func = _kcl_fence_default_wait_cb; + cb.task = current; + list_add(&cb.base.node, &fence->cb_list); + + while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { + if (intr) + __set_current_state(TASK_INTERRUPTIBLE); + else + __set_current_state(TASK_UNINTERRUPTIBLE); + spin_unlock_irqrestore(fence->lock, flags); + + ret = schedule_timeout(ret); + + spin_lock_irqsave(fence->lock, flags); + if (ret > 0 && intr && signal_pending(current)) + ret = -ERESTARTSYS; + } + + if (!list_empty(&cb.base.node)) + list_del(&cb.base.node); + __set_current_state(TASK_RUNNING); + +out: + spin_unlock_irqrestore(fence->lock, flags); + return ret; +} +EXPORT_SYMBOL(_kcl_fence_default_wait); +#endif + + +/* + * Modifications [2017-09-19] (c) [2017] + * Advanced Micro Devices, Inc. + */ +#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT +signed long +_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, + bool intr, signed long timeout, uint32_t *idx) +{ + struct default_wait_cb *cb; + signed long ret = timeout; + unsigned i; + + if (WARN_ON(!fences || !count || timeout < 0)) + return -EINVAL; + + if (timeout == 0) { + for (i = 0; i < count; ++i) + if (dma_fence_is_signaled(fences[i])) { + if (idx) + *idx = i; + return 1; + } + + return 0; + } + + cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); + if (cb == NULL) { + ret = -ENOMEM; + goto err_free_cb; + } + + for (i = 0; i < count; ++i) { + struct dma_fence *fence = fences[i]; + + + cb[i].task = current; + if (dma_fence_add_callback(fence, &cb[i].base, + _kcl_fence_default_wait_cb)) { + /* This fence is already signaled */ + if (idx) + *idx = i; + goto fence_rm_cb; + } + } + + while (ret > 0) { + if (intr) + set_current_state(TASK_INTERRUPTIBLE); + else + set_current_state(TASK_UNINTERRUPTIBLE); + + if (dma_fence_test_signaled_any(fences, count, idx)) + break; + + ret = schedule_timeout(ret); + + if (ret > 0 && intr && signal_pending(current)) + ret = -ERESTARTSYS; + } + + __set_current_state(TASK_RUNNING); + +fence_rm_cb: + while (i-- > 0) + dma_fence_remove_callback(fences[i], &cb[i].base); + +err_free_cb: + kfree(cb); + + return ret; +} +EXPORT_SYMBOL(_kcl_fence_wait_any_timeout); +#endif + +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) +{ + signed long ret; + + if (WARN_ON(timeout < 0)) + return -EINVAL; + + /* + * Modifications [2017-03-29] (c) [2017] + * Advanced Micro Devices, Inc. + */ + trace_kcl_fence_wait_start(fence); + if (fence->ops->wait) + ret = fence->ops->wait(fence, intr, timeout); + else + ret = _kcl_fence_default_wait(fence, intr, timeout); + trace_kcl_fence_wait_end(fence); + return ret; +} +EXPORT_SYMBOL(_kcl_fence_wait_timeout); +#endif + +#ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING +bool _kcl_fence_enable_signaling(struct dma_fence *f) +{ + return true; +} +EXPORT_SYMBOL(_kcl_fence_enable_signaling); +#endif +/* + * Modifications [2016-12-23] (c) [2016] + * Advanced Micro Devices, Inc. + */ +void amdkcl_fence_init(void) +{ +#if defined(HAVE_LINUX_DMA_FENCE_H) + _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); +#else + _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c new file mode 100644 index 0000000000000..d42a986ecfe1d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-array: aggregate fences to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include + +#if !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) +static void fence_array_cb_func(struct fence *f, struct fence_cb *cb); + +static const char *fence_array_get_driver_name(struct fence *fence) +{ + return "fence_array"; +} + +static const char *fence_array_get_timeline_name(struct fence *fence) +{ + return "unbound"; +} + +static void fence_array_cb_func(struct fence *f, struct fence_cb *cb) +{ + struct fence_array_cb *array_cb = + container_of(cb, struct fence_array_cb, cb); + struct fence_array *array = array_cb->array; + + if (atomic_dec_and_test(&array->num_pending)) + fence_signal(&array->base); + fence_put(&array->base); +} + +static bool fence_array_enable_signaling(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + struct fence_array_cb *cb = (void *)(&array[1]); + unsigned i; + + for (i = 0; i < array->num_fences; ++i) { + cb[i].array = array; + /* + * As we may report that the fence is signaled before all + * callbacks are complete, we need to take an additional + * reference count on the array so that we do not free it too + * early. The core fence handling will only hold the reference + * until we signal the array as complete (but that is now + * insufficient). + */ + fence_get(&array->base); + if (fence_add_callback(array->fences[i], &cb[i].cb, + fence_array_cb_func)) { + fence_put(&array->base); + if (atomic_dec_and_test(&array->num_pending)) + return false; + } + } + + return true; +} + +static bool fence_array_signaled(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + + return atomic_read(&array->num_pending) <= 0; +} + +static void fence_array_release(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + unsigned i; + + for (i = 0; i < array->num_fences; ++i) + fence_put(array->fences[i]); + + kfree(array->fences); + fence_free(fence); +} + +const struct fence_ops fence_array_ops = { + .get_driver_name = fence_array_get_driver_name, + .get_timeline_name = fence_array_get_timeline_name, + .enable_signaling = fence_array_enable_signaling, + .signaled = fence_array_signaled, + .wait = _kcl_fence_default_wait, + .release = fence_array_release, +}; + +/** + * fence_array_create - Create a custom fence array + * @num_fences: [in] number of fences to add in the array + * @fences: [in] array containing the fences + * @context: [in] fence context to use + * @seqno: [in] sequence number to use + * @signal_on_any [in] signal on any fence in the array + * + * Allocate a fence_array object and initialize the base fence with fence_init(). + * In case of error it returns NULL. + * + * The caller should allocte the fences array with num_fences size + * and fill it with the fences it wants to add to the object. Ownership of this + * array is take and fence_put() is used on each fence on release. + * + * If @signal_on_any is true the fence array signals if any fence in the array + * signals, otherwise it signals when all fences in the array signal. + */ +struct fence_array *fence_array_create(int num_fences, struct fence **fences, + u64 context, unsigned seqno, + bool signal_on_any) +{ + struct fence_array *array; + size_t size = sizeof(*array); + + /* Allocate the callback structures behind the array. */ + size += num_fences * sizeof(struct fence_array_cb); + array = kzalloc(size, GFP_KERNEL); + if (!array) + return NULL; + + spin_lock_init(&array->lock); + fence_init(&array->base, &fence_array_ops, &array->lock, + context, seqno); + + array->num_fences = num_fences; + atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); + array->fences = fences; + + return array; +} +EXPORT_SYMBOL(fence_array_create); + +#endif /* !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) */ diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index a0826323b9b29..6fa81001cb06d 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,6 +3,7 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_pci_init(void); @@ -11,6 +12,7 @@ extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_fence_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_pci_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4dd8e95a4b6df..cc4e44aa4c142 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -21,5 +21,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 new file mode 100644 index 0000000000000..843491bfe3aef --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit f54d1867005c3323f5d8ad83eed823e84226c429 +dnl # dma-buf: Rename struct fence to dma_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_HEADERS], [ + AS_IF([test $HAVE_LINUX_DMA_FENCE_H], [ + AC_KERNEL_DO_BACKGROUND([ + ]) + ], [ + dnl # + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) + AC_KERNEL_DO_BACKGROUND([ + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4b943fc42e43f..dbe8857850b67 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -20,6 +20,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_DMA_FENCE_HEADERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index b8c8be307a2e7..c1e532325f1e4 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -3,5 +3,6 @@ #define AMDSCHED_BACKPORT_H #include +#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index fe8d8882b94aa..828d4c14e59f3 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -5,4 +5,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h new file mode 100644 index 0000000000000..022951286bb7d --- /dev/null +++ b/include/kcl/backport/kcl_fence_backport.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef AMDKCL_FENCE_BACKPORT_H +#define AMDKCL_FENCE_BACKPORT_H +#include + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Allow wait_any_timeout for all fences) + */ +#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT +#define dma_fence_wait_any_timeout _kcl_fence_wait_any_timeout +#endif + +/* + * commit v4.9-rc2-472-gbcc004b629d2 + * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) + * + * commit v4.9-rc2-473-g698c0f7ff216 + * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) + */ +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +#define dma_fence_default_wait _kcl_fence_default_wait +#define dma_fence_wait_timeout _kcl_fence_wait_timeout +#endif + +/* + * commit v4.14-rc3-601-g5f72db59160c + * dma-buf/fence: Sparse wants __rcu on the object itself + */ +#ifdef AMDKCL_FENCE_GET_RCU_SAFE +#define dma_fence_get_rcu_safe _kcl_fence_get_rcu_safe +#endif +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h new file mode 100644 index 0000000000000..7a869acf02b93 --- /dev/null +++ b/include/kcl/kcl_fence.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ +#ifndef AMDKCL_FENCE_H +#define AMDKCL_FENCE_H + +#include +#include +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#include +#include +#else +#include +#include +#endif + +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#define dma_fence_cb fence_cb +#define dma_fence_ops fence_ops +#define dma_fence_array fence_array +#define dma_fence fence +#define dma_fence_init fence_init +#define dma_fence_context_alloc fence_context_alloc +#define DMA_FENCE_TRACE FENCE_TRACE +#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT +#define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT +#define dma_fence_wait fence_wait +#define dma_fence_get fence_get +#define dma_fence_put fence_put +#define dma_fence_is_signaled fence_is_signaled +#define dma_fence_signal fence_signal +#define dma_fence_signal_locked fence_signal_locked +#define dma_fence_get_rcu fence_get_rcu +#define dma_fence_array_create fence_array_create +#define dma_fence_add_callback fence_add_callback +#define dma_fence_remove_callback fence_remove_callback +#define dma_fence_enable_sw_signaling fence_enable_sw_signaling +#define dma_fence_default_wait fence_default_wait + +#define dma_fence_set_error fence_set_error +#endif + +/* commit v4.5-rc3-715-gb47bcb93bbf2 + * fall back to HAVE_LINUX_DMA_FENCE_H check directly + * as it's hard to detect the implementation in kernel + */ +#if !defined(HAVE_LINUX_DMA_FENCE_H) +static inline bool dma_fence_is_later(struct dma_fence *f1, struct dma_fence *f2) +{ + if (WARN_ON(f1->context != f2->context)) + return false; + + return (int)(f1->seqno - f2->seqno) > 0; +} +#endif + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Allow wait_any_timeout for all fences) + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_FENCE_WAIT_ANY_TIMEOUT +signed long +_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, + bool intr, signed long timeout, uint32_t *idx); +#endif + +/* + * commit v4.9-rc2-472-gbcc004b629d2 + * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) + * + * commit v4.9-rc2-473-g698c0f7ff216 + * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) +#define AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout); +extern signed long _kcl_fence_wait_timeout(struct fence *fence, bool intr, + signed long timeout); +#endif + +/* + * commit v4.14-rc3-601-g5f72db59160c + * dma-buf/fence: Sparse wants __rcu on the object itself + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) +#define AMDKCL_FENCE_GET_RCU_SAFE +static inline struct dma_fence * +_kcl_fence_get_rcu_safe(struct dma_fence __rcu **fencep) +{ + do { + struct dma_fence *fence; + + fence = rcu_dereference(*fencep); + if (!fence) + return NULL; + + if (!dma_fence_get_rcu(fence)) + continue; + + /* The atomic_inc_not_zero() inside dma_fence_get_rcu() + * provides a full memory barrier upon success (such as now). + * This is paired with the write barrier from assigning + * to the __rcu protected fence pointer so that if that + * pointer still matches the current fence, we know we + * have successfully acquire a reference to it. If it no + * longer matches, we are holding a reference to some other + * reallocated pointer. This is possible if the allocator + * is using a freelist like SLAB_TYPESAFE_BY_RCU where the + * fence remains valid for the RCU grace period, but it + * may be reallocated. When using such allocators, we are + * responsible for ensuring the reference we get is to + * the right fence, as below. + */ + if (fence == rcu_access_pointer(*fencep)) + return rcu_pointer_handoff(fence); + + dma_fence_put(fence); + } while (1); +} +#endif + +/* + * commit v4.18-rc2-519-gc701317a3eb8 + * dma-fence: Make ->enable_signaling optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING +bool _kcl_fence_enable_signaling(struct dma_fence *f); +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL \ + .enable_signaling = _kcl_fence_enable_signaling, +#else +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL +#endif + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Make ->wait callback optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL \ + .wait = dma_fence_default_wait, +#else +#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL +#endif + +#endif /* AMDKCL_FENCE_H */ diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h new file mode 100644 index 0000000000000..8bce1cf8ff00c --- /dev/null +++ b/include/kcl/kcl_fence_array.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * this file is the copy of include/linux/fence-array.h, don't modify it + * + * fence-array: aggregates fence to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef AMDKCL_FENCE_ARRAY_H +#define AMDKCL_FENCE_ARRAY_H + +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#if defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#else +#include + +/** + * struct fence_array_cb - callback helper for fence array + * @cb: fence callback structure for signaling + * @array: reference to the parent fence array object + */ +struct fence_array_cb { + struct fence_cb cb; + struct fence_array *array; +}; + +/** + * struct fence_array - fence to represent an array of fences + * @base: fence base class + * @lock: spinlock for fence handling + * @num_fences: number of fences in the array + * @num_pending: fences in the array still pending + * @fences: array of the fences + */ +struct fence_array { + struct fence base; + + spinlock_t lock; + unsigned num_fences; + atomic_t num_pending; + struct fence **fences; +}; + +extern const struct fence_ops fence_array_ops; + +/** + * to_fence_array - cast a fence to a fence_array + * @fence: fence to cast to a fence_array + * + * Returns NULL if the fence is not a fence_array, + * or the fence_array otherwise. + */ +static inline struct fence_array *to_fence_array(struct fence *fence) +{ + if (fence->ops != &fence_array_ops) + return NULL; + + return container_of(fence, struct fence_array, base); +} + +struct fence_array *fence_array_create(int num_fences, struct fence **fences, + u64 context, unsigned seqno, + bool signal_on_any); +#endif +#endif + +#endif /* __LINUX_FENCE_ARRAY_H */ From 1bc842f4f477fdebe4eb62e5250aa4f9192b3814 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 29 Mar 2017 09:03:10 +0800 Subject: [PATCH 0342/2070] drm/amdkcl: define kcl tracepoints v2: drop legacy kcl_fence_ defines v3: move kcl_trace.h to amdkcl Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Reviewed-by: Chunming Zhou Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: rename kcl_trace.h to kcl_fence_trace.h to clarify the trace is for kcl_fence Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 + drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h | 72 ++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index b943ff2fc1dfd..39b7f12e96ae8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -6,6 +6,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_suspend.o kcl_pci.o kcl_mm.o +CFLAGS_kcl_fence.o := -I$(src) + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index c67cae784f75a..ed889c91b8dd4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -23,7 +23,7 @@ #include #define CREATE_TRACE_POINTS -#include "kcl_trace.h" +#include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ static bool diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h new file mode 100644 index 0000000000000..7c857ba3c31c0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copied from include/trace/events/dma_fence.h */ +#if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_KCL_FENCE_H + +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM kcl_fence +#define TRACE_INCLUDE_FILE kcl_fence_trace + +struct dma_fence; + +DECLARE_EVENT_CLASS(kcl_fence, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence), + + TP_STRUCT__entry( + __string(driver, fence->ops->get_driver_name(fence)) + __string(timeline, fence->ops->get_timeline_name(fence)) + __field(unsigned int, context) + __field(unsigned int, seqno) + ), + + TP_fast_assign( + __assign_str(driver, fence->ops->get_driver_name(fence)) + __assign_str(timeline, fence->ops->get_timeline_name(fence)) + __entry->context = fence->context; + __entry->seqno = fence->seqno; + ), + + TP_printk("driver=%s timeline=%s context=%u seqno=%u", + __get_str(driver), __get_str(timeline), __entry->context, + __entry->seqno) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_init, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_enable_signal, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_start, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_end, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +#endif /* _TRACE_KCL_FENCE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include From 450ddbd2a88ab07109b12e4ef76093840184b5d0 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 19 Nov 2019 15:23:53 +0800 Subject: [PATCH 0343/2070] drm/amdkcl: include dma-resv.{c,h} to dkms package introduced by v5.4-rc1~32^2~17^2~36 -commit 52791eeec1d9f4a7e7fe08aaba0b1553149d93bc -dma-buf: rename reservation_object to dma_resv Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Signed-off-by: Jiansong Chen Signed-off-by: Slava Grigorev Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Chengming Gui Signed-off-by: Yifan Zhang Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Change-Id: I9b909f512608759f78d88a02254ab3bcdeb366fd drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 + drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 41 ++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/dkms/Makefile | 4 ++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 51 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 5 ++ drivers/gpu/drm/amd/dkms/sources | 3 + include/kcl/kcl_dma-resv.h | 65 ++++++++++++++++++++ include/kcl/kcl_reservation.h | 12 ++++ include/kcl/reservation.h | 9 +++ 12 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_reservation.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 create mode 100644 include/kcl/kcl_dma-resv.h create mode 100644 include/kcl/kcl_reservation.h create mode 100644 include/kcl/reservation.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 39b7f12e96ae8..787538c678ffc 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,9 +2,12 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o +amdkcl-y += dma-buf/dma-resv.o + amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_suspend.o kcl_pci.o kcl_mm.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 501b9055ad408..a5a39207c730e 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c" diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c new file mode 100644 index 0000000000000..6dc0517f2509a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include "kcl_common.h" + +void amdkcl_reservation_init(void) +{ + amdkcl_fp_setup("reservation_ww_class", NULL); +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 6fa81001cb06d..36fce46b5ff81 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,6 +4,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_fence_init(void); +extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_pci_init(void); @@ -13,6 +14,7 @@ int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_fence_init(); + amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_pci_init(); diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 7c227452be97c..dbace6b3bc0ae 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,6 +12,10 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(shell grep "HAVE_DMA_RESV_SEQ" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),n) +$(error dma_resv->seq is missing., exit...) +endif + ifdef CONFIG_CC_IS_GCC GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 new file mode 100644 index 0000000000000..c1060c688a017 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -0,0 +1,51 @@ +dnl # +dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates +dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv +dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, + [dma_resv->seq is available]) + ]) + ]) +]) + +dnl # +dnl # v4.19-rc6-1514-g27836b641c1b +dnl # dma-buf: remove shared fence staging in reservation object +dnl # +AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_LINUX_DMA_RESV_H = x ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct reservation_object *resv = NULL; + resv->staged = NULL; + ], [ + AC_DEFINE(HAVE_RESERVATION_OBJECT_STAGED, 1, + [reservation_object->staged is available]) + ]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DMA_RESV], [ + AC_AMDGPU_DMA_RESV_SEQ + AC_AMDGPU_RESERVATION_OBJECT_STAGED +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dbe8857850b67..14e15b4cedad9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -21,6 +21,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS + AC_AMDGPU_DMA_RESV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 698e69b364c03..7d481851f944d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -38,6 +38,11 @@ for sym in $SYMS; do }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h + # add amd prefix to exported symbols for file in $FILES; do awk -F'[()]' '/EXPORT_SYMBOL/ { diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index b8f2af052e55a..3470a58a43676 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -24,3 +24,6 @@ include/drm/gpu_scheduler.h include/drm/ include/drm/amd_asic_type.h include/drm/ include/drm/spsc_queue.h include/drm/ include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ +include/linux/dma-resv.h include/linux/ +include/kcl/reservation.h include/linux/ diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h new file mode 100644 index 0000000000000..be88ddb4c0d1b --- /dev/null +++ b/include/kcl/kcl_dma-resv.h @@ -0,0 +1,65 @@ +/* + * Header file for reservations for dma-buf and ttm + * + * Copyright(C) 2011 Linaro Limited. All rights reserved. + * Copyright (C) 2012-2013 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * Thomas Hellstrom + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * NOTICE: + * THIS HEADER IS FOR DMA-RESV.H ONLY + * DO NOT INCLUDE THIS HEADER ANY OTHER PLACE + * INCLUDE LINUX/DMA-RESV.H OR LINUX/RESERVATION.H INSTEAD + */ +#ifndef KCL_KCL_DMA_RESV_H +#define KCL_KCL_DMA_RESV_H + +#include +#include + +struct dma_resv_list; + +struct dma_resv { + struct ww_mutex lock; + seqcount_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; + +#if !defined(smp_store_mb) +#define smp_store_mb set_mb +#endif +#endif diff --git a/include/kcl/kcl_reservation.h b/include/kcl/kcl_reservation.h new file mode 100644 index 0000000000000..32d6d2b8b7826 --- /dev/null +++ b/include/kcl/kcl_reservation.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_KCL_RESERVATION_H +#define KCL_KCL_RESERVATION_H + +#include + +#ifndef HAVE_LINUX_DMA_RESV_H +#define reservation_object dma_resv +#define reservation_object_list dma_resv_list +#endif + +#endif /* AMDKCL_RESERVATION_H */ diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h new file mode 100644 index 0000000000000..8dcc5e3c18479 --- /dev/null +++ b/include/kcl/reservation.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_RESERVATION_H +#define KCL_RESERVATION_H + +#ifndef HAVE_LINUX_DMA_RESV_H +#include +#endif /* HAVE_LINUX_DMA_RESV_H */ + +#endif From 41973b64f7efe2bdf2d135c9658fada321bb362c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 18 Aug 2020 12:50:51 +0800 Subject: [PATCH 0344/2070] drm/amdkcl: rework reservatio_object->staged case handle reservation_object->staged incase it get updated by 3rd-party driver. Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 147 +++++++++++++++++++ include/kcl/kcl_dma-resv.h | 11 ++ include/kcl/reservation.h | 17 +++ 3 files changed, 175 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 6dc0517f2509a..16393735a2f43 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -39,3 +39,150 @@ void amdkcl_reservation_init(void) { amdkcl_fp_setup("reservation_ww_class", NULL); } + +#if defined(HAVE_RESERVATION_OBJECT_STAGED) +static void +reservation_object_add_shared_inplace(struct reservation_object *obj, + struct reservation_object_list *fobj, + struct dma_fence *fence) +{ + struct dma_fence *signaled = NULL; + u32 i, signaled_idx; + + dma_fence_get(fence); + + preempt_disable(); + write_seqcount_begin(&obj->seq); + + for (i = 0; i < fobj->shared_count; ++i) { + struct dma_fence *old_fence; + + old_fence = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + + if (old_fence->context == fence->context) { + /* memory barrier is added by write_seqcount_begin */ + RCU_INIT_POINTER(fobj->shared[i], fence); + write_seqcount_end(&obj->seq); + preempt_enable(); + + dma_fence_put(old_fence); + return; + } + + if (!signaled && dma_fence_is_signaled(old_fence)) { + signaled = old_fence; + signaled_idx = i; + } + } + + /* + * memory barrier is added by write_seqcount_begin, + * fobj->shared_count is protected by this lock too + */ + if (signaled) { + RCU_INIT_POINTER(fobj->shared[signaled_idx], fence); + } else { + BUG_ON(fobj->shared_count >= fobj->shared_max); + RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); + fobj->shared_count++; + } + + write_seqcount_end(&obj->seq); + preempt_enable(); + + dma_fence_put(signaled); +} + +static void +reservation_object_add_shared_replace(struct reservation_object *obj, + struct reservation_object_list *old, + struct reservation_object_list *fobj, + struct dma_fence *fence) +{ + unsigned i, j, k; + + dma_fence_get(fence); + + if (!old) { + RCU_INIT_POINTER(fobj->shared[0], fence); + fobj->shared_count = 1; + goto done; + } + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) { + struct dma_fence *check; + + check = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + + if (check->context == fence->context || + dma_fence_is_signaled(check)) + RCU_INIT_POINTER(fobj->shared[--k], check); + else + RCU_INIT_POINTER(fobj->shared[j++], check); + } + fobj->shared_count = j; + RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); + fobj->shared_count++; + +done: + preempt_disable(); + write_seqcount_begin(&obj->seq); + /* + * RCU_INIT_POINTER can be used here, + * seqcount provides the necessary barriers + */ + RCU_INIT_POINTER(obj->fence, fobj); + write_seqcount_end(&obj->seq); + preempt_enable(); + + if (!old) + return; + + /* Drop the references to the signaled fences */ + for (i = k; i < fobj->shared_max; ++i) { + struct dma_fence *f; + + f = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + dma_fence_put(f); + } + kfree_rcu(old, rcu); +} + +void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) +{ + struct dma_resv_list *old, *fobj = obj->staged; + + old = dma_resv_get_list(obj); + obj->staged = NULL; + + if (!fobj) + reservation_object_add_shared_inplace(obj, old, fence); + else + reservation_object_add_shared_replace(obj, old, fobj, fence); +} +EXPORT_SYMBOL(_kcl_dma_resv_add_shared_fence); + +int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + int ret; + + ret = dma_resv_copy_fences(dst, src); + if (ret) + return ret; + + kfree(dst->staged); + dst->staged = NULL; + + return ret; +} +EXPORT_SYMBOL(_kcl_dma_resv_copy_fences); +#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index be88ddb4c0d1b..5658e14dad4fe 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -51,13 +51,24 @@ struct dma_resv_list; +#if defined(HAVE_RESERVATION_OBJECT_STAGED) struct dma_resv { struct ww_mutex lock; seqcount_t seq; struct dma_fence __rcu *fence_excl; struct dma_resv_list __rcu *fence; + struct dma_resv_list *staged; }; +#else +struct dma_resv { + struct ww_mutex lock; + seqcount_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; +#endif #if !defined(smp_store_mb) #define smp_store_mb set_mb diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h index 8dcc5e3c18479..fbd036fdd650d 100644 --- a/include/kcl/reservation.h +++ b/include/kcl/reservation.h @@ -4,6 +4,23 @@ #ifndef HAVE_LINUX_DMA_RESV_H #include + +#if defined(HAVE_RESERVATION_OBJECT_STAGED) +static inline void +_kcl_reservation_object_fini(struct reservation_object *obj) +{ + dma_resv_fini(obj); + kfree(obj->staged); +} +#define amddma_resv_fini _kcl_reservation_object_fini + +void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence); +#define amddma_resv_add_shared_fence _kcl_dma_resv_add_shared_fence + +int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src); +#define amddma_resv_copy_fences _kcl_dma_resv_copy_fences + +#endif /* HAVE_RESERVATION_OBJECT_STAGED */ #endif /* HAVE_LINUX_DMA_RESV_H */ #endif From 57c0d5c01ba848914f853e4a29a420b9a39fb416 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 3 Sep 2020 16:13:29 +0800 Subject: [PATCH 0345/2070] drm/amdkcl: test seqcount_ww_mutex_init for dma_resv Signed-off-by: Flora Cui drm/amdkcl: include kcl_common.h in every .c Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 5 ++- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 42 ++++++++++++++------ include/kcl/kcl_dma-resv.h | 11 ++++- include/kcl/kcl_seqlock.h | 30 ++++++++++++++ 5 files changed, 74 insertions(+), 15 deletions(-) create mode 100644 include/kcl/kcl_seqlock.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 16393735a2f43..5bb5b8b68e64e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -33,7 +33,6 @@ * Authors: Thomas Hellstrom */ #include -#include "kcl_common.h" void amdkcl_reservation_init(void) { @@ -41,6 +40,10 @@ void amdkcl_reservation_init(void) } #if defined(HAVE_RESERVATION_OBJECT_STAGED) +/* + * Copied from v4.19-rc6-1514-g27836b641c1b^:drivers/dma-buf/reservation.c + * and modified for KCL + */ static void reservation_object_add_shared_inplace(struct reservation_object *obj, struct reservation_object_list *fobj, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cc4e44aa4c142..ce0462991cb29 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index c1060c688a017..1ede56611c58d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -1,26 +1,42 @@ dnl # -dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates -dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv -dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number +dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex +dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key dnl # AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_LINUX_DMA_RESV_H #include - #else - #include - #endif ], [ - #ifdef HAVE_LINUX_DMA_RESV_H - struct dma_resv *resv = NULL; - #else - struct reservation_object *resv = NULL; - #endif - write_seqcount_begin(&resv->seq); + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, + [dma_resv->seq is seqcount_ww_mutex_t]) AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, [dma_resv->seq is available]) + ], [ + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, + [dma_resv->seq is available]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 5658e14dad4fe..680f1fe9c1757 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -48,10 +48,19 @@ #include #include +#include struct dma_resv_list; -#if defined(HAVE_RESERVATION_OBJECT_STAGED) +#if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) +struct dma_resv { + struct ww_mutex lock; + seqcount_ww_mutex_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; +#elif defined(HAVE_RESERVATION_OBJECT_STAGED) struct dma_resv { struct ww_mutex lock; seqcount_t seq; diff --git a/include/kcl/kcl_seqlock.h b/include/kcl/kcl_seqlock.h new file mode 100644 index 0000000000000..39f2aa7baa4e5 --- /dev/null +++ b/include/kcl/kcl_seqlock.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SEQLOCK_H +#define _KCL_KCL_SEQLOCK_H + +#include + +#ifndef write_seqcount_begin +struct ww_mutex; +static __always_inline void +seqcount_ww_mutex_init(seqcount_t *s, struct ww_mutex *lock) +{ + seqcount_init(s); +} + +static inline void _kcl_write_seqcount_begin(seqcount_t *s) +{ + preempt_disable(); + write_seqcount_begin(s); +} +#define write_seqcount_begin _kcl_write_seqcount_begin + +static inline void _kcl_write_seqcount_end(seqcount_t *s) +{ + write_seqcount_end(s); + preempt_enable(); +} +#define write_seqcount_end _kcl_write_seqcount_end +#endif /* write_seqcount_begin */ + +#endif From b56c7e737deb0351a7f591b14a8d58d12ffa8733 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 16:44:20 +0800 Subject: [PATCH 0346/2070] drm/amdkcl: Test whether drm_need_swiotlb() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Change-Id: I14e2af5f5522e3ab8398f137f9d4af1cb144498f drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c | 66 ++++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 | 16 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_cache.h | 41 ++++++++++++++ 6 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 create mode 100644 include/kcl/kcl_drm_cache.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 787538c678ffc..09259a8c6a5f8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_suspend.o kcl_pci.o kcl_mm.o - kcl_fence.o kcl_fence_array.o kcl_reservation.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c new file mode 100644 index 0000000000000..85894bf3907c6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c @@ -0,0 +1,66 @@ +/* + * \file drm_memory.c + * Memory management wrappers for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +#include +#include + +/* Copied from drivers/gpu/drm/drm_memory.c */ +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits) +{ + struct resource *tmp; + resource_size_t max_iomem = 0; + + /* + * Xen paravirtual hosts require swiotlb regardless of requested dma + * transfer size. + * + * NOTE: Really, what it requires is use of the dma_alloc_coherent + * allocator used in ttm_dma_populate() instead of + * ttm_populate_and_map_pages(), which bounce buffers so much in + * Xen it leads to swiotlb buffer exhaustion. + */ + if (xen_pv_domain()) + return true; + + for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { + max_iomem = max(max_iomem, tmp->end); + } + + return max_iomem > ((u64)1 << dma_bits); +} +EXPORT_SYMBOL(drm_need_swiotlb); +#endif /* HAVE_DRM_NEED_SWIOTLB */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ce0462991cb29..eeb5a9825a4ec 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -23,5 +23,7 @@ #include #include #include +#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 new file mode 100644 index 0000000000000..42911c2cc2131 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 913b2cb727b7a47ccf8842d54c89f1b873c6deed +dnl # drm: change func to better detect wether swiotlb is needed +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CACHE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_need_swiotlb(0); + ], [ + AC_DEFINE(HAVE_DRM_NEED_SWIOTLB, 1, + [drm_need_swiotlb() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 14e15b4cedad9..c77e384680e6b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -22,6 +22,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV + AC_AMDGPU_DRM_CACHE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_cache.h b/include/kcl/kcl_drm_cache.h new file mode 100644 index 0000000000000..861205f2403bd --- /dev/null +++ b/include/kcl/kcl_drm_cache.h @@ -0,0 +1,41 @@ +/************************************************************************** + * + * Copyright 2009 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Dave Airlie + */ +#ifndef AMDKCL_DRM_CACHE_H +#define AMDKCL_DRM_CACHE_H +#include +#include + +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits); +#endif /* HAVE_DRM_NEED_SWIOTLB */ + +#endif /* AMDKCL_DRM_CACHE_H */ From 978e333f8b4a8f1e149d834aae7ea5cae1bbfec1 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Mar 2020 19:14:53 -0400 Subject: [PATCH 0347/2070] drm/amdkcl: backport drm_arch_can_wc_memory() function Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_drm_cache_backport.h | 10 ++++++ include/kcl/kcl_drm_cache.h | 35 +++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 include/kcl/backport/kcl_drm_cache_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index eeb5a9825a4ec..87f561713a3b7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -24,6 +24,6 @@ #include #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_cache_backport.h b/include/kcl/backport/kcl_drm_cache_backport.h new file mode 100644 index 0000000000000..bc936463073e5 --- /dev/null +++ b/include/kcl/backport/kcl_drm_cache_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_CACHE_BACKPORT_H +#define AMDKCL_DRM_CACHE_BACKPORT_H + +#include +#include + +#define drm_arch_can_wc_memory kcl_drm_arch_can_wc_memory + +#endif /* AMDKCL_DRM_CACHE_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_cache.h b/include/kcl/kcl_drm_cache.h index 861205f2403bd..8350e1faa62b5 100644 --- a/include/kcl/kcl_drm_cache.h +++ b/include/kcl/kcl_drm_cache.h @@ -38,4 +38,39 @@ bool drm_need_swiotlb(int dma_bits); #endif /* HAVE_DRM_NEED_SWIOTLB */ +/* + * Copied from include/drm/drm_cache.h + * v5.4-rc2-80-g268a2d600130 MIPS: Loongson64: Rename CPU TYPES + */ +static inline bool kcl_drm_arch_can_wc_memory(void) +{ +#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) + return false; +#elif defined(CONFIG_MIPS) && \ + (defined(CONFIG_CPU_LOONGSON64) || defined(CPU_LOONGSON3)) + + return false; +#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) + /* + * The DRM driver stack is designed to work with cache coherent devices + * only, but permits an optimization to be enabled in some cases, where + * for some buffers, both the CPU and the GPU use uncached mappings, + * removing the need for DMA snooping and allocation in the CPU caches. + * + * The use of uncached GPU mappings relies on the correct implementation + * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU + * will use cached mappings nonetheless. On x86 platforms, this does not + * seem to matter, as uncached CPU mappings will snoop the caches in any + * case. However, on ARM and arm64, enabling this optimization on a + * platform where NoSnoop is ignored results in loss of coherency, which + * breaks correct operation of the device. Since we have no way of + * detecting whether NoSnoop works or not, just disable this + * optimization entirely for ARM and arm64. + */ + return false; +#else + return true; +#endif +} + #endif /* AMDKCL_DRM_CACHE_H */ From c3fe710ba6816a16714408873cbbac722acbc202 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 22:41:34 +0800 Subject: [PATCH 0348/2070] drm/amdkcl: test whether drm_debug_enabled() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 19 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 38 +++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 create mode 100644 include/kcl/kcl_drm_print.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 87f561713a3b7..4d14ac4dd01f2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -25,5 +25,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 new file mode 100644 index 0000000000000..0baf031bd2e3d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v5.3-rc1-708-gf0a8f533adc2 +dnl # drm/print: add drm_debug_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_print.h], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c77e384680e6b..4ecbf98ae7cfd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -23,6 +23,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_DRM_CACHE + AC_AMDGPU_DRM_DEBUG_ENABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h new file mode 100644 index 0000000000000..03dce456987d5 --- /dev/null +++ b/include/kcl/kcl_drm_print.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#ifndef AMDKCL_DRM_PRINT_H +#define AMDKCL_DRM_PRINT_H + +#include +#include + +#ifndef HAVE_DRM_DEBUG_ENABLED +/* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ +static inline bool drm_debug_enabled(unsigned int category) +{ + return unlikely(drm_debug & category); +} +#endif /* HAVE_DRM_DEBUG_ENABLED */ +#endif From 183e3b68059ddfa606002c29dab17604567f4406 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 12 Jul 2018 14:38:53 -0400 Subject: [PATCH 0349/2070] drm/amdkcl: Test whether drm_fb_helper_remove_conflicting_pci_framebuffers() is available v1: drm/amdkcl: Test whether remove_conflicting_framebuffers() returns int v2: drm/amdkcl: Test whether drm_fb_helper_remove_conflicting_framebuffers() is available v3: drm/amdkcl: refactor drm_fb_helper_remove_conflicting_pci_framebuffers() check v4: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-remove-conflicting-pci-framebuffers.m4 v5: for drm_fb_helper_remove_conflicting_pci_framebuffers v6: split to kcl_drm_fb.c v7: drm/amdkcl: fix license for kcl drm part v8: drm/amdkcl: split fbmem related stuff Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I0bfd8baf89e77660fe2d017610a3c997001e39a2 --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 43 ++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + ...per-remove-conflicting-pci-framebuffers.m4 | 57 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_fb.h | 31 +++++++ include/kcl/kcl_drm_fb.h | 80 +++++++++++++++++++ 7 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 create mode 100644 include/kcl/backport/kcl_drm_fb.h create mode 100644 include/kcl/kcl_drm_fb.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 09259a8c6a5f8..5be165720c386 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,8 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_suspend.o kcl_pci.o kcl_mm.o - kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ + kcl_drm_fb.o kcl_fbmem.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c new file mode 100644 index 0000000000000..11a2fe7ab066e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -0,0 +1,43 @@ +/* + * linux/drivers/video/fbmem.c + * + * Copyright (C) 1994 Martin Schaller + * + * 2001 - Documented with DocBook + * - Brad Douglas + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include + +/* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) +{ + struct apertures_struct *ap; + bool primary = false; + int err = 0; + + ap = alloc_apertures(1); + if (!ap) + return -ENOMEM; + + ap->ranges[0].base = pci_resource_start(pdev, res_id); + ap->ranges[0].size = pci_resource_len(pdev, res_id); +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & + IORESOURCE_ROM_SHADOW; +#endif +#ifdef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT + err = remove_conflicting_framebuffers(ap, name, primary); +#else + remove_conflicting_framebuffers(ap, name, primary); +#endif + kfree(ap); + return err; +} +EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4d14ac4dd01f2..e13b2062cff4a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -26,5 +26,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..fe519aa4941d2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.3-rc1-541-g35616a4aa919 +dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit v4.19-rc1-110-g4d18975c78f2 + dnl # Author: Michał Mirosław + dnl # Date: Sat Sep 1 16:08:45 2018 +0200 + dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 + dnl # video/fb: Propagate error code from failing to unregister conflicting fb + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret = remove_conflicting_framebuffers(NULL, NULL, false); + ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, + [remove_conflicting_framebuffers() returns int]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ecbf98ae7cfd..95688a5941152 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,6 +24,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h new file mode 100644 index 0000000000000..c83d4ffd135b4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_fb.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef KCL_BACKPORT_KCL_DRM_FB_H +#define KCL_BACKPORT_KCL_DRM_FB_H + +#include +#include + +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) +#define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers +#endif +#endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h new file mode 100644 index 0000000000000..b05eecd7ae2bf --- /dev/null +++ b/include/kcl/kcl_drm_fb.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef KCL_KCL_DRM_FB_H +#define KCL_KCL_DRM_FB_H + +#include +#include +#include + +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(IS_REACHABLE) +/* Copied from include/linux/kconfig.h */ +#define __ARG_PLACEHOLDER_1 0, +#define __take_second_arg(__ignored, val, ...) val + +/* + * The use of "&&" / "||" is limited in certain expressions. + * The followings enable to calculate "and" / "or" with macro expansion only. + */ +#define __and(x, y) ___and(x, y) +#define ___and(x, y) ____and(__ARG_PLACEHOLDER_##x, y) +#define ____and(arg1_or_junk, y) __take_second_arg(arg1_or_junk y, 0) + +#define __or(x, y) ___or(x, y) +#define ___or(x, y) ____or(__ARG_PLACEHOLDER_##x, y) +#define ____or(arg1_or_junk, y) __take_second_arg(arg1_or_junk 1, y) + +#define IS_REACHABLE(option) __or(IS_BUILTIN(option), \ + __and(IS_MODULE(option), __is_defined(MODULE))) +#endif /*IS_REACHABLE*/ + +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, + const char *name); +static inline int +_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#if IS_REACHABLE(CONFIG_FB) + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return 0; +#endif +} +#elif !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) +static inline int +_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); +} +#endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ + +#endif From 172c57f6835eca55e27ef08d2dcc0742b8ef3248 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 26 Aug 2020 10:06:31 +0800 Subject: [PATCH 0350/2070] drm/amdkcl: add macro DRM_MODE_ROTATE_xxx v2: move to kcl_drm_crtc.h v3: fix license for kcl drm part Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_drm_crtc.h | 76 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 include/kcl/kcl_drm_crtc.h diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h new file mode 100644 index 0000000000000..f027ec142c74e --- /dev/null +++ b/include/kcl/kcl_drm_crtc.h @@ -0,0 +1,76 @@ +/* + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * For codes copied from include/drm/drm_crtc.h + * + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * For codes copied from include/drm/drm_crtc_helper.h + * + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2007 Jakob Bornecrantz + * Copyright (c) 2008 Red Hat Inc. + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA + * Copyright (c) 2007-2008 Intel Corporation + * For codes copied from include/drm/drm_mode.h + * + * Copyright 2018 Intel Corporation + * For codes copied from include/drm/drm_util.h + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_encoder.h + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_framebuffer.h + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_CRTC_H +#define KCL_KCL_DRM_CRTC_H + +#include +#include + +/* Copied from include/drm/drm_mode.h */ +#ifndef DRM_MODE_ROTATE_0 +#define DRM_MODE_ROTATE_0 (1<<0) +#endif +#ifndef DRM_MODE_ROTATE_90 +#define DRM_MODE_ROTATE_90 (1<<1) +#endif +#ifndef DRM_MODE_ROTATE_180 +#define DRM_MODE_ROTATE_180 (1<<2) +#endif +#ifndef DRM_MODE_ROTATE_270 +#define DRM_MODE_ROTATE_270 (1<<3) +#endif + +#ifndef DRM_MODE_ROTATE_MASK +#define DRM_MODE_ROTATE_MASK (\ + DRM_MODE_ROTATE_0 | \ + DRM_MODE_ROTATE_90 | \ + DRM_MODE_ROTATE_180 | \ + DRM_MODE_ROTATE_270) +#endif + +#endif From 8d6fc21ff8aa975c50f332fdc67c9f40a5217ae4 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 16:50:23 +0800 Subject: [PATCH 0351/2070] drm/amdkcl: Test whether drm_connector_update_edid_property() is available Introduced by kernel v4.19-rc1~28^2~27^2~22 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/drm-connector-update-edid-property.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 32 +++++++++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 create mode 100644 include/kcl/kcl_drm_connector.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e13b2062cff4a..52b3d22e84935 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -27,5 +27,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 new file mode 100644 index 0000000000000..eade2ed63d298 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit c555f02371c338b06752577aebf738dbdb6907bd +dnl # drm: drop _mode_ from update_edit_property() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_update_edid_property(NULL, NULL); + ],[drm_connector_update_edid_property],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY, 1, + [drm_connector_update_edid_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 95688a5941152..0b5603004b883 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -25,6 +25,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h new file mode 100644 index 0000000000000..ce58a5236fbac --- /dev/null +++ b/include/kcl/kcl_drm_connector.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef AMDKCL_DRM_CONNECTOR_H +#define AMDKCL_DRM_CONNECTOR_H + +#include +#include + +#ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY +#define drm_connector_update_edid_property drm_mode_connector_update_edid_property +#endif + +#endif /* AMDKCL_DRM_CONNECTOR_H */ From a878f64755ca62c4660b159b132a3b9648868126 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 16:58:01 +0800 Subject: [PATCH 0352/2070] drm/amdkcl: Test whether drm_connector_attach_encoder() is available Introduced by kernel v4.19-rc1~28^2~27^2~21 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- .../amd/dkms/m4/drm-connector-attach-encoder.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 new file mode 100644 index 0000000000000..9b4bd0e561b64 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit cde4c44d8769c1be16074c097592c46c7d64092b +dnl # drm: drop _mode_ from drm_mode_connector_attach_encode +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_encoder(NULL, NULL); + ],[drm_connector_attach_encoder],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_ENCODER, 1, + [drm_connector_attach_encoder() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0b5603004b883..defc6738f737a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,6 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ce58a5236fbac..5e26174b89b97 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -29,4 +29,8 @@ #define drm_connector_update_edid_property drm_mode_connector_update_edid_property #endif +#ifndef HAVE_DRM_CONNECTOR_ATTACH_ENCODER +#define drm_connector_attach_encoder drm_mode_connector_attach_encoder +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From b1e40e4c8830631eac328580d205778a59098ad3 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 17:03:30 +0800 Subject: [PATCH 0353/2070] drm/amdkcl: Test whether drm_connector_set_path_property() is available Introduced by kernel v4.19-rc1~28^2~27^2~20 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- .../dkms/m4/drm-connector-set-path-property.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 new file mode 100644 index 0000000000000..f872d0db19a2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 97e14fbeb53fe060c5f6a7a07e37fd24c087ed0c +dnl # drm: drop _mode_ from remaining connector functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_path_property(NULL, NULL); + ],[drm_connector_set_path_property],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY, 1, + [drm_connector_set_path_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index defc6738f737a..3b572d691dc12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,6 +27,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER + AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 5e26174b89b97..557629af9c283 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -33,4 +33,8 @@ #define drm_connector_attach_encoder drm_mode_connector_attach_encoder #endif +#ifndef HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY +#define drm_connector_set_path_property drm_mode_connector_set_path_property +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From e85826d85ecee21f7abe69aca57327f9c4b301d7 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 14 Feb 2019 10:08:11 +0800 Subject: [PATCH 0354/2070] drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available drm_connector_for_each_possible_encoder was introduced by the below commit since 4.19-rc1, add kcl implement for older kernel. "drm: Add drm_connector_for_each_possible_encoder()" for_each_if is introduce from v4.5-rc1 . so it's not available on drm < 4.5 like rhel6.10 . v1: drm/amdkcl: [4.19] kcl for drm_connector_for_each_possible_encoder v2: drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available v3: drm_connector_for_each_possible_encoder Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- include/kcl/kcl_drm_connector.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 557629af9c283..313ab68fc65f5 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -24,6 +24,7 @@ #include #include +#include #ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY #define drm_connector_update_edid_property drm_mode_connector_update_edid_property @@ -37,4 +38,20 @@ #define drm_connector_set_path_property drm_mode_connector_set_path_property #endif +/** + * drm_connector_for_each_possible_encoder - iterate connector's possible encoders + * @connector: &struct drm_connector pointer + * @encoder: &struct drm_encoder pointer used as cursor + * @__i: int iteration cursor, for macro-internal use + */ +#ifndef drm_connector_for_each_possible_encoder +#define drm_connector_for_each_possible_encoder(connector, encoder, __i) \ + for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) && \ + (connector)->encoder_ids[(__i)] != 0; (__i)++) \ + for_each_if((encoder) = \ + drm_encoder_find((connector)->dev, NULL, \ + (connector)->encoder_ids[(__i)])) \ + +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From c7f40f05059e55f4739aad4c6a64cb8e2d39ac1f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 5 Dec 2019 15:22:06 +0800 Subject: [PATCH 0355/2070] drm/amdkcl: Test whether drm_connector_init_with_ddc is available introduced by kernel v5.3-rc1-330-g100163df4203 v2: fix typo Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_connector.c | 14 ++++++++++++++ .../amd/dkms/m4/drm-connector-init-with-ddc.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 17 +++++++++++++++++ 5 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_connector.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5be165720c386..9b1ac5a890775 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_suspend.o kcl_pci.o kcl_mm.o kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_fbmem.o + kcl_drm_fb.o kcl_fbmem.o \ + kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_connector.c new file mode 100644 index 0000000000000..ff900e261cb43 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_connector.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#include + +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return drm_connector_init(dev, connector, funcs, connector_type); +} +EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 new file mode 100644 index 0000000000000..9af2f9f8226b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-330-g100163df4203 +dnl # drm: Add drm_connector_init() variant with ddc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_init_with_ddc(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_INIT_WITH_DDC, 1, + [drm_connector_init_with_ddc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3b572d691dc12..58213f76008d3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,6 +28,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 313ab68fc65f5..ac6c066aa3376 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -54,4 +54,21 @@ #endif +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc); +static inline +int drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return _kcl_drm_connector_init_with_ddc(dev, connector, funcs, connector_type, ddc); +} +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 13b836d19f53559c694c901124eddc31727034f4 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 11 Oct 2018 13:46:20 +0800 Subject: [PATCH 0356/2070] drm/amdkcl: check whether ACPI_VIDEO_NOTIFY_PROBE is available Signed-off-by: Prike Liang Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_video.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_video.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 52b3d22e84935..aad0ccccbce80 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_video.h b/include/kcl/kcl_video.h new file mode 100644 index 0000000000000..414cfdc2439a7 --- /dev/null +++ b/include/kcl/kcl_video.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_VIDEO_H +#define AMDKCL_VIDEO_H + +#include + +#ifndef ACPI_VIDEO_NOTIFY_PROBE +#define ACPI_VIDEO_NOTIFY_PROBE 0x81 +#endif + +#endif/*AMDKCL_VIDEO_H*/ From c9e09c562c990f03c114a077aa309a8b6dd1fed8 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 18 Feb 2019 10:46:23 +0800 Subject: [PATCH 0357/2070] drm/amdkcl: Test whether ACPI_HANDLE is defined This is a squash of: drm/amdkcl: [RHEL 6] fix ACPI_HANDLE missing Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui drm/amdkcl: Test whether ACPI_HANDLE is defined Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: add comments for kcl_acpi.h Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_acpi.h | 26 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/kcl/kcl_acpi.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index aad0ccccbce80..ed1b02861a11b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h new file mode 100644 index 0000000000000..d6f499640f0b8 --- /dev/null +++ b/include/kcl/kcl_acpi.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * acpi.h - ACPI Interface + * + * Copyright (C) 2001 Paul Diefenbaugh + */ +#ifndef AMDKCL_ACPI_H +#define AMDKCL_ACPI_H + +/** + * interface change in mainline kernel 3.13 + * but only affect RHEL6 without backport + * v3.7-rc5-12-g95f8a082b9b1 ACPI / driver core: Introduce struct acpi_dev_node + * and related macros + * v3.12-8048-g7b1998116bbb ACPI / driver core: Store an ACPI device pointer in + * struct acpi_dev_node + */ + +#include + +/* Copied from include/linux/acpi.h> */ +#ifndef ACPI_HANDLE +#define ACPI_HANDLE(dev) DEVICE_ACPI_HANDLE(dev) +#endif + +#endif /* AMDKCL_ACPI_H */ From b748be877a8811de5149bb1550a17312d9afcba3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Aug 2020 15:35:29 +0800 Subject: [PATCH 0358/2070] drm/amdkcl: test kthread_{use,unuse}_mm() introduced in commit f5678e7f2ac3 ("kernel: better document the use_mm/unuse_mm API contract") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 | 11 +++++++++ include/kcl/kcl_kthread.h | 24 +++++++++++++++++++ 4 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 create mode 100644 include/kcl/kcl_kthread.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ed1b02861a11b..cee897594f385 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 58213f76008d3..d8ff895b352cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -29,6 +29,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_KTHREAD_USE_MM AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 new file mode 100644 index 0000000000000..0b62fc9008c6b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract +dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c +dnl # +AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_use_mm kthread_unuse_mm], + [kernel/kthread.c], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) +]) diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h new file mode 100644 index 0000000000000..a1394c12dd841 --- /dev/null +++ b/include/kcl/kcl_kthread.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KTHREAD_H +#define AMDKCL_KTHREAD_H + +#include +#include +#ifndef HAVE_KTHREAD_USE_MM +#include +#endif + +#ifndef HAVE_KTHREAD_USE_MM +static inline +void kthread_use_mm(struct mm_struct *mm) +{ + use_mm(mm); +} +static inline +void kthread_unuse_mm(struct mm_struct *mm) +{ + unuse_mm(mm); +} +#endif + +#endif /* AMDKCL_KTHREAD_H */ From 832439e39a327140589b309c20c1333cbbfe77c0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:18:17 +0800 Subject: [PATCH 0359/2070] drm/amdkcl: test fault_flag_allow_retry_first() Signed-off-by: Flora Cui --- .../amd/dkms/m4/fault_flag_allow_retry_first.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 8 ++++++++ 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 new file mode 100644 index 0000000000000..ce4b655254f91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.6-5709-g4064b9827063 +dnl # mm: allow VM_FAULT_RETRY for multiple times +dnl # +AC_DEFUN([AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + fault_flag_allow_retry_first(0); + ], [ + AC_DEFINE(HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST, 1, + [fault_flag_allow_retry_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d8ff895b352cf..997f69992f308 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,6 +30,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f300ba76bf794..f7616dde77031 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -14,4 +14,12 @@ #define untagged_addr(addr) (addr) #endif +#ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST +static inline bool fault_flag_allow_retry_first(unsigned int flags) +{ + return (flags & FAULT_FLAG_ALLOW_RETRY) && + (!(flags & FAULT_FLAG_TRIED)); +} +#endif + #endif /* AMDKCL_MM_H */ From 7572140d6f495358b2746bda6b0c84a0ab442fe7 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 12 Jun 2019 11:03:57 -0400 Subject: [PATCH 0360/2070] drm/amdkcl: Test whether drm_printf() function is available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 41 +++++++++++++++++++ drivers/gpu/drm/scheduler/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_print.h | 15 ++++++- 5 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 9b1ac5a890775..0ad82e2112f24 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_suspend.o kcl_pci.o kcl_mm.o kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_fbmem.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c new file mode 100644 index 0000000000000..47b68ba76db6f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#include +#include + +#if !defined(HAVE_DRM_DRM_PRINT_H) +void drm_printf(struct drm_printer *p, const char *f, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, f); + vaf.fmt = f; + vaf.va = &args; + p->printfn(p, &vaf); + va_end(args); +} +EXPORT_SYMBOL(drm_printf); +#endif diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index c1e532325f1e4..d72474310e88f 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -4,5 +4,5 @@ #include #include - +#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 828d4c14e59f3..b30be41ddd0c4 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -6,4 +6,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 03dce456987d5..4cdae9fe3968d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -25,8 +25,19 @@ #ifndef AMDKCL_DRM_PRINT_H #define AMDKCL_DRM_PRINT_H -#include -#include +#include +#include + +#if !defined(HAVE_DRM_DRM_PRINT_H) +/* Copied from include/drm/drm_print.h */ +struct drm_printer { + void (*printfn)(struct drm_printer *p, struct va_format *vaf); + void *arg; + const char *prefix; +}; + +void drm_printf(struct drm_printer *p, const char *f, ...); +#endif #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ From 43001ae32e6d95d928f945116765f8f07e925215 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:58:05 +0800 Subject: [PATCH 0361/2070] drm/amdkcl: Test whether drm_debug_printer is available v1: drm/amdkcl: Test whether drm_debug_printer() function is available v2: drm/amdkcl: fix the struct drm_printer error. v3: drm/amdkcl: fix drm_printer related checks v4: drm/amdkcl: accommodate to drmP.h removal for drm-mm-print.m4 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Slava Grigorev Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 12 ++++++++++ .../gpu/drm/amd/dkms/m4/drm-debug-printer.m4 | 16 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 22 +++++++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 47b68ba76db6f..3b5945b8bee0a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -39,3 +39,15 @@ void drm_printf(struct drm_printer *p, const char *f, ...) } EXPORT_SYMBOL(drm_printf); #endif + +#if !defined(HAVE_DRM_DEBUG_PRINTER) +void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) +{ +#if !defined(HAVE_DRM_DRM_PRINT_H) + pr_debug("%s %pV", p->prefix, vaf); +#else + pr_debug("%s %pV", "no prefix < 4.11", vaf); +#endif +} +EXPORT_SYMBOL(__drm_printfn_debug); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 new file mode 100644 index 0000000000000..3fdcea368bf1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 3d387d923c18afbacef8f14ccaa2ace2a297df74 +dnl # drm/printer: add debug printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_debug_printer(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DEBUG_PRINTER, 1, + [drm_debug_printer() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 997f69992f308..abb693bd4e8ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_DRM_DEBUG_PRINTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 4cdae9fe3968d..bd2996d38f602 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -39,6 +39,28 @@ struct drm_printer { void drm_printf(struct drm_printer *p, const char *f, ...); #endif +/** + * drm_debug_printer - construct a &drm_printer that outputs to pr_debug() + * @prefix: debug output prefix + * + * RETURNS: + * The &drm_printer object + */ +#if !defined(HAVE_DRM_DEBUG_PRINTER) +extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); + +static inline struct drm_printer drm_debug_printer(const char *prefix) +{ + struct drm_printer p = { + .printfn = __drm_printfn_debug, +#if !defined(HAVE_DRM_DRM_PRINT_H) + .prefix = prefix +#endif + }; + return p; +} +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From e3d234c7e4599a1ab8740d029f850cd5664b2316 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 22 Nov 2019 13:09:50 +0800 Subject: [PATCH 0362/2070] drm/amdkcl: check whether DRM_DEV_{ERROR/DEBUG} are available v2: move DRM_DEV_ERROR to kcl_drm.h v3: drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Reviewed-by: Felix Kuehling --- include/kcl/kcl_drm_print.h | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index bd2996d38f602..65db884854a3d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -61,6 +61,58 @@ static inline struct drm_printer drm_debug_printer(const char *prefix) } #endif +#ifndef _DRM_PRINTK +#define _DRM_PRINTK(once, level, fmt, ...) \ + do { \ + printk##once(KERN_##level "[" DRM_NAME "] " fmt, \ + ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef DRM_WARN +#define DRM_WARN(fmt, ...) \ + _DRM_PRINTK(, WARNING, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_WARN_ONCE +#define DRM_WARN_ONCE(fmt, ...) \ + _DRM_PRINTK(_once, WARNING, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_NOTE +#define DRM_NOTE(fmt, ...) \ + _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_NOTE_ONCE +#define DRM_NOTE_ONCE(fmt, ...) \ + _DRM_PRINTK(_once, NOTICE, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_ERROR +#define DRM_ERROR(fmt, ...) \ + drm_printk(KERN_ERR, DRM_UT_NONE, fmt, ##__VA_ARGS__) +#endif + +#if !defined(DRM_DEV_DEBUG) +#define DRM_DEV_DEBUG(dev, fmt, ...) \ + DRM_DEBUG(fmt, ##__VA_ARGS__) +#endif + +#if !defined(DRM_DEV_ERROR) +#define DRM_DEV_ERROR(dev, fmt, ...) \ + DRM_ERROR(fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_DEBUG_VBL +#define DRM_UT_VBL 0x20 +#define DRM_DEBUG_VBL(fmt, args...) \ + do { \ + if (unlikely(drm_debug & DRM_UT_VBL)) \ + drm_ut_debug_printk(__func__, fmt, ##args); \ + } while (0) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 3cb4e377f57ac401330d86da74efd6c32a1543da Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Mon, 24 Sep 2018 15:29:41 -0400 Subject: [PATCH 0363/2070] drm/amdkcl: Test whether drm_gem_object_put_unlocked() is available v2: drop kcl_drm_gem_object_put_unlocked v3: Add wrap for drm_gem_object_get v4: add wrap for drm_gem_object_put() v5: drm/amdkcl: split drm_gem related stuff Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 28 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_gem.h | 45 ++++++++++++++ include/kcl/kcl_drm_gem.h | 60 +++++++++++++++++++ 5 files changed, 135 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 create mode 100644 include/kcl/backport/kcl_drm_gem.h create mode 100644 include/kcl/kcl_drm_gem.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cee897594f385..777127a82a3a7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 new file mode 100644 index 0000000000000..f73dc8440b756 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlocked() +dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put +dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_gem_object_put_locked], [drivers/gpu/drm/drm_gem.c], + [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_LOCKED, 1, + [drm_gem_object_put_locked() is available]) + ], [ + dnl # + dnl # commit v4.10-rc8-1302-ge6b62714e87c + dnl # drm: Introduce drm_gem_object_{get,put}() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_gem_object_put_unlocked(NULL); + ], [drm_gem_object_put_unlocked], [drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED, 1, + [drm_gem_object_put_unlocked() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index abb693bd4e8ee..44250eb865413 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,6 +24,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER diff --git a/include/kcl/backport/kcl_drm_gem.h b/include/kcl/backport/kcl_drm_gem.h new file mode 100644 index 0000000000000..373e3719b4c57 --- /dev/null +++ b/include/kcl/backport/kcl_drm_gem.h @@ -0,0 +1,45 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_DRM_GEM_H__ +#define __KCL_BACKPORT_KCL_DRM_GEM_H__ + +#include + +#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#define drm_gem_object_put _kcl_drm_gem_object_put +#endif +#endif + +#endif diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h new file mode 100644 index 0000000000000..a0f90deb18b06 --- /dev/null +++ b/include/kcl/kcl_drm_gem.h @@ -0,0 +1,60 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_KCL_DRM_GEM_H__ +#define __KCL_KCL_DRM_GEM_H__ + +#include +#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +static inline void +_kcl_drm_gem_object_put(struct drm_gem_object *obj) +{ + return drm_gem_object_put_unlocked(obj); +} +#else +static inline void +drm_gem_object_put(struct drm_gem_object *obj) +{ + return drm_gem_object_unreference_unlocked(obj); +} + +static inline void +drm_gem_object_get(struct drm_gem_object *obj) +{ + kref_get(&obj->refcount); +} +#endif +#endif /* HAVE_DRM_GEM_OBJECT_PUT_LOCKED */ + +#endif From fc7b808622c1641207e46d3acdd2cd56c0d589a3 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 19 Sep 2019 13:44:02 +0800 Subject: [PATCH 0364/2070] drm/amdkcl: Test whether drm_fb_helper_fill_info() is available Introduced by kernel v5.2-rc1~48^2~37^2~7 v2: implement drm_fb_helper_fill_info() for kernel don't have it. v3: drm/amdkcl: drop symbol check for drm_fb_helper_fill_info v4: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-fill-info.m4 v5: move to kcl_drm_fb.h Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 26 +++++++++++++++++++ .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 22 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 6 +++++ 4 files changed, 55 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c new file mode 100644 index 0000000000000..9f5c5ddddf524 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct drm_framebuffer *fb = fb_helper->fb; + + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); + drm_fb_helper_fill_var(info, fb_helper, + sizes->fb_width, sizes->fb_height); + + info->par = fb_helper; + snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb", + fb_helper->dev->driver->name); + +} +EXPORT_SYMBOL(drm_fb_helper_fill_info); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 new file mode 100644 index 0000000000000..23832e30bd48e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit ec8bf1942567bf0736314da9723e93bcc73c131f +dnl # drm/fb-helper: Fixup fill_info cleanup +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 44250eb865413..3cb197c8d39da 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER + AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index b05eecd7ae2bf..46fdedd66a9ca 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -77,4 +77,10 @@ _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, } #endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes); +#endif + #endif From 1f756d39784eaddc8eb2b06f8be322b8f4175edc Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 22 Aug 2019 09:52:00 +0800 Subject: [PATCH 0365/2070] drm/amdkcl: Test whehter drm_fb_helper_set_suspend_unlocked() is available drm_fb_helper_set_suspend_unlocked() introduced and exported by kernel v4.9-rc1~41^2~39^2~4 v1: drm/amdkcl: drop kcl_drm_fb_helper_set_suspend_unlocked v2: drm/amdkcl: drop symbol check for drm_fb_helper_set_suspend_unlocked v3: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-set-suspend-unlocked.m4 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Jiansong Chen Signed-off-by: Flora Cui drm/amdkcl: refactor drm-fb-helper-xxx Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui drm/amdkcl: kcl-cleanup HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED Change-Id: I47eeadd6c7a9fd91ccaff1d8d7077a6961b543ee Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 1 + .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 18 +++-- ...per-remove-conflicting-pci-framebuffers.m4 | 69 +++++++++---------- include/kcl/kcl_drm_fb.h | 4 ++ 4 files changed, 47 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 9f5c5ddddf524..abdd2c27e157b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: MIT */ #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 index 23832e30bd48e..bf7fcc83d14df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -4,16 +4,14 @@ dnl # drm/fb-helper: Fixup fill_info cleanup dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - drm_fb_helper_fill_info(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, - [drm_fb_helper_fill_info() is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); ], [ AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, [drm_fb_helper_fill_info() is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 index fe519aa4941d2..ec30c7ffa874c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -4,54 +4,53 @@ dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit v4.19-rc1-110-g4d18975c78f2 + dnl # Author: Michał Mirosław + dnl # Date: Sat Sep 1 16:08:45 2018 +0200 + dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; #include + #endif #include ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) ], [ dnl # - dnl # commit v4.19-rc1-110-g4d18975c78f2 - dnl # Author: Michał Mirosław - dnl # Date: Sat Sep 1 16:08:45 2018 +0200 - dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 + dnl # video/fb: Propagate error code from failing to unregister conflicting fb dnl # - AC_KERNEL_TRY_COMPILE([ - #include - #include + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 - dnl # video/fb: Propagate error code from failing to unregister conflicting fb - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - int ret = remove_conflicting_framebuffers(NULL, NULL, false); - ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, - [remove_conflicting_framebuffers() returns int]) - ]) + int ret = remove_conflicting_framebuffers(NULL, NULL, false); + ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, + [remove_conflicting_framebuffers() returns int]) ]) ]) - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) ]) ]) ]) diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 46fdedd66a9ca..458e516f44af1 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -83,4 +83,8 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif +#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER +extern bool is_firmware_framebuffer(struct apertures_struct *a); +#endif + #endif From 04d914f3822541dfac41991c9d50a7abab3c1b5f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 12 Oct 2019 10:26:05 +0800 Subject: [PATCH 0366/2070] drm/amdkcl: check whether dev_err_once() is available Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_device.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/kcl/kcl_device.h diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h new file mode 100644 index 0000000000000..41e786bc632fb --- /dev/null +++ b/include/kcl/kcl_device.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_H +#define AMDKCL_DEVICE_H + +/* Copied from include/linux/dev_printk.h */ +#if !defined(dev_err_once) +#ifdef CONFIG_PRINTK +#define dev_level_once(dev_level, dev, fmt, ...) \ +do { \ + static bool __print_once __read_mostly; \ + \ + if (!__print_once) { \ + __print_once = true; \ + dev_level(dev, fmt, ##__VA_ARGS__); \ + } \ +} while (0) +#else +#define dev_level_once(dev_level, dev, fmt, ...) \ +do { \ + if (0) \ + dev_level(dev, fmt, ##__VA_ARGS__); \ +} while (0) +#endif + +#define dev_err_once(dev, fmt, ...) \ + dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__) +#endif +#endif /* AMDKCL_DEVICE_H */ From ad7f05bd85ce5fe19cf6040e4af448afad82f7ff Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 12 Oct 2019 10:34:57 +0800 Subject: [PATCH 0367/2070] drm/amdkcl: check whether dev_err_ratelimited() is available Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang --- include/kcl/kcl_device.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index 41e786bc632fb..d8d3ee5263d06 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -2,7 +2,8 @@ #ifndef AMDKCL_DEVICE_H #define AMDKCL_DEVICE_H -/* Copied from include/linux/dev_printk.h */ +#include + #if !defined(dev_err_once) #ifdef CONFIG_PRINTK #define dev_level_once(dev_level, dev, fmt, ...) \ @@ -25,4 +26,18 @@ do { \ #define dev_err_once(dev, fmt, ...) \ dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__) #endif + +#if !defined(dev_err_ratelimited) +#define dev_level_ratelimited(dev_level, dev, fmt, ...) \ +do { \ + static DEFINE_RATELIMIT_STATE(_rs, \ + DEFAULT_RATELIMIT_INTERVAL, \ + DEFAULT_RATELIMIT_BURST); \ + if (__ratelimit(&_rs)) \ + dev_level(dev, fmt, ##__VA_ARGS__); \ +} while (0) + +#define dev_err_ratelimited(dev, fmt, ...) \ + dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__) +#endif #endif /* AMDKCL_DEVICE_H */ From d8021d8217e95002d343525f32ab4eb0e89f42d4 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 27 Aug 2019 14:37:02 +0800 Subject: [PATCH 0368/2070] drm/amdkcl: Test whether seq_hex_dump() is available (v2) seq_hex_dump() introduced by kernel v4.3-rc1~22^2~26 v2: fix typo, autconf --> autoconf v3: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: add kcl copy of seq_hex_dump Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Reviewed-by: Felix Kuehling Change-Id: I040b0b311b0fb9ab81ed32ef57f94407bdffa013 --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +- drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c | 57 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 | 16 ++++++ include/kcl/kcl_seq_file.h | 17 +++++- 5 files changed, 92 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0ad82e2112f24..33370dcd14172 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,8 +5,8 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_io.o - kcl_suspend.o kcl_pci.o kcl_mm.o + kcl_io.o kcl_seq_file.o\ + kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c new file mode 100644 index 0000000000000..725ca1cafbfc8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/seq_file.c + * + * helper functions for making synthetic files from sequences of records. + * initial implementation -- AV, Oct 2001. + */ +#include + +/* Copied from fs/seq_file.c */ +#ifndef HAVE_SEQ_HEX_DUMP +static void seq_set_overflow(struct seq_file *m) +{ + m->count = m->size; +} + +/* A complete analogue of print_hex_dump() */ +void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii) +{ + const u8 *ptr = buf; + int i, linelen, remaining = len; + int ret; + + if (rowsize != 16 && rowsize != 32) + rowsize = 16; + + for (i = 0; i < len && !seq_has_overflowed(m); i += rowsize) { + linelen = min(remaining, rowsize); + remaining -= rowsize; + + switch (prefix_type) { + case DUMP_PREFIX_ADDRESS: + seq_printf(m, "%s%p: ", prefix_str, ptr + i); + break; + case DUMP_PREFIX_OFFSET: + seq_printf(m, "%s%.8x: ", prefix_str, i); + break; + default: + seq_printf(m, "%s", prefix_str); + break; + } + + ret = hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize, + m->buf + m->count, m->size - m->count, + ascii); + if (ret >= m->size - m->count) { + seq_set_overflow(m); + } else { + m->count += ret; + seq_putc(m, '\n'); + } + } +} +EXPORT_SYMBOL(_kcl_seq_hex_dump); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3cb197c8d39da..7bffac987ef4d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -16,6 +16,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS diff --git a/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 new file mode 100644 index 0000000000000..5765baa40af2d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 37607102c4426cf92aeb5da1b1d9a79ba6d95e3f +dnl # seq_file: provide an analogue of print_hex_dump() +dnl # +AC_DEFUN([AC_AMDGPU_SEQ_HEX_DUMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + seq_hex_dump(NULL,NULL,0,0,0,NULL,0,0); + ], [seq_hex_dump],[fs/seq_file.c], [ + AC_DEFINE(HAVE_SEQ_HEX_DUMP, 1, + [seq_hex_dump() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h index 4e7750f341705..b884645a14388 100644 --- a/include/kcl/kcl_seq_file.h +++ b/include/kcl/kcl_seq_file.h @@ -1,7 +1,10 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_SEQ_FILE_H #define AMDKCL_SEQ_FILE_H +#include + +/* Copied from linux/seq_file.h */ #ifndef DEFINE_SHOW_ATTRIBUTE #define DEFINE_SHOW_ATTRIBUTE(__name) \ static int __name ## _open(struct inode *inode, struct file *file) \ @@ -18,4 +21,16 @@ static const struct file_operations __name ## _fops = { \ } #endif +#ifndef HAVE_SEQ_HEX_DUMP +void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii); + +static inline void seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii) +{ + _kcl_seq_hex_dump(m, prefix_str, prefix_type, rowsize, groupsize, buf, len, ascii); +} +#endif #endif From ca26bdf39d5e6278842947fbfa4ccf08fd69d94a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 13 Sep 2018 15:01:36 +0800 Subject: [PATCH 0369/2070] drm/amdkcl: Enable PCIe Extended Tags if supported commit 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") fix rocm bandwidth test H2D case. add the change for kernel < 4.11 v2: export _kcl_pci_configure_extended_tags for dkms support. v3: amd/amdkcl: make sure to enable PCIe Extended Tags if supported Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pci-configure-extended-tags.m4 | 17 +++++++++++ include/kcl/kcl_pci.h | 11 +++++++ 5 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 03814a23eb540..8eec93274a542 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2422,6 +2422,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; + kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 3068db5234542..37ae2db0b36fc 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -97,3 +97,32 @@ void amdkcl_pci_init(void) _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); #endif } + +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ + u32 cap; + u16 ctl; + int ret; + + if (!pci_is_pcie(dev)) + return; + + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (ret) + return; + + if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) + return; + + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); + if (ret) + return; + + if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_EXT_TAG); + } +} +EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7bffac987ef4d..89c227892812a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -19,6 +19,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP + AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 new file mode 100644 index 0000000000000..c46dfedbf7a34 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 62ce94a7a5a54aac80975f5e6731707225d4077e +dnl # PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken +dnl # +AC_DEFUN([AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_host_bridge bridge; + bridge.no_ext_tags = 0; + ], [ + AC_DEFINE(HAVE_PCI_CONFIGURE_EXTENDED_TAGS, 1, + [PCI driver handles extended tags]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f6f8425cea3b6..ea5c3567fecd9 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -49,4 +49,15 @@ static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) #endif } +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev); +#endif + +static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) + _kcl_pci_configure_extended_tags(dev); +#endif +} + #endif /* AMDKCL_PCI_H */ From e3117316decd82c1f42d341ce1118f8f12e55a8c Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 17:10:03 +0800 Subject: [PATCH 0370/2070] drm/amdkcl: Test whether pci_dev_id() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 6 ++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 89c227892812a..868c1c1cb5f2f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -20,6 +20,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS + AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 new file mode 100644 index 0000000000000..29c0928f6bd40 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_dev_id(NULL); + ], [ + AC_DEFINE(HAVE_PCI_DEV_ID, 1, + [pci_dev_id() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index ea5c3567fecd9..6872cad16bcbb 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -60,4 +60,10 @@ static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) #endif } +#if !defined(HAVE_PCI_DEV_ID) +static inline u16 pci_dev_id(struct pci_dev *dev) +{ + return PCI_DEVID(dev->bus->number, dev->devfn); +} +#endif /* HAVE_PCI_DEV_ID */ #endif /* AMDKCL_PCI_H */ From 278a8c85b522055f08dfaabe315fe2be9ef37d94 Mon Sep 17 00:00:00 2001 From: chen gong Date: Tue, 4 Jun 2019 16:33:34 +0800 Subject: [PATCH 0371/2070] drm/amdkcl: Test whether zone_managed_pages() is available Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/zone-managed-pages.m4 | 32 +++++++++++++++++++ include/kcl/kcl_mm.h | 13 ++++++++ 3 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 868c1c1cb5f2f..d9ba2cda90e73 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -22,6 +22,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV diff --git a/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 new file mode 100644 index 0000000000000..a1228bf4f67ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v4.20-6505-g9705bea5f833 +dnl # Author: Arun KS +dnl # Date: Fri Dec 28 00:34:24 2018 -0800 +dnl # mm: convert zone->managed_pages to atomic variable +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_MANAGED_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + zone_managed_pages(NULL); + ],[ + AC_DEFINE(HAVE_ZONE_MANAGED_PAGES, 1, + [zone_managed_pages() is available]) + ],[ + dnl # + dnl # commit v3.7-4152-g9feedc9d831e + dnl # mm: introduce new field "managed_pages" to struct zone + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct zone *z = NULL; + z->managed_pages = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_ZONE_MANAGED_PAGES, 1, + [zone->managed_pages is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f7616dde77031..a55413b715857 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -22,4 +22,17 @@ static inline bool fault_flag_allow_retry_first(unsigned int flags) } #endif +#if !defined(HAVE_ZONE_MANAGED_PAGES) +static inline unsigned long zone_managed_pages(struct zone *zone) +{ +#if defined(HAVE_STRUCT_ZONE_MANAGED_PAGES) + return (unsigned long)zone->managed_pages; +#else + /* zone->managed_pages is introduced in v3.7-4152-g9feedc9d831e */ + WARN_ONCE(1, "struct zone->managed_pages don't exist. kernel is a bit old..."); + return 0; +#endif +} +#endif /* HAVE_ZONE_MANAGED_PAGES */ + #endif /* AMDKCL_MM_H */ From e12ab82f2834549ffd736770f862ac1d6f72ceda Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Tue, 26 Jun 2018 10:31:19 +0800 Subject: [PATCH 0372/2070] drm/amdkcl: Test whether vmf_insert_*() functions are available drm/amdkcl: [4.16] add kcl/kcl_mm_types.h file for ttm compatibility Signed-off-by: Prike Liang Reviewed-by: Tao Zhou Signed-off-by: Jack Gui drm/amdkcl: Test whether vmf_insert_*() functions are available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amd/autoconf: refactor kcl_mm_types.h Signed-off-by: Flora Cui Reviewed-by: Jack Gui drm/amdkcl: drop HAVE_PFN_T check outside of kcl Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: move kcl copy of vmf_* to kcl_mm.h Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 45 +++++++++++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_memory.h | 39 ++++++++++++++++++++ include/kcl/kcl_mm.h | 7 ++++ include/kcl/kcl_mm_types.h | 39 ++++++++++++++++++++ 6 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 create mode 100644 include/kcl/kcl_memory.h create mode 100644 include/kcl/kcl_mm_types.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d9ba2cda90e73..5bb600ab85992 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -23,6 +23,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_ZONE_MANAGED_PAGES + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_VMF_INSERT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV @@ -35,7 +37,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM - AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 new file mode 100644 index 0000000000000..89789fd059839 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -0,0 +1,45 @@ +dnl # +dnl # commit v4.4-6466-g34c0fd540e79 +dnl # mm, dax, pmem: introduce pfn_t +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pfn_t pfn; + pfn.val = 0; + ], [ + dnl # + dnl # commit v4.16-7358-g1c8f422059ae + dnl # mm: change return type to vm_fault_t + dnl # + AC_DEFINE(HAVE_PFN_T, 1, [pfn_t is defined]) + + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pfn_t pfn = {}; + vmf_insert_mixed(NULL, 0, pfn); + vmf_insert_pfn(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_VMF_INSERT, 1, + [vmf_insert_*() are available]) + ], [ + dnl # + dnl # commit v4.4-6475-g01c8f1c44b83 + dnl # mm, dax, gpu: convert vm_insert_mixed to pfn_t + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pfn_t pfn = {}; + vm_insert_mixed(NULL, 0, pfn); + ], [vm_insert_mixed], [mm/memory.c], [ + AC_DEFINE(HAVE_PFN_T_VM_INSERT_MIXED, 1, + [vm_insert_mixed() wants pfn_t arg]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index b30be41ddd0c4..a236255f9270d 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,4 +7,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h new file mode 100644 index 0000000000000..f5ad19a510fe8 --- /dev/null +++ b/include/kcl/kcl_memory.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_MEMORY_H +#define _KCL_KCL_MEMORY_H + +#ifndef HAVE_VMF_INSERT +static inline vm_fault_t vmf_insert_mixed(struct vm_area_struct *vma, + unsigned long addr, + pfn_t pfn) +{ + int err; +#if !defined(HAVE_PFN_T_VM_INSERT_MIXED) + err = vm_insert_mixed(vma, addr, pfn_t_to_pfn(pfn)); +#else + err = vm_insert_mixed(vma, addr, pfn); +#endif + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} + +static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) +{ + int err = vm_insert_pfn(vma, addr, pfn); + + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} + +#endif /* HAVE_VMF_INSERT */ + +#endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index a55413b715857..f4153c5edf87c 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -7,7 +7,14 @@ #ifndef AMDKCL_MM_H #define AMDKCL_MM_H +#include +#include +#include #include +#include +#include +#include +#include #ifndef untagged_addr /* Copied from include/linux/mm.h */ diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h new file mode 100644 index 0000000000000..6cf223e559d02 --- /dev/null +++ b/include/kcl/kcl_mm_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MM_TYPES_H +#define AMDKCL_MM_TYPES_H + +#include +#ifdef HAVE_PFN_T +#include +#else +/* Copied from include/linux/pfn_t.h */ +typedef struct { + u64 val; +} pfn_t; + +#define PFN_FLAGS_MASK (((unsigned long) ~PAGE_MASK) \ + << (BITS_PER_LONG - PAGE_SHIFT)) +#define PFN_SG_CHAIN (1UL << (BITS_PER_LONG - 1)) +#define PFN_SG_LAST (1UL << (BITS_PER_LONG - 2)) +#define PFN_DEV (1UL << (BITS_PER_LONG - 3)) +#define PFN_MAP (1UL << (BITS_PER_LONG - 4)) + +static inline pfn_t __pfn_to_pfn_t(unsigned long pfn, unsigned long flags) +{ + pfn_t pfn_t = { .val = pfn | (flags & PFN_FLAGS_MASK), }; + + return pfn_t; +} + +static inline unsigned long pfn_t_to_pfn(pfn_t pfn) +{ + return pfn.val & ~PFN_FLAGS_MASK; +} +#endif + +#ifndef HAVE_VMF_INSERT +typedef int vm_fault_t; +#endif + +#endif /* AMDKCL_MM_TYPES_H */ + From ca395d74f2dc1822486e84704fcd9101636946f9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:31:58 +0800 Subject: [PATCH 0373/2070] drm/amdkcl: fake kcl copy of mmap_read_lock/unlock apis v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_mm.h | 1 + include/kcl/kcl_mmap_lock.h | 48 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 include/kcl/kcl_mmap_lock.h diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f4153c5edf87c..361811c045789 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/include/kcl/kcl_mmap_lock.h b/include/kcl/kcl_mmap_lock.h new file mode 100644 index 0000000000000..b677506d80cf1 --- /dev/null +++ b/include/kcl/kcl_mmap_lock.h @@ -0,0 +1,48 @@ +#ifndef KCL_KCL_MMAP_LOCK_H +#define KCL_KCL_MMAP_LOCK_H + +#ifdef HAVE_LINUX_MMAP_LOCK_H +#include +#else +/* Copied from include/linux/mmap_lock.h */ +static inline void mmap_init_lock(struct mm_struct *mm) +{ + init_rwsem(&mm->mmap_sem); +} + +static inline void mmap_write_lock(struct mm_struct *mm) +{ + down_write(&mm->mmap_sem); +} + +static inline bool mmap_write_trylock(struct mm_struct *mm) +{ + return down_write_trylock(&mm->mmap_sem) != 0; +} + +static inline void mmap_write_unlock(struct mm_struct *mm) +{ + up_write(&mm->mmap_sem); +} + +static inline void mmap_write_downgrade(struct mm_struct *mm) +{ + downgrade_write(&mm->mmap_sem); +} + +static inline void mmap_read_lock(struct mm_struct *mm) +{ + down_read(&mm->mmap_sem); +} + +static inline bool mmap_read_trylock(struct mm_struct *mm) +{ + return down_read_trylock(&mm->mmap_sem) != 0; +} + +static inline void mmap_read_unlock(struct mm_struct *mm) +{ + up_read(&mm->mmap_sem); +} +#endif +#endif /* KCL_KCL_MMAP_LOCK_H */ From 5996f2199f277f87e2cb71c09a1a52b6a69ded5b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 18:18:15 +0800 Subject: [PATCH 0374/2070] drm/amdkcl: test whether vmf_insert_mixed_prot() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 15 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 | 20 +++++++++++++++++++ include/kcl/kcl_memory.h | 11 ++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_memory.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 33370dcd14172..4693aa0e73bd1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -6,7 +6,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_seq_file.o\ - kcl_suspend.o kcl_pci.o kcl_mm.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c new file mode 100644 index 0000000000000..fa13000906721 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#include + +#ifndef HAVE_VMF_INSERT_MIXED_PROT +vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot) +{ + struct vm_area_struct cvma = *vma; + + cvma.vm_page_prot = pgprot; + + return vmf_insert_mixed(&cvma, addr, pfn); +} +EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5bb600ab85992..4ca1b84b983c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -25,6 +25,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_VMF_INSERT + AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 new file mode 100644 index 0000000000000..53da9747196ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # 5379e4dd3220 mm, drm/ttm: Fix vm page protection handling +dnl # 574c5b3d0e4c mm: Add a vmf_insert_mixed_prot() function +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_PROT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + pfn_t pfn; + pgprot_t prot; + vmf_insert_mixed_prot(NULL, 0, pfn, prot); + ],[vmf_insert_mixed_prot],[mm/memory.c],[ + AC_DEFINE(HAVE_VMF_INSERT_MIXED_PROT, + 1, + [vmf_insert_mixed_prot() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index f5ad19a510fe8..5c7e4817d92f9 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -36,4 +36,15 @@ static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, #endif /* HAVE_VMF_INSERT */ +#ifndef HAVE_VMF_INSERT_MIXED_PROT +vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot); +static inline +vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot) +{ + return _kcl_vmf_insert_mixed_prot(vma, addr, pfn, pgprot); +} +#endif /* HAVE_VMF_INSERT_MIXED_PROT */ + #endif From 0052236823ae56a9569522796e69a579a47b890a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 18:07:17 +0800 Subject: [PATCH 0375/2070] drm/amdkcl: fake a kcl copy of vmf_insert_pfn_prot() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 28 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 35 +++++++++++++++++++ include/kcl/kcl_memory.h | 11 ++++++ 4 files changed, 75 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index fa13000906721..9d5358ca93b48 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -13,3 +13,31 @@ vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long } EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); #endif + +#ifndef HAVE_VMF_INSERT_PFN_PROT +#ifndef HAVE_VM_INSERT_PFN_PROT +int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + struct vm_area_struct cvma = *vma; + + cvma.vm_page_prot = pgprot; + + return vm_insert_pfn(&cvma, addr, pfn); +} +#endif + +vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + int err = vm_insert_pfn_prot(vma, addr, pfn, pgprot); + + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} +EXPORT_SYMBOL(_kcl_vmf_insert_pfn_prot); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ca1b84b983c0..b53565dcbdc1f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,6 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT + AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 new file mode 100644 index 0000000000000..d1f869507e4dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v4.19-6927-gf5e6d1d5f8f3 +dnl # mm: introduce vmf_insert_pfn_prot() +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + pgprot_t prot; + vmf_insert_pfn_prot(NULL, 0, 0, prot); + ],[ + AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, + 1, + [vmf_insert_pfn_prot() is available]) + ],[ + dnl # + dnl # commit v4.4-528-g1745cbc5d0de + dnl # mm: Add vm_insert_pfn_prot() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + pgprot_t prot; + vm_insert_pfn_prot(NULL, 0, 0, prot); + ],[ + AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, + 1, + [vm_insert_pfn_prot() is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index 5c7e4817d92f9..e0dac3be04b47 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -47,4 +47,15 @@ vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, } #endif /* HAVE_VMF_INSERT_MIXED_PROT */ +#ifndef HAVE_VMF_INSERT_PFN_PROT +vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot); +static inline +vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + return _kcl_vmf_insert_pfn_prot(vma, addr, pfn, pgprot); +} +#endif /* HAVE_VMF_INSERT_PFN_PROT */ + #endif From 099bd2f7174418ab10272910463f741ff024e824 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 10 Jul 2018 16:25:09 -0400 Subject: [PATCH 0376/2070] drm/amdkcl: Test whether drm_crtc_force_disable_all() is available v2: drm/amdkcl: fix drm_crtc_force_disable_all v3: drm/amdkcl: fix license for kcl drm part Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Reviewed-by: Felix Kuehling Change-Id: Iceb48227e9cf51f819af21ceb5ba231e3750dd6b --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c | 79 +++++++++++++++++++ .../amd/dkms/m4/drm-crtc-force-disable-all.m4 | 16 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_crtc.h | 6 ++ 5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4693aa0e73bd1..676fcc86afd09 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_connector.o + kcl_drm_crtc.o kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c new file mode 100644 index 0000000000000..0dab372fcb93f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2008 Red Hat Inc. + * + * DRM core CRTC related functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Keith Packard + * Eric Anholt + * Dave Airlie + * Jesse Barnes + */ +#include + +#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) +/** + * drm_crtc_force_disable - Forcibly turn off a CRTC + * @crtc: CRTC to turn off + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_force_disable(struct drm_crtc *crtc) +{ + struct drm_mode_set set = { + .crtc = crtc, + }; + + return drm_mode_set_config_internal(&set); +} +EXPORT_SYMBOL(drm_crtc_force_disable); + +/** + * drm_crtc_force_disable_all - Forcibly turn off all enabled CRTCs + * @dev: DRM device whose CRTCs to turn off + * + * Drivers may want to call this on unload to ensure that all displays are + * unlit and the GPU is in a consistent, low power state. Takes modeset locks. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_force_disable_all(struct drm_device *dev) +{ + struct drm_crtc *crtc; + int ret = 0; + + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + ret = drm_crtc_force_disable(crtc); + if (ret) + goto out; + } +out: + drm_modeset_unlock_all(dev); + return ret; +} +EXPORT_SYMBOL(drm_crtc_force_disable_all); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 new file mode 100644 index 0000000000000..68ccba497ae81 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 6a0d95285035c43361c72776b4c618f60c0f4ab4 +dnl # drm: Add helpers to turn off CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_crtc_force_disable_all(NULL); + ], [drm_crtc_force_disable_all], [drivers/gpu/drm/drm_crtc.c], [ + AC_DEFINE(HAVE_DRM_CRTC_FORCE_DISABLE_ALL, 1, + [drm_crtc_force_disable_all() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b53565dcbdc1f..b7ae56e160ceb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -41,6 +41,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO + AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index f027ec142c74e..38861d70bd9bb 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -50,6 +50,7 @@ #include #include +#include /* Copied from include/drm/drm_mode.h */ #ifndef DRM_MODE_ROTATE_0 @@ -73,4 +74,9 @@ DRM_MODE_ROTATE_270) #endif +#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) +extern int drm_crtc_force_disable(struct drm_crtc *crtc); +extern int drm_crtc_force_disable_all(struct drm_device *dev); +#endif + #endif From 0b5bfa537702a719c9a4a5d633c36098efa4c34b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Oct 2019 14:16:22 +0800 Subject: [PATCH 0377/2070] drm/amdkcl: fix drm_add_edid_modes & drm_edid_to_eld drm_edid_to_eld() is moved to drm_add_edid_modes() in commit v4.14-rc3-592-gc945b8c14bb7 and is set to static in commit v4.14-rc3-594-g79436a1c9bcc HAVE_DRM_EDID_TO_ELD check could help to avoid duplicated drm_edid_to_eld() in most cases. Signed-off-by: Flora Cui Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jiansong Chen Signed-off-by: Yifan Zhang Change-Id: Id7c442179d03f891274ecfa549ea26c16e68fa4e --- .../gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 | 19 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_encoder.h | 56 +++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 create mode 100644 include/kcl/backport/kcl_drm_encoder.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 new file mode 100644 index 0000000000000..f0efb113db67b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v4.14-rc3-594-g79436a1c9bcc +dnl # drm/edid: make drm_edid_to_eld() static +dnl # +dnl # commit v3.1-rc6-139-g76adaa34db40 +dnl # drm: support routines for HDMI/DP ELD +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_TO_ELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_to_eld(NULL, NULL); + ], [drm_edid_to_eld], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_TO_ELD, 1, + [drm_edid_to_eld() are available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b7ae56e160ceb..7ea1ec4bb49a3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,6 +42,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL + AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h new file mode 100644 index 0000000000000..07e3a75541b80 --- /dev/null +++ b/include/kcl/backport/kcl_drm_encoder.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006 Luc Verhaegen (quirks list) + * Copyright (c) 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2010 Red Hat, Inc. + * + * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from + * FB layer. + * Copyright (C) 2006 Dennis Munsie + * For codes copied from drivers/gpu/drm/drm_edid.c + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_encoder.h + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_BACKPORT_KCL_DRM_ENCODER_H +#define KCL_BACKPORT_KCL_DRM_ENCODER_H + +#include +#include + +#if defined(HAVE_DRM_EDID_TO_ELD) +static inline +int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) +{ + int ret; + + ret = drm_add_edid_modes(connector, edid); + + if (drm_edid_is_valid(edid)) + drm_edid_to_eld(connector, edid); + + return ret; +} +#define drm_add_edid_modes _kcl_drm_add_edid_modes +#endif + +#endif From 978caa9a0324157bedbd0f2dfcba8c5ace96d4bc Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Tue, 7 Jan 2020 11:41:45 +0800 Subject: [PATCH 0378/2070] drm/amdkcl: Test whether drm_dp_atomic_find_vcpi_slots() wants five arguments it is a squash of: commit 60952ca580bfaa25cb57731bd7803bae5ec5293d Author: Stanley.Yang Date: Tue Jan 7 11:41:45 2020 +0800 drm/amdkcl: Test whether drm_dp_atomic_find_vcpi_slots() wants five arguments Signed-off-by: Stanley.Yang commit 6bbc6aadcb87e88d0f7976230b8292674b835785 Author: Slava Grigorev Date: Thu Jan 23 17:08:59 2020 -0500 drm/amdkcl: fix AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS test - a logical error in the test - compiler warning about ingnoring return value Signed-off-by: Slava Grigorev commit 655092d31b7e37020ef98bda5a0401f6a13f603c Author: Flora Cui Date: Mon Nov 16 16:34:47 2020 +0800 drm/amdkcl: move kcl copy for drm_dp_mst_helper into backport part the macros definition should be in backport to warn amdkcl to NOT include it. Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 33 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 54 +++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 create mode 100644 include/kcl/backport/kcl_drm_dp_mst_helper_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 777127a82a3a7..59d4e3c123508 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,5 +32,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 new file mode 100644 index 0000000000000..448c9066f274a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -0,0 +1,33 @@ +dnl # +dnl # commit edb1ed1ab7d314e114de84003f763da34c0f34c0 +dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); + ], [drm_dp_atomic_find_vcpi_slots], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ], [ + dnl # + dnl # commit dad1c2499a8f6d7ee01db8148f05ebba73cc41bd + dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7ea1ec4bb49a3..f2070b9694391 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,6 +38,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h new file mode 100644 index 0000000000000..500c939856d17 --- /dev/null +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -0,0 +1,54 @@ +/* + * Copyright © 2014 Red Hat + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ +#define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ + +#include + +#if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) +static inline +int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div) +{ + int pbn_backup; + int req_slots; + + if (pbn_div > 0) { + pbn_backup = mgr->pbn_div; + mgr->pbn_div = pbn_div; + } + + req_slots = drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn); + + if (pbn_div > 0) + mgr->pbn_div = pbn_backup; + + return req_slots; +} +#define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots +#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ +#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ + +#endif From ca27fedfa215572b19fdfebeef9d76ee028102cd Mon Sep 17 00:00:00 2001 From: tianci yin Date: Fri, 11 Jan 2019 15:39:47 +0800 Subject: [PATCH 0379/2070] drm/amdkcl: Test whether drm_dp_cec_xxx functions are available v1: drm/amdkcl: [4.19] kcl for drm_dp_cec_* functions v2: drm/amdkcl: Test whether drm_dp_cec_xxx functions are available v3: drm/amdkcl: fix kcl_drm_dp_cec_xxx v4: drm/amdkcl: fix drm_dp_cec_xxx check v5: drm_dp_cec_xxx are inlines with CONFIG_DRM_DP_CEC undefined. v6: drm/amdkcl: drop kcl_drm_dp_cec_xxx v7: drm/amdkcl: refactor kcl check for drm_dp_cec_irq v8: drm/amdkcl: split drm_dp_cec related stuff [why] commit "drm: add support for DisplayPort CEC-Tunneling-over-AUX" introduced drm_dp_cec_* functions. commit "drm/amdgpu: add DisplayPort CEC-Tunneling-over-AUX suppor" introduced the reference of drm_dp_cec_* functions. but for kernel < 4.19, drm_dp_cec_* functions are not available. [how] "DisplayPort CEC-Tunneling-over-AUX" is a new feature, for old kernel, we can just skip it, so we just define empty drm_dp_cec* functions like CONFIG_DRM_DP_CEC is not set. Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/drm-dp-cec-correlation-functions.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_drm_dp_helper_backport.h | 21 ++++++ include/kcl/kcl_drm_dp_cec.h | 72 +++++++++++++++++++ 5 files changed, 111 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 create mode 100644 include/kcl/backport/kcl_drm_dp_helper_backport.h create mode 100644 include/kcl/kcl_drm_dp_cec.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 59d4e3c123508..020645beb27e6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,6 +32,7 @@ #include #include #include +#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 new file mode 100644 index 0000000000000..3ded1ff2015a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-555-gae85b0df124f +dnl # drm_dp_cec: add connector info support. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_cec_register_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP, 1, + [drm_dp_cec_register_connector() wants p,p interface]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f2070b9694391..9cf8ebac5fbd9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -39,6 +39,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h new file mode 100644 index 0000000000000..8a932361c9e0e --- /dev/null +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_DRM_DP_HELPER_BACKPORT_H_ +#define _KCL_DRM_DP_HELPER_BACKPORT_H_ + +#include +#include + +/* + * commit v4.19-rc1-100-g5ce70c799ac2 + * drm_dp_cec: check that aux has a transfer function + */ +#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) +#define drm_dp_cec_irq _kcl_drm_dp_cec_irq +#define drm_dp_cec_set_edid _kcl_drm_dp_cec_set_edid +#define drm_dp_cec_unset_edid _kcl_drm_dp_cec_unset_edid +#endif + +#if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) +#define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector +#endif +#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h new file mode 100644 index 0000000000000..7dc38a930f543 --- /dev/null +++ b/include/kcl/kcl_drm_dp_cec.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DisplayPort CEC-Tunneling-over-AUX support + * + * Copyright 2018 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef __KCL_KCL_DRM_DP_CEC_H__ +#define __KCL_KCL_DRM_DP_CEC_H__ + +#include + +/* + * commit v4.19-rc1-100-g5ce70c799ac2 + * drm_dp_cec: check that aux has a transfer function + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) +#define AMDKCL_DRM_DP_CEC_XXX_CHECK_CB +#endif + +/* Copied from gpu/drm/drm_dp_cec.c and modified for KCL */ +#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) +static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) +{ +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_irq(aux); +} + +static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, + const struct edid *edid) +{ +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_set_edid(aux, edid); +} + +static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) +{ +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_unset_edid(aux); +} +#endif + +#if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) +static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, + struct drm_connector *connector) +{ +#ifdef CONFIG_DRM_DP_CEC + if (WARN_ON(!aux->transfer)) + return; +#endif + + drm_dp_cec_register_connector(aux, connector->name, connector->dev->dev); +} +#endif + + +#endif From c392b3d4589678ab42ebf3f625f01ecf626ba814 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 15:29:49 +0800 Subject: [PATCH 0380/2070] drm/amdkcl: Test whether drm_dp_mst_topology_mgr_resume is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 10 ++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 new file mode 100644 index 0000000000000..3c491e182062e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-759-g6f85f73821f6 +dnl # drm/dp_mst: Add basic topology reprobing when resuming +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_topology_mgr_resume(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS, 1, + [drm_dp_mst_topology_mgr_resume() wants 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9cf8ebac5fbd9..ee0e0ca65a69d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -40,6 +40,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 500c939856d17..85fa328d0aa09 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -51,4 +51,14 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS +static inline int +_kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, + bool sync) +{ + return drm_dp_mst_topology_mgr_resume(mgr); +} +#define drm_dp_mst_topology_mgr_resume _kcl_drm_dp_mst_topology_mgr_resume +#endif + #endif From cc2f24c41c0744d595b62969184b9f5e6a1ddbee Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 18 Feb 2019 10:56:56 +0800 Subject: [PATCH 0381/2070] drm/amdkcl: Test whether __devcgroup_check_permission() is available v1: drm/amdkcl: [4.15] Export __devcgroup_check_permission base on DKMS V2: EXport __devcgroup_check_permission by looking up the kallsys. v3: drm/amdkcl: Test whether __devcgroup_check_permission() is available v4: drm/amdkcl: fix devcgroup_check_permission() check v5: update for commit d16020d7429fffd47cfb2f3ab3b6b5b362108a6e : v6: drm/amdkcl: drop kcl_devcgroup_check_permission v7: drm/amdkcl: fix license for kcl part Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Rui Teng Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- .../gpu/drm/amd/amdkcl/kcl_device_cgroup.c | 35 +++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/dkms/m4/devcgroup-check-permission.m4 | 15 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_device_cgroup_backport.h | 10 +++++ include/kcl/kcl_device_cgroup.h | 45 +++++++++++++++++++ 9 files changed, 114 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 create mode 100644 include/kcl/backport/kcl_device_cgroup_backport.h create mode 100644 include/kcl/kcl_device_cgroup.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 676fcc86afd09..6d913ead4c38b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o + kcl_drm_crtc.o kcl_connector.o \ + kcl_device_cgroup.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c new file mode 100644 index 0000000000000..1fb1830aa5039 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * device_cgroup.c - device cgroup subsystem + * + * Copyright 2007 IBM Corp + */ +#include +#include + +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) +/* + * __devcgroup_check_permission is introduced in v3.6-6796-gad676077a2ae + * as: + * static int __devcgroup_check_permission(struct dev_cgroup *dev_cgroup, + * short type, u32 major, u32 minor, + * short access) + * + * prototype change in v3.7-rc2-147-g8c9506d16925 to: + * static int __devcgroup_check_permission(short type, u32 major, u32 minor, + * short access) + * + * the current amdkcl don't support kernel earilier than v3.7-rc2-147-g8c9506d16925 + */ +int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); +EXPORT_SYMBOL(__kcl_devcgroup_check_permission); +#endif +void amdkcl_dev_cgroup_init(void) +{ +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) + __kcl_devcgroup_check_permission = amdkcl_fp_setup("__devcgroup_check_permission", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 36fce46b5ff81..69992592b782f 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,6 +3,7 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); @@ -13,6 +14,7 @@ extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_dev_cgroup_init(); amdkcl_fence_init(); amdkcl_reservation_init(); amdkcl_io_init(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index ca25343798cf3..edda16652a2cd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -38,7 +38,9 @@ #include #include #include -#include +#include +/* amdkcl: this header file is included in kcl_device_cgroup.h +#include */ #include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 020645beb27e6..9586bdc2c01b2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 new file mode 100644 index 0000000000000..0341249c5457b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.3-rc3-2427-g4b7d4d453fc4 +dnl # device_cgroup: Export devcgroup_check_permission +dnl # +AC_DEFUN([AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + devcgroup_check_permission(0, 0, 0, 0); + ], [devcgroup_check_permission], [security/device_cgroup.c], [ + AC_DEFINE(HAVE_DEVCGROUP_CHECK_PERMISSION, 1, [devcgroup_check_permission() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ee0e0ca65a69d..7b7a07f96ef45 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,6 +30,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV + AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/include/kcl/backport/kcl_device_cgroup_backport.h b/include/kcl/backport/kcl_device_cgroup_backport.h new file mode 100644 index 0000000000000..9bac47907e956 --- /dev/null +++ b/include/kcl/backport/kcl_device_cgroup_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_CGROUP_BACKPORT_H +#define AMDKCL_DEVICE_CGROUP_BACKPORT_H + +#include + +#ifndef HAVE_DEVCGROUP_CHECK_PERMISSION +#define devcgroup_check_permission _kcl_devcgroup_check_permission +#endif /* HAVE_DEVCGROUP_CHECK_PERMISSION */ +#endif diff --git a/include/kcl/kcl_device_cgroup.h b/include/kcl/kcl_device_cgroup.h new file mode 100644 index 0000000000000..3eba9b4697856 --- /dev/null +++ b/include/kcl/kcl_device_cgroup.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_CGROUP_H +#define AMDKCL_DEVICE_CGROUP_H + +#include + +/* Copied from include/linux/device_cgroup.h */ +#ifndef DEVCG_DEV_CHAR +#define DEVCG_DEV_CHAR 2 +#endif +#ifndef DEVCG_ACC_READ +#define DEVCG_ACC_READ 2 +#endif +#ifndef DEVCG_ACC_WRITE +#define DEVCG_ACC_WRITE 4 +#endif + +/* Copied from security/device_cgroup.c and modified for KCL */ +#ifndef HAVE_DEVCGROUP_CHECK_PERMISSION +#if defined(CONFIG_CGROUP_DEVICE) +extern int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); + +static inline int _kcl_devcgroup_check_permission(short type, u32 major, u32 minor, + short access) +{ +#ifdef BPF_CGROUP_RUN_PROG_DEVICE_CGROUP + int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access); + + if (rc) + return -EPERM; +#endif + + return __kcl_devcgroup_check_permission(type, major, minor, access); +} +#else +static inline int _kcl_devcgroup_check_permission(short type, u32 major, u32 minor, + short access) +{ + return 0; +} +#endif /* CONFIG_CGROUP_DEVICE */ +#endif /* HAVE_DEVCGROUP_CHECK_PERMISSION */ + +#endif /* AMDKCL_DEVICE_CGROUP_H */ From b1edf5ba784a02bafd75c42d1e0c054597279161 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 18 Feb 2019 10:45:06 +0800 Subject: [PATCH 0382/2070] drm/amdkcl: Test whether mmu_notifier_call_srcu() is available It's a squash of 1d849edd9801 drm/amdkcl: Test whether mmu_notifier_call_srcu() is available fd62e7af6cd9 drm/amdkcl: refactor mmu_notifier_unregister_no_release() c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mn.c | 43 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 | 18 ++++++++ include/kcl/kcl_mn.h | 16 +++++++ 6 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mn.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 create mode 100644 include/kcl/kcl_mn.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6d913ead4c38b..a7a2f240159b8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o \ - kcl_device_cgroup.o + kcl_device_cgroup.o kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mn.c b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c new file mode 100644 index 0000000000000..20a0c2c5a9280 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include + +/* Copied from v3.16-6588-gb972216e27d1 mm/mmu_notifier.c */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +/* + * Modifications [2017-03-14] (c) [2017] + */ + +/* + * This function allows mmu_notifier::release callback to delay a call to + * a function that will free appropriate resources. The function must be + * quick and must not block. + */ +void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)) +{ + /* changed from call_srcu to call_rcu */ + call_rcu(rcu, func); +} +EXPORT_SYMBOL_GPL(mmu_notifier_call_srcu); + +void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + spin_lock(&mm->mmu_notifier_mm->lock); + /* + * Can not use list_del_rcu() since __mmu_notifier_release + * can delete it before we hold the lock. + */ + hlist_del_init_rcu(&mn->hlist); + spin_unlock(&mm->mmu_notifier_mm->lock); + + BUG_ON(atomic_read(&mm->mm_count) <= 0); + mmdrop(mm); +} +EXPORT_SYMBOL_GPL(mmu_notifier_unregister_no_release); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9586bdc2c01b2..1bd535bbd54a6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7b7a07f96ef45..97b80e51d737e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,6 +28,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 new file mode 100644 index 0000000000000..8b1aad73065f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 @@ -0,0 +1,18 @@ +dnl # commit b972216e27d1c853eced33f8638926636c606341 +dnl # mmu_notifier: add call_srcu and sync function +dnl # for listener to delay call and sync +dnl # +dnl # commit v5.3-rc5-63-gc96245148c1e +dnl # mm/mmu_notifiers: remove unregister_no_release +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_call_srcu(NULL, NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_CALL_SRCU, 1, [mmu_notifier_call_srcu() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mn.h b/include/kcl/kcl_mn.h new file mode 100644 index 0000000000000..02e80c3b4e386 --- /dev/null +++ b/include/kcl/kcl_mn.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MN_H +#define AMDKCL_MN_H + +#include + +/* Copied from v3.16-6588-gb972216e27d1 include/linux/mmu_notifier.h */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +extern void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)); +extern void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm); +#endif + +#endif /* AMDKCL_MN_H */ From 982bd2f4c18d122facdcf3a361008756b06deca1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 1 Jun 2020 12:48:26 +0800 Subject: [PATCH 0383/2070] drm/amdkcl: fake drm_atomic_helper_plane_reset to commit v4.19-rc1-206-ge267364a6e1b. v2: 69a65a9c531c drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/kcl_drm_atomic_helper_backport.h | 11 +++++ include/kcl/kcl_drm_atomic_helper.h | 47 ++++++++++++++++++ 5 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c create mode 100644 include/kcl/backport/kcl_drm_atomic_helper_backport.h create mode 100644 include/kcl/kcl_drm_atomic_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a7a2f240159b8..5e5c96703ca76 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o \ + kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c new file mode 100644 index 0000000000000..c6c37ceca85c8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#include +#include + +#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state) +{ + state->plane = plane; + state->rotation = DRM_MODE_ROTATE_0; + +#ifdef DRM_BLEND_ALPHA_OPAQUE + state->alpha = DRM_BLEND_ALPHA_OPAQUE; +#endif +#ifdef DRM_MODE_BLEND_PREMULTI + state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; +#endif + + plane->state = state; +} +EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1bd535bbd54a6..36fe04c621a85 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -36,5 +36,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h new file mode 100644 index 0000000000000..bcb45b685a034 --- /dev/null +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H +#define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H + +#include + +#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +#define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset +#endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ + +#endif diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h new file mode 100644 index 0000000000000..661b8cd643ff2 --- /dev/null +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#ifndef AMDKCL_DRM_ATOMIC_HELPER_H +#define AMDKCL_DRM_ATOMIC_HELPER_H + +#include +#include +#include +#include +#include + +/* + * v4.19-rc1-206-ge267364a6e1b + * drm/atomic: Initialise planes with opaque alpha values + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) +#define AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state); +#endif + +#endif From 7e59236a75d3c1f2f7b7818fc659e380133ead9d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Sep 2020 11:02:03 +0800 Subject: [PATCH 0384/2070] drm/amdkcl: test __drm_atomic_helper_crtc_reset() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c | 13 +++++++++++++ .../amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 5 +++++ 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c6c37ceca85c8..c11911f2dcbc8 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -46,3 +46,16 @@ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, } EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); #endif + +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +void +__drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + if (crtc_state) + crtc_state->crtc = crtc; + + crtc->state = crtc_state; +} +EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 new file mode 100644 index 0000000000000..637a0bc453cd7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v5.1-rc2-1163-g7d26097b4beb +dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. +dnl # +AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([__drm_atomic_helper_crtc_reset], + [drivers/gpu/drm/drm_atomic_state_helper.c], + [ + AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, + [__drm_atomic_helper_crtc_reset() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 97b80e51d737e..485d572fb04dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 661b8cd643ff2..cb5c49c24cb94 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -44,4 +44,9 @@ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, struct drm_plane_state *state); #endif +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state); +#endif + #endif From b44d27e76a077f214b34e7bd371097fcd958e032 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 31 Jul 2020 17:56:07 -0400 Subject: [PATCH 0385/2070] drm/amdkcl: Enable HDCP Build by default Add HDCP config flag to the makefile It's a squash of drm/amdkcl: test whether drm_hdcp_update_content_protection is available drm/amdkcl: add kcl/kcl_drm_hdcp.h drm/amdkcl: test drm_hdcp.h for enabling hdcp Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Bhawanpreet Lakha drm/amdkcl: fix missing CONFIG_DRM_AMD_DC_HDCP check Signed-off-by: Rui Teng Reviewed-by: Jack Gui drm/amdkcl: move hdcp related stuff to kcl_drm_hdcp.c and fix license Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: Bhawanpreet Lakha Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Change-Id: Iecbc2d3cefce447cbb2a1cc10703fea226a469e5 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 + drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c | 25 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 + drivers/gpu/drm/amd/dkms/Makefile | 4 + .../m4/drm-hdcp-update-content-protection.m4 | 16 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_hdcp.h | 316 ++++++++++++++++++ 8 files changed, 368 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 create mode 100644 include/kcl/kcl_drm_hdcp.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5e5c96703ca76..e1be142a688e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,6 +12,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o +amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o + CFLAGS_kcl_fence.o := -I$(src) ccflags-y += \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c new file mode 100644 index 0000000000000..21686ff9a5950 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +/* Copied from v5.3-rc1-380-gbb5a45d40d50 drivers/gpu/drm/drm_hdcp.c */ +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + struct drm_device *dev = connector->dev; + struct drm_connector_state *state = connector->state; + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + if (state->content_protection == val) + return; + + state->content_protection = val; +} +EXPORT_SYMBOL(_kcl_drm_hdcp_update_content_protection); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 36fe04c621a85..41a3d512210e3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,5 +37,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1c53c904b832f..77660736e03b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -95,6 +95,9 @@ #include #include #include +#ifdef CONFIG_DRM_AMD_DC_HDCP +#include +#endif #include #include diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index dbace6b3bc0ae..25f48546e8d01 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -156,6 +156,10 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +ifeq ($(shell grep "HAVE_DRM_DRM_HDCP_H" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),y) +export CONFIG_DRM_AMD_DC_HDCP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +endif # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 new file mode 100644 index 0000000000000..5b8c871002830 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-380-gbb5a45d40d50 +dnl # drm/hdcp: update content protection property with uevent +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_hdcp_update_content_protection(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION, 1, + [drm_hdcp_update_content_protection is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 485d572fb04dc..fe110b5e154b8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h new file mode 100644 index 0000000000000..ba77fb5c0973a --- /dev/null +++ b/include/kcl/kcl_drm_hdcp.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2017 Google, Inc. + * + * Authors: + * Sean Paul + */ +#ifndef AMDKCL_DRM_HDCP_H +#define AMDKCL_DRM_HDCP_H + +#ifdef CONFIG_DRM_AMD_DC_HDCP +#include +#include + +/* changed in v4.16-rc7-1717-gb8e47d87be65 + * drm: Fix HDCP downstream dev count read + */ +#ifdef DRM_HDCP_NUM_DOWNSTREAM +#undef DRM_HDCP_NUM_DOWNSTREAM +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) +#endif + +/* introduced in v5.3-rc1-377-g7672dbba85d3 + * drm: Add Content protection type property + */ +#ifndef DRM_MODE_HDCP_CONTENT_TYPE0 +#define DRM_MODE_HDCP_CONTENT_TYPE0 0 +#define DRM_MODE_HDCP_CONTENT_TYPE1 1 +#endif + +/* introduced in v4.19-rc2-1221-gaf5aad059885 + * drm: hdcp2.2 authentication msg definitions + */ +#ifndef DRM_HDCP_1_4_SRM_ID +#define DRM_HDCP_1_4_SRM_ID 0x8 +#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 +#define DRM_HDCP_1_4_DCP_SIG_SIZE 40 + +/* Protocol message definition for HDCP2.2 specification */ +/* + * Protected content streams are classified into 2 types: + * - Type0: Can be transmitted with HDCP 1.4+ + * - Type1: Can be transmitted with HDCP 2.2+ + */ +#define HDCP_STREAM_TYPE0 0x00 +#define HDCP_STREAM_TYPE1 0x01 + +/* HDCP2.2 Msg IDs */ +#define HDCP_2_2_NULL_MSG 1 +#define HDCP_2_2_AKE_INIT 2 +#define HDCP_2_2_AKE_SEND_CERT 3 +#define HDCP_2_2_AKE_NO_STORED_KM 4 +#define HDCP_2_2_AKE_STORED_KM 5 +#define HDCP_2_2_AKE_SEND_HPRIME 7 +#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 +#define HDCP_2_2_LC_INIT 9 +#define HDCP_2_2_LC_SEND_LPRIME 10 +#define HDCP_2_2_SKE_SEND_EKS 11 +#define HDCP_2_2_REP_SEND_RECVID_LIST 12 +#define HDCP_2_2_REP_SEND_ACK 15 +#define HDCP_2_2_REP_STREAM_MANAGE 16 +#define HDCP_2_2_REP_STREAM_READY 17 +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 + +#define HDCP_2_2_RTX_LEN 8 +#define HDCP_2_2_RRX_LEN 8 + +#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 +#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 +#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ + HDCP_2_2_K_PUB_RX_EXP_E_LEN) + +#define HDCP_2_2_DCP_LLC_SIG_LEN 384 + +#define HDCP_2_2_E_KPUB_KM_LEN 128 +#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) +#define HDCP_2_2_H_PRIME_LEN 32 +#define HDCP_2_2_E_KH_KM_LEN 16 +#define HDCP_2_2_RN_LEN 8 +#define HDCP_2_2_L_PRIME_LEN 32 +#define HDCP_2_2_E_DKEY_KS_LEN 16 +#define HDCP_2_2_RIV_LEN 8 +#define HDCP_2_2_SEQ_NUM_LEN 3 +#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) +#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN +#define HDCP_2_2_MAX_DEVICE_COUNT 31 +#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ + HDCP_2_2_MAX_DEVICE_COUNT) +#define HDCP_2_2_MPRIME_LEN 32 + +/* Following Macros take a byte at a time for bit(s) masking */ +/* + * TODO: This has to be changed for DP MST, as multiple stream on + * same port is possible. + * For HDCP2.2 on HDMI and DP SST this value is always 1. + */ +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_TXCAP_MASK_LEN 2 +#define HDCP_2_2_RXCAPS_LEN 3 +#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) +#define HDCP_2_2_RXINFO_LEN 2 + +/* HDCP1.x compliant device in downstream */ +#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) + +/* HDCP2.0 Compliant repeater in downstream */ +#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) +#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) +#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) +#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) +#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) +#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) + +struct hdcp2_cert_rx { + u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; + u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; + u8 reserved[2]; + u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; +} __packed; + +struct hdcp2_streamid_type { + u8 stream_id; + u8 stream_type; +} __packed; + +/* + * The TxCaps field specified in the HDCP HDMI, DP specs + * This field is big endian as specified in the errata. + */ +struct hdcp2_tx_caps { + /* Transmitter must set this to 0x2 */ + u8 version; + + /* Reserved for HDCP and DP Spec. Read as Zero */ + u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; +} __packed; + +/* Main structures for HDCP2.2 protocol communication */ +struct hdcp2_ake_init { + u8 msg_id; + u8 r_tx[HDCP_2_2_RTX_LEN]; + struct hdcp2_tx_caps tx_caps; +} __packed; + +struct hdcp2_ake_send_cert { + u8 msg_id; + struct hdcp2_cert_rx cert_rx; + u8 r_rx[HDCP_2_2_RRX_LEN]; + u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; +} __packed; + +struct hdcp2_ake_no_stored_km { + u8 msg_id; + u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; +} __packed; + +struct hdcp2_ake_stored_km { + u8 msg_id; + u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; +} __packed; + +struct hdcp2_ake_send_hprime { + u8 msg_id; + u8 h_prime[HDCP_2_2_H_PRIME_LEN]; +} __packed; + +struct hdcp2_ake_send_pairing_info { + u8 msg_id; + u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; +} __packed; + +struct hdcp2_lc_init { + u8 msg_id; + u8 r_n[HDCP_2_2_RN_LEN]; +} __packed; + +struct hdcp2_lc_send_lprime { + u8 msg_id; + u8 l_prime[HDCP_2_2_L_PRIME_LEN]; +} __packed; + +struct hdcp2_ske_send_eks { + u8 msg_id; + u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; + u8 riv[HDCP_2_2_RIV_LEN]; +} __packed; + +struct hdcp2_rep_send_receiverid_list { + u8 msg_id; + u8 rx_info[HDCP_2_2_RXINFO_LEN]; + u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; + u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; + u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; +} __packed; + +struct hdcp2_rep_send_ack { + u8 msg_id; + u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; +} __packed; + +struct hdcp2_rep_stream_manage { + u8 msg_id; + u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; + __be16 k; + struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; +} __packed; + +struct hdcp2_rep_stream_ready { + u8 msg_id; + u8 m_prime[HDCP_2_2_MPRIME_LEN]; +} __packed; + +struct hdcp2_dp_errata_stream_type { + u8 msg_id; + u8 stream_type; +} __packed; +#endif /* DRM_HDCP_1_4_SRM_ID */ + +/* introduced in v4.19-rc2-1222-g8b44fefee694 + * drm: HDMI and DP specific HDCP2.2 defines + */ +#ifndef HDCP_2_2_CERT_TIMEOUT_MS +/* HDCP2.2 TIMEOUTs in mSec */ +#define HDCP_2_2_CERT_TIMEOUT_MS 100 +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 +#define HDCP_2_2_PAIRING_TIMEOUT_MS 200 +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 +#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 +#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 +#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 + +/* HDMI HDCP2.2 Register Offsets */ +#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 +#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 +#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 +#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 +#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 + +#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) +#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 +#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF +#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 + +/* Below macros take a byte at a time and mask the bit(s) */ +#define HDCP_2_2_HDMI_RXSTATUS_LEN 2 +#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) +#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) +#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +/* DP HDCP2.2 parameter offsets in DPCD address space */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/* DP HDCP message start offsets in DPCD address space */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ + DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +#define HDCP_2_2_DP_RXSTATUS_LEN 1 +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) +#endif /* HDCP_2_2_CERT_TIMEOUT_MS */ + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val); +static inline +void drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + _kcl_drm_hdcp_update_content_protection(connector, val); +} +#endif /* HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION */ + +#endif /* CONFIG_DRM_AMD_DC_HDCP */ + +#endif /* AMDKCL_DRM_HDCP_H */ From d74b64d4145e301d50e6a806b897825954d84ece Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 13 Oct 2020 08:54:27 +0800 Subject: [PATCH 0386/2070] drm/amdkcl: test jiffies64_to_msecs() fake a kcl copy for legacy kernel support. v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_time.c | 40 +++++++++++++++++++ .../gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 | 11 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_timekeeping.h | 4 ++ 5 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_time.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e1be142a688e6..7aeb90ccb78f7 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_time.c b/drivers/gpu/drm/amd/amdkcl/kcl_time.c new file mode 100644 index 0000000000000..a6394747da818 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_time.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file contains the interface functions for the various time related + * system calls: time, stime, gettimeofday, settimeofday, adjtime + * + * Modification history: + * + * 1993-09-02 Philip Gladstone + * Created file with time related functions from sched/core.c and adjtimex() + * 1993-10-08 Torsten Duwe + * adjtime interface update and CMOS clock write code + * 1995-08-13 Torsten Duwe + * kernel PLL updated to 1994-12-13 specs (rfc-1589) + * 1999-01-16 Ulrich Windl + * Introduced error checking for many cases in adjtimex(). + * Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + * Allow time_constant larger than MAXTC(6) for NTP v4 (MAXTC == 10) + * (Even though the technical memorandum forbids it) + * 2004-07-14 Christoph Lameter + * Added getnstimeofday to allow the posix timer functions to return + * with nanosecond accuracy + */ +#include +#include + +#ifndef HAVE_JIFFIES64_TO_MSECS +/* Copied from kernel/time/time.c */ +u64 jiffies64_to_msecs(const u64 j) +{ +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (MSEC_PER_SEC / HZ) * j; +#else + return div_u64(j * HZ_TO_MSEC_NUM, HZ_TO_MSEC_DEN); +#endif +} +EXPORT_SYMBOL(jiffies64_to_msecs); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 new file mode 100644 index 0000000000000..e44504998e830 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v5.1-rc3-699-g3b15d09f7e6d +dnl # time: Introduce jiffies64_to_msecs() +dnl # +AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([jiffies64_to_msecs], [kernel/time/time.c], [ + AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fe110b5e154b8..8a8987146b097 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -45,6 +45,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index cddc7d78548af..3f2db83a37b47 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -27,4 +27,8 @@ static inline u64 ktime_get_boottime_ns(void) #endif /* HAVE_KTIME_GET_NS */ #endif /* HAVE_KTIME_GET_BOOTTIME_NS */ +#ifndef HAVE_JIFFIES64_TO_MSECS +extern u64 jiffies64_to_msecs(u64 j); +#endif + #endif From 80a57abf0f8b66507c665ef4796d94631f9b19d3 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 20 Nov 2020 14:53:01 +0800 Subject: [PATCH 0387/2070] drm/amdkcl: fake the acpi_put_table() This is caused by "Put ACPI table after using it" v5.9-rc5-1537-gc435d35df6c5 v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c | 15 +++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_acpi_table.h | 18 ++++++++++++++++++ 6 files changed, 49 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 create mode 100644 include/kcl/kcl_acpi_table.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 7aeb90ccb78f7..aa8b11b1eedc4 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,6 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_time.o + kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c new file mode 100644 index 0000000000000..554bebabd4adb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/****************************************************************************** + * + * Module Name: tbxface - ACPI table-oriented external interfaces + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#include +#include + +#ifndef HAVE_ACPI_PUT_TABLE +amdkcl_dummy_symbol(acpi_put_table, void, return, + struct acpi_table_header *table) +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 41a3d512210e3..55a242c6a03c3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -38,5 +38,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 new file mode 100644 index 0000000000000..27001acd98f95 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v4.9-rc5-17-g174cc7187e6f +dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and +dnl # early_acpi_os_unmap_memory() from Linux kernel +AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_put_table], + [drivers/acpi/acpica/tbxface.c], [ + AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, + [acpi_put_table() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8a8987146b097..d4a187b2c88f1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -46,6 +46,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_acpi_table.h b/include/kcl/kcl_acpi_table.h new file mode 100644 index 0000000000000..849e8a58a2dbd --- /dev/null +++ b/include/kcl/kcl_acpi_table.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ +/****************************************************************************** + * + * Name: acpixf.h - External interfaces to the ACPI subsystem + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#ifndef KCL_KCL_ACPI_TABLE_H +#define KCL_KCL_ACPI_TABLE_H + +#include + +#ifndef HAVE_ACPI_PUT_TABLE +void acpi_put_table(struct acpi_table_header *table); +#endif + +#endif From a047d8f4f3b6e9249742de083d57fe481ea5c31f Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 8 Dec 2020 15:24:22 +0800 Subject: [PATCH 0388/2070] drm/amdkcl: fake drm_dbg_kms This is caused by "use drm_dbg_kms to log addfb2 failures" v5.9-rc5-1859-g16dba6910508 v2: copy the drm_dev_dbg implementation v3: add the autotest for drm_dev_dbg for sle sp2 support v4: drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 26 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 | 11 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 9 ++++++++ 4 files changed, 47 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 3b5945b8bee0a..3d690609edb8f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -51,3 +51,29 @@ void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) } EXPORT_SYMBOL(__drm_printfn_debug); #endif + +#if !defined(HAVE_DRM_DEV_DBG) +void drm_dev_dbg(const struct device *dev, int category, + const char *format, ...) +{ + struct va_format vaf; + va_list args; + + if (!drm_debug_enabled(category)) + return; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + if (dev) + dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV", + __builtin_return_address(0), &vaf); + else + printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(drm_dev_dbg); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 new file mode 100644 index 0000000000000..dfcc85e60e4bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v4.16-rc1-493-gdb8708649258 +dnl # drm: Reduce object size of DRM_DEV_ uses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_DBG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_dev_dbg], [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_DEV_DBG, 1, [drm_dev_dbg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d4a187b2c88f1..32c0191cca5be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -47,6 +47,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 65db884854a3d..3ead0ab2b367f 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -113,6 +113,15 @@ static inline struct drm_printer drm_debug_printer(const char *prefix) } while (0) #endif +#if !defined(HAVE_DRM_DEV_DBG) +void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); +#endif + +#if !defined(drm_dbg_kms) +#define drm_dbg_kms(drm, fmt, ...) \ + drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 863aef24a84551b6df363d6f522bfcfd7c3133f0 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 17 Dec 2020 16:33:45 +0800 Subject: [PATCH 0389/2070] drm/amdkcl: fake pci_pr3_present This is caused by "add check for ACPI power resources" v5.9-rc5-1932-gad02c8dc25c1 v2: dummy the function if CONFIG_ACPI is not defined Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci_pr3_present.m4 | 11 ++++++++++ include/kcl/kcl_pci.h | 13 ++++++++++++ 4 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 37ae2db0b36fc..7acee9d394b0b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -19,6 +19,7 @@ #include #include +#include #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) /* @@ -126,3 +127,23 @@ void _kcl_pci_configure_extended_tags(struct pci_dev *dev) } EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); #endif + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev) +{ + struct acpi_device *adev; + + if (acpi_disabled) + return false; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return false; + + return adev->power.flags.power_resources && + acpi_has_method(adev->handle, "_PR3"); +} +EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 32c0191cca5be..ccab1a79e4140 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,6 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_DEV_DBG + AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 new file mode 100644 index 0000000000000..38e50b2c0766f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v5.4-rc2-37-g52525b7a3cf8 +dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence +dnl # +AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pci_pr3_present], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 6872cad16bcbb..9f9e1439300aa 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -66,4 +66,17 @@ static inline u16 pci_dev_id(struct pci_dev *dev) return PCI_DEVID(dev->bus->number, dev->devfn); } #endif /* HAVE_PCI_DEV_ID */ + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev); +static inline bool pci_pr3_present(struct pci_dev *pdev) +{ + return _kcl_pci_pr3_present(pdev); +} +#else +static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ + #endif /* AMDKCL_PCI_H */ From 8b2e8e416ddf84e42c689c16e0d962dfa191d4c4 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 21:55:54 +0800 Subject: [PATCH 0390/2070] drm/amdkcl: Test whether drm_helper_force_disable_all() is defined v2: drm/amdkcl: fix drm_helper_force_disable_all Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_crtc.h | 8 ++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 new file mode 100644 index 0000000000000..a0e32e7654867 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef +dnl # DRM: add mode setting support +dnl # +dnl # commit c2d88e06bcb98540bb83fac874574eaa4f320363 +dnl # drm: Move the legacy kms disable_all helper to crtc helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_helper_force_disable_all(NULL); + ], [ + AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, + [drm_helper_force_disable_all() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ccab1a79e4140..c98c8603b983f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -53,6 +53,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL + AC_AMDGPU_DRM_CRTC_HELPER AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 38861d70bd9bb..daca652324951 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -79,4 +79,12 @@ extern int drm_crtc_force_disable(struct drm_crtc *crtc); extern int drm_crtc_force_disable_all(struct drm_device *dev); #endif +#if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) +static inline +int drm_helper_force_disable_all(struct drm_device *dev) +{ + return drm_crtc_force_disable_all(dev); +} +#endif + #endif From b1abd6a92943321ac91ec342d35a555c1e1a1f15 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 17 Dec 2020 16:30:35 +0800 Subject: [PATCH 0391/2070] drm/amdkcl: rework faked drm_helper_force_disable_all Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c | 57 ++++++------------- ...per.m4 => drm_helper_force_disable_all.m4} | 10 +--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_crtc.h | 8 +-- 4 files changed, 23 insertions(+), 55 deletions(-) rename drivers/gpu/drm/amd/dkms/m4/{drm-crtc-helper.m4 => drm_helper_force_disable_all.m4} (60%) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c index 0dab372fcb93f..c4e079c49d8ab 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -31,49 +31,26 @@ */ #include -#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) -/** - * drm_crtc_force_disable - Forcibly turn off a CRTC - * @crtc: CRTC to turn off - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_force_disable(struct drm_crtc *crtc) +#ifndef HAVE_DRM_HELPER_FORCE_DISABLE_ALL +int _kcl_drm_helper_force_disable_all(struct drm_device *dev) { - struct drm_mode_set set = { - .crtc = crtc, - }; - - return drm_mode_set_config_internal(&set); -} -EXPORT_SYMBOL(drm_crtc_force_disable); + struct drm_crtc *crtc; + int ret = 0; -/** - * drm_crtc_force_disable_all - Forcibly turn off all enabled CRTCs - * @dev: DRM device whose CRTCs to turn off - * - * Drivers may want to call this on unload to ensure that all displays are - * unlit and the GPU is in a consistent, low power state. Takes modeset locks. - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_force_disable_all(struct drm_device *dev) -{ - struct drm_crtc *crtc; - int ret = 0; + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + struct drm_mode_set set = { + .crtc = crtc, + }; - drm_modeset_lock_all(dev); - drm_for_each_crtc(crtc, dev) - if (crtc->enabled) { - ret = drm_crtc_force_disable(crtc); - if (ret) - goto out; - } + ret = drm_mode_set_config_internal(&set); + if (ret) + goto out; + } out: - drm_modeset_unlock_all(dev); - return ret; + drm_modeset_unlock_all(dev); + return ret; } -EXPORT_SYMBOL(drm_crtc_force_disable_all); +EXPORT_SYMBOL(_kcl_drm_helper_force_disable_all); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 similarity index 60% rename from drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 rename to drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 index a0e32e7654867..f52b3c10ccd43 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -2,16 +2,12 @@ dnl # dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef dnl # DRM: add mode setting support dnl # -dnl # commit c2d88e06bcb98540bb83fac874574eaa4f320363 +dnl # commit v5.0-rc1-118-gc2d88e06bcb9 dnl # drm: Move the legacy kms disable_all helper to crtc helpers dnl # -AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER], [ +AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_helper_force_disable_all(NULL); - ], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, [drm_helper_force_disable_all() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c98c8603b983f..0a33708aaef42 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -52,8 +52,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO - AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL - AC_AMDGPU_DRM_CRTC_HELPER + AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index daca652324951..e0eaa2ace66b1 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -74,16 +74,12 @@ DRM_MODE_ROTATE_270) #endif -#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) -extern int drm_crtc_force_disable(struct drm_crtc *crtc); -extern int drm_crtc_force_disable_all(struct drm_device *dev); -#endif - #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) +int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline int drm_helper_force_disable_all(struct drm_device *dev) { - return drm_crtc_force_disable_all(dev); + return _kcl_drm_helper_force_disable_all(dev); } #endif From 635cc4af21e45cc87d2e96aabd9e647aeaa421be Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 24 Dec 2020 11:43:48 +0800 Subject: [PATCH 0392/2070] drm/amdkcl: fix kthread_use_mm/kthread_unuse_mm redefinition error on sle sp2 server distro with kernel 5.3.18-24 define the kthread_use_mm for kcl only when it is neither defined in kthread.c nor in mmu_context.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 | 20 +++++++++++++++---- include/kcl/kcl_kthread.h | 2 -- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 index 0b62fc9008c6b..6177b3b6fa49e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -3,9 +3,21 @@ dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c dnl # AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_use_mm kthread_unuse_mm], - [kernel/kthread.c], [ - AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, - [kthread_{use,unuse}_mm() is available]) + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # sle sp2 server distro inlines kthread_use_mm/kthread_unuse_mm + dnl # in mmu_context.h + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + kthread_use_mm(NULL); + kthread_unuse_mm(NULL); + ], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) ]) ]) diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index a1394c12dd841..5bdcc30bdf314 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -4,9 +4,7 @@ #include #include -#ifndef HAVE_KTHREAD_USE_MM #include -#endif #ifndef HAVE_KTHREAD_USE_MM static inline From a46b06515baa3fbe36103ce5bc82c0f02a099c54 Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Wed, 20 Sep 2017 09:53:26 +0800 Subject: [PATCH 0393/2070] drm/amdkcl: check whether rcu_pointer_handoff is available Change-Id: Ie20100a6353d106bd3cad3e724f0157de6e6b902 Signed-off-by: Le.Ma Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- include/kcl/kcl_rcupdate.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/kcl/kcl_rcupdate.h diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h new file mode 100644 index 0000000000000..ec31bae327ead --- /dev/null +++ b/include/kcl/kcl_rcupdate.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_RCUPDATE_H +#define AMDKCL_RCUPDATE_H + +#include +#include + +#ifndef rcu_pointer_handoff +#define rcu_pointer_handoff(p) (p) +#endif + +#endif /* AMDKCL_RCUPDATE_H */ From 40dfc35b3d935a5d33ff5bbc8bb7903a84587b3f Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 13 May 2020 17:21:35 -0400 Subject: [PATCH 0394/2070] drm/amdkcl: optional devices ID for amdgpu driver Test for amdgpu-pciid.h header file Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov Reviewed-by: Tim Writer --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 8eec93274a542..4a47c0bd79469 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2190,6 +2190,10 @@ static const struct pci_device_id pciidlist[] = { .class_mask = 0xffffff, .driver_data = CHIP_IP_DISCOVERY }, +#ifdef HAVE_DRM_AMDGPU_PCIID_H +#include +#endif + {0, 0, 0} }; From f38cad9916970cf48d2d1d3cf5728ebaffb8d5c0 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 21 Aug 2020 12:44:47 +0800 Subject: [PATCH 0395/2070] drm/amdkcl: add kcl copy of drm/task_barrier.h This is a squash of: drm/amdkcl: rework drm/task_barrier.h handling Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_task_barrier.h | 86 +++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 include/kcl/kcl_task_barrier.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 55a242c6a03c3..55d41cfd9940b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_task_barrier.h b/include/kcl/kcl_task_barrier.h new file mode 100644 index 0000000000000..341fe8e02a9d9 --- /dev/null +++ b/include/kcl/kcl_task_barrier.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_TASK_BARRIER_H +#define AMDKCL_DRM_TASK_BARRIER_H + +#ifdef HAVE_DRM_TASK_BARRIER_H +#include +#else +/* + * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. + * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ + */ +#include +#include + +/* + * Represents an instance of a task barrier. + */ +struct task_barrier { + unsigned int n; + atomic_t count; + struct semaphore enter_turnstile; + struct semaphore exit_turnstile; +}; + +static inline void task_barrier_signal_turnstile(struct semaphore *turnstile, + unsigned int n) +{ + int i; + + for (i = 0 ; i < n; i++) + up(turnstile); +} + +static inline void task_barrier_init(struct task_barrier *tb) +{ + tb->n = 0; + atomic_set(&tb->count, 0); + sema_init(&tb->enter_turnstile, 0); + sema_init(&tb->exit_turnstile, 0); +} + +static inline void task_barrier_add_task(struct task_barrier *tb) +{ + tb->n++; +} + +static inline void task_barrier_rem_task(struct task_barrier *tb) +{ + tb->n--; +} + +/* + * Lines up all the threads BEFORE the critical point. + * + * When all thread passed this code the entry barrier is back to locked state. + */ +static inline void task_barrier_enter(struct task_barrier *tb) +{ + if (atomic_inc_return(&tb->count) == tb->n) + task_barrier_signal_turnstile(&tb->enter_turnstile, tb->n); + + down(&tb->enter_turnstile); +} + +/* + * Lines up all the threads AFTER the critical point. + * + * This function is used to avoid any one thread running ahead if the barrier is + * used repeatedly . + */ +static inline void task_barrier_exit(struct task_barrier *tb) +{ + if (atomic_dec_return(&tb->count) == 0) + task_barrier_signal_turnstile(&tb->exit_turnstile, tb->n); + + down(&tb->exit_turnstile); +} + +/* Convinieince function when nothing to be done in between entry and exit */ +static inline void task_barrier_full(struct task_barrier *tb) +{ + task_barrier_enter(tb); + task_barrier_exit(tb); +} +#endif +#endif From 7e4b7fbf2f5c2dfad16c96cec24cfaf28785a9f3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2019 10:37:13 +0800 Subject: [PATCH 0396/2070] drm/amdkcl: increase drm vma offset size limit v2: increase drm vma offset size limit For 8 processes share 256GB system memory application case, 1T Bytes drm vma offset limit is not big enough. Increase the limit to 16TB, for max 44bits address space because the upper bit is encoded with gpu_id. Remove the 64GB size condition check to handle all kernels, 64GB is Ubuntu kernel default setting, CentOS, Redhat kernel default is 1TB. Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Philip Yang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + .../backport/kcl_drm_vma_manager_backport.h | 58 +++++++++++++++++++ 4 files changed, 62 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_vma_manager_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4a47c0bd79469..1e39e1d4138c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2423,6 +2423,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); + kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); + if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 55d41cfd9940b..fa3328db34b52 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index a236255f9270d..e2d7fbfba2433 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #endif diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h new file mode 100644 index 0000000000000..0a7e1bf34bd82 --- /dev/null +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013 David Herrmann + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef AMDKCL_DRM_VMA_MANAGER_H +#define AMDKCL_DRM_VMA_MANAGER_H + +/* We make up offsets for buffer objects so we can recognize them at + * mmap time. pgoff in mmap is an unsigned long, so we need to make sure + * that the faked up offset will fit + */ +#include +#include + +#if (BITS_PER_LONG == 64) +#ifdef DRM_FILE_PAGE_OFFSET_START +#undef DRM_FILE_PAGE_OFFSET_START +#endif +#ifdef DRM_FILE_PAGE_OFFSET_SIZE +#undef DRM_FILE_PAGE_OFFSET_SIZE +#endif + +#define DRM_FILE_PAGE_OFFSET_START ((0xFFFFFFFFULL >> PAGE_SHIFT) + 1) +#define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFULL >> PAGE_SHIFT) * 4096) + +static inline void +kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +{ + drm_vma_offset_manager_destroy(mgr); + drm_vma_offset_manager_init(mgr, + DRM_FILE_PAGE_OFFSET_START, + DRM_FILE_PAGE_OFFSET_SIZE); +} +#else +static inline void +kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +{ +} +#endif + +#endif From 36e2f5ce01889b7348c562f34cd9369fe87c8b5c Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 30 Aug 2019 15:30:41 +0800 Subject: [PATCH 0397/2070] drm/amdkcl: check whether DRM_FB_HELPER_DEFAULT_OPS is available DRM_FB_HELPER_DEFAULT_OPS introduced by kernel v4.9-rc1~41^2~3^2~2 - commit 74064893901ac5103cf101ecef5946e82b6ce9c6 - drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops v1: drm/amdkcl: Test whether fb_ops->fb_debug_{enter/leave}() is available v2: drm/amdkcl: add DRM_FB_HELPER_DEFAULT_OPS v3: drm/amdkcl: accommodate to drmP.h removal for fb-ops-fb-debug-xx.m4 v4: drm/amd/autoconf: fix a drm kcl compiling error in CentOS 7.3 v5: drm/amdkcl: drop test for fb_ops->fb_debug_xx Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Feifei Xu --- include/kcl/kcl_drm_fb.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 458e516f44af1..f4a9aa8c8216c 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -34,6 +34,25 @@ #include #include +/* + * Don't add fb_debug_* since the legacy drm_fb_helper_debug_* has segfault + * history: + * v2.6.35-21-gd219adc1228a fb: add hooks to handle KDB enter/exit + * v2.6.35-22-g1a7aba7f4e45 drm: add KGDB/KDB support + * v4.8-rc8-1391-g74064893901a drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops + * v4.9-rc4-808-g1e0089288b9b drm/fb-helper: add fb_debug_* to DRM_FB_HELPER_DEFAULT_OPS + * v4.9-rc4-807-g1b99b72489c6 drm/fb-helper: fix segfaults in drm_fb_helper_debug_* + * v4.10-rc8-1367-g0f3bbe074dd1 drm/fb-helper: implement ioctl FBIO_WAITFORVSYNC + */ +#ifndef DRM_FB_HELPER_DEFAULT_OPS +#define DRM_FB_HELPER_DEFAULT_OPS \ + .fb_check_var = drm_fb_helper_check_var, \ + .fb_set_par = drm_fb_helper_set_par, \ + .fb_setcmap = drm_fb_helper_setcmap, \ + .fb_blank = drm_fb_helper_blank, \ + .fb_pan_display = drm_fb_helper_pan_display +#endif + #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) #if !defined(IS_REACHABLE) /* Copied from include/linux/kconfig.h */ From 230aa64ad2b87529d3be9477c7aa4fc84a735836 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Aug 2020 16:57:05 +0800 Subject: [PATCH 0398/2070] drm/amdkcl: fake kcl copy of drm_atomic_helper_resume Signed-off-by: Flora Cui --- .../backport/kcl_drm_atomic_helper_backport.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index bcb45b685a034..1edfc203e12ce 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -4,6 +4,33 @@ #include +/* + * commit v4.14-rc4-1-g78279127253a + * drm/atomic: Unref duplicated drm_atomic_state in drm_atomic_helper_resume() + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) +static inline +int _kcl_drm_atomic_helper_resume(struct drm_device *dev, + struct drm_atomic_state *state) +{ + unsigned int prev, after; + int ret; + + prev = kref_read(&state->ref); + + drm_atomic_state_get(state); + ret = drm_atomic_helper_resume(dev, state); + + after = kref_read(&state->ref); + drm_atomic_state_put(state); + if (prev != after) + drm_atomic_state_put(state); + + return ret; +} +#define drm_atomic_helper_resume _kcl_drm_atomic_helper_resume +#endif + #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET #define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset #endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ From 709e2e810a6e561e325dfaf7231b403bb39744e0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Sep 2020 14:04:55 +0800 Subject: [PATCH 0399/2070] drm/amdkcl: test dma_buf_ops->allow_peer2peer introduced in commit v5.6-rc5-1663-g09606b5446c2 ("dma-buf: add peer2peer flag") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 656c267dbe587..141f2db9621e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -96,9 +96,11 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) attach->peer2peer = false; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; +#endif r = dma_resv_lock(bo->tbo.base.resv, NULL); if (r) @@ -194,11 +196,13 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; domains |= AMDGPU_GEM_DOMAIN_VRAM; } +#endif amdgpu_bo_placement_from_domain(bo, domains); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) @@ -533,7 +537,9 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, +#endif .move_notify = amdgpu_dma_buf_move_notify }; diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 new file mode 100644 index 0000000000000..f499b15204fa8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.6-rc5-1663-g09606b5446c2 +dnl # dma-buf: add peer2peer flag +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->allow_peer2peer = false; + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, + 1, + [struct dma_buf_ops->allow_peer2peer is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0a33708aaef42..041b4f4117c3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From e66d9452c2f0f9f69ce3c2f8829291cc6b4604b4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 17:10:16 +0800 Subject: [PATCH 0400/2070] drm/amdkcl: for dma_buf_ops->pin/unpin Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 20 ++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 141f2db9621e3..de64d1230c635 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -113,6 +113,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, return 0; } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation * @@ -167,6 +168,7 @@ static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach) amdgpu_bo_unpin(bo); } +#endif /** * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation @@ -191,6 +193,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct sg_table *sgt; long r; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (!bo->tbo.pin_count) { /* move buffer into GTT or VRAM */ struct ttm_operation_ctx ctx = { false, false }; @@ -208,6 +211,11 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, if (r) return ERR_PTR(r); } +#else + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + return ERR_PTR(r); +#endif switch (bo->tbo.resource->mem_type) { case TTM_PL_TT: @@ -283,6 +291,10 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, } else { amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt); } + +#ifndef HAVE_STRUCT_DMA_BUF_OPS_PIN + amdgpu_bo_unpin(bo); +#endif } /** @@ -358,8 +370,10 @@ static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map const struct dma_buf_ops amdgpu_dmabuf_ops = { .attach = amdgpu_dma_buf_attach, +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, .unpin = amdgpu_dma_buf_unpin, +#endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, .release = drm_gem_dmabuf_release, @@ -459,6 +473,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf) return ERR_PTR(ret); } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_move_notify - &attach.move_notify implementation * @@ -542,6 +557,7 @@ static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { #endif .move_notify = amdgpu_dma_buf_move_notify }; +#endif /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation @@ -575,8 +591,12 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, if (IS_ERR(obj)) return obj; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN attach = dma_buf_dynamic_attach(dma_buf, dev->dev, &amdgpu_dma_buf_attach_ops, obj); +#else + attach = dma_buf_dynamic_attach(dma_buf, dev->dev, true); +#endif if (IS_ERR(attach)) { drm_gem_object_put(obj); return ERR_CAST(attach); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 1fb9564006966..cd2904b19ae9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -964,8 +964,10 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) */ domain = amdgpu_bo_get_preferred_domain(adev, domain); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_pin(bo->tbo.base.import_attach); +#endif /* force to pin into visible video ram */ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) @@ -1272,9 +1274,11 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, amdgpu_bo_kunmap(abo); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (abo->tbo.base.dma_buf && !drm_gem_is_imported(&abo->tbo.base) && old_mem && old_mem->mem_type != TTM_PL_SYSTEM) dma_buf_move_notify(abo->tbo.base.dma_buf); +#endif /* move_notify is called before move happens */ trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index f499b15204fa8..dc74e703be9bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -13,6 +13,26 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_ops->allow_peer2peer is available]) + ],[ + dnl # + dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided + dnl # bd2275eeed5b dma-buf: drop dynamic_mapping flag + dnl # a448cb003edc drm/amdgpu: implement amdgpu_gem_prime_move_notify v2 + dnl # 2d4dad2734e2 drm/amdgpu: add amdgpu_dma_buf_pin/unpin v2 + dnl # 4993ba02635f drm/amdgpu: use allowed_domains for exported DMA-bufs + dnl # d2588d2ded0f drm/ttm: remove the backing store if no placement is given + dnl # bb42df4662a4 dma-buf: add dynamic DMA-buf handling v15 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->pin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) + ]) ]) ]) ]) From eacf80212447b4cde36dd038a8abd78f5c84751d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 4 Dec 2019 21:12:38 +0800 Subject: [PATCH 0401/2070] drm/amdkcl: Test whether drm_gem_object->resv is available It's a squash of b56463fa65e9 amd/amdkcl: drop BUILD_AS_DKMS compilation flag 65727463b0e9 drm/ttm,scheduler,amdgpu: properly define and initialize Makefile variables 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution de56d017a2d3 drm/amdkcl: Test whether drm_gem_object->resv is available drm/amdkcl: fix build error of amdkcl_ttm_resvp Signed-off-by: Leslie Shi Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Change-Id: Ibbd3ff2eb018141c783a2c6c0ebebac366f8ecc0 --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 10 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 | 23 ++++++++ drivers/gpu/drm/ttm/ttm_bo.c | 58 +++++++++---------- drivers/gpu/drm/ttm/ttm_bo_util.c | 16 ++--- drivers/gpu/drm/ttm/ttm_bo_vm.c | 20 +++---- drivers/gpu/drm/ttm/ttm_execbuf_util.c | 12 ++-- drivers/gpu/drm/ttm/ttm_resource.c | 4 +- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- include/drm/ttm/ttm_bo.h | 28 +++++++-- 24 files changed, 141 insertions(+), 101 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 6893d175f7c33..a570eeb21bccd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -380,7 +380,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, * table update and TLB flush here directly. */ replacement = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), ef->base.context, replacement, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(replacement); return 0; @@ -1374,7 +1374,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, vm_list_node) { struct amdgpu_bo *pd = peer_vm->root.bo; - ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, + ret = amdgpu_sync_resv(NULL, sync, amdkcl_ttm_resvp(&pd->tbo), AMDGPU_SYNC_NE_OWNER, AMDGPU_FENCE_OWNER_KFD); if (ret) @@ -1454,7 +1454,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, AMDGPU_FENCE_OWNER_KFD, false); if (ret) goto wait_pd_fail; - ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; dma_resv_add_fence(vm->root.bo->tbo.base.resv, @@ -2978,7 +2978,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * goto validate_map_fail; } } - dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, + dma_resv_for_each_fence(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, fence) { ret = amdgpu_sync_fence(&sync_obj, fence, GFP_KERNEL); if (ret) { @@ -3159,7 +3159,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem * Add process eviction fence to bo so they can * evict each other. */ - ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; dma_resv_add_fence(gws_bo->tbo.base.resv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index f3b5bcdbf2ae6..1017223692d86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -804,7 +804,7 @@ static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) struct ttm_operation_ctx ctx = { .interruptible = true, .no_wait_gpu = false, - .resv = bo->tbo.base.resv + .resv = amdkcl_ttm_resvp(&bo->tbo), }; uint32_t domain; int r; @@ -1225,7 +1225,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) drm_exec_for_each_locked_object(&p->exec, index, obj) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); enum amdgpu_sync_mode sync_mode; sync_mode = amdgpu_bo_explicit_sync(bo) ? @@ -1799,7 +1799,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, *map = mapping; /* Double check that the BO is reserved by this CS */ - if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket) + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&(*bo)->tbo)) != &parser->exec.ticket) return -EINVAL; /* Make sure VRAM is allocated contigiously */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 48b6f6077992d..956f23fbbe421 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -249,7 +249,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, goto unpin; } - r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, &work->shared_count, &work->shared); if (unlikely(r != 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index de64d1230c635..90a3b9f5ecd20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -509,7 +509,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5c90de58cc285..21208c3d123f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -141,7 +141,7 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) return ret; unlock: - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } @@ -447,7 +447,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, if (r) return r; - resv = vm->root.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); } initial_domain = (u32)(0xffffffff & args->in.domains); @@ -652,7 +652,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, return -ENOENT; robj = gem_to_amdgpu_bo(gobj); - ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(&robj->tbo), DMA_RESV_USAGE_READ, true, timeout); /* ret == 0 means not signaled, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 90d26d820bac0..1ec995c8384d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -78,7 +78,7 @@ static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni, mmu_interval_set_seq(mni, cur_seq); - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); mutex_unlock(&adev->notifier_lock); if (r <= 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index f69332eed0512..39d082f9eb44c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1596,7 +1596,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, amdgpu_vm_fini(adev, &fpriv->vm); if (pasid) - amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); + amdgpu_pasid_free_delayed(amdkcl_ttm_resvp(&pd->tbo), pasid); amdgpu_bo_unref(&pd); idr_for_each_entry(&fpriv->bo_list_handles, list, handle) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index cd2904b19ae9e..243e8610372bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -721,7 +721,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (unlikely(r)) goto fail_unreserve; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); } @@ -739,7 +739,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, fail_unreserve: if (!bp->resv) - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); amdgpu_bo_unref(&bo); return r; } @@ -823,7 +823,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) return -EPERM; - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, false, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; @@ -1154,7 +1154,7 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP); BUG_ON(bo->tbo.type == ttm_bo_type_kernel); - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); ubo = to_amdgpu_bo_user(bo); if (tiling_flags) @@ -1315,7 +1315,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) * So when this locking here fails something is wrong with the reference * counting. */ - if (WARN_ON_ONCE(!dma_resv_trylock(&bo->base._resv))) + if (WARN_ON_ONCE(!dma_resv_trylock(&amdkcl_ttm_resv(bo)))) return; amdgpu_amdkfd_remove_all_eviction_fences(abo); @@ -1325,7 +1325,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) goto out; - r = dma_resv_reserve_fences(&bo->base._resv, 1); + r = dma_resv_reserve_fences(&amdkcl_ttm_resv(bo), 1); if (r) goto out; @@ -1339,7 +1339,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) dma_fence_put(fence); out: - dma_resv_unlock(&bo->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(bo)); } /** @@ -1404,7 +1404,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared) { - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); int r; r = dma_resv_reserve_fences(resv, 1); @@ -1460,7 +1460,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, + return amdgpu_bo_sync_wait_resv(adev, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_NE_OWNER, owner, intr); } @@ -1477,7 +1477,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); - WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && + WARN_ON_ONCE(!dma_resv_is_locked(amdkcl_ttm_resvp(&bo->tbo)) && !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0977a10679dc8..c1e5457bd320d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -403,7 +403,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), - bo->base.resv, &fence); + amdkcl_ttm_resvp(bo), &fence); if (r) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 9d5cca7da1d9e..7ba95304eb7d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1172,7 +1172,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, goto err_free; } else { r = drm_sched_job_add_resv_dependencies(&job->base, - bo->tbo.base.resv, + amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index e548dc9708a22..4c4849b793905 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -328,7 +328,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 01fef0e4f4085..85c46779798a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1283,12 +1283,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, /* Implicitly sync to command submissions in the same VM before * unmapping. */ - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; if (bo) { - r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv); + r = amdgpu_sync_kfd(&sync, amdkcl_ttm_resvp(&bo->tbo)); if (r) goto error_free; } @@ -1561,7 +1561,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, * unmapping. */ amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; @@ -1633,7 +1633,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - resv = bo_va->base.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); spin_unlock(&vm->status_lock); /* Try to reserve the BO to avoid clearing its ptes */ @@ -2166,7 +2166,7 @@ void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) struct amdgpu_bo *bo; bo = mapping->bo_va->base.bo; - if (dma_resv_locking_ctx(bo->tbo.base.resv) != + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) continue; } @@ -2253,7 +2253,7 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo) return true; /* Don't evict VM page tables while they are busy */ - if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP)) + if (!dma_resv_test_signaled(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP)) return false; /* Try to block ongoing updates */ @@ -2646,7 +2646,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, } amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); - r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root_bo->tbo), 1); if (r) goto error_free_root; @@ -3206,7 +3206,7 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, */ bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) { - return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv; + return bo && amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo); } void amdgpu_vm_print_task_info(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 22e2e5b473415..e784f6311178a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -77,7 +77,7 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, uint64_t value; long r; - r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&vmbo->bo.tbo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index 31a437ce95704..105b46b4dc9ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -474,7 +474,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, bp.xcp_id_plus1 = xcp_id + 1; if (vm->root.bo) - bp.resv = vm->root.bo->tbo.base.resv; + bp.resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); return amdgpu_bo_create_vm(adev, &bp, vmbo); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index fcddb54a439f9..9fcfeca400339 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -628,7 +628,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, } } - r = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (r) { pr_debug("failed %d to reserve bo\n", r); amdgpu_bo_unreserve(bo); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 041b4f4117c3c..f0a5ced659bca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV + AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 new file mode 100644 index 0000000000000..6bf4a39e9679c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # v5.3-rc1-374-ge7f0141a217f drm/ttm: drop ttm_buffer_object->resv +dnl # v5.3-rc1-370-g5a5011a72489 drm/amdgpu: switch driver from bo->resv to bo->base.resv +dnl # v5.3-rc1-367-ge532a135d704 drm/ttm: switch ttm core from bo->resv to bo->base.resv +dnl # v5.3-rc1-365-gb96f3e7c8069 drm/ttm: use gem vma_node +dnl # v5.3-rc1-364-g1e053b10ba60 drm/ttm: use gem reservation object +dnl # v5.3-rc1-362-gc105de2828e1 drm/amdgpu: use embedded gem object +dnl # v5.3-rc1-358-g8eb8833e7ed3 drm/ttm: add gem base object +dnl # v5.0-rc1-1004-g1ba627148ef5 drm: Add reservation_object to drm_gem_object +dnl # +AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object *gem_obj = NULL; + gem_obj->resv = &gem_obj->_resv; + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, + [ttm_buffer_object->base is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index acb9197db8798..60d07b75e74ac 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -78,7 +78,7 @@ static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, */ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->resource) ttm_resource_move_to_lru_tail(bo->resource); @@ -102,7 +102,7 @@ EXPORT_SYMBOL(ttm_bo_move_to_lru_tail); void ttm_bo_set_bulk_move(struct ttm_buffer_object *bo, struct ttm_lru_bulk_move *bulk) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->bulk_move == bulk) return; @@ -150,7 +150,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, } } - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); if (ret) goto out_err; @@ -192,13 +192,13 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) { int r; - if (bo->base.resv == &bo->base._resv) + if (amdkcl_ttm_resvp(bo) == &amdkcl_ttm_resv(bo)) return 0; - BUG_ON(!dma_resv_trylock(&bo->base._resv)); + BUG_ON(!dma_resv_trylock(&amdkcl_ttm_resv(bo))); - r = dma_resv_copy_fences(&bo->base._resv, bo->base.resv); - dma_resv_unlock(&bo->base._resv); + r = dma_resv_copy_fences(&amdkcl_ttm_resv(bo), amdkcl_ttm_resvp(bo)); + dma_resv_unlock(&amdkcl_ttm_resv(bo)); if (r) return r; @@ -208,7 +208,7 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) * the resv object while holding the lru_lock. */ spin_lock(&bo->bdev->lru_lock); - bo->base.resv = &bo->base._resv; + amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); spin_unlock(&bo->bdev->lru_lock); } @@ -217,7 +217,7 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) static void ttm_bo_flush_all_fences(struct ttm_buffer_object *bo) { - struct dma_resv *resv = &bo->base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(bo); struct dma_resv_iter cursor; struct dma_fence *fence; @@ -239,11 +239,11 @@ static void ttm_bo_delayed_delete(struct work_struct *work) bo = container_of(work, typeof(*bo), delayed_delete); - dma_resv_wait_timeout(&bo->base._resv, DMA_RESV_USAGE_BOOKKEEP, false, + dma_resv_wait_timeout(&amdkcl_ttm_resv(bo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); - dma_resv_lock(bo->base.resv, NULL); + dma_resv_lock(amdkcl_ttm_resvp(bo), NULL); ttm_bo_cleanup_memtype_use(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); } @@ -263,7 +263,7 @@ static void ttm_bo_release(struct kref *kref) /* Last resort, if we fail to allocate memory for the * fences block for the BO to become idle */ - dma_resv_wait_timeout(bo->base.resv, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, 30 * HZ); } @@ -274,11 +274,11 @@ static void ttm_bo_release(struct kref *kref) drm_vma_offset_remove(bdev->vma_manager, &bo->base.vma_node); ttm_mem_io_free(bdev, bo->resource); - if (!dma_resv_test_signaled(&bo->base._resv, + if (!dma_resv_test_signaled(&amdkcl_ttm_resv(bo), DMA_RESV_USAGE_BOOKKEEP) || (want_init_on_free() && (bo->ttm != NULL)) || bo->type == ttm_bo_type_sg || - !dma_resv_trylock(bo->base.resv)) { + !dma_resv_trylock(amdkcl_ttm_resvp(bo))) { /* The BO is not idle, resurrect it for delayed destroy */ ttm_bo_flush_all_fences(bo); bo->deleted = true; @@ -313,7 +313,7 @@ static void ttm_bo_release(struct kref *kref) } ttm_bo_cleanup_memtype_use(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } atomic_dec(&ttm_glob.bo_count); @@ -366,7 +366,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, memset(&hop, 0, sizeof(hop)); - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); placement.num_placement = 0; bo->bdev->funcs->evict_flags(bo, &placement); @@ -479,7 +479,7 @@ int ttm_bo_evict_first(struct ttm_device *bdev, struct ttm_resource_manager *man ret = ttm_bo_evict(bo, ctx); } out_bo_moved: - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); out_no_lock: ttm_bo_put(bo); return ret; @@ -624,7 +624,7 @@ static int ttm_bo_evict_alloc(struct ttm_device *bdev, */ void ttm_bo_pin(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); WARN_ON_ONCE(!kref_read(&bo->kref)); spin_lock(&bo->bdev->lru_lock); if (bo->resource) @@ -643,7 +643,7 @@ EXPORT_SYMBOL(ttm_bo_pin); */ void ttm_bo_unpin(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); WARN_ON_ONCE(!kref_read(&bo->kref)); if (WARN_ON_ONCE(!bo->pin_count)) return; @@ -686,7 +686,7 @@ static int ttm_bo_add_pipelined_eviction_fences(struct ttm_buffer_object *bo, spin_unlock(&man->eviction_lock); /* TODO: this call should be removed. */ - return dma_resv_reserve_fences(bo->base.resv, 1); + return dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); } /** @@ -718,8 +718,8 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo, struct ww_acquire_ctx *ticket; int i, ret; - ticket = dma_resv_locking_ctx(bo->base.resv); - ret = dma_resv_reserve_fences(bo->base.resv, TTM_NUM_MOVE_FENCES); + ticket = dma_resv_locking_ctx(amdkcl_ttm_resvp(bo)); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), TTM_NUM_MOVE_FENCES); if (unlikely(ret)) return ret; @@ -825,7 +825,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, bool force_space; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); /* * Remove the backing store if no placement is given. @@ -944,9 +944,9 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, bo->sg = sg; bo->bulk_move = NULL; if (resv) - bo->base.resv = resv; + amdkcl_ttm_resvp(bo) = resv; else - bo->base.resv = &bo->base._resv; + amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); atomic_inc(&ttm_glob.bo_count); /* @@ -964,7 +964,7 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, * since otherwise lockdep will be angered in radeon. */ if (!resv) - WARN_ON(!dma_resv_trylock(bo->base.resv)); + WARN_ON(!dma_resv_trylock(amdkcl_ttm_resvp(bo))); else dma_resv_assert_held(resv); @@ -1074,14 +1074,14 @@ int ttm_bo_wait_ctx(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx) long ret; if (ctx->no_wait_gpu) { - if (dma_resv_test_signaled(bo->base.resv, + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)) return 0; else return -EBUSY; } - ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, ctx->interruptible, 15 * HZ); if (unlikely(ret < 0)) return ret; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index cabcfeaa70dc6..3abbe0d90d312 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -251,11 +251,11 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, fbo->base.destroy = &ttm_transfered_destroy; fbo->base.pin_count = 0; if (bo->type != ttm_bo_type_sg) - fbo->base.base.resv = &fbo->base.base._resv; + amdkcl_ttm_resvp(&fbo->base) = &amdkcl_ttm_resv(&fbo->base); - dma_resv_init(&fbo->base.base._resv); + dma_resv_init(&amdkcl_ttm_resv(&fbo->base)); fbo->base.base.dev = NULL; - ret = dma_resv_trylock(&fbo->base.base._resv); + ret = dma_resv_trylock(&amdkcl_ttm_resv(&fbo->base)); WARN_ON(!ret); ret = dma_resv_reserve_fences(&fbo->base.base._resv, TTM_NUM_MOVE_FENCES); @@ -617,7 +617,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object *bo, if (ret) return ret; - dma_resv_add_fence(&ghost_obj->base._resv, fence, + dma_resv_add_fence(&amdkcl_ttm_resv(ghost_obj), fence, DMA_RESV_USAGE_KERNEL); /** @@ -631,7 +631,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object *bo, else bo->ttm = NULL; - dma_resv_unlock(&ghost_obj->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(ghost_obj)); ttm_bo_put(ghost_obj); return 0; } @@ -708,7 +708,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, struct ttm_resource_manager *man = ttm_manager_type(bdev, new_mem->mem_type); int ret = 0; - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); if (!evict) ret = ttm_bo_move_to_ghost(bo, fence, man->use_tt); else if (!from->use_tt && pipeline) @@ -801,14 +801,14 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) if (ret) goto error_destroy_tt; - ret = dma_resv_copy_fences(&ghost->base._resv, bo->base.resv); + ret = dma_resv_copy_fences(&amdkcl_ttm_resv(ghost), amdkcl_ttm_resvp(bo)); /* Last resort, wait for the BO to be idle when we are OOM */ if (ret) { dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); } - dma_resv_unlock(&ghost->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(ghost)); ttm_bo_put(ghost); bo->ttm = ttm; return 0; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index a80510489c456..c3a30b37437bb 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -48,7 +48,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, /* * Quick non-stalling check for idle. */ - if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_KERNEL)) + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL)) return 0; /* @@ -62,10 +62,10 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, drm_gem_object_get(&bo->base); mmap_read_unlock(vmf->vma->vm_mm); - (void)dma_resv_wait_timeout(bo->base.resv, + (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); drm_gem_object_put(&bo->base); return VM_FAULT_RETRY; } @@ -73,7 +73,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, /* * Ordinary wait. */ - err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, true, + err = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (unlikely(err < 0)) { return (err != -ERESTARTSYS) ? VM_FAULT_SIGBUS : @@ -124,7 +124,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, * for reserve, and if it fails, retry the fault after waiting * for the buffer to become unreserved. */ - if (unlikely(!dma_resv_trylock(bo->base.resv))) { + if (unlikely(!dma_resv_trylock(amdkcl_ttm_resvp(bo)))) { /* * If the fault allows retry and this is the first * fault attempt, we try to release the mmap_lock @@ -134,16 +134,16 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { drm_gem_object_get(&bo->base); mmap_read_unlock(vmf->vma->vm_mm); - if (!dma_resv_lock_interruptible(bo->base.resv, + if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); drm_gem_object_put(&bo->base); } return VM_FAULT_RETRY; } - if (dma_resv_lock_interruptible(bo->base.resv, NULL)) + if (dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) return VM_FAULT_NOPAGE; } @@ -153,7 +153,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, */ if (bo->ttm && (bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL)) { if (!(bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL_MAPPABLE)) { - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return VM_FAULT_SIGBUS; } } @@ -340,7 +340,7 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c index bc7a83a9fe443..2fe50abde4b3e 100644 --- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c +++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c @@ -37,7 +37,7 @@ static void ttm_eu_backoff_reservation_reverse(struct list_head *list, list_for_each_entry_continue_reverse(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } } @@ -53,7 +53,7 @@ void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket, struct ttm_buffer_object *bo = entry->bo; ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } if (ticket) @@ -101,7 +101,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, num_fences = max(entry->num_shared, 1u); if (!ret) { - ret = dma_resv_reserve_fences(bo->base.resv, + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), num_fences); if (!ret) continue; @@ -118,7 +118,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, } if (!ret) - ret = dma_resv_reserve_fences(bo->base.resv, + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), num_fences); if (unlikely(ret != 0)) { @@ -152,10 +152,10 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket, list_for_each_entry(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - dma_resv_add_fence(bo->base.resv, fence, entry->num_shared ? + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, entry->num_shared ? DMA_RESV_USAGE_READ : DMA_RESV_USAGE_WRITE); ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } if (ticket) ww_acquire_fini(ticket); diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 192fca24f37e4..ea623aa273321 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -168,8 +168,8 @@ void ttm_lru_bulk_move_tail(struct ttm_lru_bulk_move *bulk) continue; lockdep_assert_held(&pos->first->bo->bdev->lru_lock); - dma_resv_assert_held(pos->first->bo->base.resv); - dma_resv_assert_held(pos->last->bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(pos->first->bo)); + dma_resv_assert_held(amdkcl_ttm_resvp(pos->last->bo)); man = ttm_manager_type(pos->first->bo->bdev, i); list_bulk_move_tail(&man->lru[j], &pos->first->lru.link, diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 026a57874826c..b523f50f73e94 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -73,7 +73,7 @@ int ttm_tt_create(struct ttm_buffer_object *bo, bool zero_alloc) struct drm_device *ddev = bo->base.dev; uint32_t page_flags = 0; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->ttm) return 0; diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index bca3a8849d47d..20ae857eb7a3a 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -37,6 +37,9 @@ #include #include "ttm_device.h" +#ifndef HAVE_CONFIG_H +#define HAVE_DRM_GEM_OBJECT_RESV 1 +#endif /* Default number of pre-faulted pages in the TTM fault handler */ #define TTM_BO_VM_NUM_PREFAULT 16 @@ -135,6 +138,11 @@ struct ttm_buffer_object { * reservation lock. */ struct sg_table *sg; + +#if !defined(HAVE_DRM_GEM_OBJECT_RESV) + struct dma_resv *resv; + struct dma_resv ttm_resv; +#endif }; #define TTM_BO_MAP_IOMEM_MASK 0x80 @@ -252,6 +260,14 @@ bool ttm_bo_shrink_suitable(struct ttm_buffer_object *bo, struct ttm_operation_c bool ttm_bo_shrink_avoid_wait(void); +#if defined(HAVE_DRM_GEM_OBJECT_RESV) +#define amdkcl_ttm_resv(bo) ((bo)->base._resv) +#define amdkcl_ttm_resvp(bo) ((bo)->base.resv) +#else +#define amdkcl_ttm_resv(bo) ((bo)->ttm_resv) +#define amdkcl_ttm_resvp(bo) ((bo)->resv) +#endif + /** * ttm_bo_reserve: * @@ -286,14 +302,14 @@ static inline int ttm_bo_reserve(struct ttm_buffer_object *bo, if (WARN_ON(ticket)) return -EBUSY; - success = dma_resv_trylock(bo->base.resv); + success = dma_resv_trylock(amdkcl_ttm_resvp(bo)); return success ? 0 : -EBUSY; } if (interruptible) - ret = dma_resv_lock_interruptible(bo->base.resv, ticket); + ret = dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), ticket); else - ret = dma_resv_lock(bo->base.resv, ticket); + ret = dma_resv_lock(amdkcl_ttm_resvp(bo), ticket); if (ret == -EINTR) return -ERESTARTSYS; return ret; @@ -314,13 +330,13 @@ static inline int ttm_bo_reserve_slowpath(struct ttm_buffer_object *bo, struct ww_acquire_ctx *ticket) { if (interruptible) { - int ret = dma_resv_lock_slow_interruptible(bo->base.resv, + int ret = dma_resv_lock_slow_interruptible(amdkcl_ttm_resvp(bo), ticket); if (ret == -EINTR) ret = -ERESTARTSYS; return ret; } - dma_resv_lock_slow(bo->base.resv, ticket); + dma_resv_lock_slow(amdkcl_ttm_resvp(bo), ticket); return 0; } @@ -365,7 +381,7 @@ static inline void ttm_bo_move_null(struct ttm_buffer_object *bo, static inline void ttm_bo_unreserve(struct ttm_buffer_object *bo) { ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } /** From 1ad436182d9b07216ba1f656f9431de7da9ce7b2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 17 Apr 2020 11:36:17 +0800 Subject: [PATCH 0402/2070] drm/amdkcl: Test whether dma-buf dynamic locking is available It's a squash of 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution 57da2736175c drm/amdkcl: Test whether drm_gem_map_attach() wants 2 args a881ad26f08d drm/amdkcl: Test whether dma-buf dynamic locking is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Adam Yang Reviewed-by: Flora Cui Reviewed-by: Rui Teng Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 254 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 9 + drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 16 ++ .../gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 | 14 + 4 files changed, 293 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 90a3b9f5ecd20..479ffe2d24f3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -44,6 +44,146 @@ #include #include +static int +__dma_resv_make_exclusive(struct dma_resv *obj) +{ + struct dma_fence **fences; + unsigned int count; + int r; + + if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ + return 0; + + r = dma_resv_get_fences(obj, NULL, &count, &fences); + if (r) + return r; + + if (count == 0) { + /* Now that was unexpected. */ + } else if (count == 1) { + dma_resv_add_excl_fence(obj, fences[0]); + dma_fence_put(fences[0]); + kfree(fences); + } else { + struct dma_fence_array *array; + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), 0, + false); + if (!array) + goto err_fences_put; + + dma_resv_add_excl_fence(obj, &array->base); + dma_fence_put(&array->base); + } + + return 0; + +err_fences_put: + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; +} + +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * Makes sure that the shared DMA buffer can be accessed by the target device. + * For now, simply pins it to the GTT domain, where it should be accessible by + * all DMA devices. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, +#ifndef HAVE_DRM_GEM_MAP_ATTACH_2ARGS + struct device *target_dev, +#endif + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + long r; + +#ifdef HAVE_DRM_GEM_MAP_ATTACH_2ARGS + r = drm_gem_map_attach(dma_buf, attach); +#else + r = drm_gem_map_attach(dma_buf, target_dev, attach); +#endif + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + goto error_detach; + + + if (attach->dev->driver != adev->dev->driver) { + /* + * We only create shared fences for internal use, but importers + * of the dmabuf rely on exclusive fences for implicitly + * tracking write hazards. As any of the current fences may + * correspond to a write, we need to convert all existing + * fences on the reservation object into a single exclusive + * fence. + */ + r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); + if (r) + goto error_unreserve; + } + + /* pin buffer into GTT */ + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + goto error_unreserve; + + if (attach->dev->driver != adev->dev->driver) + bo->prime_shared_count++; + +error_unreserve: + amdgpu_bo_unreserve(bo); + +error_detach: + if (r) + drm_gem_map_detach(dma_buf, attach); + return r; +} + +/** + * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * This is called when a shared DMA buffer no longer needs to be accessible by + * another device. For now, simply unpins the buffer from GTT. + */ +static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + goto error; + + amdgpu_bo_unpin(bo); + if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) + bo->prime_shared_count--; + amdgpu_bo_unreserve(bo); + +error: + drm_gem_map_detach(dma_buf, attach); +} +#else static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops; /** @@ -296,6 +436,7 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, amdgpu_bo_unpin(bo); #endif } +#endif /** * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation @@ -369,6 +510,16 @@ static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map } const struct dma_buf_ops amdgpu_dmabuf_ops = { +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) + .attach = amdgpu_dma_buf_map_attach, + .detach = amdgpu_dma_buf_map_detach, + .map_dma_buf = drm_gem_map_dma_buf, + .unmap_dma_buf = drm_gem_unmap_dma_buf, +#else +#ifdef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING + .dynamic_mapping = true, +#endif .attach = amdgpu_dma_buf_attach, #ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, @@ -376,6 +527,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { #endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, +#endif .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, @@ -422,6 +574,107 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return buf; } +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table + * implementation + * @obj: GEM buffer object (BO) + * + * Returns: + * A scatter/gather table for the pinned pages of the BO's memory. + */ +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int npages = bo->tbo.ttm->num_pages; + + return drm_prime_pages_to_sg(obj->dev, bo->tbo.ttm->pages, npages); +} + +/** + * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table + * implementation + * @dev: DRM device + * @attach: DMA-buf attachment + * @sg: Scatter/gather table + * + * Imports shared DMA buffer memory exported by another device. + * + * Returns: + * A new GEM BO of the given DRM device, representing the memory + * described by the given DMA-buf attachment and scatter/gather table. + */ +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg) +{ + struct dma_resv *resv = attach->dmabuf->resv; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_bo *bo; + struct amdgpu_bo_param bp; + int ret; + + memset(&bp, 0, sizeof(bp)); + bp.size = attach->dmabuf->size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_CPU; + bp.flags = 0; + bp.type = ttm_bo_type_sg; + bp.resv = resv; + dma_resv_lock(resv, NULL); + ret = amdgpu_bo_create(adev, &bp, &bo); + if (ret) + goto error; + + bo->tbo.sg = sg; + bo->tbo.ttm->sg = sg; + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->prime_shared_count = 1; + + dma_resv_unlock(resv); + return &bo->tbo.base; + +error: + dma_resv_unlock(resv); + return ERR_PTR(ret); +} + +/** + * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation + * @dev: DRM device + * @dma_buf: Shared DMA buffer + * + * The main work is done by the &drm_gem_prime_import helper, which in turn + * uses &amdgpu_gem_prime_import_sg_table. + * + * Returns: + * GEM BO representing the shared DMA buffer for the given device. + */ +struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, + struct dma_buf *dma_buf) +{ + struct drm_gem_object *obj; + + if (dma_buf->ops == &amdgpu_dmabuf_ops) { + obj = dma_buf->priv; + if (obj->dev == dev) { + /* + * Importing dmabuf exported from out own gem increases + * refcount on gem itself instead of f_count of dmabuf. + */ + drm_gem_object_get(obj); + return obj; + } + } + + return drm_gem_prime_import(dev, dma_buf); +} + +#else + /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -606,6 +859,7 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, obj->import_attach = attach; return obj; } +#endif /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index 3e93b9b407a97..dd7c8ffa41cf4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -25,6 +25,15 @@ #include +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg); +#endif + struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, int flags); struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index dc74e703be9bd..3f408896f437b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -32,6 +32,22 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, 1, [struct dma_buf_ops->pin() is available]) + ], [ + dnl # + dnl # commit v5.4-rc4-863-g15fd552d186c + dnl # dma-buf: change DMA-buf locking convention v3 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_buf_ops *dma_buf_ops = NULL; + dma_buf_ops->dynamic_mapping = true; + ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, + [dma_buf dynamic_mapping is available]) + ],[ + AC_AMDGPU_DRM_GEM_MAP_ATTACH + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 new file mode 100644 index 0000000000000..031d62f21740f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit v4.17-rc3-491-ga19741e5e5a9 +dnl # dma_buf: remove device parameter from attach callback v2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_MAP_ATTACH], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_gem_map_attach(NULL, NULL); + ], [drm_gem_map_attach], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_MAP_ATTACH_2ARGS, 1, + [drm_gem_map_attach() wants 2 arguments]) + ]) +]) From 9ea8675645ce8a352eeb257a823af5ce34df273e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 9 Dec 2019 14:15:16 +0800 Subject: [PATCH 0403/2070] drm/amdkcl: Test whether drm_drv->gem_prime_res_obj() is available It's a squash of 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution 22887005a0ef drm/amdkcl: Test whether drm_drv->gem_prime_res_obj() is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Change-Id: I60c3bf6ef7409f636ecb9912cda0b35967e170ad --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 +++++++ drivers/gpu/drm/amd/backport/backport.h | 3 +++ .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 479ffe2d24f3c..56abdf2e0a758 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -574,6 +574,22 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return buf; } +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +/** + * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation + * @obj: GEM BO + * + * Returns: + * The BO's reservation object. + */ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + return amdkcl_ttm_resvp(&bo->tbo); +} +#endif + #if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1e39e1d4138c3..2c114acb9d313 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3091,6 +3091,14 @@ static const struct drm_driver amdgpu_kms_driver = { #endif .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ + .gem_prime_res_obj = amdgpu_gem_prime_res_obj, +#endif +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) + .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, + .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index fa3328db34b52..e22dfaeaff262 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -29,6 +29,9 @@ #include #include #include +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +#include +#endif #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 new file mode 100644 index 0000000000000..cf63fed2c4727 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit v5.3-rc1-325-g51c98747113e +dnl # drm/amdgpu: Fill out gem_object->resv +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #else + #include + #endif + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_res_obj(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ, 1, + [drm_driver->gem_prime_res_obj() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f0a5ced659bca..a93bd4ad2e469 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -45,6 +45,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From 900a983bacdf10708204d6417c8b3ee255cbe8fc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 13:03:11 +0800 Subject: [PATCH 0404/2070] drm/amdkcl: add AMDKCL_AMDGPU_DMABUF_OPS v2:missing gem_prime_pin pointer Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 63 +++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 8 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_drm_backport.h | 9 +++ 7 files changed, 90 insertions(+), 4 deletions(-) create mode 100644 include/kcl/backport/kcl_drm_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0f6e9cdbe7d84..5dc8d614e48c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -383,6 +383,10 @@ struct amdgpu_clock { uint32_t max_pixel_clock; }; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) +extern const struct dma_buf_ops amdgpu_dmabuf_ops; +#endif + /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 3bfd79c89df32..2f77a932abdfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -547,9 +547,11 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, if (IS_ERR(dma_buf)) return PTR_ERR(dma_buf); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* Can't handle non-graphics buffers */ goto out_put; +#endif obj = dma_buf->priv; if (obj->dev->driver != adev_to_drm(adev)->driver) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 56abdf2e0a758..c7fffa1562890 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -44,6 +44,7 @@ #include #include +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -534,6 +535,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .vmap = amdgpu_dma_buf_vmap, .vunmap = amdgpu_dma_buf_vunmap, }; +#endif /** * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation @@ -568,8 +570,10 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return ERR_PTR(ret); buf = drm_gem_prime_export(gobj, flags); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; +#endif return buf; } @@ -648,7 +652,10 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bo->tbo.ttm->sg = sg; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; - bo->prime_shared_count = 1; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) + if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) +#endif + bo->prime_shared_count = 1; dma_resv_unlock(resv); return &bo->tbo.base; @@ -658,6 +665,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, return ERR_PTR(ret); } +#ifdef AMDKCL_AMDGPU_DMABUF_OPS /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -688,9 +696,8 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, return drm_gem_prime_import(dev, dma_buf); } - +#endif #else - /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -827,7 +834,6 @@ static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { .move_notify = amdgpu_dma_buf_move_notify }; #endif - /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -877,6 +883,53 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, } #endif +#ifndef AMDKCL_AMDGPU_DMABUF_OPS +int amdgpu_gem_prime_pin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + long ret = 0; + + ret = amdgpu_bo_reserve(bo, false); + if (unlikely(ret != 0)) + return ret; + + /* + * Wait for all shared fences to complete before we switch to future + * use of exclusive fence on this prime shared bo. + */ + ret = dma_resv_wait_timeout_rcu(bo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT); + if (unlikely(ret < 0)) { + DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); + amdgpu_bo_unreserve(bo); + return ret; + } + + /* pin buffer into GTT */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (likely(ret == 0)) + bo->prime_shared_count++; + + amdgpu_bo_unreserve(bo); + return ret; +} + +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + return; + + amdgpu_bo_unpin(bo); + if (bo->prime_shared_count) + bo->prime_shared_count--; + amdgpu_bo_unreserve(bo); +} +#endif + /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer * @@ -898,9 +951,11 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, if (drm_gem_is_imported(obj)) { struct dma_buf *dma_buf = obj->import_attach->dmabuf; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* No XGMI with non AMD GPUs */ return false; +#endif gobj = dma_buf->priv; bo = gem_to_amdgpu_bo(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index dd7c8ffa41cf4..db75327913c95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -36,10 +36,18 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, int flags); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); +#else +int amdgpu_gem_prime_pin(struct drm_gem_object *obj); +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); +#endif bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); +#endif extern const struct dma_buf_ops amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 2c114acb9d313..1d42ccb2664e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3090,7 +3090,13 @@ static const struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, +#else + .gem_prime_import = drm_gem_prime_import, + .gem_prime_pin = amdgpu_gem_prime_pin, + .gem_prime_unpin = amdgpu_gem_prime_unpin, +#endif #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif @@ -3100,6 +3106,7 @@ static const struct drm_driver amdgpu_kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, .major = KMS_DRIVER_MAJOR, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e22dfaeaff262..4094df27db833 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h new file mode 100644 index 0000000000000..1450036960b9c --- /dev/null +++ b/include/kcl/backport/kcl_drm_backport.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_BACKPORT_H +#define AMDKCL_DRM_BACKPORT_H + +#if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) +#define AMDKCL_AMDGPU_DMABUF_OPS +#endif + +#endif/*AMDKCL_DRM_BACKPORT_H*/ From cccc1f0ac3ffbae1fc2ad37b01e6d528cf9f4b4d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 10 Oct 2015 17:11:12 +0800 Subject: [PATCH 0405/2070] drm/amdgpu: [hybrid] add query for aperture va range Signed-off-by: Flora Cui Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 +++++++++++++ include/uapi/drm/amdgpu_drm.h | 35 +++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 39d082f9eb44c..dfb1d02f33104 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -671,6 +671,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; switch (info->query) { + case AMDGPU_INFO_VIRTUAL_RANGE: { + struct drm_amdgpu_virtual_range range_info; + + switch (info->virtual_range.aperture) { + case AMDGPU_SUA_APERTURE_PRIVATE: + range_info.start = adev->gmc.private_aperture_start; + range_info.end = adev->gmc.private_aperture_end; + break; + case AMDGPU_SUA_APERTURE_SHARED: + range_info.start = adev->gmc.shared_aperture_start; + range_info.end = adev->gmc.shared_aperture_end; + break; + default: + return -EINVAL; + } + return copy_to_user(out, &range_info, + min((size_t)size, sizeof(range_info))) ? -EFAULT : 0; + } case AMDGPU_INFO_ACCEL_WORKING: ui32 = adev->accel_working; return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 6d9c078d7a7e1..39780844a0264 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1270,6 +1270,12 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { /* query FW object size and alignment */ #define AMDGPU_INFO_UQ_FW_AREAS 0x24 +/* Hybrid Stack Specific Defs*/ +/* gpu capability */ +#define AMDGPU_INFO_CAPABILITY 0x50 +/* virtual range */ +#define AMDGPU_INFO_VIRTUAL_RANGE 0x51 + #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 @@ -1326,6 +1332,11 @@ struct drm_amdgpu_info { __u32 flags; } read_mmr_reg; + struct { + uint32_t aperture; + uint32_t _pad; + } virtual_range; + struct drm_amdgpu_query_fw query_fw; struct { @@ -1670,6 +1681,30 @@ struct drm_amdgpu_info_uq_metadata { #define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */ #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ +/** + * Definition of System Unified Address (SUA) apertures + */ +#define AMDGPU_SUA_APERTURE_PRIVATE 1 +#define AMDGPU_SUA_APERTURE_SHARED 2 +struct drm_amdgpu_virtual_range { + uint64_t start; + uint64_t end; +}; + + +/* + * Definition of free sync enter and exit signals + * We may have more options in the future + */ +#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 +#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 + +struct drm_amdgpu_freesync { + __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ + /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ + __u32 spare[7]; +}; + #if defined(__cplusplus) } #endif From 9c20b6dc9374cba0d1b4e32e58badd21099aef4e Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Thu, 14 Sep 2017 15:53:13 +0800 Subject: [PATCH 0406/2070] drm/amdgpu: [hybrid] add AMDGPU VERSION Signed-off-by: Le.Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1d42ccb2664e4..d804eef125dae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -132,6 +132,7 @@ #define KMS_DRIVER_MINOR 64 #define KMS_DRIVER_PATCHLEVEL 0 +#define AMDGPU_VERSION "19.10.9.418" /* * amdgpu.debug module options. Are all disabled by default */ @@ -3174,6 +3175,9 @@ static int __init amdgpu_init(void) if (r) goto error_fence; + DRM_INFO("amdgpu version: %s\n", AMDGPU_VERSION); + DRM_INFO("OS DRM version: %d.%d.%d\n", DRM_VER, DRM_PATCH, DRM_SUB); + amdgpu_register_atpx_handler(); amdgpu_acpi_detect(); @@ -3214,3 +3218,4 @@ module_exit(amdgpu_exit); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); +MODULE_VERSION(AMDGPU_VERSION); From 9bb1b132e13be66186165316b815dcf5f4aa1d37 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 29 Apr 2021 18:05:44 +0800 Subject: [PATCH 0407/2070] drm/amdgpu: [hybrid] use DEFINE_SHOW_ATTRIBUTE to create amdgpu_gpu_recover node This will get rid of the limitation of DEFINE_DEBUGFS_ATTRIBUTE on old distros, otherwise amdgpu_gpu_recover is not exposed. Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d209591e3710a..6b14cbf8452fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -910,9 +910,9 @@ static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused) * * Manually trigger a gpu reset at the next fence wait. */ -static int gpu_recover_get(void *data, u64 *val) +static int amdgpu_debugfs_gpu_recover_show(struct seq_file *m, void *unused) { - struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); int r; @@ -925,7 +925,7 @@ static int gpu_recover_get(void *data, u64 *val) if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work)) flush_work(&adev->reset_work); - *val = atomic_read(&adev->reset_domain->reset_res); + // *val = atomic_read(&adev->reset_domain->reset_res); pm_runtime_put_autosuspend(dev->dev); @@ -933,8 +933,7 @@ static int gpu_recover_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); -DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, - "%lld\n"); +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gpu_recover); static void amdgpu_debugfs_reset_work(struct work_struct *work) { From 3c50941eea7fc1e9c6dd8e01ed6ffba7eea3c5e4 Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Mon, 9 Nov 2015 13:39:37 +0800 Subject: [PATCH 0408/2070] drm/amdgpu: [hybrid] expose the pinning capability to user space The module option amdgpu.no_evict is added, and it is disabled by default now. Signed-off-by: Jammy Zhou Reviewed-by: Chunming Zhou Signed-off-by: Junwei Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++++++++ include/uapi/drm/amdgpu_drm.h | 4 ++++ 5 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5dc8d614e48c7..72ecb5d4cf009 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -186,6 +186,7 @@ extern int amdgpu_exp_hw_support; extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; +extern int amdgpu_no_evict; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index d804eef125dae..ab05c02cabb54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -177,6 +177,7 @@ int amdgpu_exp_hw_support; int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; +int amdgpu_no_evict; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -499,6 +500,8 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); /** * DOC: forcelongtraining (uint) * Force long memory training in resume. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index b558336bc4c6c..cd073b3a316da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -82,6 +82,7 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE | \ AMDGPU_GEM_CREATE_ENCRYPTED | \ AMDGPU_GEM_CREATE_GFX12_DCC | \ + AMDGPU_GEM_CREATE_GFX12_DCC | \ AMDGPU_GEM_CREATE_DISCARDABLE | \ AMDGPU_GEM_CREATE_COHERENT | \ AMDGPU_GEM_CREATE_UNCACHED | \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 243e8610372bb..f3ab20a9d243f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -735,6 +735,14 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + if ((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) { + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(bo, bp->domain); + amdgpu_bo_unreserve(bo); + } + return 0; fail_unreserve: diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 39780844a0264..1bdcc432e09c7 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -182,6 +182,10 @@ extern "C" { /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) +/* hybrid specific */ +/* Flag that the memory allocation should be pinned */ +#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + struct drm_amdgpu_gem_create_in { /** the requested memory size */ __u64 bo_size; From 5eb3f6d13dad99bd42f71632e0ae6f6bdd95869b Mon Sep 17 00:00:00 2001 From: jimqu Date: Mon, 16 Nov 2015 14:03:15 +0800 Subject: [PATCH 0409/2070] drm/amdgpu: [hybrid] add query amdgpu capability function with this function, it could return capability to user space driver. Change-Id: Icad47e8d0621f9e8b8b9baedb751c11ded6c9449 Signed-off-by: JimQu Reviewed-by: Chunming Zhou Reviewed-by: Jammy Zhou Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++ include/uapi/drm/amdgpu_drm.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index dfb1d02f33104..0a79586e6ce21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1186,6 +1186,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; } } + case AMDGPU_INFO_CAPABILITY: { + struct drm_amdgpu_capability cap; + + memset(&cap, 0, sizeof(cap)); + if (amdgpu_no_evict) + cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + return copy_to_user(out, &cap, + min((size_t)size, sizeof(cap))) ? -EFAULT : 0; + } case AMDGPU_INFO_SENSOR: { if (!adev->pm.dpm_enabled) return -ENOENT; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 1bdcc432e09c7..f83bc9013b623 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1279,6 +1279,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_CAPABILITY 0x50 /* virtual range */ #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 +/* query pin memory capability */ +#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1695,6 +1697,9 @@ struct drm_amdgpu_virtual_range { uint64_t end; }; +struct drm_amdgpu_capability { + __u32 flag; +}; /* * Definition of free sync enter and exit signals From 278bd5a8988bb7b2f4bdd103c5044fef31c944e6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 1 Sep 2016 12:33:01 +0800 Subject: [PATCH 0410/2070] drm/amdgpu: [hybrid] add AMDGPU_GEM_CREATE_TOP_DOWN flag so that the buffer could be allocated from the top of domain Change-Id: I7dc4ba02b78b18330c7fe00841970ab9cccbded5 Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 ++++- include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f3ab20a9d243f..f989f89000f5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -113,7 +113,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) struct ttm_placement *placement = &abo->placement; struct ttm_place *places = abo->placements; u64 flags = abo->flags; - u32 c = 0; + u32 c = 0, i; if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; @@ -212,6 +212,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); + for (i = 0; i < c; i++) + if (flags & AMDGPU_GEM_CREATE_TOP_DOWN) + places[i].flags |= TTM_PL_FLAG_TOPDOWN; placement->num_placement = c; placement->placement = places; } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index f83bc9013b623..7dbcc131176c7 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -183,6 +183,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) /* hybrid specific */ +/* Flag that the memory allocation should be from top of domain */ +#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) From 785a90db3567b746f9792b70aa912b0796757934 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 23 Apr 2021 16:38:13 +0800 Subject: [PATCH 0411/2070] drm/amdgpu: [hybrid] unpin bo per exit Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 21208c3d123f5..a44c17f66cf1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -156,6 +156,13 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); + if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { + if (!amdgpu_bo_reserve(aobj, false)) { + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); + } + } + amdgpu_hmm_unregister(aobj); ttm_bo_fini(&aobj->tbo); } From 0d3f96208ac9de35b816b636bfd4ea1031f77be5 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Thu, 30 Aug 2018 12:14:28 +0800 Subject: [PATCH 0412/2070] drm/amdgpu: [hybrid] add semaphore object support Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 462 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 64 ++++ include/uapi/drm/amdgpu_drm.h | 37 ++ 11 files changed, 589 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 7d5a4565831c8..e7e9871fef1ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -61,7 +61,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \ amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \ amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o amdgpu_hdp.o \ - amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ + amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_sem.o amdgpu_gmc.o \ amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ amdgpu_fw_attestation.o amdgpu_securedisplay.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 72ecb5d4cf009..0200111e3e310 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -68,6 +68,7 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" +#include "amdgpu_sem.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "amdgpu_uvd.h" @@ -451,6 +452,8 @@ struct amdgpu_fpriv { struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; struct amdgpu_userq_mgr userq_mgr; + spinlock_t sem_handles_lock; + struct idr sem_handles; /* Eviction fence infra */ struct amdgpu_eviction_fence_mgr evf_mgr; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 1017223692d86..3fafa90b4f585 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -41,6 +41,7 @@ #include "amdgpu_gem.h" #include "amdgpu_ras.h" #include "amdgpu_hmm.h" +#include "amdgpu_display.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, @@ -610,7 +611,7 @@ static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) { unsigned int ce_preempt = 0, de_preempt = 0; - int i, r; + int i, r = 0; for (i = 0; i < p->nchunks; ++i) { struct amdgpu_cs_chunk *chunk; @@ -657,7 +658,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } - return 0; + return amdgpu_sem_add_cs(p->ctx, p->entity, &p->job->sync); } /* Convert microseconds to bytes. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index b19e96d4c183b..9989a7ff56fc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -216,6 +216,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, GFP_KERNEL); if (!entity) return -ENOMEM; + INIT_LIST_HEAD(&entity->sem_dep_list); + mutex_init(&entity->sem_lock); ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? ctx->init_priority : ctx->override_priority; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index cf8d700a22fe8..e5eafa228388a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -39,6 +39,8 @@ struct amdgpu_ctx_entity { uint32_t hw_ip; uint64_t sequence; struct drm_sched_entity entity; + struct list_head sem_dep_list; + struct mutex sem_lock; struct dma_fence *fences[]; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ab05c02cabb54..174a56fbac4bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3073,6 +3073,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; static const struct drm_driver amdgpu_kms_driver = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index f1ed4a436f5b4..3099379af0b29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -142,6 +142,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, unsigned int cond_exec; unsigned int i; int r = 0; + unsigned extra_nop = 0; if (num_ibs == 0) return -EINVAL; @@ -197,6 +198,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, alloc_size = ring->funcs->emit_frame_size + num_ibs * ring->funcs->emit_ib_size; + if (job && !job->vm_needs_flush && ring->funcs->type == AMDGPU_RING_TYPE_GFX) { + extra_nop = 128; + alloc_size += extra_nop; + } + r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); @@ -217,6 +223,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, } if (job) { + amdgpu_ring_insert_nop(ring, extra_nop); /* prevent CE go too fast than DE */ vm_af = job->hw_vm_fence; /* VM sequence */ vm_af->ib_wptr = ring->wptr; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 0a79586e6ce21..982a489ef8bef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1542,6 +1542,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) mutex_init(&fpriv->bo_list_lock); idr_init_base(&fpriv->bo_list_handles, 1); + spin_lock_init(&fpriv->sem_handles_lock); + idr_init(&fpriv->sem_handles); r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); if (r) @@ -1588,6 +1590,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_bo_list *list; + struct amdgpu_sem *sem; struct amdgpu_bo *pd; u32 pasid; int handle; @@ -1632,6 +1635,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, idr_destroy(&fpriv->bo_list_handles); mutex_destroy(&fpriv->bo_list_lock); + idr_for_each_entry(&fpriv->sem_handles, sem, handle) + amdgpu_sem_destroy(fpriv, handle); + idr_destroy(&fpriv->sem_handles); + kfree(fpriv); file_priv->driver_priv = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c new file mode 100644 index 0000000000000..432072b28f5ae --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -0,0 +1,462 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chunming Zhou + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_sem.h" + +#define to_amdgpu_ctx_entity(e) \ + container_of((e), struct amdgpu_ctx_entity, entity) + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem); + +static void amdgpu_sem_core_free(struct kref *kref) +{ + struct amdgpu_sem_core *core = container_of( + kref, struct amdgpu_sem_core, kref); + + dma_fence_put(core->fence); + mutex_destroy(&core->lock); + kfree(core); +} + +static void amdgpu_sem_free(struct kref *kref) +{ + struct amdgpu_sem *sem = container_of( + kref, struct amdgpu_sem, kref); + + kref_put(&sem->base->kref, amdgpu_sem_core_free); + kfree(sem); +} + +static inline void amdgpu_sem_get(struct amdgpu_sem *sem) +{ + if (sem) + kref_get(&sem->kref); +} + +void amdgpu_sem_put(struct amdgpu_sem *sem) +{ + if (sem) + kref_put(&sem->kref, amdgpu_sem_free); +} + +static int amdgpu_sem_release(struct inode *inode, struct file *file) +{ + struct amdgpu_sem_core *core = file->private_data; + + /* set the core->file to null if file got released */ + mutex_lock(&core->lock); + core->file = NULL; + mutex_unlock(&core->lock); + + kref_put(&core->kref, amdgpu_sem_core_free); + return 0; +} + +static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) +{ + return 0; +} + +static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + +static const struct file_operations amdgpu_sem_fops = { + .release = amdgpu_sem_release, + .poll = amdgpu_sem_poll, + .unlocked_ioctl = amdgpu_sem_file_ioctl, + .compat_ioctl = amdgpu_sem_file_ioctl, +}; + + +static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem; + + spin_lock(&fpriv->sem_handles_lock); + + /* Check if we currently have a reference on the object */ + sem = idr_find(&fpriv->sem_handles, handle); + amdgpu_sem_get(sem); + + spin_unlock(&fpriv->sem_handles_lock); + + return sem; +} + +static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void) +{ + struct amdgpu_sem_core *core; + + core = kzalloc(sizeof(*core), GFP_KERNEL); + if (!core) + return NULL; + + kref_init(&core->kref); + mutex_init(&core->lock); + return core; +} + +static struct amdgpu_sem *amdgpu_sem_alloc(void) +{ + struct amdgpu_sem *sem; + + sem = kzalloc(sizeof(*sem), GFP_KERNEL); + if (!sem) + return NULL; + + kref_init(&sem->kref); + INIT_LIST_HEAD(&sem->list); + + return sem; +} + +static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_alloc(); + core = amdgpu_sem_core_alloc(); + if (!sem || !core) { + kfree(sem); + kfree(core); + return -ENOMEM; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handle = ret; + return 0; +} + +static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv, + u32 handle, struct dma_fence *fence) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + mutex_lock(&core->lock); + dma_fence_put(core->fence); + core->fence = dma_fence_get(fence); + mutex_unlock(&core->lock); + + amdgpu_sem_put(sem); + return 0; +} + +static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct amdgpu_sem *sem; + int ret; + + sem = amdgpu_sem_lookup(fpriv, in->handle); + if (!sem) + return -EINVAL; + + ret = amdgpu_sem_entity_add(fpriv, in, sem); + amdgpu_sem_put(sem); + + return ret; +} + +static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, + int fd, u32 *handle) +{ + struct file *file = fget(fd); + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + if (!file) + return -EINVAL; + + core = file->private_data; + if (!core) { + fput(file); + return -EINVAL; + } + + kref_get(&core->kref); + sem = amdgpu_sem_alloc(); + if (!sem) { + ret = -ENOMEM; + goto err_sem; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + goto err_out; + + *handle = ret; + fput(file); + return 0; +err_sem: + kref_put(&core->kref, amdgpu_sem_core_free); +err_out: + amdgpu_sem_put(sem); + fput(file); + return ret; + +} + +static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, + u32 handle, int *fd) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + kref_get(&core->kref); + mutex_lock(&core->lock); + if (!core->file) { + core->file = anon_inode_getfile("sem_file", + &amdgpu_sem_fops, + core, 0); + if (IS_ERR(core->file)) { + mutex_unlock(&core->lock); + ret = -ENOMEM; + goto err_put_sem; + } + } else { + get_file(core->file); + } + mutex_unlock(&core->lock); + + ret = get_unused_fd_flags(O_CLOEXEC); + if (ret < 0) + goto err_put_file; + + fd_install(ret, core->file); + + *fd = ret; + amdgpu_sem_put(sem); + + return 0; + +err_put_file: + fput(core->file); +err_put_sem: + kref_put(&core->kref, amdgpu_sem_core_free); + amdgpu_sem_put(sem); + return ret; +} + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return; + + spin_lock(&fpriv->sem_handles_lock); + idr_remove(&fpriv->sem_handles, handle); + spin_unlock(&fpriv->sem_handles_lock); + + kref_put(&sem->kref, amdgpu_sem_free); + kref_put(&sem->kref, amdgpu_sem_free); +} + +static struct dma_fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct drm_sched_entity *entity; + struct amdgpu_ctx *ctx; + struct dma_fence *fence; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return NULL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) { + amdgpu_ctx_put(ctx); + return NULL; + } + /* get the last fence of this entity */ + fence = amdgpu_ctx_get_fence(ctx, entity, in->seq); + amdgpu_ctx_put(ctx); + + return fence; +} + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_sem_dep *dep; + struct drm_sched_entity *entity; + struct amdgpu_ctx_entity *centity; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return -EINVAL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) + goto err; + + dep = kzalloc(sizeof(*dep), GFP_KERNEL); + if (!dep) + goto err; + + INIT_LIST_HEAD(&dep->list); + dep->fence = dma_fence_get(sem->base->fence); + + centity = to_amdgpu_ctx_entity(entity); + mutex_lock(¢ity->sem_lock); + list_add(&dep->list, ¢ity->sem_dep_list); + mutex_unlock(¢ity->sem_lock); + +err: + amdgpu_ctx_put(ctx); + return r; +} + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync) +{ + struct amdgpu_sem_dep *dep, *tmp; + struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); + int r = 0; + + if (list_empty(¢ity->sem_dep_list)) + return 0; + + mutex_lock(¢ity->sem_lock); + list_for_each_entry_safe(dep, tmp, ¢ity->sem_dep_list, + list) { + r = amdgpu_sync_fence(sync, dep->fence); + if (r) + goto err; + dma_fence_put(dep->fence); + list_del_init(&dep->list); + kfree(dep); + } +err: + mutex_unlock(¢ity->sem_lock); + return r; +} + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_sem *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct dma_fence *fence; + int r = 0; + + switch (args->in.op) { + case AMDGPU_SEM_OP_CREATE_SEM: + r = amdgpu_sem_create(fpriv, &args->out.handle); + break; + case AMDGPU_SEM_OP_WAIT_SEM: + r = amdgpu_sem_wait(fpriv, &args->in); + break; + case AMDGPU_SEM_OP_SIGNAL_SEM: + fence = amdgpu_sem_get_fence(fpriv, &args->in); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + return r; + } + r = amdgpu_sem_signal(fpriv, args->in.handle, fence); + dma_fence_put(fence); + break; + case AMDGPU_SEM_OP_IMPORT_SEM: + r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle); + break; + case AMDGPU_SEM_OP_EXPORT_SEM: + r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd); + break; + case AMDGPU_SEM_OP_DESTROY_SEM: + amdgpu_sem_destroy(fpriv, args->in.handle); + break; + default: + r = -EINVAL; + break; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h new file mode 100644 index 0000000000000..dbbb9d4540233 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Chunming Zhou + * + */ + + +#ifndef _LINUX_AMDGPU_SEM_H +#define _LINUX_AMDGPU_SEM_H + +#include +#include +#include +#include +#include + +struct amdgpu_sem_core { + struct file *file; + struct kref kref; + struct dma_fence *fence; + struct mutex lock; +}; + +struct amdgpu_sem_dep { + struct dma_fence *fence; + struct list_head list; +}; + +struct amdgpu_sem { + struct amdgpu_sem_core *base; + struct kref kref; + struct list_head list; +}; + +void amdgpu_sem_put(struct amdgpu_sem *sem); + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync); + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle); + +#endif /* _LINUX_AMDGPU_SEM_H */ diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 7dbcc131176c7..9302061d8880d 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -59,6 +59,9 @@ extern "C" { #define DRM_AMDGPU_USERQ_WAIT 0x18 #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 +/* hybrid specific ioctls */ +#define DRM_AMDGPU_SEM 0x5b + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) @@ -106,6 +109,9 @@ extern "C" { * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for * signalling user mode queues. */ +/* hybrid specific ioctls */ +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) + #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 @@ -183,6 +189,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) /* hybrid specific */ +/* Flag that the memory should be in SPARSE resource */ +#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) /* Flag that the memory allocation should be from top of domain */ #define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ @@ -587,6 +595,35 @@ struct drm_amdgpu_userq_wait { __u64 out_fences; }; +/* sem related */ +#define AMDGPU_SEM_OP_CREATE_SEM 1 +#define AMDGPU_SEM_OP_WAIT_SEM 2 +#define AMDGPU_SEM_OP_SIGNAL_SEM 3 +#define AMDGPU_SEM_OP_DESTROY_SEM 4 +#define AMDGPU_SEM_OP_IMPORT_SEM 5 +#define AMDGPU_SEM_OP_EXPORT_SEM 6 + +struct drm_amdgpu_sem_in { + /** AMDGPU_SEM_OP_* */ + uint32_t op; + uint32_t handle; + uint32_t ctx_id; + uint32_t ip_type; + uint32_t ip_instance; + uint32_t ring; + uint64_t seq; +}; + +union drm_amdgpu_sem_out { + int32_t fd; + uint32_t handle; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + union drm_amdgpu_sem_out out; +}; + /* vm ioctl */ #define AMDGPU_VM_OP_RESERVE_VMID 1 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 From caf963ad02ac419c79fef4ab1081c6561642f49e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Aug 2018 17:35:56 +0800 Subject: [PATCH 0413/2070] drm/amdgpu: [hybrid] add direct gma(dgma) support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: rebase on linux 4.18 and cleanup v3: 3f8d459ca0f1("drm/amdgpu: [hybrid] fix DGMA buffer info loss issue (v2)") v4: 814cd038a6b5(drm/amdkcl: modify DGMA setting for new PL_DOORBELL support) Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Junwei Zhang (v2) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Acked-by: Christian König Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 86 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 325 ++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 11 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 + include/drm/ttm/ttm_resource.h | 2 +- include/uapi/drm/amdgpu_drm.h | 22 +- 11 files changed, 504 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0200111e3e310..398443abc8e92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -188,6 +188,7 @@ extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; @@ -670,6 +671,9 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + /* VRAM scratch page for HDP bug, default vram page */ struct amdgpu_mem_scratch { struct amdgpu_bo *robj; @@ -707,6 +711,15 @@ struct amdgpu_mmio_remap { struct amdgpu_bo *bo; }; + +struct amdgpu_direct_gma { + /* reserved in visible vram*/ + struct amdgpu_bo *dgma_bo; + atomic64_t vram_usage; + /* reserved in gart */ + atomic64_t gart_usage; +}; + enum amdgpu_uid_type { AMDGPU_UID_TYPE_XCD, AMDGPU_UID_TYPE_AID, @@ -915,6 +928,9 @@ struct amdgpu_device { uint32_t bios_scratch_reg_offset; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; + /* Direct GMA */ + struct amdgpu_direct_gma direct_gma; + /* Register/doorbell mmio */ resource_size_t rmmio_base; resource_size_t rmmio_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7c57518ba6d93..fac19292d4438 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2295,6 +2295,7 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) amdgpu_device_check_block_size(adev); adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); + amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96); for (i = 0; i < MAX_XCP; i++) { switch (amdgpu_enforce_isolation) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 174a56fbac4bf..0e7f35da6105a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -178,6 +178,7 @@ int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_no_evict; +int amdgpu_direct_gma_size; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -502,6 +503,10 @@ module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); + /** * DOC: forcelongtraining (uint) * Force long memory training in resume. @@ -3073,6 +3078,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index a44c17f66cf1e..d44d3a32f826b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -155,6 +155,7 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); + struct amdgpu_device *adev = amdgpu_ttm_adev(aobj->tbo.bdev); if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { if (!amdgpu_bo_reserve(aobj, false)) { @@ -163,6 +164,13 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } + if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + atomic64_sub(amdgpu_bo_size(aobj), + &adev->direct_gma.vram_usage); + else if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + atomic64_sub(amdgpu_bo_size(aobj), + &adev->direct_gma.gart_usage); + amdgpu_hmm_unregister(aobj); ttm_bo_fini(&aobj->tbo); } @@ -176,12 +184,30 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, struct amdgpu_bo *bo; struct amdgpu_bo_user *ubo; struct amdgpu_bo_param bp; + unsigned long max_size; int r; memset(&bp, 0, sizeof(bp)); *obj = NULL; flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; + if ((initial_domain & AMDGPU_GEM_DOMAIN_DGMA) || + (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { + flags |= AMDGPU_GEM_CREATE_NO_EVICT; + max_size = (unsigned long)amdgpu_direct_gma_size << 20; + + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + max_size -= atomic64_read(&adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + max_size -= atomic64_read(&adev->direct_gma.gart_usage); + + if (size > max_size) { + DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", + size >> 20, max_size >> 20); + return -ENOMEM; + } + } + bp.size = size; bp.byte_align = alignment; bp.type = type; @@ -199,6 +225,11 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, bo = &ubo->bo; *obj = &bo->tbo.base; + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + atomic64_add(size, &adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + atomic64_add(size, &adev->direct_gma.gart_usage); + return 0; } @@ -583,6 +614,61 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return r; } +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + struct drm_amdgpu_gem_dgma *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *abo; + dma_addr_t *dma_addr; + uint32_t handle; + int i, r = 0; + + switch (args->op) { + case AMDGPU_GEM_DGMA_IMPORT: + /* create a gem object to contain this object in */ + r = amdgpu_gem_object_create(adev, args->size, 0, + AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, + 0, NULL, &gobj); + if (r) + return r; + + abo = gem_to_amdgpu_bo(gobj); + dma_addr = kmalloc_array(abo->tbo.resource->num_pages, sizeof(dma_addr_t), GFP_KERNEL); + if (unlikely(dma_addr == NULL)) + goto release_object; + + for (i = 0; i < abo->tbo.resource->num_pages; i++) + dma_addr[i] = args->addr + i * PAGE_SIZE; + abo->dgma_import_base = args->addr; + abo->dgma_addr = (void *)dma_addr; + r = drm_gem_handle_create(filp, gobj, &handle); + args->handle = handle; + break; + case AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR: + gobj = drm_gem_object_lookup(filp, args->handle); + if (gobj == NULL) + return -ENOENT; + + abo = gem_to_amdgpu_bo(gobj); + if (abo->tbo.resource->mem_type != AMDGPU_PL_DGMA) { + r = -EINVAL; + goto release_object; + } + args->addr = amdgpu_bo_gpu_offset(abo) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM) + + adev->gmc.aper_base; + break; + default: + return -EINVAL; + } + +release_object: + drm_gem_object_put(gobj); + return r; +} + int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f989f89000f5d..c346860b63758 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -61,6 +61,8 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + kfree(bo->dgma_addr); + amdgpu_bo_kunmap(bo); if (drm_gem_is_imported(&bo->tbo.base)) @@ -115,6 +117,22 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) u64 flags = abo->flags; u32 c = 0, i; + if ((domain & AMDGPU_GEM_DOMAIN_DGMA) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA; + places[c].flags = 0; + c++; + } + + if ((domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA_IMPORT; + places[c].flags = 0; + c++; + } + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); @@ -738,7 +756,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - if ((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) { + if (((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) || + bp->domain & (AMDGPU_GEM_DOMAIN_DGMA | AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { r = amdgpu_bo_reserve(bo, false); if (unlikely(r != 0)) return r; @@ -1493,6 +1512,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); + WARN_ON_ONCE(bo->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT); return amdgpu_bo_gpu_offset_no_check(bo); } @@ -1647,6 +1667,12 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) else placement = "VRAM"; break; + case AMDGPU_PL_DGMA: + placement = "DGMA"; + break; + case AMDGPU_PL_DGMA_IMPORT: + placement = "DGMA_IMPORT"; + break; case TTM_PL_TT: placement = "GTT"; break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 912c9afaf9e11..f7f93243369ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -118,6 +118,10 @@ struct amdgpu_bo { #endif struct kgd_mem *kfd_bo; + /* DGMA imported buffer info */ + void *dgma_addr; + phys_addr_t dgma_import_base; + /* * For GPUs with spatial partitioning, xcp partition number, -1 means * any partition. For other ASICs without spatial partition, always 0 @@ -132,7 +136,6 @@ struct amdgpu_bo_user { u64 metadata_flags; void *metadata; u32 metadata_size; - }; struct amdgpu_bo_vm { @@ -168,6 +171,10 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) return AMDGPU_GEM_DOMAIN_OA; case AMDGPU_PL_DOORBELL: return AMDGPU_GEM_DOMAIN_DOORBELL; + case AMDGPU_PL_DGMA: + return AMDGPU_GEM_DOMAIN_DGMA; + case AMDGPU_PL_DGMA_IMPORT: + return AMDGPU_GEM_DOMAIN_DGMA_IMPORT; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index c1e5457bd320d..3501986c50e68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -65,6 +65,11 @@ MODULE_IMPORT_NS("DMA_BUF"); #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) +struct amdgpu_dgma_node { + struct ttm_buffer_object *tbo; + struct ttm_range_mgr_node base; +}; + static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); @@ -128,6 +133,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, return; case TTM_PL_VRAM: + case AMDGPU_PL_DGMA: if (!adev->mman.buffer_funcs_enabled) { /* Move to system memory */ amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -154,6 +160,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } break; case TTM_PL_TT: + case AMDGPU_PL_DGMA_IMPORT: case AMDGPU_PL_PREEMPT: default: amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -514,6 +521,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, } abo = ttm_to_amdgpu_bo(bo); + + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -624,7 +636,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, case AMDGPU_PL_PREEMPT: break; case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; + case AMDGPU_PL_DGMA: + mem->bus.offset = (mem->start << PAGE_SHIFT) + + amdgpu_ttm_domain_start(adev, mem->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); if (adev->mman.aper_base_kaddr && mem->placement & TTM_PL_FLAG_CONTIGUOUS) @@ -646,6 +661,19 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, mem->bus.is_iomem = true; mem->bus.caching = ttm_uncached; break; + case AMDGPU_PL_DGMA_IMPORT: + { + struct amdgpu_dgma_node *node; + struct amdgpu_bo *abo; + + node = container_of(mem, struct amdgpu_dgma_node, base.base); + abo = ttm_to_amdgpu_bo(node->tbo); + mem->bus.addr = abo->dgma_addr; + mem->bus.offset = abo->dgma_import_base; + mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; + break; + } default: return -EINVAL; } @@ -658,6 +686,10 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_res_cursor cursor; + if (bo->resource->mem_type == AMDGPU_PL_DGMA || + bo->resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + return (bo->resource->bus.offset >> PAGE_SHIFT) + page_offset; + amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor); @@ -685,6 +717,12 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) return adev->gmc.gart_start; case TTM_PL_VRAM: return adev->gmc.vram_start; + case AMDGPU_PL_DGMA: + if (adev->direct_gma.dgma_bo) + return amdgpu_bo_gpu_offset(adev->direct_gma.dgma_bo); + fallthrough; + case AMDGPU_PL_DGMA_IMPORT: + return 0; } return 0; @@ -1449,6 +1487,9 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, { uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); + if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + flags |= AMDGPU_PTE_SYSTEM; + flags |= adev->gart.gart_pte_flags; flags |= AMDGPU_PTE_READABLE; @@ -1874,6 +1915,252 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } +static inline struct amdgpu_dgma_import_mgr *to_dgma_import_mgr(struct ttm_resource_manager *man) +{ + return container_of(man, struct amdgpu_dgma_import_mgr, manager); +} + +static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func; +/** + * amdgpu_dgma_import_mgr_init - init DGMA_import manager and DRM MM + * + * @adev: amdgpu_device pointer + * @dgma_size: maximum size of DGMA + * + * Allocate and initialize the DGMA manager. + */ +static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_size) +{ + struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; + struct ttm_resource_manager *man = &mgr->manager; + + man->func = &amdgpu_dgma_import_mgr_func; + + ttm_resource_manager_init(man, &adev->mman.bdev, p_size); + drm_mm_init(&mgr->mm, 0, p_size); + spin_lock_init(&mgr->lock); + atomic64_set(&mgr->available, p_size); + + ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); + ttm_resource_manager_set_used(man, true); + return 0; +} + +/** + * amdgpu_dgma_import_mgr_fini - free and destroy DGMA import manager + * + * @adev: amdgpu_device pointer + * + * Destroy and free the DGMA import manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +static void amdgpu_dgma_import_mgr_fini(struct amdgpu_device *adev) +{ + struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + + ttm_resource_manager_set_used(man, false); + + ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); + if (ret) + return; + + spin_lock(&mgr->lock); + drm_mm_takedown(&mgr->mm); + spin_unlock(&mgr->lock); + ttm_resource_manager_cleanup(man); + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); +} + +/** + * amdgpu_dgma_import_mgr_new - allocate a new node + * + * @man: TTM memory type manager + * @tbo: TTM BO we need this range for + * @place: placement flags and restrictions + * @mem: the resulting mem object + */ +static int amdgpu_dgma_import_mgr_new(struct ttm_resource_manager *man, + struct ttm_buffer_object *tbo, + const struct ttm_place *place, + struct ttm_resource **res) +{ + struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); + uint32_t num_pages = PFN_UP(tbo->base.size); + struct amdgpu_dgma_node *node; + unsigned long lpfn; + int r; + + spin_lock(&mgr->lock); + if (atomic64_read(&mgr->available) < num_pages) { + spin_unlock(&mgr->lock); + return -ENOSPC; + } + atomic64_sub(num_pages, &mgr->available); + spin_unlock(&mgr->lock); + + lpfn = place->lpfn; + if (!lpfn) + lpfn = man->size; + + node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); + if (!node) { + r = -ENOMEM; + goto err_out; + } + + node->tbo = tbo; + ttm_resource_init(tbo, place, &node->base.base); + + spin_lock(&mgr->lock); + r = drm_mm_insert_node_in_range(&mgr->mm, &node->base.mm_nodes[0], num_pages, + tbo->page_alignment, 0, place->fpfn, + lpfn, DRM_MM_INSERT_BEST); + spin_unlock(&mgr->lock); + + if (unlikely(r)) + goto err_free; + + *res = &node->base.base; + (*res)->start = node->base.mm_nodes[0].start; + + return 0; + +err_free: + kfree(node); + +err_out: + atomic64_add(num_pages, &mgr->available); + + return r; +} + +/** + * amdgpu_dgma_import_mgr_del - free ranges + * + * @man: TTM memory type manager + * @mem: TTM memory object + * + * Free the allocated node. + */ +static void amdgpu_dgma_import_mgr_del(struct ttm_resource_manager *man, + struct ttm_resource *mem) +{ + struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); + struct amdgpu_dgma_node *node = container_of(mem, struct amdgpu_dgma_node, base.base); + + if (node) { + spin_lock(&mgr->lock); + drm_mm_remove_node(&node->base.mm_nodes[0]); + spin_unlock(&mgr->lock); + kfree(node); + } + + atomic64_add(mem->num_pages, &mgr->available); +} + +static void amdgpu_dgma_import_mgr_debug(struct ttm_resource_manager *man, + struct drm_printer *printer) +{ + struct amdgpu_dgma_import_mgr *rman = to_dgma_import_mgr(man); + + spin_lock(&rman->lock); + drm_mm_print(&rman->mm, printer); + spin_unlock(&rman->lock); +} + +static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func = { + .alloc = amdgpu_dgma_import_mgr_new, + .free = amdgpu_dgma_import_mgr_del, + .debug = amdgpu_dgma_import_mgr_debug +}; + +static int amdgpu_direct_gma_init(struct amdgpu_device *adev) +{ + struct amdgpu_bo *abo; + struct amdgpu_bo_param bp; + unsigned long size; + int r; + + if (amdgpu_direct_gma_size == 0) + return 0; + + size = (unsigned long)amdgpu_direct_gma_size << 20; + + memset(&bp, 0, sizeof(bp)); + bp.size = size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_TOP_DOWN; + bp.type = ttm_bo_type_kernel; + bp.resv = NULL; + + /* reserve in visible vram */ + r = amdgpu_bo_create(adev, &bp, &abo); + if (unlikely(r)) + goto error_out; + + r = amdgpu_bo_reserve(abo, false); + if (unlikely(r)) + goto error_free; + + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + amdgpu_bo_unreserve(abo); + if (unlikely(r)) + goto error_free; + + adev->direct_gma.dgma_bo = abo; + + /* reserve in gtt */ + atomic64_add(size, &adev->gart_pin_size); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA, + false, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_put_node; + + r = amdgpu_dgma_import_mgr_init(adev, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_release_mm; + + DRM_INFO("%dMB VRAM/GTT reserved for Direct GMA\n", amdgpu_direct_gma_size); + return 0; + +error_release_mm: + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + +error_put_node: + atomic64_sub(size, &adev->gart_pin_size); +error_free: + amdgpu_bo_unref(&abo); + +error_out: + amdgpu_direct_gma_size = 0; + memset(&adev->direct_gma, 0, sizeof(adev->direct_gma)); + DRM_ERROR("Fail to enable Direct GMA\n"); + return r; +} + +static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) +{ + int r; + + if (amdgpu_direct_gma_size == 0) + return; + + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + amdgpu_dgma_import_mgr_fini(adev); + + r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); + if (r == 0) { + amdgpu_bo_unpin(adev->direct_gma.dgma_bo); + amdgpu_bo_unreserve(adev->direct_gma.dgma_bo); + } + amdgpu_bo_unref(&adev->direct_gma.dgma_bo); + atomic64_sub((u64)amdgpu_direct_gma_size << 20, &adev->gart_pin_size); +} + static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) { int i; @@ -2200,6 +2487,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) gtt_size = configured_size; } + /* reserve for DGMA import domain */ + gtt_size -= (uint64_t)amdgpu_direct_gma_size << 20; /* Initialize GTT memory pool */ r = amdgpu_gtt_mgr_init(adev, gtt_size); @@ -2210,6 +2499,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) dev_info(adev->dev, " %uM of GTT memory ready.\n", (unsigned int)(gtt_size / (1024 * 1024))); + amdgpu_direct_gma_init(adev); if (adev->flags & AMD_IS_APU) { if (adev->gmc.real_vram_size < gtt_size) adev->apu_prefer_gtt = true; @@ -2318,6 +2608,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + amdgpu_direct_gma_fini(adev); if (!adev->gmc.is_app_apu) amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); @@ -2700,7 +2991,32 @@ static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) return ttm_pool_debugfs(&adev->mman.bdev.pool, m); } +static int amdgpu_mm_dgma_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_dgma_import_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA_IMPORT); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); + /* * amdgpu_ttm_vram_read - Linear read access to VRAM @@ -2911,6 +3227,7 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) &amdgpu_ttm_iomem_fops); debugfs_create_file("ttm_page_pool", 0444, root, adev, &amdgpu_ttm_page_pool_fops); + ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), root, "amdgpu_vram_mm"); @@ -2927,5 +3244,11 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) AMDGPU_PL_OA), root, "amdgpu_oa_mm"); + if (amdgpu_direct_gma_size) { + debugfs_create_file("amdgpu_dgma_mm", 0444, root, adev, + &amdgpu_mm_dgma_table_fops); + debugfs_create_file("amdgpu_dgma_import_mm", 0444, root, adev, + &amdgpu_mm_dgma_import_table_fops); + } #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index bf101215757e7..f8ff6582718a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -37,7 +37,10 @@ #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) +#define __AMDGPU_PL_LAST (TTM_PL_PRIV + 5) #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) +#define AMDGPU_PL_DGMA (TTM_PL_PRIV + 7) +#define AMDGPU_PL_DGMA_IMPORT (TTM_PL_PRIV + 8) #define AMDGPU_GTT_MAX_TRANSFER_SIZE 1024 @@ -59,6 +62,13 @@ struct amdgpu_ttm_buffer_entity { u64 gart_window_offs[2]; }; +struct amdgpu_dgma_import_mgr { + struct ttm_resource_manager manager; + struct drm_mm mm; + spinlock_t lock; + atomic64_t available; +}; + struct amdgpu_mman { struct ttm_device bdev; struct ttm_pool *ttm_pools; @@ -77,6 +87,7 @@ struct amdgpu_mman { struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; + struct amdgpu_dgma_import_mgr dgma_import_mgr; struct ttm_resource_manager preempt_mgr; uint64_t stolen_vga_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 85c46779798a8..537315fb0248c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1174,6 +1174,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t tmp, num_entries, addr; num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; + if (pages_addr) { bool contiguous = true; @@ -1313,6 +1314,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; + else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + pages_addr = (dma_addr_t *)bo->tbo.mem.bus.addr; /* Implicitly sync to moving fences before mapping anything */ r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 33e80f30b8b82..05dbaead88ae7 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -35,7 +35,7 @@ #include #define TTM_MAX_BO_PRIORITY 4U -#define TTM_NUM_MEM_TYPES 9 +#define TTM_NUM_MEM_TYPES 13 struct dentry; struct dmem_cgroup_device; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 9302061d8880d..ce848c2d569c8 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -58,6 +58,8 @@ extern "C" { #define DRM_AMDGPU_USERQ_SIGNAL 0x17 #define DRM_AMDGPU_USERQ_WAIT 0x18 #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 +/* not upstream */ +#define DRM_AMDGPU_GEM_DGMA 0x5c /* hybrid specific ioctls */ #define DRM_AMDGPU_SEM 0x5b @@ -83,6 +85,8 @@ extern "C" { #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) +#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) + /** * DOC: memory domains * @@ -119,13 +123,17 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 +#define AMDGPU_GEM_DOMAIN_DGMA 0x400 +#define AMDGPU_GEM_DOMAIN_DGMA_IMPORT 0x800 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ AMDGPU_GEM_DOMAIN_GTT | \ AMDGPU_GEM_DOMAIN_VRAM | \ AMDGPU_GEM_DOMAIN_GDS | \ AMDGPU_GEM_DOMAIN_GWS | \ AMDGPU_GEM_DOMAIN_OA | \ - AMDGPU_GEM_DOMAIN_DOORBELL) + AMDGPU_GEM_DOMAIN_DOORBELL |\ + AMDGPU_GEM_DOMAIN_DGMA |\ + AMDGPU_GEM_DOMAIN_DGMA_IMPORT) /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) @@ -680,6 +688,15 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; +#define AMDGPU_GEM_DGMA_IMPORT 0 +#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 +struct drm_amdgpu_gem_dgma { + __u64 addr; + __u64 size; + __u32 op; + __u32 handle; +}; + /* SI-CI-VI: */ /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 @@ -1320,6 +1337,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 /* query pin memory capability */ #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) +/* query direct gma capability */ +#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1738,6 +1757,7 @@ struct drm_amdgpu_virtual_range { struct drm_amdgpu_capability { __u32 flag; + __u32 direct_gma_size; }; /* From 1ebc8995afd62127d3b5a49c1adc195043a89082 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Apr 2021 11:17:58 +0800 Subject: [PATCH 0414/2070] drm/amdgpu: [hybrid] fix bo_ptr_size for dgma Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3501986c50e68..fd86f0adde6b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2096,6 +2096,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) AMDGPU_GEM_CREATE_TOP_DOWN; bp.type = ttm_bo_type_kernel; bp.resv = NULL; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); /* reserve in visible vram */ r = amdgpu_bo_create(adev, &bp, &abo); From 635de621a4b19fe8b1748d32551fc7ec15167377 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Apr 2021 15:51:05 +0800 Subject: [PATCH 0415/2070] drm/amdgpu: [hybrid] fix gpu mapping for dgma Signed-off-by: Flora Cui Signed-off-by: xinhui pan Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 537315fb0248c..d9a8fc2ecd0a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1315,7 +1315,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) - pages_addr = (dma_addr_t *)bo->tbo.mem.bus.addr; + pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, From f974620992ebf61e36b1da48e23f9998b74f3ee3 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Fri, 17 Sep 2021 11:43:13 +0800 Subject: [PATCH 0416/2070] drm/amdgpu: [hybrid]enable dGMA path in page table mapping Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 69 +++++++++++++++----------- 1 file changed, 41 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d9a8fc2ecd0a0..d2a7e7004262c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1175,45 +1175,58 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; - if (pages_addr) { - bool contiguous = true; + if (res && (res->mem_type == AMDGPU_PL_DGMA_IMPORT || + res->mem_type == AMDGPU_PL_DGMA)) { + uint64_t pfn = offset >> PAGE_SHIFT; - if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { - uint64_t pfn = cursor.start >> PAGE_SHIFT; - uint64_t count; + if (res->mem_type == AMDGPU_PL_DGMA_IMPORT) { + addr = 0; + } else { + addr = pfn << PAGE_SHIFT; + addr += vram_base + + cursor.start + amdgpu_ttm_domain_start(adev, res->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); + params.pages_addr = NULL; + } + } else { + if (pages_addr) { + bool contiguous = true; - contiguous = pages_addr[pfn + 1] == - pages_addr[pfn] + PAGE_SIZE; + if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { + uint64_t pfn = cursor.start >> PAGE_SHIFT; + uint64_t count; - tmp = num_entries / - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - for (count = 2; count < tmp; ++count) { - uint64_t idx = pfn + count; + contiguous = pages_addr[pfn + 1] == + pages_addr[pfn] + PAGE_SIZE; + + tmp = num_entries / + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + for (count = 2; count < tmp; ++count) { + uint64_t idx = pfn + count; if (contiguous != (pages_addr[idx] == - pages_addr[idx - 1] + PAGE_SIZE)) + pages_addr[idx - 1] + PAGE_SIZE)) break; - } - if (!contiguous) + } + if (!contiguous) count--; - num_entries = count * - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - } + num_entries = count * + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + } - if (!contiguous) { - addr = cursor.start; - params.pages_addr = pages_addr; + if (!contiguous) { + addr = cursor.start; + params.pages_addr = pages_addr; + } else { + addr = pages_addr[cursor.start >> PAGE_SHIFT]; + params.pages_addr = NULL; + } + } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { + addr = vram_base + cursor.start; } else { - addr = pages_addr[cursor.start >> PAGE_SHIFT]; - params.pages_addr = NULL; + addr = 0; } - - } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { - addr = vram_base + cursor.start; - } else { - addr = 0; } - tmp = start + num_entries; r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags); if (r) From 3d89dad914277c9992696cfa565b2428d8ff6420 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 22 Apr 2020 22:53:31 -0400 Subject: [PATCH 0417/2070] drm/amdgpu: Add PCIe P2P support Allow mapping remote GPU memory in GPUVM for large-BAR GPUs with the BAR within the GPU physical address range. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 2f77a932abdfb..274a5b083a5de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -42,6 +42,7 @@ */ uint64_t amdgpu_amdkfd_total_mem_size; +extern bool pcie_p2p; static bool kfd_initialized; int amdgpu_amdkfd_init(void) From dcc2a809023df1aee6776202ebe15360d08bfb32 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 00:11:19 -0400 Subject: [PATCH 0418/2070] drm/amdkfd: Add IPC API This allows exporting and importing buffers. The API generates handles that can be used with the HIP IPC API, i.e. big numbers rather than file descriptors. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 32 ++- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 73 ++++- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 270 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 51 ++++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 5 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 28 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 106 ++++++- include/uapi/linux/kfd_ioctl.h | 22 ++ 10 files changed, 566 insertions(+), 25 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ipc.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ipc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index cdbab7f8cee8c..995c2d2072f2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -340,6 +340,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct dma_buf **dmabuf); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a570eeb21bccd..b106e58004456 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2390,12 +2390,14 @@ static int import_obj_create(struct amdgpu_device *adev, INIT_LIST_HEAD(&(*mem)->attachments); mutex_init(&(*mem)->lock); - - (*mem)->alloc_flags = - ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? - KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) - | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE - | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; + if (bo->kfd_bo) + (*mem)->alloc_flags = bo->kfd_bo->alloc_flags; + else + (*mem)->alloc_flags = + ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? + KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) + | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE + | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; @@ -2482,6 +2484,24 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } +int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct dma_buf **dmabuf) +{ + struct amdgpu_device *adev = NULL; + + if (!dmabuf || !kgd || !vm || !mem) + return -EINVAL; + + adev = get_amdgpu_device(kgd); + + *dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); + if (IS_ERR(*dmabuf)) + return -EINVAL; + + return 0; +} + /* Evict a userptr BO by stopping the queues if necessary * * Runs in MMU notifier, may be in RECLAIM_FS context. This means it diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 85fc67d521e53..3fb8ab2bba63d 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -61,6 +61,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_int_process_v12_1.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 732ad1224a619..61db202390891 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -39,6 +39,7 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_ipc.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -1066,6 +1067,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + uint64_t cpuva = 0; + unsigned int mem_type = 0; if (args->size == 0) return -EINVAL; @@ -1165,7 +1168,13 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (err) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + mem_type = flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, args->size, cpuva, mem_type, NULL); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1209,7 +1218,8 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, { struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; - void *mem; + struct kfd_bo *buf_obj; + struct kfd_dev *dev; int ret; uint64_t size = 0; @@ -1231,15 +1241,15 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, goto err_pdd; } - mem = kfd_process_device_translate_handle( - pdd, GET_IDR_HANDLE(args->handle)); - if (!mem) { + buf_obj = kfd_process_device_find_bo(pdd, + GET_IDR_HANDLE(args->handle)); + if (!buf_obj) { ret = -EINVAL; goto err_unlock; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, - (struct kgd_mem *)mem, pdd->drm_priv, &size); + buf_obj->mem, pdd->drm_priv, &size); /* If freeing the buffer failed, leave the handle in place for * clean-up during process tear-down. @@ -1603,7 +1613,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, if (r) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -1617,12 +1628,52 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, - pdd->drm_priv, NULL); + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; } +static int kfd_ioctl_ipc_export_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_export_handle_args *args = data; + struct kfd_dev *dev; + int r; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle); + if (r) + pr_err("Failed to export IPC handle\n"); + + return r; +} + +static int kfd_ioctl_ipc_import_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_import_handle_args *args = data; + struct kfd_dev *dev = NULL; + int r; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, + args->va_addr, &args->handle, + &args->mmap_offset); + if (r) + pr_err("Failed to import IPC handle\n"); + + return r; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -3325,6 +3376,12 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, kfd_ioctl_create_process, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_IMPORT_HANDLE, + kfd_ioctl_ipc_import_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, + kfd_ioctl_ipc_export_handle, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c new file mode 100644 index 0000000000000..51395a88c12a8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -0,0 +1,270 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "kfd_ipc.h" +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" + +#define KFD_IPC_HASH_TABLE_SIZE_SHIFT 4 +#define KFD_IPC_HASH_TABLE_SIZE_MASK ((1 << KFD_IPC_HASH_TABLE_SIZE_SHIFT) - 1) + +static struct kfd_ipc_handles { + DECLARE_HASHTABLE(handles, KFD_IPC_HASH_TABLE_SIZE_SHIFT); + struct mutex lock; +} kfd_ipc_handles; + +/* Since, handles are random numbers, it can be used directly as hashing key. + * The least 4 bits of the handle are used as key. However, during import all + * 128 bits of the handle are checked to prevent handle snooping. + */ +#define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) + +static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) +{ + struct kfd_ipc_obj *obj; + + obj = kmalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + + /* The initial ref belongs to the allocator process. + * The IPC object store itself does not hold a ref since + * there is no specific moment in time where that ref should + * be dropped, except "when there are no more userspace processes + * holding a ref to the object". Therefore the removal from IPC + * storage happens at ipc_obj release time. + */ + kref_init(&obj->ref); + obj->data = val; + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + memcpy(sh, obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + hlist_add_head(&obj->node, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + mutex_unlock(&kfd_ipc_handles.lock); + + if (ipc_obj) + *ipc_obj = obj; + + return 0; +} + +static void ipc_obj_release(struct kref *r) +{ + struct kfd_ipc_obj *obj; + + obj = container_of(r, struct kfd_ipc_obj, ref); + + mutex_lock(&kfd_ipc_handles.lock); + hash_del(&obj->node); + mutex_unlock(&kfd_ipc_handles.lock); + + dma_buf_put(obj->data); + kfree(obj); +} + +void ipc_obj_get(struct kfd_ipc_obj *obj) +{ + kref_get(&obj->ref); +} + +void ipc_obj_put(struct kfd_ipc_obj **obj) +{ + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; +} + +int kfd_ipc_init(void) +{ + mutex_init(&kfd_ipc_handles.lock); + hash_init(kfd_ipc_handles.handles); + return 0; +} + +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, + struct kfd_process *p, + uint32_t gpu_id, struct dma_buf *dmabuf, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset, + struct kfd_ipc_obj *ipc_obj) +{ + int r; + void *mem; + uint64_t size; + int idr_handle; + struct kfd_process_device *pdd = NULL; + + if (!handle) + return -EINVAL; + + if (!dev) + return -EINVAL; + + mutex_lock(&p->mutex); + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + r = PTR_ERR(pdd); + goto err_unlock; + } + + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, + va_addr, pdd->vm, + (struct kgd_mem **)&mem, &size, + mmap_offset); + if (r) + goto err_unlock; + + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + va_addr, size, 0, 0, + ipc_obj); + if (idr_handle < 0) { + r = -EFAULT; + goto err_free; + } + + mutex_unlock(&p->mutex); + + *handle = MAKE_HANDLE(gpu_id, idr_handle); + + return 0; + +err_free: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); +err_unlock: + mutex_unlock(&p->mutex); + return r; +} + +int kfd_ipc_import_dmabuf(struct kfd_dev *dev, + struct kfd_process *p, + uint32_t gpu_id, int dmabuf_fd, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset) +{ + int r; + struct dma_buf *dmabuf = dma_buf_get(dmabuf_fd); + + if (!dmabuf) + return -EINVAL; + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, + va_addr, handle, mmap_offset, + NULL); + dma_buf_put(dmabuf); + return r; +} + +int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset) +{ + int r; + struct kfd_ipc_obj *entry, *found = NULL; + + mutex_lock(&kfd_ipc_handles.lock); + /* Convert the user provided handle to hash key and search only in that + * bucket + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { + if (!memcmp(entry->share_handle, share_handle, + sizeof(entry->share_handle))) { + found = entry; + break; + } + } + mutex_unlock(&kfd_ipc_handles.lock); + + if (!found) + return -EINVAL; + ipc_obj_get(found); + + pr_debug("Found ipc_dma_buf: %p\n", found->data); + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->data, + va_addr, handle, mmap_offset, + found); + if (r) + goto error_unref; + + return r; + +error_unref: + ipc_obj_put(&found); + return r; +} + +int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle) +{ + struct kfd_process_device *pdd = NULL; + struct kfd_ipc_obj *obj; + struct kfd_bo *kfd_bo = NULL; + struct dma_buf *dmabuf; + int r; + + if (!dev || !ipc_handle) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + mutex_unlock(&p->mutex); + pr_err("Failed to get pdd\n"); + return PTR_ERR(pdd); + } + + kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); + mutex_unlock(&p->mutex); + + if (!kfd_bo) { + pr_err("Failed to get bo"); + return -EINVAL; + } + if (kfd_bo->kfd_ipc_obj) { + memcpy(ipc_handle, kfd_bo->kfd_ipc_obj->share_handle, + sizeof(kfd_bo->kfd_ipc_obj->share_handle)); + return 0; + } + + r = amdgpu_amdkfd_gpuvm_export_dmabuf(dev->kgd, pdd->vm, + (struct kgd_mem *)kfd_bo->mem, + &dmabuf); + if (r) + return r; + + r = ipc_store_insert(dmabuf, ipc_handle, &obj); + if (r) + return r; + + kfd_bo->kfd_ipc_obj = obj; + + return r; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h new file mode 100644 index 0000000000000..9ee8627b88b08 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_IPC_H_ +#define KFD_IPC_H_ + +#include +#include "kfd_priv.h" + +struct kfd_ipc_obj { + struct hlist_node node; + struct kref ref; + void *data; + uint32_t share_handle[4]; +}; + +int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset); +int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, + uint32_t gpu_id, int dmabuf_fd, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset); +int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle); + +void ipc_obj_get(struct kfd_ipc_obj *obj); +void ipc_obj_put(struct kfd_ipc_obj **obj); + +#endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 33aa23450b3f7..0b86c763d76b2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -53,6 +53,10 @@ static int kfd_init(void) if (err < 0) goto err_topology; + err = kfd_ipc_init(); + if (err < 0) + goto err_ipc; + err = kfd_process_create_wq(); if (err < 0) goto err_create_wq; @@ -67,6 +71,7 @@ static int kfd_init(void) return 0; err_create_wq: +err_ipc: kfd_topology_shutdown(); err_topology: kfd_chardev_exit(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index edda16652a2cd..4ce2a26a96aae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -389,6 +389,19 @@ struct kfd_dev { atomic_t kfd_processes_count; }; +struct kfd_ipc_obj; + +struct kfd_bo { + void *mem; + struct interval_tree_node it; + struct kfd_dev *dev; + struct list_head cb_data_head; + struct kfd_ipc_obj *kfd_ipc_obj; + /* page-aligned VA address */ + uint64_t cpuva; + unsigned int mem_type; +}; + enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, @@ -950,6 +963,8 @@ struct kfd_process { size_t signal_event_count; bool signal_event_limit_reached; + struct rb_root_cached bo_interval_tree; + /* Information used for memory eviction */ void *kgd_process_info; /* Eviction fence that is attached to all the BOs of this process. The @@ -1110,9 +1125,17 @@ void kfd_process_notifier_release_internal(struct kfd_process *p); /* KFD process API for creating and translating handles */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem); + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + struct kfd_ipc_obj *ipc_obj); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle); +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr); void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); @@ -1574,6 +1597,9 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +/* IPC Support */ +int kfd_ipc_init(void); + /* Compute profile */ void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 6d32941ce8c74..312585234f65e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -32,6 +32,7 @@ #include #include #include +#include "kfd_ipc.h" #include #include "amdgpu_amdkfd.h" #include "amdgpu.h" @@ -741,6 +742,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, { struct kfd_node *kdev = pdd->dev; int err; + unsigned int mem_type; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, pdd->drm_priv, mem, NULL, @@ -1046,7 +1048,7 @@ struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid) static void kfd_process_device_free_bos(struct kfd_process_device *pdd) { struct kfd_process *p = pdd->process; - void *mem; + struct kfd_bo *buf_obj; int id; int i; @@ -1054,7 +1056,8 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * Remove all handles from idr and release appropriate * local memory object */ - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kfd_process_device *peer_pdd; for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -1062,11 +1065,11 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->adev, mem, peer_pdd->drm_priv); + peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); } amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, - pdd->drm_priv, NULL); + buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } } @@ -1877,9 +1880,49 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, * Assumes that the process lock is held. */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem) + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + struct kfd_ipc_obj *ipc_obj) +{ + int handle; + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + buf_obj = kzalloc(sizeof(*buf_obj), GFP_KERNEL); + + if (!buf_obj) + return -ENOMEM; + + buf_obj->it.start = start; + buf_obj->it.last = start + length - 1; + interval_tree_insert(&buf_obj->it, &p->bo_interval_tree); + + buf_obj->mem = mem; + buf_obj->dev = pdd->dev; + buf_obj->kfd_ipc_obj = ipc_obj; + buf_obj->cpuva = cpuva; + buf_obj->mem_type = mem_type; + + INIT_LIST_HEAD(&buf_obj->cb_data_head); + + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + + if (handle < 0) + kfree(buf_obj); + + return handle; +} + +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle) { - return idr_alloc(&pdd->alloc_idr, mem, 0, 0, GFP_KERNEL); + if (handle < 0) + return NULL; + + return (struct kfd_bo *)idr_find(&pdd->alloc_idr, handle); } /* Translate specific handle from process local memory idr @@ -1888,10 +1931,37 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, int handle) { - if (handle < 0) + struct kfd_bo *buf_obj; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + return buf_obj->mem; +} + +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr) +{ + struct interval_tree_node *it_node; + struct kfd_bo *buf_obj; + + it_node = interval_tree_iter_first(&p->bo_interval_tree, + start_addr, last_addr); + if (!it_node) { + pr_err("0x%llx-0x%llx does not relate to an existing buffer\n", + start_addr, last_addr); return NULL; + } + + if (interval_tree_iter_next(it_node, start_addr, last_addr)) { + pr_err("0x%llx-0x%llx spans more than a single BO\n", + start_addr, last_addr); + return NULL; + } + + buf_obj = container_of(it_node, struct kfd_bo, it); - return idr_find(&pdd->alloc_idr, handle); + return buf_obj; } /* Remove specific handle from process local memory idr @@ -1900,8 +1970,24 @@ void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle) { - if (handle >= 0) - idr_remove(&pdd->alloc_idr, handle); + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + if (handle < 0) + return; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + if (buf_obj->kfd_ipc_obj) + ipc_obj_put(&buf_obj->kfd_ipc_obj); + + idr_remove(&pdd->alloc_idr, handle); + + interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); + + kfree(buf_obj); } static struct kfd_process_device *kfd_lookup_process_device_by_pasid(u32 pasid) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index e72359370857c..890b5d89bf8cb 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -745,6 +745,22 @@ enum kfd_mmio_remap { KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, }; +struct kfd_ioctl_ipc_export_handle_args { + __u64 handle; /* to KFD */ + __u32 share_handle[4]; /* from KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + +struct kfd_ioctl_ipc_import_handle_args { + __u64 handle; /* from KFD */ + __u64 va_addr; /* to KFD */ + __u64 mmap_offset; /* from KFD */ + __u32 share_handle[4]; /* to KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1681,6 +1697,12 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_CREATE_PROCESS \ AMDKFD_IO(0x27) +#define AMDKFD_IOC_IPC_IMPORT_HANDLE \ + AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) + +#define AMDKFD_IOC_IPC_EXPORT_HANDLE \ + AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) + #define AMDKFD_COMMAND_START 0x01 #define AMDKFD_COMMAND_END 0x28 From 7c26ad9b97dd09f1d0b462af2c6f66546ba511f2 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 01:26:36 -0400 Subject: [PATCH 0419/2070] drm/amdkfd: Add new GPU debugging API This is a completely new debug API that allows a debugger in a separate process to control wave execution, receive asynchronous notifications of events and query queue status. Change-Id: I765b39ebbd4ceb8a75c64c8a1ee24ab043c40330 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++++++++ .../drm/amd/include/asic_reg/gc/gc_10_1_0_default.h | 7 +++++++ drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 +++++ include/uapi/linux/kfd_ioctl.h | 10 ++++++++++ 5 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 804851632c4c8..805dfd6d6f95e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -2394,7 +2395,6 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, if (retval) goto out; } - retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); if (retval) goto out; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4ce2a26a96aae..9fc6afeec1ee2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1140,6 +1140,14 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); +/* Process device data iterator */ +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p); +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, + struct kfd_process_device *pdd); +bool kfd_has_process_device_data(struct kfd_process *p); + /* PASIDs */ int kfd_pasid_init(void); void kfd_pasid_exit(void); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h index 320e1ee5df1a9..2050888f7ec6d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h @@ -2616,6 +2616,13 @@ #define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f +#define mmSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_MASK_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA0_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA1_DEFAULT 0x00000000 #define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 9aba8596faa7e..ed07155666ab6 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -204,6 +204,11 @@ struct tile_config { * IH ring entry. This function allows the KFD ISR to get the VMID * from the fault status register as early as possible. * + * @get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values + * + * @build_grace_period_packet_info: build a IQ_WAUT_TIME2 reg value with an + * updated grace period value. + * * @get_cu_occupancy: Function pointer that returns to caller the number * of wave fronts that are in flight for all of the queues of a process * as identified by its pasid. It is important to note that the value diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 890b5d89bf8cb..1ec9537da6e7b 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -254,6 +254,16 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff +struct kfd_ioctl_dbg_trap_args { + __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ + __u32 pid; /* to KFD */ + __u32 gpu_id; /* to KFD */ + __u32 op; /* to KFD */ + __u32 data1; /* to KFD */ + __u32 data2; /* to KFD */ + __u32 data3; /* to KFD */ +}; + /* Matching HSA_EVENTTYPE */ #define KFD_IOC_EVENT_SIGNAL 0 #define KFD_IOC_EVENT_NODECHANGE 1 From 786ac12c4b516665131e87edd079e82450a2ebb1 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:23:36 -0400 Subject: [PATCH 0420/2070] drm/amdkfd: Add RDMA and PeerDirect support Both are interfaces between kernel drivers for direct peer-memory access between different devices, e.g. NICs and GPUs. The PeerDirect API is defined by Mellanox and supported by their non-upstream NIC driver. RDMA is an AMD interface and provides the implementation underneath the PeerDirect wrapper. It currently has no external users. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 22 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 206 ++++- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_module.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 702 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 +- drivers/gpu/drm/amd/dkms/sources | 1 + include/drm/amd_rdma.h | 78 ++ 9 files changed, 1021 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c create mode 100644 include/drm/amd_rdma.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 995c2d2072f2c..6e160ca5a5e44 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -334,6 +334,28 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, struct dma_fence __rcu **ef); int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, struct kfd_vm_fault_info *info); + +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags); +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo); +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg); +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sg); + +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, + struct dma_buf *dmabuf, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index b106e58004456..d598791a9f440 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1502,7 +1502,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, * * Return: ZERO if successful in pinning, Non-Zero in case of error. */ -static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) { int ret = 0; @@ -1545,7 +1545,7 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their * PIN count decremented. Calls to UNPIN must balance calls to PIN */ -static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) { int ret = 0; @@ -2357,6 +2357,208 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, return 0; } +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags) +{ + struct amdgpu_bo *bo = mem->bo; + + if (flags) + *flags = mem->alloc_flags; + drm_gem_object_get(&bo->tbo.base); + return bo; +} + +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) +{ + drm_gem_object_put(&bo->tbo.base); +} + +#define AMD_GPU_PAGE_SHIFT PAGE_SHIFT +#define AMD_GPU_PAGE_SIZE (_AC(1, UL) << AMD_GPU_PAGE_SHIFT) + +/** + * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance + * of scatter gather table (sg_table) for BO's that represent MMIO or + * DOORBELL memory. An example of this is the MMIO BO that is used to + * surface HDP registers. + * + * @note: Per current design and implementation MMIO or DOORBELL BO's + * use only one scatterlist node in their sg_table. This is because + * the size of backing memory is relatively small (e.g. 4096 bytes + * for MMIO BO surfacing HDP registers). Implementation of this method + * relies on this design choice. + * + * The method does the following: + * Acquire address to use in building scatterlist nodes + * Acquire size of memory to use in building scatterlist nodes + * Invoke DMA Map service to obtain DMA'able address + * Access sg_table construction service with above parameters + * Return the handle of scatter gather table + * + * @adev: GPU device whose MMIO address needs to be exported + * @bo: Buffer object representing MMIO/DOORBELL memory e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access BO's memory + * @dir: Direction of data movement from peer PCIe devices perspective + * + * @sgt: Output parameter that is built and returned + * + * Return: zero if successful, non-zero otherwise + * + * @FIXME: This will only work as long as bo->tbo.sg->sgl->dma_address + * is not a DMA address but a physical BAR address. This will be reworked + * later when we add DMA mapping support for doorbell and MMIO BOs + */ +static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **sgt) +{ + dma_addr_t dma_addr; + s32 size, ret; + u64 addr; + + /* Acquire the address of MMIO or DOORBELL BO being + * exported. By policy the entire backing memory is + * encapsulated in one scatterlist node + */ + size = bo->tbo.sg->sgl->length; + addr = bo->tbo.sg->sgl->dma_address; + pr_debug("MMIO/Doorbell address being exported: %llx\n", addr); + + /* DMA map the acquired address - MMIO or DOORBELL */ + dma_addr = dma_map_resource(dma_dev, addr, size, + dir, DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(dma_dev, dma_addr); + if (ret) + return ret; + + /* Update output parameter with a new sg_table */ + pr_debug("MMIO/Doorbell BO size: %d\n", size); + pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); + *sgt = create_doorbell_sg(dma_addr, size); + return 0; +} + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + struct sg_table *sg = NULL; + struct scatterlist *s; + struct page **pages; + uint64_t offset_in_page; + unsigned int page_size; + unsigned int cur_page; + unsigned int chunks; + unsigned int idx; + int ret; + + /* Determine access does not cross memory boundary */ + if (size + offset > amdgpu_bo_size(bo)) + return -EFAULT; + + /* For GPU memory use VRAM Mgr to build SG Table */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + ret = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, offset, + size, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_sg) that is used to surface + * resources from MMIO address space. The allocation flag of + * BO fall in MMIO_REMAP / DOORBELL domain + */ + if (bo->tbo.type == ttm_bo_type_sg && + ((flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + ret = get_sg_table_of_mmio_or_doorbel_bo(bo, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_device) that is used to surface + * memory resources from GPU's GART aperture. The allocation flag + * of BO falls in GTT domain i.e. the physical backing memory is + * part of system memory. Construction of SG Table proceeds + * as follows: + * + * Allocate memory for SG Table + * Determine number of Scatterlist node in table + * Logic uses one Scatterlist node per PAGE_SIZE + * Allocate memory for Scatterlist nodes + * Initialize Scatterlist nodes to zero length + * Walk down system memory pointed by BO while + * Updating Scatterlist nodes with system memory info + */ + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) { + ret = -ENOMEM; + goto out; + } + + page_size = PAGE_SIZE; + offset_in_page = offset & (page_size - 1); + chunks = (size + offset_in_page + page_size - 1) + / page_size; + + ret = sg_alloc_table(sg, chunks, GFP_KERNEL); + if (unlikely(ret)) + goto out; + + for_each_sgtable_sg(sg, s, idx) + s->length = 0; + + pages = bo->tbo.ttm->pages; + cur_page = offset / page_size; + for_each_sg(sg->sgl, s, sg->orig_nents, idx) { + uint64_t chunk_size, length; + + chunk_size = page_size - offset_in_page; + length = min(size, chunk_size); + + sg_set_page(s, pages[cur_page], length, offset_in_page); + s->dma_address = page_to_phys(pages[cur_page]); + s->dma_length = length; + + size -= length; + offset_in_page = 0; + cur_page++; + } + + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + + *ret_sg = sg; + return 0; + +out_of_range: + sg_free_table(sg); +out: + kfree(sg); + *ret_sg = NULL; + return ret; +} + +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sgt) +{ + /* Unmap GPU device memory */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + amdgpu_vram_mgr_free_sgt(dma_dev, dir, sgt); + return; + } + + /* Unmap system memory */ + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(sgt); +} + static int import_obj_create(struct amdgpu_device *adev, struct dma_buf *dma_buf, struct drm_gem_object *obj, diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 3fb8ab2bba63d..638a6e1bcd128 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -61,6 +61,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_int_process_v12_1.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ + $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_debug.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 0b86c763d76b2..2434619cddc1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -61,6 +61,8 @@ static int kfd_init(void) if (err < 0) goto err_create_wq; + kfd_init_peer_direct(); + /* Ignore the return value, so that we can continue * to init the KFD, even if procfs isn't craated */ @@ -83,6 +85,7 @@ static int kfd_init(void) static void kfd_exit(void) { kfd_cleanup_processes(); + kfd_close_peer_direct(); kfd_process_destroy_wq(); kfd_debugfs_fini(); kfd_procfs_shutdown(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c new file mode 100644 index 0000000000000..27fe96b788de6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -0,0 +1,702 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/* NOTE: + * + * This file contains logic to dynamically detect and enable PeerDirect + * suppor. PeerDirect support is delivered e.g. as part of OFED + * from Mellanox. Because we are not able to rely on the fact that the + * corresponding OFED will be installed we should: + * - copy PeerDirect definitions locally to avoid dependency on + * corresponding header file + * - try dynamically detect address of PeerDirect function + * pointers. + * + * If dynamic detection failed then PeerDirect support should be + * enabled using the standard PeerDirect bridge driver from: + * https://github.com/RadeonOpenCompute/ROCnRDMA + * + * + * Logic to support PeerDirect relies only on official public API to be + * non-intrusive as much as possible. + * + **/ + +#include +#include +#include +#include +#include +#include + +#include "kfd_priv.h" + +/* ----------------------- PeerDirect interface ------------------------------*/ + +/* + * Copyright (c) 2013, Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#define IB_PEER_MEMORY_NAME_MAX 64 +#define IB_PEER_MEMORY_VER_MAX 16 + +struct peer_memory_client { + char name[IB_PEER_MEMORY_NAME_MAX]; + char version[IB_PEER_MEMORY_VER_MAX]; + /* acquire return code: 1-mine, 0-not mine */ + int (*acquire)(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, + void **client_context); + int (*get_pages)(unsigned long addr, + size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context); + int (*dma_map)(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap); + int (*dma_unmap)(struct sg_table *sg_head, void *client_context, + struct device *dma_device); + void (*put_pages)(struct sg_table *sg_head, void *client_context); + unsigned long (*get_page_size)(void *client_context); + void (*release)(void *client_context); + void* (*get_context_private_data)(u64 peer_id); + void (*put_context_private_data)(void *context); +}; + +typedef int (*invalidate_peer_memory)(void *reg_handle, + void *core_context); + +void *ib_register_peer_memory_client(struct peer_memory_client *peer_client, + invalidate_peer_memory *invalidate_callback); +void ib_unregister_peer_memory_client(void *reg_handle); + + +/*------------------- PeerDirect bridge driver ------------------------------*/ + +#define AMD_PEER_BRIDGE_DRIVER_VERSION "1.0" +#define AMD_PEER_BRIDGE_DRIVER_NAME "amdkfd" + +static char rdma_name[] = "AMD RDMA"; + + +static void* (*pfn_ib_register_peer_memory_client)(struct peer_memory_client + *peer_client, + invalidate_peer_memory + *invalidate_callback); + +static void (*pfn_ib_unregister_peer_memory_client)(void *reg_handle); + +static void *ib_reg_handle; + +struct amd_mem_context { + uint64_t va; + uint64_t size; + unsigned long offset; + struct amdgpu_bo *bo; + struct kfd_dev *dev; + + struct sg_table *pages; + struct device *dma_dev; + + + /* Context received from PeerDirect call */ + void *core_context; + + pid_t pid; + uint32_t flags; +}; + +/* Workaround: Mellanox peerdirect driver expects sg lists at + * page granularity. This causes failures when an application tries + * to register size < PAGE_SIZE or addr starts at some offset. Fix + * it by aligning the size to page size and addr to page boundary. + */ +static void align_addr_size(unsigned long *addr, size_t *size) +{ + unsigned long end = ALIGN(*addr + *size, PAGE_SIZE); + + *addr = ALIGN_DOWN(*addr, PAGE_SIZE); + *size = end - *addr; +} + +static int amd_acquire(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, void **client_context) +{ + struct kfd_process *p; + struct kfd_bo *buf_obj; + struct amd_mem_context *mem_context; + + if (peer_mem_name == rdma_name) { + p = peer_mem_private_data; + } else { + p = kfd_get_process(current); + if (!p) { + pr_debug("Not a KFD process\n"); + return 0; + } + } + + align_addr_size(&addr, &size); + + mutex_lock(&p->mutex); + buf_obj = kfd_process_find_bo_from_interval(p, addr, + addr + size - 1); + if (!buf_obj) { + pr_debug("Cannot find a kfd_bo for the range\n"); + goto out_unlock; + } + + /* Initialize context used for operation with given address */ + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (!mem_context) + goto out_unlock; + + mem_context->pid = p->lead_thread->pid; + + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", + addr, size, mem_context->pid); + + mem_context->va = addr; + mem_context->size = size; + mem_context->offset = addr - buf_obj->it.start; + + mem_context->bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, + &mem_context->flags); + mem_context->dev = buf_obj->dev; + + mutex_unlock(&p->mutex); + + pr_debug("Client context: 0x%p\n", mem_context); + + /* Return pointer to allocated context */ + *client_context = mem_context; + + /* Return 1 to inform that this address which will be handled + * by AMD GPU driver + */ + return 1; + +out_unlock: + mutex_unlock(&p->mutex); + return 0; +} + +static int amd_get_pages(unsigned long addr, size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context) +{ + int ret; + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + align_addr_size(&addr, &size); + + pr_debug("addr: %#lx, size: %#lx, core_context: 0x%p\n", + addr, size, core_context); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d\n", mem_context->pid); + + if (addr != mem_context->va) { + pr_warn("Context address (%#llx) is not the same\n", + mem_context->va); + return -EINVAL; + } + + if (size != mem_context->size) { + pr_warn("Context size (%#llx) is not the same\n", + mem_context->size); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo); + if (ret) { + pr_err("Pinning of buffer failed.\n"); + return ret; + } + + /* Mark the device as active */ + kfd_inc_compute_active(mem_context->dev); + + mem_context->core_context = core_context; + + return 0; +} + + +static int amd_dma_map(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap) +{ + struct sg_table *sg_table_tmp; + int ret; + + /* + * NOTE/TODO: + * We could have potentially three cases for real memory + * location: + * - all memory in the local + * - all memory in the system (RAM) + * - memory is spread (s/g) between local and system. + * + * In the case of all memory in the system we could use + * iommu driver to build DMA addresses but not in the case + * of local memory because currently iommu driver doesn't + * deal with local/device memory addresses (it requires "struct + * page"). + * + * Accordingly returning assumes that iommu funcutionality + * should be disabled so we can assume that sg_table already + * contains DMA addresses. + * + */ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Build sg_table for buffer being exported, including DMA mapping */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table( + mem_context->dev->kgd, mem_context->bo, mem_context->flags, + mem_context->offset, mem_context->size, + dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); + if (ret) { + pr_err("Building of sg_table failed\n"); + return ret; + } + + /* Maintain a copy of the handle to sg_table */ + mem_context->pages = sg_table_tmp; + mem_context->dma_dev = dma_device; + + /* Copy information about previosly allocated sg_table */ + *sg_head = *mem_context->pages; + + /* Return number of pages */ + *nmap = mem_context->pages->nents; + + return ret; +} + +static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, + struct device *dma_device) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_table: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo || !mem_context->dma_dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Release the mapped pages of buffer */ + amdgpu_amdkfd_gpuvm_put_sg_table(mem_context->bo, + mem_context->dma_dev, + DMA_BIDIRECTIONAL, + mem_context->pages); + mem_context->pages = NULL; + + return 0; +} + +static void amd_put_pages(struct sg_table *sg_head, void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_unpin_bo(mem_context->bo); + kfd_dec_compute_active(mem_context->dev); +} + +static unsigned long amd_get_page_size(void *client_context) +{ + return PAGE_SIZE; +} + +static void amd_release(void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p\n", client_context); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_put_bo_ref(mem_context->bo); + + kfree(mem_context); +} + + +static struct peer_memory_client amd_mem_client = { + .acquire = amd_acquire, + .get_pages = amd_get_pages, + .dma_map = amd_dma_map, + .dma_unmap = amd_dma_unmap, + .put_pages = amd_put_pages, + .get_page_size = amd_get_page_size, + .release = amd_release, + .get_context_private_data = NULL, + .put_context_private_data = NULL, +}; + +/** Initialize PeerDirect interface with RDMA Network stack. + * + * Because network stack could potentially be loaded later we check + * presence of PeerDirect when HSA process is created. If PeerDirect was + * already initialized we do nothing otherwise try to detect and register. + */ +void kfd_init_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect support was already initialized\n"); + return; + } + + pr_debug("Try to initialize PeerDirect support\n"); + + pfn_ib_register_peer_memory_client = + (void *(*)(struct peer_memory_client *, + invalidate_peer_memory *)) + symbol_request(ib_register_peer_memory_client); + + pfn_ib_unregister_peer_memory_client = (void (*)(void *)) + symbol_request(ib_unregister_peer_memory_client); + + if (!pfn_ib_register_peer_memory_client || + !pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect interface was not detected\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + strcpy(amd_mem_client.name, AMD_PEER_BRIDGE_DRIVER_NAME); + strcpy(amd_mem_client.version, AMD_PEER_BRIDGE_DRIVER_VERSION); + + ib_reg_handle = pfn_ib_register_peer_memory_client(&amd_mem_client, NULL); + + if (!ib_reg_handle) { + pr_err("Cannot register peer memory client\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + pr_info("PeerDirect support was initialized successfully\n"); +} + +/** + * Close connection with PeerDirect interface with RDMA Network stack. + * + */ +void kfd_close_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + if (ib_reg_handle) + pfn_ib_unregister_peer_memory_client(ib_reg_handle); + + symbol_put(ib_unregister_peer_memory_client); + } + + if (pfn_ib_register_peer_memory_client) + symbol_put(ib_register_peer_memory_client); + + + /* Reset pointers to be safe */ + pfn_ib_unregister_peer_memory_client = NULL; + pfn_ib_register_peer_memory_client = NULL; + ib_reg_handle = NULL; +} + +/* ------------------------- AMD RDMA wrapper --------------------------------*/ + +#include "drm/amd_rdma.h" + +struct rdma_p2p_data { + struct amd_p2p_info p2p_info; + void (*free_callback)(void *client_priv); + void *client_priv; +}; + +/** + * This function makes the pages underlying a range of GPU virtual memory + * accessible for DMA operations from another PCIe device + * + * \param address - The start address in the Unified Virtual Address + * space in the specified process + * \param length - The length of requested mapping + * \param pid - Pointer to structure pid to which address belongs. + * Could be NULL for current process address space. + * \param p2p_data - On return: Pointer to structure describing + * underlying pages/locations + * \param free_callback - Pointer to callback which will be called when access + * to such memory must be stopped immediately: Memory + * was freed, GECC events, etc. + * Client should immediately stop any transfer + * operations and returned as soon as possible. + * After return all resources associated with address + * will be release and no access will be allowed. + * \param client_priv - Pointer to be passed as parameter on + * 'free_callback; + * + * \return 0 if operation was successful + */ +static int rdma_get_pages(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv) +{ + struct rdma_p2p_data *p2p_data; + struct kfd_process *p; + struct sg_table sg_head; + struct amd_mem_context *mem_context; + int nmap; + int r; + + p2p_data = kzalloc(sizeof(*p2p_data), GFP_KERNEL); + if (!p2p_data) + return -ENOMEM; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("pid lookup failed\n"); + r = -ESRCH; + goto err_lookup_process; + } + + r = amd_acquire(address, length, p, rdma_name, (void **)&mem_context); + kfd_unref_process(p); + if (r == 0) { + pr_debug("acquire failed: %d\n", r); + goto err_acquire; + } + + r = amd_get_pages(address, length, 1, 0, &sg_head, + mem_context, p2p_data); + if (r) { + pr_debug("get_pages failed: %d\n", r); + goto err_get_pages; + } + + r = amd_dma_map(&sg_head, mem_context, dma_dev, 0, &nmap); + if (r) { + pr_debug("dma_map failed: %d\n", r); + goto err_dma_map; + } + + + p2p_data->free_callback = free_callback; + p2p_data->client_priv = client_priv; + p2p_data->p2p_info.va = address; + p2p_data->p2p_info.size = length; + p2p_data->p2p_info.pid = pid; + p2p_data->p2p_info.pages = mem_context->pages; + p2p_data->p2p_info.priv = mem_context; + + *amd_p2p_data = &p2p_data->p2p_info; + + return 0; + +err_dma_map: + amd_put_pages(&sg_head, mem_context); +err_get_pages: + amd_release(mem_context); +err_acquire: +err_lookup_process: + kfree(p2p_data); + + return r; +} + +/** + * + * This function release resources previously allocated by get_pages() call. + * + * \param p_p2p_data - A pointer to pointer to amd_p2p_info entries + * allocated by get_pages() call. + * + * \return 0 if operation was successful + */ +static int rdma_put_pages(struct amd_p2p_info **p_p2p_data) +{ + struct rdma_p2p_data *p2p_data = + container_of(*p_p2p_data, struct rdma_p2p_data, p2p_info); + int r; + + r = amd_dma_unmap(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv, + NULL); + if (r) + return r; + amd_put_pages(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv); + amd_release(p2p_data->p2p_info.priv); + kfree(p2p_data); + + *p_p2p_data = NULL; + + return 0; +} + +/** + * Check if given address belongs to GPU address space. + * + * \param address - Address to check + * \param pid - Process to which given address belongs. + * Could be NULL if current one. + * + * \return 0 - This is not GPU address managed by AMD driver + * 1 - This is GPU address managed by AMD driver + */ +static int rdma_is_gpu_address(uint64_t address, struct pid *pid) +{ + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("Could not find the process\n"); + return 0; + } + + buf_obj = kfd_process_find_bo_from_interval(p, address, address); + + kfd_unref_process(p); + if (!buf_obj) + return 0; + + return 1; +} + +/** + * Return the single page size to be used when building scatter/gather table + * for given range. + * + * \param address - Address + * \param length - Range length + * \param pid - Process id structure. Could be NULL if current one. + * \param page_size - On return: Page size + * + * \return 0 if operation was successful + */ +static int rdma_get_page_size(uint64_t address, uint64_t length, + struct pid *pid, unsigned long *page_size) +{ + /* + * As local memory is always consecutive, we can assume the local + * memory page size to be arbitrary. + * Currently we assume the local memory page size to be the same + * as system memory, which is 4KB. + */ + *page_size = PAGE_SIZE; + + return 0; +} + +/** + * Singleton object: rdma interface function pointers + */ +static const struct amd_rdma_interface rdma_ops = { + .get_pages = rdma_get_pages, + .put_pages = rdma_put_pages, + .is_gpu_address = rdma_is_gpu_address, + .get_page_size = rdma_get_page_size +}; + +/** + * amdkfd_query_rdma_interface - Return interface (function pointers table) for + * rdma interface + * + * + * \param interace - OUT: Pointer to interface + * + * \return 0 if operation was successful. + */ +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **ops) +{ + *ops = &rdma_ops; + + return 0; +} +EXPORT_SYMBOL(amdkfd_query_rdma_interface); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9fc6afeec1ee2..76bc734f4b179 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -395,7 +395,6 @@ struct kfd_bo { void *mem; struct interval_tree_node it; struct kfd_dev *dev; - struct list_head cb_data_head; struct kfd_ipc_obj *kfd_ipc_obj; /* page-aligned VA address */ uint64_t cpuva; @@ -1605,6 +1604,10 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +/* PeerDirect support */ +void kfd_init_peer_direct(void); +void kfd_close_peer_direct(void); + /* IPC Support */ int kfd_ipc_init(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 312585234f65e..5b98f4640e662 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1068,7 +1068,8 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); } - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, + run_rdma_free_callback(buf_obj); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } @@ -1675,6 +1676,10 @@ struct kfd_process *create_process(const struct task_struct *thread, bool primar kfd_unref_process(process); get_task_struct(process->lead_thread); + /* If PeerDirect interface was not detected try to detect it again + * in case if network driver was loaded later. + */ + kfd_init_peer_direct(); INIT_WORK(&process->debug_event_workarea, debug_event_write_work_handler); return process; @@ -1906,8 +1911,6 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; - INIT_LIST_HEAD(&buf_obj->cb_data_head); - handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); if (handle < 0) diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 3470a58a43676..a1b74441203de 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -24,6 +24,7 @@ include/drm/gpu_scheduler.h include/drm/ include/drm/amd_asic_type.h include/drm/ include/drm/spsc_queue.h include/drm/ include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +include/drm/amd_rdma.h include/drm/ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ diff --git a/include/drm/amd_rdma.h b/include/drm/amd_rdma.h new file mode 100644 index 0000000000000..99682afae6754 --- /dev/null +++ b/include/drm/amd_rdma.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2015-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* @file This file defined kernel interfaces to communicate with amdkfd */ + +#ifndef AMD_RDMA_H_ +#define AMD_RDMA_H_ + +/* API versions: + * 1.0 Original API until ROCm 4.1, AMD_RDMA_MAJOR/MINOR undefined + * 2.0 Added IOMMU (dma-mapping) support, removed p2p_info.kfd_proc + * Introduced AMD_RDMA_MAJOR/MINOR version definition + */ +#define AMD_RDMA_MAJOR 2 +#define AMD_RDMA_MINOR 0 + +/** + * Structure describing information needed to P2P access from another device + * to specific location of GPU memory + */ +struct amd_p2p_info { + uint64_t va; /**< Specify user virt. address + * which this page table + * described + */ + uint64_t size; /**< Specify total size of + * allocation + */ + struct pid *pid; /**< Specify process pid to which + * virtual address belongs + */ + struct sg_table *pages; /**< Specify DMA/Bus addresses */ + void *priv; /**< Pointer set by AMD kernel + * driver + */ +}; + +/** + * Structure providing function pointers to support rdma/p2p requirements. + * to specific location of GPU memory + */ +struct amd_rdma_interface { + int (*get_pages)(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv); + int (*put_pages)(struct amd_p2p_info **amd_p2p_data); + int (*is_gpu_address)(uint64_t address, struct pid *pid); + int (*get_page_size)(uint64_t address, uint64_t length, struct pid *pid, + unsigned long *page_size); +}; + + +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **rdma); + + +#endif /* AMD_RDMA_H_ */ From ea051f19d268452916dd1d788656b6f1d93396b6 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:34:11 -0400 Subject: [PATCH 0421/2070] drm/amdkfd: Add module param to enable privileged queues This is useful for profiler prototyping in user mode. Change-Id: Ibb3dfedc698fadb5164637642bdd2d540cc00bd0 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 4 +++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0e7f35da6105a..7af888a99389b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -843,6 +843,14 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa int amdgpu_no_queue_eviction_on_vm_fault; MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); + +/** + * DOC: priv_cp_queues (int) + * Enable privileged mode for CP queues. Default value: 0 (off) + */ +int priv_cp_queues; +module_param(priv_cp_queues, int, 0644); +MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); #endif /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 76483d91af98b..ae53556c70899 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -31,6 +31,7 @@ #include "cik_regs.h" #include "cik_structs.h" #include "oss/oss_2_4_sh_mask.h" +#include "gca/gfx_7_2_sh_mask.h" static inline struct cik_mqd *get_mqd(void *mqd) { @@ -200,6 +201,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_pq_control |= NO_UPDATE_RPTR; + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 3622d8392cb32..167072012bd54 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -318,6 +318,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_doorbell_control |= 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; } + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index e63ef6442b358..fbce537331d75 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -226,7 +226,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } - + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 76bc734f4b179..f22be21dafb73 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -188,6 +188,11 @@ extern int debug_largebar; /* Set sh_mem_config.retry_disable on GFX v9 */ extern int amdgpu_noretry; +/* + * Enable privileged mode for all CP queues including user queues + */ +extern int priv_cp_queues; + /* Halt if HWS hang is detected */ extern int halt_if_hws_hang; From c135b5d7941df432961fe61380cb03340c369212 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:48:26 -0400 Subject: [PATCH 0422/2070] drm/amdkfd: Leave idle processes evicted This feature allows leaving processes with idle user mode queues evicted. That way more memory can be used by other processes. This is contolled by a module parameter. It's disabled by default. It needs more rigorous testing before enabling it by default. See FIXMEs below. The basic idea is to detect idle user mode queues when a process is restored after eviction. It it's found to be idle, we unmap the doorbells so the next submission from the host causes a page fault. We catch the page fault and use that to restore the process memory and the doorbells at that time. FIXME: Add check_queue_idle functions in kfd_mqd_manager_v10.c FIXME: Use READ_ONCE/WRITE_ONCE for vma->vm_private_data Change-Id: I03969b82f8fa31ac0e8593f537cc5c45ff8bc16e Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 +++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 145 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 3 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 28 ++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 47 ++++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 43 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 22 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 93 +++++++++++ 10 files changed, 411 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7af888a99389b..8fe3eb11244ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -851,6 +851,14 @@ module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_evictio int priv_cp_queues; module_param(priv_cp_queues, int, 0644); MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); + +/** + * DOC: keep_idle_process_evicted (bool) + * Keep an evicted process evicted if it is idle. Default value: false (off) + */ +bool keep_idle_process_evicted; +module_param(keep_idle_process_evicted, bool, 0444); +MODULE_PARM_DESC(keep_idle_process_evicted, "Restore evicted process only if queues are active (N = off(default), Y = on)"); #endif /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 805dfd6d6f95e..709fd518a6a0a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -157,6 +157,31 @@ void program_sh_mem_settings(struct device_queue_manager *dqm, qpd->sh_mem_bases, xcc_id); } +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + bool busy = false; + struct queue *q; + + dqm_lock(dqm); + list_for_each_entry(q, &qpd->queues_list, list) { + struct mqd_manager *mqd_mgr; + enum KFD_MQD_TYPE type; + + type = get_mqd_type_from_queue_type(q->properties.type); + mqd_mgr = dqm->mqd_mgrs[type]; + if (!mqd_mgr || !mqd_mgr->check_queue_active) + continue; + + busy = mqd_mgr->check_queue_active(q); + if (busy) + break; + } + dqm_unlock(dqm); + + return busy; +} + static void kfd_hws_hang(struct device_queue_manager *dqm) { struct device_process_node *cur; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index ef07e44916f80..a0cd2ac24253f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -308,6 +308,8 @@ unsigned int get_queues_per_pipe(struct device_queue_manager *dqm); unsigned int get_pipes_per_mec(struct device_queue_manager *dqm); unsigned int get_num_sdma_queues(struct device_queue_manager *dqm); unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm); +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); int reserve_debug_trap_vmid(struct device_queue_manager *dqm, struct qcm_process_device *qpd); int release_debug_trap_vmid(struct device_queue_manager *dqm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 05c74887fd6fd..cc97f392c90af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -103,11 +103,121 @@ void kfd_doorbell_fini(struct kfd_dev *kfd) (void **)&kfd->doorbell_kernel_ptr); } +static void kfd_doorbell_open(struct vm_area_struct *vma) +{ + /* Don't track the parent's PDD in a child process. We do set + * VM_DONTCOPY, but that can be overridden from user mode. + */ + vma->vm_private_data = NULL; +} + +static void kfd_doorbell_close(struct vm_area_struct *vma) +{ + struct kfd_process_device *pdd = vma->vm_private_data; + + if (!pdd) + return; + + mutex_lock(&pdd->qpd.doorbell_lock); + pdd->qpd.doorbell_vma = NULL; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (pdd->qpd.doorbell_mapped == 0) + pdd->qpd.doorbell_mapped = -1; + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) +{ + struct kfd_process_device *pdd = vmf->vma->vm_private_data; + + if (!pdd) + return VM_FAULT_SIGBUS; + + pr_debug("Process %d doorbell vm page fault\n", pdd->process->pasid); + + kfd_process_remap_doorbells_locked(pdd->process); + + kfd_process_schedule_restore(pdd->process); + + return VM_FAULT_NOPAGE; +} + +static const struct vm_operations_struct kfd_doorbell_vm_ops = { + .open = kfd_doorbell_open, + .close = kfd_doorbell_close, + .fault = kfd_doorbell_vm_fault, +}; + +void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + struct vm_area_struct *vma; + size_t size; + + vma = pdd->qpd.doorbell_vma; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (!vma) { + pdd->qpd.doorbell_mapped = -1; + return; + } + + pr_debug("Process %d unmapping doorbell 0x%lx\n", + process->pasid, vma->vm_start); + + size = kfd_doorbell_process_slice(pdd->dev); + zap_vma_ptes(vma, vma->vm_start, size); + pdd->qpd.doorbell_mapped = 0; +} + +void kfd_doorbell_unmap(struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->qpd.doorbell_lock); + kfd_doorbell_unmap_locked(pdd); + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +int kfd_doorbell_remap(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + phys_addr_t address; + struct vm_area_struct *vma; + size_t size; + int ret = 0; + + mutex_lock(&pdd->qpd.doorbell_lock); + if (pdd->qpd.doorbell_mapped != 0) + goto out_unlock; + + /* Calculate physical address of doorbell */ + address = kfd_get_process_doorbells(pdd); + vma = pdd->qpd.doorbell_vma; + size = kfd_doorbell_process_slice(pdd->dev); + + pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, + vma->vm_start); + + ret = vm_iomap_memory(vma, address, size); + if (ret) + pr_err("Process %d failed to remap doorbell 0x%lx\n", + process->pasid, vma->vm_start); + +out_unlock: + pdd->qpd.doorbell_mapped = 1; + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; +} + int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma) { phys_addr_t address; struct kfd_process_device *pdd; + int ret; /* * For simplicitly we only allow mapping of the entire doorbell @@ -129,20 +239,47 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("Mapping doorbell page\n" + pr_debug("Process %d mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - (unsigned long long) vma->vm_start, address, vma->vm_flags, - kfd_doorbell_process_slice(dev->kfd)); + process->pasid, (unsigned long long) vma->vm_start, + address, vma->vm_flags, kfd_doorbell_process_slice(dev)); + pdd = kfd_get_process_device_data(dev, process); + if (WARN_ON_ONCE(!pdd)) + return 0; - return io_remap_pfn_range(vma, + mutex_lock(&pdd->qpd.doorbell_lock); + + ret = io_remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT, kfd_doorbell_process_slice(dev->kfd), vma->vm_page_prot); + + if (!ret && keep_idle_process_evicted) { + vma->vm_ops = &kfd_doorbell_vm_ops; + vma->vm_private_data = pdd; + pdd->qpd.doorbell_vma = vma; + + /* If process is evicted before the first queue is created, + * process will be restored by the page fault when the + * doorbell is accessed the first time + */ + if (pdd->qpd.doorbell_mapped == -1) { + pr_debug("Process %d evicted, unmapping doorbell\n", + process->pasid); + kfd_doorbell_unmap_locked(pdd); + } else { + pdd->qpd.doorbell_mapped = 1; + } + } + + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 2429d278ef0eb..a2c487b9bacd4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -102,6 +102,8 @@ struct mqd_manager { u32 *ctl_stack_used_size, u32 *save_area_used_size); + bool (*check_queue_active)(struct queue *q); + void (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, uint32_t *ctl_stack_size); void (*checkpoint_mqd)(struct mqd_manager *mm, @@ -115,7 +117,6 @@ struct mqd_manager { const void *mqd_src, const void *ctl_stack_src, const u32 ctl_stack_size); - #if defined(CONFIG_DEBUG_FS) int (*debugfs_show_mqd)(struct seq_file *m, void *data); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index ae53556c70899..ec2209928c14d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -43,6 +43,31 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) return (struct cik_sdma_rlc_registers *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_sdma_rlc_registers *m = get_sdma_mqd(q->mqd); + + rptr = m->sdma_rlc_rb_rptr; + wptr = m->sdma_rlc_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -408,6 +433,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; mqd->mqd_size = sizeof(struct cik_mqd); @@ -423,6 +449,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct cik_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -452,6 +479,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 167072012bd54..a61b04daa08c4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -59,6 +59,49 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) return (struct v9_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t rptr_hi, wptr_hi; + struct v9_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + rptr_hi = m->sdmax_rlcx_rb_rptr_hi; + wptr_hi = m->sdmax_rlcx_rb_wptr_hi; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("rptr_hi=%d, wptr_hi=%d\n", rptr_hi, wptr_hi); + + return (rptr != wptr || rptr_hi != wptr_hi); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct v9_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr_lo % q->properties.queue_size; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo, uint32_t inst) { @@ -974,6 +1017,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->allocate_mqd = allocate_mqd; mqd->free_mqd = kfd_free_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = mqd_stride_v9; @@ -1005,6 +1049,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->free_mqd = free_mqd_hiq_sdma; mqd->update_mqd = update_mqd; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -1033,6 +1078,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; @@ -1046,6 +1092,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct v9_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index fbce537331d75..391a19d95c2c2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -45,6 +45,45 @@ static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) return (struct vi_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct vi_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct vi_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -464,6 +503,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; mqd->get_wave_state = get_wave_state; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; @@ -480,6 +520,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -495,6 +536,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -509,6 +551,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct vi_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f22be21dafb73..8b600ca431f8d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -207,6 +207,11 @@ extern int queue_preemption_timeout_ms; */ extern int amdgpu_no_queue_eviction_on_vm_fault; +/* + * Restore evicted process only if queues are active + */ +extern bool keep_idle_process_evicted; + /* Enable eviction debug messages */ extern bool debug_evictions; @@ -737,6 +742,17 @@ struct qcm_process_device { /* bitmap for dynamic doorbell allocation from the bo */ unsigned long *doorbell_bitmap; + /* doorbell user mmap vma */ + struct vm_area_struct *doorbell_vma; + /* lock to serialize doorbell unmap and remap */ + struct mutex doorbell_lock; + + /* Indicate if doorbell is mapped or unmapped + * -1 means doorbells need to be unmapped because queue is evicted + * 0 means doorbells are unmapped + * 1 means doorbells are mapped + */ + int doorbell_mapped; }; /* KFD Memory Eviction */ @@ -748,6 +764,9 @@ struct qcm_process_device { /* Approx. time before evicting the process again */ #define PROCESS_ACTIVE_TIME_MS 10 +void kfd_process_schedule_restore(struct kfd_process *p); +int kfd_process_remap_doorbells_locked(struct kfd_process *p); + /* 8 byte handle containing GPU ID in the most significant 4 bytes and * idr_handle in the least significant 4 bytes */ @@ -986,6 +1005,7 @@ struct kfd_process { * restored after an eviction */ unsigned long last_restore_timestamp; + unsigned long last_evict_timestamp; /* Indicates device process is debug attached with reserved vmid. */ bool debug_trap_enabled; @@ -1164,6 +1184,8 @@ int kfd_doorbell_init(struct kfd_dev *kfd); void kfd_doorbell_fini(struct kfd_dev *kfd); int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma); +void kfd_doorbell_unmap(struct kfd_process_device *pdd); +int kfd_doorbell_remap(struct kfd_process_device *pdd); void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, unsigned int *doorbell_off); void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 5b98f4640e662..9f2041df0f533 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1136,6 +1136,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) get_order(KFD_CWSR_TBA_TMA_SIZE)); idr_destroy(&pdd->alloc_idr); + mutex_destroy(&pdd->qpd.doorbell_lock); kfd_free_process_doorbells(pdd->dev->kfd, pdd); @@ -1733,6 +1734,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->qpd.pqm = &p->pqm; pdd->qpd.evicted = 0; pdd->qpd.mapped_gws_queue = false; + mutex_init(&pdd->qpd.doorbell_lock); pdd->process = p; pdd->bound = PDD_UNBOUND; pdd->already_dequeued = false; @@ -2200,6 +2202,95 @@ static bool signal_eviction_fence(struct kfd_process *p) return ret; } +void kfd_process_schedule_restore(struct kfd_process *p) +{ + int ret; + unsigned long evicted_jiffies; + unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); + + /* wait at least PROCESS_RESTORE_TIME_MS before attempting to restore + */ + evicted_jiffies = get_jiffies_64() - p->last_evict_timestamp; + if (delay_jiffies > evicted_jiffies) + delay_jiffies -= evicted_jiffies; + else + delay_jiffies = 0; + + pr_debug("Process %d schedule restore work\n", p->pasid); + ret = queue_delayed_work(kfd_restore_wq, &p->restore_work, + delay_jiffies); + WARN(!ret, "Schedule restore work failed\n"); +} + +static void kfd_process_unmap_doorbells(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + struct mm_struct *mm = p->mm; + + mmap_write_lock(mm); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + kfd_doorbell_unmap(pdd); + + mmap_write_unlock(mm); +} + +int kfd_process_remap_doorbells_locked(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + int ret = 0; + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + ret = kfd_doorbell_remap(pdd); + + return ret; +} + +static int kfd_process_remap_doorbells(struct kfd_process *p) +{ + struct mm_struct *mm = p->mm; + int ret = 0; + + mmap_write_lock(mm); + ret = kfd_process_remap_doorbells_locked(p); + mmap_write_unlock(mm); + + return ret; +} + +/** + * kfd_process_unmap_doorbells_if_idle - Check if queues are active + * + * Returns true if queues are idle, and unmap doorbells. + * Returns false if queues are active + */ +static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + bool busy = false; + + if (!keep_idle_process_evicted) + return false; + + /* Unmap doorbell first to avoid race conditions. Otherwise while the + * second queue is checked, the first queue may get more work, but we + * won't detect that since it has been checked + */ + kfd_process_unmap_doorbells(p); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); + if (busy) + break; + } + + /* Remap doorbell if process queue is not idle */ + if (busy) + kfd_process_remap_doorbells(p); + + return !busy; +} + static void evict_process_worker(struct work_struct *work) { int ret; @@ -2213,6 +2304,8 @@ static void evict_process_worker(struct work_struct *work) */ p = container_of(dwork, struct kfd_process, eviction_work); + p->last_evict_timestamp = get_jiffies_64(); + pr_debug("Started evicting process pid %d\n", p->lead_thread->pid); ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { From 614cbd1f38569a55272f31f1be694864f9bc57bf Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:06:45 -0400 Subject: [PATCH 0423/2070] drm/amdgpu: Workaround incorrect VRAM width reported on Fiji Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 +++++ include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 1d5bd90ac57f7..086bf24f5db8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -555,6 +555,11 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) break; } adev->gmc.vram_width = numchan * chansize; + /* FIXME: The above calculation is outdated. + * For HBM provide a temporary fix + */ + if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) + adev->gmc.vram_width = AMDGPU_VRAM_TYPE_HBM_WIDTH; } /* size in MB on si */ tmp = RREG32(mmCONFIG_MEMSIZE); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index ce848c2d569c8..87858adf780ba 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1500,6 +1500,8 @@ struct drm_amdgpu_info_vbios { #define AMDGPU_VRAM_TYPE_HBM3E 13 #define AMDGPU_VRAM_TYPE_HBM4 14 +#define AMDGPU_VRAM_TYPE_HBM_WIDTH 4096 + struct drm_amdgpu_info_device { /** PCI Device ID */ __u32 device_id; From 5560710e890ffd6ead9eadc0b150e7e872650c87 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:14:27 -0400 Subject: [PATCH 0424/2070] drm/amdkfd: Proof of concept for KFD traces Add tracing to a few KFD functions as a proof of concept. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++ drivers/gpu/drm/amd/amdkfd/kfd_trace.c | 26 ++++ drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 151 +++++++++++++++++++++++ 5 files changed, 195 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_trace.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_trace.h diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 638a6e1bcd128..7391eb56d0b8d 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -63,6 +63,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_crat.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 61db202390891..6e00d1c0fd272 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -40,6 +40,8 @@ #include "kfd_device_queue_manager.h" #include "kfd_svm.h" #include "kfd_ipc.h" +#include "kfd_trace.h" + #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -1277,6 +1279,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, int i; uint32_t *devices_arr = NULL; + trace_kfd_map_memory_to_gpu_start(p); if (!args->n_devices) { pr_debug("Device IDs array empty\n"); return -EINVAL; @@ -1370,6 +1373,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, } kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Success"); return err; get_process_device_data_failed: @@ -1380,6 +1385,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, mutex_unlock(&p->mutex); copy_from_user_failed: kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Failed"); return err; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 9f2041df0f533..7780d9bfc08e3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -43,6 +43,7 @@ struct mm_struct; #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" @@ -2303,6 +2304,7 @@ static void evict_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, eviction_work); + trace_kfd_evict_process_worker_start(p); p->last_evict_timestamp = get_jiffies_64(); @@ -2321,6 +2323,7 @@ static void evict_process_worker(struct work_struct *work) pr_debug("Finished evicting process pid %d\n", p->lead_thread->pid); } else pr_err("Failed to evict queues of process pid %d\n", p->lead_thread->pid); + trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success"); } static int restore_process_helper(struct kfd_process *p) @@ -2336,6 +2339,7 @@ static int restore_process_helper(struct kfd_process *p) } ret = kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? "Failed" : "Success"); if (!ret) pr_debug("Finished restoring process pid %d\n", p->lead_thread->pid); @@ -2359,6 +2363,7 @@ static void restore_process_worker(struct work_struct *work) */ p = container_of(dwork, struct kfd_process, restore_work); pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); + trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. * Otherwise this would have to be set by KGD (restore_process_bos) @@ -2379,6 +2384,11 @@ static void restore_process_worker(struct work_struct *work) if (mod_delayed_work(kfd_restore_wq, &p->restore_work, msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? + "Rescheduled restore" : + "Failed to reschedule restore"); + } else { + trace_kfd_restore_process_worker_end(p, "Success"); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.c b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c new file mode 100644 index 0000000000000..805a1da90bb15 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c @@ -0,0 +1,26 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#define CREATE_TRACE_POINTS +#include "kfd_trace.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h new file mode 100644 index 0000000000000..5d27a98055377 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -0,0 +1,151 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#if !defined(_AMDKFD_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _KFD_TRACE_H_ + + +#include +#include +#include + +#include "kfd_priv.h" +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM amdkfd +#define TRACE_INCLUDE_FILE kfd_trace + + +TRACE_EVENT(kfd_map_memory_to_gpu_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid =%u", __entry->pasid) +); + + +TRACE_EVENT(kfd_map_memory_to_gpu_end, + TP_PROTO(struct kfd_process *p, u32 array_size, char *pStatusMsg), + TP_ARGS(p, array_size, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __field(unsigned int, array_size) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __entry->array_size = array_size; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", + __entry->pasid, + __entry->array_size, + __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_kgd2kfd_schedule_evict_and_restore_process, + TP_PROTO(struct kfd_process *p, u32 delay_jiffies), + TP_ARGS(p, delay_jiffies), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __field(unsigned int, delay_jiffies) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __entry->delay_jiffies = delay_jiffies; + ), + TP_printk("pasid = %u, delay_jiffies = %u", + __entry->pasid, + __entry->delay_jiffies) +); + + +TRACE_EVENT(kfd_evict_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid=%u", __entry->pasid) +); + + +TRACE_EVENT(kfd_evict_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid=%u, StatusMsg=%s", + __entry->pasid, __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_restore_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid=%u", __entry->pasid) +); + +TRACE_EVENT(kfd_restore_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + entry->pasid = p->pasid; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid=%u, StatusMsg=%s", + __entry->pasid, __get_str(pStatusMsg)) +); + +#endif + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include From b2f6fd2e47a572343c8a41c44a2da3826efd4815 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:53:39 -0400 Subject: [PATCH 0425/2070] drm/amdkfd: Mapping foreign device memory to GPUVM This adds the possibility to map foreign device memory as a userptr. This assumes that the foreign memory is pinned an cannot be evicted or migrated. This is generally true for doorbells. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 25 +++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6e00d1c0fd272..ef091df29714a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1069,6 +1069,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + struct vm_area_struct *vma; uint64_t cpuva = 0; unsigned int mem_type = 0; @@ -1140,7 +1141,29 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, goto err_unlock; } - if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { + if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { + /* Check if the userptr corresponds to another (or third-party) + * device local memory. If so treat is as a doorbell. User + * space will be oblivious of this and will use this doorbell + * BO as a regular userptr BO + */ + vma = find_vma(current->mm, args->mmap_offset); + if (vma && (vma->vm_flags & VM_IO)) { + unsigned long pfn; + + follow_pfn(vma, args->mmap_offset, &pfn); + flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; + flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; + offset = (pfn << PAGE_SHIFT); + } else { + if (offset & (PAGE_SIZE - 1)) { + pr_debug("Unaligned userptr address:%llx\n", + offset); + return -EINVAL; + } + cpuva = offset; + } + } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { if (args->size != kfd_doorbell_process_slice(dev->kfd)) { err = -EINVAL; goto err_unlock; From 512f1cee68a943a076981474aaa352ea1772088c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:00:12 -0400 Subject: [PATCH 0426/2070] drm/amdkfd: Experimental support for architectures w/o ACPI Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index a1087c13f2419..d4291fe4952d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1875,8 +1875,6 @@ static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size, static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) { struct crat_header *crat_table = (struct crat_header *)pcrat_image; - struct acpi_table_header *acpi_table; - acpi_status status; struct crat_subtype_generic *sub_type_hdr; int avail_size = *size; int numa_node_id; @@ -1884,6 +1882,10 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) uint32_t entries = 0; #endif int ret = 0; +#ifdef CONFIG_ACPI + struct acpi_table_header *acpi_table; + acpi_status status; +#endif if (!pcrat_image) return -EINVAL; @@ -1900,6 +1902,7 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) sizeof(crat_table->signature)); crat_table->length = sizeof(struct crat_header); +#ifdef CONFIG_ACPI status = acpi_get_table("DSDT", 0, &acpi_table); if (status != AE_OK) pr_warn("DSDT table not found for OEM information\n"); @@ -1911,6 +1914,11 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) CRAT_OEMTABLEID_LENGTH); acpi_put_table(acpi_table); } +#else + crat_table->oem_revision = 0; + memcpy(crat_table->oem_id, "INV", CRAT_OEMID_LENGTH); + memcpy(crat_table->oem_table_id, "UNAVAIL", CRAT_OEMTABLEID_LENGTH); +#endif crat_table->total_entries = 0; crat_table->num_domains = 0; From 6067fbcda7e5a5ae0fd8c43d74758fe979c80254 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:07:48 -0400 Subject: [PATCH 0427/2070] drm/amdkfd: Report used GPU memory This change has been rejected upstream. A better solution is needed. Used memory being dynamic doesn't belong in the topology tree, which contains otherwise static information. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 44 +++++++++++++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +- 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 1ccd4514d3ee4..4a319f7c5b788 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -206,6 +206,8 @@ struct kfd_topology_device *kfd_create_topology_device( sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value) #define sysfs_show_32bit_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%u\n", value) +#define sysfs_show_64bit_val(buffer, offs, value) \ + sysfs_show_gen_prop(buffer, offs, "%llu\n", value) #define sysfs_show_str_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%s\n", value) @@ -295,11 +297,25 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, { int offs = 0; struct kfd_mem_properties *mem; + uint64_t used_mem; /* Making sure that the buffer is an empty string */ buffer[0] = 0; - mem = container_of(attr, struct kfd_mem_properties, attr); + if (strcmp(attr->name, "used_memory") == 0) { + mem = container_of(attr, struct kfd_mem_properties, + attr_used); + if (mem->gpu) { + if (kfd_devcgroup_check_permission(mem->gpu)) + return -EPERM; + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->kgd); + return sysfs_show_64bit_val(buffer, offs, used_mem); + } + /* TODO: Report APU/CPU-allocated memory; For now return 0 */ + return 0; + } + + mem = container_of(attr, struct kfd_mem_properties, attr_props); if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type); @@ -610,7 +626,12 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) if (dev->kobj_mem) { list_for_each_entry(mem, &dev->mem_props, list) if (mem->kobj) { - kfd_remove_sysfs_file(mem->kobj, &mem->attr); + /* TODO: Remove when CPU/APU supported */ + if (dev->node_props.cpu_cores_count == 0) + sysfs_remove_file(mem->kobj, + &mem->attr_used); + kfd_remove_sysfs_file(mem->kobj, + &mem->attr_props); mem->kobj = NULL; } kobject_del(dev->kobj_mem); @@ -721,12 +742,23 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, return ret; } - mem->attr.name = "properties"; - mem->attr.mode = KFD_SYSFS_FILE_MODE; - sysfs_attr_init(&mem->attr); - ret = sysfs_create_file(mem->kobj, &mem->attr); + mem->attr_props.name = "properties"; + mem->attr_props.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_props); + ret = sysfs_create_file(mem->kobj, &mem->attr_props); if (ret < 0) return ret; + + /* TODO: Support APU/CPU memory usage */ + if (dev->node_props.cpu_cores_count == 0) { + mem->attr_used.name = "used_memory"; + mem->attr_used.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_used); + ret = sysfs_create_file(mem->kobj, &mem->attr_used); + if (ret < 0) + return ret; + } + i++; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index ad63ba67b5774..129b447fcf84d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -92,7 +92,8 @@ struct kfd_mem_properties { uint32_t mem_clk_max; struct kfd_node *gpu; struct kobject *kobj; - struct attribute attr; + struct attribute attr_props; + struct attribute attr_used; }; #define CACHE_SIBLINGMAP_SIZE 128 From b9c926ef3c84d76e2b976606663e88f990f6f08f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Oct 2019 14:01:27 +0200 Subject: [PATCH 0428/2070] drm/amdgpu: work around llvm bug #42576 Code in the amdgpu driver triggers a bug when using clang to build an arm64 kernel: /tmp/sdma_v4_0-f95fd3.s: Assembler messages: /tmp/sdma_v4_0-f95fd3.s:44: Error: selected processor does not support `bfc w0,#1,#5' I expect this to be fixed in llvm soon, but we can also work around it by inserting a barrier() that prevents the optimization. Link: https://bugs.llvm.org/show_bug.cgi?id=42576 Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 44f0f23e11484..c3baaa0959b95 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1067,6 +1067,7 @@ static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) /* Set ring buffer size in dwords */ uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); + barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); From 909cd74e3eeb3abc54d41cadd0444ea6fca6d8ea Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 12 Jul 2019 15:53:23 +0800 Subject: [PATCH 0429/2070] Revert "drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback" Signed-off-by: changzhu --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 1893ceeeb26c8..0f9bf8ec08f3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -8710,7 +8710,11 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | PACKET3_RELEASE_MEM_GCR_GL2_WB | - PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ + PACKET3_RELEASE_MEM_GCR_GL2_INV | + PACKET3_RELEASE_MEM_GCR_GL2_US | + PACKET3_RELEASE_MEM_GCR_GL1_INV | + PACKET3_RELEASE_MEM_GCR_GLV_INV | + PACKET3_RELEASE_MEM_GCR_GLM_INV | PACKET3_RELEASE_MEM_GCR_GLM_WB | PACKET3_RELEASE_MEM_CACHE_POLICY(3) | PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | From 7ed4b5bea331a0a0289ed5915d45223aa007f4ae Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 24 Mar 2020 12:30:28 -0400 Subject: [PATCH 0430/2070] drm/amdkfd: block queue destroy on suspended queues When debugger is attached, queue destroy requests will be blocked until queues have resumed. Note: the debugger owns suspend_queues and resume_queues so there should be no harm blocking queue destroy until queue resume since gdb can halt CPU threads anyways. Debugger also doesn't wait on application threads since suspend is only briefly called to update_waves before resume so halting queue destroy calls shouldn't deadlock the debugger. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 449be58e884c0..d3c5a83160579 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -535,6 +535,10 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); + + if (retval == -ERESTARTSYS) + return retval; + if (retval) { pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", pdd->pasid, From 5992dc3e725f48f052ea78838773b5bc2d99ff26 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 24 Apr 2020 16:14:01 -0400 Subject: [PATCH 0431/2070] drm/amdkfd: Distance non-upstream ioctls Create a gap between upstream and non-upstream ioctls so when upstream adds an ioctl, we don't need to bump non-upstream ioctl command number. This can avoid the backwards compatibility in the future though it'll happen at this time. Signed-off-by: Amber Lin Reviewed-by: Felix Kuehling Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++-------- include/uapi/linux/kfd_ioctl.h | 8 ++++++-- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index ef091df29714a..95678bd1b70c2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3414,8 +3414,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { kfd_ioctl_ipc_export_handle, 0), }; -#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) - static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) { struct kfd_process *process; @@ -3428,12 +3426,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) int retcode = -EINVAL; bool ptrace_attached = false; - if (nr >= AMDKFD_CORE_IOCTL_COUNT) { - retcode = -ENOTTY; - goto err_i1; - } - - if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { + if (((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) || + ((nr >= AMDKFD_COMMAND_START_2) && (nr < AMDKFD_COMMAND_END_2))) { u32 amdkfd_size; ioctl = &amdkfd_ioctls[nr]; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 1ec9537da6e7b..eca5651658f52 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1707,13 +1707,17 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_CREATE_PROCESS \ AMDKFD_IO(0x27) +#define AMDKFD_COMMAND_START 0x01 +#define AMDKFD_COMMAND_END 0x28 + +/* non-upstream ioctls */ #define AMDKFD_IOC_IPC_IMPORT_HANDLE \ AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) -#define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x28 +#define AMDKFD_COMMAND_START_2 0x80 +#define AMDKFD_COMMAND_END_2 0x84 #endif From f26635c3eaf4b128309aeb3006706b84380b426d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 1 May 2020 10:40:05 -0400 Subject: [PATCH 0432/2070] drm/amdkfd: Fix a race condition getting IPC obj handle reference If an IPC object is being released (zero refcount) don't try to take another reference to it. Signed-off-by: Felix Kuehling Tested-by: Alex Sierra Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 9 +++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 51395a88c12a8..ab05edb3a652a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -88,9 +88,11 @@ static void ipc_obj_release(struct kref *r) kfree(obj); } -void ipc_obj_get(struct kfd_ipc_obj *obj) +struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) { - kref_get(&obj->ref); + if (kref_get_unless_zero(&obj->ref)) + return obj; + return NULL; } void ipc_obj_put(struct kfd_ipc_obj **obj) @@ -196,7 +198,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { if (!memcmp(entry->share_handle, share_handle, sizeof(entry->share_handle))) { - found = entry; + found = ipc_obj_get(entry); break; } } @@ -204,7 +206,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!found) return -EINVAL; - ipc_obj_get(found); pr_debug("Found ipc_dma_buf: %p\n", found->data); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 9ee8627b88b08..a6560eae9ff50 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -45,7 +45,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle); -void ipc_obj_get(struct kfd_ipc_obj *obj); +struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj); void ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ From add0d4cecbf40b31423dc2182612860aeb1c0ff3 Mon Sep 17 00:00:00 2001 From: "Philip.Cox@amd.com" Date: Wed, 1 Apr 2020 13:37:20 -0400 Subject: [PATCH 0433/2070] drm/amdkfd: Initial gfx9 debug address watch Code for new GFX9 kfd debugger address watch code. -- Adding support for: -- add address watch -- clear address watch Change-Id: I51d6494db6881c02b8fbb56c73cf970389c036fc Signed-off-by: Philip.Cox@amd.com Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 8b600ca431f8d..a10304d7eaba8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -377,6 +377,15 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /* + * A bitmask to indicate which watch points have been allocated. + * bit meaning: + * 0: unallocated/available + * 1: allocated/unavailable + */ + uint32_t allocated_debug_watch_points; + spinlock_t watch_points_lock; + struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -1642,6 +1651,16 @@ int kfd_ipc_init(void); void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); +/* Allocate and free watch point IDs for debugger */ +int kfd_allocate_debug_watch_point(struct kfd_dev *kfd, + uint64_t watch_address, + uint32_t watch_address_mask, + uint32_t *watch_point, + uint32_t watch_mode, + uint32_t debug_vmid); +int kfd_release_debug_watch_points(struct kfd_dev *kfd, + uint32_t watch_point_bit_mask_to_free); + /* Cgroup Support */ /* Check with device cgroup if @kfd device is accessible */ static inline int kfd_devcgroup_check_permission(struct kfd_node *node) From 3ba3f9cd8a4e18e8980f0fd9a11d92917562529d Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Tue, 30 Jun 2020 18:40:37 -0500 Subject: [PATCH 0434/2070] drm/amdkfd: Prevent GWS+debugger on buggy firmware Some versions of MEC2 firmware do not correctly handle simultaneously setting up debugging on a process while having a GWS-enabled queue in that process. This could lead to CWSR failure and crashing the kernel driver. Prevent this situation from happening when we are on an affected firmware version by preventing both debugging and GWS-enabled queue from both being enabled at the same time. If the process has a GWS enabled queue, attempting to turn on debugging will fail with -EBUSY. If debugging is already enabled, attempting to create a GWS-enabled queue will fail with -EBUSY. v2: Use qpd.num_gws to track GWS usage, even with suspended queues. Signed-off-by: Joseph Greathouse Reviewed-by: Rajneesh Bhardwaj Reviewed-by: Felix Kuehling Change-Id: Id4f1d12665fa6ac5d5402637cf9361bcb2dbfbc6 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 95678bd1b70c2..5fc84f32091fb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1533,6 +1533,12 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, goto out_unlock; } + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + retval = -ESRCH; + goto out_unlock; + } + if (!dev->gws) { retval = -ENODEV; goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 9a66ee661e57c..ee3befc2ed0cb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -595,6 +595,15 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } + if ((kfd->device_info->asic_family == CHIP_VEGA10 + && kfd->mec2_fw_version < 0x81b6) + || (kfd->device_info->asic_family >= CHIP_VEGA12 + && kfd->device_info->asic_family <= CHIP_RAVEN + && kfd->mec2_fw_version < 0x1b6) + || (kfd->device_info->asic_family == CHIP_ARCTURUS + && kfd->mec2_fw_version < 0x30)) + kfd->gws_debug_workaround = true; + return ret; } From 57e447758627682daf75b9a19578e2bb81446be8 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 26 Jun 2020 22:32:01 -0400 Subject: [PATCH 0435/2070] drm/amdkfd: Move ipc_obj from kfd_bo to kgd_mem This should make IPC easier to upstream. struct kfd_bo does not exist upstream and its main purpose is to support RDMA, which is not upstreamable. struct kgd_mem exists upstream and is a KFD-specific buffer object structure that can be used to store a pointer to the ipc_obj. Adding another one layer of tracking in KFD just for IPC cannot be justified when upstreaming IPC. With this change, some of the IPC functionality moves into amdgpu_amdkfd_gpuvm.c with some calls back to kfd_ipc.c. Cleaned up and exported kfd_ipc_obj_put and kfd_ipc_store_insert. Signed-off-by: Felix Kuehling Acked-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 ++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 67 ++++++++----------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 12 ++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 +-- 7 files changed, 75 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 6e160ca5a5e44..55e24372f7a00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -70,6 +70,7 @@ struct kfd_mem_attachment { struct kgd_mem { struct mutex lock; struct amdgpu_bo *bo; + struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; struct amdgpu_hmm_range *range; struct list_head attachments; @@ -353,6 +354,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, struct dma_buf *dmabuf, + struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, uint64_t *mmap_offset); @@ -362,9 +364,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); -int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, - struct kgd_mem *mem, - struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index d598791a9f440..7a16fb5d82a13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -35,6 +35,7 @@ #include "amdgpu_hmm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" +#include "kfd_ipc.h" #include #include "amdgpu_xgmi.h" #include "kfd_priv.h" @@ -1982,6 +1983,9 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( *size = 0; } + /* Unreference the ipc_obj if applicable */ + kfd_ipc_obj_put(&mem->ipc_obj); + /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); @@ -2604,6 +2608,7 @@ static int import_obj_create(struct amdgpu_device *adev, get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; (*mem)->bo = bo; + (*mem)->ipc_obj = ipc_obj; (*mem)->va = va; (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->apu_prefer_gtt ? @@ -2686,22 +2691,40 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } -int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, - struct kgd_mem *mem, - struct dma_buf **dmabuf) +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj) { struct amdgpu_device *adev = NULL; + struct dma_buf *dmabuf; + int r = 0; - if (!dmabuf || !kgd || !vm || !mem) + if (!kgd || !vm || !mem) return -EINVAL; adev = get_amdgpu_device(kgd); + mutex_lock(&mem->lock); - *dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); - if (IS_ERR(*dmabuf)) - return -EINVAL; + if (mem->ipc_obj) { + *ipc_obj = mem->ipc_obj; + goto unlock_out; + } - return 0; + dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); + if (IS_ERR(dmabuf)) { + r = PTR_ERR(dmabuf); + goto unlock_out; + } + + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj); + if (r) + dma_buf_put(dmabuf); + else + *ipc_obj = mem->ipc_obj; + +unlock_out: + mutex_unlock(&mem->lock); + return r; } /* Evict a userptr BO by stopping the queues if necessary diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 5fc84f32091fb..fde0ab1ae5ae1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1199,7 +1199,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - args->va_addr, args->size, cpuva, mem_type, NULL); + args->va_addr, args->size, cpuva, mem_type); if (idr_handle < 0) { err = -EFAULT; goto err_free; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index ab05edb3a652a..d52e0f38eef1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include #include #include @@ -42,7 +41,7 @@ static struct kfd_ipc_handles { */ #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) -static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) { struct kfd_ipc_obj *obj; @@ -58,11 +57,9 @@ static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) * storage happens at ipc_obj release time. */ kref_init(&obj->ref); - obj->data = val; + obj->dmabuf = dmabuf; get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); - memcpy(sh, obj->share_handle, sizeof(obj->share_handle)); - mutex_lock(&kfd_ipc_handles.lock); hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); @@ -84,21 +81,23 @@ static void ipc_obj_release(struct kref *r) hash_del(&obj->node); mutex_unlock(&kfd_ipc_handles.lock); - dma_buf_put(obj->data); + dma_buf_put(obj->dmabuf); kfree(obj); } -struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) +static struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) { if (kref_get_unless_zero(&obj->ref)) return obj; return NULL; } -void ipc_obj_put(struct kfd_ipc_obj **obj) +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj) { - kref_put(&(*obj)->ref, ipc_obj_release); - *obj = NULL; + if (*obj) { + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; + } } int kfd_ipc_init(void) @@ -110,10 +109,10 @@ int kfd_ipc_init(void) static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, struct kfd_process *p, - uint32_t gpu_id, struct dma_buf *dmabuf, + uint32_t gpu_id, + struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, - struct kfd_ipc_obj *ipc_obj) + uint64_t *mmap_offset) { int r; void *mem; @@ -135,7 +134,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; } - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, va_addr, pdd->vm, (struct kgd_mem **)&mem, &size, mmap_offset); @@ -143,8 +142,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0, - ipc_obj); + va_addr, size, 0, 0); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -175,9 +173,8 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, if (!dmabuf) return -EINVAL; - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, - va_addr, handle, mmap_offset, - NULL); + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, + va_addr, handle, mmap_offset); dma_buf_put(dmabuf); return r; } @@ -207,18 +204,18 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!found) return -EINVAL; - pr_debug("Found ipc_dma_buf: %p\n", found->data); + pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->data, - va_addr, handle, mmap_offset, - found); + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, + found->dmabuf, found, + va_addr, handle, mmap_offset); if (r) goto error_unref; return r; error_unref: - ipc_obj_put(&found); + kfd_ipc_obj_put(&found); return r; } @@ -226,9 +223,9 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle) { struct kfd_process_device *pdd = NULL; - struct kfd_ipc_obj *obj; + struct kfd_ipc_obj *ipc_obj; struct kfd_bo *kfd_bo = NULL; - struct dma_buf *dmabuf; + struct kgd_mem *mem; int r; if (!dev || !ipc_handle) @@ -249,23 +246,15 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, pr_err("Failed to get bo"); return -EINVAL; } - if (kfd_bo->kfd_ipc_obj) { - memcpy(ipc_handle, kfd_bo->kfd_ipc_obj->share_handle, - sizeof(kfd_bo->kfd_ipc_obj->share_handle)); - return 0; - } - - r = amdgpu_amdkfd_gpuvm_export_dmabuf(dev->kgd, pdd->vm, - (struct kgd_mem *)kfd_bo->mem, - &dmabuf); - if (r) - return r; + mem = (struct kgd_mem *)kfd_bo->mem; - r = ipc_store_insert(dmabuf, ipc_handle, &obj); + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->vm, mem, + &ipc_obj); if (r) return r; - kfd_bo->kfd_ipc_obj = obj; + memcpy(ipc_handle, ipc_obj->share_handle, + sizeof(ipc_obj->share_handle)); return r; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index a6560eae9ff50..72fe8e4af2e5c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -25,12 +25,16 @@ #define KFD_IPC_H_ #include -#include "kfd_priv.h" +#include + +/* avoid including kfd_priv.h */ +struct kfd_dev; +struct kfd_process; struct kfd_ipc_obj { struct hlist_node node; struct kref ref; - void *data; + struct dma_buf *dmabuf; uint32_t share_handle[4]; }; @@ -45,7 +49,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle); -struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj); -void ipc_obj_put(struct kfd_ipc_obj **obj); +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj); +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a10304d7eaba8..d5fc45ab00370 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -414,7 +414,6 @@ struct kfd_bo { void *mem; struct interval_tree_node it; struct kfd_dev *dev; - struct kfd_ipc_obj *kfd_ipc_obj; /* page-aligned VA address */ uint64_t cpuva; unsigned int mem_type; @@ -1160,8 +1159,7 @@ void kfd_process_notifier_release_internal(struct kfd_process *p); int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type, - struct kfd_ipc_obj *ipc_obj); + unsigned int mem_type); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 7780d9bfc08e3..33c36207c9701 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -32,7 +32,6 @@ #include #include #include -#include "kfd_ipc.h" #include #include "amdgpu_amdkfd.h" #include "amdgpu.h" @@ -1890,8 +1889,7 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type, - struct kfd_ipc_obj *ipc_obj) + unsigned int mem_type) { int handle; struct kfd_bo *buf_obj; @@ -1910,7 +1908,6 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->mem = mem; buf_obj->dev = pdd->dev; - buf_obj->kfd_ipc_obj = ipc_obj; buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; @@ -1986,9 +1983,6 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, buf_obj = kfd_process_device_find_bo(pdd, handle); - if (buf_obj->kfd_ipc_obj) - ipc_obj_put(&buf_obj->kfd_ipc_obj); - idr_remove(&pdd->alloc_idr, handle); interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); From c494cecab990983e95730e27bb2c3cbfcf7639d3 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Fri, 20 Mar 2020 17:07:06 +0800 Subject: [PATCH 0436/2070] drm/amdgpu: move csa to the lower gmc hole location Move csa to the lower gmc hole location as the cp firmware starting from Navi1x firmware can't well handle the address of upper gmc hole space. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c index 11d70fe4f75a9..7b46bffb10ccb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c @@ -28,9 +28,13 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { - uint64_t addr = AMDGPU_VA_RESERVED_CSA_START(adev); - - addr = amdgpu_gmc_sign_extend(addr); + uint64_t addr; + if (adev->asic_type >= CHIP_NAVI10) { + addr = AMDGPU_VA_RESERVED_CSA_SIZE - AMDGPU_CSA_SIZE; + } else { + addr = AMDGPU_VA_RESERVED_CSA_START(adev); + addr = amdgpu_gmc_sign_extend(addr); + } return addr; } From 6a5df7427ee2badb4e7c4e67c31908dc4f2263a9 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 7 Oct 2020 14:14:28 -0400 Subject: [PATCH 0437/2070] drm/amdkfd: Catch failures from follow_pfn This fixes uninitialized, out-of-range physical addresses being programmed into the GPUVM page table in some corner cases. Signed-off-by: Felix Kuehling Acked-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fde0ab1ae5ae1..144dd95d88c6a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1151,7 +1151,11 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (vma && (vma->vm_flags & VM_IO)) { unsigned long pfn; - follow_pfn(vma, args->mmap_offset, &pfn); + err = follow_pfn(vma, args->mmap_offset, &pfn); + if (err) { + pr_debug("Failed to get PFN: %ld\n", err); + return err; + } flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; offset = (pfn << PAGE_SHIFT); From e5dc5786b2d50befb9c8ce92147de82d8a911780 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 26 Oct 2020 18:40:58 -0400 Subject: [PATCH 0438/2070] drm/amdkfd: correctly check find_vma success Check that find_vma actually found a VM that matches the address we're looking for. If there is no such VMA, don't try to create an IO mapping. Instead a regular userptr mapping will be created, and is expected to fail later in get_user_pages. Signed-off-by: Felix Kuehling Reviewed-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 144dd95d88c6a..749d37d89e2c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1148,7 +1148,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, * BO as a regular userptr BO */ vma = find_vma(current->mm, args->mmap_offset); - if (vma && (vma->vm_flags & VM_IO)) { + if (vma && args->mmap_offset >= vma->vm_start && + (vma->vm_flags & VM_IO)) { unsigned long pfn; err = follow_pfn(vma, args->mmap_offset, &pfn); From 9390111f9bbcd070fe31948bc7592ae24fb8daa6 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Sat, 31 Oct 2020 20:43:28 -0400 Subject: [PATCH 0439/2070] drm/amdkfd: Create P2P links Create p2p links for peer accessible devices Change-Id: I6cd52e43cba99224bca0eac7b01f29311912185b Signed-off-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 4a319f7c5b788..e1d57091a68da 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -587,6 +587,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_mem_properties *mem; struct kfd_perf_properties *perf; + if (dev->kobj_p2plink) { + list_for_each_entry(p2plink, &dev->p2p_link_props, list) + if (p2plink->kobj) { + kfd_remove_sysfs_file(p2plink->kobj, + &p2plink->attr); + p2plink->kobj = NULL; + } + kobject_del(dev->kobj_p2plink); + kobject_put(dev->kobj_p2plink); + dev->kobj_p2plink = NULL; + } + if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) if (iolink->kobj) { From 3330a9553bad6e98db7c68c24f7fad8d3b68d1f2 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Wed, 21 Oct 2020 16:00:55 -0400 Subject: [PATCH 0440/2070] drm/amdgpu: allow function to allocate normal GTT memory amdgpu_amdkfd_alloc_gtt_mem currently allocates USWC memory. It uses write-combining for CPU access, which is slow for reading. Add a new parameter to amdgpu_amdkfd_alloc_gtt_mem to allocate normal GTT memory. Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 9 ++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 6 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 274a5b083a5de..7dbeae47decba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -323,7 +323,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, u32 domain, void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool cp_mqd_gfx9) + void **cpu_ptr, bool cp_mqd_gfx9, bool is_uswc_mode) { struct amdgpu_bo *bo = NULL; struct amdgpu_bo_param bp; @@ -334,8 +334,11 @@ int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, bp.size = size; bp.byte_align = PAGE_SIZE; bp.domain = domain; - bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_CPU_GTT_USWC; + if (is_uswc_mode) + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_CPU_GTT_USWC; + else + bp.flags = 0; bp.type = ttm_bo_type_kernel; bp.resv = NULL; bp.bo_ptr_size = sizeof(struct amdgpu_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 55e24372f7a00..3e2c2436c26d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -244,7 +244,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, /* Shared API */ int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, u32 domain, void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool mqd_gfx9); + void **cpu_ptr, bool mqd_gfx9, bool is_uswc_mode); void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj); int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, void **mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index ee3befc2ed0cb..7c92227129914 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -833,7 +833,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT, &kfd->gtt_mem, &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, - false)) { + false, true)) { dev_err(kfd_device, "Could not allocate %d bytes\n", size); goto alloc_kernel_mem_failure; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 709fd518a6a0a..452139c3e7afd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2927,7 +2927,7 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, size, AMDGPU_GEM_DOMAIN_GTT, &(mem_obj->mem), &(mem_obj->gpu_addr), - (void *)&(mem_obj->cpu_ptr), false); + (void *)&(mem_obj->cpu_ptr), false, true); return retval; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index a61b04daa08c4..a91bb03519636 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -201,7 +201,7 @@ static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, AMDGPU_GEM_DOMAIN_GTT, &(mqd_mem_obj->mem), &(mqd_mem_obj->gpu_addr), - (void *)&(mqd_mem_obj->cpu_ptr), true); + (void *)&(mqd_mem_obj->cpu_ptr), true, true); if (retval) { kfree(mqd_mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index d3c5a83160579..da86d76624d0b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -375,7 +375,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context bo\n"); return retval; From b5703c4e45ad9f23fe54ea6b779fc91cbb458168 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Wed, 21 Oct 2020 17:10:42 -0400 Subject: [PATCH 0441/2070] drm/amd: Add Stream Performance Counter Monitors Driver Add Driver code for user to control GPU Stream Performance Counter Monitor and dump the Sample data to measure the GPU performance. Change-Id: Id10682e05ec3fc7456bcd8b25241686e42353462 Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 9 + .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 104 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 11 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 135 +++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 137 +++++- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 127 +++++ drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 12 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 462 ++++++++++++++++++ include/uapi/linux/kfd_ioctl.h | 81 ++- 12 files changed, 1088 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_spm.c diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index e7e9871fef1ce..30248b838288a 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -286,7 +286,8 @@ amdgpu-y += \ amdgpu_amdkfd_gfx_v10_3.o \ amdgpu_amdkfd_gfx_v11.o \ amdgpu_amdkfd_gfx_v12.o \ - amdgpu_amdkfd_gfx_v12_1.o + amdgpu_amdkfd_gfx_v12_1.o \ + amdgpu_amdkfd_rlc_spm.o ifneq ($(CONFIG_DRM_AMDGPU_CIK),) amdgpu-y += amdgpu_amdkfd_gfx_v7.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 3e2c2436c26d3..c4adcc9857a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -425,6 +425,14 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif +void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl); +int amdgpu_amdkfd_rlc_spm(struct kgd_dev *kgd, void *args); +int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size); +void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr); +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); #else @@ -436,6 +444,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) #endif /* KGD2KFD callbacks */ +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd); int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c new file mode 100644 index 0000000000000..eeaca9d1e02b9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu_object.h" +#include "amdgpu_amdkfd.h" +#include +#include "amdgpu_ids.h" + +void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + if (cntl) + adev->gfx.spmfuncs->start(adev); + else + adev->gfx.spmfuncs->stop(adev); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); +} + +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_rdptr(adev, rptr); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); +} + +int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + int r; + + if (!adev->gfx.rlc.funcs->update_spm_vmid) + return -EINVAL; + + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB_0); + if (r) + return r; + + /* init spm vmid with 0x0 */ + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); + + /* set spm ring registers */ + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + return r; +} + +void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + /* stop spm stream and interrupt */ + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->stop(adev); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); + + /* revert spm vmid with 0xf */ + if (adev->gfx.rlc.funcs->update_spm_vmid) + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); +} + +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) +{ + if (adev->kfd.dev) + kgd2kfd_spm_interrupt(adev->kfd.dev); +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 720ed3a2c78c6..08f16f86c6530 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -164,6 +164,15 @@ struct amdgpu_kiq { void *mqd_backup; }; +struct spm_funcs { + void (*start)(struct amdgpu_device *adev); + void (*stop)(struct amdgpu_device *adev); + void (*set_rdptr)(struct amdgpu_device *adev, u32 rptr); + void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, u64 gpu_rptr, u32 size); + /* Packet sizes */ + int set_spm_config_size; +}; + /* * GFX configurations */ @@ -418,6 +427,7 @@ struct amdgpu_gfx { struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_imu imu; + const struct spm_funcs *spmfuncs; bool rs64_enable; /* firmware format */ const struct firmware *me_fw; /* ME firmware */ uint32_t me_fw_version; @@ -461,6 +471,7 @@ struct amdgpu_gfx { struct amdgpu_irq_src priv_inst_irq; struct amdgpu_irq_src bad_op_irq; struct amdgpu_irq_src cp_ecc_error_irq; + struct amdgpu_irq_src spm_irq; struct amdgpu_irq_src sq_irq; struct amdgpu_irq_src rlc_gc_fed_irq; struct sq_work sq_work; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0f9bf8ec08f3e..a49c510f660de 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4872,6 +4872,13 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_EOP_INTERRUPT, @@ -7537,6 +7544,7 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* WA added for Vangogh asic fixing the SMU suspend failure * It needs to set power gating again during gfxoff control @@ -7788,6 +7796,94 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v10_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); + + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, + 0, mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v10_0_spm_funcs = { + .start = &gfx_v10_0_spm_start, + .stop = &gfx_v10_0_spm_stop, + .set_rdptr = &gfx_v10_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v10_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v10_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v10_0_spm_funcs; +} + static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -7819,6 +7915,7 @@ static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v10_0_set_spm_funcs(adev); gfx_v10_0_set_kiq_pm4_funcs(adev); gfx_v10_0_set_ring_funcs(adev); gfx_v10_0_set_irq_funcs(adev); @@ -7841,6 +7938,10 @@ static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -9801,6 +9902,32 @@ static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring) amdgpu_gfx_enforce_isolation_ring_end_use(ring); } +static int gfx_v10_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v10_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} + static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { .name = "gfx_v10_0", .early_init = gfx_v10_0_early_init, @@ -9987,6 +10114,11 @@ static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { .process = gfx_v10_0_kiq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v10_0_spm_irq_funcs = { + .set = gfx_v10_0_spm_set_interrupt_state, + .process = gfx_v10_0_spm_irq, +}; + static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; @@ -9995,6 +10127,9 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v10_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a6b4c8f41dc11..25ec1ca8df8d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1910,6 +1910,12 @@ static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, + VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR, &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); if (r) @@ -4854,6 +4860,7 @@ static int gfx_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* disable KCQ to avoid CPC touch memory not valid anymore */ gfx_v8_0_kcq_disable(adev); @@ -5256,6 +5263,97 @@ static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { .get_hdp_flush_mask = &gfx_v8_0_get_hdp_flush_mask, }; +static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, + bool wc, uint32_t reg, uint32_t val) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | + WRITE_DATA_DST_SEL(0) | + (wc ? WR_CONFIRM : 0)); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v8_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmGRBM_GFX_INDEX, data); + + + data = RREG32(mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, STRM_PERFMON_STATE_START_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_INT_CNTL, 1); +} + +static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + PERFMON_STATE, CP_PERFMON_STATE_STOP_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); +} + +static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); +} + +static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_HI, upper_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_SIZE, size); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_SEGMENT_THRESHOLD, 0xff); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, 0); +} + +static const struct spm_funcs gfx_v8_0_spm_funcs = { + .start = &gfx_v8_0_spm_start, + .stop = &gfx_v8_0_spm_stop, + .set_rdptr = &gfx_v8_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v8_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v8_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v8_0_spm_funcs; +} + static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -5265,6 +5363,7 @@ static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); adev->gfx.funcs = &gfx_v8_0_gfx_funcs; + gfx_v8_0_set_spm_funcs(adev); gfx_v8_0_set_ring_funcs(adev); gfx_v8_0_set_irq_funcs(adev); gfx_v8_0_set_gds_init(adev); @@ -5305,6 +5404,10 @@ static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) return r; } + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + return 0; } @@ -6786,6 +6889,31 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ } +static int gfx_v8_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v8_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f @@ -6843,7 +6971,6 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) gfx_v8_0_emit_wave_limit_cs(ring, i, enable); } - } static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { @@ -7011,11 +7138,19 @@ static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = { .process = gfx_v8_0_sq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v8_0_spm_irq_funcs = { + .set = gfx_v8_0_spm_set_interrupt_state, + .process = gfx_v8_0_spm_irq, +}; + static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v8_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 7e9d753f4a808..bea110c04fb23 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2275,6 +2275,13 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -4056,6 +4063,7 @@ static int gfx_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -4793,6 +4801,87 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) return r; } +static void gfx_v9_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_0_spm_funcs = { + .start = &gfx_v9_0_spm_start, + .stop = &gfx_v9_0_spm_stop, + .set_rdptr = &gfx_v9_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_0_spm_funcs; +} + static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -4807,6 +4896,7 @@ static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.xcc_mask = 1; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_0_set_spm_funcs(adev); gfx_v9_0_set_kiq_pm4_funcs(adev); gfx_v9_0_set_ring_funcs(adev); gfx_v9_0_set_irq_funcs(adev); @@ -4862,6 +4952,10 @@ static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -7100,6 +7194,32 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, gfx_v9_0_query_utc_edc_status(adev, err_data); } +static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v9_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} + static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { @@ -7716,12 +7836,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { .process = amdgpu_gfx_cp_ecc_error_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_0_spm_irq_funcs = { + .set = gfx_v9_0_spm_set_interrupt_state, + .process = gfx_v9_0_spm_irq, +}; static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 7391eb56d0b8d..9b8dc9f53bb2c 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -64,6 +64,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ + $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 749d37d89e2c5..50d540d0e06ca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1855,6 +1855,12 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ioctl_rlc_spm(struct file *filep, + struct kfd_process *p, void *data) +{ + return kfd_rlc_spm(p, data); +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3423,6 +3429,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, + kfd_ioctl_rlc_spm, 0), + }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index d5fc45ab00370..4f7508c182064 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -377,6 +377,9 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /*spm process id */ + unsigned int spm_pasid; + /* * A bitmask to indicate which watch points have been allocated. * bit meaning: @@ -845,6 +848,12 @@ struct kfd_process_device { struct attribute attr_sdma; char sdma_filename[MAX_SYSFS_FILENAME_LEN]; + /* spm data */ + struct kfd_spm_cntr *spm_cntr; + struct mutex spm_mutex; + struct work_struct spm_work; + spinlock_t spm_irq_lock; + /* Eviction activity tracking */ uint64_t last_evict_timestamp; atomic64_t evict_duration_counter; @@ -1638,6 +1647,9 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +void kfd_spm_init_process_device(struct kfd_process_device *pdd); +int kfd_rlc_spm(struct kfd_process *p, void __user *data); + /* PeerDirect support */ void kfd_init_peer_direct(void); void kfd_close_peer_direct(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c new file mode 100644 index 0000000000000..d9856191ab7eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -0,0 +1,462 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "amdgpu_irq.h" +#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" +#include "ivsrcid/ivsrcid_vislands30.h" +#include // for use_mm() +#include + +struct user_buf { + uint64_t __user *user_addr; + u32 ubufsize; +}; + +struct kfd_spm_cntr { + struct user_buf ubuf; + struct mutex spm_worker_mutex; + u64 gpu_addr; + u32 ring_size; + u32 ring_mask; + u32 ring_rptr; + u32 size_copied; + u32 has_data_loss; + u32 *cpu_addr; + void *spm_obj; + wait_queue_head_t spm_buf_wq; + bool has_user_buf; + bool is_user_buf_filled; + bool is_spm_started; +}; + +static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) +{ + struct kfd_spm_cntr *spm = pdd->spm_cntr; + uint64_t __user *user_address; + uint64_t *ring_buf; + u32 user_buf_space_left; + int ret = 0; + + if (spm->ubuf.user_addr == NULL) + return -EFAULT; + + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr); + + if (user_address == NULL) + return -EFAULT; + + user_buf_space_left = spm->ubuf.ubufsize - spm->size_copied; + + if (size_to_copy < user_buf_space_left) { + ret = copy_to_user(user_address, ring_buf, size_to_copy); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + spm->size_copied += size_to_copy; + spm->ring_rptr += size_to_copy; + } else { + ret = copy_to_user(user_address, ring_buf, user_buf_space_left); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + + spm->size_copied = spm->ubuf.ubufsize; + spm->ring_rptr += user_buf_space_left; + WRITE_ONCE(spm->is_user_buf_filled, true); + wake_up(&pdd->spm_cntr->spm_buf_wq); + } + + return ret; +} + +static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) +{ + struct kfd_spm_cntr *spm = pdd->spm_cntr; + u32 size_to_copy; + int ret = 0; + u32 ring_wptr; + + ring_wptr = READ_ONCE(spm->cpu_addr[0]) & spm->ring_mask; + + /* keep SPM ring buffer running */ + if (!spm->has_user_buf || spm->is_user_buf_filled) { + spm->ring_rptr = ring_wptr; + spm->has_data_loss = true; + /* set flag due to there is no flag setup + * when read ring buffer timeout. + */ + if (!spm->is_user_buf_filled) + spm->is_user_buf_filled = true; + goto exit; + } + + if (spm->ring_rptr == ring_wptr) + goto exit; + + if ((spm->ring_rptr >= 0) && (spm->ring_rptr < 0x20)) { + /* + * First 8DW, only use for WritePtr, it is not Counter data + */ + spm->ring_rptr = 0x20; + } + + if (ring_wptr > spm->ring_rptr) { + size_to_copy = ring_wptr - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy); + } else { + size_to_copy = spm->ring_size - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy); + + /* correct counter start point */ + if (spm->ring_size == spm->ring_rptr) { + if (ring_wptr == 0) { + /* reset rptr to start point of ring buffer */ + spm->ring_rptr = ring_wptr; + goto exit; + } + spm->ring_rptr = 0x20; + size_to_copy = ring_wptr - spm->ring_rptr; + if (!ret) + ret = kfd_spm_data_copy(pdd, size_to_copy); + } + } + +exit: + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->kgd, spm->ring_rptr); + return ret; +} + +static void kfd_spm_work(struct work_struct *work) +{ + struct kfd_process_device *pdd = container_of(work, struct kfd_process_device, spm_work); + struct mm_struct *mm = NULL; // referenced + + mm = get_task_mm(pdd->process->lead_thread); + if (mm) { + kthread_use_mm(mm); + { /* attach mm */ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + kfd_spm_read_ring_buffer(pdd); + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + } /* detach mm */ + kthread_unuse_mm(mm); + /* release the mm structure */ + mmput(mm); + } +} + +void kfd_spm_init_process_device(struct kfd_process_device *pdd) +{ + mutex_init(&pdd->spm_mutex); + pdd->spm_cntr = NULL; +} + +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +{ + int ret = 0; + + mutex_lock(&pdd->spm_mutex); + + if (pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); + if (!pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -ENOMEM; + } + mutex_unlock(&pdd->spm_mutex); + + /* git spm ring buffer 4M */ + pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); + pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4 - 0xff; + pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; + pdd->spm_cntr->has_user_buf = false; + + ret = amdgpu_amdkfd_alloc_gtt_mem(kgd, + pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, + &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, + false, false); + + if (ret) + goto alloc_gtt_mem_failure; + + ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->vm, + pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); + + /* + * By definition, the last 8 DWs of the buffer are not part of the rings + * and are instead part of the Meta data area. + */ + pdd->spm_cntr->ring_size -= 0x20; + + if (ret) + goto acquire_spm_failure; + + mutex_init(&pdd->spm_cntr->spm_worker_mutex); + + init_waitqueue_head(&pdd->spm_cntr->spm_buf_wq); + INIT_WORK(&pdd->spm_work, kfd_spm_work); + + spin_lock_init(&pdd->spm_irq_lock); + + goto out; + +acquire_spm_failure: + amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + +alloc_gtt_mem_failure: + mutex_lock(&pdd->spm_mutex); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + mutex_unlock(&pdd->spm_mutex); + +out: + return ret; +} + +static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +{ + unsigned long flags; + + mutex_lock(&pdd->spm_mutex); + if (!pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + pdd->spm_cntr->is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + flush_work(&pdd->spm_work); + wake_up_all(&pdd->spm_cntr->spm_buf_wq); + + amdgpu_amdkfd_rlc_spm_release(kgd, pdd->vm); + amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + mutex_unlock(&pdd->spm_mutex); + return 0; +} + +static void spm_copy_data_to_usr(struct kfd_ioctl_spm_args *user_spm_data, + struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + user_spm_data->bytes_copied = pdd->spm_cntr->size_copied; + user_spm_data->has_data_loss = pdd->spm_cntr->has_data_loss; + pdd->spm_cntr->has_user_buf = false; + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); +} + +static void spm_set_dest_info(struct kfd_process_device *pdd, + struct kfd_ioctl_spm_args *user_spm_data) +{ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + pdd->spm_cntr->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + pdd->spm_cntr->ubuf.ubufsize = user_spm_data->buf_size; + pdd->spm_cntr->has_data_loss = false; + pdd->spm_cntr->size_copied = 0; + pdd->spm_cntr->is_user_buf_filled = false; + pdd->spm_cntr->has_user_buf = true; + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); +} + +static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, + struct kfd_ioctl_spm_args *user_spm_data) +{ + int ret = 0; + + long timeout = msecs_to_jiffies(user_spm_data->timeout); + long start_jiffies = jiffies; + + ret = wait_event_interruptible_timeout(spm->spm_buf_wq, + (READ_ONCE(spm->is_user_buf_filled) == true), + timeout); + + switch (ret) { + case -ERESTARTSYS: + /* Subtract elapsed time from timeout so we wait that much + * less when the call gets restarted. + */ + timeout -= (jiffies - start_jiffies); + if (timeout <= 0) { + ret = -ETIME; + timeout = 0; + pr_debug("[%s] interrupted by signal\n", __func__); + } + break; + + case 0: + default: + timeout = ret; + ret = 0; + break; + } + user_spm_data->timeout = jiffies_to_msecs(timeout); + + return ret; +} + +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *kgd, void *data) +{ + struct kfd_ioctl_spm_args *user_spm_data; + struct kfd_spm_cntr *spm; + unsigned long flags; + int ret = 0; + + user_spm_data = (struct kfd_ioctl_spm_args *) data; + + mutex_lock(&pdd->spm_mutex); + spm = pdd->spm_cntr; + + if (spm == NULL) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + if (user_spm_data->timeout && spm->has_user_buf && + !READ_ONCE(spm->is_user_buf_filled)) { + ret = spm_wait_for_fill_awake(spm, user_spm_data); + if (ret == -ETIME) { + /* Copy (partial) data to user buffer after a timeout */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + /* This is not an error */ + ret = 0; + } else if (ret) { + /* handle other errors normally, including -ERESTARTSYS */ + mutex_unlock(&pdd->spm_mutex); + return ret; + } + } else if (!user_spm_data->timeout && spm->has_user_buf) { + /* Copy (partial) data to user buffer */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + } + + if (spm->has_user_buf) { + /* get info about filled space in previous output buffer */ + spm_copy_data_to_usr(user_spm_data, pdd); + } + + if (user_spm_data->dest_buf) { + /* setup new dest buf, start streaming if necessary */ + spm_set_dest_info(pdd, user_spm_data); + + /* Start SPM */ + if (spm->is_spm_started == false) { + amdgpu_amdkfd_rlc_spm_cntl(kgd, 1); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = true; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + } else { + /* If SPM was already started, there may already + * be data in the ring-buffer that needs to be read. + */ + schedule_work(&pdd->spm_work); + } + } else { + amdgpu_amdkfd_rlc_spm_cntl(kgd, 0); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + } + + mutex_unlock(&pdd->spm_mutex); + + return ret; +} + +int kfd_rlc_spm(struct kfd_process *p, void *data) +{ + struct kfd_ioctl_spm_args *args = data; + struct kfd_dev *dev; + struct kfd_process_device *pdd; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) { + pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); + return -EINVAL; + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return -EINVAL; + + switch (args->op) { + case KFD_IOCTL_SPM_OP_ACQUIRE: + dev->spm_pasid = p->pasid; + return kfd_acquire_spm(pdd, dev->kgd); + + case KFD_IOCTL_SPM_OP_RELEASE: + return kfd_release_spm(pdd, dev->kgd); + + case KFD_IOCTL_SPM_OP_SET_DEST_BUF: + return kfd_set_dest_buffer(pdd, dev->kgd, data); + + default: + return -EINVAL; + } + + return -EINVAL; +} + +void kgd2kfd_spm_interrupt(struct kfd_dev *dev) +{ + struct kfd_process_device *pdd; + uint16_t pasid = dev->spm_pasid; + + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + unsigned long flags; + + if (!p) { + pr_debug("kfd_spm_interrupt p = %p\n", p); + return; /* Presumably process exited. */ + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return; + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + + if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) + schedule_work(&pdd->spm_work); + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + kfd_unref_process(p); +} + diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index eca5651658f52..9aedbefce073d 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -597,6 +597,81 @@ struct kfd_ioctl_smi_events_args { __u32 anon_fd; /* from KFD */ }; +/** + * kfd_ioctl_spm_op - SPM ioctl operations + * + * @KFD_IOCTL_SPM_OP_ACQUIRE: acquire exclusive access to SPM + * @KFD_IOCTL_SPM_OP_RELEASE: release exclusive access to SPM + * @KFD_IOCTL_SPM_OP_SET_DEST_BUF: set or unset destination buffer for SPM streaming + */ +enum kfd_ioctl_spm_op { + KFD_IOCTL_SPM_OP_ACQUIRE, + KFD_IOCTL_SPM_OP_RELEASE, + KFD_IOCTL_SPM_OP_SET_DEST_BUF +}; + +/** + * kfd_ioctl_spm_args - Arguments for SPM ioctl + * + * @op[in]: specifies the operation to perform + * @gpu_id[in]: GPU ID of the GPU to profile + * @dst_buf[in]: used for the address of the destination buffer + * in @KFD_IOCTL_SPM_SET_DEST_BUFFER + * @buf_size[in]: size of the destination buffer + * @timeout[in/out]: [in]: timeout in milliseconds, [out]: amount of time left + * `in the timeout window + * @bytes_copied[out]: amount of data that was copied to the previous dest_buf + * @has_data_loss: boolean indicating whether data was lost + * (e.g. due to a ring-buffer overflow) + * + * This ioctl performs different functions depending on the @op parameter. + * + * KFD_IOCTL_SPM_OP_ACQUIRE + * ------------------------ + * + * Acquires exclusive access of SPM on the specified @gpu_id for the calling process. + * This must be called before using KFD_IOCTL_SPM_OP_SET_DEST_BUF. + * + * KFD_IOCTL_SPM_OP_RELEASE + * ------------------------ + * + * Releases exclusive access of SPM on the specified @gpu_id for the calling process, + * which allows another process to acquire it in the future. + * + * KFD_IOCTL_SPM_OP_SET_DEST_BUF + * ----------------------------- + * + * If @dst_buf is NULL, the destination buffer address is unset and copying of counters + * is stopped. + * + * If @dst_buf is not NULL, it specifies the pointer to a new destination buffer. + * @buf_size specifies the size of the buffer. + * + * If @timeout is non-0, the call will wait for up to @timeout ms for the previous + * buffer to be filled. If previous buffer to be filled before timeout, the @timeout + * will be updated value with the time remaining. If the timeout is exceeded, the function + * copies any partial data available into the previous user buffer and returns success. + * The amount of valid data in the previous user buffer is indicated by @bytes_copied. + * + * If @timeout is 0, the function immediately replaces the previous destination buffer + * without waiting for the previous buffer to be filled. That means the previous buffer + * may only be partially filled, and @bytes_copied will indicate how much data has been + * copied to it. + * + * If data was lost, e.g. due to a ring buffer overflow, @has_data_loss will be non-0. + * + * Returns negative error code on failure, 0 on success. + */ +struct kfd_ioctl_spm_args { + __u64 dest_buf; + __u32 buf_size; + __u32 op; + __u32 timeout; + __u32 gpu_id; + __u32 bytes_copied; + __u32 has_data_loss; +}; + /* * SVM event tracing via SMI system management interface * @@ -747,7 +822,6 @@ struct kfd_criu_bo_bucket { /* CRIU IOCTLs - END */ /**************************************************************************************************/ - /* Register offset inside the remapped mmio page */ enum kfd_mmio_remap { @@ -1717,7 +1791,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) +#define AMDKFD_IOC_RLC_SPM \ + AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x84 +#define AMDKFD_COMMAND_END_2 0x85 #endif From 345f9de5901fd750bca7c268ea890721bbc2ef3d Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 7 Jan 2021 13:54:26 +0800 Subject: [PATCH 0442/2070] Revert "drm/amd/pm: typo fix (CUSTOM -> COMPUTE)" This reverts commit 11a4d4b89bfd7981aeb765683e1c5f7222f645f5. It breaks one test. Root cause identifying is still on the way. Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 6268bc5ed3e68..c7b7179a38eff 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -252,7 +252,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; From 8127825c7666cc7ff10b1477ca34b964b2319810 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Thu, 14 Jan 2021 22:54:39 -0500 Subject: [PATCH 0443/2070] drm/amdkfd: Create indirect links Create GPU<->CPU indirect IO links Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index e1d57091a68da..7db7588b2cee1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1418,6 +1418,20 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } + + /* Create CPU<->GPU indirect links so apply flags setting to all */ + list_for_each_entry(link, &dev->p2p_link_props, list) { + cpu_dev = kfd_topology_device_by_proximity_domain( + link->node_to); + if (cpu_dev && !cpu_dev->gpu) { + list_for_each_entry(cpu_link, + &cpu_dev->p2p_link_props, list) + if (cpu_link->node_to == link->node_from) { + link->flags = flag; + cpu_link->flags = cpu_flag; + } + } + } } static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev, From c4d24eadcbf4122d6a66eb0e76b3eeb686811190 Mon Sep 17 00:00:00 2001 From: Philip Cox Date: Tue, 17 Nov 2020 11:05:36 -0500 Subject: [PATCH 0444/2070] drm/amdkfd: Change kfd debugger to use PID. Rework the kfd debugger API to use PID rather than the device id. Debugging actions are now on all devices, rather than a single device. Change-Id: Ie2a18a0299176b6a68c23113da057c7f7746c3a6 Signed-off-by: Philip Cox Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ------ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 ------------------- include/uapi/linux/kfd_ioctl.h | 2 +- 3 files changed, 1 insertion(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 50d540d0e06ca..6db923e9f75ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1538,12 +1538,6 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, goto out_unlock; } - pdd = kfd_bind_process_to_device(dev, p); - if (IS_ERR(pdd)) { - retval = -ESRCH; - goto out_unlock; - } - if (!dev->gws) { retval = -ENODEV; goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4f7508c182064..d80cb5b90bc0b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -380,15 +380,6 @@ struct kfd_dev { /*spm process id */ unsigned int spm_pasid; - /* - * A bitmask to indicate which watch points have been allocated. - * bit meaning: - * 0: unallocated/available - * 1: allocated/unavailable - */ - uint32_t allocated_debug_watch_points; - spinlock_t watch_points_lock; - struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -1661,16 +1652,6 @@ int kfd_ipc_init(void); void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); -/* Allocate and free watch point IDs for debugger */ -int kfd_allocate_debug_watch_point(struct kfd_dev *kfd, - uint64_t watch_address, - uint32_t watch_address_mask, - uint32_t *watch_point, - uint32_t watch_mode, - uint32_t debug_vmid); -int kfd_release_debug_watch_points(struct kfd_dev *kfd, - uint32_t watch_point_bit_mask_to_free); - /* Cgroup Support */ /* Check with device cgroup if @kfd device is accessible */ static inline int kfd_devcgroup_check_permission(struct kfd_node *node) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 9aedbefce073d..1a0fbb092780b 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -257,11 +257,11 @@ struct kfd_ioctl_dbg_wave_control_args { struct kfd_ioctl_dbg_trap_args { __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ - __u32 gpu_id; /* to KFD */ __u32 op; /* to KFD */ __u32 data1; /* to KFD */ __u32 data2; /* to KFD */ __u32 data3; /* to KFD */ + __u32 data4; /* to KFD */ }; /* Matching HSA_EVENTTYPE */ From 2a55fb6f55681394ac9b3ba980f3056fa26ad45b Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 19 Jan 2021 23:45:47 -0500 Subject: [PATCH 0445/2070] drm/amdkfd: enable exception code reporting to the debugger Report EC_TRAP_HANDLER (debug notifier only at the moment), EC_QUEUE_NEW, EC_QUEUE_DELETE and EC_MEMORY_VIOLATION to the debugger with the new exception code features. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- include/uapi/linux/kfd_ioctl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 1a0fbb092780b..647a97374a315 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -255,6 +255,7 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff struct kfd_ioctl_dbg_trap_args { + __u64 exception_mask; /* to KFD */ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ __u32 op; /* to KFD */ From 1a1461411c31f72a3240ca5fdc1633d6a7dfe6c4 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:43:26 +0800 Subject: [PATCH 0446/2070] drm/amdkcl: test drm_driver->gem_prime_export() This is a squash of: drm/amdkcl: fix test for drm_gem_prime_export() Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 5 +++++ .../drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index c7fffa1562890..634b23c033304 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -547,7 +547,12 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { * Returns: * Shared DMA buffer representing the GEM BO from the given device. */ +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); @@ -569,7 +574,12 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, if (ret) return ERR_PTR(ret); +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI buf = drm_gem_prime_export(gobj, flags); +#else + buf = drm_gem_prime_export(dev, gobj, flags); +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index db75327913c95..f7a7492b68f55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -34,7 +34,12 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct sg_table *sg); #endif +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags); #if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 new file mode 100644 index 0000000000000..bac95ca04518c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-870-ge4fa8457b219 +dnl # drm/prime: Align gem_prime_export with obj_funcs.export +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_prime_export(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI, 1, + [drm_gem_prime_export() with p,i arg is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a93bd4ad2e469..bae8699fb36fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -46,6 +46,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ + AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From 1623f6004c116842f92a76befdac985003374111 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Wed, 26 Jun 2019 15:20:19 -0400 Subject: [PATCH 0447/2070] drm/amdkcl: Test whether ttm_bo_vm_fault() wants 2 args v2: Test whether vm_fault->{address/vma} is available v3: fix intree failure due to vmf->vma kcl wrapper v4: refactor test for vm_operations_struct->fault() Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui Reviewed-by: Jiansong Chen Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 8 +++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vm_operations_struct.m4 | 35 +++++++++++++++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 45 ++++++++++++++++--- include/drm/ttm/ttm_bo.h | 16 +++++++ 5 files changed, 99 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index cc97f392c90af..cbd0d109ea883 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -128,9 +128,15 @@ static void kfd_doorbell_close(struct vm_area_struct *vma) mutex_unlock(&pdd->qpd.doorbell_lock); } +#ifdef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) { - struct kfd_process_device *pdd = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#else +static int kfd_doorbell_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#endif + struct kfd_process_device *pdd = vma->vm_private_data; if (!pdd) return VM_FAULT_SIGBUS; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bae8699fb36fa..faf8024a2e334 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,6 +27,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT + AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 new file mode 100644 index 0000000000000..9e01b9fb9f36b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v4.10-9602-g11bac8000449 +dnl # mm, fs: reduce fault, page_mkwrite, and pfn_mkwrite to take only vmf +dnl # +AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf) = 0; + struct vm_operations_struct *vm_ops = NULL; + vm_ops->fault(NULL); + ], [ + AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, + [vm_operations_struct->fault() wants 1 arg]) + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vam} is available]) + ], [ + dnl # + dnl # commit v4.9-7746-g82b0f8c39a38 + dnl # mm: join struct fault_env and vm_fault + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct vm_fault *ptest = NULL; + ptest->address = 0; + ptest->vma = NULL; + ], [ + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vam} is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index c3a30b37437bb..5671add1ffd8a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -41,7 +41,8 @@ #include static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, - struct vm_fault *vmf) + struct vm_fault *vmf, + struct vm_area_struct *vma) { long err = 0; @@ -61,7 +62,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, return VM_FAULT_RETRY; drm_gem_object_get(&bo->base); - mmap_read_unlock(vmf->vma->vm_mm); + mmap_read_unlock(vma->vm_mm); (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); @@ -115,9 +116,17 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, * VM_FAULT_RETRY if blocking wait. * VM_FAULT_NOPAGE if blocking wait and retrying was not allowed. */ +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf) + struct vm_fault *vmf, + struct vm_area_struct *vma) { +#else +vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, + struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; +#endif /* * Work around locking order reversal in fault / nopfn * between mmap_lock and bo_reserve: Perform a trylock operation @@ -133,7 +142,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, if (fault_flag_allow_retry_first(vmf->flags)) { if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { drm_gem_object_get(&bo->base); - mmap_read_unlock(vmf->vma->vm_mm); + mmap_read_unlock(vma->vm_mm); if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) dma_resv_unlock(amdkcl_ttm_resvp(bo)); @@ -180,11 +189,19 @@ EXPORT_SYMBOL(ttm_bo_vm_reserve); * VM_FAULT_OOM on out-of-memory * VM_FAULT_RETRY if retryable wait */ +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, + struct vm_area_struct *vma, + pgprot_t prot, + pgoff_t num_prefault) +{ +#else vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; unsigned long page_offset; unsigned long page_last; @@ -194,13 +211,17 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, int err; pgoff_t i; vm_fault_t ret = VM_FAULT_NOPAGE; +#ifndef HAVE_VM_FAULT_ADDRESS_VMA + unsigned long address = (unsigned long)vmf->virtual_address; +#else unsigned long address = vmf->address; +#endif /* * Wait for buffer data in transit, due to a pipelined * move. */ - ret = ttm_bo_vm_fault_idle(bo, vmf); + ret = ttm_bo_vm_fault_idle(bo, vmf, vma); if (unlikely(ret != 0)) return ret; @@ -318,21 +339,35 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) } EXPORT_SYMBOL(ttm_bo_vm_dummy_page); +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; vm_fault_t ret; pgprot_t prot; int idx; +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_reserve(bo, vmf, vma); +#else ret = ttm_bo_vm_reserve(bo, vmf); +#endif if (ret) return ret; prot = vma->vm_page_prot; if (drm_dev_enter(bo->base.dev, &idx)) { + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_fault_reserved(vmf, vma, prot, TTM_BO_VM_NUM_PREFAULT); +#else ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); +#endif drm_dev_exit(idx); } else { ret = ttm_bo_vm_dummy_page(vmf, prot); diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 20ae857eb7a3a..71ed1026d0933 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -39,6 +39,7 @@ #include "ttm_device.h" #ifndef HAVE_CONFIG_H #define HAVE_DRM_GEM_OBJECT_RESV 1 +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 #endif /* Default number of pre-faulted pages in the TTM fault handler */ @@ -439,12 +440,27 @@ int ttm_bo_evict_first(struct ttm_device *bdev, struct ttm_operation_ctx *ctx); int ttm_bo_access(struct ttm_buffer_object *bo, unsigned long offset, void *buf, int len, int write); + +#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault); vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); +#else +vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, + struct vm_fault *vmf, + struct vm_area_struct *vma); + +vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, + struct vm_area_struct *vma, + pgprot_t prot, + pgoff_t num_prefault); + +vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf); +#endif + void ttm_bo_vm_open(struct vm_area_struct *vma); void ttm_bo_vm_close(struct vm_area_struct *vma); int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned long addr, From df99bf1878e4fcb19f2c12e61fb986e4afed0023 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:58:05 +0800 Subject: [PATCH 0448/2070] drm/amdkcl: Test whether drm_mm_print is available v1: drm/amdkcl: Test whether drm_debug_printer() function is available v2: drm/amdkcl: fix the struct drm_printer error. v3: drm/amdkcl: fix drm_printer related checks v4: drm/amdkcl: accommodate to drmP.h removal for drm-mm-print.m4 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Slava Grigorev Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Change-Id: I66988af2c3ae0af9782f278edebaaafbccd3fa30 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/drm/ttm/ttm_resource.h | 4 ++++ 6 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 9b0bcf6aca445..bdfac8d7f8afa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -295,12 +295,20 @@ static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, +#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) +#else + const char *prefix) +#endif { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); spin_lock(&mgr->lock); +#if defined(HAVE_DRM_MM_PRINT) drm_mm_print(&mgr->mm, printer); +#else + drm_mm_debug_table(&mgr->mm, prefix); +#endif spin_unlock(&mgr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fd86f0adde6b7..24b79559ad63c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2984,7 +2984,6 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) } #if defined(CONFIG_DEBUG_FS) - static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) { struct amdgpu_device *adev = m->private; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 9d934c07fa6b8..71a024217a8b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -874,7 +874,11 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, +#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) +#else + const char *prefix) +#endif { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct drm_buddy *mm = &mgr->mm; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 new file mode 100644 index 0000000000000..2d1d63b131ce7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit b5c3714fe8789745521d8351d75049b9c6a0d26b +dnl # drm/mm: Convert to drm_printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MM_PRINT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_mm_print(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_MM_PRINT, 1, [drm_mm_print() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index faf8024a2e334..d1a5a2f35cb78 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,6 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT + AC_AMDGPU_DRM_MM_PRINT AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 05dbaead88ae7..5733a161e8c79 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -178,8 +178,12 @@ struct ttm_resource_manager_func { * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ +#if defined(HAVE_DRM_MM_PRINT) void (*debug)(struct ttm_resource_manager *man, struct drm_printer *printer); +#else + void (*debug)(struct ttm_resource_manager *man, const char *prefix); +#endif }; /** From 0feeb53f39778a6c522b5f7e36d93dd945384e3e Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 30 Jul 2019 08:58:34 +0800 Subject: [PATCH 0449/2070] drm/amdkcl: add sync obj macros clean amdgpu_cs.c code v1: drm/amdkcl: remove DRIVER_SYNCOBJ_TIMELINE in kms_driver v2: sync with mainline v3: drm/amdkcl: add HAVE_CHUNK_ID_SYNOBJ_IN_OUT in amdgpu_cs_post_dep v4: drm/amd/autoconf: fix CHUNK_ID_SCHEDULED_DEPENDENCIES check error v5: drm/amdkcl: drop kcl_drm_syncobj_find_fence Signed-off-by: Yifan Zhang Signed-off-by: Adam Yang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Acked-by: Feifei Xu / --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++-- .../dkms/m4/chunk-id-scheduled-dependencies.m4 | 16 ++++++++++++++++ .../m4/chunk-id-syncobj-timeline-wait-signal.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ 5 files changed, 51 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 3fafa90b4f585..e41efb649485e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -264,12 +264,15 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, case AMDGPU_CHUNK_ID_DEPENDENCIES: case AMDGPU_CHUNK_ID_SYNCOBJ_IN: case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: break; - default: goto free_partial_kdata; } @@ -587,6 +590,7 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, return 0; } +#endif static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, struct amdgpu_cs_chunk *chunk) @@ -1272,6 +1276,7 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) int i; for (i = 0; i < p->num_post_deps; ++i) { +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) if (p->post_deps[i].chain && p->post_deps[i].point) { drm_syncobj_add_point(p->post_deps[i].syncobj, p->post_deps[i].chain, @@ -1281,6 +1286,10 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) drm_syncobj_replace_fence(p->post_deps[i].syncobj, p->fence); } +#else + drm_syncobj_replace_fence(p->post_deps[i].syncobj, + p->fence); +#endif } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 8fe3eb11244ee..bab5e16243f5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3102,8 +3102,12 @@ static const struct drm_driver amdgpu_kms_driver = { .driver_features = DRIVER_ATOMIC | DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_RENDER | DRIVER_MODESET + | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .ioctls = amdgpu_ioctls_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 new file mode 100644 index 0000000000000..c1075f2a16d7f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 @@ -0,0 +1,16 @@ +dnl # commit 67dd1a36334ffce82bebeb2d633e152aa436d370 +dnl # drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifndef AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + #error AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES not #defined + #endif + ], [ + AC_DEFINE(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES, 1, + [whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 new file mode 100644 index 0000000000000..1ae2aee78530f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 @@ -0,0 +1,17 @@ +dnl # commit 2624dd154bcc53ac2de16ecae9746ba867b6ca70 +dnl # drm/amdgpu: add timeline support in amdgpu CS v3 +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT) ||\ + !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL) + #error CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL not #defined + #endif + ], [ + AC_DEFINE(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, 1, + [whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d1a5a2f35cb78..116076bfd882b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -49,6 +49,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT + AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From 51eb60d999270f87e68bfe65ac49231600ab6c5e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 20:31:21 +0800 Subject: [PATCH 0450/2070] drm/amdkcl: test drm_fb_helper_init() Signed-off-by: Flora Cui Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 400 ++++++++++++++++++ .../gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 | 35 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 436 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c new file mode 100644 index 0000000000000..2b3ae83638ca1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -0,0 +1,400 @@ +/* + * Copyright © 2007 David Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * David Airlie + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "amdgpu.h" +#include "cikd.h" +#include "amdgpu_gem.h" + +#include "amdgpu_display.h" + +/* object hierarchy - + this contains a helper + a amdgpu fb + the helper contains a pointer to amdgpu framebuffer baseclass. +*/ + +static int +amdgpufb_open(struct fb_info *info, int user) +{ + struct drm_fb_helper *fb_helper = info->par; + int ret = pm_runtime_get_sync(fb_helper->dev->dev); + if (ret < 0 && ret != -EACCES) { + pm_runtime_mark_last_busy(fb_helper->dev->dev); + pm_runtime_put_autosuspend(fb_helper->dev->dev); + return ret; + } + return 0; +} + +static int +amdgpufb_release(struct fb_info *info, int user) +{ + struct drm_fb_helper *fb_helper = info->par; + + pm_runtime_mark_last_busy(fb_helper->dev->dev); + pm_runtime_put_autosuspend(fb_helper->dev->dev); + return 0; +} + +static const struct fb_ops amdgpufb_ops = { + .owner = THIS_MODULE, + DRM_FB_HELPER_DEFAULT_OPS, + .fb_open = amdgpufb_open, + .fb_release = amdgpufb_release, + .fb_fillrect = drm_fb_helper_cfb_fillrect, + .fb_copyarea = drm_fb_helper_cfb_copyarea, + .fb_imageblit = drm_fb_helper_cfb_imageblit, +}; + + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) +{ + int aligned = width; + int pitch_mask = 0; + + switch (cpp) { + case 1: + pitch_mask = 255; + break; + case 2: + pitch_mask = 127; + break; + case 3: + case 4: + pitch_mask = 63; + break; + } + + aligned += pitch_mask; + aligned &= ~pitch_mask; + return aligned * cpp; +} + +static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); + int ret; + + ret = amdgpu_bo_reserve(abo, true); + if (likely(ret == 0)) { + amdgpu_bo_kunmap(abo); + amdgpu_bo_unpin(abo); + amdgpu_bo_unreserve(abo); + } + drm_gem_object_put(gobj); +} + +static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object **gobj_p) +{ + const struct drm_format_info *info; + struct amdgpu_device *adev = rfbdev->adev; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *abo = NULL; + bool fb_tiled = false; /* useful for testing */ + u32 tiling_flags = 0, domain; + int ret; + int aligned_size, size; + int height = mode_cmd->height; + u32 cpp; + u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED; + + info = drm_get_format_info(adev_to_drm(adev), mode_cmd); + cpp = info->cpp[0]; + + /* need to align pitch with crtc limits */ + mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, + fb_tiled); + domain = amdgpu_display_supported_domains(adev, flags); + height = ALIGN(mode_cmd->height, 8); + size = mode_cmd->pitches[0] * height; + aligned_size = ALIGN(size, PAGE_SIZE); + ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, + ttm_bo_type_device, NULL, &gobj); + if (ret) { + pr_err("failed to allocate framebuffer (%d)\n", aligned_size); + return -ENOMEM; + } + abo = gem_to_amdgpu_bo(gobj); + + if (fb_tiled) + tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); + + ret = amdgpu_bo_reserve(abo, false); + if (unlikely(ret != 0)) + goto out_unref; + + if (tiling_flags) { + ret = amdgpu_bo_set_tiling_flags(abo, + tiling_flags); + if (ret) + dev_err(adev->dev, "FB failed to set tiling flags\n"); + } + + ret = amdgpu_bo_pin(abo, domain); + if (ret) { + amdgpu_bo_unreserve(abo); + goto out_unref; + } + + ret = amdgpu_ttm_alloc_gart(&abo->tbo); + if (ret) { + amdgpu_bo_unreserve(abo); + dev_err(adev->dev, "%p bind failed\n", abo); + goto out_unref; + } + + ret = amdgpu_bo_kmap(abo, NULL); + amdgpu_bo_unreserve(abo); + if (ret) { + goto out_unref; + } + + *gobj_p = gobj; + return 0; +out_unref: + amdgpufb_destroy_pinned_object(gobj); + *gobj_p = NULL; + return ret; +} + +static int amdgpufb_create(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; + struct amdgpu_device *adev = rfbdev->adev; + struct fb_info *info; + struct drm_framebuffer *fb = NULL; + struct drm_mode_fb_cmd2 mode_cmd; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *abo = NULL; + int ret; + + memset(&mode_cmd, 0, sizeof(mode_cmd)); + mode_cmd.width = sizes->surface_width; + mode_cmd.height = sizes->surface_height; + + if (sizes->surface_bpp == 24) + sizes->surface_bpp = 32; + + mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, + sizes->surface_depth); + + ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); + if (ret) { + DRM_ERROR("failed to create fbcon object %d\n", ret); + return ret; + } + + abo = gem_to_amdgpu_bo(gobj); + + /* okay we have an object now allocate the framebuffer */ + info = drm_fb_helper_alloc_fbi(helper); + if (IS_ERR(info)) { + ret = PTR_ERR(info); + goto out; + } + + ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, + &mode_cmd, gobj); + if (ret) { + DRM_ERROR("failed to initialize framebuffer %d\n", ret); + goto out; + } + + fb = &rfbdev->rfb.base; + + /* setup helper */ + rfbdev->helper.fb = fb; + + info->fbops = &amdgpufb_ops; + + info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); + info->fix.smem_len = amdgpu_bo_size(abo); + info->screen_base = amdgpu_bo_kptr(abo); + info->screen_size = amdgpu_bo_size(abo); + + drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); + + /* setup aperture base/size for vesafb takeover */ + info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; + info->apertures->ranges[0].size = adev->gmc.aper_size; + + /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ + + if (info->screen_base == NULL) { + ret = -ENOSPC; + goto out; + } + + DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); + DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); + DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); + DRM_INFO("fb depth is %d\n", fb->format->depth); + DRM_INFO("pitch is %d\n", fb->pitches[0]); + + vga_switcheroo_client_fb_set(adev->pdev, info); + return 0; + +out: + if (abo) { + + } + if (fb && ret) { + drm_gem_object_put(gobj); + drm_framebuffer_unregister_private(fb); + drm_framebuffer_cleanup(fb); + kfree(fb); + } + return ret; +} + +static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) +{ + struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + int i; + + drm_fb_helper_unregister_fbi(&rfbdev->helper); + + if (rfb->base.obj[0]) { + for (i = 0; i < rfb->base.format->num_planes; i++) + drm_gem_object_put(rfb->base.obj[0]); + amdgpufb_destroy_pinned_object(rfb->base.obj[0]); + rfb->base.obj[0] = NULL; + drm_framebuffer_unregister_private(&rfb->base); + drm_framebuffer_cleanup(&rfb->base); + } + drm_fb_helper_fini(&rfbdev->helper); + + return 0; +} + +static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { + .fb_probe = amdgpufb_create, +}; + +int amdgpu_fbdev_init(struct amdgpu_device *adev) +{ + struct amdgpu_fbdev *rfbdev; + int bpp_sel = 32; + int ret; + + /* don't init fbdev on hw without DCE */ + if (!adev->mode_info.mode_config_initialized) + return 0; + + /* don't init fbdev if there are no connectors */ + if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) + return 0; + + /* select 8 bpp console on low vram cards */ + if (adev->gmc.real_vram_size <= (32*1024*1024)) + bpp_sel = 8; + + rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); + if (!rfbdev) + return -ENOMEM; + + rfbdev->adev = adev; + adev->mode_info.rfbdev = rfbdev; + + drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, + &amdgpu_fb_helper_funcs); + +#if defined(HAVE_DRM_FB_HELPER_INIT_2ARGS) + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); +#elif defined(HAVE_DRM_FB_HELPER_INIT_3ARGS) + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, + AMDGPUFB_CONN_LIMIT); +#else + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, + adev->mode_info.num_crtc, AMDGPUFB_CONN_LIMIT); +#endif + + if (ret) { + kfree(rfbdev); + return ret; + } + + /* disable all the possible outputs/crtcs before entering KMS mode */ + if (!amdgpu_device_has_dc_support(adev)) + drm_helper_disable_unused_functions(adev_to_drm(adev)); + + drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); + return 0; +} + +void amdgpu_fbdev_fini(struct amdgpu_device *adev) +{ + if (!adev->mode_info.rfbdev) + return; + + amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); + kfree(adev->mode_info.rfbdev); + adev->mode_info.rfbdev = NULL; +} + +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) +{ + if (adev->mode_info.rfbdev) + drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, + state); +} + +int amdgpu_fbdev_total_size(struct amdgpu_device *adev) +{ + struct amdgpu_bo *robj; + int size = 0; + + if (!adev->mode_info.rfbdev) + return 0; + + robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); + size += amdgpu_bo_size(robj); + return size; +} + +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) +{ + if (!adev->mode_info.rfbdev) + return false; + if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) + return true; + return false; +} diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 new file mode 100644 index 0000000000000..8c0d4b9e932ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v5.6-rc2-1021-g2dea2d118217 +dnl # drm: Remove unused arg from drm_fb_helper_init +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + drm_fb_helper_init(NULL, NULL); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_2ARGS, 1, + [drm_fb_helper_init() has 2 args]) + ], [ + dnl # + dnl # commit v4.10-rc5-1046-ge4563f6ba717 + dnl # drm: Rely on mode_config data for fb_helper initialization + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + drm_fb_helper_init(NULL, NULL, 0); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_3ARGS, 1, + [drm_fb_helper_init() has 3 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 116076bfd882b..767dd3a49a1fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -60,6 +60,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO + AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From 70aa221cb07210a9b1a8d8dd6a45429ddbb7534c Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 13 Aug 2018 17:21:10 +0800 Subject: [PATCH 0451/2070] drm/amdkcl: [4.16] fix drm .last code, .output_poll_changed conflict .last_close and .output_poll_changed helpers are introduced in the same commit v4.14-rc3-576-g304a4f6accac drm_fb_helper_output_poll_changed & drm_fb_helper_lastclose can't be in amdkcl like other nonexistent symbols because there's no way to get fb_helper pointer from drm_device. amdgpu_device is required to get fb_helper pointer in this case. drm_device->fb_helper is introduced in v4.14-rc3-575-g29ad20b22c8f. and the 2 helper are introduced in v4.14-rc3-576-g304a4f6accac. Squash of 9d340fac6ea4 drm/amdkcl: add drm_fb_helper_output_poll_changed & drm_fb_helper_lastclose 686ea5e4ffe8 drm/amdkcl: refactor check for HAVE_DRM_FB_HELPER_LASTCLOSE 9c3af6d1cc70 drm/amdkcl: [4.16] fix drm .last code, .output_poll_changed conflict ae16f355fd44 drm/amdkcl: Test whether drm_fb_helper_lastclose is available 394828020901 drm/amdkcl: fix license for kcl backport part Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4094df27db833..2ba252f5828ba 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -45,5 +45,6 @@ #include #include #include +#include "kcl/kcl_amdgpu_drm_fb_helper.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h new file mode 100644 index 0000000000000..7b5938a2cd3ce --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H + +#include + +#ifndef HAVE_DRM_FB_HELPER_LASTCLOSE +void drm_fb_helper_lastclose(struct drm_device *dev); +void drm_fb_helper_output_poll_changed(struct drm_device *dev); +#endif +#endif From 0952cb2d7ac353a46e1ded9d676023c87e088dd5 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 15 Aug 2018 17:21:02 +0800 Subject: [PATCH 0452/2070] drm/amdkcl: fake drm_gem_fb_get_obj & kcl_drm_gem_fb_set_obj drm_gem_fb_get_obj() is introdued in v4.13-rc2-421-g4c3dbb2c312c. same with include/drm/drm_gem_framebuffer_helper.h fake a kcl copy for legacy kernel. Squash of e1357d7a01b8 drm/amdkcl: fake drm_gem_fb_get_obj & kcl_drm_gem_fb_set_obj c5ec212d2f24 drm/amdkcl: [4.14] fix drm_gem_object compile error Reviewed-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I2c087d77e289caabc6f5215f2bd54dc0e33e634e Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 8 ++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++--- .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 21 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 8 files changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 956f23fbbe421..5f45e997f6910 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -217,13 +217,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; /* schedule unpin of the old buffer */ - obj = crtc->primary->fb->obj[0]; + obj = drm_gem_fb_get_obj(crtc->primary->fb, 0); /* take a reference to the old object */ work->old_abo = gem_to_amdgpu_bo(obj); amdgpu_bo_ref(work->old_abo); - obj = fb->obj[0]; + obj = drm_gem_fb_get_obj(fb, 0); new_abo = gem_to_amdgpu_bo(obj); /* pin the new buffer */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 2b3ae83638ca1..24738cf5f0fad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -288,15 +288,17 @@ static int amdgpufb_create(struct drm_fb_helper *helper, static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) { struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + struct drm_gem_object *obj = NULL; int i; drm_fb_helper_unregister_fbi(&rfbdev->helper); + obj = drm_gem_fb_get_obj(&rfb->base, 0); if (rfb->base.obj[0]) { for (i = 0; i < rfb->base.format->num_planes; i++) drm_gem_object_put(rfb->base.obj[0]); amdgpufb_destroy_pinned_object(rfb->base.obj[0]); - rfb->base.obj[0] = NULL; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); } @@ -385,7 +387,7 @@ int amdgpu_fbdev_total_size(struct amdgpu_device *adev) if (!adev->mode_info.rfbdev) return 0; - robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); + robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0)); size += amdgpu_bo_size(robj); return size; } @@ -394,7 +396,7 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { if (!adev->mode_info.rfbdev) return false; - if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) + if (robj == gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0))) return true; return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index dc8d2f52c7d61..623f31939885c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -298,6 +298,9 @@ struct amdgpu_display_funcs { struct amdgpu_framebuffer { struct drm_framebuffer base; +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + struct drm_gem_object *obj; +#endif uint64_t tiling_flags; bool tmz_surface; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 61302204e9b4f..3a9c28b5bf9f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1865,7 +1865,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2064,7 +2064,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2550,7 +2550,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 8f4b4c2e36b9c..a8732183a680d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1902,7 +1902,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2079,7 +2079,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2518,7 +2518,7 @@ static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 9d1853c41fcd1..3a3fef7401b7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1812,7 +1812,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -1991,7 +1991,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2469,7 +2469,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 7b5938a2cd3ce..7e316b60c45f9 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -31,9 +31,30 @@ #define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H #include +#include +#include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif + +static inline +void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) +{ +#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + if (fb) + fb->obj[index] = obj; +#else + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)index; /* for compile un-used warning */ + if (afb) + afb->obj = obj; +#endif +} +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane); +#endif + #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 091fa7c151f58..f184fbaa04ff6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1032,7 +1032,7 @@ static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, if (!old_state->fb) return; - rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(old_state->fb, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { DRM_ERROR("failed to reserve rbo before unpin\n"); From feb99b4a20e98f1f69ea15c032705b7a27357b95 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 15 Jun 2020 15:36:36 +0800 Subject: [PATCH 0453/2070] drm/amdkcl: fake drm_gem_fb_destroy & drm_gem_fb_create_handle the 2 api are introduced in commit v4.13-rc2-421-g4c3dbb2c312c, could leverage test for drm/drm_gem_framebuffer_helper.h Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I55b7e056751e522ef827cadb905468675e342d96 --- .../drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 7e316b60c45f9..40a89aea46e78 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -55,6 +55,9 @@ void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_ge #ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, unsigned int plane); +void drm_gem_fb_destroy(struct drm_framebuffer *fb); +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle); #endif #endif From a77436b35aa18e1502ada5562bce480269147621 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 10:29:27 +0800 Subject: [PATCH 0454/2070] drm/amdkcl: test drm_device->driver_features Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 18 +++++++++++++--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 21 +++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index bab5e16243f5e..26e050cb6fbd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2450,8 +2450,17 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; +#else + /* warn the user if they mix atomic and non-atomic capable GPUs */ + if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) + DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); + /* support atomic early so the atomic debugfs stuff gets created */ + if (supports_atomic) + kms_driver.driver_features |= DRIVER_ATOMIC; +#endif kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); @@ -3100,9 +3109,12 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { static const struct drm_driver amdgpu_kms_driver = { .driver_features = - DRIVER_ATOMIC | - DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET + 0 +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES + | DRIVER_ATOMIC +#endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + | DRIVER_GEM + | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ #ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE | DRIVER_SYNCOBJ_TIMELINE diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 767dd3a49a1fc..5940f75f096da 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -51,6 +51,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MM_PRINT AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL + AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 new file mode 100644 index 0000000000000..73fd46cf9315c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.19-rc1-194-g18ace11f87e6 +dnl # drm: Introduce per-device driver_features +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->driver_features = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, + [dev_device->driver_features is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + ]) +]) From f6e8af5b5462d2d81608d70660772cf696e269be Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 16:37:51 +0800 Subject: [PATCH 0455/2070] drm/amdkcl: Test whether drm_driver->driver_features available test whether DRIVER_ATOMIC/DRIVER_SYNCOBJ_TIMELINE/DRIVER_IRQ_SHARED are available v1: drm/amdkcl: acommodate drmP.h drop for drm-driver-feature.m4 v2: drm/amdkcl: test DRIVER_PRIME is available Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++ .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 78 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 88 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 26e050cb6fbd9..3e2954d950471 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2450,6 +2450,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); +#ifdef HAVE_DRM_DRV_DRIVER_ATOMIC #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; @@ -2460,6 +2461,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) kms_driver.driver_features |= DRIVER_ATOMIC; +#endif #endif kcl_pci_configure_extended_tags(pdev); @@ -3113,6 +3115,13 @@ static const struct drm_driver amdgpu_kms_driver = { #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES | DRIVER_ATOMIC #endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + | DRIVER_HAVE_IRQ +#ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED + | DRIVER_IRQ_SHARED +#endif /* HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ +#ifdef HAVE_DRM_DRV_DRIVER_PRIME + | DRIVER_PRIME +#endif /* HAVE_DRM_DRV_DRIVER_PRIME */ | DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 new file mode 100644 index 0000000000000..3afe53a169b8c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -0,0 +1,78 @@ +dnl # +dnl # commit 88a48e297b3a3bac6022c03babfb038f1a886cea +dnl # drm: add atomic properties +dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d +dnl # drm: Switch DRIVER_ flags to an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int _ = DRIVER_ATOMIC; + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ + drm_driver_feature DRIVER_ATOMIC is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ + drm_driver_feature DRIVER_ATOMIC is available]) + ]) + ]) + + dnl # + dnl # commit: 060cebb20cdbcd3185d593e7194fa7a738201817 + dnl # drm: introduce a capability flag for syncobj timeline support + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_SYNCOBJ_TIMELINE; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ]) + + dnl # + dnl # commit: 1ff494813bafa127ecba1160262ba39b2fdde7ba + dnl # drm/irq: Ditch DRIVER_IRQ_SHARED + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) + ]) + ]) + ]) + + dnl # + dnl # commit: v5.2-rc5-867-g0424fdaf883a + dnl # drm/prime: Actually remove DRIVER_PRIME everywhere + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5940f75f096da..19e6d902945c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -52,6 +52,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE + AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From 168000516bc78ad76e1c2fdc540a5206fec3ac2f Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:26:01 +0800 Subject: [PATCH 0456/2070] drm/amdkcl: test drm_device->open_count squash of b6521032d361 drm/amdkcl: fix drm/drm_device.h in m4 578fa0c102a1 drm/amdkcl: add AC_AMDGPU_STRUCT_DRM_DEVICE Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fac19292d4438..17be9c157ca5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2390,7 +2390,11 @@ static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ +#ifdef HAVE_DRM_DEVICE_OPEN_COUNT_INT + return dev->open_count == 0; +#else return atomic_read(&dev->open_count) == 0; +#endif } static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 73fd46cf9315c..7016ff6694c88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -14,8 +14,25 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ ]) ]) +dnl # +dnl # commit v5.5-rc2-1419-g7e13ad896484 +dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->open_count = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, + [drm_device->open_count is int]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) ]) From 912539aeffe904f1748360c3eb9cbfdb450079e5 Mon Sep 17 00:00:00 2001 From: Yintian Tao Date: Mon, 2 Mar 2020 17:09:57 +0800 Subject: [PATCH 0457/2070] drm/amdkcl: get drm_dev reference Before 4.18.0, drm_dev_unplug will confirm dev->open_count to detemine whether to call drm_dev_put(), it will raise the problem below. Therefore, to get drm_dev_reference ensure not release drm_device before amdgpu_driver_unload_kms(). [ 43.055735] ------------[ cut here ]------------ [ 43.055736] Memory manager not clean during takedown. [ 43.055777] WARNING: CPU: 1 PID: 2807 at /build/linux-hwe-9KJ07q/linux-hwe-4.18.0/drivers/gpu/drm/drm_mm.c:913 drm_mm_takedown+0x24/0x30 [drm] [ 43.055778] Modules linked in: amdgpu(OE-) amd_sched(OE) amdttm(OE) amdkcl(OE) amd_iommu_v2 drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_generic nfit kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm ghash_clmulni_intel snd_seq_midi snd_seq_midi_event pcbc snd_rawmidi snd_seq snd_seq_device aesni_intel snd_timer joydev aes_x86_64 crypto_simd cryptd glue_helper snd soundcore input_leds mac_hid serio_raw qemu_fw_cfg binfmt_misc sch_fq_codel nfsd auth_rpcgss nfs_acl lockd grace sunrpc parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic floppy usbhid psmouse hid i2c_piix4 e1000 pata_acpi [ 43.055819] CPU: 1 PID: 2807 Comm: modprobe Tainted: G OE 4.18.0-15-generic #16~18.04.1-Ubuntu [ 43.055820] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 [ 43.055830] RIP: 0010:drm_mm_takedown+0x24/0x30 [drm] [ 43.055831] Code: 84 00 00 00 00 00 0f 1f 44 00 00 48 8b 47 38 48 83 c7 38 48 39 c7 75 02 f3 c3 55 48 c7 c7 38 33 80 c0 48 89 e5 e8 1c 41 ec d0 <0f> 0b 5d c3 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41 [ 43.055857] RSP: 0018:ffffae33c1393d28 EFLAGS: 00010286 [ 43.055859] RAX: 0000000000000000 RBX: ffff9651b4a29800 RCX: 0000000000000006 [ 43.055860] RDX: 0000000000000007 RSI: 0000000000000096 RDI: ffff9651bfc964b0 [ 43.055861] RBP: ffffae33c1393d28 R08: 00000000000002a6 R09: 0000000000000004 [ 43.055861] R10: ffffae33c1393d20 R11: 0000000000000001 R12: ffff9651ba6cb000 [ 43.055863] R13: ffff9651b7f40000 R14: ffffffffc0de3a10 R15: ffff9651ba5c6460 [ 43.055864] FS: 00007f1d3c08d540(0000) GS:ffff9651bfc80000(0000) knlGS:0000000000000000 [ 43.055865] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 43.055866] CR2: 00005630a5831640 CR3: 000000012e274004 CR4: 00000000003606e0 [ 43.055870] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 43.055871] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 43.055871] Call Trace: [ 43.055885] drm_vma_offset_manager_destroy+0x1b/0x30 [drm] [ 43.055894] drm_gem_destroy+0x19/0x40 [drm] [ 43.055903] drm_dev_fini+0x7f/0x90 [drm] [ 43.055911] drm_dev_release+0x2b/0x40 [drm] [ 43.055919] drm_dev_unplug+0x64/0x80 [drm] [ 43.055994] amdgpu_pci_remove+0x39/0x70 [amdgpu] [ 43.055998] pci_device_remove+0x3e/0xc0 [ 43.056001] device_release_driver_internal+0x18a/0x260 [ 43.056003] driver_detach+0x3f/0x80 [ 43.056004] bus_remove_driver+0x59/0xd0 [ 43.056006] driver_unregister+0x2c/0x40 [ 43.056008] pci_unregister_driver+0x22/0xa0 [ 43.056087] amdgpu_exit+0x15/0x57c [amdgpu] [ 43.056090] __x64_sys_delete_module+0x146/0x280 [ 43.056094] do_syscall_64+0x5a/0x120 [ 43.056097] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 43.056098] RIP: 0033:0x7f1d3bbb31b7 v2: use < 4.19.0 instead of <= 4.18.0 v3: move the version check into kcl v4: drm_dev_unplug() drop ref change in commit bd53280ef042 ("drm/drv: Fix incorrect resolution of merge conflict") rework kcl wrapper for the ref change Squash of 7109e9b49244 drm/amdkcl: rework kcl wrapper for drm_dev_unplug() e8364b615641 drm/amdkcl: add kcl wrapper for drm_dev_unplug 4e12efdfbcd4 drm/amdkcl: get drm_dev reference Signed-off-by: Yintian Tao Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 2 +- include/kcl/backport/kcl_drm_drv.h | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 include/kcl/backport/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c11911f2dcbc8..4ef77c1846213 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -26,7 +26,7 @@ * Daniel Vetter */ #include -#include +#include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, diff --git a/include/kcl/backport/kcl_drm_drv.h b/include/kcl/backport/kcl_drm_drv.h new file mode 100644 index 0000000000000..dcc5c195b2d08 --- /dev/null +++ b/include/kcl/backport/kcl_drm_drv.h @@ -0,0 +1,52 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H__ +#define __KCL_BACKPORT_KCL_DRM_DRV_H__ + +/* + * v5.1-rc5-1150-gbd53280ef042 drm/drv: Fix incorrect resolution of merge conflict + * v5.1-rc2-5-g3f04e0a6cfeb drm: Fix drm_release() and device unplug + */ +#if DRM_VERSION_CODE < DRM_VERSION(5, 2, 0) +static inline +void _kcl_drm_dev_unplug(struct drm_device *dev) +{ + unsigned int prev, post; + + drm_dev_get(dev); + + prev = kref_read(&dev->ref); + drm_dev_unplug(dev); + post = kref_read(&dev->ref); + + if (prev == post) + drm_dev_put(dev); +} +#define drm_dev_unplug _kcl_drm_dev_unplug +#endif + +#endif From 6630692a92f59f226935af5ecd3cc06990fd0c60 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 14:38:11 +0800 Subject: [PATCH 0458/2070] drm/amdkcl: add AMDKCL_AMDGPU_DEBUGFS_CLEANUP for debugfs_cleanup. macro AMDKCL_AMDGPU_DEBUGFS_CLEANUP would be more friendly for hybrid branch maintaining. Signed-off-by: Flora Cui Acked-by: Feifei Xu Change-Id: I006ec85bf1e697d4fb5173023f4f4ee9e81bf286 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 19 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ include/kcl/backport/kcl_drm_backport.h | 8 ++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index aeb90708f2293..c582ed0e4e1fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -42,6 +42,25 @@ #if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) +void amdgpu_debugfs_cleanup(struct drm_minor *minor) +{ + struct drm_info_node *node, *tmp; + + if (!&minor->debugfs_root) + return; + + mutex_lock(&minor->debugfs_lock); + list_for_each_entry_safe(node, tmp, + &minor->debugfs_list, list) { + debugfs_remove(node->dent); + list_del(&node->list); + kfree(node); + } + mutex_unlock(&minor->debugfs_lock); +} +#endif + /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index e7b3c38e51864..79bfd1d1871ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -26,6 +26,11 @@ * Debugfs */ +#if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) +void amdgpu_debugfs_cleanup(struct drm_minor *minor); +#endif +#endif int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3e2954d950471..bfaf9029a105d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3131,6 +3131,12 @@ static const struct drm_driver amdgpu_kms_driver = { , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, +#if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) + .debugfs_cleanup = amdgpu_debugfs_cleanup, +#endif +#endif + .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 1450036960b9c..84ca7b867d62d 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -2,6 +2,14 @@ #ifndef AMDKCL_DRM_BACKPORT_H #define AMDKCL_DRM_BACKPORT_H +/* + * commit v4.10-rc3-539-g086f2e5cde74 + * drm: debugfs: Remove all files automatically on cleanup + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 11, 0) +#define AMDKCL_AMDGPU_DEBUGFS_CLEANUP +#endif + #if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) #define AMDKCL_AMDGPU_DMABUF_OPS #endif From 39202e92a5d33ea7dac2cd17b3ad1db10173d50e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 14:42:32 +0800 Subject: [PATCH 0459/2070] drm/amdkcl: for drm_crtc_funcs->get_vblank_timestamp() add vblank macros AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS it is a squash of: commit 56d1d766045efd0a35ec331be7f176482022ac58 Author: Yifan Zhang Date: Tue Aug 6 13:46:25 2019 +0800 drm/amdkcl: use unsigned pipe v1: drm/amdkcl: drop kcl_amdgpu.c v2: merge unsigned pipe check into get-scanout-position Change-Id: If81006bf54584b6aff68082e0f4be48d1758cd7c Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Flora Cui commit 5e00d69a73fb4c5c0f888dcdeaca25bd42add60b Author: Slava Grigorev Date: Fri Feb 7 16:13:47 2020 -0500 drm/amdkcl: introduce parallel autoconf tests execution Change-Id: Ifff3054a6cd9403a6a34135bf5fb942f5aa760f8 Signed-off-by: Slava Grigorev drm/amdkcl: Test whether get_scanout_position has flags v1: drm/amd/autoconf: add a missing GET_SCANOUT_POSITION_HAVE_FLAGS v2: drm/amd/autoconf: fix drm_driver->get_scanout_position v3: drm/amdkcl: fix drm_driver->get_vblank_timestamp v4: drm/amd/autoconf: fix kcl_amdgpu_get_vblank_timestamp_kms() v5: drm/amdkcl: fix missing amdgpu_get_vblank_timestamp_kms() v6: drm/amd/autoconf: test drm_calc_vbltimestamp_from_scanoutpos() v7: fix macro for amdgpu_get_vblank_timestamp_kms() v8: drm/amdkcl: fix check for drm_driver->get_vblank_timestamp v9: drm/amdkcl: accommodate to drmP.h removal for drm-calc-vbltimestamp-from-scanoutpos.m4 v10: drm/amdkcl: accommodate to drmP.h removal for get-vblank-timestamp-in-struct-drm-driver.m4 v11: drm/amdkcl: merge use-unsigned-pipe.m4 into get-scanout-position-in-struct-drm-driver.m4 v12: drm/amdkcl: accommodate to drmP.h removal for get-scanout-position-in-struct-drm-driver.m4 Signed-off-by: Yifan Zhang Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui History-1: v2.6.37-rc3-1-g27641c3f003e int (*get_scanout_position) (struct drm_device *dev, int crtc, int *vpos, int *hpos); v3.12-rc3-485-g8f6fce03ddaf - int *vpos, int *hpos); + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime); v4.3-rc2-44-g3bb403bf421b - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime); + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + ` const struct drm_display_mode *mode); v4.3-rc3-73-g88e72717c2de - int crtc, + unsigned int pipe, v4.11-rc7-1902-g1bf6ad622b9b - int (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, + bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, History-2: v2.6.37-rc3-1-g27641c3f003e introduce int (*get_vblank_timestamp) (struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags); v4.3-rc3-73-g88e72717c2de - int (*get_vblank_timestamp) (struct drm_device *dev, int crtc, + int (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, v4.11-rc7-1899-gd673c02c4bdb - int (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, v4.11-rc7-1900-g3fcdcb270936 - unsigned flags); + bool in_vblank_irq); v4.14-rc3-721-g67680d3c0464 - struct timeval *vblank_time, + ktime_t *vblank_time, History-3: v2.6.37-rc3-1-g27641c3f003e int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags, struct drm_crtc *refcrtc) v3.13-rc8-550-g7da903ef0485 - struct drm_crtc *refcrtc); + const struct drm_crtc *refcrtc, + const struct drm_display_mode *mode); v4.2-rc3-517-gcc1ef118fc09 - int crtc, + unsigned int pipe, v4.3-rc2-43-geba1f35dfe14 - const struct drm_crtc *refcrtc, History-4: v4.11-rc7-1899-gd673c02c4bdb -int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, +bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, v4.11-rc7-1900-g3fcdcb270936 - unsigned flags, + bool in_vblank_irq, v4.11-rc7-1902-g1bf6ad622b9b - bool in_vblank_irq, - const struct drm_display_mode *mode) + bool in_vblank_irq) v4.14-rc3-721-g67680d3c0464 - struct timeval *vblank_time, + ktime_t *vblank_time, Signed-off-by: Yifan Zhang Change-Id: I61cb503c47518e6f11769ec4382ba7984c6faa48 Signed-off-by: Flora Cui drm/amdkcl: rework test for drm_calc_vbltimestamp_from_scanoutpos Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 45 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 ++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 24 ++++++++++ 10 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 398443abc8e92..ae8bbd872003a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1606,6 +1606,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); + int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index bfaf9029a105d..7ab45c98a088f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3135,6 +3135,13 @@ static const struct drm_driver amdgpu_kms_driver = { #if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) .debugfs_cleanup = amdgpu_debugfs_cleanup, #endif +#endif +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, + .enable_vblank = kcl_amdgpu_enable_vblank_kms, + .disable_vblank = kcl_amdgpu_disable_vblank_kms, + .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, + .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, #endif .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 3a9c28b5bf9f4..3f8bc47b7871e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2478,10 +2478,12 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2665,7 +2667,9 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { .prepare = dce_v10_0_crtc_prepare, .commit = dce_v10_0_crtc_commit, .disable = dce_v10_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v10_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index a8732183a680d..7be80d57742bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2450,10 +2450,12 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2632,7 +2634,9 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { .prepare = dce_v6_0_crtc_prepare, .commit = dce_v6_0_crtc_commit, .disable = dce_v6_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v6_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 3a3fef7401b7e..b9f5d3ae3c4a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2397,10 +2397,12 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2591,7 +2593,9 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { .prepare = dce_v8_0_crtc_prepare, .commit = dce_v8_0_crtc_commit, .disable = dce_v8_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v8_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2ba252f5828ba..56189db5b0fb1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -46,5 +46,6 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h new file mode 100644 index 0000000000000..e66daebae09d9 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_H + +#include +#include "amdgpu.h" + +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_get_vblank_counter_kms(drm_crtc); +} + +static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int crtc) +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_enable_vblank_kms(drm_crtc); +} + +static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int crtc) +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_disable_vblank_kms(drm_crtc); +} + +static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); +} + +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, ktime_t *vblank_time, + bool in_vblank_irq) +{ + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); +} +#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 9fcd72d87d25b..cd086c24819d1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -578,10 +578,12 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, - .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif @@ -716,7 +718,9 @@ static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { .disable = amdgpu_dm_crtc_helper_disable, .atomic_check = amdgpu_dm_crtc_helper_atomic_check, .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 19e6d902945c5..29ba65f7f0ce9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -65,6 +65,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 new file mode 100644 index 0000000000000..31099519500e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -0,0 +1,24 @@ +dnl # +dnl # v5.5-rc2-1557-ge3eff4b5d91e drm/amdgpu: Convert to CRTC VBLANK callbacks +dnl # v5.5-rc2-1556-gea702333e567 drm/amdgpu: Convert to struct drm_crtc_helper_funcs.get_scanout_position() +dnl # v5.5-rc2-1555-g7fe3f0d15aac drm: Add get_vblank_timestamp() to struct drm_crtc_funcs +dnl # v5.5-rc2-1554-gf1e2b6371c12 drm: Add get_scanout_position() to struct drm_crtc_helper_funcs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_crtc_funcs *ptr = NULL; + ptr->get_vblank_timestamp(NULL, NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP, + 1, + [struct drm_crtc_funcs->get_vblank_timestamp() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +]) From 7884c46a47234e068827c2b7f2e4d421afc235ae Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Sep 2020 11:02:03 +0800 Subject: [PATCH 0460/2070] drm/amdkcl: test __drm_atomic_helper_crtc_reset() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 29ba65f7f0ce9..fbb232b43122e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -46,6 +46,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT From 84e26c19cdae4e23cd79bc0da2dc1749d4c415ff Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 19 Jun 2020 17:31:03 +0800 Subject: [PATCH 0461/2070] drm/amdkcl: check drm_connector_funcs->detect drm_connector_funcs->detect() is optional since commit v4.9-rc4-949-g949f08862d66 Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- include/kcl/kcl_drm_connector.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ac6c066aa3376..1da6773c7ee4b 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -26,6 +26,14 @@ #include #include +/* + * commit v4.9-rc4-949-g949f08862d66 + * drm: Make the connector .detect() callback optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) +#define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY +#endif + #ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY #define drm_connector_update_edid_property drm_mode_connector_update_edid_property #endif From df25db4d66dfae6d78f31b18a3404e3eb96e493e Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 29 Apr 2020 15:30:15 +0800 Subject: [PATCH 0462/2070] drm/amdkcl: repalce crtc->index with drm_crtc_index Reviewed-by: Feifei Xu Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 5f45e997f6910..d294b3e5d3342 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1732,7 +1732,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, stime, etime, mode); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 982a489ef8bef..27632f9a1e40f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1668,7 +1668,7 @@ void amdgpu_driver_release_kms(struct drm_device *dev) u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int vpos, hpos, stat; u32 count; @@ -1736,7 +1736,7 @@ u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); @@ -1753,7 +1753,7 @@ int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); From ff04f1cc6d38108bf6173377d0795d44607a212e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 14:41:17 +0800 Subject: [PATCH 0463/2070] drm/amdkcl: test whether drm_driver->release() is available introduced by v4.10-rc5-1045-gf30c92576af4 This patch is caused by 'drm/amdgpu: Embed drm_device into amdgpu_device (v2) Although v5.5-rc2-1531-ge62bf83aa1bb has removed checking on dev->dev_private, some distro with kernel v5.6+ (such as ubuntu20.04-oem) may still access dev->dev_private In case of accessing dev->dev_private in drm code, init dev->dev_private to amdgpu_device. Wrap this initialization with kcl inline function for easy tracking. Squash of 469aa26d1979 drm/amdkcl: fix reture val for faked __devm_drm_dev_alloc() af31a40bf581 drm/amdkcl: rework the faked __devm_drm_dev_alloc 312a6b63c4e9 drm/amdkcl: fake devm_drm_dev_alloc 2ec2a0da80d7 drm/amdkcl: always init drm_device.dev_private 22de9a4cefd6 drm/amdkcl: test whether drm_dev_fini() is available (v2) introduced by v5.5-rc2-1531-ge62bf83aa1bb f9896ea4089f drm/amdkcl: test whether drm checking on dev->dev_private d4300369d400 drm/amdkcl: test whether drm_dev_fini() is available Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Reviewed-by: Shiwu Zhang Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 ++++++++- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 2 + .../backport/include/kcl/kcl_amdgpu_drm_drv.h | 43 +++++++++++++++++++ drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 36 ++++++++++++++++ 6 files changed, 102 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_drv.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7ab45c98a088f..bf94766348c07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2467,7 +2467,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) +#ifndef AMDKCL_DEVM_DRM_DEV_ALLOC return ret; +#else + goto err_free; +#endif pci_set_drvdata(pdev, ddev); @@ -2564,6 +2568,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, err_pci: pci_disable_device(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +err_free: + amdkcl_drm_dev_release(ddev); +#endif return ret; } @@ -2577,7 +2585,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) amdgpu_xcp_dev_unplug(adev); amdgpu_gmc_prepare_nps_mode_change(adev); drm_dev_unplug(dev); - if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); @@ -2594,6 +2601,16 @@ amdgpu_pci_remove(struct pci_dev *pdev) pci_wait_for_pending_transaction(pdev); } +#ifndef HAVE_DRM_DRM_MANAGED_H +static void amdgpu_driver_release(struct drm_device *ddev) +{ + struct amdgpu_device *adev = drm_to_adev(ddev); + + drm_dev_fini(ddev); + kfree(adev); +} +#endif + static void amdgpu_pci_shutdown(struct pci_dev *pdev) { @@ -3136,6 +3153,7 @@ static const struct drm_driver amdgpu_kms_driver = { .debugfs_cleanup = amdgpu_debugfs_cleanup, #endif #endif + #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, .enable_vblank = kcl_amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 1ad8a02a4b19f..8880468d474a6 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := +BACKPORT_OBJS := kcl_drm_drv.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 56189db5b0fb1..bdf6f86b1012f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -47,5 +47,6 @@ #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" +#include "kcl/kcl_amdgpu_drm_drv.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index e66daebae09d9..30313214c72d2 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -4,6 +4,7 @@ #include #include "amdgpu.h" +#include #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) @@ -42,4 +43,5 @@ static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, u return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ + #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..926e4cd441519 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,43 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +void amdkcl_drm_dev_release(struct drm_device *ddev); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..0ad2345d7061a --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include "amdgpu.h" + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + drm = container + offset; + ret = drm_dev_init(drm, driver, parent); + if (ret) { + drm_dev_put(drm); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#endif + drm->dev_private = container; + return container; +} + +void amdkcl_drm_dev_release(struct drm_device *ddev) +{ + drm_dev_put(ddev); +} + +#endif From 581554cf58e46aff2695fc4cbd4461e0f1fc19be Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 14 Feb 2019 10:08:11 +0800 Subject: [PATCH 0464/2070] drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available drm_connector_for_each_possible_encoder was introduced by the below commit since 4.19-rc1, add kcl implement for older kernel. "drm: Add drm_connector_for_each_possible_encoder()" for_each_if is introduce from v4.5-rc1 . so it's not available on drm < 4.5 like rhel6.10 . v1: drm/amdkcl: [4.19] kcl for drm_connector_for_each_possible_encoder v2: drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available v3: drm_connector_for_each_possible_encoder Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 39 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++ ...drm-connector-for-each-possible-encoder.m4 | 20 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index d3e312bda4ede..6486c50a8b1ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -219,10 +219,15 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; + int i; best_encoder = connector_funcs->best_encoder(connector); +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if ((encoder == best_encoder) && (status == connector_status_connected)) connected = true; else @@ -237,8 +242,13 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type == encoder_type) return encoder; } @@ -323,9 +333,14 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; + int i; /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1105,8 +1120,13 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) continue; @@ -1155,8 +1175,13 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (amdgpu_connector->use_digital == true) { if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) return encoder; @@ -1171,7 +1196,11 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) /* then check use digitial */ /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1349,8 +1378,13 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); switch (amdgpu_encoder->encoder_id) { @@ -1369,9 +1403,14 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; + int i; bool found = false; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) found = true; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 77660736e03b4..7f6c3b9d33cd0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8536,6 +8536,7 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS struct drm_encoder *encoder; /* There is only one encoder per connector */ @@ -8543,6 +8544,9 @@ static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector * return encoder; return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif } static void amdgpu_dm_get_native_mode(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 new file mode 100644 index 0000000000000..0f57128fcf1a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.3-rc1-656-g62afb4ad425a +dnl # drm/connector: Allow max possible encoders to attach to a connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + drm_connector_for_each_possible_encoder(connector, encoder) + return 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS, 1, + [drm_connector_for_each_possible_encoder() wants 2 arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fbb232b43122e..fdead8c8af6f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 22987ec6067531782dc854a92f6c4a0ed7d689ba Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Fri, 20 Sep 2019 16:34:11 +0800 Subject: [PATCH 0465/2070] drm/amdkcl: Test drm_hdmi_avi_infoframe_from_display_mode() interface history v1: f6cdebf80917 Test whether drm_hdmi_avi_infoframe_from_display_mode() wants 2 args Signed-off-by: Adam Yang Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix drm_hdmi_avi_infoframe_from_display_mode 1. fix compile waring 2. remove extra "," Signed-off-by: Flora Cui Signed-off-by: Jack Gui Change-Id: I0b32a9991abed7088f72652740aa71604fe40b10 --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++ drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 | 35 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 3f8bc47b7871e..8fac16311a54a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1700,7 +1700,13 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, dce_v10_0_audio_write_sad_regs(encoder); dce_v10_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 7be80d57742bc..9c8fbf8e3f82e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1527,7 +1527,13 @@ static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, ssize_t err; u32 tmp; +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index b9f5d3ae3c4a6..476838197a375 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1652,7 +1652,13 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, dce_v8_0_audio_write_sad_regs(encoder); dce_v8_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7f6c3b9d33cd0..0341de86bc1c0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6685,12 +6685,18 @@ static void fill_stream_properties_from_drm_display_mode( } if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); if (err < 0) drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", connector->name, err); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in, false); +#else + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 new file mode 100644 index 0000000000000..02a5a8a2b5875 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # 13d0add333afea7b2fef77473232b10dea3627dd +dnl # drm/edid: Pass connector to AVI infoframe functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + struct drm_connector *connector = NULL; + const struct drm_display_mode *mode = NULL; + drm_hdmi_avi_infoframe_from_display_mode(frame, connector, mode); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface]) + ], [ + dnl # + dnl # 10a8512008655d5ce62f8c56323a6b5bd221c920 + dnl # drm: Add HDMI infoframe helpers + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + const struct drm_display_mode *mode = NULL; + bool is_hdmi2_sink = false; + drm_hdmi_avi_infoframe_from_display_mode(frame, mode, is_hdmi2_sink); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fdead8c8af6f7..ab9566d58e2ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_KERNEL_WAIT From 7428839c1fea62576d4d543a19bc7bd4bcc1fdc7 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 12 Jul 2019 14:49:19 +0800 Subject: [PATCH 0466/2070] drm/amdkcl: add AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER it is a squash of: drm/amdkcl: test whether drm/drm_audio_component.h is available [why] drm_audio_component.h is not defined before drm version 4.19.0. So there will be build error when using them before drm version 4.19.0. [How] Use autoconf way to check drm_audio_component_ops, drm_audio_component_audio_ops,drm_audio_component in kernel. If they are not defined,avoid to use them in driver code. This autoconf patch is caused by patch: drm/amd/display: Add drm_audio_component support to amdgpu_dm Change-Id: Ic75928406a042a0e08f5b06cf64543555c62e476 Signed-off-by: changzhu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jack Gui drm/amdkcl: correct drm_audio_component_header.m4 patten Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix check for drm/drm_audio_component.h Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun Change-Id: I7717d2f117361cfa3fa7a0f941e88ac3d99327b8 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++++ .../amd/dkms/m4/drm-audio-component-header.m4 | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c old mode 100644 new mode 100755 index 0341de86bc1c0..3d2830439f65e --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -77,7 +77,10 @@ #include #include #include + +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include +#endif #include #include @@ -93,7 +96,9 @@ #include #include #include +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include +#endif #include #ifdef CONFIG_DRM_AMD_DC_HDCP #include @@ -1106,6 +1111,7 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) @@ -1243,6 +1249,7 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) pin, -1); } } +#endif static int dm_dmub_hw_init(struct amdgpu_device *adev) { @@ -1894,7 +1901,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); + +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_init(&adev->dm.audio_lock); +#endif if (amdgpu_dm_irq_init(adev)) { drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); @@ -2319,7 +2329,9 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_destroy(&adev->dm.audio_lock); +#endif mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); } @@ -4898,12 +4910,14 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) } #endif +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) r = amdgpu_dm_audio_init(adev); if (r) { dc_state_release(state->context); kfree(state); return r; } +#endif return 0; } @@ -8920,7 +8934,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) aconnector->audio_inst = -1; +#endif aconnector->pack_sdp_v1_3 = false; aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); @@ -10254,6 +10270,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, kfree(bundle); } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { @@ -10334,6 +10351,7 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev, amdgpu_dm_audio_eld_notify(adev, inst); } } +#endif /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC @@ -11056,8 +11074,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->wb_enabled = true; } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); +#endif /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h old mode 100644 new mode 100755 index 8008136717482..3df5d5b13075d --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -463,6 +463,7 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /** * @audio_lock: * @@ -484,6 +485,7 @@ struct amdgpu_display_manager { * successfully, false otherwise. */ bool audio_registered; +#endif /** * @irq_handler_list_low_tab: @@ -814,8 +816,10 @@ struct amdgpu_dm_connector { */ int max_vfreq ; +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Audio instance - protected by audio_lock. */ int audio_inst; +#endif struct mutex hpd_lock; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 new file mode 100644 index 0000000000000..520d72bebcb5c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_audio_component.h], [ + AC_DEFINE(HAVE_DRM_AUDIO_COMPONENT_HEADER, 1, + [whether drm/drm_audio_component.h is defined]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ab9566d58e2ce..389234ec04fef 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_DMA_FENCE_HEADERS + AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION From fef72947b2b65f63c0f38e97ab0f291e3e102534 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 24 Sep 2019 13:30:02 +0800 Subject: [PATCH 0467/2070] drm/amdkcl: Test whether drm_mode_is_420_xxx() is available v2: drm/amdkcl: refactor kcl copy rm_mode_is_420_xxx v3: fix license for kcl drm part Change-Id: I3b71e9df855e8996d76a040ac6b650fdb52702fa Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I2797279336841ff551df87ec663ec384b01022ca --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 41 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++-- .../drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 | 17 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_modes.h | 39 ++++++++++++++++++ 7 files changed, 106 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 create mode 100644 include/kcl/kcl_drm_modes.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index aa8b11b1eedc4..4be64eea1ec80 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o + kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c new file mode 100644 index 0000000000000..bf57f999e4fc2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -0,0 +1,41 @@ +/* + * Copyright © 1997-2003 by The XFree86 Project, Inc. + * Copyright © 2007 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2005-2006 Luc Verhaegen + * Copyright (c) 2001, Andy Ritger aritger@nvidia.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ +#include +#include +#include + +#ifndef HAVE_DRM_MODE_IS_420_XXX +amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, + const struct drm_display_info *display, const struct drm_display_mode *mode) +amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, + const struct drm_display_info *display, const struct drm_display_mode *mode) +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bdf6f86b1012f..5fe005591056e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3d2830439f65e..2031de1b8120c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6458,6 +6458,11 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, { u8 bpc; + bpc = (uint8_t)connector->display_info.bpc; + /* Assume 8 bpc by default if no bpc is specified. */ + bpc = bpc ? bpc : 8; + +#ifdef HAVE_DRM_MODE_IS_420_XXX if (is_y420) { bpc = 8; @@ -6468,11 +6473,8 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, bpc = 12; else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; - } else { - bpc = (uint8_t)connector->display_info.bpc; - /* Assume 8 bpc by default if no bpc is specified. */ - bpc = bpc ? bpc : 8; } +#endif if (requested_bpc > 0) { /* diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 new file mode 100644 index 0000000000000..65c9ec9268e1b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 2570fe2586254ff174c2ba5a20dabbde707dbb9b +dnl # drm: add helper functions for YCBCR420 handling +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_IS_420_XXX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_is_420_only(NULL, NULL); + drm_mode_is_420_also(NULL, NULL); + ], [drm_mode_is_420_only drm_mode_is_420_also],[drivers/gpu/drm/drm_modes.c],[ + AC_DEFINE(HAVE_DRM_MODE_IS_420_XXX, 1, + [drm_mode_is_420_xxx() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 389234ec04fef..a44637ce16787 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -70,6 +70,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_MODE_IS_420_XXX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h new file mode 100644 index 0000000000000..c47d691ca6e7a --- /dev/null +++ b/include/kcl/kcl_drm_modes.h @@ -0,0 +1,39 @@ +/* + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_MODES_H +#define KCL_KCL_DRM_MODES_H + +#include + +#ifndef HAVE_DRM_MODE_IS_420_XXX +bool drm_mode_is_420_only(const struct drm_display_info *display, + const struct drm_display_mode *mode); +bool drm_mode_is_420_also(const struct drm_display_info *display, + const struct drm_display_mode *mode); +#endif + +#endif From de07f04fed9a026cefef74ae5e747015aa2924e4 Mon Sep 17 00:00:00 2001 From: Rui Teng Date: Mon, 23 Sep 2019 19:29:57 +0800 Subject: [PATCH 0468/2070] drm/amdkcl: check whether DEFINE_DEBUGFS_ATTRIBUTE is available DEFINE_DEBUGFS_ATTRIBUTE and debugfs_create_file_unsafe is introduced by kernel 4.7 - commit c64688081490321f2d23a292ef24e60bb321f3f1 - Author: Nicolai Stange - debugfs: add support for self-protecting attribute file fops Change-Id: Ia4c9ddf96d50a5eea76a28c6e8f3a012332f1f69 Signed-off-by: Rui Teng Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix compile error if DEFINE_DEBUGFS_ATTRIBUTE not defined Change-Id: I23277d6b9c298fb4325cc54b1ca7379e45b68d99 Signed-off-by: Stanley.Yang --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index d6d43f1bf6d25..97814849b0fe0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3152,8 +3152,10 @@ static int force_yuv420_output_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, force_yuv420_output_set, "%llu\n"); +#endif /* * Read Replay state @@ -3415,6 +3417,7 @@ static int dmcub_trace_event_state_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, dmcub_trace_event_state_set, "%llu\n"); @@ -3432,6 +3435,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); +#endif DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, ips_residency_cntl_set, "%llu\n"); @@ -3444,7 +3448,9 @@ static const struct { char *name; const struct file_operations *fops; } connector_debugfs_entries[] = { +#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"force_yuv420_output", &force_yuv420_output_fops}, +#endif {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, {"internal_display", &internal_display_fops}, {"odm_combine_segments", &odm_combine_segments_fops} @@ -3615,6 +3621,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) dp_debugfs_entries[i].fops); } } + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); @@ -3636,6 +3644,7 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); } +#endif for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { debugfs_create_file(connector_debugfs_entries[i].name, @@ -4105,8 +4114,10 @@ static int force_timing_sync_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, force_timing_sync_set, "%llu\n"); +#endif /* @@ -4244,8 +4255,10 @@ static int visual_confirm_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(mst_topo); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); +#endif /* @@ -4371,6 +4384,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); @@ -4411,4 +4425,5 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev, &ips_residency_fops); } +#endif } From 318c14d07a3372fde05a2a56a9101fe4baf3f369 Mon Sep 17 00:00:00 2001 From: chen gong Date: Thu, 16 May 2019 16:29:41 +0800 Subject: [PATCH 0469/2070] drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available drm/amdkcl: Test whether for_each_oldnew_plane_in_state() is defined Change-Id: Iff20a648d390ab976a5d98443ee6037b10968561 Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether for_each_oldnew_connector_in_state() is defined Change-Id: I7b2847ca6fc7e847ba9e06bc2e2e9173ef26e8cf Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether for_each_new_crtc_in_state() is defined Change-Id: Iedac8a5691e7bec594db95096259ff260d05b684 Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: add protection for for_each_new_crtc_in_state Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available drm/amdkcl: test for_each_new_crtc_in_state directly for_each_new_crtc_in_state is a macro which can be tested directly with #ifdef, save a m4 macro Change-Id: I747b753244b1b514ef4a2ad4c1e0cc8bd8fb1314 Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test for_each_oldnew_plane_in_state directly Change-Id: Ia1a265e35b690ecbf2620a235191c0f269c84fbf Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test for_each_oldnew_connector_in_state directly Change-Id: I054e2e8db8091d3aa63ebd38c350f2b219edae6c Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available Related commit: v4.12~21^2~8^2~134 - commit 581e49fe6b411f407102a7f2377648849e0fa37f - drm/atomic: Add new iterators over all state, v3 v4.17-rc2~1^2~24^2~13 - commit 55de2923847c3318459758931ff175996facce69 - drm/atomic: Add new reverse iterator over all plane state (V2) Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: rework for_each_oldnew_plane_in_state_reverse to fix install failure with ubuntu16.04.5 & phontom Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Change-Id: Ib4bb484bd839ddd20881f0e0d8166e24877124ab Signed-off-by: chen gong --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 31 +++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2031de1b8120c..a856425e22236 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10419,7 +10419,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, } for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { + new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); @@ -12505,9 +12505,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); - if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->color_mgmt_changed && old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 3df5d5b13075d..2b07277136a59 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -253,6 +253,31 @@ struct amdgpu_dm_backlight_caps { struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; +/** + * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic + * update in reverse order + * @__state: &struct drm_atomic_state pointer + * @plane: &struct drm_plane iteration cursor + * @old_plane_state: &struct drm_plane_state iteration cursor for the old state + * @new_plane_state: &struct drm_plane_state iteration cursor for the new state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all planes in an atomic update in reverse order, + * tracking both old and new state. This is useful in places where the + * state delta needs to be considered, for example in atomic check functions. + */ +#if !defined(for_each_oldnew_plane_in_state_reverse) && \ + defined(for_each_oldnew_plane_in_state) +#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ + for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ + (__i) >= 0; \ + (__i)--) \ + for_each_if ((__state)->planes[__i].ptr && \ + ((plane) = (__state)->planes[__i].ptr, \ + (old_plane_state) = (__state)->planes[__i].old_state,\ + (new_plane_state) = (__state)->planes[__i].new_state, 1)) +#endif + /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations @@ -267,6 +292,7 @@ struct dal_allocation { u64 gpu_addr; }; + /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work @@ -1119,7 +1145,12 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +#ifndef for_each_new_connector_in_state + struct drm_crtc *crtc, + bool from_state_var); +#else struct drm_crtc *crtc); +#endif int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); From 46d2429246b0fec0d88482813d8f908021539825 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 23:25:40 +0800 Subject: [PATCH 0470/2070] drm/amdkcl: test whether drm_dp_mst_allocate_vcpi() has p,p,i,i interface It's a squash of drm/amdkcl: Test whether drm_dp_mst_{get,put}_port_malloc() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I99ef7484b72edf3266bed3cd7cb0cc1db117f05d Signed-off-by: Adam Yang Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yang Xiong --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++ .../drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 45 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 5e92eaa67aa33..20346d4a5545c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -159,7 +159,9 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) drm_edid_free(aconnector->drm_edid); drm_connector_cleanup(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_put_port_malloc(aconnector->mst_output_port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ kfree(aconnector); } @@ -706,7 +708,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, */ amdgpu_dm_connector_funcs_reset(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_get_port_malloc(port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ return connector; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 new file mode 100644 index 0000000000000..2eee635844c96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -0,0 +1,45 @@ +dnl # +dnl # commit 1e797f556c616a42f1e039b1ff1d3c58f61b6104 +dnl # drm/dp: Split drm_dp_mst_allocate_vcpi +dnl # +dnl # Note: This autoconf only works with compiler flag -Werror +dnl # The interface types are specified in Hungarian notation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ + dnl # + dnl # commit d25689760b747287c6ca03cfe0729da63e0717f4 + dnl # drm/amdgpu/display: Keep malloc ref to MST port + dnl # + dnl # commit ebcc0e6b509108b4a67daa4c55809a05ab7f4b77 + dnl # drm/dp_mst: Introduce new refcounting scheme for mstbs and ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_get_port_malloc(NULL); + drm_dp_mst_put_port_malloc(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC, 1, [ + drm_dp_mst_{get,put}_port_malloc() is available]) + ]) + ]) + dnl # + dnl # commit aad0eab4e8dd76d1ba5248f9278633829cbcec38 + dnl # drm/dp_mst: Enable registration of AUX devices for MST ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_connector_early_unregister(NULL, NULL); + drm_dp_mst_connector_late_register(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + drm_dp_mst_connector_early_unregister() is available]) + AC_DEFINE(HAVE_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + drm_dp_mst_connector_late_register() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a44637ce16787..3c087f2d178a3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -71,6 +71,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX + AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e66300ad240fdca48467d84f05c5a2f77d4c9245 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 19 Apr 2019 13:58:42 +0800 Subject: [PATCH 0471/2070] drm/amdkcl: test whether struct drm_dp_mst_topology_cbs has hotplug drm/amdkcl: [5.1] Fix multiple MST daisy chain issues within DM [Why] This patch fixes the following issues: - Null pointer dereference was found with MST monitor attached - MST daisy chain hotplugging doesn't work [How] Until DRM Ver.5.0, we need a MST hotplug function to deal with MST hotplug operations. (this function is not needed since DRV Ver.5.1 rc1). Hence a MST hotplug function is added to avoid hotplug failure. (the old hotplug structure was replaced within DRV Ver.5.1) Signed-off-by: Zhan Liu Reviewed-by: Xiaojie Yuan Reviewed-by: Junwei Zhang drm/amdkcl: fix dm_dp_mst_hotplug custom kernel build error [Why] There is build error when using dm_dp_mst_hotplug to build custom kernel on dkms-5.0 branch [How] Avoid using dm_dp_mst_hotplug when building custom kernel on dkms-5.0 branch. This kcl patch is supplement for kcl patch: drm/amdkcl: [5.1] Fix multiple MST daisy chain issues within DM Change-Id: I827c06eee369f0b5468e8298376f8aea344c5533 Signed-off-by: changzhu Reviewed-by: Zhan Liu drm/amdkcl: test whether struct drm_dp_mst_topology_cbs has hotplug Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 31 ++++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 42 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 20346d4a5545c..028a432d6f577 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -824,8 +824,39 @@ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) +static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + + drm_kms_helper_hotplug_event(dev); +} +#endif + +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR +static void dm_dp_mst_register_connector(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (adev->mode_info.rfbdev) + drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); + else + DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); + + drm_connector_register(connector); +} +#endif + static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) + .hotplug = dm_dp_mst_hotplug, +#endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + .register_connector = dm_dp_mst_register_connector +#endif .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, }; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 new file mode 100644 index 0000000000000..5847b52020f9f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit v4.20-rc4-941-g16bff572cc66 +dnl # drm/dp-mst-helper: Remove hotplug callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->hotplug(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG, 1, + [struct drm_dp_mst_topology_cbs has hotplug member]) + ]) +]) + + +dnl # +dnl # commit v5.6-rc2-1065-ga5c4dc165957 +dnl # drm/dp_mst: Remove register_connector callback +dnl # +dnl # commit v4.3-rc3-39-gd9515c5ec1a2 +dnl # drm/dp/mst: split connector registration into two parts (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->register_connector(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->register_connector is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3c087f2d178a3..805646555cade 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,6 +72,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_DP_MST_TOPOLOGY + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From dba5a3b0536a20c7fa2e7dec673aade77b79df1e Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:52:25 +0800 Subject: [PATCH 0472/2070] drm/amdkcl: whether struct drm_atomic_state have async_update Change-Id: Ic9a0e4c28255e46fae3af23c0a12d0fbf6fccbf5 Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a856425e22236..0f9a1604e499b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12744,6 +12744,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } + /* Perform validation of MST topology in the state*/ + ret = drm_dp_mst_atomic_check(state); + if (ret) + goto fail; + if (state->legacy_cursor_update) { /* * This is a fast cursor update coming from the plane update From 70fe4f57c7288565c4f6f18d056c39e25da9eba5 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 27 Dec 2019 14:29:23 +0800 Subject: [PATCH 0473/2070] drm/amdkcl: Test whether drm_dp_mst_atomic_check() is available Change-Id: I6d5801df6e80e208e07e3806a031b8672d55e4d1 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0f9a1604e499b..94f7cbce65c32 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12744,10 +12744,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_STRUCT_NAME_CB_NAME_2ARGS) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) /* Perform validation of MST topology in the state*/ ret = drm_dp_mst_atomic_check(state); if (ret) goto fail; +#endif if (state->legacy_cursor_update) { /* @@ -12860,11 +12862,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * dc_validate_global_state(), or there is a chance * to get stuck in an infinite loop and hang eventually. */ +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); if (status != DC_OK) { drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 028a432d6f577..abbd9f07ab254 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -905,6 +905,8 @@ uint32_t dm_mst_get_pbn_divider(struct dc_link *link) return dfixed_const(pbn_div_x100) / 100; } +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; @@ -1827,6 +1829,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, return is_dsc_possible; } #endif +#endif /* HAVE_DRM_DP_MST_ATOMIC_CHECK */ #if defined(CONFIG_DRM_AMD_DC_FP) static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw) @@ -2020,3 +2023,4 @@ enum dc_status dm_dp_mst_is_port_support_mode( #endif return DC_OK; } +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 new file mode 100644 index 0000000000000..dc4167e33a865 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit eceae147246749c6dbaeefda802b30f804a3c54c +dnl # drm/dp_mst: Start tracking per-port VCPI allocations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_atomic_check(NULL); + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, + [drm_dp_mst_atomic_check() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 805646555cade..0b250d67b78f9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -73,6 +73,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 431958793a2c6fd4e8d86c4e4edac0ec99b16768 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Mon, 6 Jan 2020 14:59:32 +0800 Subject: [PATCH 0474/2070] drm/amdkcl: Test whether drm_dp_calc_pbn_mode() wants three arguments v2: drm/amdkcl: Test whether mul_u32_u32 is available v3: drm/amdkcl: move kcl copy for drm_dp_mst_helper into backport part the macros definition should be in backport to warn amdkcl to NOT include it. It is not necessary to wrap a mul_u32_u32() funcion, because function mul_u32_u32() is introdued into kernel before function drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc). Signed-off-by: Stanley.Yang Signed-off-by: Yifan Zhang Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 14 ++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 new file mode 100644 index 0000000000000..d168a591bcd23 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 9a7c0da823fd4e65098bd466a996503cc8309c0e +dnl # drm/dp_mst: Add PBN calculation for DSC modes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_calc_pbn_mode(0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, + [drm_dp_calc_pbn_mode() wants 3args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0b250d67b78f9..c7f490e3a341b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 85fa328d0aa09..183e49a5ba766 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -24,6 +24,20 @@ #include +/* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ +#if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) +static inline +int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) +{ + if (dsc) + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), + 8 * 54 * 1000 * 1000); + + return drm_dp_calc_pbn_mode(clock, bpp); +} +#define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode +#endif + #if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline From 2fecf1964872480fe6f06b5191e0dfbf41e57118 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 21 Jan 2020 15:22:52 +0800 Subject: [PATCH 0475/2070] drm/amdkcl: refactor test for drm_connector_helper_funcs->atomic_check it is a squash of: commit ae74c678762b314212c82c0afcbc7b06f18f3c15 Author: Slava Grigorev Date: Thu Feb 13 12:43:57 2020 -0500 drm/amdkcl: properly define the root of the build directories Change-Id: I5064df48df8b742be9175b01ba9340378d674103 Signed-off-by: Slava Grigorev Change-Id: I32b0308637042a254d34dc5b1a7d0b01fee0190c Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++++----- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 94f7cbce65c32..6a65ab20a7c53 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6920,7 +6920,6 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) for (i = 0; i < context->stream_count ; i++) { stream = context->streams[i]; - if (!stream) continue; @@ -6991,7 +6990,6 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, return NULL; } } - highest_refresh = drm_mode_vrefresh(m_pref); /* @@ -7723,7 +7721,6 @@ static void amdgpu_dm_connector_unregister(struct drm_connector *connector) cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); } - static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7762,7 +7759,6 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree(aconnector->dm_dp_aux.aux.name); - kfree(connector); } @@ -7784,8 +7780,10 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_hborder = 0; state->underscan_vborder = 0; state->base.max_requested_bpc = 8; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) state->vcpi_slots = 0; state->pbn = 0; +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { if (amdgpu_dm_abm_level <= 0) @@ -7818,8 +7816,10 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) new_state->underscan_enable = state->underscan_enable; new_state->underscan_hborder = state->underscan_hborder; new_state->underscan_vborder = state->underscan_vborder; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) new_state->vcpi_slots = state->vcpi_slots; new_state->pbn = state->pbn; +#endif return &new_state->base; } @@ -8347,6 +8347,7 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { @@ -8367,6 +8368,7 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) } return 0; } +#endif static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, @@ -12744,7 +12746,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } -#if defined(HAVE_STRUCT_NAME_CB_NAME_2ARGS) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) /* Perform validation of MST topology in the state*/ ret = drm_dp_mst_atomic_check(state); if (ret) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 2b07277136a59..baaef4dce3c4d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1053,8 +1053,10 @@ struct dm_connector_state { bool update_hdcp; bool abm_sysfs_forbidden; uint8_t abm_level; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int vcpi_slots; uint64_t pbn; +#endif }; #define to_dm_connector_state(x)\ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index abbd9f07ab254..ee5d06044dcb2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -580,6 +580,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { @@ -589,13 +590,16 @@ static int dm_dp_mst_atomic_check(struct drm_connector *connector, return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } +#endif static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, .detect_ctx = dm_dp_mst_detect, +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, +#endif }; static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 new file mode 100644 index 0000000000000..148d0cc472804 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c7f490e3a341b..78559461554db 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -75,6 +75,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 6427d9e63c5cb3b2828aae1c12f075d0ae254a03 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Wed, 8 Jan 2020 14:23:18 +0800 Subject: [PATCH 0476/2070] drm/amdkcl: Test whether drm_dp_mst_atomic_enable_dsc() is available Change-Id: If8f9e171797152ab6a10c4bc05b1e8cf014f0d98 Signed-off-by: Stanley.Yang Acked-by: Hawking Zhang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ .../amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6a65ab20a7c53..f8bb33b0501f0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8446,6 +8446,8 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) @@ -8522,6 +8524,8 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, } return 0; } +#endif +#endif static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) { @@ -12852,11 +12856,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } #endif +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); if (ret) { drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); goto fail; } +#endif /* * Perform validation of MST topology in the state: @@ -12865,11 +12871,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * to get stuck in an infinite loop and hang eventually. */ #ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif #endif status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); if (status != DC_OK) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 new file mode 100644 index 0000000000000..17422c2217f46 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 0529a1d385b9ce6cd7498d180f720eeb3f755980 +dnl # drm/dp_mst: Add DSC enablement helpers to DRM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); + ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_mst_atomic_enable_dsc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 78559461554db..195eb661c60e0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -75,6 +75,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_KERNEL_WAIT From 2fade1bbd28783a8093c49cc971f5d11a7ba203e Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 May 2017 09:35:40 +0800 Subject: [PATCH 0477/2070] drm/amdkcl: [4.11] fix for drm_dp_mst_topology_mgr_init This is a squash of: drm/amdkcl: test drm_dp_mst_topology_mgr_init() the prototype change introduced in v4.10-rc3-517-g7b0a89a6db9a Change-Id: I288af7fc96335e1ae8d1aaf768f4f3f7bb6a8810 Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- .../amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 18 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 new file mode 100644 index 0000000000000..98d2982594b7c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.10-rc3-517-g7b0a89a6db9a +dnl # drm/dp: Store drm_device in MST topology manager +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT, 1, + [drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate]) + + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 195eb661c60e0..e9c74e5f435d3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -77,6 +77,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 5ecde1d2c2f6fc947042bef0cb311f6f7c4afdba Mon Sep 17 00:00:00 2001 From: tianci yin Date: Mon, 21 Jan 2019 10:45:32 +0800 Subject: [PATCH 0478/2070] drm/amdkcl: [5.0] fix null pointer crash in drm_pick_crtcs It is a squash of: amd/amdkcl: drop AC_AMDGPU_DRM_ATOMIC_HELPER_BEST_ENCODER test [why] drm_pick_crtcs called the best_encoder function pointer directly without NULL checking on rhel6.10, and patch "drm/amdgpu: Remove default best_encoder hook from DC" remove the assignment for .best_encoder, this cause the null crash. [how] bring the assignment code back for these old kernel. Change-Id: I5e687b6c3c83ad3814204c6f7e9a9e8338e18fae Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Ma Jun Signed-off-by: tianci yin --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f8bb33b0501f0..b93baa642c4eb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8329,6 +8329,21 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } +static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + struct drm_encoder *encoder; + + /* There is only one encoder per connector */ + drm_connector_for_each_possible_encoder(connector, encoder) + return encoder; + + return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif +} + static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = { /* @@ -8340,6 +8355,7 @@ amdgpu_dm_connector_helper_funcs = { .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_check = amdgpu_dm_connector_atomic_check, + .best_encoder = amdgpu_dm_connector_to_encoder }; static void dm_encoder_helper_disable(struct drm_encoder *encoder) @@ -8562,21 +8578,6 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) } } -static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) -{ -#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS - struct drm_encoder *encoder; - - /* There is only one encoder per connector */ - drm_connector_for_each_possible_encoder(connector, encoder) - return encoder; - - return NULL; -#else - return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); -#endif -} - static void amdgpu_dm_get_native_mode(struct drm_connector *connector) { struct drm_encoder *encoder; From b446fa0fd84ad5544e4b153ab694aedcb5effbbe Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 4 Mar 2019 10:32:16 +0800 Subject: [PATCH 0479/2070] drm/amdkcl: [4.12] fix for Refactor pageflips plane commit This is a squash of: drm/amdkcl: [4.12] fix drm_crtc_state pageflip_flags build error in amdgpu_dm_atomic_commit_tail drm/amdkcl: Test whether drm_crtc_state->async_flip is available drm/amdkcl: [4.12] Reserve flip_flags for display usage drm/amdkcl: add test for drm_crtc_state->pageflip_flags drm/amdkcl: refactor test for pageflip flag in struct drm-crtc-state [Why] In patch:drm/amd/display: Refactor pageflips plane commit Pageflip code is moved from an if statement to after a continue. Because the new code lacks the kcl control,we need to implement it in the new code. [How] Use the old kcl control way in the new code. Change-Id: I82ada88f319ee7c0b9a33f798123ef01e0371b8d Signed-off-by: changzhu Reviewed-by: tianci yin Reviewed-by: Prike Liang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I8b738edde37ecee67d0aba0dcfaf49d4dd881413 Signed-off-by: changzhu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I922e6eefbe5ae01c8a69c4467ea3f22f8398a1e8 Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: Ia7396521f5e11468e83cf2cabac1b6cbbcda21cd Signed-off-by: Le.Ma Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I2f78c678a412ba5945af3d584a525fed5714a6c0 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 5 +++++ drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b93baa642c4eb..0df3282a78b95 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10070,7 +10070,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, plane->base.id, plane->name); bundle->flip_addrs[planes_count].flip_immediate = +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) crtc->state->async_flip && +#else + (crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif acrtc_state->update_type == UPDATE_TYPE_FAST && get_mem_type(old_plane_state->fb) == get_mem_type(fb); @@ -11047,7 +11052,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip) +#else + if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) +#endif wait_for_vblank = false; /* update planes when needed per crtc*/ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index cd086c24819d1..6153b0b2f9c31 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -686,7 +686,12 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, * Only allow async flips for fast updates that don't change the FB * pitch, the DCC state, rotation, etc. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc_state->async_flip && +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif dm_crtc_state->update_type != UPDATE_TYPE_FAST) { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] async flips are only supported for fast updates\n", diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 new file mode 100644 index 0000000000000..cc6860f55c68e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc3-2032-g4d85f45c73a2 +dnl # drm/atomic: Rename crtc_state->pageflip_flags to async_flip +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_state *crtc_state = NULL; + crtc_state->async_flip = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP, 1, + [struct drm_crtc_state->async_flip is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e9c74e5f435d3..92a0e54d1c7ff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -77,6 +77,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From d415a95b85947ffeedfe7735de870d0dd0f198d1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 15:39:25 +0800 Subject: [PATCH 0480/2070] drm/amdkcl: [display] add missing linux/debugfs.h for amdgpu_dm_debugfs.c Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 97814849b0fe0..15190785f1b7d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "dc.h" #include "amdgpu.h" From 3fbcf708537c794a87b1be09294bccfc0438100b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Mar 2024 16:35:34 +0800 Subject: [PATCH 0481/2070] drm/amdkcl: Test whether drm_dp_mst_detect_port() is available v2: drm/amdkcl: fix drm_dp_mst_detect_port() prototype change v2 Change-Id: I3c263f29db3827f340eb80aecd0d48335f8d53c7 Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Asher Song --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 22 +++++++++++++++++++ .../drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 17 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ee5d06044dcb2..61751f23b362c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -143,7 +143,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, return result; } +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP +static enum drm_connector_status +dm_dp_mst_detect(struct drm_connector *connector, bool force) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct amdgpu_dm_connector *master = aconnector->mst_port; + + enum drm_connector_status status = + drm_dp_mst_detect_port( + connector, + &master->mst_mgr, + aconnector->port); + return status; +} +#endif static void dm_dp_mst_connector_destroy(struct drm_connector *connector) { @@ -230,6 +245,9 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) } static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP + .detect = dm_dp_mst_detect, +#endif .fill_modes = drm_helper_probe_single_connector_modes, .destroy = dm_dp_mst_connector_destroy, .reset = amdgpu_dm_connector_funcs_reset, @@ -509,6 +527,7 @@ dm_mst_atomic_best_encoder(struct drm_connector *connector, return &adev->dm.mst_encoders[acrtc->crtc_id].base; } +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP static int dm_dp_mst_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, bool force) @@ -579,6 +598,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#endif #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, @@ -596,7 +616,9 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP .detect_ctx = dm_dp_mst_detect, +#endif #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 new file mode 100644 index 0000000000000..4198140ed6a0e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-752-g3f9b3f02dda5 +dnl # drm/dp_mst: Protect drm_dp_mst_port members with locking +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_DETECT_PORT_PPPP, 1, + [drm_dp_mst_detect_port() wants p,p,p,p args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 92a0e54d1c7ff..0fb25be1ebb03 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -77,6 +77,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT From 62c95757221c7e43e8eb4dc691dc65aa3d647fab Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 16:31:52 +0800 Subject: [PATCH 0482/2070] drm/amdkcl: fix for commit "drm/amd/display: Expose HDR output metadata for supported connectors" Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I03f5e07550343e269ef5cb7b0dba24249ad20adb --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0df3282a78b95..316258cf4d130 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7253,7 +7253,6 @@ create_stream_for_sink(struct drm_connector *connector, sink = aconnector->dc_sink; dc_sink_retain(sink); } - stream = dc_create_stream_for_sink(sink); if (stream == NULL) { @@ -8189,6 +8188,7 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec return result; } +#ifdef HDMI_DRM_INFOFRAME_SIZE static int fill_hdr_info_packet(const struct drm_connector_state *state, struct dc_info_packet *out) { @@ -8328,7 +8328,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } - +#endif static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS @@ -8354,7 +8354,9 @@ amdgpu_dm_connector_helper_funcs = { */ .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, +#ifdef HDMI_DRM_INFOFRAME_SIZE .atomic_check = amdgpu_dm_connector_atomic_check, +#endif .best_encoder = amdgpu_dm_connector_to_encoder }; @@ -9036,6 +9038,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_HDMIA || connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_connector_attach_hdr_output_metadata_property(&aconnector->base); if (!aconnector->mst_root) @@ -10880,9 +10883,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); struct dc_surface_update *dummy_updates; struct dc_stream_update stream_update; - struct dc_info_packet hdr_packet; struct dc_stream_status *status = NULL; - bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; +#ifdef HDMI_DRM_INFOFRAME_SIZE + struct dc_info_packet hdr_packet; + bool hdr_changed; +#endif + bool abm_changed, scaling_changed, output_color_space_changed = false; memset(&stream_update, 0, sizeof(stream_update)); @@ -10909,10 +10915,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) abm_changed = dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE hdr_changed = !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); +#endif - if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) + if (!scaling_changed && !abm_changed && !output_color_space_changed +#ifdef HDMI_DRM_INFOFRAME_SIZE + && !hdr_changed +#endif + ) continue; stream_update.stream = dm_new_crtc_state->stream; @@ -10937,10 +10949,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) stream_update.abm_level = &dm_new_crtc_state->abm_level; } +#ifdef HDMI_DRM_INFOFRAME_SIZE if (hdr_changed) { fill_hdr_info_packet(new_con_state, &hdr_packet); stream_update.hdr_static_metadata = &hdr_packet; } +#endif status = dc_stream_get_status(dm_new_crtc_state->stream); @@ -11477,10 +11491,12 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE ret = fill_hdr_info_packet(drm_new_conn_state, &new_stream->hdr_static_metadata); if (ret) goto fail; +#endif /* * If we already removed the old stream from the context From 7dd048b4575d4acc797cc03df4e94a59aa3346fb Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Thu, 19 Dec 2019 14:58:42 +0800 Subject: [PATCH 0483/2070] drm/amdkcl: fix implicit declaration of prepare_flip_isr dm_page_flip is activated for CentOS7.3 kernel(drm version 4.6.5). The funciton will call prepare_flip_isr and its definition is in front of prepare_flip_isr. Change-Id: I084653267001f327adb75f05b9b8f6608af1d9c1 Signed-off-by: Jiansong Chen Reviewed-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 316258cf4d130..f760707e5f49b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -243,7 +243,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); - +static void prepare_flip_isr(struct amdgpu_crtc *acrtc); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); From 05f829e18e01d661442608a7b962414631061752 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Thu, 26 Dec 2019 17:15:39 +0800 Subject: [PATCH 0484/2070] drm/amdkcl: Test whether drm_dp_mst_dsc_aux_for_port is available Change-Id: If098c1c8474741511e7ae338be90c1a382e3f5cc Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 +++++++-- .../amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 61751f23b362c..79a7e56a2167b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -293,8 +293,9 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 u8 *dsc_branch_dec_caps = NULL; +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); - +#endif /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -496,6 +497,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) amdgpu_dm_update_freesync_caps( connector, aconnector->drm_edid); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) memset(&aconnector->dc_sink->dsc_caps, @@ -505,6 +508,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); +#endif +#endif } } @@ -932,7 +937,7 @@ uint32_t dm_mst_get_pbn_divider(struct dc_link *link) } #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 new file mode 100644 index 0000000000000..06d77b61ab828 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit d251c02a2b78245bb32d7909a66b06285f7922a2 +dnl # drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_dsc_aux_for_port(NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, + [drm_dp_mst_dsc_aux_for_port() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0fb25be1ebb03..085a06cd371d2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE + AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From e491195733a26482c589f6cacfd9b5a0d0cb6647 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 27 Dec 2019 15:20:06 +0800 Subject: [PATCH 0485/2070] drm/amdkcl: Test whether drm_dp_mst_add_affected_dsc_crtcs() is available Change-Id: Icefa820b7602cfd943cbb4d49caac6fa71083263 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f760707e5f49b..c8f9a2be4f11d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12234,6 +12234,7 @@ static inline struct __drm_planes_state *__get_next_zpos( (old_plane_state) = __i->old_state, \ (new_plane_state) = __i->new_state, 1)) +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) { struct drm_connector *connector; @@ -12263,6 +12264,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); } +#endif /** * DOC: Cursor Modes - Native vs Overlay @@ -12526,6 +12528,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, new_crtc_state->connectors_changed = true; } +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) if (dc_resource_is_dsc_encoding_supported(dc)) { for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { @@ -12537,6 +12540,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } +#endif for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 new file mode 100644 index 0000000000000..1d4564270d065 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 971fb192aaeb4b5086ac3f21d00943a5e1431176 +dnl # drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, + [drm_dp_mst_add_affected_dsc_crtcs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 085a06cd371d2..6c04d15d6b4ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -80,6 +80,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT + AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 98da282f19eae1faf6183350734ecda1802365fc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 21 Jan 2020 15:35:48 +0800 Subject: [PATCH 0486/2070] drm/amdkcl: adapt for drm_connector_helper_funcs->atomic_check() prototype change prototype change is in v5.2-rc2-529-g6f3b62781bbd macro HDMI_DRM_INFOFRAME_SIZE is introduced in v5.1-rc5-1691-g2cdbfd66a829 thus there's no need to check atomic_check() availability. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Change-Id: I511b2784fc4d815f3425a58ecc1b64ae8e291444 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c8f9a2be4f11d..d8c73e52092d9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8250,10 +8250,16 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *new_con_state = drm_atomic_get_new_connector_state(state, conn); +#else + struct drm_connector_state *new_con_state) +{ + struct drm_atomic_state *state = new_con_state->state; +#endif struct drm_connector_state *old_con_state = drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; From 21db400c8a101a04ec272225ac646ae4d91ee75f Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 6 Mar 2020 11:44:27 +0800 Subject: [PATCH 0487/2070] drm/amdkcl: add protection for P010 pixel format Change-Id: Iebdf9ccdb876bba345ae49c06669518101fe35ee Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d8c73e52092d9..26df59bc0892f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6106,9 +6106,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_NV12: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; +#ifdef DRM_FORMAT_P010 case DRM_FORMAT_P010: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; break; +#endif case DRM_FORMAT_XRGB16161616F: case DRM_FORMAT_ARGB16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index f184fbaa04ff6..4bb7b62d1cd9e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -801,8 +801,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; +#ifdef DRM_FORMAT_P010 if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; +#endif if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 476780a5450fb..7ff9b450b3713 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -514,7 +514,9 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, +#ifdef DRM_FORMAT_P010 .p010 = false +#endif }, .max_upscale_factor = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 107612595db60..294cff6191ed2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -589,7 +589,9 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, +#ifdef DRM_FORMAT_P010 .p010 = true +#endif }, .max_upscale_factor = { From 09e4f4e0511fafb149140fee65b60753d1e3a1b4 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 6 May 2020 15:38:49 +0800 Subject: [PATCH 0488/2070] drm/amdkcl: Test whether drm_dp_send_real_edid_checksum is available introduced by commit: e11f5bd8228fc3760c221f940b9f6365dbf3e7ed drm: Add support for DP 1.4 Compliance edid corruption test Signed-off-by: Chengming Gui Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++- .../dkms/m4/drm-dp-send-real-edid-checksum.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7d0ecce6b0340..9294956f9a500 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1004,7 +1004,9 @@ enum dc_edid_status dm_helpers_read_local_edid( struct dc_sink *sink) { struct amdgpu_dm_connector *aconnector = link->priv; +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM struct drm_connector *connector = &aconnector->base; +#endif struct i2c_adapter *ddc; int retry = 25; enum dc_edid_status edid_status = EDID_NO_RESPONSE; @@ -1030,6 +1032,7 @@ enum dc_edid_status dm_helpers_read_local_edid( drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); @@ -1038,6 +1041,7 @@ enum dc_edid_status dm_helpers_read_local_edid( connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } +#endif if (!drm_edid) continue; @@ -1090,7 +1094,6 @@ enum dc_edid_status dm_helpers_read_local_edid( DP_TEST_RESPONSE, &test_response.raw, sizeof(test_response)); - } return edid_status; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 new file mode 100644 index 0000000000000..c15c7d3d88eb9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit e11f5bd8228fc3760c221f940b9f6365dbf3e7ed +dnl # drm: Add support for DP 1.4 Compliance edid corruption test +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_send_real_edid_checksum(NULL, 0); + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, + [drm_dp_send_real_edid_checksum() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6c04d15d6b4ca..7edc7e97c22fd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -46,6 +46,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET From f1a33e63929fe51ad5cedc9c05888a50d0fc9776 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 7 May 2020 13:59:32 +0800 Subject: [PATCH 0489/2070] drm/amdkcl: Check whether DRM_FORMAT_XRGB16161616F is defined DRM_FORMAT_XRGB16161616F introduced by commit: drm/fourcc: Add 64 bpp half float formats Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Change-Id: I44c6d15e6f91c01377f59520e1d8a360c9796a1a --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 26df59bc0892f..8bcdefd9b40a3 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6119,6 +6119,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; break; +#ifdef DRM_FORMAT_XRGB16161616 case DRM_FORMAT_XRGB16161616: case DRM_FORMAT_ARGB16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; @@ -6127,6 +6128,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; break; +#endif default: drm_err(adev_to_drm(adev), "Unsupported screen format %p4cc\n", From 210d47884d0742a749078c1c587fb1d89b7f967e Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Mon, 6 Jul 2020 17:20:41 +0800 Subject: [PATCH 0490/2070] drm/amdkcl: fix build error of drm_atomic_get_new_crtc_state undefined This kcl patch is caused by patch: drm/amd/display: clip plane rects in DM before passing into DC Change-Id: I0932a38c7d28db411b721fcb6303cefed51d8674 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 4bb7b62d1cd9e..28dbb61935f7b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1249,9 +1249,9 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = - drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + new_crtc_state = kcl_drm_atomic_get_new_crtc_state_before_commit( + state, new_plane_state->crtc); + if (!new_crtc_state) return -EINVAL; From a832cdafa0470b6e6e963766a58ddd1fd1fd3bd0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 11:24:49 +0800 Subject: [PATCH 0491/2070] drm/amdkcl: test whether struct drm_connector_state has hdcp_content_type This patch is caused by 'drm/amdkcl: Enable HDCP Build by default' Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Bhawanpreet Lakha Change-Id: I4c9d082592f89270bcdc292b07cf9bdbfeb9f51b Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 ++++ .../m4/drm-connector-state-hdcp-content-type.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8bcdefd9b40a3..fd55641406d1b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9055,7 +9055,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_vrr_capable_property(&aconnector->base); if (adev->dm.hdcp_workqueue) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE drm_connector_attach_content_protection_property(&aconnector->base, true); +#else + drm_connector_attach_content_protection_property(&aconnector->base); +#endif } if (connector_type == DRM_MODE_CONNECTOR_eDP) { @@ -9452,6 +9456,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat new_crtc_state->active_changed, new_crtc_state->connectors_changed); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE /* hdcp content type change */ if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { @@ -9459,6 +9464,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); return true; } +#endif /* CP is being re enabled, ignore this */ if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && @@ -10810,7 +10816,12 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) if (aconnector->dc_link) hdcp_update_display( adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, - new_con_state->hdcp_content_type, enable_encryption); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + new_con_state->hdcp_content_type, +#else + DRM_MODE_HDCP_CONTENT_TYPE0, +#endif + enable_encryption); } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index a10401675f53d..752c83854a385 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -374,6 +374,7 @@ static void event_property_update(struct work_struct *work) } if (hdcp_work->encryption_status[conn_index] != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (conn_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 && hdcp_work->encryption_status[conn_index] <= @@ -388,6 +389,9 @@ static void event_property_update(struct work_struct *work) drm_hdcp_update_content_protection(connector, DRM_MODE_CONTENT_PROTECTION_ENABLED); } +#else + drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED); +#endif } else { DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); drm_hdcp_update_content_protection(connector, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 new file mode 100644 index 0000000000000..6d852b75d9e05 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc1-377-g7672dbba85d3 +dnl # drm: Add Content protection type property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdcp_content_type = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE, 1, + [struct drm_connector_state has hdcp_content_type member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7edc7e97c22fd..28830a6c53b5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -83,6 +83,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 8c9b7ebbe0217245f8666978f6ddbc3304298bde Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Fri, 4 Sep 2020 21:45:09 +0800 Subject: [PATCH 0492/2070] drm/amdkcl: drm_device to amdgpu_device by inline-f This patch is caused by the following patche: drm/amdgpu: drm_device to amdgpu_device by inline-f (v2) Change-Id: If95bc03e61ac1f9431be788b7c3ab623e87db5a8 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 79a7e56a2167b..f0355f548e0d6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -869,7 +869,7 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) static void dm_dp_mst_register_connector(struct drm_connector *connector) { struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_device *adev = drm_to_adev(dev); if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); From 25e3f1d33d0b677da45f58344b44b92c11814816 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 9 Aug 2019 11:06:58 +0800 Subject: [PATCH 0493/2070] drm/amdkcl: Test whether whether drm_dp_mst_connector_{early_unregister,late_register} are available Rebase 5.3 squash: * 600691173f87 drm/amd/autoconf: Test whether drm_dp_mst_connector_late_register is available * 8baafc6b96b7 drm/amd/autoconf: Test whether whether drm_dp_mst_connector_early_unregister is available Change-Id: I8d5367bf7adf47083cb0c050a9b01b1b5145614f Signed-off-by: Adam Yang Signed-off-by: changzhu Reviewed-by: Leo Li Reviewed-by: Slava Grigorev Signed-off-by: Jack Gui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index f0355f548e0d6..f6ff49e6377da 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -180,6 +180,7 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) kfree(aconnector); } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) static int amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) { @@ -198,7 +199,7 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) return 0; } - +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ static inline void amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector) @@ -210,6 +211,7 @@ amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector aconnector->vc_full_pbn = 0; } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) static void amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) { @@ -243,6 +245,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) aconnector->mst_status = MST_STATUS_DEFAULT; drm_modeset_unlock(&root->mst_mgr.base.lock); } +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP @@ -255,8 +258,12 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_set_property = amdgpu_dm_connector_atomic_set_property, .atomic_get_property = amdgpu_dm_connector_atomic_get_property, +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) .late_register = amdgpu_dm_mst_connector_late_register, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) .early_unregister = amdgpu_dm_mst_connector_early_unregister, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; bool needs_dsc_aux_workaround(struct dc_link *link) From bf839e0739eb023d0dc4c5e0601820c2060dd095 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 12 Oct 2020 15:02:05 +0800 Subject: [PATCH 0494/2070] drm/amdkcl: DCN301 backport for DC This is caused by "Add dcn3.01 support to DC" v5.9-rc2-568-g94e09bdc1c96 v1: enable DCN301 for DKMS build v2: guard the DSC related code under the macro CONFIG_DRM_AMD_DC_DSC_SUPPORT v3: fix the SSE build error for floating operation v4: remove the unnecessary depends for Kconfig Signed-off-by: Shiwu Zhang Reviewed-by: Yang Xiong --- .../display/dc/dio/dcn301/dcn301_dio_link_encoder.c | 2 ++ .../drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 2 ++ .../display/dc/resource/dcn301/dcn301_resource.c | 13 ++++++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index 47d84a2a48ce8..ee3e776748ee6 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -48,7 +48,9 @@ (enc10->link_regs->index) static const struct link_encoder_funcs dcn301_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, .setup = dcn10_link_encoder_setup, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 33cc48cd01962..67090dca038c7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -136,7 +136,9 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index e1d0c166b4848..ef02cf0045ba2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -47,7 +47,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dce/dce_clock_source.h" @@ -489,6 +491,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -507,6 +510,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -648,7 +652,9 @@ static struct resource_caps res_cap_dcn301 = { .num_ddc = 4, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1055,10 +1061,12 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1225,6 +1233,7 @@ static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn301_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1239,7 +1248,7 @@ static struct display_stream_compressor *dcn301_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } - +#endif static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1656,6 +1665,7 @@ static bool dcn301_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1664,6 +1674,7 @@ static bool dcn301_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn301_dwbc_create(ctx, &pool->base)) { From 563ae66c2aa58b829d150601cc78d6c14b3a8df8 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 19 Oct 2020 14:57:24 +0800 Subject: [PATCH 0495/2070] drm/amdkcl: DCN302 backport for DC This is caused by "Add support for DCN302 (v2)" v5.9-rc2-689-gbe0899b1f9f0 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 2 ++ .../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h | 2 ++ .../gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c | 2 ++ .../amd/display/dc/resource/dcn302/dcn302_resource.c | 12 ++++++++++++ 4 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c index 0a6d58dd8f6da..40fad52521647 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c @@ -156,6 +156,7 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; @@ -221,3 +222,4 @@ void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h index 1e5126a0e695d..6317b4a0f363e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h @@ -30,6 +30,8 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +#endif #endif /* __DC_HWSS_DCN302_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c index 637f9514d37b2..1602be017597a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c @@ -37,5 +37,7 @@ void dcn302_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; +#endif } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index c0d4a1dc94f8a..3a2849b42e6a1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -40,7 +40,9 @@ #include "dcn30/dcn30_optc.h" #include "dcn30/dcn30_resource.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn20/dcn20_resource.h" #include "dml/dcn30/dcn30_fpu.h" @@ -132,7 +134,9 @@ static const struct resource_caps res_cap_dcn302 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -661,6 +665,7 @@ static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -692,6 +697,7 @@ static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -1007,10 +1013,12 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } +#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1145,7 +1153,9 @@ static struct resource_funcs dcn302_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1434,6 +1444,7 @@ static bool dcn302_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn302_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1442,6 +1453,7 @@ static bool dcn302_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn302_dwbc_create(ctx, pool)) { From ea04afc208139eb3b528aa8a8c6629f65c692312 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Oct 2020 13:55:40 +0800 Subject: [PATCH 0496/2070] drm/amdkcl: update config checks with _is_kcl_macro_defined Signed-off-by: Flora Cui Reviewed-by: shiwu.zhang --- drivers/gpu/drm/amd/dkms/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 25f48546e8d01..26cce7ae2a0cb 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,7 +12,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(shell grep "HAVE_DMA_RESV_SEQ" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),n) +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) $(error dma_resv->seq is missing., exit...) endif @@ -156,10 +156,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -ifeq ($(shell grep "HAVE_DRM_DRM_HDCP_H" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),y) export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP -endif # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check From 3f65067c0cd6b9427b0f9e98770d380e7de6bb0c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 2 Oct 2020 12:48:30 +0800 Subject: [PATCH 0497/2070] drm/amdkcl: drop test for DRIVER_ATOMIC DRIVER_ATOMIC is introduced in v3.18-1050-g88a48e297b3a Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 -- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 22 ++----------------- 2 files changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index bf94766348c07..f3127ae06ddd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2450,7 +2450,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); -#ifdef HAVE_DRM_DRV_DRIVER_ATOMIC #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; @@ -2461,7 +2460,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) kms_driver.driver_features |= DRIVER_ATOMIC; -#endif #endif kcl_pci_configure_extended_tags(pdev); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index 3afe53a169b8c..0970897b2338a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -1,28 +1,10 @@ dnl # -dnl # commit 88a48e297b3a3bac6022c03babfb038f1a886cea -dnl # drm: add atomic properties dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d dnl # drm: Switch DRIVER_ flags to an enum dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - int _ = DRIVER_ATOMIC; - ], [ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ - drm_driver_feature DRIVER_ATOMIC is available]) - ]) - ], [ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ - drm_driver_feature DRIVER_ATOMIC is available]) - ]) - ]) - dnl # - dnl # commit: 060cebb20cdbcd3185d593e7194fa7a738201817 + dnl # commit: v5.1-rc5-1467-g060cebb20cdb dnl # drm: introduce a capability flag for syncobj timeline support dnl # AC_KERNEL_DO_BACKGROUND([ @@ -42,7 +24,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ ]) dnl # - dnl # commit: 1ff494813bafa127ecba1160262ba39b2fdde7ba + dnl # commit: v5.0-rc1-390-g1ff494813baf dnl # drm/irq: Ditch DRIVER_IRQ_SHARED dnl # AC_KERNEL_DO_BACKGROUND([ From face0412fcbab863d534aaf62e6dc30ad816228d Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 3 Nov 2020 15:47:44 +0800 Subject: [PATCH 0498/2070] drm/amdkcl: use the kcl wrapper for get/set gem object This is caused by "Store tiling_flags in the framebuffer" v5.9-rc5-1363-gdd3cc8e45355 Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index d294b3e5d3342..4fe82ed6f5dad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1172,7 +1172,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { From d6b8a58d1c387472b2f0dae143211583a76cbd09 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 16 Nov 2020 21:08:17 +0800 Subject: [PATCH 0499/2070] drm/amdkcl: access drm_mm in ttm mem manager by memory type for centos7.3 and 7.4 backport This is caused by "drop priv pointer in memory manager" v5.8-rc2-636-g7ee6c95e05e9 v2: use the static inline function instead Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/backport/include/kcl/kcl_amdgpu_ttm.h | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5fe005591056e..aca7d40e66a28 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -45,6 +45,7 @@ #include #include #include +#include "kcl/kcl_amdgpu_ttm.h" #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h new file mode 100644 index 0000000000000..1c4be1340422f --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_ttm.h" + +#if !defined(HAVE_DRM_MM_PRINT) +extern struct drm_mm *kcl_ttm_range_res_manager_to_drm_mm(struct ttm_resource_manager *man); + +static inline struct drm_mm *kcl_ttm_get_drm_mm_by_mem_type(struct amdgpu_device *adev, unsigned char ttm_pl) +{ + if (ttm_pl == TTM_PL_TT) { + return &(adev->mman.gtt_mgr.mm); + } else if (ttm_pl == TTM_PL_VRAM) { + return &(adev->mman.vram_mgr.mm); + } else { + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); + return kcl_ttm_range_res_manager_to_drm_mm(man); + } +} +#endif + +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H */ From f5e5cd84b3e4611c01cf14c5bf8e94824412b136 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 24 Nov 2020 16:58:39 +0800 Subject: [PATCH 0500/2070] drm/amdkcl: fake the func of timestamping calculation This is caused by "Always get CRTC updated constant values inside commit tail" v5.9-rc5-1644-gea29955035a6 This is a squash of: drm/amdkcl: call legacy update only for backport This is caused by "Remove the timestamping constant update from drm_atomic_helper_update_legacy_modeset_state()" v5.9-rc5-1595-ge1ad957d45f7 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 28 +++++++++++++++++++ ...omic_helper_calc_timestamping_constants.m4 | 13 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 4 +++ 4 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 4ef77c1846213..3e2cf46b8526c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -27,6 +27,7 @@ */ #include #include +#include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, @@ -59,3 +60,30 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, } EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); #endif + +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +/* + * This implementation is duplicated from v5.9-rc5-1595-ge1ad957d45f7 + * "Extract drm_atomic_helper_calc_timestamping_constants()" + * + */ +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_crtc_state *new_crtc_state; + struct drm_crtc *crtc; + int i; + +#if !defined(for_each_new_crtc_in_state) + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + new_crtc_state = crtc->state; +#else + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif + if (new_crtc_state->enable) + drm_calc_timestamping_constants(crtc, + &new_crtc_state->adjusted_mode); + } +} +EXPORT_SYMBOL(drm_atomic_helper_calc_timestamping_constants); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 new file mode 100644 index 0000000000000..79ab39b5802f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.9-rc5-1595-ge1ad957d45f7 +dnl # Extract drm_atomic_helper_calc_timestamping_constants() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_atomic_helper_calc_timestamping_constants], + [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, + [drm_atomic_helper_calc_timestamping_constants() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 28830a6c53b5a..6b9179c4125a6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index cb5c49c24cb94..208a5e9edf330 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -49,4 +49,8 @@ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); #endif +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); +#endif + #endif From 17b6dbe749b70ae45f762ac9b74a0f5b49a2e736 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 17 Nov 2020 16:48:12 +0800 Subject: [PATCH 0501/2070] drm/amdkcl: disable modifier support for DRM before 5.0 This is caused by "Add formats for DCC with 2/3 planes" and "Expose modifiers" v5.9-rc5-1367-g564b9f4c7cf9 and v5.9-rc5-1368-g86ce3ed796ff This is a squash of: drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amdkcl: guard the modifier code for backport This is caused by "Store gem objects for planes 1-3" v5.9-rc5-1565-gbf01c77ad320 Signed-off-by: Shiwu Zhang Reviewed-by: Bhawanpreet Lakha drm/amdkcl: update the AMD modifer macros This is caused by "Fix modifier field mask for AMD modifiers", "add table describing AMD modifiers bit layout", "fix AMD modifiers PACKERS field doc" v5.9-rc5-1563-g80363c69ca44, v5.9-rc5-1564-gbac8bece9c55 and v5.9-rc5-1594-g11e500d2892a Signed-off-by: Shiwu Zhang drm/amdkcl: fix the config.h mismatch for autotest and regenerate the config.h Signed-off-by: Shiwu Zhang drm/amdkcl: disable modifier feature if Floating point 64bpp RGB format is not defined This is to avoid warning printing during modprobe on the OS like rhel 7.9 Signed-off-by: Shiwu Zhang Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Reviewed-by: Bhawanpreet Lakha Signed-off-by: Ma Jun Change-Id: If9ccae068c5b8cf3f475fa8c178b5d3135a9b84a --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 10 + .../gpu/drm/amd/dkms/m4/drm_format_info.m4 | 20 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 9 +- include/kcl/kcl_drm_fourcc.h | 217 ++++++++++++++++++ 7 files changed, 261 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 create mode 100644 include/kcl/kcl_drm_fourcc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 4fe82ed6f5dad..a82ae6059dd55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -746,6 +746,7 @@ static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) { struct amdgpu_device *adev = drm_to_adev(afb->base.dev); @@ -939,6 +940,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) afb->base.flags |= DRM_MODE_FB_MODIFIERS; return 0; } +#endif /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) @@ -1245,6 +1247,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, * This needs to happen before modifier conversion as that might change * the number of planes. */ +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 1; i < rfb->base.format->num_planes; ++i) { if (mode_cmd->handles[i] != mode_cmd->handles[0]) { drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", @@ -1253,12 +1256,14 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } } +#endif ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface, &rfb->gfx12_dcc); if (ret) return ret; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); @@ -1289,6 +1294,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, drm_gem_object_get(rfb->base.obj[0]); rfb->base.obj[i] = rfb->base.obj[0]; } +#endif return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index aca7d40e66a28..1dccbc9e08638 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -47,6 +47,7 @@ #include #include "kcl/kcl_amdgpu_ttm.h" #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fd55641406d1b..1c3d2bcec58fe 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3767,7 +3767,9 @@ const struct amdgpu_ip_block_version dm_ip_block = { static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .get_format_info = amdgpu_dm_plane_get_format_info, +#endif .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 28dbb61935f7b..cb35f9ce85a3e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -165,10 +165,12 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 *size += 1; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); } +#endif static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) { @@ -308,6 +310,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, const enum surface_pixel_format format, @@ -358,6 +361,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg return ret; } +#endif static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, @@ -912,12 +916,14 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, if (ret) return ret; } else if (adev->family >= AMDGPU_FAMILY_AI) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, address); if (ret) return ret; +#endif } else { amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); } @@ -1838,7 +1844,9 @@ static const struct drm_plane_funcs dm_plane_funcs = { .reset = amdgpu_dm_plane_drm_plane_reset, .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .format_mod_supported = amdgpu_dm_plane_format_mod_supported, +#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = dm_atomic_plane_set_property, .atomic_get_property = dm_atomic_plane_get_property, @@ -1860,9 +1868,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, ARRAY_SIZE(formats)); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); if (res) return res; +#endif if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 new file mode 100644 index 0000000000000..95a45563d402e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v5.9-rc5-1367-g564b9f4c7cf9 +dnl # drm/amd/display: Add formats for DCC with 2/3 planes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_format_info format = { + .format = DRM_FORMAT_XRGB16161616F, + .block_w = {0}, + .block_h = {0}, + }; + ], [ + AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, + [drm_format_info.block_w and rm_format_info.block_h is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6b9179c4125a6..576b63236b200 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -58,10 +58,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET - AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION - AC_AMDGPU_JIFFIES64_TO_MSECS - AC_AMDGPU_ACPI_PUT_TABLE - AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM @@ -85,6 +81,11 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS + AC_AMDGPU_DRM_FORMAT_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h new file mode 100644 index 0000000000000..25cf40f897b23 --- /dev/null +++ b/include/kcl/kcl_drm_fourcc.h @@ -0,0 +1,217 @@ +/* + * Copyright 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_FOURCC_H +#define KCL_KCL_DRM_FOURCC_H + +#include + +/* Copied from include/uapi/drm/drm_fourcc.h */ +/* + * Linear Layout + * + * Just plain linear layout. Note that this is different from no specifying any + * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), + * which tells the driver to also take driver-internal information into account + * and so might actually result in a tiled framebuffer. + */ +#if !defined(DRM_FORMAT_MOD_VENDOR_NONE) +#define DRM_FORMAT_MOD_VENDOR_NONE 0 +#endif + +#if !defined(DRM_FORMAT_MOD_LINEAR) +#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) +#endif + +#if !defined(DRM_FORMAT_RESERVED) +#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#endif +/* + * * Invalid Modifier + * * + * * This modifier can be used as a sentinel to terminate the format modifiers + * * list, or to initialize a variable with an invalid modifier. It might also be + * * used to report an error back to userspace for certain APIs. + * */ +#if !defined(DRM_FORMAT_MOD_INVALID) +#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) +#endif + +/* + * AMD modifiers + * + * Memory layout: + * + * without DCC: + * - main surface + * + * with DCC & without DCC_RETILE: + * - main surface in plane 0 + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) + * + * with DCC & DCC_RETILE: + * - main surface in plane 0 + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) + * + * For multi-plane formats the above surfaces get merged into one plane for + * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero + */ + +#if !defined(AMD_FMT_MOD) +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) + +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) + +/* Reserve 0 for GFX8 and older */ +#define AMD_FMT_MOD_TILE_VER_GFX9 1 +#define AMD_FMT_MOD_TILE_VER_GFX10 2 +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 + +/* + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical + * version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 + +/* + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has + * GFX9 as canonical version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 + +#define AMD_FMT_MOD_DCC_BLOCK_64B 0 +#define AMD_FMT_MOD_DCC_BLOCK_128B 1 +#define AMD_FMT_MOD_DCC_BLOCK_256B 2 + +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF +#define AMD_FMT_MOD_TILE_SHIFT 8 +#define AMD_FMT_MOD_TILE_MASK 0x1F + +/* Whether DCC compression is enabled. */ +#define AMD_FMT_MOD_DCC_SHIFT 13 +#define AMD_FMT_MOD_DCC_MASK 0x1 + +/* + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and + * one which is not-aligned. + */ +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 + +/* Only set if DCC_RETILE = false */ +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 + +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 + +/* + * DCC supports embedding some clear colors directly in the DCC surface. + * However, on older GPUs the rendering HW ignores the embedded clear color + * and prefers the driver provided color. This necessitates doing a fastclear + * eliminate operation before a process transfers control. + * + * If this bit is set that means the fastclear eliminate is not needed for these + * embeddable colors. + */ +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 + +/* + * The below fields are for accounting for per GPU differences. These are only + * relevant for GFX9 and later and if the tile field is *_X/_T. + * + * PIPE_XOR_BITS = always needed + * BANK_XOR_BITS = only for TILE_VER_GFX9 + * PACKERS = only for TILE_VER_GFX10_RBPLUS + * RB = only for TILE_VER_GFX9 & DCC + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) + */ +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_PACKERS_SHIFT 27 +#define AMD_FMT_MOD_PACKERS_MASK 0x7 +#define AMD_FMT_MOD_RB_SHIFT 30 +#define AMD_FMT_MOD_RB_MASK 0x7 +#define AMD_FMT_MOD_PIPE_SHIFT 33 +#define AMD_FMT_MOD_PIPE_MASK 0x7 + +#define AMD_FMT_MOD_SET(field, value) \ + ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) +#define AMD_FMT_MOD_GET(field, value) \ + (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) +#define AMD_FMT_MOD_CLEAR(field) \ + (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) +#endif + +/* + * 2 plane YCbCr MSB aligned + * index 0 = Y plane, [15:0] Y:x [10:6] little endian + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian + */ +#ifndef DRM_FORMAT_P010 +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ +#endif +/* + * Floating point 64bpp RGB + * IEEE 754-2008 binary16 half-precision float + * [15:0] sign:exponent:mantissa 1:5:10 + */ +#ifndef DRM_FORMAT_XRGB16161616F +#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ + +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#endif + +#endif /* KCL_KCL_DRM_FOURCC_H */ From bb03370fc8bcb68dac191312b4d139a832b18b9b Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 15 Dec 2020 17:30:45 +0800 Subject: [PATCH 0502/2070] drm/amdkcl: dummy the amdgpu dm tracepoint for backport This is caused by "Add tracepoint for amdgpu_dm" v5.9-rc5-1254-gb694b19508a3 v2: more autotests to make the new tracepoints valid on the tier1 OS of rhel7.9 and above v3: fix indent and use the autotests already defined before Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 88 ++++++++++++++++--- .../gpu/drm/amd/dkms/m4/drm-atomic-state.m4 | 18 ++++ .../drm/amd/dkms/m4/drm-connector-state.m4 | 26 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_dm_tracepoint.h | 21 +++++ 5 files changed, 143 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 create mode 100644 include/kcl/backport/kcl_dm_tracepoint.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index aa56fd6d56c34..045283ad899b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -41,6 +41,7 @@ #include "dc/inc/hw/optc.h" #include "dc/inc/core_types.h" +#include DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), @@ -113,13 +114,19 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __field(uint32_t, crtc_id) __field(uint32_t, best_encoder_id) __field(enum drm_link_status, link_status) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_aware) +#endif __field(enum hdmi_picture_aspect, picture_aspect_ratio) __field(unsigned int, content_type) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __field(unsigned int, hdcp_content_type) +#endif __field(unsigned int, content_protection) __field(unsigned int, scaling_mode) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __field(u32, colorspace) +#endif __field(u8, max_requested_bpc) __field(u8, max_bpc) ), @@ -133,28 +140,52 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __entry->best_encoder_id = state->best_encoder ? state->best_encoder->base.id : 0; __entry->link_status = state->link_status; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_aware = state->self_refresh_aware; +#endif __entry->picture_aspect_ratio = state->picture_aspect_ratio; __entry->content_type = state->content_type; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __entry->hdcp_content_type = state->hdcp_content_type; +#endif __entry->content_protection = state->content_protection; __entry->scaling_mode = state->scaling_mode; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __entry->colorspace = state->colorspace; +#endif __entry->max_requested_bpc = state->max_requested_bpc; __entry->max_bpc = state->max_bpc; ), TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u " - "best_encoder_id=%u link_status=%d self_refresh_aware=%d " + "best_encoder_id=%u link_status=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_aware=%d " +#endif "picture_aspect_ratio=%d content_type=%u " - "hdcp_content_type=%u content_protection=%u scaling_mode=%u " - "colorspace=%u max_requested_bpc=%u max_bpc=%u", +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + "hdcp_content_type=%u " +#endif + "content_protection=%u scaling_mode=%u " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + "colorspace=%u " +#endif + "max_requested_bpc=%u max_bpc=%u", __entry->conn_id, __entry->conn_state, __entry->state, __entry->commit, __entry->crtc_id, __entry->best_encoder_id, - __entry->link_status, __entry->self_refresh_aware, + __entry->link_status, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_aware, +#endif __entry->picture_aspect_ratio, __entry->content_type, - __entry->hdcp_content_type, __entry->content_protection, - __entry->scaling_mode, __entry->colorspace, +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + __entry->hdcp_content_type, +#endif + __entry->content_protection, + __entry->scaling_mode, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + __entry->colorspace, +#endif __entry->max_requested_bpc, __entry->max_bpc) ); @@ -176,9 +207,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __field(bool, zpos_changed) __field(bool, color_mgmt_changed) __field(bool, no_vblank) +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __field(bool, async_flip) +#endif __field(bool, vrr_enabled) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_active) +#endif __field(u32, plane_mask) __field(u32, connector_mask) __field(u32, encoder_mask) @@ -198,9 +233,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __entry->zpos_changed = state->zpos_changed; __entry->color_mgmt_changed = state->color_mgmt_changed; __entry->no_vblank = state->no_vblank; +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __entry->async_flip = state->async_flip; +#endif __entry->vrr_enabled = state->vrr_enabled; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_active = state->self_refresh_active; +#endif __entry->plane_mask = state->plane_mask; __entry->connector_mask = state->connector_mask; __entry->encoder_mask = state->encoder_mask; @@ -208,16 +247,29 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed(" "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) " - "state(enable=%d active=%d async_flip=%d vrr_enabled=%d " - "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x " + "state(enable=%d active=%d " +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + "async_flip=%d " +#endif + "vrr_enabled=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_active=%d " +#endif + "no_vblank=%d) mask(plane=%x conn=%x " "enc=%x)", __entry->crtc_id, __entry->crtc_state, __entry->state, __entry->commit, __entry->planes_changed, __entry->mode_changed, __entry->active_changed, __entry->connectors_changed, __entry->zpos_changed, __entry->color_mgmt_changed, __entry->enable, __entry->active, - __entry->async_flip, __entry->vrr_enabled, - __entry->self_refresh_active, __entry->no_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + __entry->async_flip, +#endif + __entry->vrr_enabled, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_active, +#endif + __entry->no_vblank, __entry->plane_mask, __entry->connector_mask, __entry->encoder_mask) ); @@ -323,7 +375,9 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __field(bool, allow_modeset) __field(bool, legacy_cursor_update) __field(bool, async_update) +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __field(bool, duplicated) +#endif __field(int, num_connector) __field(int, num_private_objs) ), @@ -333,16 +387,26 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __entry->allow_modeset = state->allow_modeset; __entry->legacy_cursor_update = state->legacy_cursor_update; __entry->async_update = state->async_update; +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __entry->duplicated = state->duplicated; +#endif __entry->num_connector = state->num_connector; __entry->num_private_objs = state->num_private_objs; ), TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d " - "async_update=%d duplicated=%d num_connector=%d " + "async_update=%d " +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + "duplicated=%d " +#endif + "num_connector=%d " "num_private_objs=%d", __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update, - __entry->async_update, __entry->duplicated, __entry->num_connector, + __entry->async_update, +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + __entry->duplicated, +#endif + __entry->num_connector, __entry->num_private_objs) ); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 new file mode 100644 index 0000000000000..cd7227d5c12eb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.0-rc1-415-g022debad063e +dnl # drm/atomic: Add drm_atomic_state->duplicated +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_atomic_state *state = NULL; + state->duplicated = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED, 1, + [struct drm_connector_state->duplicated is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 new file mode 100644 index 0000000000000..69753da371891 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v4.20-rc3-425-g1398958cfd8d +dnl # drm: Add vrr_enabled property to drm CRTC +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [struct drm_connector_state->colorspace is available]) + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->self_refresh_aware = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE, 1, + [struct drm_connector_state->self_refresh_aware is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 576b63236b200..791616d192d67 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -86,6 +86,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_dm_tracepoint.h b/include/kcl/backport/kcl_dm_tracepoint.h new file mode 100644 index 0000000000000..7d0e772c51ece --- /dev/null +++ b/include/kcl/backport/kcl_dm_tracepoint.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_BACKPORT_KCL_DM_TRACEPOINT_H +#define KCL_BACKPORT_KCL_DM_TRACEPOINT_H + +#ifndef DECLARE_EVENT_NOP +#define DECLARE_EVENT_NOP(name, proto, args) \ + static inline void trace_##name(proto) \ + { } \ + static inline bool trace_##name##_enabled(void) \ + { \ + return false; \ + } + +#define TRACE_EVENT_NOP(name, proto, args, struct, assign, print) \ + DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args)) + +#define DEFINE_EVENT_NOP(template, name, proto, args) \ + DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args)) +#endif + +#endif /* KCL_BACKPORT_KCL_DM_TRACEPOINT_H */ From bf0c1acddb243ba0b6fdf0ba413e6f65629d3e65 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 8 Jan 2020 17:12:58 +0800 Subject: [PATCH 0503/2070] drm/amdkcl: enable CONFIG_DRM_TTM_DMA_PAGE_POOL Signed-off-by: Flora Cui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 26cce7ae2a0cb..cfe73b92bcad9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -141,6 +141,7 @@ LINUXINCLUDE := \ export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m +export CONFIG_DRM_TTM_DMA_PAGE_POOL=y export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m export CONFIG_DRM_AMDGPU_CIK=y @@ -150,6 +151,7 @@ export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y subdir-ccflags-y += -DCONFIG_HSA_AMD +subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From b0a4de71f4427c0003511768255c83d72e35e7ba Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Mon, 18 Feb 2019 10:40:35 +0800 Subject: [PATCH 0504/2070] drm/amdkcl: check whether u64_to_user_ptr is available v1: drm/amdkcl: [4.7] kcl for u64_to_user_ptr() v2: drm/amdkcl: drop kcl_u64_to_user_ptr Signed-off-by: Le.Ma Reviewed-by: Junwei Zhang Reviewed-by: Evan Quan Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_kernel.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_kernel.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1dccbc9e08638..39f88ec9d1d56 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h new file mode 100644 index 0000000000000..e1a0dfe11a386 --- /dev/null +++ b/include/kcl/kcl_kernel.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KERNEL_H +#define AMDKCL_KERNEL_H + +#include + +/* Copied from include/linux/kernel.h */ +#ifndef u64_to_user_ptr +#define u64_to_user_ptr(x) ( \ +{ \ + typecheck(u64, x); \ + (void __user *)(uintptr_t)x; \ +} \ +) +#endif + +#endif /* AMDKCL_KERNEL_H */ From 8b206a2773d486ee2057a31490fd8aa8798359a4 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Tue, 23 Jan 2018 15:33:23 +0800 Subject: [PATCH 0505/2070] drm/amdkcl: check whether __GFP_RETRY_MAYFAIL is available kernel 4.13: rename __GFP_REPEAT to __GFP_RETRY_MAYFAIL Reviewed-by: Le Ma Reviewed-by: Roger He Signed-Off-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_kernel.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index e2d7fbfba2433..ed995d9f22cec 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,6 +3,7 @@ #define AMDTTM_BACKPORT_H #include +#include #include #include #include diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index e1a0dfe11a386..6624b9a50f79a 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -3,6 +3,7 @@ #define AMDKCL_KERNEL_H #include +#include /* Copied from include/linux/kernel.h */ #ifndef u64_to_user_ptr @@ -14,4 +15,8 @@ ) #endif +#ifndef __GFP_RETRY_MAYFAIL +#define __GFP_RETRY_MAYFAIL __GFP_REPEAT +#endif + #endif /* AMDKCL_KERNEL_H */ From 767150102f25957ac239034800c3c957dafd7ed7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 12 Mar 2020 21:00:19 +0800 Subject: [PATCH 0506/2070] drm/amdkcl: add macro ALIGN_DOWN Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang --- include/kcl/kcl_kernel.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index 6624b9a50f79a..f33fc452d8243 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -19,4 +19,8 @@ #define __GFP_RETRY_MAYFAIL __GFP_REPEAT #endif +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) +#endif /* ALIGN_DOWN */ + #endif /* AMDKCL_KERNEL_H */ From d0255ac9ec3e259ff3fe11299442d638e85825cd Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 18 Mar 2020 17:09:57 +0800 Subject: [PATCH 0507/2070] drm/amdkcl: add kcl_compiler_attributes.h Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 2 ++ include/kcl/kcl_compiler_attributes.h | 13 +++++++++++++ 4 files changed, 17 insertions(+) create mode 100644 include/kcl/kcl_compiler_attributes.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 39f88ec9d1d56..23c179e30356d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index d72474310e88f..6ca5e362390fd 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -3,6 +3,7 @@ #define AMDSCHED_BACKPORT_H #include +#include #include #include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index ed995d9f22cec..9500725e818f5 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -4,10 +4,12 @@ #include #include +#include #include #include #include #include #include #include + #endif diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h new file mode 100644 index 0000000000000..34d035352059c --- /dev/null +++ b/include/kcl/kcl_compiler_attributes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_COMPILER_ATTRIBUTES_H +#define AMDKCL_COMPILER_ATTRIBUTES_H + +#ifdef HAVE_LINUX_COMPILER_ATTRIBUTES_H +#include +#endif + +#ifndef fallthrough +#define fallthrough do {} while (0) /* fallthrough */ +#endif + +#endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ From 049f89814ac79ca443b0c80c24891e45a33965e0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 10 Sep 2020 13:32:43 +0800 Subject: [PATCH 0508/2070] drm/amdkcl: fake dma_alloc_attrs api for dma_attrs change Signed-off-by: Flora Cui Change-Id: If4dffb0b4f0d2a6d9a7067ab5e15c3d42e31e198 --- drivers/gpu/drm/ttm/ttm_pool.c | 4 ++-- include/kcl/kcl_dma_mapping.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index 217e459580994..cdad09312a59b 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -171,7 +171,7 @@ static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags, if (order) attr |= DMA_ATTR_NO_WARN; - vaddr = dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, + vaddr = kcl_dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, &dma->addr, gfp_flags, attr); if (!vaddr) goto error_free; @@ -219,7 +219,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching, dma = (void *)p->private; vaddr = (void *)(dma->vaddr & PAGE_MASK); - dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, + kcl_dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, attr); kfree(dma); } diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index c7de48cd9aad7..ff07e493a88fe 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -26,6 +26,38 @@ void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, dma_set_attr(i, dma_attrs); } } + +static inline +void *kcl_dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t flag, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + return dma_alloc_attrs(dev, size, dma_handle, flag, &dma_attrs); +} + +static inline +void kcl_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + dma_free_attrs(dev, size, cpu_addr, dma_handle, &dma_attrs); +} +#else +static inline void *kcl_dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag, + unsigned long attrs) +{ + return dma_alloc_attrs(dev, size, dma_handle, flag, attrs); +} +static inline void kcl_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, unsigned long attrs) +{ + return dma_free_attrs(dev, size, cpu_addr, dma_handle, attrs); +} #endif #ifndef HAVE_DMA_MAP_SGTABLE From 629fcad2690af28003dea3612005c3f748aa2e39 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Sep 2020 13:36:31 +0800 Subject: [PATCH 0509/2070] drm/amdkcl: test for_each_sgtable_sg() Signed-off-by: Flora Cui --- include/kcl/kcl_dma_mapping.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index ff07e493a88fe..73070e3605f89 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -119,4 +119,13 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, } #endif +/* + * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") + * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") + */ +#ifndef for_each_sgtable_sg +#define for_each_sgtable_sg(sgt, sg, i) \ + for_each_sg((sgt)->sgl, sg, (sgt)->orig_nents, i) +#endif + #endif From 1367ef7220f4dce19824017d00581d889a72d5d2 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Fri, 10 Jul 2020 16:04:02 +0800 Subject: [PATCH 0510/2070] drm/amdkcl: add kcl copy of epoll event masks macro introduced in v4.11-rc2-2-g7e040726850a This kcl patch is caused by patch: drm/amdkfd: sparse: fix incorrect type in assignment Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Change-Id: I2ab2c440728cfa1a38c1cd8a0e230fb3ee7327ae --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_eventpoll.h | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 include/kcl/kcl_eventpoll.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 23c179e30356d..5875be87cdc97 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_eventpoll.h b/include/kcl/kcl_eventpoll.h new file mode 100644 index 0000000000000..5f23d49a7e46f --- /dev/null +++ b/include/kcl/kcl_eventpoll.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * include/linux/eventpoll.h ( Efficient event polling implementation ) + * Copyright (C) 2001,...,2006 Davide Libenzi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Davide Libenzi + * + */ +#ifndef AMDKCL_EVENTPOLL_H +#define AMDKCL_EVENTPOLL_H + +#include + +/* Copied from include/uapi/linux/eventpoll.h */ +#ifndef EPOLLIN +#define EPOLLIN 0x00000001 +#define EPOLLPRI 0x00000002 +#define EPOLLOUT 0x00000004 +#define EPOLLERR 0x00000008 +#define EPOLLHUP 0x00000010 +#define EPOLLRDNORM 0x00000040 +#define EPOLLRDBAND 0x00000080 +#define EPOLLWRNORM 0x00000100 +#define EPOLLWRBAND 0x00000200 +#define EPOLLMSG 0x00000400 +#define EPOLLRDHUP 0x00002000 +#endif +#endif From 8e3d122b5920b787760f6d302ecae2ba75ff02fe Mon Sep 17 00:00:00 2001 From: tianci yin Date: Mon, 18 Feb 2019 10:59:12 +0800 Subject: [PATCH 0511/2070] drm/amdkcl: Test whether system_highpri_wq is available This is a squash of: drm/amdkcl: [3.16] add system_highpri_wq support Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui drm/amdkcl: Test whether system_highpri_wq is available system_highpri_wq is exported in kernel 3.6 and declared in kernel 3.15 Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amd/autoconf: fix system_highpri_wq unexported issue Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: drop test for system_highpri_wq Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_workqueue.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/kcl/kcl_workqueue.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5875be87cdc97..e079d86a1275e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_workqueue.h b/include/kcl/kcl_workqueue.h new file mode 100644 index 0000000000000..345bd0f2cc384 --- /dev/null +++ b/include/kcl/kcl_workqueue.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_WORKQUEUE_H +#define KCL_LINUX_WORKQUEUE_H + +#include + +/* + * System-wide workqueues which are always present. + * + * system_highpri_wq is similar to system_wq but for work items which + * require WQ_HIGHPRI. + * + * v3.15-rc1-18-g73e4354444ee workqueue: declare system_highpri_wq + * v3.6-rc1-20-g1aabe902ca36 workqueue: introduce system_highpri_wq + */ +extern struct workqueue_struct *system_highpri_wq; + +#endif From ed0466c0f7a29d50236c287b70da600b1ee0f14c Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 22 Oct 2018 17:08:04 +0800 Subject: [PATCH 0512/2070] drm/amdkcl: [4.13] Add sysfs node max_link_speed/width, current_link_speed/width For SWDEV-165476 require and implement the feature inquire node. KCL originally implemented as commit 02805f8d0d76 to add sysfs node for max_link_speed, max_link_width, current_link_speed, current_link_width proposed in commit 56c1af4606f0. Since most of the attributes introduced in the commit 56c1af4606f0 are static and only visible within the PCI compile unit, we cannot use autoconf to check if they are defined. In this commit, we use the macro PCI_EXP_LNKCAP_SLS_8_0GB checked-in along with these attributes as a workaround and further check the return value after calling device_create_file() by deliberately ignoring the -EEXIST error code to make sure the error log is not mis-reported. v1: drm/amdkcl: Add sysfs node max_link_speed/width, current_link_speed/width v2: drm/amdkcl: add macros in kcl_pci.h if checked undefinded v3: add macro undefined check for remove BUILD_AS_DKMS macro v4: drm/amdkcl: remove sysfs entry on exit Signed-off-by: Prike Liang Reviewed-by: xinhui pan Reviewed-by: Junwei Zhang Signed-off-by: Adam Yang Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 122 ++++++++++++++++++++++++ include/kcl/kcl_pci.h | 75 +++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f3127ae06ddd7..21ff6b1c8f6a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2462,6 +2462,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kms_driver.driver_features |= DRIVER_ATOMIC; #endif + kcl_pci_create_measure_file(pdev); kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) @@ -2595,6 +2596,7 @@ amdgpu_pci_remove(struct pci_dev *pdev) * Clear the Bus Master Enable bit and then wait on the PCIe Device * StatusTransactions Pending bit. */ + kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); } diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 7acee9d394b0b..27734a1d565c3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -147,3 +147,125 @@ bool _kcl_pci_pr3_present(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); #endif #endif /* HAVE_PCI_PR3_PRESENT */ + +#ifdef AMDKCL_CREATE_MEASURE_FILE +static ssize_t max_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%s\n", PCIE_SPEED2STR(kcl_pcie_get_speed_cap(pdev))); +} +static DEVICE_ATTR_RO(max_link_speed); + +static ssize_t max_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%u\n", kcl_pcie_get_width_cap(pdev)); +} +static DEVICE_ATTR_RO(max_link_width); + +static ssize_t current_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + const char *speed; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_16_0GB: + speed = "16 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_8_0GB: + speed = "8 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_5_0GB: + speed = "5 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_2_5GB: + speed = "2.5 GT/s"; + break; + default: + speed = "Unknown speed"; + } + + return sprintf(buf, "%s\n", speed); +} +static DEVICE_ATTR_RO(current_link_speed); + +static ssize_t current_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + return sprintf(buf, "%u\n", + (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT); +} +static DEVICE_ATTR_RO(current_link_width); + +static struct attribute *pcie_dev_attrs[] = { + &dev_attr_current_link_speed.attr, + &dev_attr_current_link_width.attr, + &dev_attr_max_link_width.attr, + &dev_attr_max_link_speed.attr, + NULL, +}; + +int _kcl_pci_create_measure_file(struct pci_dev *pdev) +{ + int ret = 0; + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_speed sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_speed sysfs files: %d\n", ret); + return ret; + } + + return ret; +} +EXPORT_SYMBOL(_kcl_pci_create_measure_file); + +void _kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_current_link_speed); + device_remove_file(&pdev->dev, &dev_attr_current_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_speed); +} +EXPORT_SYMBOL(_kcl_pci_remove_measure_file); +#endif /* AMDKCL_CREATE_MEASURE_FILE */ diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 9f9e1439300aa..26a871d319e2a 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -26,6 +26,58 @@ #include #include +#ifndef PCI_EXP_DEVCAP2_ATOMIC_ROUTE +#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP32 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP64 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion*/ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP128 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion*/ +#endif +#ifndef PCI_EXP_DEVCTL2_ATOMIC_REQ +#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ +#endif +#ifndef PCI_EXP_DEVCTL2_ATOMIC_BLOCK +#define PCI_EXP_DEVCTL2_ATOMIC_BLOCK 0x0040 /* Block AtomicOp on egress */ +#endif + +#ifndef PCIE_SPEED_16_0GT +#define PCIE_SPEED_16_0GT 0x17 +#endif +#ifndef PCI_EXP_LNKCAP2_SLS_16_0GB +#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ +#endif +#ifndef PCI_EXP_LNKCAP_SLS_16_0GB +#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ +#endif +#ifndef PCI_EXP_LNKSTA_CLS_16_0GB +#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ +#endif + +/* PCIe link information */ +#ifndef PCIE_SPEED2STR +#define PCIE_SPEED2STR(speed) \ + ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ + (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ + (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ + (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ + "Unknown speed") +#endif + +/* PCIe speed to Mb/s reduced by encoding overhead */ +#ifndef PCIE_SPEED2MBS_ENC +#define PCIE_SPEED2MBS_ENC(speed) \ + ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ + (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ + (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ + (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ + 0) +#endif + #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); @@ -79,4 +131,27 @@ static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } #endif #endif /* HAVE_PCI_PR3_PRESENT */ +#ifndef PCI_EXP_LNKCAP_SLS_8_0GB +#define AMDKCL_CREATE_MEASURE_FILE +#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ +int _kcl_pci_create_measure_file(struct pci_dev *pdev); +void _kcl_pci_remove_measure_file(struct pci_dev *pdev); +#endif + +static inline int kcl_pci_create_measure_file(struct pci_dev *pdev) +{ +#ifdef AMDKCL_CREATE_MEASURE_FILE + return _kcl_pci_create_measure_file(pdev); +#else + return 0; +#endif +} + +static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ +#ifdef AMDKCL_CREATE_MEASURE_FILE + _kcl_pci_remove_measure_file(pdev); +#endif +} + #endif /* AMDKCL_PCI_H */ From d10a3d8e58fa67c40dc90c7f7a468b8f8f27510a Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 22:15:29 +0800 Subject: [PATCH 0513/2070] drm/amdkcl: add PCI_EXP macro in kcl Change-Id: I16e3b99df53731bc3f8f836aeb1ac41763443810 Signed-off-by: Yifan Zhang --- include/kcl/kcl_pci.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 26a871d319e2a..9b5f1bf8605e2 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -44,6 +44,25 @@ #ifndef PCI_EXP_DEVCTL2_ATOMIC_BLOCK #define PCI_EXP_DEVCTL2_ATOMIC_BLOCK 0x0040 /* Block AtomicOp on egress */ #endif +#ifndef PCI_EXP_LNKCTL2_ENTER_COMP +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#endif +#ifndef PCI_EXP_LNKCTL2_TX_MARGIN +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ +#endif + +#ifndef PCI_EXP_LNKCTL2_TLS +#define PCI_EXP_LNKCTL2_TLS 0x000f +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_2_5GT +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_5_0GT +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_8_0GT +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#endif #ifndef PCIE_SPEED_16_0GT #define PCIE_SPEED_16_0GT 0x17 From e6a344c48a27201f726dc1acbfc2bd81b4490057 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Fri, 28 Aug 2020 16:25:15 +0800 Subject: [PATCH 0514/2070] drm/amdkcl: add macro for_each_if Signed-off-by: Tianci Yin Signed-off-by: tianci yin --- include/kcl/kcl_drm_crtc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index e0eaa2ace66b1..8b8b027aefbf9 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -74,6 +74,12 @@ DRM_MODE_ROTATE_270) #endif +/* Copied from include/drm/drm_util.h */ +/* helper for handling conditionals in various for_each macros */ +#ifndef for_each_if +#define for_each_if(condition) if (!(condition)) {} else +#endif + #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline From e280018dd169aee5c8f11a9140e3767f7bba8a2d Mon Sep 17 00:00:00 2001 From: changzhu Date: Wed, 26 Aug 2020 10:08:03 +0800 Subject: [PATCH 0515/2070] drm/amdkcl: check whether drm_for_each_xxx macros are available This is a squahs of: drm/amdkcl: drop redundant macro Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang This commit is used to fix bug in kcl_drm.h in redhat 7.2 v2: 57e9a478b988 - Clean up KCL macros. v3: drm/amdkcl: remove kcl_drm_for_each_ macro v4: move to kcl_drm_crtc.h Signed-off-by: changzhu Reviewed-by: Amber Lin Signed-off-by: Flora Cui --- include/kcl/kcl_drm_crtc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 8b8b027aefbf9..2f01179d0c2b1 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -80,6 +80,21 @@ #define for_each_if(condition) if (!(condition)) {} else #endif +#ifndef drm_for_each_crtc +#define drm_for_each_crtc(crtc, dev) \ + list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) +#endif + +#ifndef drm_for_each_encoder +#define drm_for_each_encoder(encoder, dev) \ + list_for_each_entry(encoder, &(dev)->mode_config.encoder_list, head) +#endif + +#ifndef drm_for_each_fb +#define drm_for_each_fb(fb, dev) \ + list_for_each_entry(fb, &(dev)->mode_config.fb_list, head) +#endif + #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline @@ -89,4 +104,5 @@ int drm_helper_force_disable_all(struct drm_device *dev) } #endif + #endif From f41d7e960ae68cdedb907f28461dbd8ce49a46fe Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 29 Jul 2019 11:14:34 +0800 Subject: [PATCH 0516/2070] drm/amdkcl: check whether DP_DPRX_FEATURE_ENUMERATION_LIST is available This is a squash of: drm/amdkcl: test DP_TRAINING_PATTERN_SET_PHY_REPEATER1 directly Change-Id: I883c0612c232e08039518f40a794fdb9b148cd16 Signed-off-by: Stanley.Yang Reviewed-by: Rui Teng Signed-off-by: Yifan Zhang drm/amdkcl: test DP_TEST_AUDIO_MODE directory Change-Id: I1b903fc00c3710f88d9db5bd5f72bd60e88d7373 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang drm/amdkcl: fake macro DP_DSC_SUPPORT Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang drm/amdkcl: move DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED check to kcl_drm_dp_helper.h Signed-off-by: Chengming Gui Reviewed-by: Flora Cui drm/amdkcl: refactor dp related macros Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: fake kcl copy of DP_PHY_TEST_PATTERN Signed-off-by: Flora Cui Change-Id: I351a01e5881df067a68f0128ec48aba922e42790 Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- include/kcl/kcl_drm_dp_helper.h | 165 ++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 include/kcl/kcl_drm_dp_helper.h diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h new file mode 100644 index 0000000000000..edb6b4202915b --- /dev/null +++ b/include/kcl/kcl_drm_dp_helper.h @@ -0,0 +1,165 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + + +#ifndef _KCL_DRM_DP_HELPER_H_ +#define _KCL_DRM_DP_HELPER_H_ + +#include +#include +#include + +#include +#include +#include +#include + +/* + * v4.13-rc5-840-gc673fe7f0cd5 + * drm/dp: DPCD register defines for link status within ESI field + */ +#ifndef DP_LANE0_1_STATUS_ESI +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ +#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ +#endif + +/* + * v4.13-rc5-1383-gac58fff15516 + * drm/dp-helper: add missing defines needed by AMD display core. + */ +#ifndef DP_ADJUST_REQUEST_POST_CURSOR2 +#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c + +#define DP_TEST_MISC0 0x232 + +#define DP_TEST_PHY_PATTERN 0x248 +#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 +#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 +#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 +#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 +#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 +#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 +#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 +#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 +#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 +#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 + +#define DP_BRANCH_REVISION_START 0x509 + +#define DP_DP13_DPCD_REV 0x2200 +#define DP_DP13_MAX_LINK_RATE 0x2201 +#endif + + +#if !defined(DP_DPRX_FEATURE_ENUMERATION_LIST) +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ +#endif + +#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#endif + +#if !defined(DP_LANE0_1_STATUS_PHY_REPEATER1) +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#endif + +#if !defined(DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1) +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#endif + +#if !defined(DP_TRAINING_LANE0_SET_PHY_REPEATER1) +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE_TRANSPARENT) +#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE) +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE_NON_TRANSPARENT) +#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ +#endif + +#if !defined(DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#endif + +#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT) +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#endif + +#if !defined(DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV) +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#endif + +#if !defined(DP_MAX_LINK_RATE_PHY_REPEATER) +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#endif + +#if !defined(DP_PHY_REPEATER_CNT) +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#endif + +#if !defined(DP_MAX_LANE_COUNT_PHY_REPEATER) +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#endif + +#if !defined(DP_TEST_AUDIO_MODE) +#define DP_TEST_AUDIO_MODE 0x271 +#endif + +#if !defined(DP_TEST_AUDIO_PATTERN_TYPE) +#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 +#endif + +#if !defined(DP_TEST_AUDIO_PERIOD_CH1) +#define DP_TEST_AUDIO_PERIOD_CH1 0x273 +#endif + +#if !defined(DP_DSC_SUPPORT) +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ +#endif + +/* + * v5.6-1624-g8811d9eb4dfa + * drm/amd/display: Align macro name as per DP spec + */ +#ifdef DP_TEST_PHY_PATTERN +#define DP_PHY_TEST_PATTERN DP_TEST_PHY_PATTERN +#endif + +/* commit fc1424c2ec813080aa1eaa2948070902b1a0e507 + * drm: Correct DP DSC macro typo */ +#ifdef DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED +#define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED +#endif + +#endif /* _KCL_DRM_DP_HELPER_H_ */ From ee2ec385cc7f38456fe1ac075014e4f76906e849 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 18:24:00 +0800 Subject: [PATCH 0517/2070] drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL && AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL dma_fence_get_rcu_safe() history: v4.8-rc8-1410-g4be0542073a3 introduce +static inline struct fence *fence_get_rcu_safe(struct fence * __rcu *fencep) v4.9-rc2-299-gf54d1867005c dma-buf: Rename struct fence to dma_fence v4.14-rc3-486-gf8e0731db4a0 dma-fence: fix dma_fence_get_rcu_safe v2 - if (!fence || !dma_fence_get_rcu(fence)) + if (!fence) return NULL; + if (!dma_fence_get_rcu(fence)) + continue; + v4.14-rc3-601-g5f72db59160c dma-buf/fence: Sparse wants __rcu on the object itself -dma_fence_get_rcu_safe(struct dma_fence * __rcu *fencep) +dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) v1: drm/amdkcl: [4.8] add fence array support v2: drm/amdkcl: Test whether dma_fence header is available v3: drm/amdkcl: refactor kcl copy dma_fence_is_later() v4: drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL v5: drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL v6: drm/amdkcl: refactor check for dma_fence_wait_any_timeout v7: drm/amdkcl: refactor check for fence_default_wait, fence_wait_timeout v8: drm/amdkcl: refactor check for fence_get_rcu_safe v9: drm/amdkcl: include kcl_fence.h for dkms build v10: drm/amdkcl: drop kcl_fence_context_alloc & kcl_fence_init v11: drm/amdkcl: fix kcl_fence_get_rcu_safe() v12: drm/amdkcl: fix kcl_fence_default_wait v13: drm/amdkcl: drop test for linux/dma-fence.h outside of kcl v14: drm/amdkcl: drop test for linux/dma-fence-array.h outside of kcl Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + drivers/gpu/drm/scheduler/sched_fence.c | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 31b8fa52b42fa..984a752542a54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -190,5 +190,6 @@ static const struct dma_fence_ops amdkfd_fence_ops = { .get_driver_name = amdkfd_fence_get_driver_name, .get_timeline_name = amdkfd_fence_get_timeline_name, .enable_signaling = amdkfd_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdkfd_fence_release, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 6b14cbf8452fa..49fc459314a47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -855,6 +855,7 @@ static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, .enable_signaling = amdgpu_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_fence_release, }; diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 9391d6f0dc01d..acd4eaab1fd03 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -183,12 +183,16 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, + AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_scheduled, }; static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, + AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, .set_deadline = drm_sched_fence_set_deadline_finished, }; From 0483ad05f408242dc1f83b3821b5d2760dc19eec Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 13 Jul 2020 14:39:08 +0800 Subject: [PATCH 0518/2070] drm/amdgpu: [hybrid] add direct gma(dgma) support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: rebase on linux 4.18 and cleanup v3: 3f8d459ca0f1("drm/amdgpu: [hybrid] fix DGMA buffer info loss issue (v2)") v4: 814cd038a6b5(drm/amdkcl: modify DGMA setting for new PL_DOORBELL support) Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Junwei Zhang (v2) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Acked-by: Christian König Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 97 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 111 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 15 + drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 480 +++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 36 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 228 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 35 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 15 files changed, 1022 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hmm.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 30248b838288a..7fea74ffe51d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -314,7 +314,7 @@ endif amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o -amdgpu-$(CONFIG_HMM_MIRROR) += amdgpu_hmm.o +amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_hmm.o include $(FULL_AMD_PATH)/pm/Makefile diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ae8bbd872003a..d10b57fb43618 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1173,7 +1173,9 @@ struct amdgpu_device { enum pp_mp1_state mp1_state; struct amdgpu_doorbell_index doorbell_index; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct mutex notifier_lock; +#endif int asic_reset_res; struct work_struct xgmi_reset_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index c4adcc9857a40..4767c46721c1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -84,6 +84,9 @@ struct kgd_mem { uint32_t invalid; struct amdkfd_process_info *process_info; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct page **user_pages; +#endif struct amdgpu_sync sync; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7a16fb5d82a13..8471c76bc379f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1103,6 +1103,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { amdgpu_hmm_range_free(range); @@ -1112,6 +1113,29 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto unregister_out; } +#else + /* If no restore worker is running concurrently, user_pages + * should not be allocated + */ + WARN(mem->user_pages, "Leaking user_pages array"); + + mem->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", __func__); + ret = -ENOMEM; + goto unregister_out; + } + + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + pr_err("%s: Failed to get user pages: %d\n", __func__, ret); + goto free_out; + } + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); +#endif ret = amdgpu_bo_reserve(bo, true); if (ret) { @@ -1128,7 +1152,15 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_bo_unreserve(bo); release_out: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(range); +#else + if (ret) + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); +free_out: + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif unregister_out: if (ret) amdgpu_hmm_unregister(bo); @@ -1936,6 +1968,17 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( list_del_init(&mem->validate_list); mutex_unlock(&process_info->lock); +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, + mem->bo->tbo.ttm->num_pages); + kvfree(mem->user_pages); + } +#endif + ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) return ret; @@ -2835,6 +2878,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, mem->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!mem->range)) return -ENOMEM; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { @@ -2871,11 +2915,37 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = 0; } - amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->range); +#else + if (!mem->user_pages) { + mem->user_pages = + kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", + __func__); + return -ENOMEM; + } + } else if (mem->user_pages[0]) { + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + } - mutex_lock(&process_info->notifier_lock); + /* Get updated user pages */ + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + mem->user_pages[0] = NULL; + pr_info("%s: Failed to get user pages: %d\n", + __func__, ret); + /* Pretend it succeeded. It will fail later + * with a VM fault if the GPU tries to access + * it. Better than hanging indefinitely with + * stalled user mode queues. + */ + } +#endif + mutex_lock(&process_info->notifier_lock); /* Mark the BO as valid unless it was invalidated * again concurrently. */ @@ -2949,6 +3019,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Validate the BO if we got user pages */ if (bo->tbo.ttm->pages[0]) { amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -2959,6 +3030,28 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } } +#else + /* Copy pages array and validate the BO if we got user pages */ + if (mem->user_pages[0]) { + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, + mem->user_pages); + amdgpu_bo_placement_from_domain(bo, mem->domain); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) { + pr_err("%s: failed to validate BO\n", __func__); + goto unreserve_out; + } + } + + /* Validate succeeded, now the BO owns the pages, free + * our copy of the pointer array. Put this BO back on + * the userptr_valid_list. If we need to revalidate + * it, we need to start from scratch. + */ + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif + /* Update mapping. If the BO was not validated * (because we couldn't get user pages), this will * clear the page table entries, which will result in diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 2b5e7c46a39d4..ad81170f068da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -39,7 +39,11 @@ struct amdgpu_bo_list_entry { struct amdgpu_bo_va *bo_va; uint32_t priority; struct amdgpu_hmm_range *range; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; +#else + int user_invalidated; +#endif }; struct amdgpu_bo_list { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index e41efb649485e..9d2ea8e8b26d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -866,6 +866,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo_list_entry *e; struct drm_gem_object *obj; unsigned long index; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + unsigned tries = 10; +#endif unsigned int i; int r; @@ -888,6 +891,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, mutex_lock(&p->bo_list->bo_list_mutex); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get userptr backing pages. If pages are updated after registered * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do * amdgpu_ttm_backend_bind() to flush and invalidate new pages @@ -941,6 +946,82 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } +#else + while (1) { + struct list_head need_pages; + + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, + &duplicates); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); + goto error_free_pages; + } + + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { + + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } + } + + /* And try again. */ + list_splice(&need_pages, &p->validated); + } +#endif amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct mm_struct *usermm; @@ -1000,11 +1081,24 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bo_list->oa_obj); return 0; + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED out_free_user_pages: amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { amdgpu_hmm_range_free(e->range); e->range = NULL; } +#else +error_free_pages: + + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + if (!e->user_pages) + continue; + + release_pages(e->user_pages, e->tv.bo->ttm->num_pages); + kvfree(e->user_pages); + } +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return r; } @@ -1328,6 +1422,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_job_set_gang_leader(p->jobs[i], leader); } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* No memory allocation is allowed while holding the notifier lock. * The lock is held until amdgpu_cs_submit is finished and fence is * added to BOs. @@ -1348,6 +1443,18 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, mutex_unlock(&p->adev->notifier_lock); return r; } +#else + /* No memory allocation is allowed while holding the mn lock */ + amdgpu_mn_lock(p->mn); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { + r = -ERESTARTSYS; + goto error_abort; + } + } +#endif p->fence = dma_fence_get(&leader->base.s_fence->finished); drm_exec_for_each_locked_object(&p->exec, index, gobj) { @@ -1391,7 +1498,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_unlock(&p->adev->notifier_lock); +#else + amdgpu_mn_unlock(p->mn); +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 17be9c157ca5a..4977c17a41659 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4430,7 +4430,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_init(&adev->notifier_lock); +#endif mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); mutex_init(&adev->gfx.reset_sem_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index d44d3a32f826b..f60e46a5dfa68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -600,14 +600,29 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, } r = drm_gem_handle_create(filp, gobj, &handle); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (r) goto user_pages_done; args->handle = handle; +#else + /* drop reference from allocate - handle holds it now */ + drm_gem_object_put(gobj); + if (r) + return r; + + args->handle = handle; + return 0; +#endif user_pages_done: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) amdgpu_hmm_range_free(range); +#else + release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); +#endif + release_object: drm_gem_object_put(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 1ec995c8384d4..ca398dbd5975a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -51,8 +51,485 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_hmm.h" -#define MAX_WALK_BYTE (2UL << 30) +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +/** + * struct amdgpu_mn + * + * @adev: amdgpu device pointer + * @mm: process address space + * @mn: MMU notifier structure + * @type: type of MMU notifier + * @work: destruction work item + * @node: hash table node to find structure by adev and mn + * @lock: rw semaphore protecting the notifier nodes + * @objects: interval tree containing amdgpu_mn_nodes + * @read_lock: mutex for recursive locking of @lock + * @recursion: depth of recursion + * + * Data for each amdgpu device and process address space. + */ +struct amdgpu_mn { + /* constant after initialisation */ + struct amdgpu_device *adev; + struct mm_struct *mm; + struct mmu_notifier mn; + enum amdgpu_mn_type type; + + /* only used on destruction */ + struct work_struct work; + + /* protected by adev->mn_lock */ + struct hlist_node node; + + /* objects protected by lock */ + struct rw_semaphore lock; + struct rb_root_cached objects; + struct mutex read_lock; + atomic_t recursion; +}; + +/** + * struct amdgpu_mn_node + * + * @it: interval node defining start-last of the affected address range + * @bos: list of all BOs in the affected address range + * + * Manages all BOs which are affected of a certain range of address space. + */ +struct amdgpu_mn_node { + struct interval_tree_node it; + struct list_head bos; +}; + +/** + * amdgpu_mn_destroy - destroy the MMU notifier + * + * @work: previously sheduled work item + * + * Lazy destroys the notifier from a work item + */ +static void amdgpu_mn_destroy(struct work_struct *work) +{ + struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work); + struct amdgpu_device *adev = amn->adev; + struct amdgpu_mn_node *node, *next_node; + struct amdgpu_bo *bo, *next_bo; + + mutex_lock(&adev->mn_lock); + down_write(&amn->lock); + hash_del(&amn->node); + rbtree_postorder_for_each_entry_safe(node, next_node, + &amn->objects.rb_root, it.rb) { + list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { + bo->mn = NULL; + list_del_init(&bo->mn_list); + } + kfree(node); + } + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); + mmu_notifier_unregister_no_release(&amn->mn, amn->mm); + kfree(amn); +} + +/** + * amdgpu_mn_release - callback to notify about mm destruction + * + * @mn: our notifier + * @mm: the mm this callback is about + * + * Shedule a work item to lazy destroy our notifier. + */ +static void amdgpu_mn_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + INIT_WORK(&amn->work, amdgpu_mn_destroy); + schedule_work(&amn->work); +} + + +/** + * amdgpu_mn_lock - take the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_lock(struct amdgpu_mn *mn) +{ + if (mn) + down_write(&mn->lock); +} + +/** + * amdgpu_mn_unlock - drop the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_unlock(struct amdgpu_mn *mn) +{ + if (mn) + up_write(&mn->lock); +} + +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) +{ + if (blockable) + mutex_lock(&amn->read_lock); + else if (!mutex_trylock(&amn->read_lock)) + return -EAGAIN; + + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); + + return 0; +} + +/** + * amdgpu_mn_read_unlock - drop the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn) +{ + if (atomic_dec_return(&amn->recursion) == 0) + up_read_non_owner(&amn->lock); +} + +/** + * amdgpu_mn_invalidate_node - unmap all BOs of a node + * + * @node: the node with the BOs to unmap + * @start: start of address range affected + * @end: end of address range affected + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, + unsigned long start, + unsigned long end) +{ + struct amdgpu_bo *bo; + long r; + + list_for_each_entry(bo, &node->bos, mn_list) { + + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) + continue; + + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), + true, false, MAX_SCHEDULE_TIMEOUT); + if (r <= 0) + DRM_ERROR("(%ld) failed to wait for user bo\n", r); + + amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm); + } +} + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @range: mmu notifier context + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + /* TODO we should be able to split locking for interval tree and + * amdgpu_mn_invalidate_node + */ + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + + if (!mmu_notifier_range_blockable(range)) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + amdgpu_mn_invalidate_node(node, range->start, end); + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + + if (!mmu_notifier_range_blockable(range)) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + range->start, + end)) + amdgpu_amdkfd_evict_userptr(mem, range->mm); + } + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_end - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Release the lock again to allow new command submissions. + */ +static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + amdgpu_mn_read_unlock(amn); +} + +static const struct mmu_notifier_ops amdgpu_mn_ops[] = { + [AMDGPU_MN_TYPE_GFX] = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, + [AMDGPU_MN_TYPE_HSA] = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, +}; + +/* Low bits of any reasonable mm pointer will be unused due to struct + * alignment. Use these bits to make a unique key from the mm pointer + * and notifier type. + */ +#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type)) + +/** + * amdgpu_mn_get - create notifier context + * + * @adev: amdgpu device pointer + * @type: type of MMU notifier context + * + * Creates a notifier context for current->mm. + */ +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + struct mm_struct *mm = current->mm; + struct amdgpu_mn *amn; + unsigned long key = AMDGPU_MN_KEY(mm, type); + int r; + + mutex_lock(&adev->mn_lock); + if (down_write_killable(&mm->mmap_sem)) { + mutex_unlock(&adev->mn_lock); + return ERR_PTR(-EINTR); + } + + hash_for_each_possible(adev->mn_hash, amn, node, key) + if (AMDGPU_MN_KEY(amn->mm, amn->type) == key) + goto release_locks; + + amn = kzalloc(sizeof(*amn), GFP_KERNEL); + if (!amn) { + amn = ERR_PTR(-ENOMEM); + goto release_locks; + } + + amn->adev = adev; + amn->mm = mm; + init_rwsem(&amn->lock); + amn->type = type; + amn->mn.ops = &amdgpu_mn_ops[type]; + amn->objects = RB_ROOT_CACHED; + mutex_init(&amn->read_lock); + atomic_set(&amn->recursion, 0); + + r = __mmu_notifier_register(&amn->mn, mm); + if (r) + goto free_amn; + + hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type)); + +release_locks: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + + return amn; + +free_amn: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + kfree(amn); + + return ERR_PTR(r); +} + +/** + * amdgpu_mn_register - register a BO for notifier updates + * + * @bo: amdgpu buffer object + * @addr: userptr addr we should monitor + * + * Registers an MMU notifier for the given BO at the specified address. + * Returns 0 on success, -ERRNO if anything goes wrong. + */ +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + unsigned long end = addr + amdgpu_bo_size(bo) - 1; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + enum amdgpu_mn_type type = + bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX; + struct amdgpu_mn *amn; + struct amdgpu_mn_node *node = NULL, *new_node; + struct list_head bos; + struct interval_tree_node *it; + + amn = amdgpu_mn_get(adev, type); + if (IS_ERR(amn)) + return PTR_ERR(amn); + + new_node = kmalloc(sizeof(*new_node), GFP_KERNEL); + if (!new_node) + return -ENOMEM; + + INIT_LIST_HEAD(&bos); + + down_write(&amn->lock); + + while ((it = interval_tree_iter_first(&amn->objects, addr, end))) { + kfree(node); + node = container_of(it, struct amdgpu_mn_node, it); + interval_tree_remove(&node->it, &amn->objects); + addr = min(it->start, addr); + end = max(it->last, end); + list_splice(&node->bos, &bos); + } + + if (!node) + node = new_node; + else + kfree(new_node); + + bo->mn = amn; + + node->it.start = addr; + node->it.last = end; + INIT_LIST_HEAD(&node->bos); + list_splice(&bos, &node->bos); + list_add(&bo->mn_list, &node->bos); + + interval_tree_insert(&node->it, &amn->objects); + + up_write(&amn->lock); + + return 0; +} + +/** + * amdgpu_mn_unregister - unregister a BO for notifier updates + * + * @bo: amdgpu buffer object + * + * Remove any registration of MMU notifier updates from the buffer object. + */ +void amdgpu_mn_unregister(struct amdgpu_bo *bo) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_mn *amn; + struct list_head *head; + + mutex_lock(&adev->mn_lock); + + amn = bo->mn; + if (amn == NULL) { + mutex_unlock(&adev->mn_lock); + return; + } + + down_write(&amn->lock); + + /* save the next list entry for later */ + head = bo->mn_list.next; + + bo->mn = NULL; + list_del_init(&bo->mn_list); + + if (list_empty(head)) { + struct amdgpu_mn_node *node; + + node = container_of(head, struct amdgpu_mn_node, bos); + interval_tree_remove(&node->it, &amn->objects); + kfree(node); + } + + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); +} + +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#define MAX_WALK_BYTE (2UL << 30) /** * amdgpu_hmm_invalidate_gfx - callback to notify about mm change * @@ -291,3 +768,4 @@ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) amdgpu_bo_unref(&range->bo); kfree(range); } +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 140bc9cd57b42..77a33d65bc987 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -24,6 +24,41 @@ #ifndef __AMDGPU_MN_H__ #define __AMDGPU_MN_H__ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#include +/* + * MMU Notifier + */ +struct amdgpu_mn; + +enum amdgpu_mn_type { + AMDGPU_MN_TYPE_GFX, + AMDGPU_MN_TYPE_HSA, +}; + +#if defined(CONFIG_MMU_NOTIFIER) +void amdgpu_mn_lock(struct amdgpu_mn *mn); +void amdgpu_mn_unlock(struct amdgpu_mn *mn); +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type); +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_mn_unregister(struct amdgpu_bo *bo); +#else /* !CONFIG_MMU_NOTIFIER */ +static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} +static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} +static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + return NULL; +} +static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + return -ENODEV; +} +static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +#endif /* CONFIG_MMU_NOTIFIER */ +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include #include #include @@ -69,5 +104,6 @@ static inline struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo * static inline void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) {} #endif +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index f7f93243369ef..7a3a809063658 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -113,9 +113,14 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; #endif +#else + struct list_head mn_list; +#endif + struct kgd_mem *kfd_bo; /* DGMA imported buffer info */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 24b79559ad63c..2d3f725b046af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -32,6 +32,9 @@ #include #include +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#endif #include #include #include @@ -731,6 +734,13 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) /* * TTM backend functions. */ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +struct amdgpu_ttm_gup_task_list { + struct list_head list; + struct task_struct *task; +}; +#endif + struct amdgpu_ttm_tt { struct ttm_tt ttm; struct drm_gem_object *gobj; @@ -739,12 +749,19 @@ struct amdgpu_ttm_tt { struct task_struct *usertask; uint32_t userflags; bool bound; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spinlock_t guptasklock; + struct list_head guptasks; + atomic_t mmu_invalidations; + uint32_t last_set_pages; +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ int32_t pool_id; }; #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) #ifdef CONFIG_DRM_AMDGPU_USERPTR +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update @@ -797,9 +814,88 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return r; } +#else +/* + * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR + * pointer to memory + * + * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos(). + * This provides a wrapper around the get_user_pages() call to provide + * device accessible pages that back user memory. + */ +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +{ + struct ttm_tt *ttm = bo->tbo.ttm; + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct mm_struct *mm = gtt->usertask->mm; + unsigned int flags = 0; + unsigned pinned = 0; + int r; -#endif + if (!mm) /* Happens during process shutdown */ + return -ESRCH; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + flags |= FOLL_WRITE; + + down_read(&mm->mmap_sem); + + if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { + /* + * check that we only use anonymous memory to prevent problems + * with writeback + */ + unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; + struct vm_area_struct *vma; + + vma = find_vma(mm, gtt->userptr); + if (!vma || vma->vm_file || vma->vm_end < end) { + up_read(&mm->mmap_sem); + return -EPERM; + } + } + + /* loop enough times using contiguous pages of memory */ + do { + unsigned num_pages = ttm->num_pages - pinned; + uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; + struct page **p = pages + pinned; + struct amdgpu_ttm_gup_task_list guptask; + + guptask.task = current; + spin_lock(>t->guptasklock); + list_add(&guptask.list, >t->guptasks); + spin_unlock(>t->guptasklock); + + if (mm == current->mm) + r = get_user_pages(userptr, num_pages, flags, p, NULL); + else + r = get_user_pages_remote(mm, userptr, num_pages, + flags, p, NULL, NULL); + + spin_lock(>t->guptasklock); + list_del(&guptask.list); + spin_unlock(>t->guptasklock); + + if (r < 0) + goto release_pages; + + pinned += r; + } while (pinned < ttm->num_pages); + + up_read(&mm->mmap_sem); + return 0; + +release_pages: + release_pages(pages, pinned); + up_read(&mm->mmap_sem); + return r; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif /* CONFIG_DRM_AMDGPU_USERPTR */ + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. * @@ -815,6 +911,52 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *r ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; } +#else +/** + * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. + * + * Called by amdgpu_cs_list_validate(). This creates the page list + * that backs user memory and will ultimately be mapped into the device + * address space. + */ +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + gtt->last_set_pages = atomic_read(>t->mmu_invalidations); + for (i = 0; i < ttm->num_pages; ++i) { + if (ttm->pages[i]) + put_page(ttm->pages[i]); + + ttm->pages[i] = pages ? pages[i] : NULL; + } +} + +/** + * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty + * + * Called while unpinning userptr pages + */ +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + for (i = 0; i < ttm->num_pages; ++i) { + struct page *page = ttm->pages[i]; + + if (!page) + continue; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + set_page_dirty(page); + + mark_page_accessed(page); + } +} +#endif + /* * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages * @@ -874,7 +1016,15 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, /* unmap the pages mapped to the device */ dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED + sg_free_table(ttm->sg); +#else + /* mark the pages as dirty */ + amdgpu_ttm_tt_mark_user_pages(ttm); + sg_free_table(ttm->sg); +#endif } /* @@ -1370,6 +1520,13 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, gtt->usertask = current->group_leader; get_task_struct(gtt->usertask); +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spin_lock_init(>t->guptasklock); + INIT_LIST_HEAD(>t->guptasks); + atomic_set(>t->mmu_invalidations, 0); + gtt->last_set_pages = 0; +#endif + return 0; } @@ -1389,6 +1546,7 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) return gtt->usertask->mm; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an * address range for the current task. @@ -1428,6 +1586,74 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) return true; } +#else +/* + * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an + * address range for the current task. + * + */ +bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, + unsigned long end) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct amdgpu_ttm_gup_task_list *entry; + unsigned long size; + + if (gtt == NULL || !gtt->userptr) + return false; + + /* Return false if no part of the ttm_tt object lies within + * the range + */ + size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; + if (gtt->userptr > end || gtt->userptr + size <= start) + return false; + + /* Search the lists of tasks that hold this mapping and see + * if current is one of them. If it is return false. + */ + spin_lock(>t->guptasklock); + list_for_each_entry(entry, >t->guptasks, list) { + if (entry->task == current) { + spin_unlock(>t->guptasklock); + return false; + } + } + spin_unlock(>t->guptasklock); + + atomic_inc(>t->mmu_invalidations); + + return true; +} + +/** + * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated? + */ +bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, + int *last_invalidated) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + int prev_invalidated = *last_invalidated; + + *last_invalidated = atomic_read(>t->mmu_invalidations); + return prev_invalidated != *last_invalidated; +} + +/** + * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object + * been invalidated since the last time they've been set? + */ +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL || !gtt->userptr) + return false; + + return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ + /* * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index f8ff6582718a5..cfb10ecf74047 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -248,9 +248,14 @@ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, unsigned long end, unsigned long *userptr); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +#else bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, int *last_invalidated); -bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm); +#endif bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 new file mode 100644 index 0000000000000..5cda4aed70d25 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 +dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 +dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 +dnl # a22dd506400d - mm/hmm: remove hmm_mirror and related 2019-11-23 19:56:45 -0400 +dnl # 81fa1af31b5d - drm/amdgpu: Use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # 62914a99dee5 - drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # a9ae8731e6e5 - drm/amdgpu: Call find_vma under mmap_sem 2019-11-23 19:56:44 -0400 +dnl # 20fef4ef84bf - nouveau: use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # c625c274ee00 - nouveau: use mmu_notifier directly for invalidate_range_start 2019-11-23 19:56:44 -0400 +dnl # 3506ff69c3ec - drm/radeon: use mmu_interval_notifier_insert 2019-11-23 19:56:44 -0400 +dnl # 3889551db212 - RDMA/hfi1: Use mmu_interval_notifier_insert for user_exp_rcv 2019-11-23 19:56:44 -0400 +dnl # f25a546e6529 - RDMA/odp: Use mmu_interval_notifier_insert() 2019-11-23 19:56:44 -0400 +dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h even if disabled 2019-11-23 19:56:44 -0400 +dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 +dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # +AC_DEFUN([AC_AMDGPU_HMM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifdef CONFIG_HMM_MIRROR + struct hmm_range *range = NULL; + range->notifier = NULL; + #else + #error CONFIG_HMM_MIRROR not enabled + #endif + ], [ + AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, + [hmm support is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 791616d192d67..97cb9cf1b25c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_HMM AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From e8a430e6d6dd804945905f17554c8665e43e826c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 31 Aug 2020 15:42:28 +0800 Subject: [PATCH 0519/2070] drm/amdkcl: fake hmm_range_fault() protocol changed in v5.6-rc3-21-g6bfef2f91945("mm/hmm: remove HMM_FAULT_SNAPSHOT") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 16 ++++++++++++++++ include/kcl/backport/kcl_hmm.h | 18 ++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 include/kcl/backport/kcl_hmm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e079d86a1275e..1d068ea4dab5c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,6 +32,7 @@ #include #include #include +#include #include #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ #include diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 5cda4aed70d25..1e351ff9c3b3f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -1,3 +1,18 @@ +dnl # +dnl # v5.6-rc3-21-g6bfef2f91945 +dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT +dnl # +AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL); + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) +]) + dnl # dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 @@ -30,6 +45,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ ], [ AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, [hmm support is enabled]) + AC_AMDGPU_HMM_RANGE_FAULT ]) ]) ]) diff --git a/include/kcl/backport/kcl_hmm.h b/include/kcl/backport/kcl_hmm.h new file mode 100644 index 0000000000000..233b0cbda947a --- /dev/null +++ b/include/kcl/backport/kcl_hmm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_BACKPORT_KCL_HMM_H +#define _KCL_BACKPORT_KCL_HMM_H + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include + +#ifndef HAVE_HMM_RANGE_FAULT_1ARG +static inline +int _kcl_hmm_range_fault(struct hmm_range *range) +{ + return hmm_range_fault(range, 0); +} +#define hmm_range_fault _kcl_hmm_range_fault +#endif /* HAVE_HMM_RANGE_FAULT_1ARG */ + +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif From d81fa3886f4739570e04706ae420761dd0a0db83 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 31 Aug 2020 16:06:54 +0800 Subject: [PATCH 0520/2070] drm/amdkcl: test whether hmm remove the customizable pfn format Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 26 +++++++++++++++++++++---- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 2d3f725b046af..3676745ea7c82 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -762,6 +762,20 @@ struct amdgpu_ttm_tt { #ifdef CONFIG_DRM_AMDGPU_USERPTR #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 1e351ff9c3b3f..228e66022b959 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -1,15 +1,33 @@ dnl # -dnl # v5.6-rc3-21-g6bfef2f91945 -dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT +dnl # v5.7-rc4-4-g2733ea144dcc mm/hmm: remove the customizable pfn format from hmm_range_fault +dnl # v5.7-rc4-3-g5c8f3c4cf18a mm/hmm: remove HMM_PFN_SPECIAL +dnl # v5.7-rc4-2-g4e2490843d55 drm/amdgpu: remove dead code after hmm_range_fault() +dnl # v5.7-rc4-1-gbe957c886d92 mm/hmm: make hmm_range_fault return 0 or -1 dnl # AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - hmm_range_fault(NULL); + enum hmm_pfn_flags flag; + flag = HMM_PFN_REQ_FAULT; ], [ + AC_DEFINE(HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT, 1, + [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, - [hmm_range_fault() wants 1 arg]) + [hmm_range_fault() wants 1 arg]) + ], [ + dnl # + dnl # v5.6-rc3-21-g6bfef2f91945 + dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL);; + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) ]) ]) From 895b55c23da47368906a048e22728368bf4ef749 Mon Sep 17 00:00:00 2001 From: chen gong Date: Fri, 3 May 2019 11:53:41 +0800 Subject: [PATCH 0521/2070] drm/amdkcl: Test whether invalidate_range_start() wants 2 args or 5 args Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix invalidate_range_end() leverage HAVE_2ARGS_INVALIDATE_RANGE_START for invalidate_range_end() check Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 145 ++++++++++++++++++ .../drm/amd/dkms/m4/invalidate-range-start.m4 | 36 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 182 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index ca398dbd5975a..d1c0de24ddb0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -172,6 +172,20 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) up_write(&mn->lock); } +#if !defined(HAVE_5ARGS_INVALIDATE_RANGE_START) && !defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) +{ + mutex_lock(&amn->read_lock); + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); +} +#else /** * amdgpu_mn_read_lock - take the read side lock for this notifier * @@ -190,6 +204,7 @@ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) return 0; } +#endif /** * amdgpu_mn_read_unlock - drop the read side lock for this notifier @@ -233,6 +248,7 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, } } +#if defined(HAVE_2ARGS_INVALIDATE_RANGE_START) /** * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change * @@ -327,6 +343,129 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, return 0; } +#else + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (!blockable) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } +#endif + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + amdgpu_mn_invalidate_node(node, start, end); + } +} + + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (!blockable) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } +#endif + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + start, end)) + amdgpu_amdkfd_evict_userptr(mem, mm); + } + } +} + +#endif + /** * amdgpu_mn_invalidate_range_end - callback to notify about mm change * @@ -338,7 +477,13 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, * Release the lock again to allow new command submissions. */ static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, +#ifdef HAVE_2ARGS_INVALIDATE_RANGE_START const struct mmu_notifier_range *range) +#else + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); diff --git a/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 new file mode 100644 index 0000000000000..d9edaefbebdcf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 @@ -0,0 +1,36 @@ +dnl # +dnl # commit 5d6527a784f7a6d247961e046e830de8d71b47d1 +dnl # Author: Jérôme Glisse +dnl # Date: Fri Dec 28 00:38:05 2018 -0800 +dnl # mm/mmu_notifier: use structure for invalidate_range_start/end callback +dnl # Patch series "mmu notifier contextual informations", v2. +dnl # +AC_DEFUN([AC_AMDGPU_INVALIDATE_RANGE_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL); + ], [ + AC_DEFINE(HAVE_2ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 2 args) + ], [ + dnl # + dnl # commit 93065ac753e4443840a057bfef4be71ec766fde9 + dnl # Author: Michal Hocko + dnl # Date: Tue Aug 21 21:52:33 2018 -0700 + dnl # mm, oom: distinguish blockable mode for mmu notifiers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL, 1, 1, 1); + ], [ + AC_DEFINE(HAVE_5ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 5 args) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 97cb9cf1b25c5..73f8e3e49b6e8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,6 +36,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM + AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 19416b95e1f92a97095c4a8b02c973d2f263c0a3 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 12 Dec 2019 10:04:29 -0500 Subject: [PATCH 0522/2070] drm/amdkcl: add return value for amdgpu_mn_invalidate_range_start_gfx Otherwise it returns random value and generates below kernel warning. The return value is ignored by the calling function, this will just remove the warnings, no function change. v2: add return value for amdgpu_mn_invalidate_range_start_hsa Dec 9 10:08:33 debian-rocm kernel: [ 883.795760] amdgpu_mn_invalidate_range_start_hsa+0x0/0x100 [amdgpu] callback failed with 226470832 in blockable context. Dec 9 10:08:33 debian-rocm kernel: [ 883.805443] amdgpu_mn_invalidate_range_start_hsa+0x0/0x100 [amdgpu] callback failed with 226470832 in blockable context. Change-Id: I2ad1c8703c4d4ec615ccdd5d402dd2ccdf08136b Signed-off-by: Philip Yang Reviewed-by: Eric Huang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index d1c0de24ddb0c..6e55756feb143 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -398,6 +398,10 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, amdgpu_mn_invalidate_node(node, start, end); } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif } @@ -462,6 +466,10 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, amdgpu_amdkfd_evict_userptr(mem, mm); } } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif } #endif From bf649543049d01f2845a8f60ea62826de3829587 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Aug 2019 20:15:47 -0300 Subject: [PATCH 0523/2070] drm/amdkcl: Test whether mmu_notifier_synchronize is available introduced by kernel v5.3-rc1-29-g2c7933f53f6b Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I0a46e15c16ec5d3e79687a1a33e50069ba956244 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mmu-notifier-synchronize.m4 | 31 +++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 21ff6b1c8f6a1..6c65672b1853c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3290,7 +3290,9 @@ static void __exit amdgpu_exit(void) amdgpu_acpi_release(); amdgpu_sync_fini(); amdgpu_userq_fence_slab_fini(); +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE mmu_notifier_synchronize(); +#endif amdgpu_xcp_drv_release(); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index d80cb5b90bc0b..b351ceba59c9f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -971,6 +971,11 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; +#ifndef HAVE_MMU_NOTIFIER_SYNCHRONIZE + /* Use for delayed freeing of kfd_process structure */ + struct rcu_head rcu; +#endif + /* * Array of kfd_process_device pointers, * one for each device the process is using. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 33c36207c9701..071445a368156 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1277,6 +1277,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { /* This increments p->ref counter if kfd process p exists */ @@ -1289,6 +1290,14 @@ static void kfd_process_free_notifier(struct mmu_notifier *mn) { kfd_unref_process(container_of(mn, struct kfd_process, mmu_notifier)); } +#else +static void kfd_process_destroy_delayed(struct rcu_head *rcu) +{ + struct kfd_process *p = container_of(rcu, struct kfd_process, rcu); + + kfd_unref_process(p); +} +#endif static void kfd_process_table_remove(struct kfd_process *p) { @@ -1377,8 +1386,10 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, +#endif }; /* @@ -1600,7 +1611,9 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, struct kfd_process *create_process(const struct task_struct *thread, bool primary) { struct kfd_process *process; +#ifdef HAVE_MMU_NOTIFIER_PUT struct mmu_notifier *mn; +#endif int err = -ENOMEM; process = kzalloc(sizeof(*process), GFP_KERNEL); @@ -1659,12 +1672,20 @@ struct kfd_process *create_process(const struct task_struct *thread, bool primar */ if (primary) { process->context_id = KFD_CONTEXT_ID_PRIMARY; +#ifdef HAVE_MMU_NOTIFIER_PUT mn = mmu_notifier_get(&kfd_process_mmu_notifier_ops, process->mm); if (IS_ERR(mn)) { err = PTR_ERR(mn); goto err_register_notifier; } BUG_ON(mn != &process->mmu_notifier); +#else + /* Must be last, have to use release destruction after this */ + process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops; + err = mmu_notifier_register(&process->mmu_notifier, process->mm); + if (err) + goto err_register_notifier; +#endif ida_init(&process->id_table); } diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 73f8e3e49b6e8..87d66fc6faac2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -29,6 +29,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 new file mode 100644 index 0000000000000..a5e8dcde897ff --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.3-rc1-29-g2c7933f53f6b +dnl # mm/mmu_notifiers: add a get/put scheme for the registration +dnl # +dnl # amdkcl: mmu_notifier_put() & mmu_notifier_synchronize() is +dnl # introduced in the same commit, yet rhel7.7 has different behavior +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_PUT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_put(NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_PUT, 1, + [mmu_notifier_put() is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_synchronize(); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_SYNCHRONIZE, 1, + [mmu_notifier_synchronize() is available]) + ]) + AC_AMDGPU_MMU_NOTIFIER_PUT + ]) +]) From 0d008bf2d10d3c9301c6482ad7c27b2d6e649af7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 22:15:18 +0800 Subject: [PATCH 0524/2070] drm/amdkcl: Test whether mmu_notifier_put is available Change-Id: I6a1119a60093799f5560d72ea00b8bf44bc2b773 Signed-off-by: Flora Cui Signed-off-by: Jack.Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index b351ceba59c9f..22565f93c7134 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -971,7 +971,7 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; -#ifndef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifndef HAVE_MMU_NOTIFIER_PUT /* Use for delayed freeing of kfd_process structure */ struct rcu_head rcu; #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 071445a368156..766a6c0c4528b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1277,7 +1277,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } -#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifdef HAVE_MMU_NOTIFIER_PUT static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { /* This increments p->ref counter if kfd process p exists */ @@ -1386,7 +1386,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, -#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifdef HAVE_MMU_NOTIFIER_PUT .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, #endif From b5ac3a4d41f0afc9b1547929b86b9534cee8dc6f Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 1 Sep 2020 11:19:53 +0800 Subject: [PATCH 0525/2070] drm/amdkcl: Test whether get_user_{pages/pages_remote}() wants {5/6,8} args v2: rework get_user_pages() & get_user_pages_remote() test v3: adapt to get_user_pages_remote() prototype change (drop task_struct) Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Reviewed-by: Jack Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 53 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 30 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_mm_backport.h | 45 ++++++++++++++++ 5 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3676745ea7c82..a36236a61626a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -884,7 +884,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) if (mm == current->mm) r = get_user_pages(userptr, num_pages, flags, p, NULL); else - r = get_user_pages_remote(mm, userptr, num_pages, + r = kcl_get_user_pages_remote(gtt->usertask, + mm, userptr, num_pages, flags, p, NULL, NULL); spin_lock(>t->guptasklock); diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 new file mode 100644 index 0000000000000..8f70124da00f0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -0,0 +1,53 @@ +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # v4.5-rc4-71-g1e9877902dc7 + dnl # mm/gup: Introduce get_user_pages_remote() + dnl # + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_user_pages_remote],[mm/gup.c], + [ + dnl # + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ + dnl # + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ], [ + dnl # + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 new file mode 100644 index 0000000000000..7f9931fdf453f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -0,0 +1,30 @@ +dnl # +dnl # commit v4.8-14095-g768ae309a961 +dnl # mm: replace get_user_pages() write/force parameters with gup_flags +dnl # +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_GUP_FLAGS, 1, + [get_user_pages() wants gup_flags parameter]) + ], [ + dnl # + dnl # commit v4.6-rc2-1-gc12d2da56d0e + dnl # mm/gup: Remove the macro overload API migration helpers + dnl # from the get_user*() APIs + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, 0, NULL, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, + [get_user_pages() wants 6 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 87d66fc6faac2..a9fd40d5f903b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,6 +38,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM AC_AMDGPU_INVALIDATE_RANGE_START + AC_AMDGPU_GET_USER_PAGES_REMOTE + AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 055945c8728ef..3fc317a922a8d 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -5,4 +5,49 @@ #include #include +#ifdef get_user_pages_remote +#undef get_user_pages_remote +#endif +#ifdef get_user_pages +#undef get_user_pages +#endif + +static inline +long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, + unsigned long start, unsigned long nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas, int *locked) +{ +#if defined(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT) + return get_user_pages_remote(mm, start, nr_pages, gup_flags, pages, vmas, locked); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_LOCKED) + return get_user_pages_remote(tsk, mm, start, nr_pages, gup_flags, pages, vmas, locked); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS) + return get_user_pages_remote(tsk, mm, start, nr_pages, gup_flags, pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED) + return get_user_pages_remote(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#else + return get_user_pages(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#endif +} + +#ifndef HAVE_GET_USER_PAGES_GUP_FLAGS +static inline +long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas) +{ +#if defined(HAVE_GET_USER_PAGES_6ARGS) + return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#else + return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#endif +} +#define get_user_pages _kcl_get_user_pages +#endif /* HAVE_GET_USER_PAGES_GUP_FLAGS */ + #endif From 94d2e7fa7ab26b37a12c8487563dd3456ef9b448 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 18 Apr 2020 19:46:03 +0800 Subject: [PATCH 0526/2070] drm/amdkcl: workaroud for shared address space with dma bufs Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++++- include/kcl/backport/kcl_drm_backport.h | 8 ++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 634b23c033304..9adb448c4f9df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -580,10 +580,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, buf = drm_gem_prime_export(dev, gobj, flags); #endif + if (!IS_ERR(buf)) { +#ifdef AMDKCL_DMA_BUF_SHARE_ADDR_SPACE + buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; +#endif #if defined(AMDKCL_AMDGPU_DMABUF_OPS) - if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; #endif + } return buf; } diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 84ca7b867d62d..668fa168e20bd 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -14,4 +14,12 @@ #define AMDKCL_AMDGPU_DMABUF_OPS #endif +/* + * commit v5.4-rc4-1120-gb3fac52c5193 + * drm: share address space for dma bufs + */ +#if DRM_VERSION_CODE < DRM_VERSION(5, 5, 0) +#define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE +#endif + #endif/*AMDKCL_DRM_BACKPORT_H*/ From 12c7baa7272d1d67b3f8871b79ccd7008a47df90 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 16:50:24 +0800 Subject: [PATCH 0527/2070] drm/amdkcl: fix pr_fmt() macro is redefined warning Signed-off-by: Adam Yang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/ttm/ttm_agp_backend.c | 3 +++ drivers/gpu/drm/ttm/ttm_bo.c | 3 +++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 +++ drivers/gpu/drm/ttm/ttm_tt.c | 3 +++ 4 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c index fca0a1a3c6fd3..dd86a462b2c2a 100644 --- a/drivers/gpu/drm/ttm/ttm_agp_backend.c +++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c @@ -30,6 +30,9 @@ * Keith Packard. */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 60d07b75e74ac..8f033e4687923 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 5671add1ffd8a..ed2724232dcef 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index b523f50f73e94..1f7cd5e0e3970 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include From be6fd70c208c337e781e505c317b77971d2d8e36 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Fri, 28 Jun 2019 15:41:36 -0400 Subject: [PATCH 0528/2070] drm/amdkcl: check whether pgprot_decrypted is available Change-Id: I55f9dd3b5b7bf756dd48f74810028c67855bec02 Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index ed2724232dcef..35c5c94f997fa 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -258,8 +258,10 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, return VM_FAULT_SIGBUS; } } else { +#ifdef pgprot_decrypted /* Iomem should not be marked encrypted */ prot = pgprot_decrypted(prot); +#endif } /* From 5572c72cca3a6a66ce6f2889835be365d6d33c95 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 8 Sep 2020 12:45:50 +0800 Subject: [PATCH 0529/2070] drm/amdkcl: use wait_queue_head_t for backward compatibility Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 79bfd1d1871ac..5696dcb7f3be4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,7 +25,6 @@ /* * Debugfs */ - #if defined(CONFIG_DEBUG_FS) #if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) void amdgpu_debugfs_cleanup(struct drm_minor *minor); From bf5818e3a8088c949bd2c498bf3c6ac7895c3ba1 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 9 Aug 2019 14:29:29 +0800 Subject: [PATCH 0530/2070] drm/amdkcl: Test whether amd_iommu_pc_supported is available (v2) amd_iommu_pc_xxx introduced by kernel v3.11-rc1~144^2~20 v2: fix typo and correct header file included Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amd/autoconf: fix missing HAVE_AMD_IOMMU_PC_SUPPORTED Signed-off-by: Flora Cui Reviewed-by: Jack Gui drm/amd/autoconf: fix missing HAVE_AMD_IOMMU_PC_SUPPORTED this break rhel7.6 Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amd/autoconf: check CONFIG_AMD_IOMMU enabled for amd_iommu_pc_* or else the symbols are missing. This is for in-tree build. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: Fix kfd_iommu dkms install error Issue introduced by commit: 4b38b7a521e3aa401f986483722154b3ba701538 Fix RHEL7.6 with 3.10 kernel kfd_iommu dkms install error some legacy kcl path miss replaced with autoconf macro Signed-off-by: Chengming Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: fix test for amd_iommu_pc_xxx Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 25 ++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 +++ drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 41 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 7db7588b2cee1..2f99b4a143d84 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -115,7 +115,9 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; struct kfd_iolink_properties *p2plink; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; +#endif list_del(&dev->list); @@ -147,12 +149,14 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(p2plink); } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); list_del(&perf->list); kfree(perf); } +#endif kfree(dev); } @@ -189,7 +193,9 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); INIT_LIST_HEAD(&dev->p2p_link_props); +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED INIT_LIST_HEAD(&dev->perf_props); +#endif list_add_tail(&dev->list, device_list); @@ -383,6 +389,7 @@ static const struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /****** Sysfs of Performance Counters ******/ struct kfd_perf_attr { @@ -416,6 +423,7 @@ static struct kfd_perf_attr perf_attr_iommu[] = { KFD_PERF_DESC(counter_ids, 0), }; /****************************************/ +#endif static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) @@ -585,7 +593,9 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; +#endif if (dev->kobj_p2plink) { list_for_each_entry(p2plink, &dev->p2p_link_props, list) @@ -651,6 +661,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED if (dev->kobj_perf) { list_for_each_entry(perf, &dev->perf_props, list) { kfree(perf->attr_group); @@ -660,6 +671,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) kobject_put(dev->kobj_perf); dev->kobj_perf = NULL; } +#endif if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); @@ -678,10 +690,13 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; - int ret; - uint32_t i, num_attrs; + uint32_t num_attrs; struct attribute **attrs; +#endif + int ret; + uint32_t i; if (WARN_ON(dev->kobj_node)) return -EEXIST; @@ -716,9 +731,11 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_p2plink) return -ENOMEM; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; +#endif /* * Creating sysfs files for node properties @@ -837,6 +854,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -862,6 +880,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; } +#endif return 0; } @@ -1084,8 +1103,10 @@ int kfd_topology_init(void) goto err; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED kdev = list_first_entry(&temp_topology_device_list, struct kfd_topology_device, list); +#endif down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 129b447fcf84d..a5e07857299e1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -135,12 +135,14 @@ struct kfd_iolink_properties { struct attribute attr; }; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties { struct list_head list; char block_name[16]; uint32_t max_concurrent; struct attribute_group *attr_group; }; +#endif struct kfd_topology_device { struct list_head list; @@ -151,14 +153,18 @@ struct kfd_topology_device { struct list_head cache_props; struct list_head io_link_props; struct list_head p2p_link_props; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct list_head perf_props; +#endif struct kfd_node *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; struct kobject *kobj_p2plink; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kobject *kobj_perf; +#endif struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5c604c53ed971..3c27c1d6c67b3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -4,6 +4,12 @@ /* *FLAGS_.o support to take the path relative to $(obj) */ #define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 +/* amd_iommu_pc_get_max_banks() declared */ +#define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 + +/* amd_iommu_pc_get_max_banks() arg is unsigned int */ +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ + /* Define to 1 if you have the header file. */ #define HAVE_ASM_FPU_API_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 new file mode 100644 index 0000000000000..67cbbec8cac3e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -0,0 +1,41 @@ +dnl # +dnl # v5.12-rc3-5-gfc1b6620501f iommu/amd: Move a few prototypes to include/linux/amd-iommu.h +dnl # v5.12-rc3-4-gb29a1fc7595a iommu/amd: Remove a few unused exports +dnl # v4.11-rc4-171-gf5863a00e73c x86/events/amd/iommu.c: Modify functions to query max banks and counters +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + amd_iommu_pc_get_max_banks(0); + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, + [amd_iommu_pc_get_max_banks() declared]) + ], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_amd_iommu], + [drivers/iommu/amd/init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, + [amd_iommu_pc_get_max_banks() arg is unsigned int]) + ]) + ]) +]) + +dnl # +dnl # commit v3.10-rc3-89-g30861ddc9cca +dnl # perf/x86/amd: Add IOMMU Performance Counter resource management +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + #ifndef CONFIG_AMD_IOMMU + #error CONFIG_AMD_IOMMU not enabled + #endif + ], [amd_iommu_pc_supported], [drivers/iommu/amd/init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_SUPPORTED, 1, + [amd_iommu_pc_supported() is available]) + AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a9fd40d5f903b..33f7f8c2b36c8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -41,6 +41,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES_REMOTE AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF + AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From 086ddedb3e71f04342cb53626f5b01c8ed6772ad Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 15:53:10 +0800 Subject: [PATCH 0531/2070] drm/amdkcl: fix bridge_pm_usable v2: drm/amdkcl: add AMDKCL_PCIE_BRIDGE_PM_USABLE to be friendly for hybrid branch maintainer Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Jack Gui --- .../gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 17 +++++++++++++++++ include/kcl/backport/kcl_pci_backport.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index 3893e6fc2f037..3353c78a258aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -44,7 +44,9 @@ struct amdgpu_atpx { static struct amdgpu_atpx_priv { bool atpx_detected; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool bridge_pm_usable; +#endif unsigned int quirks; /* handle for device - and atpx */ acpi_handle dhandle; @@ -221,11 +223,18 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) atpx->is_hybrid = false; } else { pr_notice("ATPX Hybrid Graphics\n"); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE /* * Disable legacy PM methods only when pcie port PM is usable, * otherwise the device might fail to power off or power on. */ atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable; +#else + /* + * This is a temporary hack for the kernel doesn't support D3. + */ + atpx->functions.power_cntl = true; +#endif atpx->is_hybrid = true; } } @@ -604,16 +613,20 @@ static bool amdgpu_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool d3_supported = false; struct pci_dev *parent_pdev; +#endif while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -622,8 +635,10 @@ static bool amdgpu_atpx_detect(void) has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -632,7 +647,9 @@ static bool amdgpu_atpx_detect(void) pr_info("vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE amdgpu_atpx_priv.bridge_pm_usable = d3_supported; +#endif amdgpu_atpx_init(); return true; } diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index cc2af255e21b5..29bdd6c628b28 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -9,4 +9,8 @@ #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) #define pcie_get_speed_cap _kcl_pcie_get_speed_cap #endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) +#define AMDKCL_PCIE_BRIDGE_PM_USABLE +#endif #endif From 870a35d161a8fc08c9a2c84542c558f4b07d724d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 10:07:49 +0800 Subject: [PATCH 0532/2070] drm/amdkcl: add AMDKCL_ENABLE_RESIZE_FB_BAR for resize BAR enable This is a squash of: drm/amdkcl: move AMDKCL_ENABLE_RESIZE_FB_BAR to kcl_pci part no actual change. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui drm/amdkcl: rework pci resize dependency. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui drm/amdkcl: move pci resize macro to kcl_pci.h Signed-off-by: Flora Cui Signed-off-by: Flora Cui Acked-by: Feifei Xu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ include/kcl/backport/kcl_pci_backport.h | 1 + include/kcl/kcl_pci.h | 10 ++++++++++ 4 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d10b57fb43618..b19372bcca01c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1533,7 +1533,14 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, u64 num_vis_bytes); +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); +#else +static inline int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) +{ + return 0; +} +#endif void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4977c17a41659..7e9f901677de5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1799,6 +1799,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) spin_unlock_irqrestore(&adev->wb.lock, flags); } +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR /** * amdgpu_device_resize_fb_bar - try to resize FB BAR * @@ -1894,6 +1895,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) return 0; } +#endif /* * GPU helpers function. diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 29bdd6c628b28..21799422a6abd 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -13,4 +13,5 @@ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) #define AMDKCL_PCIE_BRIDGE_PM_USABLE #endif + #endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 9b5f1bf8605e2..69781073d7116 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -173,4 +173,14 @@ static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) #endif } +/* + * v4.18-rc1-3-gb1277a226d8c PCI: Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling + * v4.18-rc1-2-gd3252ace0bc6 PCI: Restore resized BAR state on resume + * v4.14-rc3-3-g8bb705e3e79d PCI: Add pci_resize_resource() for resizing BARs + * v4.14-rc3-2-g276b738deb5b PCI: Add resizable BAR infrastructure + */ +#ifdef PCI_REBAR_CTRL_BAR_SHIFT +#define AMDKCL_ENABLE_RESIZE_FB_BAR +#endif /* PCI_REBAR_CTRL_BAR_SHIFT */ + #endif /* AMDKCL_PCI_H */ From 464fabe390b26c0c40325c69d69463e82a362e89 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Mon, 1 Jun 2020 15:23:39 +0800 Subject: [PATCH 0533/2070] drm/amdkcl: test for RATELIMIT_MSG_ON_RELEASE The macro RATELIMIT_MSG_ON_RELEASE is introduced by the patch: 6b1d174b0c27 ratelimit: extend to print suppressed messages on release. Drop the RATELIMIT_MSG_ON_RELEASE related code if RATELIMIT_MSG_ON_RELEASE is not defined. The only side effect is that some warning messages on ratelimit release will be left over. This kcl patch is caused by patch: drm/amdgpu: added a sysfs interface for thermal throttling related V4 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7e9f901677de5..a25694f4e9ce5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4515,7 +4515,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, */ ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); +#ifdef RATELIMIT_MSG_ON_RELEASE ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); +#endif /* Registers mapping */ /* TODO: block userspace mapping of io register */ From 786fc60b6a2091de0609dc94949fed241038dff0 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 15 Aug 2019 16:11:59 +0800 Subject: [PATCH 0534/2070] drm/amdkcl: check whether DEFINE_SRCU is available (v2) DEFINE_SRCU introduced by kernel v3.8-rc1~173^2^2~4^4~1 v2: replace autoconf test with macro name check Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 9 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 +++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 2434619cddc1c..ee7d72124e4c6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -26,6 +26,11 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" +#ifndef DEFINE_SRCU +void kfd_init_processes_srcu(void); +void kfd_cleanup_processes_srcu(void); +#endif + static int kfd_init(void) { int err; @@ -70,6 +75,10 @@ static int kfd_init(void) kfd_debugfs_init(); +#ifndef DEFINE_SRCU + kfd_init_processes_srcu(); +#endif + return 0; err_create_wq: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 766a6c0c4528b..75a2b15995077 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -53,7 +53,20 @@ struct mm_struct; DEFINE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); DEFINE_MUTEX(kfd_processes_mutex); +#ifndef DEFINE_SRCU +struct srcu_struct kfd_processes_srcu; +void kfd_init_processes_srcu(void) +{ + init_srcu_struct(&kfd_processes_srcu); +} + +void kfd_cleanup_processes_srcu(void) +{ + cleanup_srcu_struct(&kfd_processes_srcu); +} +#else DEFINE_SRCU(kfd_processes_srcu); +#endif /* For process termination handling */ static struct workqueue_struct *kfd_process_wq; From 4a61cb5056f2bc7f4787b997670c4b220d944ee6 Mon Sep 17 00:00:00 2001 From: changzhu Date: Sun, 18 Aug 2019 21:38:39 +0800 Subject: [PATCH 0535/2070] drm/amdkcl: Test whether DW_I2S_QUIRK_16BIT_IDX_OVERRIDE is available [Why] DW_I2S_QUIRK_16BIT_IDX_OVERRIDE is not defined until patch: ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver So there will be build when it's not defined. [How] Define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE if it's not defined. Change-Id: I92c4695c24cb7fd7aed80659a53ac57ca8064cef Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 381ef205b0dfb..80e0798ed8ec3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -87,9 +87,12 @@ #define ACP_TIMEOUT_LOOP 0x000000FF #define ACP_DEVS 4 #define ACP_SRC_ID 162 - static unsigned long acp_machine_id; +#ifndef DW_I2S_QUIRK_16BIT_IDX_OVERRIDE +#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) +#endif + enum { ACP_TILE_P1 = 0, ACP_TILE_P2, From baf908a8d99b274cc45274cbbbeaf326d797d266 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Tue, 25 Aug 2020 12:24:13 +0800 Subject: [PATCH 0536/2070] drm/amdkcl: test whether down_read_killable is available introduced by v4.14-rc4-65-g76f8507f7a64 This patch is caused by 'drm/amdgpu: change reset lock from mutex to rw_semaphore' v2:change reset_sem to reset_domain->sem, it's caused by "drm/amdgpu: Move reset sem into reset_domain" Signed-off-by: Yang Xiong Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index c582ed0e4e1fa..5362a871dd5b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1930,9 +1930,13 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) return -ENOMEM; /* Avoid accidently unparking the sched thread during GPU reset */ +#ifdef HAVE_DOWN_READ_KILLABLE r = down_read_killable(&adev->reset_domain->sem); if (r) goto pro_end; +#else + down_read(&adev->reset_domain->sem); +#endif /* stop the scheduler */ drm_sched_wqueue_stop(&ring->sched); diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 new file mode 100644 index 0000000000000..6de71b3c0a40d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -0,0 +1,14 @@ +#dnl +#dnl commit v4.14-rc4-65-g76f8507f7a64 +#dnl locking/rwsem: Add down_read_killable() +#dnl +AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [down_read_killable], + [kernel/locking/rwsem.c], + [AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + [down_read_killable() is available])] + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 33f7f8c2b36c8..4f472fdd0829c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,6 +42,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From 42918e54d88df8759fcc5d4b59712214019a4e30 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 15 Oct 2020 14:01:05 +0800 Subject: [PATCH 0537/2070] drm/amdkcl: include kcl_mn with CONFIG_MMU_NOTIFIER enabled Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4be64eea1ec80..1ba32c43ad0b6 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,6 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o +amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) From fee99494bd4a5db12f7acf88bd5d1d10ddd145d1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 16 Nov 2020 10:56:56 +0800 Subject: [PATCH 0538/2070] drm/amdkcl: rename kcl_connector.c to kcl_drm_connector.c Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/{kcl_connector.c => kcl_drm_connector.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/gpu/drm/amd/amdkcl/{kcl_connector.c => kcl_drm_connector.c} (100%) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 1ba32c43ad0b6..8e0db6aceb191 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ + kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c similarity index 100% rename from drivers/gpu/drm/amd/amdkcl/kcl_connector.c rename to drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c From cd1876878bca5ca9fc1c2b611476182081f5dde4 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 25 Dec 2020 16:52:50 +0800 Subject: [PATCH 0539/2070] drm/amdkcl: dummy the dp subconnector property This is caused by "utilize subconnector property for DP through atombios" and "utilize subconnector property for DP through DisplayManager" v5.8-rc2-673-g65bf2cf95d3a and v5.8-rc2-673-g65bf2cf95d3a Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 8 ++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- .../gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 16 ++++++++++++++++ 5 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index ff900e261cb43..a467ebb08a8f3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -12,3 +12,11 @@ int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, } EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); #endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +amdkcl_dummy_symbol(drm_connector_attach_dp_subconnector_property, void, return, + struct drm_connector *connector) +amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, + struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]) +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1c3d2bcec58fe..4a4d8e53f4014 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -211,10 +211,11 @@ static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) if (aconnector->dc_sink) subconnector = get_subconnector_type(link); - +#ifdef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY drm_object_property_set_value(&connector->base, connector->dev->mode_config.dp_subconnector_property, subconnector); +#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 new file mode 100644 index 0000000000000..527068f2403f8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.8-rc2-671-ge5b92773287c drm: report dp downstream port type as a subconnector property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SUBCONNECTOR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->dp_subconnector_property = NULL; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY, 1, + [drm_mode_config->dp_subconnector_property is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4f472fdd0829c..fade578249fc4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -95,6 +95,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 1da6773c7ee4b..76362de0c45ed 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -79,4 +79,20 @@ int drm_connector_init_with_ddc(struct drm_device *dev, } #endif +#ifndef DP_MAX_DOWNSTREAM_PORTS +#define DP_MAX_DOWNSTREAM_PORTS 0x10 +#endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +void drm_connector_attach_dp_subconnector_property(struct drm_connector *connector); +void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]); + +#define DRM_MODE_SUBCONNECTOR_VGA 1 +#define DRM_MODE_SUBCONNECTOR_DisplayPort 10 +#define DRM_MODE_SUBCONNECTOR_HDMIA 11 +#define DRM_MODE_SUBCONNECTOR_Native 15 +#define DRM_MODE_SUBCONNECTOR_Wireless 18 +#endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ + #endif /* AMDKCL_DRM_CONNECTOR_H */ From a52b808734062225fe0be6f1ebdaed59571aed19 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 11:52:01 +0800 Subject: [PATCH 0540/2070] drm/amdkcl: fake hexint support for module_param Change-Id: Ic6b3fd5e2ca1e6e645c658924cc051b6119297b6 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1d068ea4dab5c..c32386c08a52f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -50,9 +50,10 @@ #include #include #include -#include "kcl/kcl_amdgpu_ttm.h" +#include #include #include +#include "kcl/kcl_amdgpu_ttm.h" #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" From 79c26099ca3b23296aa434678ec1a48aec3be5ca Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:54:35 +0800 Subject: [PATCH 0541/2070] drm/amdkcl: add kcl/kcl_dma-buf-map.h Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_dma-buf-map.h | 141 ++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 include/kcl/kcl_dma-buf-map.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c32386c08a52f..6eeb49670202f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 9500725e818f5..9c28eb7a4f6c4 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h new file mode 100644 index 0000000000000..5bcaad09cabd8 --- /dev/null +++ b/include/kcl/kcl_dma-buf-map.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer to dma-buf-mapped memory, plus helpers. + * Copied from include/kcl/dma-buf-map.h + */ + +#ifndef _KCL_KCL__DMA_BUF_MAP_H__H__ +#define _KCL_KCL__DMA_BUF_MAP_H__H__ + +#include + +#ifndef HAVE_LINUX_DMA_BUF_MAP_H +#include + +/** + * struct dma_buf_map - Pointer to vmap'ed dma-buf memory. + * @vaddr_iomem: The buffer's address if in I/O memory + * @vaddr: The buffer's address if in system memory + * @is_iomem: True if the dma-buf memory is located in I/O + * memory, or false otherwise. + */ +struct dma_buf_map { + union { + void __iomem *vaddr_iomem; + void *vaddr; + }; + bool is_iomem; +}; + +/** + * DMA_BUF_MAP_INIT_VADDR - Initializes struct dma_buf_map to an address in system memory + * @vaddr: A system-memory address + */ +#define DMA_BUF_MAP_INIT_VADDR(vaddr_) \ + { \ + .vaddr = (vaddr_), \ + .is_iomem = false, \ + } + +/** + * dma_buf_map_set_vaddr - Sets a dma-buf mapping structure to an address in system memory + * @map: The dma-buf mapping structure + * @vaddr: A system-memory address + * + * Sets the address and clears the I/O-memory flag. + */ +static inline void dma_buf_map_set_vaddr(struct dma_buf_map *map, void *vaddr) +{ + map->vaddr = vaddr; + map->is_iomem = false; +} + +/** + * dma_buf_map_set_vaddr_iomem - Sets a dma-buf mapping structure to an address in I/O memory + * @map: The dma-buf mapping structure + * @vaddr_iomem: An I/O-memory address + * + * Sets the address and the I/O-memory flag. + */ +static inline void dma_buf_map_set_vaddr_iomem(struct dma_buf_map *map, + void __iomem *vaddr_iomem) +{ + map->vaddr_iomem = vaddr_iomem; + map->is_iomem = true; +} + + +/** + * dma_buf_map_is_equal - Compares two dma-buf mapping structures for equality + * @lhs: The dma-buf mapping structure + * @rhs: A dma-buf mapping structure to compare with + * + * Two dma-buf mapping structures are equal if they both refer to the same type of memory + * and to the same address within that memory. + * + * Returns: + * True is both structures are equal, or false otherwise. + */ +static inline bool dma_buf_map_is_equal(const struct dma_buf_map *lhs, + const struct dma_buf_map *rhs) +{ + if (lhs->is_iomem != rhs->is_iomem) + return false; + else if (lhs->is_iomem) + return lhs->vaddr_iomem == rhs->vaddr_iomem; + else + return lhs->vaddr == rhs->vaddr; +} + +/** + * dma_buf_map_is_null - Tests for a dma-buf mapping to be NULL + * @map: The dma-buf mapping structure + * + * Depending on the state of struct dma_buf_map.is_iomem, tests if the + * mapping is NULL. + * + * Returns: + * True if the mapping is NULL, or false otherwise. + */ +static inline bool dma_buf_map_is_null(const struct dma_buf_map *map) +{ + if (map->is_iomem) + return !map->vaddr_iomem; + return !map->vaddr; +} + +/** + * dma_buf_map_is_set - Tests is the dma-buf mapping has been set + * @map: The dma-buf mapping structure + * + * Depending on the state of struct dma_buf_map.is_iomem, tests if the + * mapping has been set. + * + * Returns: + * True if the mapping is been set, or false otherwise. + */ +static inline bool dma_buf_map_is_set(const struct dma_buf_map *map) +{ + return !dma_buf_map_is_null(map); +} + +/** + * dma_buf_map_clear - Clears a dma-buf mapping structure + * @map: The dma-buf mapping structure + * + * Clears all fields to zero; including struct dma_buf_map.is_iomem. So + * mapping structures that were set to point to I/O memory are reset for + * system memory. Pointers are cleared to NULL. This is the default. + */ +static inline void dma_buf_map_clear(struct dma_buf_map *map) +{ + if (map->is_iomem) { + map->vaddr_iomem = NULL; + map->is_iomem = false; + } else { + map->vaddr = NULL; + } +} +#endif /* HAVE_LINUX_DMA_BUF_MAP_H */ + +#endif From c0e6b82e31b558e09586a6b85ddbf8cf5622e56e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 11:05:33 +0800 Subject: [PATCH 0542/2070] drm/amdkcl: Test whether drm_memcpy_from_wc() is available This is caused by 053c57696cb9 "drm/ttm: Use drm_memcpy_from_wc for TTM bo moves" v5.13-rc3-862-g053c57696cb9 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 | 16 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 19 ++++++++++ include/kcl/kcl_dma-buf-map.h | 35 +++++++++++++++++++ 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 new file mode 100644 index 0000000000000..491ada31c112a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b7e32bef4ae5f9149276203564b7911fac466588 +dnl # drm: Add a prefetching memcpy_from_wc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fade578249fc4..d568326d43127 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -96,6 +96,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 3abbe0d90d312..3bd5c663501a8 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -117,7 +117,26 @@ void ttm_move_memcpy(bool clear, dst_ops->map_local(dst_iter, &dst_map, i); src_ops->map_local(src_iter, &src_map, i); +#ifdef HAVE_DRM_MEMCPY_FROM_WC drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE); +#else + if (!src_map.is_iomem && !dst_map.is_iomem) { + memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE); + } else if (!src_map.is_iomem) { + dma_buf_map_memcpy_to(&dst_map, src_map.vaddr, + PAGE_SIZE); + } else if (!dst_map.is_iomem) { + memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem, + PAGE_SIZE); + } else { + int j; + u32 __iomem *src = src_map.vaddr_iomem; + u32 __iomem *dst = dst_map.vaddr_iomem; + + for (j = 0; j < (PAGE_SIZE / sizeof(u32)); ++j) + iowrite32(ioread32(src++), dst++); + } +#endif if (src_ops->unmap_local) src_ops->unmap_local(src_iter, &src_map); diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h index 5bcaad09cabd8..4ce925f647ec5 100644 --- a/include/kcl/kcl_dma-buf-map.h +++ b/include/kcl/kcl_dma-buf-map.h @@ -136,6 +136,41 @@ static inline void dma_buf_map_clear(struct dma_buf_map *map) map->vaddr = NULL; } } + +/** + * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping + * @dst: The dma-buf mapping structure + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a dma-buf mapping. The source buffer is in system + * memory. Depending on the buffer's location, the helper picks the correct + * method of accessing the memory. + */ +static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem, src, len); + else + memcpy(dst->vaddr, src, len); +} + +/** + * dma_buf_map_incr - Increments the address stored in a dma-buf mapping + * @map: The dma-buf mapping structure + * @incr: The number of bytes to increment + * + * Increments the address stored in a dma-buf mapping. Depending on the + * buffer's location, the correct value will be updated. + */ +static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr) +{ + if (map->is_iomem) + map->vaddr_iomem += incr; + else + map->vaddr += incr; +} + #endif /* HAVE_LINUX_DMA_BUF_MAP_H */ #endif From 6cbe59c796a52006edfbd0e0cb6100e1a20d4d2d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 11:27:39 +0800 Subject: [PATCH 0543/2070] drm/amdkcl: Test whether is_cow_mapping() is available This is caused by f91142c62161 "drm/ttm: nuke VM_MIXEDMAP on BO mappings v3" v5.13-rc3-873-gf91142c62161 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 7 +++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 new file mode 100644 index 0000000000000..c0bf84f081f2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit 97a7e4733b9b221d012ae68fcd3b3251febf6341 +dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow +dnl # +AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + is_cow_mapping(VM_SHARED); + ], [ + AC_DEFINE(HAVE_IS_COW_MAPPING, 1, [is_cow_mapping() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d568326d43127..6fe9bbf4adf7e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -97,6 +97,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_MEMCPY_FROM_WC + AC_AMDGPU_IS_COW_MAPPING AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 361811c045789..47e575291a832 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -43,4 +43,11 @@ static inline unsigned long zone_managed_pages(struct zone *zone) } #endif /* HAVE_ZONE_MANAGED_PAGES */ +#ifndef HAVE_IS_COW_MAPPING +static inline bool is_cow_mapping(vm_flags_t flags) +{ + return (flags & (VM_SHARED | VM_MAYWRITE)) == VM_MAYWRITE; +} +#endif /* HAVE_IS_COW_MAPPING */ + #endif /* AMDKCL_MM_H */ From 1144470e6e9c3a974094190268a288ee35673389 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 15:13:38 +0800 Subject: [PATCH 0544/2070] drm/amdkcl: Test whether drm_aperture_* is available This is caused by 6848c291a54f "drm/aperture: Convert drivers to aperture interfaces" v5.12-rc3-331-g6848c291a54f Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 139 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 | 16 ++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +- .../gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 | 16 ++ include/kcl/kcl_drm_aperture.h | 25 ++++ 8 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 create mode 100644 include/kcl/kcl_drm_aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8e0db6aceb191..d405d0ff0e8bf 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ - kcl_acpi_table.o + kcl_acpi_table.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c new file mode 100644 index 0000000000000..b3fa22920b7f2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: MIT + +#ifndef HAVE_DRM_APERTURE +#include +#include +#include +#include +#include +#include + +struct drm_aperture { + struct drm_device *dev; + resource_size_t base; + resource_size_t size; + struct list_head lh; + void (*detach)(struct drm_device *dev); +}; + +static LIST_HEAD(drm_apertures); +static DEFINE_MUTEX(drm_apertures_lock); + +static bool overlap(resource_size_t base1, resource_size_t end1, + resource_size_t base2, resource_size_t end2) +{ + return (base1 < end2) && (end1 > base2); +} + + +static void drm_aperture_detach_drivers(resource_size_t base, resource_size_t size) +{ + resource_size_t end = base + size; + struct list_head *pos, *n; + + mutex_lock(&drm_apertures_lock); + + list_for_each_safe(pos, n, &drm_apertures) { + struct drm_aperture *ap = + container_of(pos, struct drm_aperture, lh); + struct drm_device *dev = ap->dev; + + if (WARN_ON_ONCE(!dev)) + continue; + + if (!overlap(base, end, ap->base, ap->base + ap->size)) + continue; + + ap->dev = NULL; /* detach from device */ + list_del(&ap->lh); + + ap->detach(dev); + } + + mutex_unlock(&drm_apertures_lock); +} + + +/** + * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range + * @base: the aperture's base address in physical memory + * @size: aperture size in bytes + * @primary: also kick vga16fb if present + * @name: requesting driver name + * + * This function removes graphics device drivers which use memory range described by + * @base and @size. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name) +{ +#if IS_REACHABLE(CONFIG_FB) + struct apertures_struct *a; + int ret; + + a = alloc_apertures(1); + if (!a) + return -ENOMEM; + + a->ranges[0].base = base; + a->ranges[0].size = size; + + ret = remove_conflicting_framebuffers(a, name, primary); + kfree(a); + + if (ret) + return ret; +#endif + + drm_aperture_detach_drivers(base, size); + + return 0; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); + +/** + * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices + * @pdev: PCI device + * @name: requesting driver name + * + * This function removes graphics device drivers using memory range configured + * for any of @pdev's memory bars. The function assumes that PCI device with + * shadowed ROM drives a primary display and so kicks out vga16fb. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + resource_size_t base, size; + int bar, ret = 0; + + for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + base = pci_resource_start(pdev, bar); + size = pci_resource_len(pdev, bar); + drm_aperture_detach_drivers(base, size); + } + + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ + +#ifdef HAVE_VGA_REMOVE_VGACON +#if IS_REACHABLE(CONFIG_FB) + ret = remove_conflicting_pci_framebuffers(pdev, name); +#endif + if (ret == 0) + ret = vga_remove_vgacon(pdev); +#endif + + return ret; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); + +#endif /* HAVE_DRM_APERTURE */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6eeb49670202f..64b7e2df23d04 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -58,5 +58,6 @@ #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 new file mode 100644 index 0000000000000..532e9149653c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 2916059147ea38f76787d7b38dee883da2e9def2 +dnl # drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_aperture_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE, 1, + [drm_aperture_remove_* is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5db23c22d9fe3..16ebd93fc3ea8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -38,4 +38,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm: add managed resources tied to drm_device dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + + dnl # + dnl # v5.12-rc3-330-g2916059147ea + dnl # drm/aperture: Add infrastructure for aperture ownership + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6fe9bbf4adf7e..bcb38c815f1a4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -98,7 +98,9 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING - + AC_AMDGPU_VGA_REMOVE_VGACON + AC_AMDGPU_DRM_APERTURE + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 new file mode 100644 index 0000000000000..f95a903f3143b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.0-rc1-998-gc6b38fbbde91 +dnl # drm: move i915_kick_out_vgacon to vgaarb +dnl # +AC_DEFUN([AC_AMDGPU_VGA_REMOVE_VGACON], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vga_remove_vgacon(NULL); + ], [ + AC_DEFINE(HAVE_VGA_REMOVE_VGACON, 1, + [vga_remove_vgacon() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h new file mode 100644 index 0000000000000..5c402e251a5d9 --- /dev/null +++ b/include/kcl/kcl_drm_aperture.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_APERTURE_H +#define KCL_KCL_DRM_APERTURE_H + +#ifndef HAVE_DRM_APERTURE + +#include + +/* Copied from uapi/linux/pci_regs.h */ +#ifndef PCI_STD_NUM_BARS +#define PCI_STD_NUM_BARS 6 +#endif + +/* Copied from drm/drm_aperture.h */ +struct drm_device; +struct pci_dev; + +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name); + +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); + +#endif /* HAVE_DRM_APERTURE */ + +#endif From 08e1104de5a3bc2467e30eb9c3d84c05f70cbfea Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 15:43:10 +0800 Subject: [PATCH 0545/2070] drm/amdkcl: Test whether struct pci_driver has field dev_groups This is caused by 35bba8313b95 "drm/amdgpu: Convert driver sysfs attributes to static attributes" v5.13-rc1-237-g35bba8313b95 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6c65672b1853c..0077b3fcb8b6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3242,7 +3242,9 @@ static struct pci_driver amdgpu_kms_pci_driver = { .shutdown = amdgpu_pci_shutdown, .driver.pm = pm_ptr(&amdgpu_pm_ops), .err_handler = &amdgpu_pci_err_handler, +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS .dev_groups = amdgpu_sysfs_groups, +#endif }; static int __init amdgpu_init(void) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bcb38c815f1a4..52ccb4b3cd5ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -100,6 +100,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE + AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 new file mode 100644 index 0000000000000..7a673c73d6b1c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ded13b9cfd595adb478a1e371d2282048bba1df5 +dnl # PCI: Add support for dev_groups to struct pci_driver +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct pci_driver pd; + pd.dev_groups = NULL; + ], [], [], [ + AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) + ]) + ]) +]) From ddeaa8a3573917d2fe51dee6f40f2253288bb4bd Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:38:10 +0800 Subject: [PATCH 0546/2070] drm/amdkcl: add faked pci_rebar_bytes_to_size() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 11 +++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 52ccb4b3cd5ce..a77c96839bbf7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -21,6 +21,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 new file mode 100644 index 0000000000000..01d066282244a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 192f1bf7559e895d51f81c3976c5892c8b1e0601 +dnl # PCI: Add pci_rebar_bytes_to_size() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_rebar_bytes_to_size(0); + ], [ + AC_DEFINE(HAVE_PCI_REBAR_BYTES_TO_SIZE, 1, + [pci_rebar_bytes_to_size() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 69781073d7116..ea08289368a27 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -181,6 +181,17 @@ static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) */ #ifdef PCI_REBAR_CTRL_BAR_SHIFT #define AMDKCL_ENABLE_RESIZE_FB_BAR + +/* Copied from 192f1bf7559e895d51f81c3976c5892c8b1e0601 include/linux/pci.h */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static inline int pci_rebar_bytes_to_size(u64 bytes) +{ + bytes = roundup_pow_of_two(bytes); + + /* Return BAR size as defined in the resizable BAR specification */ + return max(ilog2(bytes), 20) - 20; +} +#endif #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ #endif /* AMDKCL_PCI_H */ From 2026c825cca04f2bf22bd3f4a1928ff5eb9a05db Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:46:01 +0800 Subject: [PATCH 0547/2070] drm/amdkcl: add faked pci_rebar_get_possible_sizes() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 51 ++++++++++++++++++++++++++++ include/kcl/kcl_pci.h | 12 +++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 27734a1d565c3..a49eef473bef2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -269,3 +269,54 @@ void _kcl_pci_remove_measure_file(struct pci_dev *pdev) } EXPORT_SYMBOL(_kcl_pci_remove_measure_file); #endif /* AMDKCL_CREATE_MEASURE_FILE */ + +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static int _kcl_pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; + if (bar_idx == bar) + return pos; + } + + return -ENOENT; +} + +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos = _kcl_pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap &= PCI_REBAR_CAP_SIZES; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x7000) + cap = 0x3f000; + + return cap >> 4; +} +EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); +#endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ +#endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index ea08289368a27..fcaace33f6ee2 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -191,7 +191,19 @@ static inline int pci_rebar_bytes_to_size(u64 bytes) /* Return BAR size as defined in the resizable BAR specification */ return max(ilog2(bytes), 20) - 20; } + +/* + * 907830b0fc9e PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse + * 8fbdbb66f8c1 PCI: Export pci_rebar_get_possible_sizes() + */ +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); +static inline +u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + return _kcl_pci_rebar_get_possible_sizes(pdev, bar); +} #endif + #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ #endif /* AMDKCL_PCI_H */ From 15ee4b23afe6473b9a8416b8920c069ccc8c714b Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 14:15:32 +0800 Subject: [PATCH 0548/2070] drm/amdkcl: fake the drm_prime_sg_to_dma_addr_array This is caused by "drm/prime: split array import functions v4" v5.10-rc3-1140-gc67e62790f5c Signed-off-by: Shiwu Zhang --- drivers/block/umem.c | 1130 ++++++++++ drivers/block/umem.h | 132 ++ drivers/block/xsysace.c | 1273 ++++++++++++ drivers/extcon/extcon-arizona.c | 1816 +++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 11 + .../gpu/drm/amd/dkms/m4/highmem-internal.m4 | 16 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_prime.h | 19 + 9 files changed, 4400 insertions(+), 1 deletion(-) create mode 100644 drivers/block/umem.c create mode 100644 drivers/block/umem.h create mode 100644 drivers/block/xsysace.c create mode 100644 drivers/extcon/extcon-arizona.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 create mode 100644 include/kcl/kcl_drm_prime.h diff --git a/drivers/block/umem.c b/drivers/block/umem.c new file mode 100644 index 0000000000000..664280f23bee1 --- /dev/null +++ b/drivers/block/umem.c @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3 + * + * (C) 2001 San Mehat + * (C) 2001 Johannes Erdfelt + * (C) 2001 NeilBrown + * + * This driver for the Micro Memory PCI Memory Module with Battery Backup + * is Copyright Micro Memory Inc 2001-2002. All rights reserved. + * + * This driver provides a standard block device interface for Micro Memory(tm) + * PCI based RAM boards. + * 10/05/01: Phap Nguyen - Rebuilt the driver + * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning + * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn + * - use stand disk partitioning (so fdisk works). + * 08nov2001:NeilBrown - change driver name from "mm" to "umem" + * - incorporate into main kernel + * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet + * - use spin_lock_bh instead of _irq + * - Never block on make_request. queue + * bh's instead. + * - unregister umem from devfs at mod unload + * - Change version to 2.3 + * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal) + * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA + * 15May2002:NeilBrown - convert to bio for 2.5 + * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect + * - a sequence of writes that cover the card, and + * - set initialised bit then. + */ + +#undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include /* O_ACCMODE */ +#include /* HDIO_GETGEO */ + +#include "umem.h" + +#include +#include + +#define MM_MAXCARDS 4 +#define MM_RAHEAD 2 /* two sectors */ +#define MM_BLKSIZE 1024 /* 1k blocks */ +#define MM_HARDSECT 512 /* 512-byte hardware sectors */ +#define MM_SHIFT 6 /* max 64 partitions on 4 cards */ + +/* + * Version Information + */ + +#define DRIVER_NAME "umem" +#define DRIVER_VERSION "v2.3" +#define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown" +#define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver" + +static int debug; +/* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */ +#define HW_TRACE(x) + +#define DEBUG_LED_ON_TRANSFER 0x01 +#define DEBUG_BATTERY_POLLING 0x02 + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug bitmask"); + +static int pci_read_cmd = 0x0C; /* Read Multiple */ +module_param(pci_read_cmd, int, 0); +MODULE_PARM_DESC(pci_read_cmd, "PCI read command"); + +static int pci_write_cmd = 0x0F; /* Write and Invalidate */ +module_param(pci_write_cmd, int, 0); +MODULE_PARM_DESC(pci_write_cmd, "PCI write command"); + +static int pci_cmds; + +static int major_nr; + +#include +#include + +struct cardinfo { + struct pci_dev *dev; + + unsigned char __iomem *csr_remap; + unsigned int mm_size; /* size in kbytes */ + + unsigned int init_size; /* initial segment, in sectors, + * that we know to + * have been written + */ + struct bio *bio, *currentbio, **biotail; + struct bvec_iter current_iter; + + struct request_queue *queue; + + struct mm_page { + dma_addr_t page_dma; + struct mm_dma_desc *desc; + int cnt, headcnt; + struct bio *bio, **biotail; + struct bvec_iter iter; + } mm_pages[2]; +#define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc)) + + int Active, Ready; + + struct tasklet_struct tasklet; + unsigned int dma_status; + + struct { + int good; + int warned; + unsigned long last_change; + } battery[2]; + + spinlock_t lock; + int check_batteries; + + int flags; +}; + +static struct cardinfo cards[MM_MAXCARDS]; +static struct timer_list battery_timer; + +static int num_cards; + +static struct gendisk *mm_gendisk[MM_MAXCARDS]; + +static void check_batteries(struct cardinfo *card); + +static int get_userbit(struct cardinfo *card, int bit) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + return led & bit; +} + +static int set_userbit(struct cardinfo *card, int bit, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state) + led |= bit; + else + led &= ~bit; + writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL); + + return 0; +} + +/* + * NOTE: For the power LED, use the LED_POWER_* macros since they differ + */ +static void set_led(struct cardinfo *card, int shift, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state == LED_FLIP) + led ^= (1<csr_remap + MEMCTRLCMD_LEDCTRL); + +} + +#ifdef MM_DIAG +static void dump_regs(struct cardinfo *card) +{ + unsigned char *p; + int i, i1; + + p = card->csr_remap; + for (i = 0; i < 8; i++) { + printk(KERN_DEBUG "%p ", p); + + for (i1 = 0; i1 < 16; i1++) + printk("%02x ", *p++); + + printk("\n"); + } +} +#endif + +static void dump_dmastat(struct cardinfo *card, unsigned int dmastat) +{ + dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - "); + if (dmastat & DMASCR_ANY_ERR) + printk(KERN_CONT "ANY_ERR "); + if (dmastat & DMASCR_MBE_ERR) + printk(KERN_CONT "MBE_ERR "); + if (dmastat & DMASCR_PARITY_ERR_REP) + printk(KERN_CONT "PARITY_ERR_REP "); + if (dmastat & DMASCR_PARITY_ERR_DET) + printk(KERN_CONT "PARITY_ERR_DET "); + if (dmastat & DMASCR_SYSTEM_ERR_SIG) + printk(KERN_CONT "SYSTEM_ERR_SIG "); + if (dmastat & DMASCR_TARGET_ABT) + printk(KERN_CONT "TARGET_ABT "); + if (dmastat & DMASCR_MASTER_ABT) + printk(KERN_CONT "MASTER_ABT "); + if (dmastat & DMASCR_CHAIN_COMPLETE) + printk(KERN_CONT "CHAIN_COMPLETE "); + if (dmastat & DMASCR_DMA_COMPLETE) + printk(KERN_CONT "DMA_COMPLETE "); + printk("\n"); +} + +/* + * Theory of request handling + * + * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME + * We have two pages of mm_dma_desc, holding about 64 descriptors + * each. These are allocated at init time. + * One page is "Ready" and is either full, or can have request added. + * The other page might be "Active", which DMA is happening on it. + * + * Whenever IO on the active page completes, the Ready page is activated + * and the ex-Active page is clean out and made Ready. + * Otherwise the Ready page is only activated when it becomes full. + * + * If a request arrives while both pages a full, it is queued, and b_rdev is + * overloaded to record whether it was a read or a write. + * + * The interrupt handler only polls the device to clear the interrupt. + * The processing of the result is done in a tasklet. + */ + +static void mm_start_io(struct cardinfo *card) +{ + /* we have the lock, we know there is + * no IO active, and we know that card->Active + * is set + */ + struct mm_dma_desc *desc; + struct mm_page *page; + int offset; + + /* make the last descriptor end the chain */ + page = &card->mm_pages[card->Active]; + pr_debug("start_io: %d %d->%d\n", + card->Active, page->headcnt, page->cnt - 1); + desc = &page->desc[page->cnt-1]; + + desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN); + desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN); + desc->sem_control_bits = desc->control_bits; + + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_ON); + + desc = &page->desc[page->headcnt]; + writel(0, card->csr_remap + DMA_PCI_ADDR); + writel(0, card->csr_remap + DMA_PCI_ADDR + 4); + + writel(0, card->csr_remap + DMA_LOCAL_ADDR); + writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4); + + writel(0, card->csr_remap + DMA_TRANSFER_SIZE); + writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4); + + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR); + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4); + + offset = ((char *)desc) - ((char *)page->desc); + writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff), + card->csr_remap + DMA_DESCRIPTOR_ADDR); + /* Force the value to u64 before shifting otherwise >> 32 is undefined C + * and on some ports will do nothing ! */ + writel(cpu_to_le32(((u64)page->page_dma)>>32), + card->csr_remap + DMA_DESCRIPTOR_ADDR + 4); + + /* Go, go, go */ + writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds), + card->csr_remap + DMA_STATUS_CTRL); +} + +static int add_bio(struct cardinfo *card); + +static void activate(struct cardinfo *card) +{ + /* if No page is Active, and Ready is + * not empty, then switch Ready page + * to active and start IO. + * Then add any bh's that are available to Ready + */ + + do { + while (add_bio(card)) + ; + + if (card->Active == -1 && + card->mm_pages[card->Ready].cnt > 0) { + card->Active = card->Ready; + card->Ready = 1-card->Ready; + mm_start_io(card); + } + + } while (card->Active == -1 && add_bio(card)); +} + +static inline void reset_page(struct mm_page *page) +{ + page->cnt = 0; + page->headcnt = 0; + page->bio = NULL; + page->biotail = &page->bio; +} + +/* + * If there is room on Ready page, take + * one bh off list and add it. + * return 1 if there was room, else 0. + */ +static int add_bio(struct cardinfo *card) +{ + struct mm_page *p; + struct mm_dma_desc *desc; + dma_addr_t dma_handle; + int offset; + struct bio *bio; + struct bio_vec vec; + + bio = card->currentbio; + if (!bio && card->bio) { + card->currentbio = card->bio; + card->current_iter = card->bio->bi_iter; + card->bio = card->bio->bi_next; + if (card->bio == NULL) + card->biotail = &card->bio; + card->currentbio->bi_next = NULL; + return 1; + } + if (!bio) + return 0; + + if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE) + return 0; + + vec = bio_iter_iovec(bio, card->current_iter); + + dma_handle = dma_map_page(&card->dev->dev, + vec.bv_page, + vec.bv_offset, + vec.bv_len, + bio_op(bio) == REQ_OP_READ ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + + p = &card->mm_pages[card->Ready]; + desc = &p->desc[p->cnt]; + p->cnt++; + if (p->bio == NULL) + p->iter = card->current_iter; + if ((p->biotail) != &bio->bi_next) { + *(p->biotail) = bio; + p->biotail = &(bio->bi_next); + bio->bi_next = NULL; + } + + desc->data_dma_handle = dma_handle; + + desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle); + desc->local_addr = cpu_to_le64(card->current_iter.bi_sector << 9); + desc->transfer_size = cpu_to_le32(vec.bv_len); + offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc)); + desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset)); + desc->zero1 = desc->zero2 = 0; + offset = (((char *)(desc+1)) - ((char *)p->desc)); + desc->next_desc_addr = cpu_to_le64(p->page_dma+offset); + desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN| + DMASCR_PARITY_INT_EN| + DMASCR_CHAIN_EN | + DMASCR_SEM_EN | + pci_cmds); + if (bio_op(bio) == REQ_OP_WRITE) + desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ); + desc->sem_control_bits = desc->control_bits; + + + bio_advance_iter(bio, &card->current_iter, vec.bv_len); + if (!card->current_iter.bi_size) + card->currentbio = NULL; + + return 1; +} + +static void process_page(unsigned long data) +{ + /* check if any of the requests in the page are DMA_COMPLETE, + * and deal with them appropriately. + * If we find a descriptor without DMA_COMPLETE in the semaphore, then + * dma must have hit an error on that descriptor, so use dma_status + * instead and assume that all following descriptors must be re-tried. + */ + struct mm_page *page; + struct bio *return_bio = NULL; + struct cardinfo *card = (struct cardinfo *)data; + unsigned int dma_status = card->dma_status; + + spin_lock(&card->lock); + if (card->Active < 0) + goto out_unlock; + page = &card->mm_pages[card->Active]; + + while (page->headcnt < page->cnt) { + struct bio *bio = page->bio; + struct mm_dma_desc *desc = &page->desc[page->headcnt]; + int control = le32_to_cpu(desc->sem_control_bits); + int last = 0; + struct bio_vec vec; + + if (!(control & DMASCR_DMA_COMPLETE)) { + control = dma_status; + last = 1; + } + + page->headcnt++; + vec = bio_iter_iovec(bio, page->iter); + bio_advance_iter(bio, &page->iter, vec.bv_len); + + if (!page->iter.bi_size) { + page->bio = bio->bi_next; + if (page->bio) + page->iter = page->bio->bi_iter; + } + + dma_unmap_page(&card->dev->dev, desc->data_dma_handle, + vec.bv_len, + (control & DMASCR_TRANSFER_READ) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (control & DMASCR_HARD_ERROR) { + /* error */ + bio->bi_status = BLK_STS_IOERR; + dev_printk(KERN_WARNING, &card->dev->dev, + "I/O error on sector %d/%d\n", + le32_to_cpu(desc->local_addr)>>9, + le32_to_cpu(desc->transfer_size)); + dump_dmastat(card, control); + } else if (op_is_write(bio_op(bio)) && + le32_to_cpu(desc->local_addr) >> 9 == + card->init_size) { + card->init_size += le32_to_cpu(desc->transfer_size) >> 9; + if (card->init_size >> 1 >= card->mm_size) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory now initialised\n"); + set_userbit(card, MEMORY_INITIALIZED, 1); + } + } + if (bio != page->bio) { + bio->bi_next = return_bio; + return_bio = bio; + } + + if (last) + break; + } + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_OFF); + + if (card->check_batteries) { + card->check_batteries = 0; + check_batteries(card); + } + if (page->headcnt >= page->cnt) { + reset_page(page); + card->Active = -1; + activate(card); + } else { + /* haven't finished with this one yet */ + pr_debug("do some more\n"); + mm_start_io(card); + } + out_unlock: + spin_unlock(&card->lock); + + while (return_bio) { + struct bio *bio = return_bio; + + return_bio = bio->bi_next; + bio->bi_next = NULL; + bio_endio(bio); + } +} + +static void mm_unplug(struct blk_plug_cb *cb, bool from_schedule) +{ + struct cardinfo *card = cb->data; + + spin_lock_irq(&card->lock); + activate(card); + spin_unlock_irq(&card->lock); + kfree(cb); +} + +static int mm_check_plugged(struct cardinfo *card) +{ + return !!blk_check_plugged(mm_unplug, card, sizeof(struct blk_plug_cb)); +} + +static blk_qc_t mm_submit_bio(struct bio *bio) +{ + struct cardinfo *card = bio->bi_bdev->bd_disk->private_data; + + pr_debug("mm_make_request %llu %u\n", + (unsigned long long)bio->bi_iter.bi_sector, + bio->bi_iter.bi_size); + + blk_queue_split(&bio); + + spin_lock_irq(&card->lock); + *card->biotail = bio; + bio->bi_next = NULL; + card->biotail = &bio->bi_next; + if (op_is_sync(bio->bi_opf) || !mm_check_plugged(card)) + activate(card); + spin_unlock_irq(&card->lock); + + return BLK_QC_T_NONE; +} + +static irqreturn_t mm_interrupt(int irq, void *__card) +{ + struct cardinfo *card = (struct cardinfo *) __card; + unsigned int dma_status; + unsigned short cfg_status; + +HW_TRACE(0x30); + + dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL)); + + if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) { + /* interrupt wasn't for me ... */ + return IRQ_NONE; + } + + /* clear COMPLETION interrupts */ + if (card->flags & UM_FLAG_NO_BYTE_STATUS) + writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE), + card->csr_remap + DMA_STATUS_CTRL); + else + writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16, + card->csr_remap + DMA_STATUS_CTRL + 2); + + /* log errors and clear interrupt status */ + if (dma_status & DMASCR_ANY_ERR) { + unsigned int data_log1, data_log2; + unsigned int addr_log1, addr_log2; + unsigned char stat, count, syndrome, check; + + stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS); + + data_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG)); + data_log2 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG + 4)); + addr_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_ADDR_LOG)); + addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4); + + count = readb(card->csr_remap + ERROR_COUNT); + syndrome = readb(card->csr_remap + ERROR_SYNDROME); + check = readb(card->csr_remap + ERROR_CHECK); + + dump_dmastat(card, dma_status); + + if (stat & 0x01) + dev_printk(KERN_ERR, &card->dev->dev, + "Memory access error detected (err count %d)\n", + count); + if (stat & 0x02) + dev_printk(KERN_ERR, &card->dev->dev, + "Multi-bit EDC error\n"); + + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n", + addr_log2, addr_log1, data_log2, data_log1); + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Check 0x%02x, Fault Syndrome 0x%02x\n", + check, syndrome); + + writeb(0, card->csr_remap + ERROR_COUNT); + } + + if (dma_status & DMASCR_PARITY_ERR_REP) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR REPORTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_PARITY_ERR_DET) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR DETECTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_SYSTEM_ERR_SIG) { + dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_TARGET_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_MASTER_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + /* and process the DMA descriptors */ + card->dma_status = dma_status; + tasklet_schedule(&card->tasklet); + +HW_TRACE(0x36); + + return IRQ_HANDLED; +} + +/* + * If both batteries are good, no LED + * If either battery has been warned, solid LED + * If both batteries are bad, flash the LED quickly + * If either battery is bad, flash the LED semi quickly + */ +static void set_fault_to_battery_status(struct cardinfo *card) +{ + if (card->battery[0].good && card->battery[1].good) + set_led(card, LED_FAULT, LED_OFF); + else if (card->battery[0].warned || card->battery[1].warned) + set_led(card, LED_FAULT, LED_ON); + else if (!card->battery[0].good && !card->battery[1].good) + set_led(card, LED_FAULT, LED_FLASH_7_0); + else + set_led(card, LED_FAULT, LED_FLASH_3_5); +} + +static void init_battery_timer(void); + +static int check_battery(struct cardinfo *card, int battery, int status) +{ + if (status != card->battery[battery].good) { + card->battery[battery].good = !card->battery[battery].good; + card->battery[battery].last_change = jiffies; + + if (card->battery[battery].good) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now good\n", battery + 1); + card->battery[battery].warned = 0; + } else + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now FAILED\n", battery + 1); + + return 1; + } else if (!card->battery[battery].good && + !card->battery[battery].warned && + time_after_eq(jiffies, card->battery[battery].last_change + + (HZ * 60 * 60 * 5))) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d still FAILED after 5 hours\n", battery + 1); + card->battery[battery].warned = 1; + + return 1; + } + + return 0; +} + +static void check_batteries(struct cardinfo *card) +{ + /* NOTE: this must *never* be called while the card + * is doing (bus-to-card) DMA, or you will need the + * reset switch + */ + unsigned char status; + int ret1, ret2; + + status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + if (debug & DEBUG_BATTERY_POLLING) + dev_printk(KERN_DEBUG, &card->dev->dev, + "checking battery status, 1 = %s, 2 = %s\n", + (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK", + (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK"); + + ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE)); + ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE)); + + if (ret1 || ret2) + set_fault_to_battery_status(card); +} + +static void check_all_batteries(struct timer_list *unused) +{ + int i; + + for (i = 0; i < num_cards; i++) + if (!(cards[i].flags & UM_FLAG_NO_BATT)) { + struct cardinfo *card = &cards[i]; + spin_lock_bh(&card->lock); + if (card->Active >= 0) + card->check_batteries = 1; + else + check_batteries(card); + spin_unlock_bh(&card->lock); + } + + init_battery_timer(); +} + +static void init_battery_timer(void) +{ + timer_setup(&battery_timer, check_all_batteries, 0); + battery_timer.expires = jiffies + (HZ * 60); + add_timer(&battery_timer); +} + +static void del_battery_timer(void) +{ + del_timer(&battery_timer); +} + +/* + * Note no locks taken out here. In a worst case scenario, we could drop + * a chunk of system memory. But that should never happen, since validation + * happens at open or mount time, when locks are held. + * + * That's crap, since doing that while some partitions are opened + * or mounted will give you really nasty results. + */ +static int mm_revalidate(struct gendisk *disk) +{ + struct cardinfo *card = disk->private_data; + set_capacity(disk, card->mm_size << 1); + return 0; +} + +static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct cardinfo *card = bdev->bd_disk->private_data; + int size = card->mm_size * (1024 / MM_HARDSECT); + + /* + * get geometry: we have to fake one... trim the size to a + * multiple of 2048 (1M): tell we have 32 sectors, 64 heads, + * whatever cylinders. + */ + geo->heads = 64; + geo->sectors = 32; + geo->cylinders = size / (geo->heads * geo->sectors); + return 0; +} + +static const struct block_device_operations mm_fops = { + .owner = THIS_MODULE, + .submit_bio = mm_submit_bio, + .getgeo = mm_getgeo, + .revalidate_disk = mm_revalidate, +}; + +static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + int ret; + struct cardinfo *card = &cards[num_cards]; + unsigned char mem_present; + unsigned char batt_status; + unsigned int saved_bar, data; + unsigned long csr_base; + unsigned long csr_len; + int magic_number; + static int printed_version; + + if (!printed_version++) + printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n"); + + ret = pci_enable_device(dev); + if (ret) + return ret; + + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8); + pci_set_master(dev); + + card->dev = dev; + + csr_base = pci_resource_start(dev, 0); + csr_len = pci_resource_len(dev, 0); + if (!csr_base || !csr_len) + return -ENODEV; + + dev_printk(KERN_INFO, &dev->dev, + "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n"); + + if (dma_set_mask(&dev->dev, DMA_BIT_MASK(64)) && + dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) { + dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n"); + return -ENOMEM; + } + + ret = pci_request_regions(dev, DRIVER_NAME); + if (ret) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to request memory region\n"); + goto failed_req_csr; + } + + card->csr_remap = ioremap(csr_base, csr_len); + if (!card->csr_remap) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to remap memory region\n"); + ret = -ENOMEM; + + goto failed_remap_csr; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "CSR 0x%08lx -> 0x%p (0x%lx)\n", + csr_base, card->csr_remap, csr_len); + + switch (card->dev->device) { + case 0x5415: + card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG; + magic_number = 0x59; + break; + + case 0x5425: + card->flags |= UM_FLAG_NO_BYTE_STATUS; + magic_number = 0x5C; + break; + + case 0x6155: + card->flags |= UM_FLAG_NO_BYTE_STATUS | + UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT; + magic_number = 0x99; + break; + + default: + magic_number = 0x100; + break; + } + + if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) { + dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n"); + ret = -ENOMEM; + goto failed_magic; + } + + card->mm_pages[0].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[0].page_dma, GFP_KERNEL); + card->mm_pages[1].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[1].page_dma, GFP_KERNEL); + if (card->mm_pages[0].desc == NULL || + card->mm_pages[1].desc == NULL) { + dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n"); + ret = -ENOMEM; + goto failed_alloc; + } + reset_page(&card->mm_pages[0]); + reset_page(&card->mm_pages[1]); + card->Ready = 0; /* page 0 is ready */ + card->Active = -1; /* no page is active */ + card->bio = NULL; + card->biotail = &card->bio; + spin_lock_init(&card->lock); + + card->queue = blk_alloc_queue(NUMA_NO_NODE); + if (!card->queue) { + ret = -ENOMEM; + goto failed_alloc; + } + + tasklet_init(&card->tasklet, process_page, (unsigned long)card); + + card->check_batteries = 0; + + mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY); + switch (mem_present) { + case MEM_128_MB: + card->mm_size = 1024 * 128; + break; + case MEM_256_MB: + card->mm_size = 1024 * 256; + break; + case MEM_512_MB: + card->mm_size = 1024 * 512; + break; + case MEM_1_GB: + card->mm_size = 1024 * 1024; + break; + case MEM_2_GB: + card->mm_size = 1024 * 2048; + break; + default: + card->mm_size = 0; + break; + } + + /* Clear the LED's we control */ + set_led(card, LED_REMOVE, LED_OFF); + set_led(card, LED_FAULT, LED_OFF); + + batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + + card->battery[0].good = !(batt_status & BATTERY_1_FAILURE); + card->battery[1].good = !(batt_status & BATTERY_2_FAILURE); + card->battery[0].last_change = card->battery[1].last_change = jiffies; + + if (card->flags & UM_FLAG_NO_BATT) + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB\n", card->mm_size); + else { + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n", + card->mm_size, + batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled", + card->battery[0].good ? "OK" : "FAILURE", + batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled", + card->battery[1].good ? "OK" : "FAILURE"); + + set_fault_to_battery_status(card); + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar); + data = 0xffffffff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar); + data &= 0xfffffff0; + data = ~data; + data += 1; + + if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME, + card)) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to allocate IRQ\n"); + ret = -ENODEV; + goto failed_req_irq; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "Window size %d bytes, IRQ %d\n", data, dev->irq); + + pci_set_drvdata(dev, card); + + if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */ + pci_write_cmd = 0x07; /* then Memory Write command */ + + if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */ + unsigned short cfg_command; + pci_read_config_word(dev, PCI_COMMAND, &cfg_command); + cfg_command |= 0x10; /* Memory Write & Invalidate Enable */ + pci_write_config_word(dev, PCI_COMMAND, cfg_command); + } + pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24); + + num_cards++; + + if (!get_userbit(card, MEMORY_INITIALIZED)) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory NOT initialized. Consider over-writing whole device.\n"); + card->init_size = 0; + } else { + dev_printk(KERN_INFO, &card->dev->dev, + "memory already initialized\n"); + card->init_size = card->mm_size; + } + + /* Enable ECC */ + writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL); + + return 0; + + failed_req_irq: + failed_alloc: + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + failed_magic: + iounmap(card->csr_remap); + failed_remap_csr: + pci_release_regions(dev); + failed_req_csr: + + return ret; +} + +static void mm_pci_remove(struct pci_dev *dev) +{ + struct cardinfo *card = pci_get_drvdata(dev); + + tasklet_kill(&card->tasklet); + free_irq(dev->irq, card); + iounmap(card->csr_remap); + + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + blk_cleanup_queue(card->queue); + + pci_release_regions(dev); + pci_disable_device(dev); +} + +static const struct pci_device_id mm_pci_ids[] = { + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)}, + { + .vendor = 0x8086, + .device = 0xB555, + .subvendor = 0x1332, + .subdevice = 0x5460, + .class = 0x050000, + .class_mask = 0, + }, { /* end: all zeroes */ } +}; + +MODULE_DEVICE_TABLE(pci, mm_pci_ids); + +static struct pci_driver mm_pci_driver = { + .name = DRIVER_NAME, + .id_table = mm_pci_ids, + .probe = mm_pci_probe, + .remove = mm_pci_remove, +}; + +static int __init mm_init(void) +{ + int retval, i; + int err; + + retval = pci_register_driver(&mm_pci_driver); + if (retval) + return -ENOMEM; + + err = major_nr = register_blkdev(0, DRIVER_NAME); + if (err < 0) { + pci_unregister_driver(&mm_pci_driver); + return -EIO; + } + + for (i = 0; i < num_cards; i++) { + mm_gendisk[i] = alloc_disk(1 << MM_SHIFT); + if (!mm_gendisk[i]) + goto out; + } + + for (i = 0; i < num_cards; i++) { + struct gendisk *disk = mm_gendisk[i]; + sprintf(disk->disk_name, "umem%c", 'a'+i); + spin_lock_init(&cards[i].lock); + disk->major = major_nr; + disk->first_minor = i << MM_SHIFT; + disk->fops = &mm_fops; + disk->private_data = &cards[i]; + disk->queue = cards[i].queue; + set_capacity(disk, cards[i].mm_size << 1); + add_disk(disk); + } + + init_battery_timer(); + printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE); +/* printk("mm_init: Done. 10-19-01 9:00\n"); */ + return 0; + +out: + pci_unregister_driver(&mm_pci_driver); + unregister_blkdev(major_nr, DRIVER_NAME); + while (i--) + put_disk(mm_gendisk[i]); + return -ENOMEM; +} + +static void __exit mm_cleanup(void) +{ + int i; + + del_battery_timer(); + + for (i = 0; i < num_cards ; i++) { + del_gendisk(mm_gendisk[i]); + put_disk(mm_gendisk[i]); + } + + pci_unregister_driver(&mm_pci_driver); + + unregister_blkdev(major_nr, DRIVER_NAME); +} + +module_init(mm_init); +module_exit(mm_cleanup); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/block/umem.h b/drivers/block/umem.h new file mode 100644 index 0000000000000..58384978ff054 --- /dev/null +++ b/drivers/block/umem.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file contains defines for the + * Micro Memory MM5415 + * family PCI Memory Module with Battery Backup. + * + * Copyright Micro Memory INC 2001. All rights reserved. + */ + +#ifndef _DRIVERS_BLOCK_MM_H +#define _DRIVERS_BLOCK_MM_H + + +#define IRQ_TIMEOUT (1 * HZ) + +/* CSR register definition */ +#define MEMCTRLSTATUS_MAGIC 0x00 +#define MM_MAGIC_VALUE (unsigned char)0x59 + +#define MEMCTRLSTATUS_BATTERY 0x04 +#define BATTERY_1_DISABLED 0x01 +#define BATTERY_1_FAILURE 0x02 +#define BATTERY_2_DISABLED 0x04 +#define BATTERY_2_FAILURE 0x08 + +#define MEMCTRLSTATUS_MEMORY 0x07 +#define MEM_128_MB 0xfe +#define MEM_256_MB 0xfc +#define MEM_512_MB 0xf8 +#define MEM_1_GB 0xf0 +#define MEM_2_GB 0xe0 + +#define MEMCTRLCMD_LEDCTRL 0x08 +#define LED_REMOVE 2 +#define LED_FAULT 4 +#define LED_POWER 6 +#define LED_FLIP 255 +#define LED_OFF 0x00 +#define LED_ON 0x01 +#define LED_FLASH_3_5 0x02 +#define LED_FLASH_7_0 0x03 +#define LED_POWER_ON 0x00 +#define LED_POWER_OFF 0x01 +#define USER_BIT1 0x01 +#define USER_BIT2 0x02 + +#define MEMORY_INITIALIZED USER_BIT1 + +#define MEMCTRLCMD_ERRCTRL 0x0C +#define EDC_NONE_DEFAULT 0x00 +#define EDC_NONE 0x01 +#define EDC_STORE_READ 0x02 +#define EDC_STORE_CORRECT 0x03 + +#define MEMCTRLCMD_ERRCNT 0x0D +#define MEMCTRLCMD_ERRSTATUS 0x0E + +#define ERROR_DATA_LOG 0x20 +#define ERROR_ADDR_LOG 0x28 +#define ERROR_COUNT 0x3D +#define ERROR_SYNDROME 0x3E +#define ERROR_CHECK 0x3F + +#define DMA_PCI_ADDR 0x40 +#define DMA_LOCAL_ADDR 0x48 +#define DMA_TRANSFER_SIZE 0x50 +#define DMA_DESCRIPTOR_ADDR 0x58 +#define DMA_SEMAPHORE_ADDR 0x60 +#define DMA_STATUS_CTRL 0x68 +#define DMASCR_GO 0x00001 +#define DMASCR_TRANSFER_READ 0x00002 +#define DMASCR_CHAIN_EN 0x00004 +#define DMASCR_SEM_EN 0x00010 +#define DMASCR_DMA_COMP_EN 0x00020 +#define DMASCR_CHAIN_COMP_EN 0x00040 +#define DMASCR_ERR_INT_EN 0x00080 +#define DMASCR_PARITY_INT_EN 0x00100 +#define DMASCR_ANY_ERR 0x00800 +#define DMASCR_MBE_ERR 0x01000 +#define DMASCR_PARITY_ERR_REP 0x02000 +#define DMASCR_PARITY_ERR_DET 0x04000 +#define DMASCR_SYSTEM_ERR_SIG 0x08000 +#define DMASCR_TARGET_ABT 0x10000 +#define DMASCR_MASTER_ABT 0x20000 +#define DMASCR_DMA_COMPLETE 0x40000 +#define DMASCR_CHAIN_COMPLETE 0x80000 + +/* +3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE +READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA +TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE +TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS +(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, +AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING +DMA READ OPERATIONS. +*/ +#define DMASCR_READ 0x60000000 +#define DMASCR_READLINE 0xE0000000 +#define DMASCR_READMULTI 0xC0000000 + + +#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) +#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) + +#define WINDOWMAP_WINNUM 0x7B + +#define DMA_READ_FROM_HOST 0 +#define DMA_WRITE_TO_HOST 1 + +struct mm_dma_desc { + __le64 pci_addr; + __le64 local_addr; + __le32 transfer_size; + u32 zero1; + __le64 next_desc_addr; + __le64 sem_addr; + __le32 control_bits; + u32 zero2; + + dma_addr_t data_dma_handle; + + /* Copy of the bits */ + __le64 sem_control_bits; +} __attribute__((aligned(8))); + +/* bits for card->flags */ +#define UM_FLAG_DMA_IN_REGS 1 +#define UM_FLAG_NO_BYTE_STATUS 2 +#define UM_FLAG_NO_BATTREG 4 +#define UM_FLAG_NO_BATT 8 +#endif diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c new file mode 100644 index 0000000000000..eb8ef65778c35 --- /dev/null +++ b/drivers/block/xsysace.c @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Xilinx SystemACE device driver + * + * Copyright 2007 Secret Lab Technologies Ltd. + */ + +/* + * The SystemACE chip is designed to configure FPGAs by loading an FPGA + * bitstream from a file on a CF card and squirting it into FPGAs connected + * to the SystemACE JTAG chain. It also has the advantage of providing an + * MPU interface which can be used to control the FPGA configuration process + * and to use the attached CF card for general purpose storage. + * + * This driver is a block device driver for the SystemACE. + * + * Initialization: + * The driver registers itself as a platform_device driver at module + * load time. The platform bus will take care of calling the + * ace_probe() method for all SystemACE instances in the system. Any + * number of SystemACE instances are supported. ace_probe() calls + * ace_setup() which initialized all data structures, reads the CF + * id structure and registers the device. + * + * Processing: + * Just about all of the heavy lifting in this driver is performed by + * a Finite State Machine (FSM). The driver needs to wait on a number + * of events; some raised by interrupts, some which need to be polled + * for. Describing all of the behaviour in a FSM seems to be the + * easiest way to keep the complexity low and make it easy to + * understand what the driver is doing. If the block ops or the + * request function need to interact with the hardware, then they + * simply need to flag the request and kick of FSM processing. + * + * The FSM itself is atomic-safe code which can be run from any + * context. The general process flow is: + * 1. obtain the ace->lock spinlock. + * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is + * cleared. + * 3. release the lock. + * + * Individual states do not sleep in any way. If a condition needs to + * be waited for then the state much clear the fsm_continue flag and + * either schedule the FSM to be run again at a later time, or expect + * an interrupt to call the FSM when the desired condition is met. + * + * In normal operation, the FSM is processed at interrupt context + * either when the driver's tasklet is scheduled, or when an irq is + * raised by the hardware. The tasklet can be scheduled at any time. + * The request method in particular schedules the tasklet when a new + * request has been indicated by the block layer. Once started, the + * FSM proceeds as far as it can processing the request until it + * needs on a hardware event. At this point, it must yield execution. + * + * A state has two options when yielding execution: + * 1. ace_fsm_yield() + * - Call if need to poll for event. + * - clears the fsm_continue flag to exit the processing loop + * - reschedules the tasklet to run again as soon as possible + * 2. ace_fsm_yieldirq() + * - Call if an irq is expected from the HW + * - clears the fsm_continue flag to exit the processing loop + * - does not reschedule the tasklet so the FSM will not be processed + * again until an irq is received. + * After calling a yield function, the state must return control back + * to the FSM main loop. + * + * Additionally, the driver maintains a kernel timer which can process + * the FSM. If the FSM gets stalled, typically due to a missed + * interrupt, then the kernel timer will expire and the driver can + * continue where it left off. + * + * To Do: + * - Add FPGA configuration control interface. + * - Request major number from lanana + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_OF) +#include +#include +#include +#endif + +MODULE_AUTHOR("Grant Likely "); +MODULE_DESCRIPTION("Xilinx SystemACE device driver"); +MODULE_LICENSE("GPL"); + +/* SystemACE register definitions */ +#define ACE_BUSMODE (0x00) + +#define ACE_STATUS (0x04) +#define ACE_STATUS_CFGLOCK (0x00000001) +#define ACE_STATUS_MPULOCK (0x00000002) +#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ +#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ +#define ACE_STATUS_CFDETECT (0x00000010) +#define ACE_STATUS_DATABUFRDY (0x00000020) +#define ACE_STATUS_DATABUFMODE (0x00000040) +#define ACE_STATUS_CFGDONE (0x00000080) +#define ACE_STATUS_RDYFORCFCMD (0x00000100) +#define ACE_STATUS_CFGMODEPIN (0x00000200) +#define ACE_STATUS_CFGADDR_MASK (0x0000e000) +#define ACE_STATUS_CFBSY (0x00020000) +#define ACE_STATUS_CFRDY (0x00040000) +#define ACE_STATUS_CFDWF (0x00080000) +#define ACE_STATUS_CFDSC (0x00100000) +#define ACE_STATUS_CFDRQ (0x00200000) +#define ACE_STATUS_CFCORR (0x00400000) +#define ACE_STATUS_CFERR (0x00800000) + +#define ACE_ERROR (0x08) +#define ACE_CFGLBA (0x0c) +#define ACE_MPULBA (0x10) + +#define ACE_SECCNTCMD (0x14) +#define ACE_SECCNTCMD_RESET (0x0100) +#define ACE_SECCNTCMD_IDENTIFY (0x0200) +#define ACE_SECCNTCMD_READ_DATA (0x0300) +#define ACE_SECCNTCMD_WRITE_DATA (0x0400) +#define ACE_SECCNTCMD_ABORT (0x0600) + +#define ACE_VERSION (0x16) +#define ACE_VERSION_REVISION_MASK (0x00FF) +#define ACE_VERSION_MINOR_MASK (0x0F00) +#define ACE_VERSION_MAJOR_MASK (0xF000) + +#define ACE_CTRL (0x18) +#define ACE_CTRL_FORCELOCKREQ (0x0001) +#define ACE_CTRL_LOCKREQ (0x0002) +#define ACE_CTRL_FORCECFGADDR (0x0004) +#define ACE_CTRL_FORCECFGMODE (0x0008) +#define ACE_CTRL_CFGMODE (0x0010) +#define ACE_CTRL_CFGSTART (0x0020) +#define ACE_CTRL_CFGSEL (0x0040) +#define ACE_CTRL_CFGRESET (0x0080) +#define ACE_CTRL_DATABUFRDYIRQ (0x0100) +#define ACE_CTRL_ERRORIRQ (0x0200) +#define ACE_CTRL_CFGDONEIRQ (0x0400) +#define ACE_CTRL_RESETIRQ (0x0800) +#define ACE_CTRL_CFGPROG (0x1000) +#define ACE_CTRL_CFGADDR_MASK (0xe000) + +#define ACE_FATSTAT (0x1c) + +#define ACE_NUM_MINORS 16 +#define ACE_SECTOR_SIZE (512) +#define ACE_FIFO_SIZE (32) +#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) + +#define ACE_BUS_WIDTH_8 0 +#define ACE_BUS_WIDTH_16 1 + +struct ace_reg_ops; + +struct ace_device { + /* driver state data */ + int id; + int media_change; + int users; + struct list_head list; + + /* finite state machine data */ + struct tasklet_struct fsm_tasklet; + uint fsm_task; /* Current activity (ACE_TASK_*) */ + uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ + uint fsm_continue_flag; /* cleared to exit FSM mainloop */ + uint fsm_iter_num; + struct timer_list stall_timer; + + /* Transfer state/result, use for both id and block request */ + struct request *req; /* request being processed */ + void *data_ptr; /* pointer to I/O buffer */ + int data_count; /* number of buffers remaining */ + int data_result; /* Result of transfer; 0 := success */ + + int id_req_count; /* count of id requests */ + int id_result; + struct completion id_completion; /* used when id req finishes */ + int in_irq; + + /* Details of hardware device */ + resource_size_t physaddr; + void __iomem *baseaddr; + int irq; + int bus_width; /* 0 := 8 bit; 1 := 16 bit */ + struct ace_reg_ops *reg_ops; + int lock_count; + + /* Block device data structures */ + spinlock_t lock; + struct device *dev; + struct request_queue *queue; + struct gendisk *gd; + struct blk_mq_tag_set tag_set; + struct list_head rq_list; + + /* Inserted CF card parameters */ + u16 cf_id[ATA_ID_WORDS]; +}; + +static DEFINE_MUTEX(xsysace_mutex); +static int ace_major; + +/* --------------------------------------------------------------------- + * Low level register access + */ + +struct ace_reg_ops { + u16(*in) (struct ace_device * ace, int reg); + void (*out) (struct ace_device * ace, int reg, u16 val); + void (*datain) (struct ace_device * ace); + void (*dataout) (struct ace_device * ace); +}; + +/* 8 Bit bus width */ +static u16 ace_in_8(struct ace_device *ace, int reg) +{ + void __iomem *r = ace->baseaddr + reg; + return in_8(r) | (in_8(r + 1) << 8); +} + +static void ace_out_8(struct ace_device *ace, int reg, u16 val) +{ + void __iomem *r = ace->baseaddr + reg; + out_8(r, val); + out_8(r + 1, val >> 8); +} + +static void ace_datain_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *dst = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + *dst++ = in_8(r++); + ace->data_ptr = dst; +} + +static void ace_dataout_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *src = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + out_8(r++, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_8_ops = { + .in = ace_in_8, + .out = ace_out_8, + .datain = ace_datain_8, + .dataout = ace_dataout_8, +}; + +/* 16 bit big endian bus attachment */ +static u16 ace_in_be16(struct ace_device *ace, int reg) +{ + return in_be16(ace->baseaddr + reg); +} + +static void ace_out_be16(struct ace_device *ace, int reg, u16 val) +{ + out_be16(ace->baseaddr + reg, val); +} + +static void ace_datain_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_le16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_le16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +/* 16 bit little endian bus attachment */ +static u16 ace_in_le16(struct ace_device *ace, int reg) +{ + return in_le16(ace->baseaddr + reg); +} + +static void ace_out_le16(struct ace_device *ace, int reg, u16 val) +{ + out_le16(ace->baseaddr + reg, val); +} + +static void ace_datain_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_be16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_be16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_be16_ops = { + .in = ace_in_be16, + .out = ace_out_be16, + .datain = ace_datain_be16, + .dataout = ace_dataout_be16, +}; + +static struct ace_reg_ops ace_reg_le16_ops = { + .in = ace_in_le16, + .out = ace_out_le16, + .datain = ace_datain_le16, + .dataout = ace_dataout_le16, +}; + +static inline u16 ace_in(struct ace_device *ace, int reg) +{ + return ace->reg_ops->in(ace, reg); +} + +static inline u32 ace_in32(struct ace_device *ace, int reg) +{ + return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); +} + +static inline void ace_out(struct ace_device *ace, int reg, u16 val) +{ + ace->reg_ops->out(ace, reg, val); +} + +static inline void ace_out32(struct ace_device *ace, int reg, u32 val) +{ + ace_out(ace, reg, val); + ace_out(ace, reg + 2, val >> 16); +} + +/* --------------------------------------------------------------------- + * Debug support functions + */ + +#if defined(DEBUG) +static void ace_dump_mem(void *base, int len) +{ + const char *ptr = base; + int i, j; + + for (i = 0; i < len; i += 16) { + printk(KERN_INFO "%.8x:", i); + for (j = 0; j < 16; j++) { + if (!(j % 4)) + printk(" "); + printk("%.2x", ptr[i + j]); + } + printk(" "); + for (j = 0; j < 16; j++) + printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); + printk("\n"); + } +} +#else +static inline void ace_dump_mem(void *base, int len) +{ +} +#endif + +static void ace_dump_regs(struct ace_device *ace) +{ + dev_info(ace->dev, + " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" + " status:%.8x mpu_lba:%.8x busmode:%4x\n" + " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", + ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD), + ace_in(ace, ACE_VERSION), + ace_in32(ace, ACE_STATUS), + ace_in32(ace, ACE_MPULBA), + ace_in(ace, ACE_BUSMODE), + ace_in32(ace, ACE_ERROR), + ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); +} + +static void ace_fix_driveid(u16 *id) +{ +#if defined(__BIG_ENDIAN) + int i; + + /* All half words have wrong byte order; swap the bytes */ + for (i = 0; i < ATA_ID_WORDS; i++, id++) + *id = le16_to_cpu(*id); +#endif +} + +/* --------------------------------------------------------------------- + * Finite State Machine (FSM) implementation + */ + +/* FSM tasks; used to direct state transitions */ +#define ACE_TASK_IDLE 0 +#define ACE_TASK_IDENTIFY 1 +#define ACE_TASK_READ 2 +#define ACE_TASK_WRITE 3 +#define ACE_FSM_NUM_TASKS 4 + +/* FSM state definitions */ +#define ACE_FSM_STATE_IDLE 0 +#define ACE_FSM_STATE_REQ_LOCK 1 +#define ACE_FSM_STATE_WAIT_LOCK 2 +#define ACE_FSM_STATE_WAIT_CFREADY 3 +#define ACE_FSM_STATE_IDENTIFY_PREPARE 4 +#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 +#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 +#define ACE_FSM_STATE_REQ_PREPARE 7 +#define ACE_FSM_STATE_REQ_TRANSFER 8 +#define ACE_FSM_STATE_REQ_COMPLETE 9 +#define ACE_FSM_STATE_ERROR 10 +#define ACE_FSM_NUM_STATES 11 + +/* Set flag to exit FSM loop and reschedule tasklet */ +static inline void ace_fsm_yieldpoll(struct ace_device *ace) +{ + tasklet_schedule(&ace->fsm_tasklet); + ace->fsm_continue_flag = 0; +} + +static inline void ace_fsm_yield(struct ace_device *ace) +{ + dev_dbg(ace->dev, "%s()\n", __func__); + ace_fsm_yieldpoll(ace); +} + +/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ +static inline void ace_fsm_yieldirq(struct ace_device *ace) +{ + dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); + + if (ace->irq > 0) + ace->fsm_continue_flag = 0; + else + ace_fsm_yieldpoll(ace); +} + +static bool ace_has_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + + return !list_empty(&ace->rq_list); +} + +/* Get the next read/write request; ending requests that we don't handle */ +static struct request *ace_get_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + struct request *rq; + + rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist); + if (rq) { + list_del_init(&rq->queuelist); + blk_mq_start_request(rq); + } + + return NULL; +} + +static void ace_fsm_dostate(struct ace_device *ace) +{ + struct request *req; + u32 status; + u16 val; + int count; + +#if defined(DEBUG) + dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", + ace->fsm_state, ace->id_req_count); +#endif + + /* Verify that there is actually a CF in the slot. If not, then + * bail out back to the idle state and wake up all the waiters */ + status = ace_in32(ace, ACE_STATUS); + if ((status & ACE_STATUS_CFDETECT) == 0) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_info(ace->dev, "No CF in slot\n"); + + /* Drop all in-flight and pending requests */ + if (ace->req) { + blk_mq_end_request(ace->req, BLK_STS_IOERR); + ace->req = NULL; + } + while ((req = ace_get_next_request(ace->queue)) != NULL) + blk_mq_end_request(req, BLK_STS_IOERR); + + /* Drop back to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = -EIO; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + } + + switch (ace->fsm_state) { + case ACE_FSM_STATE_IDLE: + /* See if there is anything to do */ + if (ace->id_req_count || ace_has_next_request(ace->queue)) { + ace->fsm_iter_num++; + ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; + mod_timer(&ace->stall_timer, jiffies + HZ); + if (!timer_pending(&ace->stall_timer)) + add_timer(&ace->stall_timer); + break; + } + del_timer(&ace->stall_timer); + ace->fsm_continue_flag = 0; + break; + + case ACE_FSM_STATE_REQ_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* Already have the lock, jump to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* Request the lock */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); + ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; + break; + + case ACE_FSM_STATE_WAIT_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* got the lock; move to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* wait a bit for the lock */ + ace_fsm_yield(ace); + break; + + case ACE_FSM_STATE_WAIT_CFREADY: + status = ace_in32(ace, ACE_STATUS); + if (!(status & ACE_STATUS_RDYFORCFCMD) || + (status & ACE_STATUS_CFBSY)) { + /* CF card isn't ready; it needs to be polled */ + ace_fsm_yield(ace); + break; + } + + /* Device is ready for command; determine what to do next */ + if (ace->id_req_count) + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; + else + ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; + break; + + case ACE_FSM_STATE_IDENTIFY_PREPARE: + /* Send identify command */ + ace->fsm_task = ACE_TASK_IDENTIFY; + ace->data_ptr = ace->cf_id; + ace->data_count = ACE_BUF_PER_SECTOR; + ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* irq handler takes over from this point; wait for the + * transfer to complete */ + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; + ace_fsm_yieldirq(ace); + break; + + case ACE_FSM_STATE_IDENTIFY_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", + ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + ace_fsm_yield(ace); + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + ace_fsm_yield(ace); + break; + } + + /* Transfer the next buffer */ + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* transfer finished; kick state machine */ + dev_dbg(ace->dev, "identify finished\n"); + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; + break; + + case ACE_FSM_STATE_IDENTIFY_COMPLETE: + ace_fix_driveid(ace->cf_id); + ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */ + + if (ace->data_result) { + /* Error occurred, disable the disk */ + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_err(ace->dev, "error fetching CF id (%i)\n", + ace->data_result); + } else { + ace->media_change = 0; + + /* Record disk parameters */ + set_capacity(ace->gd, + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + dev_info(ace->dev, "capacity: %i sectors\n", + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + } + + /* We're done, drop to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = ace->data_result; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + break; + + case ACE_FSM_STATE_REQ_PREPARE: + req = ace_get_next_request(ace->queue); + if (!req) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } + + /* Okay, it's a data request, set it up for transfer */ + dev_dbg(ace->dev, + "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n", + (unsigned long long)blk_rq_pos(req), + blk_rq_sectors(req), blk_rq_cur_sectors(req), + rq_data_dir(req)); + + ace->req = req; + ace->data_ptr = bio_data(req->bio); + ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR; + ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF); + + count = blk_rq_sectors(req); + if (rq_data_dir(req)) { + /* Kick off write request */ + dev_dbg(ace->dev, "write data\n"); + ace->fsm_task = ACE_TASK_WRITE; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_WRITE_DATA); + } else { + /* Kick off read request */ + dev_dbg(ace->dev, "read data\n"); + ace->fsm_task = ACE_TASK_READ; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_READ_DATA); + } + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* Move to the transfer state. The systemace will raise + * an interrupt once there is something to do + */ + ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; + if (ace->fsm_task == ACE_TASK_READ) + ace_fsm_yieldirq(ace); /* wait for data ready */ + break; + + case ACE_FSM_STATE_REQ_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, + "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yield(ace); /* need to poll CFBSY bit */ + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + dev_dbg(ace->dev, + "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yieldirq(ace); + break; + } + + /* Transfer the next buffer */ + if (ace->fsm_task == ACE_TASK_WRITE) + ace->reg_ops->dataout(ace); + else + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* bio finished; is there another one? */ + if (blk_update_request(ace->req, BLK_STS_OK, + blk_rq_cur_bytes(ace->req))) { + /* dev_dbg(ace->dev, "next block; h=%u c=%u\n", + * blk_rq_sectors(ace->req), + * blk_rq_cur_sectors(ace->req)); + */ + ace->data_ptr = bio_data(ace->req->bio); + ace->data_count = blk_rq_cur_sectors(ace->req) * 16; + ace_fsm_yieldirq(ace); + break; + } + + ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; + break; + + case ACE_FSM_STATE_REQ_COMPLETE: + ace->req = NULL; + + /* Finished request; go to idle state */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + + default: + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } +} + +static void ace_fsm_tasklet(unsigned long data) +{ + struct ace_device *ace = (void *)data; + unsigned long flags; + + spin_lock_irqsave(&ace->lock, flags); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +static void ace_stall_timer(struct timer_list *t) +{ + struct ace_device *ace = from_timer(ace, t, stall_timer); + unsigned long flags; + + dev_warn(ace->dev, + "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", + ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + spin_lock_irqsave(&ace->lock, flags); + + /* Rearm the stall timer *before* entering FSM (which may then + * delete the timer) */ + mod_timer(&ace->stall_timer, jiffies + HZ); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +/* --------------------------------------------------------------------- + * Interrupt handling routines + */ +static int ace_interrupt_checkstate(struct ace_device *ace) +{ + u32 sreg = ace_in32(ace, ACE_STATUS); + u16 creg = ace_in(ace, ACE_CTRL); + + /* Check for error occurrence */ + if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && + (creg & ACE_CTRL_ERRORIRQ)) { + dev_err(ace->dev, "transfer failure\n"); + ace_dump_regs(ace); + return -EIO; + } + + return 0; +} + +static irqreturn_t ace_interrupt(int irq, void *dev_id) +{ + u16 creg; + struct ace_device *ace = dev_id; + + /* be safe and get the lock */ + spin_lock(&ace->lock); + ace->in_irq = 1; + + /* clear the interrupt */ + creg = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); + ace_out(ace, ACE_CTRL, creg); + + /* check for IO failures */ + if (ace_interrupt_checkstate(ace)) + ace->data_result = -EIO; + + if (ace->fsm_task == 0) { + dev_err(ace->dev, + "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", + ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD)); + dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", + ace->fsm_task, ace->fsm_state, ace->data_count); + } + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + /* done with interrupt; drop the lock */ + ace->in_irq = 0; + spin_unlock(&ace->lock); + + return IRQ_HANDLED; +} + +/* --------------------------------------------------------------------- + * Block ops + */ +static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx, + const struct blk_mq_queue_data *bd) +{ + struct ace_device *ace = hctx->queue->queuedata; + struct request *req = bd->rq; + + if (blk_rq_is_passthrough(req)) { + blk_mq_start_request(req); + return BLK_STS_IOERR; + } + + spin_lock_irq(&ace->lock); + list_add_tail(&req->queuelist, &ace->rq_list); + spin_unlock_irq(&ace->lock); + + tasklet_schedule(&ace->fsm_tasklet); + return BLK_STS_OK; +} + +static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing) +{ + struct ace_device *ace = gd->private_data; + dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change); + + return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0; +} + +static void ace_media_changed(struct ace_device *ace) +{ + unsigned long flags; + + dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); + + spin_lock_irqsave(&ace->lock, flags); + ace->id_req_count++; + spin_unlock_irqrestore(&ace->lock, flags); + + tasklet_schedule(&ace->fsm_tasklet); + wait_for_completion(&ace->id_completion); + + dev_dbg(ace->dev, "revalidate complete\n"); +} + +static int ace_open(struct block_device *bdev, fmode_t mode) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + unsigned long flags; + + dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users++; + spin_unlock_irqrestore(&ace->lock, flags); + + if (bdev_check_media_change(bdev) && ace->media_change) + ace_media_changed(ace); + mutex_unlock(&xsysace_mutex); + + return 0; +} + +static void ace_release(struct gendisk *disk, fmode_t mode) +{ + struct ace_device *ace = disk->private_data; + unsigned long flags; + u16 val; + + dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users--; + if (ace->users == 0) { + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); + } + spin_unlock_irqrestore(&ace->lock, flags); + mutex_unlock(&xsysace_mutex); +} + +static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + u16 *cf_id = ace->cf_id; + + dev_dbg(ace->dev, "ace_getgeo()\n"); + + geo->heads = cf_id[ATA_ID_HEADS]; + geo->sectors = cf_id[ATA_ID_SECTORS]; + geo->cylinders = cf_id[ATA_ID_CYLS]; + + return 0; +} + +static const struct block_device_operations ace_fops = { + .owner = THIS_MODULE, + .open = ace_open, + .release = ace_release, + .check_events = ace_check_events, + .getgeo = ace_getgeo, +}; + +static const struct blk_mq_ops ace_mq_ops = { + .queue_rq = ace_queue_rq, +}; + +/* -------------------------------------------------------------------- + * SystemACE device setup/teardown code + */ +static int ace_setup(struct ace_device *ace) +{ + u16 version; + u16 val; + int rc; + + dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); + dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", + (unsigned long long)ace->physaddr, ace->irq); + + spin_lock_init(&ace->lock); + init_completion(&ace->id_completion); + INIT_LIST_HEAD(&ace->rq_list); + + /* + * Map the device + */ + ace->baseaddr = ioremap(ace->physaddr, 0x80); + if (!ace->baseaddr) + goto err_ioremap; + + /* + * Initialize the state machine tasklet and stall timer + */ + tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); + timer_setup(&ace->stall_timer, ace_stall_timer, 0); + + /* + * Initialize the request queue + */ + ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2, + BLK_MQ_F_SHOULD_MERGE); + if (IS_ERR(ace->queue)) { + rc = PTR_ERR(ace->queue); + ace->queue = NULL; + goto err_blk_initq; + } + ace->queue->queuedata = ace; + + blk_queue_logical_block_size(ace->queue, 512); + blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH); + + /* + * Allocate and initialize GD structure + */ + ace->gd = alloc_disk(ACE_NUM_MINORS); + if (!ace->gd) + goto err_alloc_disk; + + ace->gd->major = ace_major; + ace->gd->first_minor = ace->id * ACE_NUM_MINORS; + ace->gd->fops = &ace_fops; + ace->gd->events = DISK_EVENT_MEDIA_CHANGE; + ace->gd->queue = ace->queue; + ace->gd->private_data = ace; + snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); + + /* set bus width */ + if (ace->bus_width == ACE_BUS_WIDTH_16) { + /* 0x0101 should work regardless of endianess */ + ace_out_le16(ace, ACE_BUSMODE, 0x0101); + + /* read it back to determine endianess */ + if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) + ace->reg_ops = &ace_reg_le16_ops; + else + ace->reg_ops = &ace_reg_be16_ops; + } else { + ace_out_8(ace, ACE_BUSMODE, 0x00); + ace->reg_ops = &ace_reg_8_ops; + } + + /* Make sure version register is sane */ + version = ace_in(ace, ACE_VERSION); + if ((version == 0) || (version == 0xFFFF)) + goto err_read; + + /* Put sysace in a sane state by clearing most control reg bits */ + ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | + ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); + + /* Now we can hook up the irq handler */ + if (ace->irq > 0) { + rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); + if (rc) { + /* Failure - fall back to polled mode */ + dev_err(ace->dev, "request_irq failed\n"); + ace->irq = rc; + } + } + + /* Enable interrupts */ + val = ace_in(ace, ACE_CTRL); + val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; + ace_out(ace, ACE_CTRL, val); + + /* Print the identification */ + dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", + (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); + dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", + (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); + + ace->media_change = 1; + ace_media_changed(ace); + + /* Make the sysace device 'live' */ + add_disk(ace->gd); + + return 0; + +err_read: + /* prevent double queue cleanup */ + ace->gd->queue = NULL; + put_disk(ace->gd); +err_alloc_disk: + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); +err_blk_initq: + iounmap(ace->baseaddr); +err_ioremap: + dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", + (unsigned long long) ace->physaddr); + return -ENOMEM; +} + +static void ace_teardown(struct ace_device *ace) +{ + if (ace->gd) { + del_gendisk(ace->gd); + put_disk(ace->gd); + } + + if (ace->queue) { + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); + } + + tasklet_kill(&ace->fsm_tasklet); + + if (ace->irq > 0) + free_irq(ace->irq, ace); + + iounmap(ace->baseaddr); +} + +static int ace_alloc(struct device *dev, int id, resource_size_t physaddr, + int irq, int bus_width) +{ + struct ace_device *ace; + int rc; + dev_dbg(dev, "ace_alloc(%p)\n", dev); + + /* Allocate and initialize the ace device structure */ + ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); + if (!ace) { + rc = -ENOMEM; + goto err_alloc; + } + + ace->dev = dev; + ace->id = id; + ace->physaddr = physaddr; + ace->irq = irq; + ace->bus_width = bus_width; + + /* Call the setup code */ + rc = ace_setup(ace); + if (rc) + goto err_setup; + + dev_set_drvdata(dev, ace); + return 0; + +err_setup: + dev_set_drvdata(dev, NULL); + kfree(ace); +err_alloc: + dev_err(dev, "could not initialize device, err=%i\n", rc); + return rc; +} + +static void ace_free(struct device *dev) +{ + struct ace_device *ace = dev_get_drvdata(dev); + dev_dbg(dev, "ace_free(%p)\n", dev); + + if (ace) { + ace_teardown(ace); + dev_set_drvdata(dev, NULL); + kfree(ace); + } +} + +/* --------------------------------------------------------------------- + * Platform Bus Support + */ + +static int ace_probe(struct platform_device *dev) +{ + int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ + resource_size_t physaddr; + struct resource *res; + u32 id = dev->id; + int irq; + int i; + + dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); + + /* device id and bus width */ + if (of_property_read_u32(dev->dev.of_node, "port-number", &id)) + id = 0; + if (of_find_property(dev->dev.of_node, "8-bit", NULL)) + bus_width = ACE_BUS_WIDTH_8; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + physaddr = res->start; + if (!physaddr) + return -ENODEV; + + irq = platform_get_irq_optional(dev, 0); + + /* Call the bus-independent setup code */ + return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); +} + +/* + * Platform bus remove() method + */ +static int ace_remove(struct platform_device *dev) +{ + ace_free(&dev->dev); + return 0; +} + +#if defined(CONFIG_OF) +/* Match table for of_platform binding */ +static const struct of_device_id ace_of_match[] = { + { .compatible = "xlnx,opb-sysace-1.00.b", }, + { .compatible = "xlnx,opb-sysace-1.00.c", }, + { .compatible = "xlnx,xps-sysace-1.00.a", }, + { .compatible = "xlnx,sysace", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ace_of_match); +#else /* CONFIG_OF */ +#define ace_of_match NULL +#endif /* CONFIG_OF */ + +static struct platform_driver ace_platform_driver = { + .probe = ace_probe, + .remove = ace_remove, + .driver = { + .name = "xsysace", + .of_match_table = ace_of_match, + }, +}; + +/* --------------------------------------------------------------------- + * Module init/exit routines + */ +static int __init ace_init(void) +{ + int rc; + + ace_major = register_blkdev(ace_major, "xsysace"); + if (ace_major <= 0) { + rc = -ENOMEM; + goto err_blk; + } + + rc = platform_driver_register(&ace_platform_driver); + if (rc) + goto err_plat; + + pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); + return 0; + +err_plat: + unregister_blkdev(ace_major, "xsysace"); +err_blk: + printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); + return rc; +} +module_init(ace_init); + +static void __exit ace_exit(void) +{ + pr_debug("Unregistering Xilinx SystemACE driver\n"); + platform_driver_unregister(&ace_platform_driver); + unregister_blkdev(ace_major, "xsysace"); +} +module_exit(ace_exit); diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c new file mode 100644 index 0000000000000..aae82db542a5e --- /dev/null +++ b/drivers/extcon/extcon-arizona.c @@ -0,0 +1,1816 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * extcon-arizona.c - Extcon driver Wolfson Arizona devices + * + * Copyright (C) 2012-2014 Wolfson Microelectronics plc + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define ARIZONA_MAX_MICD_RANGE 8 + +#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4 +#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5 +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9 +#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb + +#define ARIZONA_TST_CAP_DEFAULT 0x3 +#define ARIZONA_TST_CAP_CLAMP 0x1 + +#define ARIZONA_HPDET_MAX 10000 + +#define HPDET_DEBOUNCE 500 +#define DEFAULT_MICD_TIMEOUT 2000 + +#define ARIZONA_HPDET_WAIT_COUNT 15 +#define ARIZONA_HPDET_WAIT_DELAY_MS 20 + +#define QUICK_HEADPHONE_MAX_OHM 3 +#define MICROPHONE_MIN_OHM 1257 +#define MICROPHONE_MAX_OHM 30000 + +#define MICD_DBTIME_TWO_READINGS 2 +#define MICD_DBTIME_FOUR_READINGS 4 + +#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \ + ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \ + ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \ + ARIZONA_MICD_LVL_7) + +#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7) + +#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8) + +struct arizona_extcon_info { + struct device *dev; + struct arizona *arizona; + struct mutex lock; + struct regulator *micvdd; + struct input_dev *input; + + u16 last_jackdet; + + int micd_mode; + const struct arizona_micd_config *micd_modes; + int micd_num_modes; + + const struct arizona_micd_range *micd_ranges; + int num_micd_ranges; + + bool micd_reva; + bool micd_clamp; + + struct delayed_work hpdet_work; + struct delayed_work micd_detect_work; + struct delayed_work micd_timeout_work; + + bool hpdet_active; + bool hpdet_done; + bool hpdet_retried; + + int num_hpdet_res; + unsigned int hpdet_res[3]; + + bool mic; + bool detecting; + int jack_flips; + + int hpdet_ip_version; + + struct extcon_dev *edev; + + struct gpio_desc *micd_pol_gpio; +}; + +static const struct arizona_micd_config micd_default_modes[] = { + { ARIZONA_ACCDET_SRC, 1, 0 }, + { 0, 2, 1 }, +}; + +static const struct arizona_micd_range micd_default_ranges[] = { + { .max = 11, .key = BTN_0 }, + { .max = 28, .key = BTN_1 }, + { .max = 54, .key = BTN_2 }, + { .max = 100, .key = BTN_3 }, + { .max = 186, .key = BTN_4 }, + { .max = 430, .key = BTN_5 }, +}; + +/* The number of levels in arizona_micd_levels valid for button thresholds */ +#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64 + +static const int arizona_micd_levels[] = { + 3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46, + 49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100, + 105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245, + 270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071, + 1257, 30000, +}; + +static const unsigned int arizona_cable[] = { + EXTCON_MECHANICAL, + EXTCON_JACK_MICROPHONE, + EXTCON_JACK_HEADPHONE, + EXTCON_JACK_LINE_OUT, + EXTCON_NONE, +}; + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info); + +static void arizona_extcon_hp_clamp(struct arizona_extcon_info *info, + bool clamp) +{ + struct arizona *arizona = info->arizona; + unsigned int mask = 0, val = 0; + unsigned int cap_sel = 0; + int ret; + + switch (arizona->type) { + case WM8998: + case WM1814: + mask = 0; + break; + case WM5110: + case WM8280: + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) { + val = ARIZONA_HP1L_SHRTO; + cap_sel = ARIZONA_TST_CAP_CLAMP; + } else { + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + cap_sel = ARIZONA_TST_CAP_DEFAULT; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_TEST_CTRL_1, + ARIZONA_HP1_TST_CAP_SEL_MASK, + cap_sel); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to set TST_CAP_SEL: %d\n", ret); + break; + default: + mask = ARIZONA_RMV_SHRT_HP1L; + if (clamp) + val = ARIZONA_RMV_SHRT_HP1L; + break; + } + + snd_soc_dapm_mutex_lock(arizona->dapm); + + arizona->hpdet_clamp = clamp; + + /* Keep the HP output stages disabled while doing the clamp */ + if (clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable headphone outputs: %d\n", + ret); + } + + if (mask) { + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1L, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1R, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + } + + /* Restore the desired state while not doing the clamp */ + if (!clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, arizona->hp_ena); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to restore headphone outputs: %d\n", + ret); + } + + snd_soc_dapm_mutex_unlock(arizona->dapm); +} + +static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) +{ + struct arizona *arizona = info->arizona; + + mode %= info->micd_num_modes; + + gpiod_set_value_cansleep(info->micd_pol_gpio, + info->micd_modes[mode].gpio); + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_SRC_MASK, + info->micd_modes[mode].bias << + ARIZONA_MICD_BIAS_SRC_SHIFT); + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[mode].src); + + info->micd_mode = mode; + + dev_dbg(arizona->dev, "Set jack polarity to %d\n", mode); +} + +static const char *arizona_extcon_get_micbias(struct arizona_extcon_info *info) +{ + switch (info->micd_modes[0].bias) { + case 1: + return "MICBIAS1"; + case 2: + return "MICBIAS2"; + case 3: + return "MICBIAS3"; + default: + return "MICVDD"; + } +} + +static void arizona_extcon_pulse_micbias(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + int ret; + + ret = snd_soc_component_force_enable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to enable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (!arizona->pdata.micd_force_micbias) { + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + } +} + +static void arizona_start_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + bool change; + int ret; + unsigned int mode; + + /* Microphone detection can't use idle mode */ + pm_runtime_get(info->dev); + + if (info->detecting) { + ret = regulator_allow_bypass(info->micvdd, false); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to regulate MICVDD: %d\n", + ret); + } + } + + ret = regulator_enable(info->micvdd); + if (ret != 0) { + dev_err(arizona->dev, "Failed to enable MICVDD: %d\n", + ret); + } + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x0 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + if (info->detecting && arizona->pdata.micd_software_compare) + mode = ARIZONA_ACCDET_MODE_ADC; + else + mode = ARIZONA_ACCDET_MODE_MIC; + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, mode); + + arizona_extcon_pulse_micbias(info); + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA, + &change); + if (ret < 0) { + dev_err(arizona->dev, "Failed to enable micd: %d\n", ret); + } else if (!change) { + regulator_disable(info->micvdd); + pm_runtime_put_autosuspend(info->dev); + } +} + +static void arizona_stop_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + bool change = false; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) + dev_err(arizona->dev, "Failed to disable micd: %d\n", ret); + + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x2 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + if (change) { + regulator_disable(info->micvdd); + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + } +} + +static struct { + unsigned int threshold; + unsigned int factor_a; + unsigned int factor_b; +} arizona_hpdet_b_ranges[] = { + { 100, 5528, 362464 }, + { 169, 11084, 6186851 }, + { 169, 11065, 65460395 }, +}; + +#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb + +static struct { + int min; + int max; +} arizona_hpdet_c_ranges[] = { + { 0, 30 }, + { 8, 100 }, + { 100, 1000 }, + { 1000, 10000 }, +}; + +static int arizona_hpdet_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val, range; + int ret; + + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HPDET status: %d\n", + ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (!(val & ARIZONA_HP_DONE)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_MASK; + break; + + case 1: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP value: %d\n", + ret); + return -EAGAIN; + } + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 && + (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d\n", + range); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + /* If we go out of range report top of range */ + if (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX) { + dev_dbg(arizona->dev, "Measurement out of range\n"); + return ARIZONA_HPDET_MAX; + } + + dev_dbg(arizona->dev, "HPDET read %d in range %d\n", + val, range); + + val = arizona_hpdet_b_ranges[range].factor_b + / ((val * 100) - + arizona_hpdet_b_ranges[range].factor_a); + break; + + case 2: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to ohms, the value is in 0.5 ohm increments */ + val /= 2; + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + /* Skip up a range, or report? */ + if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 && + (val >= arizona_hpdet_c_ranges[range].max)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", + arizona_hpdet_c_ranges[range].min, + arizona_hpdet_c_ranges[range].max); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + if (range && (val < arizona_hpdet_c_ranges[range].min)) { + dev_dbg(arizona->dev, "Reporting range boundary %d\n", + arizona_hpdet_c_ranges[range].min); + val = arizona_hpdet_c_ranges[range].min; + } + break; + + default: + dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", + info->hpdet_ip_version); + return -EINVAL; + } + + dev_dbg(arizona->dev, "HP impedance %d ohms\n", val); + return val; +} + +static int arizona_hpdet_do_id(struct arizona_extcon_info *info, int *reading, + bool *mic) +{ + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + + if (!arizona->pdata.hpdet_acc_id) + return 0; + + /* + * If we're using HPDET for accessory identification we need + * to take multiple measurements, step through them in sequence. + */ + info->hpdet_res[info->num_hpdet_res++] = *reading; + + /* Only check the mic directly if we didn't already ID it */ + if (id_gpio && info->num_hpdet_res == 1) { + dev_dbg(arizona->dev, "Measuring mic\n"); + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK | + ARIZONA_ACCDET_SRC, + ARIZONA_ACCDET_MODE_HPR | + info->micd_modes[0].src); + + gpio_set_value_cansleep(id_gpio, 1); + + regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + return -EAGAIN; + } + + /* OK, got both. Now, compare... */ + dev_dbg(arizona->dev, "HPDET measured %d %d\n", + info->hpdet_res[0], info->hpdet_res[1]); + + /* Take the headphone impedance for the main report */ + *reading = info->hpdet_res[0]; + + /* Sometimes we get false readings due to slow insert */ + if (*reading >= ARIZONA_HPDET_MAX && !info->hpdet_retried) { + dev_dbg(arizona->dev, "Retrying high impedance\n"); + info->num_hpdet_res = 0; + info->hpdet_retried = true; + arizona_start_hpdet_acc_id(info); + pm_runtime_put(info->dev); + return -EAGAIN; + } + + /* + * If we measure the mic as high impedance + */ + if (!id_gpio || info->hpdet_res[1] > 50) { + dev_dbg(arizona->dev, "Detected mic\n"); + *mic = true; + info->detecting = true; + } else { + dev_dbg(arizona->dev, "Detected headphone\n"); + } + + /* Make sure everything is reset back to the real polarity */ + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[0].src); + + return 0; +} + +static irqreturn_t arizona_hpdet_irq(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + unsigned int report = EXTCON_JACK_HEADPHONE; + int ret, reading; + bool mic = false; + + mutex_lock(&info->lock); + + /* If we got a spurious IRQ for some reason then ignore it */ + if (!info->hpdet_active) { + dev_warn(arizona->dev, "Spurious HPDET IRQ\n"); + mutex_unlock(&info->lock); + return IRQ_NONE; + } + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + goto out; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring HPDET for removed cable\n"); + goto done; + } + + ret = arizona_hpdet_read(info); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + reading = ret; + + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + ret = arizona_hpdet_do_id(info, &reading, &mic); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + + /* Report high impedence cables as line outputs */ + if (reading >= 5000) + report = EXTCON_JACK_LINE_OUT; + else + report = EXTCON_JACK_HEADPHONE; + + ret = extcon_set_state_sync(info->edev, report, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report HP/line: %d\n", + ret); + +done: + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + arizona_extcon_hp_clamp(info, false); + + if (id_gpio) + gpio_set_value_cansleep(id_gpio, 0); + + /* If we have a mic then reenable MICDET */ + if (mic || info->mic) + arizona_start_mic(info); + + if (info->hpdet_active) { + pm_runtime_put_autosuspend(info->dev); + info->hpdet_active = false; + } + + info->hpdet_done = true; + +out: + mutex_unlock(&info->lock); + + return IRQ_HANDLED; +} + +static void arizona_identify_headphone(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + if (info->hpdet_done) + return; + + dev_dbg(arizona->dev, "Starting HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get(info->dev); + + info->hpdet_active = true; + + arizona_stop_mic(info); + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + + return; + +err: + arizona_extcon_hp_clamp(info, false); + pm_runtime_put_autosuspend(info->dev); + + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + if (info->mic) + arizona_start_mic(info); + + info->hpdet_active = false; +} + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int hp_reading = 32; + bool mic; + int ret; + + dev_dbg(arizona->dev, "Starting identification via HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get_sync(info->dev); + + info->hpdet_active = true; + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + if (arizona->pdata.hpdet_acc_id_line) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, + "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + } else { + arizona_hpdet_do_id(info, &hp_reading, &mic); + } + + return; + +err: + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + info->hpdet_active = false; +} + +static void arizona_micd_timeout_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_timeout_work.work); + + mutex_lock(&info->lock); + + dev_dbg(info->arizona->dev, "MICD timed out, reporting HP\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + + mutex_unlock(&info->lock); +} + +static int arizona_micd_adc_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int ret; + + /* Must disable MICD before we read the ADCVAL */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET_ADCVAL: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val); + + val &= ARIZONA_MICDET_ADCVAL_MASK; + if (val < ARRAY_SIZE(arizona_micd_levels)) + val = arizona_micd_levels[val]; + else + val = INT_MAX; + + if (val <= QUICK_HEADPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0; + else if (val <= MICROPHONE_MIN_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1; + else if (val <= MICROPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8; + else + val = ARIZONA_MICD_LVL_8; + + return val; +} + +static int arizona_micd_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val = 0; + int ret, i; + + for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET: %x\n", val); + + if (!(val & ARIZONA_MICD_VALID)) { + dev_warn(arizona->dev, + "Microphone detection state invalid\n"); + return -EINVAL; + } + } + + if (i == 10 && !(val & MICD_LVL_0_TO_8)) { + dev_err(arizona->dev, "Failed to get valid MICDET value\n"); + return -EINVAL; + } + + return val; +} + +static int arizona_micdet_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int ret, val; + + if (info->detecting && arizona->pdata.micd_software_compare) + ret = arizona_micd_adc_read(info); + else + ret = arizona_micd_read(info); + if (ret < 0) + return ret; + + val = ret; + + /* Due to jack detect this should never happen */ + if (!(val & ARIZONA_MICD_STS)) { + dev_warn(arizona->dev, "Detected open circuit\n"); + info->mic = false; + info->detecting = false; + arizona_identify_headphone(info); + return 0; + } + + /* If we got a high impedence we should have a headset, report it. */ + if (val & ARIZONA_MICD_LVL_8) { + info->mic = true; + info->detecting = false; + + arizona_identify_headphone(info); + + ret = extcon_set_state_sync(info->edev, + EXTCON_JACK_MICROPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Headset report failed: %d\n", + ret); + + /* Don't need to regulate for button detection */ + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + return 0; + } + + /* If we detected a lower impedence during initial startup + * then we probably have the wrong polarity, flip it. Don't + * do this for the lowest impedences to speed up detection of + * plain headphones. If both polarities report a low + * impedence then give up and report headphones. + */ + if (val & MICD_LVL_1_TO_7) { + if (info->jack_flips >= info->micd_num_modes * 10) { + dev_dbg(arizona->dev, "Detected HP/line\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + } else { + info->micd_mode++; + if (info->micd_mode == info->micd_num_modes) + info->micd_mode = 0; + arizona_extcon_set_mode(info, info->micd_mode); + + info->jack_flips++; + + if (arizona->pdata.micd_software_compare) + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, + ARIZONA_MICD_ENA); + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(arizona->pdata.micd_timeout)); + } + + return 0; + } + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. + */ + dev_dbg(arizona->dev, "Headphone detected\n"); + info->detecting = false; + + arizona_identify_headphone(info); + + return 0; +} + +static int arizona_button_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int val, key, lvl, i; + + val = arizona_micd_read(info); + if (val < 0) + return val; + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. Otherwise it's a button press. + */ + if (val & MICD_LVL_0_TO_7) { + if (info->mic) { + dev_dbg(arizona->dev, "Mic button detected\n"); + + lvl = val & ARIZONA_MICD_LVL_MASK; + lvl >>= ARIZONA_MICD_LVL_SHIFT; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + + if (lvl && ffs(lvl) - 1 < info->num_micd_ranges) { + key = info->micd_ranges[ffs(lvl) - 1].key; + input_report_key(info->input, key, 1); + input_sync(info->input); + } else { + dev_err(arizona->dev, "Button out of range\n"); + } + } else { + dev_warn(arizona->dev, "Button with no mic: %x\n", + val); + } + } else { + dev_dbg(arizona->dev, "Mic button released\n"); + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + arizona_extcon_pulse_micbias(info); + } + + return 0; +} + +static void arizona_micd_detect(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_detect_work.work); + struct arizona *arizona = info->arizona; + int ret; + + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + mutex_unlock(&info->lock); + return; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n"); + mutex_unlock(&info->lock); + return; + } + + if (info->detecting) + arizona_micdet_reading(info); + else + arizona_button_reading(info); + + pm_runtime_mark_last_busy(info->dev); + mutex_unlock(&info->lock); +} + +static irqreturn_t arizona_micdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int debounce = arizona->pdata.micd_detect_debounce; + + cancel_delayed_work_sync(&info->micd_detect_work); + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + if (!info->detecting) + debounce = 0; + mutex_unlock(&info->lock); + + if (debounce) + queue_delayed_work(system_power_efficient_wq, + &info->micd_detect_work, + msecs_to_jiffies(debounce)); + else + arizona_micd_detect(&info->micd_detect_work.work); + + return IRQ_HANDLED; +} + +static void arizona_hpdet_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + hpdet_work.work); + + mutex_lock(&info->lock); + arizona_start_hpdet_acc_id(info); + mutex_unlock(&info->lock); +} + +static int arizona_hpdet_wait(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int i, ret; + + for (i = 0; i < ARIZONA_HPDET_WAIT_COUNT; i++) { + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, + &val); + if (ret) { + dev_err(arizona->dev, + "Failed to read HPDET state: %d\n", ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (val & ARIZONA_HP_DONE) + return 0; + break; + default: + if (val & ARIZONA_HP_DONE_B) + return 0; + break; + } + + msleep(ARIZONA_HPDET_WAIT_DELAY_MS); + } + + dev_warn(arizona->dev, "HPDET did not appear to complete\n"); + + return -ETIMEDOUT; +} + +static irqreturn_t arizona_jackdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + unsigned int val, present, mask; + bool cancelled_hp, cancelled_mic; + int ret, i; + + cancelled_hp = cancel_delayed_work_sync(&info->hpdet_work); + cancelled_mic = cancel_delayed_work_sync(&info->micd_timeout_work); + + pm_runtime_get_sync(info->dev); + + mutex_lock(&info->lock); + + if (info->micd_clamp) { + mask = ARIZONA_MICD_CLAMP_STS; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read jackdet status: %d\n", + ret); + mutex_unlock(&info->lock); + pm_runtime_put_autosuspend(info->dev); + return IRQ_NONE; + } + + val &= mask; + if (val == info->last_jackdet) { + dev_dbg(arizona->dev, "Suppressing duplicate JACKDET\n"); + if (cancelled_hp) + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + + if (cancelled_mic) { + int micd_timeout = arizona->pdata.micd_timeout; + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(micd_timeout)); + } + + goto out; + } + info->last_jackdet = val; + + if (info->last_jackdet == present) { + dev_dbg(arizona->dev, "Detected jack\n"); + ret = extcon_set_state_sync(info->edev, + EXTCON_MECHANICAL, true); + + if (ret != 0) + dev_err(arizona->dev, "Mechanical report failed: %d\n", + ret); + + info->detecting = true; + info->mic = false; + info->jack_flips = 0; + + if (!arizona->pdata.hpdet_acc_id) { + arizona_start_mic(info); + } else { + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + } + + if (info->micd_clamp || !arizona->pdata.jd_invert) + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | + ARIZONA_JD1_DB, 0); + } else { + dev_dbg(arizona->dev, "Detected jack removal\n"); + + arizona_stop_mic(info); + + info->num_hpdet_res = 0; + for (i = 0; i < ARRAY_SIZE(info->hpdet_res); i++) + info->hpdet_res[i] = 0; + info->mic = false; + info->hpdet_done = false; + info->hpdet_retried = false; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + + for (i = 0; i < ARRAY_SIZE(arizona_cable) - 1; i++) { + ret = extcon_set_state_sync(info->edev, + arizona_cable[i], false); + if (ret != 0) + dev_err(arizona->dev, + "Removal report failed: %d\n", ret); + } + + /* + * If the jack was removed during a headphone detection we + * need to wait for the headphone detection to finish, as + * it can not be aborted. We don't want to be able to start + * a new headphone detection from a fresh insert until this + * one is finished. + */ + arizona_hpdet_wait(info); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB); + } + +out: + /* Clear trig_sts to make sure DCVDD is not forced up */ + regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, + ARIZONA_MICD_CLAMP_FALL_TRIG_STS | + ARIZONA_MICD_CLAMP_RISE_TRIG_STS | + ARIZONA_JD1_FALL_TRIG_STS | + ARIZONA_JD1_RISE_TRIG_STS); + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + return IRQ_HANDLED; +} + +/* Map a level onto a slot in the register bank */ +static void arizona_micd_set_level(struct arizona *arizona, int index, + unsigned int level) +{ + int reg; + unsigned int mask; + + reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2); + + if (!(index % 2)) { + mask = 0x3f00; + level <<= 8; + } else { + mask = 0x3f; + } + + /* Program the level itself */ + regmap_update_bits(arizona->regmap, reg, mask, level); +} + +static int arizona_extcon_get_micd_configs(struct device *dev, + struct arizona *arizona) +{ + const char * const prop = "wlf,micd-configs"; + const int entries_per_config = 3; + struct arizona_micd_config *micd_configs; + int nconfs, ret; + int i, j; + u32 *vals; + + nconfs = device_property_count_u32(arizona->dev, prop); + if (nconfs <= 0) + return 0; + + vals = kcalloc(nconfs, sizeof(u32), GFP_KERNEL); + if (!vals) + return -ENOMEM; + + ret = device_property_read_u32_array(arizona->dev, prop, vals, nconfs); + if (ret < 0) + goto out; + + nconfs /= entries_per_config; + micd_configs = devm_kcalloc(dev, nconfs, sizeof(*micd_configs), + GFP_KERNEL); + if (!micd_configs) { + ret = -ENOMEM; + goto out; + } + + for (i = 0, j = 0; i < nconfs; ++i) { + micd_configs[i].src = vals[j++] ? ARIZONA_ACCDET_SRC : 0; + micd_configs[i].bias = vals[j++]; + micd_configs[i].gpio = vals[j++]; + } + + arizona->pdata.micd_configs = micd_configs; + arizona->pdata.num_micd_configs = nconfs; + +out: + kfree(vals); + return ret; +} + +static int arizona_extcon_device_get_pdata(struct device *dev, + struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + unsigned int val = ARIZONA_ACCDET_MODE_HPL; + int ret; + + device_property_read_u32(arizona->dev, "wlf,hpdet-channel", &val); + switch (val) { + case ARIZONA_ACCDET_MODE_HPL: + case ARIZONA_ACCDET_MODE_HPR: + pdata->hpdet_channel = val; + break; + default: + dev_err(arizona->dev, + "Wrong wlf,hpdet-channel DT value %d\n", val); + pdata->hpdet_channel = ARIZONA_ACCDET_MODE_HPL; + } + + device_property_read_u32(arizona->dev, "wlf,micd-detect-debounce", + &pdata->micd_detect_debounce); + + device_property_read_u32(arizona->dev, "wlf,micd-bias-start-time", + &pdata->micd_bias_start_time); + + device_property_read_u32(arizona->dev, "wlf,micd-rate", + &pdata->micd_rate); + + device_property_read_u32(arizona->dev, "wlf,micd-dbtime", + &pdata->micd_dbtime); + + device_property_read_u32(arizona->dev, "wlf,micd-timeout-ms", + &pdata->micd_timeout); + + pdata->micd_force_micbias = device_property_read_bool(arizona->dev, + "wlf,micd-force-micbias"); + + pdata->micd_software_compare = device_property_read_bool(arizona->dev, + "wlf,micd-software-compare"); + + pdata->jd_invert = device_property_read_bool(arizona->dev, + "wlf,jd-invert"); + + device_property_read_u32(arizona->dev, "wlf,gpsw", &pdata->gpsw); + + pdata->jd_gpio5 = device_property_read_bool(arizona->dev, + "wlf,use-jd2"); + pdata->jd_gpio5_nopull = device_property_read_bool(arizona->dev, + "wlf,use-jd2-nopull"); + + ret = arizona_extcon_get_micd_configs(dev, arizona); + if (ret < 0) + dev_err(arizona->dev, "Failed to read micd configs: %d\n", ret); + + return 0; +} + +static int arizona_extcon_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_extcon_info *info; + unsigned int val; + unsigned int clamp_mode; + int jack_irq_fall, jack_irq_rise; + int ret, mode, i, j; + + if (!arizona->dapm || !arizona->dapm->card) + return -EPROBE_DEFER; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (!dev_get_platdata(arizona->dev)) + arizona_extcon_device_get_pdata(&pdev->dev, arizona); + + info->micvdd = devm_regulator_get(&pdev->dev, "MICVDD"); + if (IS_ERR(info->micvdd)) { + ret = PTR_ERR(info->micvdd); + dev_err(arizona->dev, "Failed to get MICVDD: %d\n", ret); + return ret; + } + + mutex_init(&info->lock); + info->arizona = arizona; + info->dev = &pdev->dev; + info->last_jackdet = ~(ARIZONA_MICD_CLAMP_STS | ARIZONA_JD1_STS); + INIT_DELAYED_WORK(&info->hpdet_work, arizona_hpdet_work); + INIT_DELAYED_WORK(&info->micd_detect_work, arizona_micd_detect); + INIT_DELAYED_WORK(&info->micd_timeout_work, arizona_micd_timeout_work); + platform_set_drvdata(pdev, info); + + switch (arizona->type) { + case WM5102: + switch (arizona->rev) { + case 0: + info->micd_reva = true; + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 1; + break; + } + break; + case WM5110: + case WM8280: + switch (arizona->rev) { + case 0 ... 2: + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + } + break; + case WM8998: + case WM1814: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + default: + break; + } + + info->edev = devm_extcon_dev_allocate(&pdev->dev, arizona_cable); + if (IS_ERR(info->edev)) { + dev_err(&pdev->dev, "failed to allocate extcon device\n"); + return -ENOMEM; + } + + ret = devm_extcon_dev_register(&pdev->dev, info->edev); + if (ret < 0) { + dev_err(arizona->dev, "extcon_dev_register() failed: %d\n", + ret); + return ret; + } + + info->input = devm_input_allocate_device(&pdev->dev); + if (!info->input) { + dev_err(arizona->dev, "Can't allocate input dev\n"); + ret = -ENOMEM; + return ret; + } + + info->input->name = "Headset"; + info->input->phys = "arizona/extcon"; + + if (!pdata->micd_timeout) + pdata->micd_timeout = DEFAULT_MICD_TIMEOUT; + + if (pdata->num_micd_configs) { + info->micd_modes = pdata->micd_configs; + info->micd_num_modes = pdata->num_micd_configs; + } else { + info->micd_modes = micd_default_modes; + info->micd_num_modes = ARRAY_SIZE(micd_default_modes); + } + + if (arizona->pdata.gpsw > 0) + regmap_update_bits(arizona->regmap, ARIZONA_GP_SWITCH_1, + ARIZONA_SW1_MODE_MASK, arizona->pdata.gpsw); + + if (pdata->micd_pol_gpio > 0) { + if (info->micd_modes[0].gpio) + mode = GPIOF_OUT_INIT_HIGH; + else + mode = GPIOF_OUT_INIT_LOW; + + ret = devm_gpio_request_one(&pdev->dev, pdata->micd_pol_gpio, + mode, "MICD polarity"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + pdata->micd_pol_gpio, ret); + return ret; + } + + info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio); + } else { + if (info->micd_modes[0].gpio) + mode = GPIOD_OUT_HIGH; + else + mode = GPIOD_OUT_LOW; + + /* We can't use devm here because we need to do the get + * against the MFD device, as that is where the of_node + * will reside, but if we devm against that the GPIO + * will not be freed if the extcon driver is unloaded. + */ + info->micd_pol_gpio = gpiod_get_optional(arizona->dev, + "wlf,micd-pol", + GPIOD_OUT_LOW); + if (IS_ERR(info->micd_pol_gpio)) { + ret = PTR_ERR(info->micd_pol_gpio); + dev_err(arizona->dev, + "Failed to get microphone polarity GPIO: %d\n", + ret); + return ret; + } + } + + if (arizona->pdata.hpdet_id_gpio > 0) { + ret = devm_gpio_request_one(&pdev->dev, + arizona->pdata.hpdet_id_gpio, + GPIOF_OUT_INIT_LOW, + "HPDET"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + arizona->pdata.hpdet_id_gpio, ret); + goto err_gpio; + } + } + + if (arizona->pdata.micd_bias_start_time) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK, + arizona->pdata.micd_bias_start_time + << ARIZONA_MICD_BIAS_STARTTIME_SHIFT); + + if (arizona->pdata.micd_rate) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_RATE_MASK, + arizona->pdata.micd_rate + << ARIZONA_MICD_RATE_SHIFT); + + switch (arizona->pdata.micd_dbtime) { + case MICD_DBTIME_FOUR_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, + ARIZONA_MICD_DBTIME); + break; + case MICD_DBTIME_TWO_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, 0); + break; + default: + break; + } + + BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) < + ARIZONA_NUM_MICD_BUTTON_LEVELS); + + if (arizona->pdata.num_micd_ranges) { + info->micd_ranges = pdata->micd_ranges; + info->num_micd_ranges = pdata->num_micd_ranges; + } else { + info->micd_ranges = micd_default_ranges; + info->num_micd_ranges = ARRAY_SIZE(micd_default_ranges); + } + + if (arizona->pdata.num_micd_ranges > ARIZONA_MAX_MICD_RANGE) { + dev_err(arizona->dev, "Too many MICD ranges: %d\n", + arizona->pdata.num_micd_ranges); + } + + if (info->num_micd_ranges > 1) { + for (i = 1; i < info->num_micd_ranges; i++) { + if (info->micd_ranges[i - 1].max > + info->micd_ranges[i].max) { + dev_err(arizona->dev, + "MICD ranges must be sorted\n"); + ret = -EINVAL; + goto err_gpio; + } + } + } + + /* Disable all buttons by default */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + ARIZONA_MICD_LVL_SEL_MASK, 0x81); + + /* Set up all the buttons the user specified */ + for (i = 0; i < info->num_micd_ranges; i++) { + for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++) + if (arizona_micd_levels[j] >= info->micd_ranges[i].max) + break; + + if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) { + dev_err(arizona->dev, "Unsupported MICD level %d\n", + info->micd_ranges[i].max); + ret = -EINVAL; + goto err_gpio; + } + + dev_dbg(arizona->dev, "%d ohms for MICD threshold %d\n", + arizona_micd_levels[j], i); + + arizona_micd_set_level(arizona, i, j); + input_set_capability(info->input, EV_KEY, + info->micd_ranges[i].key); + + /* Enable reporting of that range */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + 1 << i, 1 << i); + } + + /* Set all the remaining keys to a maximum */ + for (; i < ARIZONA_MAX_MICD_RANGE; i++) + arizona_micd_set_level(arizona, i, 0x3f); + + /* + * If we have a clamp use it, activating in conjunction with + * GPIO5 if that is connected for jack detect operation. + */ + if (info->micd_clamp) { + if (arizona->pdata.jd_gpio5) { + /* Put the GPIO into input mode with optional pull */ + val = 0xc101; + if (arizona->pdata.jd_gpio5_nopull) + val &= ~ARIZONA_GPN_PU; + + regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, + val); + + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL_GP5H; + } else { + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL; + } + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, clamp_mode); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB, + ARIZONA_MICD_CLAMP_DB); + } + + arizona_extcon_set_mode(info, 0); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + ret = arizona_request_irq(arizona, jack_irq_rise, + "JACKDET rise", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", + ret); + goto err_pm; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD rise IRQ wake: %d\n", + ret); + goto err_rise; + } + + ret = arizona_request_irq(arizona, jack_irq_fall, + "JACKDET fall", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JD fall IRQ: %d\n", ret); + goto err_rise_wake; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_fall, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD fall IRQ wake: %d\n", + ret); + goto err_fall; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_MICDET, + "MICDET", arizona_micdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get MICDET IRQ: %d\n", ret); + goto err_fall_wake; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_HPDET, + "HPDET", arizona_hpdet_irq, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get HPDET IRQ: %d\n", ret); + goto err_micdet; + } + + arizona_clk32k_enable(arizona); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_JD1_DB, ARIZONA_JD1_DB); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, ARIZONA_JD1_ENA); + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) + dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", + ret); + + ret = input_register_device(info->input); + if (ret) { + dev_err(&pdev->dev, "Can't register input device: %d\n", ret); + goto err_hpdet; + } + + pm_runtime_put(&pdev->dev); + + return 0; + +err_hpdet: + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); +err_micdet: + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); +err_fall_wake: + arizona_set_irq_wake(arizona, jack_irq_fall, 0); +err_fall: + arizona_free_irq(arizona, jack_irq_fall, info); +err_rise_wake: + arizona_set_irq_wake(arizona, jack_irq_rise, 0); +err_rise: + arizona_free_irq(arizona, jack_irq_rise, info); +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); +err_gpio: + gpiod_put(info->micd_pol_gpio); + return ret; +} + +static int arizona_extcon_remove(struct platform_device *pdev) +{ + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + struct arizona *arizona = info->arizona; + int jack_irq_rise, jack_irq_fall; + bool change; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to disable micd on remove: %d\n", + ret); + } else if (change) { + regulator_disable(info->micvdd); + pm_runtime_put(info->dev); + } + + gpiod_put(info->micd_pol_gpio); + + pm_runtime_disable(&pdev->dev); + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + arizona_set_irq_wake(arizona, jack_irq_rise, 0); + arizona_set_irq_wake(arizona, jack_irq_fall, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); + arizona_free_irq(arizona, jack_irq_rise, info); + arizona_free_irq(arizona, jack_irq_fall, info); + cancel_delayed_work_sync(&info->hpdet_work); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, 0); + arizona_clk32k_disable(arizona); + + return 0; +} + +static struct platform_driver arizona_extcon_driver = { + .driver = { + .name = "arizona-extcon", + }, + .probe = arizona_extcon_probe, + .remove = arizona_extcon_remove, +}; + +module_platform_driver(arizona_extcon_driver); + +MODULE_DESCRIPTION("Arizona Extcon driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:extcon-arizona"); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 64b7e2df23d04..c4bd6b13ad993 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include "kcl/kcl_amdgpu_ttm.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 new file mode 100644 index 0000000000000..4a1160753c960 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # commit v5.10-rc3-1140-gc67e62790f5c +dnl # drm/prime: split array import functions v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, [drm_prime_sg_to_dma_addr_array() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 new file mode 100644 index 0000000000000..b2614eabab932 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit f3ba3c710ac5a30cd058615a9eb62d2ad95bb782 +dnl # mm/highmem: Provide kmap_local* +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pgprot_t prot; + kmap_local_page_prot(NULL, prot); + ], [], [], [ + AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a77c96839bbf7..441a5a67a743d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -97,12 +97,13 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS - + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h new file mode 100644 index 0000000000000..7f02b6c95d10c --- /dev/null +++ b/include/kcl/kcl_drm_prime.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __KCL_DRM_PRIME_H__ +#define __KCL_DRM_PRIME_H__ + +#include +#include +#include + +#ifndef HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY +static inline +int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, + int max_entries) +{ + return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); + +} +#endif +#endif From 038f2f7aab5deaa4a8de1a45bd5d2a13835fb631 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 3 Feb 2021 18:07:54 +0800 Subject: [PATCH 0549/2070] drm/amdkcl: test drm_prime_pages_to_sg() Test whether drm_prime_pages_to_sg() takes 3 arguments Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 | 21 ++++++++ .../drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 | 14 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_drm_prime.h | 49 +++++++++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 create mode 100644 include/kcl/backport/kcl_drm_prime.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c4bd6b13ad993..aa3323b6243e7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 new file mode 100644 index 0000000000000..b33ceb61643ce --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit a4574f63edc6f76fb46dcd65d3eb4d5a8e23ba38 +dnl # mm/memremap_pages: convert to 'struct range' +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dev_pagemap *pm = NULL; + pm->range.start = 0; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_RANGE, 1, + [there is 'range' field within dev_pagemap structure]) + ]) + ]) +]) +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP], [ + AC_AMDGPU_DEV_PAGEMAP_RANGE +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 new file mode 100644 index 0000000000000..5854aa864fd2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e +dnl # drm: allow limiting the scatter list size. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 441a5a67a743d..a636bbf7b39fe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_DEV_PAGEMAP AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED @@ -98,6 +99,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY + AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h new file mode 100644 index 0000000000000..1c3895f60823d --- /dev/null +++ b/include/kcl/backport/kcl_drm_prime.h @@ -0,0 +1,49 @@ +/* + * Copyright © 2012 Red Hat + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + * Rob Clark + * + */ + +// Copied from include/drm/drm_prime.h +#ifndef _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ +#define _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ + +#include + +#ifndef HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS +static inline +struct sg_table *_kcl_drm_prime_pages_to_sg(struct drm_device *dev, + struct page **pages, unsigned int nr_pages) +{ + pr_warn_once("legacy kernel with drm_prime_pages_to_sg() ignore segment size limits, which is buggy\n"); + return drm_prime_pages_to_sg(pages, nr_pages); +} +#define drm_prime_pages_to_sg _kcl_drm_prime_pages_to_sg +#endif + +#endif From a470bfef6b9253f3b29c1553ad369533f61ab53e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 3 Feb 2021 16:33:18 +0800 Subject: [PATCH 0550/2070] drm/amdkcl: test amd_iommu_invalidate_ctx protocol Test whether type of pasid is u32 Reviewed-by: Guchun Chen Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 18 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 new file mode 100644 index 0000000000000..ff2bf9c8949ad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860 +dnl # drm, iommu: Change type of pasid to u32 +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void (*f)(struct pci_dev *pdev, u32 pasid); + amd_iommu_invalidate_ctx callback = f; + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, + [amd_iommu_invalidate_ctx take arg type of pasid as u32]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a636bbf7b39fe..c07b54119c1f8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE From a7be79301d19f4576540dac907ff6f0a52a5484c Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 20:20:27 +0800 Subject: [PATCH 0551/2070] drm/amdkcl: check the callback prototype of atomic_best_encoder This is caused by "drm: Pass the full state to connectors atomic functions" v5.10-rc3-1075-geca22edb37d2 Signed-off-by: Shiwu Zhang --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index f6ff49e6377da..80f6af388905a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -529,10 +529,15 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) static struct drm_encoder * dm_mst_atomic_best_encoder(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); +#else + struct drm_connector_state *connector_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index 148d0cc472804..c31a4f9b86b56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -16,3 +16,27 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ ]) ]) ]) + +dnl # +dnl # v5.10-rc3-1075-geca22edb37d2 +dnl # drm: Pass the full state to connectors atomic functions +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_best_encoder(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE, 1, + [atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c07b54119c1f8..2858adb49a963 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -84,7 +84,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC - AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From 725bd48786e205887c8f648ae9a40553cae9d008 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 20:54:21 +0800 Subject: [PATCH 0552/2070] drm/amdkcl: check the callback prototype of atomic_check in drm_crtc_helper_funcs Signed-off-by: Shiwu Zhang Signed-off-by: Ma Jun Change-Id: Ie6eb721917f480b955f6187de194d4426ae0392b --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 5 +++++ .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 6153b0b2f9c31..bb83aa44aa900 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -652,10 +652,15 @@ static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, } static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, +#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); +#else + struct drm_crtc_state *crtc_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 new file mode 100644 index 0000000000000..7f43ce7a2f5e2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2858adb49a963..2c42ece57e684 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From 193462fbd19266ee80021825a39148e4ae1d5804 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 24 Feb 2021 16:09:01 +0800 Subject: [PATCH 0553/2070] drm/amdkcl: wrapper the code for hmm dkms support and monitor_range related code under DISPLAY_INFO_MONITOR_RANGE This is caused by "remove unused variable from struct amdgpu_bo" and "Add Freesync HDMI support to DM" v5.9-rc5-2435-g3e6c7e19c2a5 and v5.9-rc5-2419-g1556b0c185e3 Signed-off-by: Shiwu Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 4 ++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 7a3a809063658..c72f4ac77c9f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -113,6 +113,10 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct amdgpu_mn *mn; +#endif + #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4a4d8e53f4014..37a5ef074f938 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13388,8 +13388,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } From 568145ab1656c023d9b09edfcb6a20c2e982b7c2 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 22 Feb 2021 18:36:34 +0800 Subject: [PATCH 0554/2070] drm/amdkcl: do not use drm middle layer for dgma debugfs This is a squash of: drm/amdkcl: simplify kcl handling of drm_mm_print() Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui drm/amdkcl: restore prev handling of drm_debug_printer() Signed-off-by: Flora Cui This is caused by "do not use drm middle layer for debugfs" v5.9-rc5-2401-g80453ffefd61 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ie651234201ff972b9a49dc77d592bed663a08987 --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 4 --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 14 +++++--- drivers/gpu/drm/amd/backport/backport.h | 1 - .../amd/backport/include/kcl/kcl_amdgpu_ttm.h | 26 --------------- .../gpu/drm/amd/dkms/m4/drm-debug-printer.m4 | 16 --------- drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 | 15 --------- drivers/gpu/drm/amd/dkms/m4/drm_print.m4 | 21 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/drm/ttm/ttm_resource.h | 4 --- include/kcl/kcl_drm_print.h | 33 +++++++++++++------ 13 files changed, 61 insertions(+), 93 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 5362a871dd5b4..9410a01094ceb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1799,12 +1799,14 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib); DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark, "%lld\n"); +#endif static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, struct dma_fence **fences) @@ -2107,16 +2109,18 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) amdgpu_fw_attestation_debugfs_init(adev); amdgpu_psp_debugfs_init(adev); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_evict_vram", 0400, root, adev, &amdgpu_evict_vram_fops); debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev, &amdgpu_evict_gtt_fops); + debugfs_create_file("amdgpu_benchmark", 0200, root, adev, + &amdgpu_benchmark_fops); +#endif debugfs_create_file("amdgpu_test_ib", 0400, root, adev, &amdgpu_debugfs_test_ib_fops); debugfs_create_file("amdgpu_vm_info", 0444, root, adev, &amdgpu_debugfs_vm_info_fops); - debugfs_create_file("amdgpu_benchmark", 0200, root, adev, - &amdgpu_benchmark_fops); adev->debugfs_vbios_blob.data = adev->bios; adev->debugfs_vbios_blob.size = adev->bios_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index bdfac8d7f8afa..9b0bcf6aca445 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -295,20 +295,12 @@ static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, -#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) -#else - const char *prefix) -#endif { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); spin_lock(&mgr->lock); -#if defined(HAVE_DRM_MM_PRINT) drm_mm_print(&mgr->mm, printer); -#else - drm_mm_debug_table(&mgr->mm, prefix); -#endif spin_unlock(&mgr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a36236a61626a..d4a02ae1d19af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -3258,7 +3258,6 @@ DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); - /* * amdgpu_ttm_vram_read - Linear read access to VRAM * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 71a024217a8b9..9d934c07fa6b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -874,11 +874,7 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, -#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) -#else - const char *prefix) -#endif { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct drm_buddy *mm = &mgr->mm; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 3d690609edb8f..0c47443e0f189 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -38,15 +38,21 @@ void drm_printf(struct drm_printer *p, const char *f, ...) va_end(args); } EXPORT_SYMBOL(drm_printf); + +void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf) +{ + seq_printf(p->arg, "%pV", vaf); +} +EXPORT_SYMBOL(__drm_printfn_seq_file); #endif -#if !defined(HAVE_DRM_DEBUG_PRINTER) +#if !defined(HAVE_DRM_PRINTER_PREFIX) void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) { -#if !defined(HAVE_DRM_DRM_PRINT_H) - pr_debug("%s %pV", p->prefix, vaf); +#ifndef HAVE_DRM_DRM_PRINT_H + printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", p->prefix, vaf); #else - pr_debug("%s %pV", "no prefix < 4.11", vaf); + printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", "no prefix", vaf); #endif } EXPORT_SYMBOL(__drm_printfn_debug); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index aa3323b6243e7..a0ef73d9c2677 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -56,7 +56,6 @@ #include #include #include -#include "kcl/kcl_amdgpu_ttm.h" #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h deleted file mode 100644 index 1c4be1340422f..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H -#define AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H -#include -#include -#include -#include "amdgpu.h" -#include "amdgpu_ttm.h" - -#if !defined(HAVE_DRM_MM_PRINT) -extern struct drm_mm *kcl_ttm_range_res_manager_to_drm_mm(struct ttm_resource_manager *man); - -static inline struct drm_mm *kcl_ttm_get_drm_mm_by_mem_type(struct amdgpu_device *adev, unsigned char ttm_pl) -{ - if (ttm_pl == TTM_PL_TT) { - return &(adev->mman.gtt_mgr.mm); - } else if (ttm_pl == TTM_PL_VRAM) { - return &(adev->mman.vram_mgr.mm); - } else { - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); - return kcl_ttm_range_res_manager_to_drm_mm(man); - } -} -#endif - -#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 deleted file mode 100644 index 3fdcea368bf1e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 3d387d923c18afbacef8f14ccaa2ace2a297df74 -dnl # drm/printer: add debug printer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEBUG_PRINTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_debug_printer(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DEBUG_PRINTER, 1, - [drm_debug_printer() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 deleted file mode 100644 index 2d1d63b131ce7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 +++ /dev/null @@ -1,15 +0,0 @@ -dnl # -dnl # commit b5c3714fe8789745521d8351d75049b9c6a0d26b -dnl # drm/mm: Convert to drm_printer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MM_PRINT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_mm_print(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_MM_PRINT, 1, [drm_mm_print() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 new file mode 100644 index 0000000000000..3c4a306d53cd3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v4.9-rc2-477-gd8187177b0b1 drm: add helper for printing to log or seq_file +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test $HAVE_DRM_DRM_PRINT_H], [ + dnl # + dnl # v4.9-rc8-1738-gb5c3714fe878 drm/mm: Convert to drm_printer + dnl # v4.9-rc8-1737-g3d387d923c18 drm/printer: add debug printer + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_printer *p = NULL; + p->prefix = NULL; + ], [ + AC_DEFINE(HAVE_DRM_PRINTER_PREFIX, 1, [drm_printer->prefix is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2c42ece57e684..f3467a8d97dc6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,7 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT - AC_AMDGPU_DRM_MM_PRINT + AC_AMDGPU_DRM_PRINTER AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE @@ -71,7 +71,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM - AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 5733a161e8c79..05dbaead88ae7 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -178,12 +178,8 @@ struct ttm_resource_manager_func { * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ -#if defined(HAVE_DRM_MM_PRINT) void (*debug)(struct ttm_resource_manager *man, struct drm_printer *printer); -#else - void (*debug)(struct ttm_resource_manager *man, const char *prefix); -#endif }; /** diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 3ead0ab2b367f..10ba443b49303 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -29,7 +29,7 @@ #include #if !defined(HAVE_DRM_DRM_PRINT_H) -/* Copied from include/drm/drm_print.h */ +/* Copied from d8187177b0b1 include/drm/drm_print.h */ struct drm_printer { void (*printfn)(struct drm_printer *p, struct va_format *vaf); void *arg; @@ -37,28 +37,41 @@ struct drm_printer { }; void drm_printf(struct drm_printer *p, const char *f, ...); +void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf); +static inline struct drm_printer drm_seq_file_printer(struct seq_file *f) +{ + struct drm_printer p = { + .printfn = __drm_printfn_seq_file, + .arg = f, + }; + return p; +} #endif -/** - * drm_debug_printer - construct a &drm_printer that outputs to pr_debug() - * @prefix: debug output prefix - * - * RETURNS: - * The &drm_printer object - */ -#if !defined(HAVE_DRM_DEBUG_PRINTER) +/* Copied from 3d387d923c18 include/drm/drm_print.h */ +#if !defined(HAVE_DRM_PRINTER_PREFIX) extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); static inline struct drm_printer drm_debug_printer(const char *prefix) { struct drm_printer p = { .printfn = __drm_printfn_debug, -#if !defined(HAVE_DRM_DRM_PRINT_H) +#ifndef HAVE_DRM_DRM_PRINT_H .prefix = prefix #endif }; return p; } + +static inline +void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) +{ +#ifndef HAVE_DRM_DRM_PRINT_H + drm_mm_debug_table(mm, p->prefix); +#else + drm_mm_debug_table(mm, "no prefix"); +#endif +} #endif #ifndef _DRM_PRINTK From 700c35c66b6ea593e72a0d857cafc1835865b06f Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 21 Jan 2021 20:25:47 +0800 Subject: [PATCH 0555/2070] drm/amdkcl: check whether drm_display_info have monitor_range This is caused by "Report Freesync to vrr_range debugfs entry in DRM" v5.9-rc5-2241-ga5df71e584c0 squrash: 1aaf7981408b231b5125a59cdd198824af316025 drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE Signed-off-by: Bob Zhou Signed-off-by: Shiwu Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 37a5ef074f938..2ecd1a0c10604 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13343,6 +13343,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || sink->sink_signal == SIGNAL_TYPE_EDP)) { +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE if (amdgpu_dm_connector->dc_link && amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; @@ -13350,7 +13351,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; } - +#endif parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (vsdb_info.replay_mode) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 new file mode 100644 index 0000000000000..61eef3b454776 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit v5.6-rc2-1062-ga1d11d1efe4d +dnl # drm/edid: Add function to parse EDID descriptors for monitor range +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->monitor_range.min_vfreq=0; + info->monitor_range.max_vfreq=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE, 1, + [struct drm_display_info has monitor_range member]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f3467a8d97dc6..6e43cfae051a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -106,6 +106,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS + AC_AMDGPU_DRM_DISPLAY_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From a305e14f088e952f646f84e3f1cd01e5c95bbea3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 1 Mar 2021 15:43:59 +0800 Subject: [PATCH 0556/2070] drm/amdkcl: adapt for drm_mm_insert_node prototype change This is caused "drm/amdgpu: reserve backup pages for bad page retirment" v5.9-rc5-2461-g3a5cce0da738 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_drm_mm_backport.h | 23 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_mm_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a0ef73d9c2677..e9733f176c049 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -56,6 +56,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h new file mode 100644 index 0000000000000..8c20d53ed7f4f --- /dev/null +++ b/include/kcl/backport/kcl_drm_mm_backport.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_MM_H +#define AMDKCL_DRM_MM_H + +/** + * interface change in mainline kernel 4.10 + * v4.10-rc5-1060-g4e64e5539d15 drm: Improve drm_mm search (and fix topdown allocation) + * with rbtrees + */ + +#include + +#ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS +static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, + struct drm_mm_node *node, + u64 size) +{ + return drm_mm_insert_node(mm, node, size, 0, DRM_MM_SEARCH_DEFAULT); +} +#define drm_mm_insert_node _kcl_drm_mm_insert_node +#endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ + +#endif /* AMDKCL_DRM_MM_H */ From 621b542467f21f9dc5ecc25fd17d2117269cd9dd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 2 Mar 2021 15:22:04 +0800 Subject: [PATCH 0557/2070] drm/amdkcl: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amdgpu: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE" v5.9-rc5-2487-gd7ce9ec795fb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 9410a01094ceb..51d370d6e46d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2020,11 +2020,13 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) return ret; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, amdgpu_debugfs_ib_preempt, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, amdgpu_debugfs_sclk_set, "%llu\n"); +#endif int amdgpu_debugfs_init(struct amdgpu_device *adev) { @@ -2035,6 +2037,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) if (!debugfs_initialized()) return 0; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_x32("amdgpu_smu_debug", 0600, root, &adev->pm.smu_debug_mask); @@ -2053,6 +2056,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) "unable to create amdgpu_set_sclk debugsfs file\n"); return PTR_ERR(ent); } +#endif /* Register debugfs entries for amdgpu_ttm */ amdgpu_ttm_debugfs_init(adev); From e491efa3c0ad5d3f20afd105dcacb2a0347b64a8 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 5 Jan 2021 14:45:43 +0800 Subject: [PATCH 0558/2070] drm/amdkcl: add pixel format definitions for backport This is caused by "Check plane scaling against format specific hw plane caps" v5.9-rc5-2058-g9302b36fd9a0 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: I1170bb9d453ab4b4536b1a2cf2cc4a0144a67490 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- .../gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 2 -- .../gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 -- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index cb35f9ce85a3e..93a9011fc6258 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -805,10 +805,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; -#ifdef DRM_FORMAT_P010 + if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; -#endif + if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 7ff9b450b3713..476780a5450fb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -514,9 +514,7 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, -#ifdef DRM_FORMAT_P010 .p010 = false -#endif }, .max_upscale_factor = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 294cff6191ed2..107612595db60 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -589,9 +589,7 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, -#ifdef DRM_FORMAT_P010 .p010 = true -#endif }, .max_upscale_factor = { From 20f787f78aba588f97b603d985cdf53afb7e5b58 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 22 Jan 2021 13:04:18 +0800 Subject: [PATCH 0559/2070] drm/amdkcl: fake the PCIe 5.0 speed enum by using macro This is caused by "Add pcie gen5 support in pcie capability" v5.9-rc5-2265-g14769c60e22e Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_pci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index fcaace33f6ee2..e6bbb2a4924fa 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -64,9 +64,9 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #endif -#ifndef PCIE_SPEED_16_0GT #define PCIE_SPEED_16_0GT 0x17 -#endif +#define PCIE_SPEED_32_0GT 0x18 + #ifndef PCI_EXP_LNKCAP2_SLS_16_0GB #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #endif From 7de0e4f887c6b088f3a255c27410ae4f93020d44 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 21 Dec 2020 13:50:14 +0800 Subject: [PATCH 0560/2070] drm/amdkcl: test drm_dp_mst_topology_cbs->destroy_connector drm_dp_mst_topology_cbs->destroy_connector() is a must before commit d29333cf5cd7 ("drm/dp_mst: Remove PDT teardown in drm_dp_destroy_port() and refactor"). otherwise kernel NULL pointer dereference jump out. Reviewed-by: Guchun Chen Reviewed-by: Aurabindo Pillai Signed-off-by: Flora Cui --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 37 +++++++++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 17 +++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 80f6af388905a..3db84128cfdef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -165,11 +165,13 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR if (aconnector->dc_sink) { dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); dc_sink_release(aconnector->dc_sink); } +#endif drm_edid_free(aconnector->drm_edid); @@ -867,6 +869,38 @@ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR +static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_connector *connector) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + + DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", + aconnector, connector->base.id, aconnector->mst_port); + + if (aconnector->dc_sink) { + amdgpu_dm_update_freesync_caps(connector, NULL); + dc_link_remove_remote_sink(aconnector->dc_link, + aconnector->dc_sink); + dc_sink_release(aconnector->dc_sink); + aconnector->dc_sink = NULL; + mutex_lock(&mgr->lock); + if (!mgr->mst_state) + aconnector->dc_link->cur_link_settings.lane_count = 0; + mutex_unlock(&mgr->lock); + } + drm_connector_unregister(connector); +#ifdef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS + if (adev->mode_info.rfbdev) + drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); +#endif + drm_connector_put(connector); +} +#endif + #if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) { @@ -894,6 +928,9 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + .destroy_connector = dm_dp_destroy_mst_connector, +#endif #if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) .hotplug = dm_dp_mst_hotplug, #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 5847b52020f9f..f08316600fcbd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -34,9 +34,26 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ ]) ]) +dnl # +dnl # commit v5.6-rc5-1703-g72dc0f515913 +dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->destroy_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->destroy_connector is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR ]) ]) From d0f5ff0dcbc901ab73196fcff394ce0fc897f3fb Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 20 Jan 2021 14:29:34 +0800 Subject: [PATCH 0561/2070] drm/amdkcl: Work around mmu_notifier_put issue on RHEL 8.3 The DRM backport from kernel 5.6 includes some MMU notifier changes that cause problems with the mmu_notifier_put function. The free_notifier never gets called. This leads to a leak of kfd_process structures and their doorbells. Work around this by falling back to the old method of releasing the MMU notifier and destryoing the process structure. Signed-off-by: Felix Kuehling Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_mn.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_mn.h b/include/kcl/kcl_mn.h index 02e80c3b4e386..f828b5dedec49 100644 --- a/include/kcl/kcl_mn.h +++ b/include/kcl/kcl_mn.h @@ -4,6 +4,12 @@ #include +/* mmu_notifier_put in the RH DRM backport from 5.6 is broken */ +#if DRM_VER == 5 && DRM_PATCH == 6 && \ + LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +#undef HAVE_MMU_NOTIFIER_PUT +#endif + /* Copied from v3.16-6588-gb972216e27d1 include/linux/mmu_notifier.h */ #if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ !defined(HAVE_MMU_NOTIFIER_PUT) From af297cf6c60ac425523cf8a05ec100a8fee72b0c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 16:22:49 +0800 Subject: [PATCH 0562/2070] drm/amdkcl: fake drm_gem_ttm_{vmap,vunmap} Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 16 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 + drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_drm_gem_ttm_helper.h | 37 +++++++++++++++++ .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 ++++ .../drm/amd/dkms/m4/drm_gem_object_funcs.m4 | 28 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_gem_ttm_helper.h | 9 +++++ 12 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 create mode 100644 include/kcl/header/drm/drm_gem_ttm_helper.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0077b3fcb8b6d..c6214704d59dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3163,6 +3163,11 @@ static const struct drm_driver amdgpu_kms_driver = { #endif .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_free_object_unlocked = amdgpu_gem_object_free, + .gem_open_object = amdgpu_gem_object_open, + .gem_close_object = amdgpu_gem_object_close, +#endif .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, @@ -3173,6 +3178,10 @@ static const struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_export = amdgpu_gem_prime_export, +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, #else @@ -3189,6 +3198,11 @@ static const struct drm_driver amdgpu_kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_vmap = drm_gem_ttm_vmap, + .gem_prime_vunmap = drm_gem_ttm_vunmap, +#endif + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f60e46a5dfa68..acca2cdc77e90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -112,6 +112,9 @@ amdgpu_gem_update_timeline_node(struct drm_file *filp, return 0; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#else static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) { struct ttm_buffer_object *bo = vmf->vma->vm_private_data; @@ -153,6 +156,7 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { }; static void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#endif { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); struct amdgpu_device *adev = amdgpu_ttm_adev(aobj->tbo.bdev); @@ -261,8 +265,13 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */ +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); @@ -348,8 +357,13 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, return r; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -423,6 +437,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, @@ -433,6 +448,7 @@ const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; +#endif /* * GEM ioctls. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index cd073b3a316da..51dbaec84db28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -33,7 +33,9 @@ #define AMDGPU_GEM_DOMAIN_MAX 0x3 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK extern const struct drm_gem_object_funcs amdgpu_gem_object_funcs; +#endif unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index c346860b63758..b09ed112c96af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -685,7 +685,9 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bo == NULL) return -ENOMEM; drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK bo->tbo.base.funcs = &amdgpu_gem_object_funcs; +#endif bo->vm_bo = NULL; bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : bp->domain; diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 8880468d474a6..115fc89f8204f 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := kcl_drm_drv.o +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e9733f176c049..faa446bfc30fa 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -60,6 +60,7 @@ #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..10d002f55b191 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copied from include/drm/drm_gem_ttm_helper.h */ + +#ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H +#define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H + +#include + +#ifndef HAVE_DRM_GEM_TTM_VMAP +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr); + +void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj); + +static inline +void drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + _kcl_drm_gem_ttm_vunmap(gem, vaddr); +} + +static inline +void *drm_gem_ttm_vmap(struct drm_gem_object *obj) +{ + return _kcl_drm_gem_ttm_vmap(obj); +} +#endif + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *obj); +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv); +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c new file mode 100644 index 0000000000000..ef1c82463f8e0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#include +#include +#include +#include +#include +#include + +#ifndef drm_gem_ttm_of_gem +#define drm_gem_ttm_of_gem(gem_obj) \ + container_of(gem_obj, struct ttm_buffer_object, base) +#endif + +#ifndef HAVE_DRM_GEM_TTM_VMAP +void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); + struct dma_buf_map map; + + ttm_bo_vmap(bo, &map); + return map.vaddr; +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_vmap); + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct dma_buf_map map; + + map.vaddr = vaddr; + map.is_iomem = bo->mem.bus.is_iomem; + + ttm_bo_vunmap(bo, &map); +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 16ebd93fc3ea8..1f21aec4ff2ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -39,6 +39,13 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + dnl # + dnl # v5.3-rc1-623-gff540b76f14a + dnl # drm/ttm: add drm gem ttm helpers, + dnl # starting with drm_gem_ttm_print_info() + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) + dnl # dnl # v5.12-rc3-330-g2916059147ea dnl # drm/aperture: Add infrastructure for aperture ownership diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 new file mode 100644 index 0000000000000..353a678db52d7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # commit v4.9-rc8-1739-g6d1b81d8e25d +dnl # drm: add crtc helper drm_crtc_from_index() +dnl # commit v5.9-rc5-1077-gd693def4fd1c +dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_TTM_VMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_ttm_vmap], [drivers/gpu/drm/drm_gem_ttm_helper.c], [ + AC_DEFINE(HAVE_DRM_GEM_TTM_VMAP, 1, [drm_gem_ttm_vmap() is available]) + ],[ + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6e43cfae051a0..005e3b320574f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..1f4610148dd07 --- /dev/null +++ b/include/kcl/header/drm/drm_gem_ttm_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_VBLANK_H_H_ +#define _KCL_HEADER_DRM_VBLANK_H_H_ + +#ifdef HAVE_DRM_DRM_DRM_GEM_TTM_HELPER_H +#include_next +#endif + +#endif From afaec3cc0e297f6bc244f53230b0b3bf18fc0160 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 10:57:32 +0800 Subject: [PATCH 0563/2070] drm/amdkcl: refactor test for drm_driver_feature Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 59 ++++++++++--------- 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index 0970897b2338a..d10e0fcde3942 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -8,16 +8,15 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm: introduce a capability flag for syncobj timeline support dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_SYNCOBJ_TIMELINE; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ - drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) - ]) - ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_SYNCOBJ_TIMELINE; + ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) ]) @@ -28,15 +27,17 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm/irq: Ditch DRIVER_IRQ_SHARED dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_IRQ_SHARED; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ - drm_driver_feature DRIVER_IRQ_SHARED is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) ]) ]) @@ -45,15 +46,17 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm/prime: Actually remove DRIVER_PRIME everywhere dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_PRIME; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ - drm_driver_feature DRIVER_PRIME is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) ]) ]) ]) From 72b1afb27eb46816fa812cab17ae99e665a49edc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 11:20:01 +0800 Subject: [PATCH 0564/2070] drm/amdkcl: refactor test for drm_device Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 7016ff6694c88..7ea0061caa47e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -3,14 +3,16 @@ dnl # commit v4.19-rc1-194-g18ace11f87e6 dnl # drm: Introduce per-device driver_features dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_device *ddev = NULL; - ddev->driver_features = 0; - ],[ - AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, - [dev_device->driver_features is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->driver_features = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, + [dev_device->driver_features is available]) + ]) ]) ]) @@ -19,6 +21,7 @@ dnl # commit v5.5-rc2-1419-g7e13ad896484 dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include ],[ @@ -28,11 +31,10 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, [drm_device->open_count is int]) ]) + ]) ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES - AC_AMDGPU_DRM_DEVICE_OPEN_COUNT - ]) + AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) From 0c63aad4c7bab32adc72e3ddb4e824107a68cf1d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 11:34:46 +0800 Subject: [PATCH 0565/2070] drm/amdkcl: refactor test for drm/drm_audio_component.h Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ------------------ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ---- .../amd/dkms/m4/drm-audio-component-header.m4 | 9 --------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2ecd1a0c10604..1a8acd142611d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -78,9 +78,7 @@ #include #include -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include -#endif #include #include @@ -96,9 +94,7 @@ #include #include #include -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include -#endif #include #ifdef CONFIG_DRM_AMD_DC_HDCP #include @@ -1112,7 +1108,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) @@ -1250,7 +1245,6 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) pin, -1); } } -#endif static int dm_dmub_hw_init(struct amdgpu_device *adev) { @@ -1903,9 +1897,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_init(&adev->dm.audio_lock); -#endif if (amdgpu_dm_irq_init(adev)) { drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); @@ -2330,9 +2322,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_destroy(&adev->dm.audio_lock); -#endif mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); } @@ -4913,14 +4903,12 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) } #endif -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) r = amdgpu_dm_audio_init(adev); if (r) { dc_state_release(state->context); kfree(state); return r; } -#endif return 0; } @@ -8958,9 +8946,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) aconnector->audio_inst = -1; -#endif aconnector->pack_sdp_v1_3 = false; aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); @@ -10306,7 +10292,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, kfree(bundle); } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { @@ -10387,7 +10372,6 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev, amdgpu_dm_audio_eld_notify(adev, inst); } } -#endif /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC @@ -11130,10 +11114,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->wb_enabled = true; } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); -#endif /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index baaef4dce3c4d..5998b6f055f10 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -489,7 +489,6 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /** * @audio_lock: * @@ -511,7 +510,6 @@ struct amdgpu_display_manager { * successfully, false otherwise. */ bool audio_registered; -#endif /** * @irq_handler_list_low_tab: @@ -842,10 +840,8 @@ struct amdgpu_dm_connector { */ int max_vfreq ; -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Audio instance - protected by audio_lock. */ int audio_inst; -#endif struct mutex hpd_lock; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 deleted file mode 100644 index 520d72bebcb5c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 +++ /dev/null @@ -1,9 +0,0 @@ -AC_DEFUN([AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_audio_component.h], [ - AC_DEFINE(HAVE_DRM_AUDIO_COMPONENT_HEADER, 1, - [whether drm/drm_audio_component.h is defined]) - ]) - ]) -]) - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 005e3b320574f..64574f278983a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,7 +33,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_DMA_FENCE_HEADERS - AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION From 04d5dd517b1b058c55213fcc9c1a0fc0e221f723 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 11:41:06 +0800 Subject: [PATCH 0566/2070] drm/amdkcl: refactor test for drm_debug_enabled Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 0baf031bd2e3d..0250d30115d15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -3,17 +3,15 @@ dnl # commit v5.3-rc1-708-gf0a8f533adc2 dnl # drm/print: add drm_debug_enabled() dnl # AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_print.h], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - drm_debug_enabled(0); - ],[ - AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, - 1, - [drm_debug_enabled() is available]) - ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) ]) ]) ]) From 6d1b1d2a70e4863730e399ed9701276fa77d1109 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 19 Feb 2021 14:21:21 +0800 Subject: [PATCH 0567/2070] drm/amdkcl: simplify test for drm_connector_xxx the prototype change is introduced in a series of patch. no need to test for each api. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- .../amd/dkms/m4/drm-connector-attach-encoder.m4 | 16 ---------------- .../dkms/m4/drm-connector-set-path-property.m4 | 16 ---------------- .../m4/drm-connector-update-edid-property.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 --- include/kcl/kcl_drm_connector.h | 12 ------------ 5 files changed, 63 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 deleted file mode 100644 index 9b4bd0e561b64..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit cde4c44d8769c1be16074c097592c46c7d64092b -dnl # drm: drop _mode_ from drm_mode_connector_attach_encode -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_attach_encoder(NULL, NULL); - ],[drm_connector_attach_encoder],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_ENCODER, 1, - [drm_connector_attach_encoder() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 deleted file mode 100644 index f872d0db19a2e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 97e14fbeb53fe060c5f6a7a07e37fd24c087ed0c -dnl # drm: drop _mode_ from remaining connector functions -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_set_path_property(NULL, NULL); - ],[drm_connector_set_path_property],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY, 1, - [drm_connector_set_path_property() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 deleted file mode 100644 index eade2ed63d298..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit c555f02371c338b06752577aebf738dbdb6907bd -dnl # drm: drop _mode_ from update_edit_property() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_update_edid_property(NULL, NULL); - ],[drm_connector_update_edid_property],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY, 1, - [drm_connector_update_edid_property() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 64574f278983a..67ff9be97051f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -49,9 +49,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS - AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY - AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER - AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 76362de0c45ed..d0548c78ac046 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -34,18 +34,6 @@ #define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY #endif -#ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY -#define drm_connector_update_edid_property drm_mode_connector_update_edid_property -#endif - -#ifndef HAVE_DRM_CONNECTOR_ATTACH_ENCODER -#define drm_connector_attach_encoder drm_mode_connector_attach_encoder -#endif - -#ifndef HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY -#define drm_connector_set_path_property drm_mode_connector_set_path_property -#endif - /** * drm_connector_for_each_possible_encoder - iterate connector's possible encoders * @connector: &struct drm_connector pointer From f769437357483c800eeeb824fc15ba31c55ce5a2 Mon Sep 17 00:00:00 2001 From: xinhui pan Date: Wed, 18 Mar 2020 16:50:45 +0800 Subject: [PATCH 0568/2070] drm/amdgpu: fix OOM panic and deadlock In mmu release, we schedule a work to free amn. however there is race between exit_mmap and oom_reap_task_mm. exit_mmap -> mmu_notifier_release oom_reap_task_mm -> __oom_reap_task_mm -> mmu_notifier_invalidate_range_start_nonblock So the amn might have been freed. sync rcu in destroy to wait for ongoing range invalidate. calltrace: [ 4407.908455] BUG: kernel NULL pointer dereference, address: 0000000000000050 [ 4407.915591] #PF: supervisor read access in kernel mode [ 4407.920827] #PF: error_code(0x0000) - not-present page [ 4407.926079] PGD 0 P4D 0 [ 4407.928662] Oops: 0000 [#1] SMP PTI [ 4407.932216] CPU: 3 PID: 55 Comm: oom_reaper Tainted: G W O 5.4.0-rc7+ #1 [ 4407.940206] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 [ 4407.949080] RIP: 0010:mark_lock+0xc9/0x540 [ 4407.953282] Code: 31 c0 eb 12 48 8d 14 80 48 8d 04 50 48 c1 e0 04 48 05 00 dd 01 9c 41 bc 01 00 00 00 89 d9 41 bf 01 00 00 00 41 d3 e4 4d 63 e4 <4c> 85 60 50 0f 85 50 ff ff ff e8 18 bb ff ff 85 c0 0f 84 40 ff ff [ 4407.972385] RSP: 0018:ffffab4440253ab0 EFLAGS: 00010006 [ 4407.977723] RAX: 0000000000000000 RBX: 0000000000000008 RCX: 0000000000000008 [ 4407.984977] RDX: ffff9df1d9fd8040 RSI: 0000000000000001 RDI: ffffffff9a318d0a [ 4407.992222] RBP: ffffab4440253af0 R08: 0000000000000000 R09: 000000000003b540 [ 4407.999493] R10: 0000000000000000 R11: 0000000000000037 R12: 0000000000000100 [ 4408.006774] R13: ffff9df1d9fd8040 R14: ffff9df1d9fd8c88 R15: 0000000000000001 [ 4408.014062] FS: 0000000000000000(0000) GS:ffff9df1de180000(0000) knlGS:0000000000000000 [ 4408.022295] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4408.028154] CR2: 0000000000000050 CR3: 0000000393410001 CR4: 00000000003606e0 [ 4408.035427] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 4408.042689] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 4408.049968] Call Trace: [ 4408.052467] __lock_acquire+0x261/0x1600 [ 4408.056486] ? __lock_acquire+0x43a/0x1600 [ 4408.060628] ? __lock_acquire+0x43a/0x1600 [ 4408.064816] lock_acquire+0xb8/0x1c0 [ 4408.068482] ? rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.073509] _raw_spin_lock_irq+0x3b/0x50 [ 4408.077624] ? rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.082582] rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.087401] ? finish_task_switch+0x63/0x230 [ 4408.091759] ? __schedule+0x2b3/0x860 [ 4408.095487] down_read_non_owner+0x86/0x160 [ 4408.099767] ? down_read_non_owner+0x86/0x160 [ 4408.104295] amdgpu_mn_read_lock+0x9f/0xb0 [amdgpu] [ 4408.109364] amdgpu_mn_invalidate_range_start_gfx+0x3f/0x1e0 [amdgpu] [ 4408.115941] __mmu_notifier_invalidate_range_start+0x9e/0x190 [ 4408.121816] ? __oom_reap_task_mm+0x6d/0x220 [ 4408.126166] __oom_reap_task_mm+0x1b5/0x220 [ 4408.130450] oom_reaper+0x4d0/0x650 [ 4408.133991] ? __kthread_parkme+0x2f/0x90 [ 4408.138083] ? finish_wait+0x90/0x90 [ 4408.141715] kthread+0x12c/0x150 [ 4408.145043] ? __oom_reap_task_mm+0x220/0x220 [ 4408.149461] ? kthread_park+0x90/0x90 [ 4408.153208] ret_from_fork+0x3a/0x50 There is another deadlock. calltrace: [ 1635.072660] BUG: sleeping function called from invalid context at ../kernel/locking/rwsem.c:1621 [ 1635.081870] in_atomic(): 0, irqs_disabled(): 0, non_block: 1, pid: 55, name: oom_reaper [ 1635.090106] 4 locks held by oom_reaper/55: [ 1635.091485] init_user_pages: Failed to get user pages: -512 [ 1635.094302] #0: ffff9ca48e94b5d8 (&mm->mmap_sem#2){++++}, at: oom_reaper+0xa4/0x650 [ 1635.108116] #1: ffffffff82750fc0 (mmu_notifier_invalidate_range_start){+.+.}, at: __oom_reap_task_mm+0x6d/0x220 [ 1635.118558] #2: ffffffff827637f0 (srcu){....}, at: __mmu_notifier_invalidate_range_start+0x5/0x190 [ 1635.127879] #3: ffff9ca4f7c605f0 (&amn->read_lock){+.+.}, at: amdgpu_mn_read_lock+0x75/0xb0 [amdgpu] [ 1635.137614] CPU: 3 PID: 55 Comm: oom_reaper Tainted: G W O 5.4.0-rc7+ #1 [ 1635.145787] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 [ 1635.154744] Call Trace: [ 1635.157264] dump_stack+0x98/0xd5 [ 1635.160688] ___might_sleep+0x175/0x260 [ 1635.164675] __might_sleep+0x4a/0x80 [ 1635.168340] down_read_non_owner+0x20/0x160 [ 1635.172748] amdgpu_mn_read_lock+0x9f/0xb0 [amdgpu] [ 1635.177884] amdgpu_mn_invalidate_range_start_hsa+0x3f/0x180 [amdgpu] [ 1635.184477] __mmu_notifier_invalidate_range_start+0x9e/0x190 [ 1635.190337] ? __oom_reap_task_mm+0x6d/0x220 [ 1635.194725] __oom_reap_task_mm+0x1b5/0x220 [ 1635.199069] oom_reaper+0x4d0/0x650 [ 1635.202611] ? __kthread_parkme+0x2f/0x90 [ 1635.206740] ? finish_wait+0x90/0x90 [ 1635.210425] kthread+0x12c/0x150 [ 1635.213714] ? __oom_reap_task_mm+0x220/0x220 [ 1635.218215] ? kthread_park+0x90/0x90 [ 1635.221976] ret_from_fork+0x3a/0x50 [ 1815.108088] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 1815.116065] kworker/1:1 D 0 9357 2 0x80004000 [ 1815.121873] Workqueue: events amdgpu_mn_destroy [amdgpu] [ 1815.127264] Call Trace: [ 1815.129765] __schedule+0x2ab/0x860 [ 1815.133299] ? rwsem_down_write_slowpath+0x329/0x660 [ 1815.138382] schedule+0x3a/0xc0 [ 1815.141613] rwsem_down_write_slowpath+0x32e/0x660 [ 1815.146523] down_write+0x74/0x80 [ 1815.149921] ? down_write+0x40/0x80 [ 1815.153490] ? down_write+0x74/0x80 [ 1815.157285] amdgpu_mn_destroy+0x6e/0x240 [amdgpu] [ 1815.162176] process_one_work+0x231/0x5c0 [ 1815.166313] worker_thread+0x3f/0x3b0 [ 1815.170100] ? __kthread_parkme+0x61/0x90 [ 1815.174204] kthread+0x12c/0x150 [ 1815.177573] ? process_one_work+0x5c0/0x5c0 [ 1815.181857] ? kthread_park+0x90/0x90 [ 1815.185591] ret_from_fork+0x3a/0x50 oom killer want to invalidate range in nonblock context. But the amdgpu_mn_read_lock might sleep, and casue deadlock then. Reviewed-by: Flora Cui Signed-off-by: xinhui pan Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 63 ++++++++++++++----------- 1 file changed, 35 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 6e55756feb143..f103284f1ffd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -86,6 +86,9 @@ struct amdgpu_mn { struct rb_root_cached objects; struct mutex read_lock; atomic_t recursion; +#if !defined(HAVE_MMU_NOTIFIER_PUT) + struct rcu_head rcu; +#endif }; /** @@ -101,6 +104,18 @@ struct amdgpu_mn_node { struct list_head bos; }; +#ifdef HAVE_MMU_NOTIFIER_PUT +static void amdgpu_mn_free(struct mmu_notifier *mn) +{ + kfree(container_of(mn, struct amdgpu_mn, mn)); +} +#else +static void amdgpu_mn_free(struct rcu_head *rcu) +{ + kfree(container_of(rcu, struct amdgpu_mn, rcu)); +} +#endif + /** * amdgpu_mn_destroy - destroy the MMU notifier * @@ -128,8 +143,12 @@ static void amdgpu_mn_destroy(struct work_struct *work) } up_write(&amn->lock); mutex_unlock(&adev->mn_lock); +#ifdef HAVE_MMU_NOTIFIER_PUT + mmu_notifier_put(&amn->mn); +#else mmu_notifier_unregister_no_release(&amn->mn, amn->mm); - kfree(amn); + mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); +#endif } /** @@ -180,6 +199,9 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) */ static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) { + /* FIXME: Need figure out one way to detect + * if we are in oom reaper context. + */ mutex_lock(&amn->read_lock); if (atomic_inc_return(&amn->recursion) == 1) down_read_non_owner(&amn->lock); @@ -193,11 +215,14 @@ static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) */ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) { - if (blockable) - mutex_lock(&amn->read_lock); - else if (!mutex_trylock(&amn->read_lock)) + /* Non blockable occurs only in oom reaper context. + * In this case, process is going to be killed anyway. + * Let oom reaper fail at this stage. + */ + if (!blockable) return -EAGAIN; + mutex_lock(&amn->read_lock); if (atomic_inc_return(&amn->recursion) == 1) down_read_non_owner(&amn->lock); mutex_unlock(&amn->read_lock); @@ -278,11 +303,6 @@ static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; - if (!mmu_notifier_range_blockable(range)) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, range->start, end); @@ -322,11 +342,6 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn_node *node; struct amdgpu_bo *bo; - if (!mmu_notifier_range_blockable(range)) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, range->start, end); @@ -386,13 +401,6 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; -#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) - if (!blockable) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } -#endif - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -448,13 +456,6 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn_node *node; struct amdgpu_bo *bo; -#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) - if (!blockable) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } -#endif - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -500,11 +501,17 @@ static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, static const struct mmu_notifier_ops amdgpu_mn_ops[] = { [AMDGPU_MN_TYPE_GFX] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif .release = amdgpu_mn_release, .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, .invalidate_range_end = amdgpu_mn_invalidate_range_end, }, [AMDGPU_MN_TYPE_HSA] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif .release = amdgpu_mn_release, .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, .invalidate_range_end = amdgpu_mn_invalidate_range_end, From 0697d814b0d2c5f72879609cec4092038598f056 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 15 Sep 2020 17:25:54 -0400 Subject: [PATCH 0569/2070] drm/amdgpu: prevent double release ttm->pages If ttm_bo_validate failed, pages are released, but ttm->pages is not cleared, this causes below backtrace. This issue happens on DELL machine with Ubuntu 18.04 kernel 4.15. put pages and set ttm->pages to NULL if ttm_bo_validate failed under memory pressure. [ 5400.077763] 0000:23:00.0: IOMMU mapping error in map_sg (io-pages: 32981732) [ 5400.097080] [drm:amdgpu_ttm_backend_bind [amdgpu]] *ERROR* failed to pin userptr [ 5400.097104] amdgpu: init_user_pages: failed to validate BO [ 5400.285482] BUG: Bad page state in process kfdtest pfn:1f6eac9 [ 5400.285533] page:ffffe07f7dbab240 count:0 mapcount:1 mapping:0000000000000000 index:0x1 [ 5400.285578] flags: 0x17ffffc0000000() [ 5400.285602] raw: 0017ffffc0000000 0000000000000000 0000000000000001 0000000000000000 [ 5400.285643] raw: dead000000000100 dead000000000200 0000000000000000 0000000000000000 [ 5400.285684] page dumped because: nonzero mapcount [ 5400.285710] Modules linked in: xt_conntrack ipt_MASQUERADE 4.15.0-117-generic #118-Ubuntu [ 5400.285779] Hardware name: Dell Inc. PowerEdge R7525/0PYVT1, BIOS 1.5.4 07/09/2020 [ 5400.285780] Call Trace: [ 5400.285793] dump_stack+0x6d/0x8e [ 5400.285798] bad_page+0xcb/0x120 [ 5400.285801] free_pages_check_bad+0x5f/0x70 [ 5400.285803] free_pcppages_bulk+0x44a/0x4e0 [ 5400.285808] ? mem_cgroup_uncharge+0x64/0x70 [ 5400.285810] free_unref_page_commit+0xb1/0xf0 [ 5400.285813] free_unref_page+0x59/0x70 [ 5400.285815] __put_page+0x40/0x80 [ 5400.285906] amdgpu_ttm_tt_set_user_pages+0x64/0xc0 [amdgpu] [ 5400.285983] amdgpu_ttm_tt_unpopulate+0x55/0x80 [amdgpu] [ 5400.285988] ttm_tt_unpopulate.part.10+0x53/0x60 [amdttm] [ 5400.285992] ttm_tt_destroy.part.11+0x4f/0x60 [amdttm] [ 5400.285996] ttm_tt_destroy+0x13/0x20 [amdttm] [ 5400.286000] ttm_bo_cleanup_memtype_use+0x36/0x80 [amdttm] [ 5400.286004] ttm_bo_release+0x1c9/0x360 [amdttm] [ 5400.286008] amdttm_bo_put+0x24/0x30 [amdttm] [ 5400.286083] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 5400.286192] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x9ca/0xb10 [amdgpu] [ 5400.286293] kfd_ioctl_alloc_memory_of_gpu+0xef/0x2c0 [amdgpu] Change-Id: Ide1cac32300e4195257a4faf125f4d85e1fc3d64 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Reviewed-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 8471c76bc379f..83548271b4eb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1156,7 +1156,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_hmm_range_free(range); #else if (ret) - release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); free_out: kvfree(mem->user_pages); mem->user_pages = NULL; From 2e29be4c51d0018d65105edf4e372205615ba609 Mon Sep 17 00:00:00 2001 From: xinhui pan Date: Wed, 4 Nov 2020 11:43:39 +0800 Subject: [PATCH 0570/2070] drm/amdkcl: define __GFP_RETRY_MAYFAIL as __GFP_NORETRY In old kernel, __GFP_NORETRY would not invoke OOM killer. TTM prefers that usage when TTM_PAGE_FLAG_NO_RETRY is set. Signed-off-by: xinhui pan Reviewed-by: Kevin Wang --- include/kcl/kcl_kernel.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index f33fc452d8243..f93febef548d8 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -16,7 +16,7 @@ #endif #ifndef __GFP_RETRY_MAYFAIL -#define __GFP_RETRY_MAYFAIL __GFP_REPEAT +#define __GFP_RETRY_MAYFAIL __GFP_NORETRY #endif #ifndef ALIGN_DOWN From 41b6a8278bfefbe8399d4bd591eed63d77b0567b Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 13:28:34 +0800 Subject: [PATCH 0571/2070] drm/amdkcl: fake the fs_reclaim_acquire{release} Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c | 143 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 | 15 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_sched_mm.h | 35 +++++ 7 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 create mode 100644 include/kcl/kcl_sched_mm.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d405d0ff0e8bf..c29acce60a682 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ - kcl_acpi_table.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c new file mode 100644 index 0000000000000..d56b220384800 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/mm/page_alloc.c + * + * Manages the free list, the system allocates free pages here. + * Note that kmalloc() lives in slab.c + * + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * Swap reorganised 29.12.95, Stephen Tweedie + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 + * Reshaped it to be a zoned allocator, Ingo Molnar, Red Hat, 1999 + * Discontiguous memory support, Kanoj Sarcar, SGI, Nov 1999 + * Zone balancing, Kanoj Sarcar, SGI, Jan 2000 + * Per cpu hot/cold page lists, bulk allocation, Martin J. Bligh, Sept 2002 + * (lots of bits borrowed from Ingo Molnar & Andrew Morton) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include + +#include +#include +#include +//#include "internal.h" +//#include "shuffle.h" +//#include "page_reporting.h" + +/* Copied from mm/page_allo.c */ +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +static struct lockdep_map __fs_reclaim_map = + STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); + +static bool __need_reclaim(gfp_t gfp_mask) +{ + /* no reclaim without waiting on it */ + if (!(gfp_mask & __GFP_DIRECT_RECLAIM)) + return false; + + /* this guy won't enter reclaim */ + if (current->flags & PF_MEMALLOC) + return false; + + if (gfp_mask & __GFP_NOLOCKDEP) + return false; + + return true; +} + +void __fs_reclaim_acquire(void) +{ + lock_map_acquire(&__fs_reclaim_map); +} + +void __fs_reclaim_release(void) +{ + lock_map_release(&__fs_reclaim_map); +} + +void _kcl_fs_reclaim_acquire(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_acquire(); + +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#endif + + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_acquire); + +void _kcl_fs_reclaim_release(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_release(); + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_release); +#endif +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index faa446bfc30fa..85c86633f00f3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -57,6 +57,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 new file mode 100644 index 0000000000000..be2f5c9928ae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v4.13-rc4-164-gd92a8cfcb37e +dnl # locking/lockdep: Rework FS_RECLAIM annotation +dnl # +AC_DEFUN([AC_AMDGPU_FS_RECLAIM_ACQUIRE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + fs_reclaim_acquire(0); + ],[ + AC_DEFINE(HAVE_FS_RECLAIM_ACQUIRE, 1, [fs_reclaim_acquire() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 67ff9be97051f..6394af0be5ce0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -98,6 +98,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_GEM_TTM_VMAP + AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 9c28eb7a4f6c4..7e99b0005482d 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -12,5 +12,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h new file mode 100644 index 0000000000000..3458dc2617c6a --- /dev/null +++ b/include/kcl/kcl_sched_mm.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SCHED_MM_H +#define _KCL_KCL_SCHED_MM_H + +#include +#include +#include +#include +#include +#include + +#ifndef SHRINK_EMPTY +#define SHRINK_EMPTY (~0UL - 1) +#define SHRINK_STOP (~0UL) +#endif + +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +extern void __fs_reclaim_acquire(void); +extern void __fs_reclaim_release(void); +static inline void fs_reclaim_acquire(gfp_t gfp_mask) { + return _kcl_fs_reclaim_acquire(gfp_mask); +} +static inline void fs_reclaim_release(gfp_t gfp_mask) { + return _kcl_fs_reclaim_release(gfp_mask); +} +#else +static inline void __fs_reclaim_acquire(void) { } +static inline void __fs_reclaim_release(void) { } +static inline void fs_reclaim_acquire(gfp_t gfp_mask) { } +static inline void fs_reclaim_release(gfp_t gfp_mask) { } +#endif +#endif + +#endif From a1eac35ecab4aa3188d0edf6bff7f64bedc30589 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 15:23:24 +0800 Subject: [PATCH 0572/2070] drm/amdkcl: fake memalloc_noreclaim_save() Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/memalloc_noreclaim_save.m4 | 16 ++++++++++++++++ include/kcl/kcl_sched_mm.h | 18 ++++++++++++++++-- 3 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6394af0be5ce0..119bab4e0fbfb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -99,6 +99,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE + AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 new file mode 100644 index 0000000000000..f9d0ba9a842cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + memalloc_noreclaim_save(); + ], [ + AC_DEFINE(HAVE_MEMALLOC_NORECLAIM_SAVE, 1, + [memalloc_noreclaim_save() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h index 3458dc2617c6a..be8915e298c62 100644 --- a/include/kcl/kcl_sched_mm.h +++ b/include/kcl/kcl_sched_mm.h @@ -29,7 +29,21 @@ static inline void __fs_reclaim_acquire(void) { } static inline void __fs_reclaim_release(void) { } static inline void fs_reclaim_acquire(gfp_t gfp_mask) { } static inline void fs_reclaim_release(gfp_t gfp_mask) { } -#endif -#endif +#endif /* CONFIG_LOCKDEP */ +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ + +#ifndef HAVE_MEMALLOC_NORECLAIM_SAVE +static inline unsigned int memalloc_noreclaim_save(void) +{ + unsigned int flags = current->flags & PF_MEMALLOC; + current->flags |= PF_MEMALLOC; + return flags; +} + +static inline void memalloc_noreclaim_restore(unsigned int flags) +{ + current->flags = (current->flags & ~PF_MEMALLOC) | flags; +} +#endif /* HAVE_MEMALLOC_NORECLAIM_SAVE */ #endif From 5a233678de72466f91b6116c199df3599b39e1a8 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 20:10:01 +0800 Subject: [PATCH 0573/2070] drm/amdkcl: fake the macro of __GFP_KSWAPD_RECLAIM Signed-off-by: Shiwu Zhang --- include/kcl/kcl_kernel.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index f93febef548d8..ef5bdee50ee36 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -23,4 +23,9 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #endif /* ALIGN_DOWN */ +#ifndef ___GFP_KSWAPD_RECLAIM +#define ___GFP_KSWAPD_RECLAIM 0x00u +#define __GFP_KSWAPD_RECLAIM ((__force gfp_t)___GFP_KSWAPD_RECLAIM) /* kswapd can wake */ +#endif /* ___GFP_KSWAPD_RECLAIM */ + #endif /* AMDKCL_KERNEL_H */ From 4163bdc279800c44103b61eb8ef70782e57f1fd4 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 17 Mar 2021 17:36:05 +0800 Subject: [PATCH 0574/2070] drm/amdkcl: init the ddev->pdev for legacy os This is caused by "Upcast struct drm_device.dev to struct pci_device; replace pdev" v5.11-rc2-514-g36b73b051c41 Otherwise, NULL pointer dereference will be reported for drm_pci_set_busid: [ 55.850413] BUG: kernel NULL pointer dereference, address: 0000000000000038 [ 55.850456] #PF: supervisor read access in kernel mode [ 55.850482] #PF: error_code(0x0000) - not-present page [ 55.850507] PGD 0 P4D 0 [ 55.850524] Oops: 0000 [#1] SMP NOPTI [ 55.850545] CPU: 7 PID: 1687 Comm: Xorg Tainted: G OE 5.8.0-45-generic #51~20.04.1-Ubuntu [ 55.850587] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1201 07/29/2019 [ 55.850655] RIP: 0010:drm_pci_set_busid+0x16/0x80 [drm] [ 55.850681] Code: 8b 85 80 01 00 00 eb 86 c3 66 2e 0f 1f 84 00 00 00 00 00 90 0f 1f 44 00 00 55 31 d2 48 89 e5 53 48 8b 87 88 01 00 00 48 89 f3 <44> 8b 40 38 48 8b 40 10 45 89 c1 41 c1 e8 03 0f b6 88 e0 00 00 00 [ 55.850762] RSP: 0018:ffffb768c0fabd20 EFLAGS: 00010246 [ 55.850788] RAX: 0000000000000000 RBX: ffffa0745070a840 RCX: 0000000000000002 [ 55.850820] RDX: 0000000000000000 RSI: ffffa0745070a840 RDI: ffffa0742dbe0010 [ 55.850853] RBP: ffffb768c0fabd28 R08: 0000000000000000 R09: ffffffffc046e5d9 [ 55.850886] R10: 0000000000000000 R11: 0000000000000000 R12: ffffa0742dbe0010 [ 55.850918] R13: ffffa0742d2abe00 R14: ffffa0742dbe00b8 R15: ffffa0745070a840 [ 55.850952] FS: 00007f6673a15a40(0000) GS:ffffa0745ddc0000(0000) knlGS:0000000000000000 [ 55.850989] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 55.851016] CR2: 0000000000000038 CR3: 00000004506da006 CR4: 00000000003606e0 [ 55.851049] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 55.851082] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 55.851114] Call Trace: [ 55.851149] drm_setversion+0x14e/0x190 [drm] [ 55.851188] ? drm_ioctl_permit+0x80/0x80 [drm] [ 55.851227] drm_ioctl_kernel+0xae/0xf0 [drm] [ 55.851266] drm_ioctl+0x234/0x3d0 [drm] [ 55.851302] ? drm_ioctl_permit+0x80/0x80 [drm] [ 55.851449] amdgpu_drm_ioctl+0x4e/0x80 [amdgpu] [ 55.851478] ksys_ioctl+0x9d/0xd0 [ 55.851496] __x64_sys_ioctl+0x1a/0x20 [ 55.851519] do_syscall_64+0x49/0xc0 [ 55.851539] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 55.851565] RIP: 0033:0x7f6673d7550b Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c6214704d59dd..a0671e4ff8baa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2472,6 +2472,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, goto err_free; #endif + ddev->pdev = pdev; pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); From ae4c8cef18597ba5213087b751e1e8d96ae150df Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Mar 2021 13:11:31 +0800 Subject: [PATCH 0575/2070] drm/amdkcl: add BIT_PER_TYPE macro This patch is caused by 'drm/amdkfd: Fix UBSAN shift-out-of-bounds warning' v5.11-2606-g9f3ada6b3e86 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_bitops.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_bitops.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 85c86633f00f3..d9bc00f778d2b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -56,6 +56,7 @@ #include #include #include +#include #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" diff --git a/include/kcl/kcl_bitops.h b/include/kcl/kcl_bitops.h new file mode 100644 index 0000000000000..f022f59a6a772 --- /dev/null +++ b/include/kcl/kcl_bitops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BITOPS_BACKPORT_H +#define AMDKCL_BITOPS_BACKPORT_H + +#include +/* Copied froma include/linux/bitops.h */ +#ifndef BITS_PER_TYPE +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) +#endif + +#endif From dc6a59007e5754a210838caf63d26b27aa059abc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Mar 2021 16:14:09 +0800 Subject: [PATCH 0576/2070] drm/amdkcl: change drm_framebuffer field access code to kcl_drm_gem_fb_set_obj This patch is caused by 'drm/amdgpu: Verify bo size can fit framebuffer size on init.' v5.11-2639-g9e429bf5aabb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 28 +++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a82ae6059dd55..362b26b74c25a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1193,6 +1193,30 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return r; } +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); + + ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); + if (ret) + goto err; + + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (ret) + goto err; + + return 0; +err: + drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + return ret; +} + static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, @@ -1202,7 +1226,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, { int ret; - rfb->base.obj[0] = obj; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, @@ -1231,7 +1255,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); - rfb->base.obj[0] = NULL; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); return ret; } From 1f76c8f59ebb41bc5e466a43c1c9470c6c10ed6a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Mar 2021 16:58:47 +0800 Subject: [PATCH 0577/2070] drm/amdkcl: fake drm_err macro This patch is caused by 'drm/amdgpu: Verify bo size can fit framebuffer size on init.' v5.11-2639-g9e429bf5aabb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 19 +++++++++++++++++++ include/kcl/kcl_drm_print.h | 20 ++++++++++++++++---- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 0c47443e0f189..b5d9e1a9113a3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -83,3 +83,22 @@ void drm_dev_dbg(const struct device *dev, int category, } EXPORT_SYMBOL(drm_dev_dbg); #endif + +#if !defined(HAVE_DRM_ERR_MACRO) +void kcl_drm_err(const char *format, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(kcl_drm_err); + +#endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 10ba443b49303..c51497dc79f3e 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -27,6 +27,7 @@ #include #include +#include #if !defined(HAVE_DRM_DRM_PRINT_H) /* Copied from d8187177b0b1 include/drm/drm_print.h */ @@ -102,10 +103,20 @@ void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) _DRM_PRINTK(_once, NOTICE, fmt, ##__VA_ARGS__) #endif -#ifndef DRM_ERROR -#define DRM_ERROR(fmt, ...) \ - drm_printk(KERN_ERR, DRM_UT_NONE, fmt, ##__VA_ARGS__) -#endif +#ifndef drm_err +#define drm_err(drm, fmt, ...) \ + dev_err((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) + +__printf(1, 2) +void kcl_drm_err(const char *format, ...); + +#undef DRM_ERROR +#define DRM_ERROR(fmt, ...) \ + kcl_drm_err(fmt, ##__VA_ARGS__) + +#else +#define HAVE_DRM_ERR_MACRO +#endif /* drm_err */ #if !defined(DRM_DEV_DEBUG) #define DRM_DEV_DEBUG(dev, fmt, ...) \ @@ -142,4 +153,5 @@ static inline bool drm_debug_enabled(unsigned int category) return unlikely(drm_debug & category); } #endif /* HAVE_DRM_DEBUG_ENABLED */ + #endif From 943a8540ec05f3685503074814547a97763bf1f5 Mon Sep 17 00:00:00 2001 From: charles sun Date: Sun, 14 Mar 2021 19:19:10 +0800 Subject: [PATCH 0578/2070] the dcn301_calculate_wm_and_dl() calculation exposed a issue - switch to dcn30 version for now. still need to follow up with dcn301 watermark updates version. Signed-off-by: Charles Sun Reviewed-by: Nikola Cornij Acked-by: Charles Sun --- .../gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index ef02cf0045ba2..483f665dd0a31 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1398,7 +1398,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, From 577959e73ec90ad79acc858f01c297ac9d161d13 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Mar 2021 15:07:31 +0800 Subject: [PATCH 0579/2070] drm/amdkcl: cleanup HAVE_DRM_MM_INSERT_MODE Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_drm_mm_backport.h | 6 +- include/kcl/kcl_drm_mm.h | 68 ++++++++++++++++++++++ 3 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_drm_mm.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 7e99b0005482d..a156d45879b92 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h index 8c20d53ed7f4f..1a2614d47ab59 100644 --- a/include/kcl/backport/kcl_drm_mm_backport.h +++ b/include/kcl/backport/kcl_drm_mm_backport.h @@ -8,7 +8,7 @@ * with rbtrees */ -#include +#include #ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, @@ -20,4 +20,8 @@ static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, #define drm_mm_insert_node _kcl_drm_mm_insert_node #endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ +#ifndef HAVE_DRM_MM_INSERT_MODE +#define drm_mm_insert_node_in_range _kcl_drm_mm_insert_node_in_range +#endif + #endif /* AMDKCL_DRM_MM_H */ diff --git a/include/kcl/kcl_drm_mm.h b/include/kcl/kcl_drm_mm.h new file mode 100644 index 0000000000000..5387e6c05bc65 --- /dev/null +++ b/include/kcl/kcl_drm_mm.h @@ -0,0 +1,68 @@ +/************************************************************************** + * + * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. + * Copyright 2016 Intel Corporation + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Thomas Hellstrom + */ +#ifndef _KCL_KCL_DRM_MM_H_H_ +#define _KCL_KCL_DRM_MM_H_H_ +#include + +#ifndef HAVE_DRM_MM_INSERT_MODE +/* Copied from 4e64e5539d15 include/drm/drm_mm.h */ +enum drm_mm_insert_mode { + DRM_MM_INSERT_BEST = 0, + DRM_MM_INSERT_LOW, + DRM_MM_INSERT_HIGH, + DRM_MM_INSERT_EVICT, +}; + +static inline +int _kcl_drm_mm_insert_node_in_range(struct drm_mm * const mm, + struct drm_mm_node * const node, + u64 size, u64 alignment, + unsigned long color, + u64 range_start, u64 range_end, + enum drm_mm_insert_mode mode) +{ + enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; + enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; + + if (mode == DRM_MM_INSERT_HIGH) { + sflags = DRM_MM_SEARCH_BELOW; + aflags = DRM_MM_CREATE_TOP; + } + + return drm_mm_insert_node_in_range_generic(mm, node, size, + alignment, color, range_start, range_end, + sflags, aflags); +} +#endif /* HAVE_DRM_MM_INSERT_MODE */ + +#endif From c05d653d2cc681461221a2e49d0a5de57b165f63 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 25 Mar 2021 16:03:17 +0800 Subject: [PATCH 0580/2070] drm/amdkcl: add Centos7.3, 7.4 and 7.6 phantom support clear the compiling errors like lacking header files Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++++ drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c | 1 - drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_tt.c | 4 ++++ include/kcl/backport/kcl_drm_prime.h | 4 ++++ include/kcl/kcl_drm_hdcp.h | 7 +++++++ include/kcl/kcl_sched_mm.h | 1 - 9 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a0671e4ff8baa..2a9f4a1504fa4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2232,7 +2232,7 @@ static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { {0x67FF, 0xF7, CHIP_POLARIS10}, }; -static const struct drm_driver amdgpu_kms_driver; +static struct drm_driver amdgpu_kms_driver; static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) { @@ -2455,11 +2455,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, ddev->driver_features &= ~DRIVER_ATOMIC; #else /* warn the user if they mix atomic and non-atomic capable GPUs */ - if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) + if ((amdgpu_kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) - kms_driver.driver_features |= DRIVER_ATOMIC; + amdgpu_kms_driver.driver_features |= DRIVER_ATOMIC; #endif kcl_pci_create_measure_file(pdev); @@ -3127,7 +3127,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; -static const struct drm_driver amdgpu_kms_driver = { +static struct drm_driver amdgpu_kms_driver = { .driver_features = 0 #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index f01f385091083..e110383ec40e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -77,7 +77,11 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; } +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES ddev->driver_features &= ~DRIVER_ATOMIC; +#else + ddev->driver->driver_features &= ~DRIVER_ATOMIC; +#endif adev->cg_flags = 0; adev->pg_flags = 0; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c index d56b220384800..4b6735959d945 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -62,7 +62,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d9bc00f778d2b..9ecde4e4e59e2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -31,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index a156d45879b92..2de8df93b5298 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -14,5 +14,6 @@ #include #include #include +#include #endif diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 1f7cd5e0e3970..1857075d429bb 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -217,10 +217,14 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, ttm_tt_init_fields(ttm, bo, page_flags, caching, 0); +#ifndef HAVE_TTM_SG_TT_INIT + ret = ttm_dma_tt_alloc_page_directory(ttm); +#else if (page_flags & TTM_TT_FLAG_EXTERNAL) ret = ttm_sg_tt_alloc_page_directory(ttm); else ret = ttm_dma_tt_alloc_page_directory(ttm); +#endif if (ret) { pr_err("Failed allocating page table\n"); return -ENOMEM; diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h index 1c3895f60823d..33187c1891d71 100644 --- a/include/kcl/backport/kcl_drm_prime.h +++ b/include/kcl/backport/kcl_drm_prime.h @@ -33,7 +33,11 @@ #ifndef _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ #define _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ +#ifdef HAVE_DRM_DRMP_H +#include +#else #include +#endif #ifndef HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS static inline diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index ba77fb5c0973a..b3f6318e1f652 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -45,6 +45,13 @@ #define HDCP_STREAM_TYPE0 0x00 #define HDCP_STREAM_TYPE1 0x01 +/* introduced in v4.15-rc4-1351-g495eb7f877ab + * drm: Add some HDCP related #defines + */ +#ifndef DRM_HDCP_KSV_LEN +#define DRM_HDCP_KSV_LEN 5 +#endif + /* HDCP2.2 Msg IDs */ #define HDCP_2_2_NULL_MSG 1 #define HDCP_2_2_AKE_INIT 2 diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h index be8915e298c62..31e59278e4b5d 100644 --- a/include/kcl/kcl_sched_mm.h +++ b/include/kcl/kcl_sched_mm.h @@ -7,7 +7,6 @@ #include #include #include -#include #ifndef SHRINK_EMPTY #define SHRINK_EMPTY (~0UL - 1) From cf9cb33f4a3d23e8769ccae5dd21bcfbfdd59ebb Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 22 Mar 2021 17:08:28 +0800 Subject: [PATCH 0581/2070] drm/amdkcl: update the config.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/config/config.h | 817 +++++++++++++++++++++++ 1 file changed, 817 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3c27c1d6c67b3..a5ac4170b3f72 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1,6 +1,21 @@ /* config/config.h. Generated from config.h.in by configure. */ /* config/config.h.in. Generated from configure.ac by autoheader. */ +/* whether invalidate_range_start() wants 2 args */ +#define HAVE_2ARGS_INVALIDATE_RANGE_START 1 + +/* whether invalidate_range_start() wants 5 args */ +/* #undef HAVE_5ARGS_INVALIDATE_RANGE_START */ + +/* whether access_ok(x, x) is available */ +#define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 + +/* acpi_put_table() is available */ +/* #undef HAVE_ACPI_PUT_TABLE */ + +/* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ +#define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 + /* *FLAGS_.o support to take the path relative to $(obj) */ #define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 @@ -10,15 +25,290 @@ /* amd_iommu_pc_get_max_banks() arg is unsigned int */ /* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ +/* hmm support is enabled */ +#define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 + +/* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ +#define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 + +/* amd_iommu_pc_supported() is available */ +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ + +/* arch_io_{reserve/free}_memtype_wc() are available */ +#define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 + /* Define to 1 if you have the header file. */ #define HAVE_ASM_FPU_API_H 1 /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* backlight_device_set_brightness() is available */ +#define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 + +/* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ +#define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 + +/* whether CHUNK_ID_SYNOBJ_IN_OUT is defined */ +#define HAVE_CHUNK_ID_SYNOBJ_IN_OUT 1 + +/* compat_ptr_ioctl() is available */ +#define HAVE_COMPAT_PTR_IOCTL 1 + +/* debugfs_create_file_size() is available */ +#define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 + +/* devcgroup_check_permission() is available */ +#define HAVE_DEVCGROUP_CHECK_PERMISSION 1 + +/* devm_memremap_pages() wants struct dev_pagemap */ +#define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 + +/* devm_memremap_pages() wants p,p,p,p interface */ +/* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ + +/* there is 'range' field within dev_pagemap structure */ +#define HAVE_DEV_PAGEMAP_RANGE 1 + +/* dev_pm_set_driver_flags() is available */ +#define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 + +/* dma_buf dynamic_mapping is available */ +/* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ + +/* whether dma_fence_get_stub exits */ +#define HAVE_DMA_FENCE_GET_STUB 1 + +/* dma_fence_set_error() is available */ +#define HAVE_DMA_FENCE_SET_ERROR 1 + +/* dma_map_resource() is enabled */ +#define HAVE_DMA_MAP_RESOURCE 1 + +/* dma_map_sgtable() is enabled */ +#define HAVE_DMA_MAP_SGTABLE 1 + +/* dma_resv->seq is available */ +#define HAVE_DMA_RESV_SEQ 1 + +/* dma_resv->seq is seqcount_ww_mutex_t */ +#define HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T 1 + +/* down_read_killable() is available */ +#define HAVE_DOWN_READ_KILLABLE 1 + +/* down_write_killable() is available */ +#define HAVE_DOWN_WRITE_KILLABLE 1 + +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DP_MST_CONNECTOR_LATE_REGISTER 1 + +/* drm_accurate_vblank_count() is available */ +/* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ + +/* DRM_AMDGPU_FENCE_TO_HANDLE is defined */ +#define HAVE_DRM_AMDGPU_FENCE_TO_HANDLE 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ +/* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are + available */ +#define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 + +/* drm_atomic_get_new_plane_state() is available */ +#define HAVE_DRM_ATOMIC_GET_NEW_PLANE_STATE 1 + +/* drm_atomic_helper_calc_timestamping_constants() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 + +/* drm_atomic_helper_check_plane_state() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 + +/* drm_atomic_helper_shutdown() is available */ +#define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 + +/* drm_atomic_helper_wait_for_flip_done() is available */ +#define HAVE_DRM_ATOMIC_HELPER_WAIT_FOR_FLIP_DONE 1 + +/* {drm_atomic_helper_crtc_set_property, drm_atomic_helper_plane_set_property, + drm_atomic_helper_connector_set_property, drm_atomic_helper_connector_dpms} + is available */ +/* #undef HAVE_DRM_ATOMIC_HELPER_XXX_SET_PROPERTY */ + +/* drm_atomic_nonblocking_commit() is available */ +#define HAVE_DRM_ATOMIC_NONBLOCKING_COMMIT 1 + +/* drm_atomic_plane_disabling() wants drm_plane_state * arg */ +#define HAVE_DRM_ATOMIC_PLANE_DISABLING_DRM_PLANE_STATE 1 + +/* drm_atomic_private_obj_init() is available */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 + +/* drm_atomic_private_obj_init() has p,p,p,p interface */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P 1 + +/* whether struct drm_atomic_state have async_update */ +#define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 + +/* drm_atomic_state_put() is available */ +#define HAVE_DRM_ATOMIC_STATE_PUT 1 + +/* drm_color_lut_size() is available */ +#define HAVE_DRM_COLOR_LUT_SIZE 1 + +/* drm_connector_for_each_possible_encoder() wants 2 arguments */ +#define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 + +/* struct drm_connector_funcs has register members */ +#define HAVE_DRM_CONNECTOR_FUNCS_REGISTER 1 + +/* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state + */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state + arg */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_init_with_ddc() is available */ +#define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 + +/* connector property "max bpc" is available */ +#define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 + +/* drm_connector_put() is available */ +#define HAVE_DRM_CONNECTOR_PUT 1 + +/* connector reference counting is available */ +#define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 + +/* struct drm_connector_state has hdcp_content_type member */ +#define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 + +/* drm_connector_unreference() is available */ +/* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ + +/* drm_connector_xxx() drop _mode_ */ +#define HAVE_DRM_CONNECTOR_XXX_DROP_MODE 1 + +/* ddrm_atomic_stat has __drm_crtcs_state */ +/* #undef HAVE_DRM_CRTCS_STATE_MEMBER */ + +/* drm_crtc_accurate_vblank_count() is available */ +#define HAVE_DRM_CRTC_ACCURATE_VBLANK_COUNT 1 + +/* drm_crtc_enable_color_mgmt() is available */ +#define HAVE_DRM_CRTC_ENABLE_COLOR_MGMT 1 + +/* drm_crtc_from_index() is available */ +#define HAVE_DRM_CRTC_FROM_INDEX 1 + +/* drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_crtc_init_with_planes() wants name */ +#define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 + +/* drm_debug_enabled() is available */ +#define HAVE_DRM_DEBUG_ENABLED 1 + +/* dev_device->driver_features is available */ +#define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 + +/* drm_device->filelist_mutex is available */ +#define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 + +/* drm_device->open_count is int */ +/* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ + +/* drm_dev_dbg() is available */ +#define HAVE_DRM_DEV_DBG 1 + +/* drm_dev_put() is available */ +#define HAVE_DRM_DEV_PUT 1 + +/* drm_dev_unplug() is available */ +#define HAVE_DRM_DEV_UNPLUG 1 + +/* display_info->hdmi.scdc.scrambling are available */ +#define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 + +/* display_info->max_tmds_clock is available */ +#define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 + +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + +/* drm_dp_atomic_find_vcpi_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 + +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 + +/* drm_dp_calc_pbn_mode() wants 3args */ +#define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 + +/* drm_dp_cec_register_connector() wants p,p interface */ +#define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 + +/* drm_dp_mst_add_affected_dsc_crtcs() is available */ +#define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 + +/* drm_dp_mst_atomic_check() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_CHECK 1 + +/* drm_dp_mst_atomic_enable_dsc() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 + +/* drm_dp_mst_detect_port() wants p,p,p,p args */ +#define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 + +/* drm_dp_mst_dsc_aux_for_port() is available */ +#define HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT 1 + +/* drm_dp_mst_{get,put}_port_malloc() is available */ +#define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 + +/* struct drm_dp_mst_topology_cbs->destroy_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ + +/* struct drm_dp_mst_topology_cbs has hotplug member */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ + +/* struct drm_dp_mst_topology_cbs->register_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ + +/* drm_dp_mst_topology_mgr_init() wants drm_device arg */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 + +/* drm_dp_mst_topology_mgr_resume() wants 2 args */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 + +/* drm_dp_send_real_edid_checksum() is available */ +#define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 + +/* drm_dp_start_crc() is available */ +#define HAVE_DRM_DP_START_CRC 1 + +/* drm_driver->gem_prime_res_obj() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ + +/* drm_driver->get_scanout_position() return bool */ +/* #undef HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL */ + +/* drm_driver->get_vblank_timestamp() return bool */ +/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL */ + +/* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ +/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ + +/* drm_driver->release() is available */ +#define HAVE_DRM_DRIVER_RELEASE 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -56,6 +346,9 @@ */ #define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_TTM_HELPER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 @@ -83,12 +376,287 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_VBLANK_H 1 +/* drm_driver_feature DRIVER_IRQ_SHARED is available */ +/* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ + +/* drm_driver_feature DRIVER_PRIME is available */ +/* #undef HAVE_DRM_DRV_DRIVER_PRIME */ + +/* drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available */ +#define HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE 1 + +/* drm_gem_prime_export() with p,i arg is available */ +#define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 + +/* drm_edid_to_eld() are available */ +/* #undef HAVE_DRM_EDID_TO_ELD */ + +/* drm_encoder_find() wants file_priv */ +#define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 + +/* drm_fb_helper_single_add_all_connectors() && + drm_fb_helper_remove_one_connector() are symbol */ +/* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ + +/* drm_fb_helper_fill_info() is available */ +#define HAVE_DRM_FB_HELPER_FILL_INFO 1 + +/* drm_fb_helper_init() has 2 args */ +#define HAVE_DRM_FB_HELPER_INIT_2ARGS 1 + +/* drm_fb_helper_init() has 3 args */ +/* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ + +/* whether drm_fb_helper_lastclose() is available */ +#define HAVE_DRM_FB_HELPER_LASTCLOSE 1 + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ +#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS 1 + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ +#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP 1 + +/* drm_fb_helper_set_suspend_unlocked() is available */ +#define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 + +/* drm_format_info.block_w and rm_format_info.block_h is available */ +#define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 + +/* whether struct drm_framebuffer have format */ +#define HAVE_DRM_FRAMEBUFFER_FORMAT 1 + +/* drm_gem_map_attach() wants 2 arguments */ +/* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ + +/* drm_gem_object_lookup() wants 2 args */ +#define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 + +/* drm_gem_object_put_locked() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT_LOCKED 1 + +/* drm_gem_object_put_unlocked() is available */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED */ + +/* ttm_buffer_object->base is available */ +#define HAVE_DRM_GEM_OBJECT_RESV 1 + +/* drm_gem_ttm_vmap() is available */ +#define HAVE_DRM_GEM_TTM_VMAP 1 + +/* drm_get_format_info() is available */ +#define HAVE_DRM_GET_FORMAT_INFO 1 + +/* drm_get_format_name() has i,p interface */ +#define HAVE_DRM_GET_FORMAT_NAME_I_P 1 + +/* drm_hdcp_update_content_protection is available */ +#define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ +/* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface */ +#define HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 + +/* drm_helper_force_disable_all() is available */ +#define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 + +/* drm_helper_mode_fill_fb_struct() wants dev arg */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV 1 + +/* drm_is_current_master() is available */ +#define HAVE_DRM_IS_CURRENT_MASTER 1 + +/* drm_kms_helper_is_poll_worker() is available */ +#define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 + +/* whether drm_mm_insert_mode is available */ +#define HAVE_DRM_MM_INSERT_MODE 1 + +/* drm_mm_insert_node has three parameters */ +#define HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS 1 + +/* drm_mode_config->dp_subconnector_property is available */ +#define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 + +/* drm_mode_config_funcs->atomic_state_alloc() is available */ +#define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 + +/* drm_mode_config->helper_private is available */ +#define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 + +/* drm_mode_get_hv_timing is available */ +#define HAVE_DRM_MODE_GET_HV_TIMING 1 + +/* drm_mode_is_420_xxx() is available */ +#define HAVE_DRM_MODE_IS_420_XXX 1 + +/* enum drm_mode_subconnector is available */ +/* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ + +/* drm_need_swiotlb() is availablea */ +#define HAVE_DRM_NEED_SWIOTLB 1 + +/* drm atomic nonblocking commit support is available */ +#define HAVE_DRM_NONBLOCKING_COMMIT_SUPPORT 1 + +/* drm_plane_helper_check_state is available */ +/* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ + +/* drm_plane_mask is available */ +#define HAVE_DRM_PLANE_MASK 1 + +/* drm_plane_create_alpha_property, drm_plane_create_blend_mode_property are + available */ +#define HAVE_DRM_PLANE_PROPERTY_ALPHA_BLEND_MODE 1 + +/* drm_plane_create_color_properties is available */ +#define HAVE_DRM_PLANE_PROPERTY_COLOR_ENCODING_RANGE 1 + +/* drm_plane_create_rotation_property is available */ +#define HAVE_DRM_PLANE_PROPERTY_ROTATION 1 + +/* drm_prime_pages_to_sg() wants 3 arguments */ +#define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 + +/* drm_prime_sg_to_dma_addr_array() is available */ +#define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 + +/* drm_printer->prefix is available */ +#define HAVE_DRM_PRINTER_PREFIX 1 + +/* drm_syncobj_fence_get() is available */ +/* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ + +/* drm_syncobj_find_fence() is available */ +#define HAVE_DRM_SYNCOBJ_FIND_FENCE 1 + +/* whether drm_syncobj_find_fence() wants 3 args */ +/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_3ARGS */ + +/* whether drm_syncobj_find_fence() wants 4 args */ +/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_4ARGS */ + +/* whether drm_syncobj_find_fence() wants 5 args */ +#define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 +/* drm_universal_plane_init() wants 7 args */ +/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_7ARGS */ + +/* drm_universal_plane_init() wants 8 args */ +/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_8ARGS */ + +/* drm_universal_plane_init() wants 9 args */ +#define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 + +/* drm_vma_node_verify_access() 2nd argument is drm_file */ +#define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 + +/* Variable refresh rate(vrr) is supported */ +#define HAVE_DRM_VRR_SUPPORTED 1 + +/* fault_flag_allow_retry_first() is available */ +#define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 + +/* drm_mode_object->free_cb is available */ +/* #undef HAVE_FREE_CB_IN_STRUCT_DRM_MODE_OBJECT */ + +/* fs_reclaim_acquire() is available */ +#define HAVE_FS_RECLAIM_ACQUIRE 1 + +/* drm_driver->gem_free_object_unlocked() is available */ +/* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ + +/* get_user_pages() wants 6 args */ +/* #undef HAVE_GET_USER_PAGES_6ARGS */ + +/* get_user_pages() wants gup_flags parameter */ +#define HAVE_GET_USER_PAGES_GUP_FLAGS 1 + +/* get_user_pages_remote() wants gup_flags parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ + +/* get_user_pages_remote() is introduced with initial prototype */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_INTRODUCED */ + +/* get_user_pages_remote() wants locked parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ + +/* get_user_pages_remote() remove task_struct pointer */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT 1 + +/* drm_connector_hdr_sink_metadata() is available */ +#define HAVE_HDR_SINK_METADATA 1 + +/* hmm remove the customizable pfn format */ +#define HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT 1 + +/* hmm_range_fault() wants 1 arg */ +#define HAVE_HMM_RANGE_FAULT_1ARG 1 + +/* struct i2c_lock_operations is defined */ +#define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 + +/* i2c_new_client_device() is enabled */ +#define HAVE_I2C_NEW_CLIENT_DEVICE 1 + +/* idr_remove return void pointer */ +#define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 + +/* in_compat_syscall is defined */ +#define HAVE_IN_COMPAT_SYSCALL 1 + +/* jiffies64_to_msecs() is available */ +#define HAVE_JIFFIES64_TO_MSECS 1 + /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* kref_read() function is available */ +#define HAVE_KREF_READ 1 + +/* ksys_sync_helper() is available */ +#define HAVE_KSYS_SYNC_HELPER 1 + +/* kthread_{park/unpark/parkme/should_park}() is available */ +#define HAVE_KTHREAD_PARK_XX 1 + +/* kthread_{use,unuse}_mm() is available */ +#define HAVE_KTHREAD_USE_MM 1 + +/* ktime_get_boottime_ns() is available */ +#define HAVE_KTIME_GET_BOOTTIME_NS 1 + +/* ktime_get_mono_fast_ns is available */ +#define HAVE_KTIME_GET_MONO_FAST_NS 1 + +/* ktime_get_ns is available */ +#define HAVE_KTIME_GET_NS 1 + +/* ktime_get_raw_ns is available */ +#define HAVE_KTIME_GET_RAW_NS 1 + +/* ktime_get_real_seconds() is available */ +#define HAVE_KTIME_GET_REAL_SECONDS 1 + +/* kvcalloc() is available */ +#define HAVE_KVCALLOC 1 + +/* kvfree() is available */ +#define HAVE_KVFREE 1 + +/* kvmalloc_array() is available */ +#define HAVE_KVMALLOC_ARRAY 1 + +/* kv[mz]alloc() are available */ +#define HAVE_KVZALLOC_KVMALLOC 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 @@ -98,12 +666,18 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_BUF_MAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_RESV_H 1 +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_FENCE_ARRAY_H */ + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 @@ -131,9 +705,252 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_TASK_H 1 +/* list_bulk_move_tail() is available */ +#define HAVE_LIST_BULK_MOVE_TAIL 1 + +/* list_is_first() is available */ +#define HAVE_LIST_IS_FIRST 1 + +/* list_rotate_to_front() is available */ +#define HAVE_LIST_ROTATE_TO_FRONT 1 + +/* memalloc_nofs_{save,restore}() are available */ +#define HAVE_MEMALLOC_NOFS_SAVE 1 + +/* memalloc_noreclaim_save() is available */ +#define HAVE_MEMALLOC_NORECLAIM_SAVE 1 + +/* mem_encrypt_active() is available */ +#define HAVE_MEM_ENCRYPT_ACTIVE 1 + +/* mmgrab() is available */ +#define HAVE_MMGRAB 1 + +/* mmu_notifier_call_srcu() is available */ +/* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ + +/* mmu_notifier_put() is available */ +#define HAVE_MMU_NOTIFIER_PUT 1 + +/* mmu_notifier_range_blockable() is available */ +#define HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE 1 + +/* mmu_notifier_synchronize() is available */ +#define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 + +/* mm_access() is available */ +#define HAVE_MM_ACCESS 1 + +/* release_pages() wants 2 args */ +#define HAVE_MM_RELEASE_PAGES_2ARGS 1 + +/* num_u32_u32 is available */ +#define HAVE_MUL_U32_U32 1 + +/* pcie_bandwidth_available() is available */ +#define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 + +/* pci_enable_atomic_ops_to_root() exist */ +#define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 + +/* pcie_get_speed_cap() and pcie_get_width_cap() exist */ +#define HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP 1 + +/* PCI driver handles extended tags */ +#define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 + +/* pci_dev_id() is available */ +#define HAVE_PCI_DEV_ID 1 + +/* pci_is_thunderbolt_attached() is available */ +#define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 + +/* pci_pr3_present() is available */ +#define HAVE_PCI_PR3_PRESENT 1 + +/* pci_rebar_bytes_to_size() is available */ +#define HAVE_PCI_REBAR_BYTES_TO_SIZE 1 + +/* pci_upstream_bridge() is available */ +#define HAVE_PCI_UPSTREAM_BRIDGE 1 + +/* perf_event_update_userpage() is exported */ +#define HAVE_PERF_EVENT_UPDATE_USERPAGE 1 + +/* pfn_t is defined */ +#define HAVE_PFN_T 1 + +/* vm_insert_mixed() wants pfn_t arg */ +/* #undef HAVE_PFN_T_VM_INSERT_MIXED */ + +/* pm_genpd_remove_device() wants 2 arguments */ +/* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ + +/* remove_conflicting_framebuffers() returns int */ +/* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ + +/* request_firmware_direct() is available */ +#define HAVE_REQUEST_FIRMWARE_DIRECT 1 + +/* reservation_object->staged is available */ +/* #undef HAVE_RESERVATION_OBJECT_STAGED */ + +/* sched_set_fifo_low() is available */ +#define HAVE_SCHED_SET_FIFO_LOW 1 + +/* seq_hex_dump() is available */ +#define HAVE_SEQ_HEX_DUMP 1 + +/* drm_driver->set_busid is available */ +/* #undef HAVE_SET_BUSID_IN_STRUCT_DRM_DRIVER */ + +/* whether si_mem_available() is available */ +#define HAVE_SI_MEM_AVAILABLE 1 + +/* strscpy() is available */ +#define HAVE_STRSCPY 1 + +/* struct dma_buf_ops->allow_peer2peer is available */ +/* #undef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER */ + +/* struct dma_buf_ops->pin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 + +/* struct drm_connector_state->duplicated is available */ +#define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 + +/* struct drm_connector_state->colorspace is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE 1 + +/* struct drm_connector_state->self_refresh_aware is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 + +/* drm_connector->ycbcr_420_allowed is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 + +/* drm_crtc_funcs->enable_vblank() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 + +/* crtc->funcs->gamma_set() wants 5 args */ +/* #undef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS */ + +/* crtc->funcs->gamma_set() wants 6 args */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 + +/* struct drm_crtc_funcs->get_vblank_timestamp() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 + +/* drm_crtc_funcs->{get,verify}_crc_sources() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 + +/* drm_crtc_funcs->page_flip_target() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET 1 + +/* drm_crtc_funcs->page_flip_target() wants ctx parameter */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX 1 + +/* drm_crtc_funcs->set_config() wants ctx parameter */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 + +/* crtc->funcs->set_crc_source() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 + +/* crtc->funcs->set_crc_source() wants 2 args */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE_2ARGS 1 + +/* struct drm_crtc_state->async_flip is available */ +#define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 + +/* struct drm_crtc_state has flag for flip */ +#define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 + +/* struct drm_crtc_state->pageflip_flags is available */ +/* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ + +/* drm_gem_open_object is defined in struct drm_drv */ +/* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + +/* drm_pending_vblank_event->sequence is available */ +#define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 + +/* drm_plane_helper_funcs->atomic_async_check() is available */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 + +/* drm_plane_helper_funcs->prepare_fb() wants const p arg */ +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ + +/* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 + +/* zone->managed_pages is available */ +/* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ + +/* timer_setup() is available */ +#define HAVE_TIMER_SETUP 1 + +/* interval_tree_insert have struct rb_root_cached */ +#define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 + +/* ttm_sg_tt_init() is available */ +#define HAVE_TTM_SG_TT_INIT 1 + +/* __poll_t is available */ +#define HAVE_TYPE__POLL_T 1 + /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_switcheroo_set_dynamic_switch() exist */ +/* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ + +/* vmf_insert_*() are available */ +#define HAVE_VMF_INSERT 1 + +/* vmf_insert_mixed_prot() is available */ +#define HAVE_VMF_INSERT_MIXED_PROT 1 + +/* vmf_insert_pfn_{pmd,pud}() wants 3 args */ +/* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ + +/* vmf_insert_pfn_{pmd,pud}_prot() is available */ +#define HAVE_VMF_INSERT_PFN_PMD_PROT 1 + +/* vmf_insert_pfn_prot() is available */ +#define HAVE_VMF_INSERT_PFN_PROT 1 + +/* vmf_insert_pfn_pud() is available */ +/* #undef HAVE_VMF_INSERT_PFN_PUD */ + +/* vm_fault->{address/vam} is available */ +#define HAVE_VM_FAULT_ADDRESS_VMA 1 + +/* vm_insert_pfn_prot() is available */ +/* #undef HAVE_VM_INSERT_PFN_PROT */ + +/* vm_operations_struct->fault() wants 1 arg */ +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 + +/* wait_queue_entry_t exists */ +#define HAVE_WAIT_QUEUE_ENTRY 1 + +/* zone_managed_pages() is available */ +#define HAVE_ZONE_MANAGED_PAGES 1 + +/* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ +#define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 + +/* __drm_atomic_helper_crtc_destroy_state() wants 1 arg */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_P 1 + +/* __drm_atomic_helper_crtc_reset() is available */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 + +/* __kthread_should_park() is available */ +#define HAVE___KTHREAD_SHOULD_PARK 1 + +/* __print_array is available */ +#define HAVE___PRINT_ARRAY 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From 9b45a8091245dff11be4f428e20091d96c54c1cf Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 24 Mar 2021 17:30:18 +0800 Subject: [PATCH 0582/2070] drm/amdkcl: re-generate the config.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/config/config.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a5ac4170b3f72..e310e9d540d11 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -/* #undef HAVE_ACPI_PUT_TABLE */ +#define HAVE_ACPI_PUT_TABLE 1 /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -32,7 +32,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ +#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -446,6 +446,9 @@ /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 +/* drm_gen_fb_init_with_funcs() is available */ +#define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 + /* drm_get_format_info() is available */ #define HAVE_DRM_GET_FORMAT_INFO 1 From d95028c7f26b62b7f308c9ddb07d5bc75e4bb1c5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 21 Jan 2021 15:02:48 +0800 Subject: [PATCH 0583/2070] drm/amdkcl: rework dma-fence header file handling Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- include/kcl/header/linux/dma-fence-array.h | 11 +++++++++++ include/kcl/header/linux/dma-fence.h | 11 +++++++++++ include/kcl/kcl_fence.h | 7 +------ include/kcl/kcl_fence_array.h | 6 +++--- 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 include/kcl/header/linux/dma-fence-array.h create mode 100644 include/kcl/header/linux/dma-fence.h diff --git a/include/kcl/header/linux/dma-fence-array.h b/include/kcl/header/linux/dma-fence-array.h new file mode 100644 index 0000000000000..49bb1fcd2a798 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-array.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_H) +#include_next +#elif defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#endif + +#endif diff --git a/include/kcl/header/linux/dma-fence.h b/include/kcl/header/linux/dma-fence.h new file mode 100644 index 0000000000000..d4bb6177302a3 --- /dev/null +++ b/include/kcl/header/linux/dma-fence.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 7a869acf02b93..947efbf7e38aa 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -14,13 +14,8 @@ #include #include -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#include -#include -#else #include -#include -#endif +#include #if !defined(HAVE_LINUX_DMA_FENCE_H) #define dma_fence_cb fence_cb diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h index 8bce1cf8ff00c..1e8f37c5864d3 100644 --- a/include/kcl/kcl_fence_array.h +++ b/include/kcl/kcl_fence_array.h @@ -23,10 +23,10 @@ #ifndef AMDKCL_FENCE_ARRAY_H #define AMDKCL_FENCE_ARRAY_H +#include + #if !defined(HAVE_LINUX_DMA_FENCE_H) -#if defined(HAVE_LINUX_FENCE_ARRAY_H) -#include -#else +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) #include /** From fdf1a9eaf7f03c1767e77bfd6ba9630fc174df2e Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 29 Mar 2021 20:24:42 +0800 Subject: [PATCH 0584/2070] drm/amdkcl: fix the autotest of drm_gem_ttm_helper.h Signed-off-by: Shiwu Zhang --- include/kcl/header/drm/drm_gem_ttm_helper.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h index 1f4610148dd07..5612902e4958d 100644 --- a/include/kcl/header/drm/drm_gem_ttm_helper.h +++ b/include/kcl/header/drm/drm_gem_ttm_helper.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_VBLANK_H_H_ -#define _KCL_HEADER_DRM_VBLANK_H_H_ +#ifndef _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ +#define _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ -#ifdef HAVE_DRM_DRM_DRM_GEM_TTM_HELPER_H +#ifdef HAVE_DRM_DRM_GEM_TTM_HELPER_H #include_next #endif From 299c846db66f71de03f86c7f187553d6615f1152 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:46:45 +0800 Subject: [PATCH 0585/2070] drm/amdkcl: clear up the license left out during rebase Signed-off-by: Shiwu Zhang Signed-off-by: Asher Song --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 2 + .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 22 +++++++++- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 30 +++++++++++++- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 32 ++++++++++++++- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 1 + drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 21 ---------- .../kcl_amdgpu_drm_gem_framebuffer_helper.h | 30 ++++++++++++++ drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 28 ++++++++++++- .../backport/kcl_drm_gem_framebuffer_helper.c | 40 +++++++++++++++++++ .../backport/kcl_drm_atomic_helper_backport.h | 28 ++++++++++++- include/kcl/backport/kcl_drm_encoder.h | 1 + .../backport/kcl_drm_vma_manager_backport.h | 1 + include/kcl/backport/kcl_hmm.h | 9 ++++- include/kcl/backport/kcl_pci_backport.h | 2 +- include/kcl/kcl_device.h | 5 +++ include/kcl/kcl_dma_mapping.h | 1 + include/kcl/kcl_drm_fb.h | 1 + include/kcl/kcl_kernel.h | 1 + include/kcl/kcl_kthread.h | 1 + include/kcl/kcl_mm.h | 1 + include/kcl/kcl_pci.h | 1 + include/kcl/kcl_preempt.h | 2 +- include/kcl/kcl_rcupdate.h | 19 ++++++++- include/kcl/kcl_task_barrier.h | 24 ++++++++++- include/kcl/kcl_version.h | 2 +- 27 files changed, 276 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 3e2cf46b8526c..58beb9fcedf38 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -30,6 +30,7 @@ #include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c and modified for KCL */ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, struct drm_plane_state *state) { @@ -49,6 +50,7 @@ EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); #endif #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c */ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index a467ebb08a8f3..ebcb2ae541c33 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -1,4 +1,24 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ #include #ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index abdd2c27e157b..11e5390896f68 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -1,4 +1,32 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ #include #include #include diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index 9d5358ca93b48..f5d947730e628 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -1,6 +1,36 @@ -/* SPDX-License-Identifier: MIT */ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/************************************************************************** + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ #include +/* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ #ifndef HAVE_VMF_INSERT_MIXED_PROT vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, pfn_t pfn, pgprot_t pgprot) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index a49eef473bef2..96fc94dc7c244 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -149,6 +149,7 @@ EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); #endif /* HAVE_PCI_PR3_PRESENT */ #ifdef AMDKCL_CREATE_MEASURE_FILE +/* Copied from drivers/pci/pci-sysfs.c */ static ssize_t max_link_speed_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 115fc89f8204f..ba3805d29cbc3 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ + kcl_drm_gem_framebuffer_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9ecde4e4e59e2..95033ba9e46a4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -60,6 +60,7 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_drm_gem_ttm_helper.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 40a89aea46e78..b67bfda700d77 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -39,25 +39,4 @@ void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif -static inline -void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) -{ -#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - if (fb) - fb->obj[index] = obj; -#else - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)index; /* for compile un-used warning */ - if (afb) - afb->obj = obj; -#endif -} -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane); -void drm_gem_fb_destroy(struct drm_framebuffer *fb); -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle); -#endif - #endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h new file mode 100644 index 0000000000000..bbd3326b824bf --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h @@ -0,0 +1,30 @@ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ + +#include +#include "amdgpu.h" + +static inline +void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) +{ +#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + if (fb) + fb->obj[index] = obj; +#else + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)index; /* for compile un-used warning */ + if (afb) + afb->obj = obj; +#endif +} + +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +/* Copied from include/drm/drm_gem_framebuffer_helper.h */ +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane); +void drm_gem_fb_destroy(struct drm_framebuffer *fb); +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c index 0ad2345d7061a..0d243c59b5f6a 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -1,4 +1,30 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include #include "amdgpu.h" diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c new file mode 100644 index 0000000000000..1f68cf8bbe2b3 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * drm gem framebuffer helper functions + * + * Copyright (C) 2017 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_gem_framebuffer_helper.c and modified for KCL */ +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane) +{ + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)plane; /* for compile un-used warning */ + if (afb) + return afb->obj; + else + return NULL; +} + +void drm_gem_fb_destroy(struct drm_framebuffer *fb) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + drm_gem_object_put(amdgpu_fb->obj); + + drm_framebuffer_cleanup(fb); + kfree(fb); +} + +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + return drm_gem_handle_create(file, amdgpu_fb->obj, handle); +} +#endif diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index 1edfc203e12ce..eaa2464b77353 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -1,4 +1,30 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ #ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H #define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h index 07e3a75541b80..0efc8f747defd 100644 --- a/include/kcl/backport/kcl_drm_encoder.h +++ b/include/kcl/backport/kcl_drm_encoder.h @@ -37,6 +37,7 @@ #include #include +/* Copied from drivers/gpu/drm/drm_edid.c and modified for KCL */ #if defined(HAVE_DRM_EDID_TO_ELD) static inline int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h index 0a7e1bf34bd82..9893688f6fac2 100644 --- a/include/kcl/backport/kcl_drm_vma_manager_backport.h +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -29,6 +29,7 @@ #include #include +/* Copied from include/drm/drm_vma_manager.h */ #if (BITS_PER_LONG == 64) #ifdef DRM_FILE_PAGE_OFFSET_START #undef DRM_FILE_PAGE_OFFSET_START diff --git a/include/kcl/backport/kcl_hmm.h b/include/kcl/backport/kcl_hmm.h index 233b0cbda947a..7dad7453aaa89 100644 --- a/include/kcl/backport/kcl_hmm.h +++ b/include/kcl/backport/kcl_hmm.h @@ -1,4 +1,11 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Red Hat Inc. + * + * Authors: Jérôme Glisse + * + * See Documentation/vm/hmm.rst for reasons and overview of what HMM is. + */ #ifndef _KCL_BACKPORT_KCL_HMM_H #define _KCL_BACKPORT_KCL_HMM_H diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 21799422a6abd..2cf66ef4aa69f 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_PCI_BACKPORT_H #define AMDKCL_PCI_BACKPORT_H diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index d8d3ee5263d06..b2e3a9d24811b 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -1,9 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for the NVM Express interface + * Copyright (c) 2011-2014, Intel Corporation. + */ #ifndef AMDKCL_DEVICE_H #define AMDKCL_DEVICE_H #include +/* Copied from include/linux/dev_printk.h */ #if !defined(dev_err_once) #ifdef CONFIG_PRINTK #define dev_level_once(dev_level, dev, fmt, ...) \ diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 73070e3605f89..e9321cdb661fd 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -122,6 +122,7 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, /* * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") + * Copied from include/linux/scatterlist.h */ #ifndef for_each_sgtable_sg #define for_each_sgtable_sg(sgt, sg, i) \ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index f4a9aa8c8216c..9bc9148fc5854 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -34,6 +34,7 @@ #include #include +/* Copied from include/drm/drm_fb_helper.h */ /* * Don't add fb_debug_* since the legacy drm_fb_helper_debug_* has segfault * history: diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index ef5bdee50ee36..d055fad138c19 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -16,6 +16,7 @@ #endif #ifndef __GFP_RETRY_MAYFAIL +/* Copied from include/linux/gfp.h and modified for KCL */ #define __GFP_RETRY_MAYFAIL __GFP_NORETRY #endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 5bdcc30bdf314..4b2ad6841c793 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -6,6 +6,7 @@ #include #include +/* Copied from v5.7-13665-g9bf5b9eb232b kernel/kthread.c */ #ifndef HAVE_KTHREAD_USE_MM static inline void kthread_use_mm(struct mm_struct *mm) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 47e575291a832..856be87fc0043 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -31,6 +31,7 @@ static inline bool fault_flag_allow_retry_first(unsigned int flags) #endif #if !defined(HAVE_ZONE_MANAGED_PAGES) +/* Copied from v4.20-6505-g9705bea5f833 include/linux/mmzone.h and modified for KCL */ static inline unsigned long zone_managed_pages(struct zone *zone) { #if defined(HAVE_STRUCT_ZONE_MANAGED_PAGES) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index e6bbb2a4924fa..3404986968bbd 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -131,6 +131,7 @@ static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) #endif } +/* Copied from v5.1-rc1-5-g4e544bac8267 include/linux/pci.h */ #if !defined(HAVE_PCI_DEV_ID) static inline u16 pci_dev_id(struct pci_dev *dev) { diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h index d76961463a6e3..1e59cbca1bf73 100644 --- a/include/kcl/kcl_preempt.h +++ b/include/kcl/kcl_preempt.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_PREEMPT_H #define AMDKCL_PREEMPT_H #include diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h index ec31bae327ead..da63bf6d4f9e0 100644 --- a/include/kcl/kcl_rcupdate.h +++ b/include/kcl/kcl_rcupdate.h @@ -1,4 +1,21 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Read-Copy Update mechanism for mutual exclusion + * + * Copyright IBM Corporation, 2001 + * + * Author: Dipankar Sarma + * + * Based on the original work by Paul McKenney + * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. + * Papers: + * http://www.rdrop.com/users/paulmck/paper/rclockpdcsproof.pdf + * http://lse.sourceforge.net/locking/rclock_OLS.2001.05.01c.sc.pdf (OLS2001) + * + * For detailed explanation of Read-Copy Update mechanism see - + * http://lse.sourceforge.net/locking/rcupdate.html + * + */ #ifndef AMDKCL_RCUPDATE_H #define AMDKCL_RCUPDATE_H diff --git a/include/kcl/kcl_task_barrier.h b/include/kcl/kcl_task_barrier.h index 341fe8e02a9d9..315bff4402dbc 100644 --- a/include/kcl/kcl_task_barrier.h +++ b/include/kcl/kcl_task_barrier.h @@ -1,10 +1,32 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ #ifndef AMDKCL_DRM_TASK_BARRIER_H #define AMDKCL_DRM_TASK_BARRIER_H #ifdef HAVE_DRM_TASK_BARRIER_H #include #else +/* Copied from include/drm/task_barrier.h */ /* * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ diff --git a/include/kcl/kcl_version.h b/include/kcl/kcl_version.h index 4a470ef6dbbc7..59a859a26a540 100644 --- a/include/kcl/kcl_version.h +++ b/include/kcl/kcl_version.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_VERSION_H #define AMDKCL_VERSION_H From cddeca9789705f787a0ccbb6823e4356515a3b2a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 14:47:46 +0800 Subject: [PATCH 0586/2070] drm/amdkcl: add DPM_FLAG_SMART_SUSPEND and DPM_FLAG_MAY_SKIP_RESUME macro This patch is caused by following commit 'drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and DPM_FLAG_SMART_SUSPEND flags (v2)' v5.11-2760-g3d6ae23c0594 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- include/kcl/kcl_pm.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 157fc65f14708..37c761718589e 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -7,6 +7,7 @@ #ifndef KCL_KCL_PM_H #define KCL_KCL_PM_H +#include #include /* @@ -17,4 +18,21 @@ #define DPM_FLAG_NO_DIRECT_COMPLETE DPM_FLAG_NEVER_SKIP #endif + +/* + * v4.15-rc1-1-g0d4b54c6fee8 + * PM / core: Add LEAVE_SUSPENDED driver flag + */ +#ifndef DPM_FLAG_SMART_SUSPEND +#define DPM_FLAG_SMART_SUSPEND BIT(2) +#endif + +/* + * v5.7-rc2-8-g2a3f34750b8b + * PM: sleep: core: Rename DPM_FLAG_LEAVE_SUSPENDED + */ +#ifndef DPM_FLAG_MAY_SKIP_RESUME +#define DPM_FLAG_MAY_SKIP_RESUME BIT(3) +#endif + #endif From 9b2ec60a16255dbe33143295fc22e5ddd26c9f11 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 23 Mar 2021 15:41:51 +0800 Subject: [PATCH 0587/2070] drm/amdkcl: adapt code using drm_gem_fb_get_obj for legacy os This patch is caused by following commit 'drm/amdgpu: clean up non-DC suspend/resume handling' v5.11-2764-ga7c22df2fd07 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 362b26b74c25a..84bffe8ed407d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1817,10 +1817,10 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) } } - if (!fb || !fb->obj[0]) + if (!fb || !drm_gem_fb_get_obj(fb, 0)) continue; - robj = gem_to_amdgpu_bo(fb->obj[0]); + robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { From 6807148b18ade61238df9f493a987d38d69b3314 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 8 Sep 2020 17:25:51 +0800 Subject: [PATCH 0588/2070] drm/amdkfd: add debug support for aldebaran The following commits have been squashed/touched up from npi and will go into dkms-staging: 'commit 156affb5f5d7 ("drm/amdkfd: update per-vmid registers for debug attach/detach")' 'commit 656b84994342 ("drm/amdgpu: fix lock scheme on aldebaran debug functions")' 'commit a376539fcd40 ("drm/amdkfd: add precise memory operations enable for aldebaran")' 'commit 32548be937a8 ("drm/amdgpu: unify debug setting fixes in aldebaran")' 'commit fc209adaf7ce ("drm/amdgpu: add new address watch functions to aldebaran")' The following has been omitted: References to anything emulation related Experimental host trap commands Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index 7e9f7a280c1b9..c55bc29a2c77c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -26,6 +26,7 @@ #include "amdgpu_amdkfd_aldebaran.h" #include "gc/gc_9_4_2_offset.h" #include "gc/gc_9_4_2_sh_mask.h" +#include "soc15.h" #include /* From 2e2a7634a36498aaaa2794bc6a8186b34faf3391 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 31 Mar 2021 11:03:09 +0800 Subject: [PATCH 0589/2070] drm/amdkcl: fake the sysfs_emit This is caused by "Convert sysfs sprintf/snprintf family to sysfs_emit" v5.11-2844-g5f7dd9b5c2d3 Signed-off-by: Leslie Shi Reviewed by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c | 32 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 4 +-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 13 +++++++++ include/kcl/kcl_sysfs_emit.h | 25 ++++++++++++++++ 7 files changed, 75 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 create mode 100644 include/kcl/kcl_sysfs_emit.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index c29acce60a682..ca9832a6560c3 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,6 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o +amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c new file mode 100644 index 0000000000000..798745cbfff91 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fs/sysfs/file.c - sysfs regular (text) file implementation + * + * Copyright (c) 2001-3 Patrick Mochel + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include +#include + +/* Copied from fs/sysfs/file.c */ +#ifndef HAVE_SYSFS_EMIT +int sysfs_emit(char *buf, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf), + "invalid sysfs_emit: buf:%p\n", buf)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf, PAGE_SIZE, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 95033ba9e46a4..ac77487c8ecd0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -56,6 +56,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e310e9d540d11..4111272193b18 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -888,8 +888,8 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* timer_setup() is available */ -#define HAVE_TIMER_SETUP 1 +/* sysfs_emit() is available */ +#define HAVE_SYSFS_EMIT 1 /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 119bab4e0fbfb..ac45a034a4cc2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -100,6 +100,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE + AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 new file mode 100644 index 0000000000000..e9f403134af83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v5.9-rc5-23-g2efc459d06f1 +dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # to format sysfs output +AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit], + [fs/sysfs/file.c], [ + AC_DEFINE(HAVE_SYSFS_EMIT, 1, + [sysfs_emit() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_sysfs_emit.h b/include/kcl/kcl_sysfs_emit.h new file mode 100644 index 0000000000000..ab87e74f817ff --- /dev/null +++ b/include/kcl/kcl_sysfs_emit.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sysfs.h - definitions for the device driver filesystem + * + * Copyright (c) 2001,2002 Patrick Mochel + * Copyright (c) 2004 Silicon Graphics, Inc. + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include + +#ifndef HAVE_SYSFS_EMIT +#ifdef CONFIG_SYSFS +__printf(2, 3) +int sysfs_emit(char *buf, const char *fmt, ...); +#else +__printf(2, 3) +static inline int sysfs_emit(char *buf, const char *fmt, ...) +{ + return 0; +} +#endif +#endif From 8684dd0a46f5cf87796b3d2506c8e28c62f63b4e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 10:40:27 +0800 Subject: [PATCH 0590/2070] drm/amdkcl: Test whether io_mapping_unmap_local() is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- .../amd/dkms/m4/io-mapping-map-local-wc.m4 | 15 +++++++++++ .../drm/amd/dkms/m4/io-mapping-unmap-local.m4 | 15 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_io-mapping.h | 26 +++++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 create mode 100644 include/kcl/kcl_io-mapping.h diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 new file mode 100644 index 0000000000000..72ba661169b58 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_map_local_wc(NULL, 0); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_MAP_LOCAL_WC, 1, [io_mapping_map_local_wc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 new file mode 100644 index 0000000000000..282b77e11e1c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_unmap_local(NULL); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_UNMAP_LOCAL, 1, [io_mapping_unmap_local() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ac45a034a4cc2..37577d387d015 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -107,6 +107,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_AMDGPU_DRM_DISPLAY_INFO + AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL + AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 2de8df93b5298..496e1bb82f3dd 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -15,5 +15,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_io-mapping.h b/include/kcl/kcl_io-mapping.h new file mode 100644 index 0000000000000..6551e94cf3551 --- /dev/null +++ b/include/kcl/kcl_io-mapping.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright © 2008 Keith Packard + */ + +#ifndef KCL_KCL_IO_MAPPING_H +#define KCL_KCL_IO_MAPPING_H + +#include + +#ifndef HAVE_IO_MAPPING_UNMAP_LOCAL +static inline void io_mapping_unmap_local(void __iomem *vaddr) +{ + io_mapping_unmap(vaddr); +} +#endif + +#ifndef HAVE_IO_MAPPING_MAP_LOCAL_WC +static inline void __iomem * +io_mapping_map_local_wc(struct io_mapping *mapping, unsigned long offset) +{ + return io_mapping_map_wc(mapping, offset, PAGE_SIZE); +} +#endif + +#endif /* KCL_KCL_IO_MAPPING_H */ From d99025be7e1518be3cbf6584e6508b8df06e6800 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 14:01:12 +0800 Subject: [PATCH 0591/2070] drm/amdkcl: Test whether kmap_local_* is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/dkms/m4/highmem-internal.m4 | 6 +-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_highmem-internal.h | 41 +++++++++++++++++++ 4 files changed, 46 insertions(+), 3 deletions(-) create mode 100644 include/kcl/kcl_highmem-internal.h diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 index b2614eabab932..326a3fc8e64c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -4,12 +4,12 @@ dnl # mm/highmem: Provide kmap_local* dnl # AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include ], [ pgprot_t prot; kmap_local_page_prot(NULL, prot); - ], [], [], [ + ], [ AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 37577d387d015..d75bfc4d59667 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,6 +109,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC + AC_AMDGPU_KMAP_LOCAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 496e1bb82f3dd..d7a9bfaa2ae11 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -16,5 +16,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_highmem-internal.h b/include/kcl/kcl_highmem-internal.h new file mode 100644 index 0000000000000..7304f188d7c2d --- /dev/null +++ b/include/kcl/kcl_highmem-internal.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_KCL_HIGHMEM_INTERNAL_H +#define KCL_KCL_HIGHMEM_INTERNAL_H + +#include +#include + +#ifndef HAVE_KMAP_LOCAL + +static inline void *kmap_local_page(struct page *page) +{ + return page_address(page); +} + +static inline void *kmap_local_page_prot(struct page *page, pgprot_t prot) +{ + return kmap_local_page(page); +} + +#endif + +#ifndef kunmap_local + +static inline void __kunmap_local(void *addr) +{ +#ifdef ARCH_HAS_FLUSH_ON_KUNMAP + kunmap_flush_on_unmap(addr); +#endif +} + +#define kunmap_local(__addr) \ +do { \ + BUILD_BUG_ON(__same_type((__addr), struct page *)); \ + __kunmap_local(__addr); \ +} while (0) +#endif /* kunmap_local */ + + + +#endif From 182d0b1adea6efc9a139e60550bb60fdbdb5c3ed Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 16:01:03 +0800 Subject: [PATCH 0592/2070] drm/amdkcl: fix build error of amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 9adb448c4f9df..62ff5ea9cf7bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -799,7 +799,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d2a7e7004262c..2e617934195fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1536,7 +1536,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, */ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); struct dma_resv_iter cursor; struct dma_fence *fence; From 3fdbaf7fd4f75bb2e8cdc6a1f3deb1302d6a98d7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 10:25:47 +0800 Subject: [PATCH 0593/2070] drm/amdkcl: Test whether struct drm_dp_aux has member drm_dev This is caused by 6cba3fe43341 "drm/dp: Add backpointer to drm_device in drm_dp_aux" v5.12-rc7-1495-g6cba3fe43341 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 492813ab1b541..9370fb91ca909 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -189,7 +189,10 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) { amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; + +#ifdef HAVE_DRM_DP_AUX_DRM_DEV amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; +#endif drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 new file mode 100644 index 0000000000000..d851ad71eab97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.12-rc7-1495-g6cba3fe43341 +dnl # drm/dp: Add backpointer to drm_device in drm_dp_aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux dda; + dda.drm_dev = NULL; + ], [],[],[ + AC_DEFINE(HAVE_DRM_DP_AUX_DRM_DEV, 1, + [struct drm_dp_aux has member named 'drm_dev']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d75bfc4d59667..5fe91a208583a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -110,6 +110,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_AMDGPU_KMAP_LOCAL + AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d1dcdc7a51556c915b59102d83209d120f847155 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 10:39:04 +0800 Subject: [PATCH 0594/2070] drm/amdkcl: Test whether drm_dp_link_train_clock_recovery_delay() has 2 args This is caused by 9e9866664456 "drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()" v5.12-rc7-1497-g9e9866664456 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 4 ++++ .../drm-dp-link-train-clock-recovery-delay.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 9370fb91ca909..2d9cffe6c4e52 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -616,7 +616,11 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; voltage = 0xff; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) < 0) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 new file mode 100644 index 0000000000000..4d8e0f733eb7e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1497-g9e9866664456 +dnl # drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + drm_dp_link_train_clock_recovery_delay(aux, dpcd); + ], [drm_dp_link_train_clock_recovery_delay],[drm/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, + [drm_dp_link_train_clock_recovery_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5fe91a208583a..f35dcc8822f3e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -111,6 +111,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_AMDGPU_KMAP_LOCAL AC_AMDGPU_DRM_DP_AUX_DRM_DEV + AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 5a55f3c38ba964af17ff6f606d43fcb4238e2cb2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 13:27:27 +0800 Subject: [PATCH 0595/2070] drm/amdkcl: Test whether drm_dp_link_train_channel_eq_delay() has 2 args This is caused by 0c4fada608c1 "drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay()" v5.12-rc7-1498-g0c4fada608c1 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 4 ++++ .../m4/drm-dp-link-train-channel-eq-delay.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 2d9cffe6c4e52..b81674da7ed76 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -685,7 +685,11 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; channel_eq = false; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_channel_eq_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) < 0) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 new file mode 100644 index 0000000000000..664b63498814e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1498-g0c4fada608c1 +dnl # drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + drm_dp_link_train_channel_eq_delay(aux, dpcd); + ], [drm_dp_link_train_channel_eq_delay],[drm/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, + [drm_dp_link_train_channel_eq_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f35dcc8822f3e..0857aa17d6f8c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -112,6 +112,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KMAP_LOCAL AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY + AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From fe1e495c99991594c854fbdfb36e3a2752c28518 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 31 Mar 2021 15:17:23 +0800 Subject: [PATCH 0596/2070] drm/amdkcl: access drm_plane index field using drm_plane_index This is caused by "drm/amd/display: Use appropriate DRM_DEBUG_... level" v5.11-2836-g27f1f74cc17e Signed-off-by: Leslie Shi Reviewed by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1a8acd142611d..7740e3f9b52eb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10026,7 +10026,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, afb->tmz_surface); drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", - new_plane_state->plane->index, + drm_plane_index(new_plane_state->plane), bundle->plane_infos[planes_count].dcc.enable); bundle->surface_updates[planes_count].plane_info = From d209d687b441fa734e7e3984bc1f067795d0dbd9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 1 Apr 2021 16:59:38 +0800 Subject: [PATCH 0597/2070] drm/amdkcl: wrap the code under HAVE_KTIME_IS_UNION This is caused by "drm/amd/display: Add refresh rate trace" v5.11-2869-g3b8fa2a4ed4c Signed-off-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 | 17 +++++++++++++++++ 5 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7740e3f9b52eb..82e79c310c099 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -582,9 +582,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; +#ifndef HAVE_KTIME_IS_UNION struct drm_device *drm_dev; struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; +#endif unsigned long flags; int vrr_active; @@ -592,6 +594,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); +#ifndef HAVE_KTIME_IS_UNION drm_dev = acrtc->base.dev; vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); @@ -603,6 +606,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) ktime_divns(NSEC_PER_SEC, frame_duration_ns)); atomic64_set(&irq_params->previous_timestamp, vblank->time); } +#endif drm_dbg_vbl(drm_dev, "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index 045283ad899b4..cf168868a0f16 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -685,6 +685,7 @@ TRACE_EVENT(amdgpu_dmub_trace_high_irq, __entry->param0, __entry->param1) ); +#ifndef HAVE_KTIME_IS_UNION TRACE_EVENT(amdgpu_refresh_rate_track, TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz), TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz), @@ -703,6 +704,7 @@ TRACE_EVENT(amdgpu_refresh_rate_track, __entry->refresh_rate_hz, __entry->refresh_rate_ns) ); +#endif TRACE_EVENT(dcn_fpu, TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth), diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4111272193b18..a939444d95703 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -648,6 +648,9 @@ /* ktime_get_real_seconds() is available */ #define HAVE_KTIME_GET_REAL_SECONDS 1 +/* ktime_t is union */ +/* #undef HAVE_KTIME_IS_UNION */ + /* kvcalloc() is available */ #define HAVE_KVCALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0857aa17d6f8c..40fda1fe1fbd0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_SYSFS_EMIT + AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 new file mode 100644 index 0000000000000..0bd3f631e535f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.18-rc1-35-ga8802d97e733 +dnl # ktime: Get rid of the union +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_IS_UNION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t t; + t.tv64 = 0; + ], [ + AC_DEFINE(HAVE_KTIME_IS_UNION, 1, + [ktime_t is union]) + ]) + ]) +]) From e7dec227e2742b55eaa7b2140ec5f88bf43632b8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Apr 2021 16:26:22 +0800 Subject: [PATCH 0598/2070] drm/amdkcl: access resv field using amdkcl_ttm_resvp This is caused by "drm/amdgpu: reserve fence slot to update page table" v5.11-2904-gf63da9ae7584 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 2e617934195fb..f59f50e9a58ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3032,7 +3032,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, value = 0; } - r = dma_resv_reserve_fences(root->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root->tbo), 1); if (r) { pr_debug("failed %d to reserve fence slot\n", r); goto error_unlock; From 373e59b5267068810efb9c01f778e878f2690886 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 7 Apr 2021 14:56:34 +0800 Subject: [PATCH 0599/2070] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add MST capability to trigger_hotplug interface" v5.11-2937-gd39b43894f55 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 15190785f1b7d..47e135ceb41e1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4011,6 +4011,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Sets trigger hpd for MST topologies. * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. @@ -4084,7 +4085,7 @@ static int trigger_hpd_mst_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, trigger_hpd_mst_set, "%llu\n"); - +#endif /* * Sets the force_timing_sync debug option from the given string. From a2a7336b42153c02df52df0f189555ec1f461f48 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 7 Apr 2021 16:15:49 +0800 Subject: [PATCH 0600/2070] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add debugfs entry for LTTPR register status" v5.11-2928-g4721d0678f7c Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Change-Id: I84809cf9dabb0b697c76bb8bd24e9e043e532b65 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 47e135ceb41e1..9354be306c398 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -575,6 +575,7 @@ static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, return result; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int dp_lttpr_status_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -609,6 +610,7 @@ static int dp_lttpr_status_show(struct seq_file *m, void *unused) seq_puts(m, "\n"); return 0; } +#endif static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) @@ -2980,7 +2982,9 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); +#endif DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); @@ -3100,7 +3104,9 @@ static const struct { } dp_debugfs_entries[] = { {"link_settings", &dp_link_settings_debugfs_fops}, {"phy_settings", &dp_phy_settings_debugfs_fop}, +#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"lttpr_status", &dp_lttpr_status_fops}, +#endif {"test_pattern", &dp_phy_test_pattern_fops}, {"hdcp_sink_capability", &hdcp_sink_capability_fops}, {"sdp_message", &sdp_message_fops}, From 2a679b277934ec556749c8359748460de9702836 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 9 Apr 2021 11:01:14 +0800 Subject: [PATCH 0601/2070] drm/amdkcl: fix pytorch test memory page fault Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index f59f50e9a58ce..d50bac89ba8bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1289,6 +1289,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t flags; bool uncached; int r; + struct amdgpu_device *bo_adev; amdgpu_sync_create(&sync); if (clear) { @@ -1338,8 +1339,6 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, } if (bo) { - struct amdgpu_device *bo_adev; - flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); if (amdgpu_bo_encrypted(bo)) @@ -1382,6 +1381,18 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, amdgpu_gmc_get_vm_pte(adev, vm, bo, mapping->flags, &update_flags); + if (adev != bo_adev && + !(update_flags & AMDGPU_PTE_SYSTEM) && + !mapping->bo_va->is_xgmi) { + if (amdgpu_device_is_peer_accessible(bo_adev, adev)) { + update_flags |= AMDGPU_PTE_SYSTEM; + vram_base = bo_adev->gmc.aper_base; + } else { + DRM_DEBUG_DRIVER("Failed to map the VRAM for peer device access.\n"); + return -EINVAL; + } + } + trace_amdgpu_vm_bo_update(mapping); r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, From 433bb4644eee17b6a86fa48852b29f60ce56732f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 13 Apr 2021 13:10:01 +0800 Subject: [PATCH 0602/2070] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add debugfs to repress HPD and HPR_RX IRQs" v5.11-2975-g14bc8d04dd21 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 9354be306c398..06fff21e5f473 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4128,6 +4128,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, #endif +#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Disables all HPD and HPD RX interrupt handling in the * driver when set to 1. Default is 0. @@ -4157,6 +4158,7 @@ static int disable_hpd_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); +#endif /* * Prints hardware capabilities. These are used for IGT testing. From 11e3b092a17ac6773bcd638e8c29437031ccf1df Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 15 Apr 2021 14:03:09 +0800 Subject: [PATCH 0603/2070] drm/amdgpu: use ratelimited print in sdma4 interrupt dev_*_ratelimited printing will avoid dmesg flush. Signed-off-by: Feifei Xu Acked-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index c3baaa0959b95..64fef615642cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2178,7 +2178,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, instance = sdma_v4_0_irq_id_to_seq(entry->client_id); if (instance < 0 || instance >= adev->sdma.num_instances) { - dev_err(adev->dev, "sdma instance invalid %d\n", instance); + dev_err_ratelimited(adev->dev, "sdma instance invalid %d\n", instance); return -EINVAL; } From 56ed86f357a08929f0d212a48c4dbfe799cf5495 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 20 Apr 2021 15:53:54 +0800 Subject: [PATCH 0604/2070] drm/amd/amdgpu: Add missing bo size setting for bo_create MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing bp.bo_ptr_size setting in amdgpu_gem_prime_import_sg_table Signed-off-by: Chengming Gui Reviewed-by: Christian König Reviewed-by: Guchun Chen Change-Id: Ibe8ed71e797c12587684b2604c76e513adf98803 --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 62ff5ea9cf7bb..89e90afd122fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -657,6 +657,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bp.flags = 0; bp.type = ttm_bo_type_sg; bp.resv = resv; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); dma_resv_lock(resv, NULL); ret = amdgpu_bo_create(adev, &bp, &bo); if (ret) From 289dffdf436502f134023f48b73fef9d7be42f89 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 16 Apr 2021 15:53:12 +0800 Subject: [PATCH 0605/2070] drm/amdkcl: replace vm parameter with drm_priv This is caused by "drm/amdkfd: Use drm_priv to pass VM from KFD to amdgpu" v5.11-3019-g9be47f808bf7 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index d52e0f38eef1c..88ab20909ce39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -135,7 +135,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, - va_addr, pdd->vm, + va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, mmap_offset); if (r) @@ -248,7 +248,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, } mem = (struct kgd_mem *)kfd_bo->mem; - r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->vm, mem, + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, &ipc_obj); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index d9856191ab7eb..ceabdb3680a64 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -208,7 +208,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->vm, + ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->drm_priv, pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -259,7 +259,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(kgd, pdd->vm); + amdgpu_amdkfd_rlc_spm_release(kgd, pdd->drm_priv); amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From f4edb2b1f2fc2c269b4f33c0e7539f1825cbca34 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 24 Feb 2020 21:17:30 -0500 Subject: [PATCH 0606/2070] drm/amdkcl: move kcl part for hmm into amdgpu_mn Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index f103284f1ffd9..f6d0d49ce4ccb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -802,6 +802,21 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) bo->notifier.mm = NULL; } +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif + int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, @@ -820,10 +835,20 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, } hmm_range->notifier = notifier; +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + hmm_range->flags = hmm_range_flags; + hmm_range->values = hmm_range_values; + hmm_range->pfn_shift = PAGE_SHIFT; + hmm_range->default_flags = hmm_range_flags[HMM_PFN_VALID]; + if (!readonly) + hmm_range->default_flags |= hmm_range->flags[HMM_PFN_WRITE]; + hmm_range->pfns = (uint64_t *)pfns; +#else hmm_range->default_flags = HMM_PFN_REQ_FAULT; if (!readonly) hmm_range->default_flags |= HMM_PFN_REQ_WRITE; hmm_range->hmm_pfns = pfns; +#endif hmm_range->start = start; end = start + npages * PAGE_SIZE; hmm_range->dev_private_owner = owner; @@ -839,8 +864,16 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, retry: hmm_range->notifier_seq = mmu_interval_read_begin(notifier); r = hmm_range_fault(hmm_range); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if (unlikely(r <= 0)) { +#else if (unlikely(r)) { +#endif +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout)) +#else if (r == -EBUSY && !time_after(jiffies, timeout)) +#endif goto retry; goto out_free_pfns; } From a68f624f6ec1f6b0232208e2fc02038a9bf47ad4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 11:42:37 +0800 Subject: [PATCH 0607/2070] drm/amdkcl: adapt to dev_pagemap->range update Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 27 ++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 10bc81ce37cbf..ad6fcc0ef2e09 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -212,7 +212,11 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence) unsigned long svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) { +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr + adev->kfd.pgmap.range.start) >> PAGE_SHIFT; +#else + return (addr + adev->kfd.dev->pgmap.res.start) >> PAGE_SHIFT; +#endif } static void @@ -242,7 +246,12 @@ svm_migrate_addr(struct amdgpu_device *adev, struct page *page) unsigned long addr; addr = page_to_pfn(page) << PAGE_SHIFT; +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr - adev->kfd.pgmap.range.start); +#else + return (addr - adev->kfd.dev->pgmap.res.start); +#endif + } static struct page * @@ -1044,20 +1053,34 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) * should remove reserved size */ size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) { +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = adev->gmc.aper_base; pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#else + pgmap->res.start = adev->gmc.aper_base; + pgmap->res.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#endif pgmap->type = MEMORY_DEVICE_COHERENT; - } else { + } else +#endif + { res = devm_request_free_mem_region(adev->dev, &iomem_resource, size); if (IS_ERR(res)) return PTR_ERR(res); +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = res->start; pgmap->range.end = res->end; +#else + pgmap->res.start = res->start; + pgmap->res.end = res->end; +#endif pgmap->type = MEMORY_DEVICE_PRIVATE; } - pgmap->nr_range = 1; pgmap->ops = &svm_migrate_pgmap_ops; pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); pgmap->flags = 0; From 86fcc21c2034f427affc0536b1364770fa015b92 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 11:46:35 +0800 Subject: [PATCH 0608/2070] drm/amdkcl: enable HSA_AMD_SVM in dkms package Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/svm.m4 | 21 +++++++++++++++++++++ 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/svm.m4 diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index cfe73b92bcad9..4fc3b8e5ba5a4 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -158,6 +158,11 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +ifeq ($(call _is_kcl_macro_defined,HAVE_HSA_AMD_SVM_ENABLED),y) +export CONFIG_HSA_AMD_SVM=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +endif + export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a939444d95703..d20f61bb5f707 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -603,6 +603,9 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 +/* dev_pagemap->owner is available */ +#define HAVE_HSA_AMD_SVM_ENABLED 1 + /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 40fda1fe1fbd0..0351a62453a1f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP + AC_AMDGPU_HSA_AMD_SVM AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 new file mode 100644 index 0000000000000..ef2c930e21391 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma +dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap +dnl # +AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + [dev_pagemap->owner is available]) + ]) + ]) +]) + From 0fcfb32d4fc2c8e6cd64eba0291781a5bcb27496 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 14:10:59 +0800 Subject: [PATCH 0609/2070] drm/amdkcl: test for migrate_vma->pgmap_owner kernel 5.8 doesnot have migrate_vma.pgmap_owner, it uses migrate_vma.src_owner=NULL for system memory and migrate_vma.src_ovner=adev for device memory. Kernel 5.9 and 5.11 add migrate_vma.pgmap_owner, and migrate_vma.flags to distinguish system memory or device memory. Signed-off-by: Flora Cui Signed-off-by: Philip Yang Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/svm.m4 | 17 +++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index ad6fcc0ef2e09..488bace2256c8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -419,8 +419,12 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#else + migrate.src_owner = NULL; +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t), @@ -718,11 +722,15 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; +#else + migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t), @@ -1084,6 +1092,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) pgmap->ops = &svm_migrate_pgmap_ops; pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); pgmap->flags = 0; + /* Device manager releases device-specific resources, memory region and * pgmap when driver disconnects from device. */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d20f61bb5f707..803e7b61e529c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -732,6 +732,9 @@ /* mem_encrypt_active() is available */ #define HAVE_MEM_ENCRYPT_ACTIVE 1 +/* migrate_vma->pgmap_owner is available */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 + /* mmgrab() is available */ #define HAVE_MMGRAB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index ef2c930e21391..0deabfae97260 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -1,3 +1,18 @@ +dnl # +dnl # v5.8-rc4-7-g5143192cd410 mm/migrate: add a flags parameter to migrate_vma +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma *migrate = NULL; + migrate->pgmap_owner = NULL; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_PGMAP_OWNER, 1, + [migrate_vma->pgmap_owner is available]) + ]) +]) + dnl # dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap @@ -15,6 +30,8 @@ AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ ], [ AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER ]) ]) ]) From 0afedf05964cbac4b11591730a3351d57fa0cabe Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 19 Apr 2021 13:12:39 +0800 Subject: [PATCH 0610/2070] drm/amdkcl: direct include memremap.h for legacy os This is caused by "drm/amdkfd: register HMM device private zone" v5.11-3037-g2f833caf32eb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 22565f93c7134..468dbe49ac80d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -47,6 +47,7 @@ #include #include #include +#include #include "amdgpu_amdkfd.h" #include "amd_shared.h" From 8a2132e03366ad503ca426f2368a3b561eeed914 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 20 Apr 2021 10:21:04 +0800 Subject: [PATCH 0611/2070] drm/amdkcl: fix autoconf test for svm config Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/svm.m4 | 30 +++++++++++++-------------- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 228e66022b959..5137132996950 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -15,6 +15,8 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, [hmm_range_fault() wants 1 arg]) + + AC_AMDGPU_HSA_AMD_SVM ], [ dnl # dnl # v5.6-rc3-21-g6bfef2f91945 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0351a62453a1f..40fda1fe1fbd0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,7 +44,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP - AC_AMDGPU_HSA_AMD_SVM AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index 0deabfae97260..dbcd257ba1662 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -18,21 +18,19 @@ dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pag dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap dnl # AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) - #error "DEVICE_PRIVATE is a must for svm support" - #endif - ], [ - struct dev_pagemap *pm = NULL; - pm->owner = NULL; - ], [ - AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, - [dev_pagemap->owner is available]) - - AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER - ]) - ]) + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER + ]) ]) From 2ecbb2b3f425ffc41769856131ac6084eb2c1633 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 14 Apr 2021 12:19:39 -0500 Subject: [PATCH 0612/2070] drm/amdgpu: Use VRAM Mgr api's to export SG Tables Use api's exported by VRAM Mgr (amdgpu_vram_mgr.c) to build and export SG Tables for access by peer PCIe devices. These api's allow a VRAM buffer object to be partitioned into multiple non-overlapping segments. For example one could partition a VRAM buffer into two segments, one serving as SRC buffer while the other serves as DST buffer. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 83548271b4eb0..a603c101d0985 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2540,6 +2540,7 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, * Walk down system memory pointed by BO while * Updating Scatterlist nodes with system memory info */ + sg = kmalloc(sizeof(*sg), GFP_KERNEL); if (!sg) { ret = -ENOMEM; From dbff0313feb94d57b46ef114621aa604a452430e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 21 Apr 2021 10:57:09 +0800 Subject: [PATCH 0613/2070] drm/amdkcl: wrap the code under HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE This is caused by "drm/amd/display: update hdcp display using correct CP type." v5.11-3068-g2b39a66dfe7b Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Signed-off-by: Ma Jun Change-Id: I8c6650ceb98679c6e708d7b8d8380634a279fb99 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 752c83854a385..f605164312e5c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -590,6 +590,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback; hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1, @@ -604,6 +605,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) drm_connector_put(&hdcp_w->aconnector[conn_index]->base); hdcp_w->aconnector[conn_index] = aconnector; process_output(hdcp_w); +#endif } /** From 84f10fabc140fbfd64751223e84f4f8682b5e0cc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Sun, 25 Apr 2021 11:10:48 +0800 Subject: [PATCH 0614/2070] drm/amdkcl: adapt code to access format field of struct drm_framebuffer This is caused by "drm/amd/display: Reject non-zero src_y and src_x for video planes" v5.11-3116-g7af71c0752f0 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ic7b7718302c27d2bf2193760407933401c923f48 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 82e79c310c099..a2982f5017105 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6149,7 +6149,6 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, break; } - plane_info->visible = true; plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 93a9011fc6258..3e21f89d167a4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1179,8 +1179,8 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, */ if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && - (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && - (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) + (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) return -EINVAL; scaling_info->src_rect.width = state->src_w >> 16; From 3fef1b0bbd90aec8d3b00aa85825963b816a7a51 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 21 Apr 2021 13:34:01 -0400 Subject: [PATCH 0615/2070] drm/amdkcl: test for is_smca_umc_v2 symbol Test if is_smca_umc_v2 symbol is available or not. This symbol is needed for page retirement handling on Aldebaran. Signed-off-by: Mukul Joshi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 14 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 new file mode 100644 index 0000000000000..28eda1decdae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # +dnl # is_smca_umc_v2() +dnl # +AC_DEFUN([AC_AMDGPU_CHECK_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([is_smca_umc_v2], + [arch/x86/kernel/cpu/mce/amd.c], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [is_smca_umc_v2() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 40fda1fe1fbd0..419f8ba17b1ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -102,6 +102,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION + AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From a0db86e63d8e49083c294fbcbacc74f109ee37fc Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 21 Apr 2021 13:37:06 -0400 Subject: [PATCH 0616/2070] drm/amdgpu: Register bad page handler for Aldebaran On Aldebaran, GPU driver will handle bad page retirement even though UMC is host managed. As a result, register a bad page retirement handler on the mce notifier chain to retire bad pages on Aldebaran. Signed-off-by: Mukul Joshi Reviewed-By: John Clements Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 856b1bf83533d..7f1ce6755f2db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -132,6 +132,16 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define BYPASS_ALLOCATED_ADDRESS 0x0 #define BYPASS_INITIALIZATION_ADDRESS 0x1 +#ifdef HAVE_SMCA_UMC_V2 +#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) +#define GET_UMC_INST_NIBBLE(m) (((m) >> 20) & 0xF) +#define GET_CHAN_INDEX_NIBBLE(m) (((m) >> 12) & 0xF) +#define GPU_ID_OFFSET 8 + +static bool notifier_registered = false; +static void amdgpu_register_bad_pages_mca_notifier(void); +#endif + enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -3902,10 +3912,13 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); amdgpu_ras_ecc_log_init(&con->umc_ecc_log); #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); #endif +#endif + return 0; free: @@ -4904,6 +4917,7 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) } #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 static struct amdgpu_device *find_adev(uint32_t node_id) { int i; @@ -5026,6 +5040,7 @@ static void amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev) } } #endif +#endif struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) { From 6d3e38a23a4548eab72aecaf0a523f993aeb3bcb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 27 Apr 2021 11:06:29 +0800 Subject: [PATCH 0617/2070] drm/amdkcl: update config.h Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 803e7b61e529c..3455ad3cc3ea4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -819,6 +819,9 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 +/* is_smca_umc_v2() is available */ +/* #undef HAVE_SMCA_UMC_V2 */ + /* strscpy() is available */ #define HAVE_STRSCPY 1 From f19e59f06bf646c0af7e1ca3bf77d10057ac49fb Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 29 Apr 2021 16:58:17 +0800 Subject: [PATCH 0618/2070] drm/amdkcl: fix sg to page arrays callback for legacy OS To call the legacy drm_prime_sg_to_page_addr_arrays, the 2nd parameter should be page array instead of NULL pointer Otherwise, the page fault will be triggered Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_drm_prime.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 7f02b6c95d10c..8f207f1f44b91 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -12,8 +12,19 @@ static inline int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, int max_entries) { +#ifdef HAVE_TTM_SG_TT_INIT return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); - -} +#else + /* + * the page array stands right next to dma address array, + * so get the page array pointer directly by max_entries offset + * refer to ttm_sg_tt_init() for initial array allocation and + * c67e62790f5c drm/prime: split array import functions v4 for + * the change to drm_prime_sg_to_page_addr_arrays() + */ + struct page **pages = (void*)addrs - max_entries; + return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); #endif +} +#endif /* HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY */ #endif From 36a859a792845fe6e83c255a0352cefc09da0500 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 30 Apr 2021 14:56:46 +0800 Subject: [PATCH 0619/2070] drm/amdkcl: fake hmm_pfn_to_page() Suggested-by: Felix Kuehling Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 16 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 -------------- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index f6d0d49ce4ccb..03f307e34b84e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -804,13 +804,13 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT /* flags used by HMM internal, not related to CPU/GPU PTE flags */ -static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { +const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { (1 << 0), /* HMM_PFN_VALID */ (1 << 1), /* HMM_PFN_WRITE */ 0 /* HMM_PFN_DEVICE_PRIVATE */ }; -static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { +const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ 0, /* HMM_PFN_NONE */ 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 77a33d65bc987..f2d02bb057c94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -66,6 +66,22 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} #include #include +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +extern const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX]; +extern const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX]; + +static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) +{ + struct hmm_range hmm_range = { + .flags = hmm_range_flags, + .values = hmm_range_values, + .pfn_shift = PAGE_SHIFT, + }; + + return hmm_device_entry_to_page(&hmm_range, hmm_pfn); +} +#endif struct amdgpu_hmm_range { struct hmm_range hmm_range; struct amdgpu_bo *bo; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index d4a02ae1d19af..dd94ac9b10219 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -762,20 +762,6 @@ struct amdgpu_ttm_tt { #ifdef CONFIG_DRM_AMDGPU_USERPTR #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED -#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT -/* flags used by HMM internal, not related to CPU/GPU PTE flags */ -static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { - (1 << 0), /* HMM_PFN_VALID */ - (1 << 1), /* HMM_PFN_WRITE */ - 0 /* HMM_PFN_DEVICE_PRIVATE */ -}; - -static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { - 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ - 0, /* HMM_PFN_NONE */ - 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ -}; -#endif /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update From 9b681c2581e0717856f658848f054421b29cdd97 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 30 Apr 2021 13:58:54 +0800 Subject: [PATCH 0620/2070] drm/amdkcl: rework svm enabled dependency Signed-off-by: Flora Cui Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 ++++-- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++--- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 3 +-- drivers/gpu/drm/amd/dkms/m4/svm.m4 | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 488bace2256c8..458d1611ed3ae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -422,7 +422,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, #ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); -#else +#elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = NULL; #endif @@ -728,7 +728,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; -#else +#elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); #endif @@ -1090,7 +1090,9 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) } pgmap->ops = &svm_migrate_pgmap_ops; +#ifdef HAVE_DEV_PAGEMAP_OWNER pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif pgmap->flags = 0; /* Device manager releases device-specific resources, memory region and diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4fc3b8e5ba5a4..b1eecc92ebfb3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -158,7 +158,7 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -ifeq ($(call _is_kcl_macro_defined,HAVE_HSA_AMD_SVM_ENABLED),y) +ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) export CONFIG_HSA_AMD_SVM=y subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3455ad3cc3ea4..2cc031c08d203 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -67,6 +67,9 @@ /* devm_memremap_pages() wants p,p,p,p interface */ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ +/* dev_pagemap->owner is available */ +#define HAVE_DEV_PAGEMAP_OWNER 1 + /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -603,9 +606,6 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 -/* dev_pagemap->owner is available */ -#define HAVE_HSA_AMD_SVM_ENABLED 1 - /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 5137132996950..c175fd6289702 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -15,8 +15,6 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, [hmm_range_fault() wants 1 arg]) - - AC_AMDGPU_HSA_AMD_SVM ], [ dnl # dnl # v5.6-rc3-21-g6bfef2f91945 @@ -66,6 +64,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, [hmm support is enabled]) AC_AMDGPU_HMM_RANGE_FAULT + AC_AMDGPU_HSA_AMD_SVM ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index dbcd257ba1662..17657770988f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -27,7 +27,7 @@ AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ struct dev_pagemap *pm = NULL; pm->owner = NULL; ], [ - AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + AC_DEFINE(HAVE_DEV_PAGEMAP_OWNER, 1, [dev_pagemap->owner is available]) AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER From 664cb9b959a265cb535e5846516abaa7601be8e1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 7 May 2021 13:59:37 +0800 Subject: [PATCH 0621/2070] drm/amdkcl: wrap the code under HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED This is caused by "drm/amdgpu: Use device specific BO size & stride check." v5.11-3225-gdf0c606a6ced Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 84bffe8ed407d..42d8852ac5ea1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -963,6 +963,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) } } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, unsigned int *width, unsigned int *height) { @@ -1045,17 +1046,16 @@ static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane (uint64_t)rfb->base.pitches[plane] / block_pitch * block_size * DIV_ROUND_UP(height, block_height); - if (rfb->base.obj[0]->size < size) { + if (drm_gem_fb_get_obj(&rfb->base, 0)->size < size) { drm_dbg_kms(rfb->base.dev, "BO size 0x%zx is less than 0x%llx required for plane %d\n", - rfb->base.obj[0]->size, size, plane); + drm_gem_fb_get_obj(&rfb->base, 0)->size, size, plane); return -EINVAL; } return 0; } - static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) { const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); @@ -1159,6 +1159,7 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) return 0; } +#endif static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, uint64_t *tiling_flags, bool *tmz_surface, @@ -1228,6 +1229,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, mode_cmd->modifier[0])) { @@ -1238,6 +1240,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, ret = -EINVAL; goto err; } +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1349,13 +1352,17 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); if (drm_gem_is_imported(obj) && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-EINVAL); } amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); if (amdgpu_fb == NULL) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-ENOMEM); } @@ -1363,11 +1370,16 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, info, mode_cmd, obj); if (ret) { kfree(amdgpu_fb); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(ret); } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif + return &amdgpu_fb->base; } From d53706b6f8341488ac8d552073afbac5e71e1065 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 7 May 2021 18:07:00 +0800 Subject: [PATCH 0622/2070] drm/amdkcl: export the symbol of pxm_to_node This is caused by "add ACPI SRAT parsing for topology" v2: dummy pxm_to_node() in case the symbol cannot be found by kallsyms_lookup_name() Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_numa.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 | 13 +++++++++++++ include/kcl/backport/kcl_numa_backport.h | 10 ++++++++++ 8 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_numa.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 create mode 100644 include/kcl/backport/kcl_numa_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ca9832a6560c3..200f718370bd0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_numa.c b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c new file mode 100644 index 0000000000000..92605529089d1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +#ifndef HAVE_PXM_TO_NODE +int (*_kcl_pxm_to_node)(int pxm); +EXPORT_SYMBOL(_kcl_pxm_to_node); + +/* Copied from include/acpi/acpi_numa.h */ +static int __kcl_pxm_to_node_stub(int pxm) +{ + return 0; +} +#endif + +void amdkcl_numa_init(void) +{ +#ifndef HAVE_PXM_TO_NODE + _kcl_pxm_to_node = amdkcl_fp_setup("pxm_to_node", __kcl_pxm_to_node_stub); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 69992592b782f..7e6b682cbc483 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -10,6 +10,7 @@ extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); +extern void amdkcl_numa_init(void); int __init amdkcl_init(void) { @@ -21,6 +22,7 @@ int __init amdkcl_init(void) amdkcl_mm_init(); amdkcl_pci_init(); amdkcl_suspend_init(); + amdkcl_numa_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ac77487c8ecd0..06e34a8321b0d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -60,6 +60,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2cc031c08d203..32bc3940fcaad 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -798,6 +798,12 @@ /* pm_genpd_remove_device() wants 2 arguments */ /* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ +/* pm_suspend_via_firmware() is available */ +#define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 + +/* pxm_to_node() is available */ +#define HAVE_PXM_TO_NODE 1 + /* remove_conflicting_framebuffers() returns int */ /* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 419f8ba17b1ad..7e81ea0c9b3ec 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -103,6 +103,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_CHECK_SMCA_UMC_V2 + AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 new file mode 100644 index 0000000000000..35651096f8e2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.7-20-gf2af6d3978d7 +dnl # virtio-mem: Allow to specify an ACPI PXM as nid +dnl # +AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pxm_to_node], + [drivers/acpi/numa/srat.c], [ + AC_DEFINE(HAVE_PXM_TO_NODE, 1, + [pxm_to_node() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_numa_backport.h b/include/kcl/backport/kcl_numa_backport.h new file mode 100644 index 0000000000000..ef190c784cdbf --- /dev/null +++ b/include/kcl/backport/kcl_numa_backport.h @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#ifndef AMDKCL_NUMA_BACKPORT_H +#define AMDKCL_NUMA_BACKPORT_H + +#if !defined(HAVE_PXM_TO_NODE) +extern int _kcl_pxm_to_node(int pxm); +#define pxm_to_node _kcl_pxm_to_node +#endif + +#endif From d32c8166ee407a9735aa06bd0d46de12519ef5f1 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Sat, 8 May 2021 11:48:26 +0800 Subject: [PATCH 0623/2070] drm/amdkcl: wrap the code of GENERIC_AFFINITY processing Disable the GENERIC_AFFINITY related code for legacy OS where ACPI 6.x is NOT supported. This is caused by "add ACPI SRAT parsing for topology" Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index d4291fe4952d3..702a08745f13f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -2070,6 +2070,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) if (pxm > max_pxm) max_pxm = pxm; break; +#ifdef HAVE_ACPI_SRAT_GENERIC_AFFINITY case ACPI_SRAT_TYPE_GENERIC_AFFINITY: gpu = (struct acpi_srat_generic_affinity *)sub_header; bdf = *((u16 *)(&gpu->device_handle[0])) << 16 | @@ -2079,6 +2080,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) numa_node = pxm_to_node(gpu->proximity_domain); } break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 32bc3940fcaad..c8804baf27540 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -13,6 +13,9 @@ /* acpi_put_table() is available */ #define HAVE_ACPI_PUT_TABLE 1 +/* struct acpi_srat_generic_affinity is available */ +#define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 new file mode 100644 index 0000000000000..16493b5e8d995 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit aa475a59fff172ec858093fbc8471c0993081481 +dnl # ACPICA: ACPI 6.3: SRAT: add Generic Affinity Structure subtable +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct acpi_srat_generic_affinity *p = NULL; + p->reserved = 0; + ], [ + AC_DEFINE(HAVE_ACPI_SRAT_GENERIC_AFFINITY, 1, [struct acpi_srat_generic_affinity is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7e81ea0c9b3ec..be958722e08ac 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -104,6 +104,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE + AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From 7b5515e40a3e9c0a8e14b5ae9e5cbd6d97924a1c Mon Sep 17 00:00:00 2001 From: Matt Ezell Date: Wed, 12 May 2021 12:38:14 -0400 Subject: [PATCH 0624/2070] drm/amdkfd: Unlock mutex in error path of kfd_ioctl_alloc_memory_of_gpu Signed-off-by: Matt Ezell Reviewed-by: Felix Kuehling Signed-off-by: Felix Kuehling Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6db923e9f75ba..eb3e0b4741325 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1155,7 +1155,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = follow_pfn(vma, args->mmap_offset, &pfn); if (err) { pr_debug("Failed to get PFN: %ld\n", err); - return err; + goto err_unlock; } flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; @@ -1164,7 +1164,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (offset & (PAGE_SIZE - 1)) { pr_debug("Unaligned userptr address:%llx\n", offset); - return -EINVAL; + err = -EINVAL; + goto err_unlock; } cpuva = offset; } From c74e848f7a481291e94aca5d038acf9614ba4c14 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 17 May 2021 13:07:54 +0800 Subject: [PATCH 0625/2070] drm/amdgpu: disable GFX RAS on A + A platform this is a regression introduced by 0c15d459a359ff3e02e0556248fc0af17e11b178 GFX RAS should be disabled by default on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 7f1ce6755f2db..5bdfeaa5d5fb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4152,9 +4152,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | - 1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } /* apply asic specific settings (vega20 only for now) */ From 22468bb95cfdf20bcf38102db9ec2f3fb53d8459 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 10:18:24 +0800 Subject: [PATCH 0626/2070] drm/amdkcl: fix IGT gamma test failure [why] Patch "drm: automatic legacy gamma support" removes the assignment of amdgpu_dm_crtc_funcs.gamma_set, it's ok on new kernel that drm core handled the gamma setting, but on old kernel, it results drm_mode_gamma_set_ioctl() exit with ENOSYS, then the IGT gamma test failed. [how] Bring the assignment code back to fix the failure. Change-Id: Iebdf4752e5a06fa551df18810e3da1ba52c9fba0 Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Signed-off-by: Ma Jun Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 3 +++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 13 +++++++++++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index bb83aa44aa900..9943f44951d3a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -571,6 +571,9 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = amdgpu_dm_crtc_reset_state, .destroy = amdgpu_dm_crtc_destroy, +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL + .gamma_set = drm_atomic_helper_legacy_gamma_set, +#endif .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c8804baf27540..e983ad23b5415 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -134,6 +134,9 @@ /* drm_atomic_helper_check_plane_state() is available */ #define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 + /* drm_atomic_helper_shutdown() is available */ #define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 31099519500e0..8ad24bc40f5fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -19,6 +19,19 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) +dnl # +dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c], [], + [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, + [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 8b3f48f1a2e266f270325b8e59fd92b0e7807aee Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 18 May 2021 17:14:05 +0800 Subject: [PATCH 0627/2070] drm/amdkcl: fix the calculation of pages array based on dma array Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_drm_prime.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 8f207f1f44b91..2c5e972520576 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -22,7 +22,7 @@ int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, * c67e62790f5c drm/prime: split array import functions v4 for * the change to drm_prime_sg_to_page_addr_arrays() */ - struct page **pages = (void*)addrs - max_entries; + struct page **pages = (void*)((unsigned long)addrs - max_entries*sizeof(dma_addr_t)); return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); #endif } From e50f6f641c161ca21f2477083635973d10b9ef18 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 May 2021 13:25:00 +0800 Subject: [PATCH 0628/2070] drm/amdkcl: wrap the code under CONFIG_DRM_AMD_DC_DSC_SUPPORT This is caused by "drm/amd/display: Initial DC support for Beige Goby" v5.11-3391-g54f910c6372e Signed-off-by: Leslie Shi --- .../amd/display/dc/resource/dcn303/dcn303_resource.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 75e09c2c283e0..1ad44c910ae9b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -129,7 +129,9 @@ static const struct resource_caps res_cap_dcn303 = { .num_ddc = 2, .num_vmid = 16, .num_mpc_3dlut = 1, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 2, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -625,6 +627,7 @@ static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -653,6 +656,7 @@ static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -951,10 +955,12 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } +#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1089,7 +1095,9 @@ static struct resource_funcs dcn303_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1366,6 +1374,7 @@ static bool dcn303_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn303_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1374,6 +1383,7 @@ static bool dcn303_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn303_dwbc_create(ctx, pool)) { From bfc46941507098913c51dc353ef890e490faad7d Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 19 May 2021 09:29:00 -0400 Subject: [PATCH 0629/2070] drm/amdkfd: complete indirect peer no-atomics support checks When setting no-atomics flags for a target GPU, the target should self check atomic support over root and check the source GPU's atomic endpoint support to complete the flag check and set. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 35 ++++++++++++++++------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 2f99b4a143d84..a900d274f7026 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1280,7 +1280,16 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI) return; - /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */ + /* checkout source dev has atomics support on root. */ + if (dev->gpu && (!dev->gpu->pci_atomic_requested || + dev->gpu->device_info->asic_family == + CHIP_HAWAII)) { + link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; + return; + } + + /* check target_gpu_dev is atomics capable. */ if (target_gpu_dev) { uint32_t cap; @@ -1440,17 +1449,23 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) } } - /* Create CPU<->GPU indirect links so apply flags setting to all */ + /* Create indirect links so apply flags setting to all */ list_for_each_entry(link, &dev->p2p_link_props, list) { - cpu_dev = kfd_topology_device_by_proximity_domain( + link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(dev, NULL, link); + peer_dev = kfd_topology_device_by_proximity_domain( link->node_to); - if (cpu_dev && !cpu_dev->gpu) { - list_for_each_entry(cpu_link, - &cpu_dev->p2p_link_props, list) - if (cpu_link->node_to == link->node_from) { - link->flags = flag; - cpu_link->flags = cpu_flag; - } + + if (!peer_dev) + continue; + + list_for_each_entry(inbound_link, &peer_dev->p2p_link_props, + list) { + if (inbound_link->node_to != link->node_from) + continue; + + inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); } } } From ca2cdba410fa40ced2a593de6625d71cc77b1dee Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 May 2021 15:53:33 +0800 Subject: [PATCH 0630/2070] drm/amdkcl: adapt code for legacy os This is caused by following commits: d9e1c5963c97 drm/amd/amdgpu: fix refcount leak 9faf262c32d3 drm/amdgpu: Add DMA mapping of GTT BOs ac89ed0789f8 drm/amdgpu: Move kfd_mem_attach outside reservation Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 8 +++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a603c101d0985..48826a6124ca8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -835,6 +835,7 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) return 0; } +#ifdef AMDKCL_AMDGPU_DMABUF_OPS static int kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo **bo) @@ -855,6 +856,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, return 0; } +#endif /* kfd_mem_attach - Add a BO to a VM * @@ -946,6 +948,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = create_dmamap_sg_bo(adev, mem, &bo[i]); if (ret) goto unwind; +#ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT and VRAM BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { @@ -954,6 +957,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); +#endif } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 24738cf5f0fad..8210c0bc5ccb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -294,10 +294,12 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb drm_fb_helper_unregister_fbi(&rfbdev->helper); obj = drm_gem_fb_get_obj(&rfb->base, 0); - if (rfb->base.obj[0]) { + if (obj) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 0; i < rfb->base.format->num_planes; i++) - drm_gem_object_put(rfb->base.obj[0]); - amdgpufb_destroy_pinned_object(rfb->base.obj[0]); + drm_gem_object_put(obj); +#endif + amdgpufb_destroy_pinned_object(obj); kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); From 816a13a363c50cd48e7dc9b5b3d20d9833924716 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Fri, 21 May 2021 16:14:38 +0800 Subject: [PATCH 0631/2070] drm/amdgpu: allow force enable gfx ras on A + A platform This is temporary solution to allow enable gfx ras on A + A platform by setting kernel module parameter ras_mask to 0xe. It should be removed when gfx ras is enabled by default on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: John Clements Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5bdfeaa5d5fb2..d9f4ae071e1d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4154,6 +4154,12 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) * when GPU is connected cpu through XGMI */ adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | 1 << AMDGPU_RAS_BLOCK__MMHUB); + /* This is temporary workaround to leverage ras_mask + * to allow nable GFX RAS manually. Should be removed later + */ + if (amdgpu_ras_enable && + (amdgpu_ras_mask == 0xe)) + adev->ras_hw_enabled |= 1 << AMDGPU_RAS_BLOCK__GFX; } /* apply asic specific settings (vega20 only for now) */ From e983f54c9b7097a4ecc9385c51f5beb260cbb20c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 26 May 2021 14:59:49 +0800 Subject: [PATCH 0632/2070] drm/amdkcl: wrap code under macro for legacy os This is caused by "drm/amdgpu: Move dmabuf attach/detach to backend_(un)bind" v5.11-3411-g6c6210ae18ba Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen drm/amdkcl: fix a define typo Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dd94ac9b10219..5a91dbdf4f73f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1113,6 +1113,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, return r; } } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) if (!ttm->sg) { struct dma_buf_attachment *attach; struct sg_table *sgt; @@ -1124,6 +1126,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, ttm->sg = sgt; } +#endif drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, ttm->num_pages); @@ -1236,11 +1239,14 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, if (gtt->userptr) { amdgpu_ttm_tt_unpin_userptr(bdev, ttm); } else if (ttm->sg && drm_gem_is_imported(gtt->gobj)) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) struct dma_buf_attachment *attach; attach = gtt->gobj->import_attach; dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); ttm->sg = NULL; +#endif } if (!gtt->bound) From de77bfb24185b0f3f2331cbe49de57f89daa8218 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 8 Dec 2020 11:43:29 -0500 Subject: [PATCH 0633/2070] drm/amdgpu: fix mmu notifier release callback race exit_mmap calls MMU notifier release callback first, which schedule kfd_process_wq_release work and amdgpu_mn_destroy work, then calls unmap_vmas to unmap userptr, which calls amdgpu_mn_invalidate_range_start_hsa. kfd_process_wq_release work calls free_outstanding_kfd_bos -> amdgpu_mn_unregister to remove bo from amn->objects. amdgpu_mn_destroy work free bo nodes from amn->objects. amdgpu_mn_invalidate_range_start_hsa scans amn->objects tree to find bo. amdgpu_mn_destroy free bo nodes on the interval tree, but not free the tree. amdgpu_mn_invalidate_range_start_hsa scan the amn->objects to lookup bo node, this causes kernel BUG or NULL pointer access because bo node maybe freed. Fix: Set amn->objects tree to NULL, and remove amn from MMU notifier in amdgpu_mn_destroy before releasing adev->mn_lock. Kernel BUG backtrace: [849938.299554] BUG: unable to handle kernel paging request at [849938.314382] Call Trace: [849938.315637] amdgpu_mn_invalidate_range_start_hsa+0x55/0xc0 [amdgpu] [849938.316778] __mmu_notifier_invalidate_range_start+0x52/0x80 [849938.317627] try_to_unmap_one+0x101/0xa70 [849938.318545] ? entry_SYSCALL_64_after_hwframe+0xb9/0xca [849938.319590] ? __switch_to_asm+0x41/0x70 [849938.320434] ? __switch_to_asm+0x35/0x70 [849938.321525] ? __switch_to_asm+0x41/0x70 [849938.322676] rmap_walk_file+0xf7/0x260 [849938.323822] try_to_munlock+0x4d/0x70 [849938.324939] ? page_remove_rmap+0x350/0x350 [849938.326031] ? anon_vma_ctor+0x40/0x40 [849938.327089] ? page_get_anon_vma+0x80/0x80 [849938.328143] __munlock_isolated_page+0x26/0x60 [849938.329217] munlock_vma_page+0xff/0x110 [849938.330289] munlock_vma_pages_range+0x8d/0x3d0 [849938.331381] ? enqueue_entity+0x108/0x640 [849938.332466] ? select_idle_sibling+0x22/0x430 [849938.333560] ? enqueue_task_fair+0x7d/0x460 [849938.334671] exit_mmap+0x132/0x190 [849938.335750] ? __delayacct_add_tsk+0x183/0x1b0 [849938.336794] ? kmem_cache_free+0x18c/0x1b0 [849938.337816] mmput+0x54/0x130 [849938.338823] do_exit+0x353/0xb40 [849938.339821] do_group_exit+0x3a/0xa0 [849938.340814] get_signal+0x147/0x850 [849938.341825] do_signal+0x36/0x660 [849938.342835] ? ktime_get_ts64+0x40/0xe0 [849938.343839] exit_to_usermode_loop+0x89/0xf0 [849938.344605] do_syscall_64+0x198/0x1a0 BUG: SWDEV-262212 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 03f307e34b84e..d832f3d338b6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -141,14 +141,19 @@ static void amdgpu_mn_destroy(struct work_struct *work) } kfree(node); } + + amn->objects = RB_ROOT_CACHED; + up_write(&amn->lock); - mutex_unlock(&adev->mn_lock); + #ifdef HAVE_MMU_NOTIFIER_PUT mmu_notifier_put(&amn->mn); #else mmu_notifier_unregister_no_release(&amn->mn, amn->mm); mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); #endif + + mutex_unlock(&adev->mn_lock); } /** From c08d1dbfadc8dacdccba0dddb7a87e5811f607b0 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Sun, 30 May 2021 22:52:03 -0400 Subject: [PATCH 0634/2070] drm/amdgpu: unregister MMU notifier in release callback Schedule work to unregister MMU notifier in MMU release callback, if the work remove MMU notifier between invalidate_range_start and invalidate_range_end, amdgpu_mn_invalidate_range_end will not be called because the notifier is gone. This causes amn->lock is not unlocked, then amdgpu_mn_unregister hold adev->mn_lock, wait for amn->lock forever, and new process amdgpu_mn_register wait for adev->mn_lock, it is deadklock. Fix: Unregister MMU notifier in MMU notifier release callback, remove amn->work, it is not needed anymore. As a result, exit_mmap unmap outstanding userptr will not cause unnecessary queue evction and restore because MMU notifier is already removed before unmap userptr. BUG: SWDEV-262212 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index d832f3d338b6a..a55a9ef8726d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -75,9 +75,6 @@ struct amdgpu_mn { struct mmu_notifier mn; enum amdgpu_mn_type type; - /* only used on destruction */ - struct work_struct work; - /* protected by adev->mn_lock */ struct hlist_node node; @@ -119,13 +116,12 @@ static void amdgpu_mn_free(struct rcu_head *rcu) /** * amdgpu_mn_destroy - destroy the MMU notifier * - * @work: previously sheduled work item + * @amn: our notifier * - * Lazy destroys the notifier from a work item + * Destroy the notifier */ -static void amdgpu_mn_destroy(struct work_struct *work) +static void amdgpu_mn_destroy(struct amdgpu_mn *amn) { - struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work); struct amdgpu_device *adev = amn->adev; struct amdgpu_mn_node *node, *next_node; struct amdgpu_bo *bo, *next_bo; @@ -162,15 +158,14 @@ static void amdgpu_mn_destroy(struct work_struct *work) * @mn: our notifier * @mm: the mm this callback is about * - * Shedule a work item to lazy destroy our notifier. + * Destroy our notifier. */ static void amdgpu_mn_release(struct mmu_notifier *mn, struct mm_struct *mm) { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); - INIT_WORK(&amn->work, amdgpu_mn_destroy); - schedule_work(&amn->work); + amdgpu_mn_destroy(amn); } From 6f80c24c25c220e12ab8565bf77264dcbbd23f60 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 2 Jun 2021 10:13:34 +0800 Subject: [PATCH 0635/2070] drm/amdkcl: define macro DRM_FORMAT_{XRGB/XBGR/ARGB/ABGR}16161616 for legacy os This is caused by bcd05bd9251f "drm/amd/display: Enable support for 16 bpc fixed-point framebuffers." Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 25cf40f897b23..d40688cb6422d 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -214,4 +214,17 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif + +/* 64 bpp RGB */ +#ifndef DRM_FORMAT_XRGB16161616 +/* Copied from v5.11-3544-ga2fe23ecdbb7 */ +#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ +#endif + +#ifndef DRM_FORMAT_ARGB16161616 +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From 41634b7ed58bd0fff4f2b82af97e07a59fbd0c8e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 2 Jun 2021 15:54:34 +0800 Subject: [PATCH 0636/2070] drm/amdkcl: add macro drm_dbg_atomic This is caused by 216502b1e930 "amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic" v5.11-3568-g216502b1e930 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c51497dc79f3e..c2dac790ba1c8 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -141,6 +141,11 @@ void kcl_drm_err(const char *format, ...); void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); #endif +#if !defined(drm_dbg_atomic) +#define drm_dbg_atomic(drm, fmt, ...) \ + drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) +#endif + #if !defined(drm_dbg_kms) #define drm_dbg_kms(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) From d8f5408e0ec91331da251d7e84bb08b8d48c0358 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 4 Jun 2021 17:17:18 +0800 Subject: [PATCH 0637/2070] drm/amdkcl: fix the _kcl_pxm_to_node func declaration As _kcl_pxm_to_node is defined as func pointer the same for the declaration format. Otherwise the page fault will happen since the address of the pointer var itself is used for calling the func. [ 284.537683] kernel tried to execute NX-protected page - exploit attempt? (uid: 0) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/backport/kcl_numa_backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_numa_backport.h b/include/kcl/backport/kcl_numa_backport.h index ef190c784cdbf..99251097a9e76 100644 --- a/include/kcl/backport/kcl_numa_backport.h +++ b/include/kcl/backport/kcl_numa_backport.h @@ -3,7 +3,7 @@ #define AMDKCL_NUMA_BACKPORT_H #if !defined(HAVE_PXM_TO_NODE) -extern int _kcl_pxm_to_node(int pxm); +extern int (*_kcl_pxm_to_node)(int pxm); #define pxm_to_node _kcl_pxm_to_node #endif From 8270303d2ce02c73740c4ad57cd32db060318316 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 4 Jun 2021 12:51:31 -0500 Subject: [PATCH 0638/2070] drm/amdgpu: Access peer GPU VRAM BO's as DMABUF objects Current design enabling access to peer GPU's VRAM BO requires that system run with IOMMU disabled. Enabling the use of DMABUF objects relaxes this constraint i.e. access is not affected by IOMMU being ON or OFF. However, the use of DMABUF objects requires config option DMABUF_MOVE_NOTIFY to be enabled. When this config option is not SET access requests are valid only if IOMMU is OFF. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 48826a6124ca8..7834af6e7fd69 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -858,6 +858,38 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, } #endif +/** + * @kfd_mem_attach_vram_bo: Acquires the handle of a VRAM BO that could + * be used to enable a peer GPU access it + * + * Implementation determines if access to VRAM BO would employ DMABUF + * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config + * option DMABUF_MOVE_NOTIFY enabled. Employ Shared BO mechanism if above + * config option is not set. It is important to note that a Shared BO + * cannot be used to enable peer acces if system has IOMMU enabled + * + * @TODO: ADD Check to ensure IOMMU is not enabled. Should this check + * be somewhere as this is information could be useful in other places + */ +static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, + struct kgd_mem *mem, struct amdgpu_bo **bo, + struct kfd_mem_attachment *attachment) +{ + int ret = 0; + +#ifdef CONFIG_DMABUF_MOVE_NOTIFY + attachment->type = KFD_MEM_ATT_DMABUF; + ret = kfd_mem_attach_dmabuf(adev, mem, bo); + pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); +#else + *bo = mem->bo; + attachment->type = KFD_MEM_ATT_SHARED; + drm_gem_object_get(&(*bo)->tbo.base); + pr_debug("Employ Shared BO mechanim to enable peer GPU access\n"); +#endif + return ret; +} + /* kfd_mem_attach - Add a BO to a VM * * Everything that needs to bo done only once when a BO is first added @@ -958,6 +990,13 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); #endif + /* Enable peer acces to VRAM BO's */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && + mem->bo->tbo.type == ttm_bo_type_device) { + ret = kfd_mem_attach_vram_bo(adev, mem, + &bo[i], attachment[i]); + if (ret) + goto unwind; } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; From e54f54415d1892d948b7e5c792b23b4dddd8afbf Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 8 Jun 2021 12:13:06 -0400 Subject: [PATCH 0639/2070] drm/amdkcl: get list of supported ASIC The patch ensures that DKMS build succeeds against kernels that don't support all chips defined in amdgpu_pciid.h Change-Id: Id00ed13b2d8210965bd9de6759da1f1e776a3d4f Signed-off-by: Slava Grigorev Reviewed-by: Tim Writer Reviewed-by: Slava Abramov --- .../drm/amd/dkms/config/config-amd-chips.h | 3 ++ drivers/gpu/drm/amd/dkms/config/config.h | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 29 +++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/config/config-amd-chips.h diff --git a/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h new file mode 100644 index 0000000000000..9ff8bd1cb6a04 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h @@ -0,0 +1,3 @@ +/* + * This file is managed by DKMS build. Do not edit. + */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e983ad23b5415..46af6d633ad0d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -995,3 +995,5 @@ /* Define to the version of this package. */ #define PACKAGE_VERSION "19.40" + +#include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 1f21aec4ff2ee..5c9cf41e67120 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -46,6 +46,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) + dnl # + dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amd_asic_type.h]) + dnl # dnl # v5.12-rc3-330-g2916059147ea dnl # drm/aperture: Add infrastructure for aperture ownership diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index be958722e08ac..b7ce2f4189dba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_KERNEL_SUPPORTED_AMD_CHIPS AC_AMDGPU_IDR_REMOVE AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE @@ -124,6 +125,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ ]) AC_SUBST(KERNEL_MAKE) + AH_BOTTOM([#include "config-amd-chips.h"]) ]) dnl # @@ -526,3 +528,30 @@ AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_RESULT([failed]) ]) ]) + +dnl # +dnl # AC_KERNEL_SUPPORTED_AMD_CHIPS +dnl # get list of graphics chips supported by the amdgpu kernel driver +dnl # +AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ + AC_MSG_CHECKING([for supported chips]) + AS_IF([test $HAVE_DRM_AMD_ASIC_TYPE_H], [ + chips=$(awk 'BEGIN {enum = 0} { + if ($[0] ~ "^enum amd_asic_type") + enum = 1; + if (enum && $[1] ~ "CHIP_") { + gsub(",", ""); + if ($[1] == "CHIP_LAST") + exit; + print $[1]; + } + }' $LINUX/include/drm/amd_asic_type.h) + + for i in $chips; do + $as_echo "#define HAVE_$i" >>config/config-amd-chips.h + done + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) From bf2bee69e5f22d253c1f2e0616fd85d5fa194d06 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 9 Jun 2021 12:42:06 +0800 Subject: [PATCH 0640/2070] drm/amdkcl: wrap the coder under HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE This is caused by 4238367e9de8 "drm/amd/display: force CP to DESIRED when removing display" v5.11-3747-g084150ff1151 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index f605164312e5c..37e8f717c17ea 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -267,9 +267,11 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms); +#endif } mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); From 47be741a16586555db65c04e8b9af9935eb82615 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Jun 2021 15:30:18 +0800 Subject: [PATCH 0641/2070] drm/amdkcl: disable support for 16 bpc fixed-point framebuffers in legacy os This is caused by 0c53c5194ddf "drm/amd/display: Enable support for 16 bpc fixed-point framebuffers." v5.11-3548-g0c53c5194ddf Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Signed-off-by: Ma Jun Change-Id: I20f72b0bd90888520cb4e47453b94ffb1a75c157 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ include/kcl/kcl_drm_fourcc.h | 13 ------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 3e21f89d167a4..1391f091796c5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -55,10 +55,12 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_ABGR2101010, +#ifdef DRM_FORMAT_XRGB16161616 DRM_FORMAT_XRGB16161616, DRM_FORMAT_XBGR16161616, DRM_FORMAT_ARGB16161616, DRM_FORMAT_ABGR16161616, +#endif DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index d40688cb6422d..25cf40f897b23 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -214,17 +214,4 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif - -/* 64 bpp RGB */ -#ifndef DRM_FORMAT_XRGB16161616 -/* Copied from v5.11-3544-ga2fe23ecdbb7 */ -#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ -#endif - -#ifndef DRM_FORMAT_ARGB16161616 -#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ -#endif - #endif /* KCL_KCL_DRM_FOURCC_H */ From 593e429581e6cd67880b2ffd8e121dee9a0d58f5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Jun 2021 13:45:38 +0800 Subject: [PATCH 0642/2070] drm/amdkcl: add DP_* macro for legacy os This is caused by f50245219f8c "drm/amd/display: Partition DPCD address space and break up transactions" v5.11-3817-gf50245219f8c Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_dp_helper.h | 53 ++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index edb6b4202915b..7fb0da12e569b 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -108,10 +108,6 @@ #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ #endif -#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) -#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ -#endif - #if !defined(DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT) #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ #endif @@ -162,4 +158,53 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +/* v5.9-rc4-979-g9782f52ab5d6 + * drm/dp: Add LTTPR helpers + */ +#ifndef DP_TRAINING_PATTERN_SET_PHY_REPEATER + +enum drm_dp_phy { + DP_PHY_DPRX, + + DP_PHY_LTTPR1, + DP_PHY_LTTPR2, + DP_PHY_LTTPR3, + DP_PHY_LTTPR4, + DP_PHY_LTTPR5, + DP_PHY_LTTPR6, + DP_PHY_LTTPR7, + DP_PHY_LTTPR8, + + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, +}; + +#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ +#define DP_LTTPR_BASE(dp_phy) \ + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1)) +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#endif + +#ifndef DP_FEC_STATUS_PHY_REPEATER + +#define __DP_FEC1_BASE 0xf0290 /* 1.4 */ +#define __DP_FEC2_BASE 0xf0298 /* 1.4 */ +#define DP_FEC_BASE(dp_phy) \ + (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1))) +#define DP_FEC_REG(dp_phy, fec1_reg) \ + (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ +#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ + DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) +#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ +#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ + +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From f0c0177f687433cb807cc9bb4a117ba3a9e67b94 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Thu, 17 Jun 2021 10:15:18 -0400 Subject: [PATCH 0643/2070] drm/amdkfd: Set p2plink non-coherent in topology Fix non-coherent bit of p2plink properties flag which always is 0. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index a900d274f7026..9ea0d9cd8c91a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1466,6 +1466,7 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); + kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } } From f2bb8992425cc6babe4803379b529a79c8ad2b9a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 18 Jun 2021 14:02:34 +0800 Subject: [PATCH 0644/2070] drm/amdkcl: fix kgd2kfd_resume() prototype in dkms branch Signed-off-by: Flora Cui Reported-by: chen gong Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 4767c46721c1d..f290ba07dfea9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -512,7 +512,7 @@ static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) { return 0; } From 8b5c301b782852f5ba704270b8bd691dfe7d382f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 18 Jun 2021 13:14:46 +0800 Subject: [PATCH 0645/2070] drm/amdkcl: fake the sysfs_emit_at This is caused by d0d2e18213f7 "amdgpu/pm: replaced snprintf usage in amdgpu_pm.c with sysfs_emit" v5.11-3838-gd0d2e18213f7 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c | 29 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 9 ++++--- include/kcl/kcl_sysfs_emit.h | 10 +++++++ 4 files changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c index 798745cbfff91..0b23918cc8486 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -29,4 +29,33 @@ int sysfs_emit(char *buf, const char *fmt, ...) return len; } EXPORT_SYMBOL_GPL(sysfs_emit); + +/** + * sysfs_emit_at - scnprintf equivalent, aware of PAGE_SIZE buffer. + * @buf: start of PAGE_SIZE buffer. + * @at: offset in @buf to start write in bytes + * @at must be >= 0 && < PAGE_SIZE + * @fmt: format + * @...: optional arguments to @fmt + * + * + * Returns number of characters written starting at &@buf[@at]. + */ +int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf) || at < 0 || at >= PAGE_SIZE, + "invalid sysfs_emit_at: buf:%p at:%d\n", buf, at)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf + at, PAGE_SIZE - at, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit_at); + #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 46af6d633ad0d..1294072c19565 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -912,7 +912,7 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* sysfs_emit() is available */ +/* sysfs_emit() and sysfs_emit_at are available */ #define HAVE_SYSFS_EMIT 1 /* interval_tree_insert have struct rb_root_cached */ diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 index e9f403134af83..c1dc1717cc324 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -1,13 +1,16 @@ dnl # dnl # commit: v5.9-rc5-23-g2efc459d06f1 -dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # sysfs: Add sysfs_emit and sysfs_emit_at dnl # to format sysfs output AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit], + AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit sysfs_emit_at], [fs/sysfs/file.c], [ AC_DEFINE(HAVE_SYSFS_EMIT, 1, - [sysfs_emit() is available]) + [sysfs_emit() and sysfs_emit_at() are available]) ]) ]) ]) + + +) diff --git a/include/kcl/kcl_sysfs_emit.h b/include/kcl/kcl_sysfs_emit.h index ab87e74f817ff..381265a29b7e1 100644 --- a/include/kcl/kcl_sysfs_emit.h +++ b/include/kcl/kcl_sysfs_emit.h @@ -15,11 +15,21 @@ #ifdef CONFIG_SYSFS __printf(2, 3) int sysfs_emit(char *buf, const char *fmt, ...); + +__printf(3, 4) +int sysfs_emit_at(char *buf, int at, const char *fmt, ...); + #else __printf(2, 3) static inline int sysfs_emit(char *buf, const char *fmt, ...) { return 0; } + +__printf(3, 4) +static inline int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + return 0; +} #endif #endif From 6168740f13e615803e789b8a65f8c758a451bfcc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Jul 2021 15:33:05 +0800 Subject: [PATCH 0646/2070] drm/amdkcl: not use xarray for storing pasid in legacy os This is caused by 9538d0fc5286 "drm/amdgpu: use xarray for storing pasid in vm" v5.11-3985-g9538d0fc5286 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 28 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/xarray.m4 | 17 ++++++++++++++ 5 files changed, 54 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/xarray.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d50bac89ba8bc..9bc473745974c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2911,7 +2911,12 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) adev->vm_manager.vm_update_mode = 0; #endif +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->vm_manager.pasid_idr); + spin_lock_init(&adev->vm_manager.pasid_lock); +#endif } /** @@ -2923,8 +2928,13 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) */ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) { +#ifdef HAVE_STRUCT_XARRAY WARN_ON(!xa_empty(&adev->vm_manager.pasids)); xa_destroy(&adev->vm_manager.pasids); +#else + WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); + idr_destroy(&adev->vm_manager.pasid_idr); +#endif amdgpu_vmid_mgr_fini(adev); } @@ -2989,15 +2999,24 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, struct amdgpu_vm *vm; int r; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm) { root = amdgpu_bo_ref(vm->root.bo); is_compute_context = vm->is_compute_context; } else { root = NULL; } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!root) return false; @@ -3015,11 +3034,20 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, goto error_unref; /* Double check that the VM still exists */ +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm && vm->root.bo != root) vm = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!vm) goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index dc4b0ec672ec0..3e65e9a72750f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -482,7 +482,12 @@ struct amdgpu_vm_manager { /* PASID to VM mapping, will be used in interrupt context to * look up VM of a page fault */ +#ifdef HAVE_STRUCT_XARRAY struct xarray pasids; +#else + struct idr pasid_idr; + spinlock_t pasid_lock; +#endif /* Global registration of recent page fault information */ struct amdgpu_vm_fault_info fault_info; }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1294072c19565..c1d8b25aa3b4b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -909,6 +909,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* struct xarray is available */ +#define HAVE_STRUCT_XARRAY 1 + /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b7ce2f4189dba..dfb177d1d0f52 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -106,6 +106,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY + AC_AMDGPU_STRUCT_XARRAY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/xarray.m4 b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 new file mode 100644 index 0000000000000..bfe64c548f1c1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.19-rc5-244-gf8d5d0cc145c +dnl # xarray: Add definition of struct xarray +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_XARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct xarray x; + xa_init(&x); + ], [ + AC_DEFINE(HAVE_STRUCT_XARRAY, 1, + [struct xarray is available]) + ]) + ]) +]) From ab589316de10dabcc866b41d9dd933930e99eba4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Jul 2021 15:44:07 +0800 Subject: [PATCH 0647/2070] drm/amdkcl: add I2C_AQ_NO_ZERO_LEN macro This is caused by b79271766c50 "drm/amdgpu: The I2C IP doesn't support 0 writes/reads" v5.11-3990-gb79271766c50 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_i2c.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h index 66b3195eff49d..2e7f36acdeadc 100644 --- a/include/kcl/kcl_i2c.h +++ b/include/kcl/kcl_i2c.h @@ -23,4 +23,11 @@ i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *inf } #endif +#ifndef I2C_AQ_NO_ZERO_LEN +#define I2C_AQ_NO_ZERO_LEN_READ BIT(5) +#define I2C_AQ_NO_ZERO_LEN_WRITE BIT(6) +#define I2C_AQ_NO_ZERO_LEN (I2C_AQ_NO_ZERO_LEN_READ | I2C_AQ_NO_ZERO_LEN_WRITE) +#endif + + #endif From 01fa3295fe47874f05d758ee06f25874a46ffb12 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 25 Jun 2021 16:50:03 +0800 Subject: [PATCH 0648/2070] drm/amdkcl: wrap the coder under CONFIG_DRM_AMD_DC_DSC_SUPPORT This is caused by b37360fb390e "drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN" v5.11-3882-gb37360fb390e Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- .../display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 2 ++ .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 ++++- .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 2 ++ .../gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c | 2 ++ .../amd/display/dc/resource/dcn31/dcn31_resource.c | 12 ++++++++++++ 5 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 07d362ef0daf3..de58d5886054d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -247,7 +247,9 @@ void enc31_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn31_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc31_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index db2f7cbb12ff5..183db4e247d32 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -276,6 +276,7 @@ void dcn31_init_hw(struct dc *dc) dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -338,6 +339,7 @@ void dcn31_dsc_pg_control( } } +#endif void dcn31_enable_power_gating_plane( @@ -534,10 +536,11 @@ static void dcn31_reset_back_end_for_pipe( dc->hwseq->wa_state.skip_blank_stream = true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); - +#endif pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index e56b9a46aecfe..af7c65b76f8cd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -140,7 +140,9 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn31_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index c6417538090f2..23e66bc6c1ba0 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -489,7 +489,9 @@ static const struct timing_generator_funcs dcn31_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 8ad72557b16a4..a0d49405ab97a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -563,6 +563,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -581,6 +582,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -824,7 +826,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1385,10 +1389,12 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1563,6 +1569,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1577,6 +1584,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn31_destroy_resource_pool(struct resource_pool **pool) { @@ -1842,7 +1850,9 @@ static struct resource_funcs dcn31_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2144,6 +2154,7 @@ static bool dcn31_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2152,6 +2163,7 @@ static bool dcn31_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { From 01b703bbe6176b0e2b7921e213c34a243f8c6889 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 15 Jul 2021 10:11:26 -0400 Subject: [PATCH 0649/2070] drm/amdkcl: fix get list of supported ASIC Use amd_asic_type.h header in DKMS tree instead of system kernel tree to search for supported ASIC. Change-Id: Ie20e9670cecdea28616c325d983f99fb0155b616 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dfb177d1d0f52..3c79482eecf12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -546,7 +546,7 @@ AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ exit; print $[1]; } - }' $LINUX/include/drm/amd_asic_type.h) + }' ../../include/drm/amd_asic_type.h) for i in $chips; do $as_echo "#define HAVE_$i" >>config/config-amd-chips.h From 6d4cfa12807505a7c77270eb8d0575048485f5d0 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 17 May 2021 19:48:51 -0400 Subject: [PATCH 0650/2070] drm/amdkfd: synchronize runtime enable with the debugger If the debugger is attached, raise an EC_PROCESS_RUNTIME_ENABLE/DISABLE event on runtime enable/disable and block until the debugger sends the process event to unblock. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 468dbe49ac80d..e0f5875f9eb03 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -39,6 +39,7 @@ #include #include #include +#include /* amdkcl: this header file is included in kcl_device_cgroup.h #include */ #include From 21e568c4ad09724f75d964bcf487cf9cfc788ec5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 12:28:49 +0800 Subject: [PATCH 0651/2070] drm/amdkcl: Add const cast to adapt function prototype and Fix compile warning Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c2dac790ba1c8..6dea17070b5de 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -68,9 +68,9 @@ static inline void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) { #ifndef HAVE_DRM_DRM_PRINT_H - drm_mm_debug_table(mm, p->prefix); + drm_mm_debug_table((struct drm_mm *)mm, p->prefix); #else - drm_mm_debug_table(mm, "no prefix"); + drm_mm_debug_table((struct drm_mm *)mm, "no prefix"); #endif } #endif From 28fb314387f274165662e0e5d568521abbccf468 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 13:47:37 +0800 Subject: [PATCH 0652/2070] drm/amdkcl: Fix redefined dma_fence_default_wait macro Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/backport/kcl_fence_backport.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 022951286bb7d..7e3e1ab42138b 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -19,6 +19,11 @@ * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) */ #ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT + +#ifdef dma_fence_default_wait +#undef dma_fence_default_wait +#endif + #define dma_fence_default_wait _kcl_fence_default_wait #define dma_fence_wait_timeout _kcl_fence_wait_timeout #endif From 1696a39c5292c8a22f0526ebde4c732dad8290f1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 13:47:19 +0800 Subject: [PATCH 0653/2070] drm/amdkcl: Remove unused local variable Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 58beb9fcedf38..c0f145df309d3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -71,15 +71,15 @@ EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); */ void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) { - struct drm_device *dev = state->dev; struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; - int i; #if !defined(for_each_new_crtc_in_state) + struct drm_device *dev = state->dev; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { new_crtc_state = crtc->state; #else + int i; for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { #endif if (new_crtc_state->enable) From 87e3db63188549d94d376df678bcbe364d92050e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 16:02:19 +0800 Subject: [PATCH 0654/2070] drm/amdkcl: wrap function dma_fence_test_signaled_any under the macro Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index ed889c91b8dd4..1376705d31822 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -26,6 +26,7 @@ #include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ +#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) || defined(AMDKCL_FENCE_WAIT_ANY_TIMEOUT) static bool dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, uint32_t *idx) @@ -42,6 +43,7 @@ dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, } return false; } +#endif struct default_wait_cb { struct dma_fence_cb base; From 79e7b8eeffd9150db1bfcf3e73539c3575064e08 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 20 Jul 2021 22:10:49 -0400 Subject: [PATCH 0655/2070] drm/amdkfd: IPC export and import memory alloc flags Support query pointer info memory alloc flags, ex CoarseGrain, for shared memory by IPC. App pass memory alloc flags to export handle ioctl, to save memory alloc flags to ipc object, import handle ioctl get ipc object and pass memory alloc flags back to app which could be different process. Keep import export handle ioctl interface, rename unused _u32 pad field to flags. Signed-off-by: Philip Yang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 12 ++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 9 ++++++--- include/uapi/linux/kfd_ioctl.h | 6 +++--- 6 files changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index f290ba07dfea9..e95014cf30784 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -369,7 +369,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, struct kgd_mem *mem, - struct kfd_ipc_obj **ipc_obj); + struct kfd_ipc_obj **ipc_obj, + uint32_t flags); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7834af6e7fd69..99ad1cec3657a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2780,7 +2780,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, struct kgd_mem *mem, - struct kfd_ipc_obj **ipc_obj) + struct kfd_ipc_obj **ipc_obj, + uint32_t flags) { struct amdgpu_device *adev = NULL; struct dma_buf *dmabuf; @@ -2803,7 +2804,7 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, goto unlock_out; } - r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj); + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags); if (r) dma_buf_put(dmabuf); else diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index eb3e0b4741325..d162e65cdbf89 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1682,7 +1682,8 @@ static int kfd_ioctl_ipc_export_handle(struct file *filep, if (!dev) return -EINVAL; - r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle); + r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle, + args->flags); if (r) pr_err("Failed to export IPC handle\n"); @@ -1703,7 +1704,7 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, - &args->mmap_offset); + &args->mmap_offset, &args->flags); if (r) pr_err("Failed to import IPC handle\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 88ab20909ce39..b5d89265d3c2d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -41,7 +41,8 @@ static struct kfd_ipc_handles { */ #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) -int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags) { struct kfd_ipc_obj *obj; @@ -59,6 +60,7 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) kref_init(&obj->ref); obj->dmabuf = dmabuf; get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + obj->flags = flags; mutex_lock(&kfd_ipc_handles.lock); hlist_add_head(&obj->node, @@ -182,7 +184,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) + uint64_t *mmap_offset, uint32_t *pflags) { int r; struct kfd_ipc_obj *entry, *found = NULL; @@ -212,6 +214,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (r) goto error_unref; + *pflags = found->flags; return r; error_unref: @@ -220,7 +223,8 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, } int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, - uint64_t handle, uint32_t *ipc_handle) + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags) { struct kfd_process_device *pdd = NULL; struct kfd_ipc_obj *ipc_obj; @@ -249,7 +253,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, - &ipc_obj); + &ipc_obj, flags); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 72fe8e4af2e5c..7915b8cad13db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -36,20 +36,23 @@ struct kfd_ipc_obj { struct kref ref; struct dma_buf *dmabuf; uint32_t share_handle[4]; + uint32_t flags; }; int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset); + uint64_t *mmap_offset, uint32_t *pflags); int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset); int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, - uint64_t handle, uint32_t *ipc_handle); + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags); -int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj); +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags); void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 647a97374a315..bf6e0832d7cdd 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -834,16 +834,16 @@ struct kfd_ioctl_ipc_export_handle_args { __u64 handle; /* to KFD */ __u32 share_handle[4]; /* from KFD */ __u32 gpu_id; /* to KFD */ - __u32 pad; + __u32 flags; /* to KFD */ }; struct kfd_ioctl_ipc_import_handle_args { __u64 handle; /* from KFD */ __u64 va_addr; /* to KFD */ - __u64 mmap_offset; /* from KFD */ + __u64 mmap_offset; /* from KFD */ __u32 share_handle[4]; /* to KFD */ __u32 gpu_id; /* to KFD */ - __u32 pad; + __u32 flags; /* from KFD */ }; /* Guarantee host access to memory */ From 6158fa349a8c3b59b0a1eadd959cbb92f686b15a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 14:14:34 +0800 Subject: [PATCH 0656/2070] drm/amdkcl: Test whether struct dev_pagemap has member range This is caused by 1d5dbfe6c06a "drm/amdkfd: classify and map mixed svm range pages in GPU" v5.13-rc7-1639-g1d5dbfe6c06a Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 9fcfeca400339..f79b4ebbda6a5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -185,7 +185,11 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange, addr[i] = (hmm_pfns[i] << PAGE_SHIFT) + bo_adev->vm_manager.vram_base_offset - +#ifdef HAVE_DEV_PAGEMAP_RANGE bo_adev->kfd.pgmap.range.start; +#else + bo_adev->kfd.dev->pgmap.res.start; +#endif addr[i] |= SVM_RANGE_VRAM_DOMAIN; pr_debug_ratelimited("vram address: 0x%llx\n", addr[i]); continue; From f7e3416cb3f739d7024393ea99384840b4355988 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 14:44:49 +0800 Subject: [PATCH 0657/2070] drm/amdkcl: wrap the code under macro HAVE_DRM_DP_AUX_DRM_DEV This is caused by 6cba3fe43341 "drm/dp: Add backpointer to drm_device in drm_dp_aux" v5.12-rc7-1495-g6cba3fe43341 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3db84128cfdef..15d0ee425f106 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -950,7 +950,9 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", link_index); aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; +#ifdef HAVE_DRM_DP_AUX_DRM_DEV aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; +#endif aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; drm_dp_aux_init(&aconnector->dm_dp_aux.aux); From 78d3806542bcd0ea27ed6d42335f1377744e1adc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 15:35:04 +0800 Subject: [PATCH 0658/2070] =?UTF-8?q?drm/amdkcl:=20Test=20whether=20drm=5F?= =?UTF-8?q?connector=5Fatomic=5Fhdr=5Fmetadata=5Fequal=EF=BC=88=EF=BC=89?= =?UTF-8?q?=20is=20available?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is caused by 72921cdf8ac2 "drm/connector: Add helper to compare HDR metadata" v5.12-rc7-1582-g72921cdf8ac2 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 23 +++++++++++++++++++ ...drm-connector-atomic-hdr-metadata-equal.m4 | 16 +++++++++++++ ...drm-connector-state-hdr-output-metadata.m4 | 17 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 5 ++++ include/kcl/kcl_drm_connector.h | 5 ++++ 5 files changed, 66 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index ebcb2ae541c33..f8bb8819388e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -40,3 +40,26 @@ amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 prot_cap[4]) #endif + +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state) +{ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + struct drm_property_blob *old_blob = old_state->hdr_output_metadata; + struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + + if (!old_blob || !new_blob) + return old_blob == new_blob; + + if (old_blob->length != new_blob->length) + return false; + + return !memcmp(old_blob->data, new_blob->data, old_blob->length); +#else + return false; +#endif +} +EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 new file mode 100644 index 0000000000000..7ae2c3fd78efd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1582-g72921cdf8ac2 +dnl # drm/connector: Add helper to compare HDR metadata +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_atomic_hdr_metadata_equal(NULL, NULL); + ], [drm_connector_atomic_hdr_metadata_equal], [drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, + [drm_connector_atomic_hdr_metadata_equal() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 new file mode 100644 index 0000000000000..d79d5c876e35b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.1-rc5-1688-gfbb5d0353c62 +dnl # drm: Add HDR source metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdr_output_metadata = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA, 1, + [struct drm_connector_state has hdr_output_metadata member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3c79482eecf12..af26d21bc0ce9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -119,6 +119,11 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY + AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + AC_AMDGPU_DMA_BUF_UNPIN + AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN + AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index d0548c78ac046..60b46940afa02 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -83,4 +83,9 @@ void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_ #define DRM_MODE_SUBCONNECTOR_Wireless 18 #endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state); +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 2f9214568b589e717cf0fb72ce1bb7c7d2c5b386 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 16:05:02 +0800 Subject: [PATCH 0659/2070] =?UTF-8?q?drm/amdkcl:=20Test=20whether=20drm=5F?= =?UTF-8?q?connector=5Fattach=5Fhdr=5Foutput=5Fmetadata=5Fproperty?= =?UTF-8?q?=EF=BC=88=EF=BC=89=20is=20available?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is caused by e057b52c1d90 "drm/connector: Create a helper to attach the hdr_output_metadata property" v5.12-rc7-1581-ge057b52c1d90 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 15 +++++++++++++++ ...nector-attach-hdr-output-metadata-property.m4 | 16 ++++++++++++++++ include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index f8bb8819388e6..79c907264d709 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -63,3 +63,18 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta } EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); #endif + +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.hdr_output_metadata_property; + + drm_object_attach_property(&connector->base, prop, 0); +#endif + + return 0; +} +EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 new file mode 100644 index 0000000000000..fccf8755fc7fe --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1581-ge057b52c1d90 +dnl # drm/connector: Create a helper to attach the hdr_output_metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_attach_hdr_output_metadata_property(NULL); + ], [drm_connector_attach_hdr_output_metadata_property], [drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, + [drm_connector_attach_hdr_output_metadata_property() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 60b46940afa02..02b2633b0c66f 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -88,4 +88,8 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta struct drm_connector_state *new_state); #endif +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 2fb78b8f79d9e956234b4c213687666bff3cf661 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 16:57:47 +0800 Subject: [PATCH 0660/2070] drm/amdkcl: Test whether drm_plane_helper_funcs.atomic_check second param is struct drm_atomic_state* This is caused by 5ddb0bd4ddc3 "drm/atomic: Pass the full state to planes async atomic check and update" v5.11-rc2-698-g5ddb0bd4ddc3 Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ib363f19e14009df6191f30959f76fe17ce68a5ca --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 33 ++++++++++++++++--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 18 ++++++++++ 3 files changed, 48 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 1391f091796c5..1bcbc658b7c3d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1239,10 +1239,18 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, } static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state = state; +#endif struct amdgpu_device *adev = drm_to_adev(plane->dev); struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state; @@ -1257,8 +1265,12 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = kcl_drm_atomic_get_new_crtc_state_before_commit( - state, new_plane_state->crtc); + new_crtc_state = +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif if (!new_crtc_state) return -EINVAL; @@ -1278,7 +1290,11 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, } static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_atomic_state *state, bool flip) +#else + struct drm_plane_state *state, bool flip) +#endif { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; @@ -1419,12 +1435,21 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *new_state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); +#else + struct drm_plane_state *old_state = + drm_atomic_get_old_plane_state(new_state->state, plane); +#endif trace_amdgpu_dm_atomic_update_cursor(new_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index af26d21bc0ce9..b09c2a2973053 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -78,6 +78,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 new file mode 100644 index 0000000000000..3f28dbaae58fe --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -0,0 +1,18 @@ +dnl # commit v5.11-rc2-701-g7c11b99a8e58 +dnl # drm/atomic: Pass the full state to planes atomic_check +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs *funcs = NULL; + funcs->atomic_check((struct drm_crtc *)NULL, (struct drm_atomic_state *)NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, + [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS],[AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS +]) From b1ea2048ee64fb185d9f73b68ae738365b9a807f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 17:15:56 +0800 Subject: [PATCH 0661/2070] drm/amdkcl: fix build error for renamed struct field Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index ef1c82463f8e0..5acf8485888f7 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -32,7 +32,7 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, struct dma_buf_map map; map.vaddr = vaddr; - map.is_iomem = bo->mem.bus.is_iomem; + map.is_iomem = bo->resource->bus.is_iomem; ttm_bo_vunmap(bo, &map); } From de20ca7f3f2f9a42bff3bc2ec8f8610d18816f9e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 13 Aug 2021 16:26:58 +0800 Subject: [PATCH 0662/2070] drm/amdkcl: access resv field using amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 8f033e4687923..9375e31f76d7e 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -426,8 +426,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, { struct ttm_resource *res = bo->resource; - dma_resv_assert_held(bo->base.resv); - + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (res->mem_type == TTM_PL_SYSTEM) return true; From a99808bc54d7ab381bba212a3335de6422398d56 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 18 Aug 2021 10:51:54 +0800 Subject: [PATCH 0663/2070] drm/amdkcl: DROPME rework config.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 81 +++++++++++++++++------- 1 file changed, 59 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c1d8b25aa3b4b..3e9eeb36639ee 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -#define HAVE_ACPI_PUT_TABLE 1 +/* #undef HAVE_ACPI_PUT_TABLE */ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 @@ -35,7 +35,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -121,6 +121,12 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_AMD_ASIC_TYPE_H 1 + +/* drm_aperture_remove_* is availablea */ +#define HAVE_DRM_APERTURE 1 + /* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are available */ #define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 @@ -134,9 +140,6 @@ /* drm_atomic_helper_check_plane_state() is available */ #define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 -/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 - /* drm_atomic_helper_shutdown() is available */ #define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 @@ -169,6 +172,12 @@ /* drm_color_lut_size() is available */ #define HAVE_DRM_COLOR_LUT_SIZE 1 +/* drm_connector_atomic_hdr_metadata_equal() is available */ +/* #undef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL */ + +/* drm_connector_attach_hdr_output_metadata_property() is available */ +/* #undef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY */ + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -258,12 +267,21 @@ /* drm_dp_atomic_find_vcpi_slots() wants 5args */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 +/* struct drm_dp_aux has member named 'drm_dev' */ +#define HAVE_DRM_DP_AUX_DRM_DEV 1 + /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 +/* drm_dp_link_train_channel_eq_delay() has 2 args */ +/* #undef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS */ + +/* drm_dp_link_train_clock_recovery_delay() has 2 args */ +/* #undef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS */ + /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 @@ -321,6 +339,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_APERTURE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 @@ -420,13 +441,13 @@ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 /* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ -#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS 1 +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ /* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ /* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ /* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ -#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP 1 +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 @@ -452,18 +473,15 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 +/* drm_gem_prime_mmap() is available */ +/* #undef HAVE_DRM_GEM_PRIME_MMAP */ + /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 -/* drm_get_format_info() is available */ -#define HAVE_DRM_GET_FORMAT_INFO 1 - -/* drm_get_format_name() has i,p interface */ -#define HAVE_DRM_GET_FORMAT_NAME_I_P 1 - /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -485,6 +503,9 @@ /* drm_kms_helper_is_poll_worker() is available */ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 +/* drm_memcpy_from_wc() is availablea */ +#define HAVE_DRM_MEMCPY_FROM_WC 1 + /* whether drm_mm_insert_mode is available */ #define HAVE_DRM_MM_INSERT_MODE 1 @@ -624,12 +645,27 @@ /* in_compat_syscall is defined */ #define HAVE_IN_COMPAT_SYSCALL 1 +/* io_mapping_map_local_wc() is available */ +#define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 + +/* io_mapping_unmap_local() is available */ +#define HAVE_IO_MAPPING_UNMAP_LOCAL 1 + +/* is_cow_mapping() is available */ +#define HAVE_IS_COW_MAPPING 1 + /* jiffies64_to_msecs() is available */ #define HAVE_JIFFIES64_TO_MSECS 1 /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* kernel_write() take arg type of position as pointer */ +#define HAVE_KERNEL_WRITE_PPOS 1 + +/* kmap_local_page_prot() is available */ +#define HAVE_KMAP_LOCAL_PAGE_PROT 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 @@ -780,6 +816,9 @@ /* pci_dev_id() is available */ #define HAVE_PCI_DEV_ID 1 +/* struct pci_driver has field dev_groups */ +#define HAVE_PCI_DRIVER_DEV_GROUPS 1 + /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 @@ -811,7 +850,7 @@ #define HAVE_PXM_TO_NODE 1 /* remove_conflicting_framebuffers() returns int */ -/* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ +#define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 @@ -858,11 +897,8 @@ /* drm_crtc_funcs->enable_vblank() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 -/* crtc->funcs->gamma_set() wants 5 args */ -/* #undef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS */ - -/* crtc->funcs->gamma_set() wants 6 args */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 /* struct drm_crtc_funcs->get_vblank_timestamp() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 @@ -900,8 +936,9 @@ /* drm_pending_vblank_event->sequence is available */ #define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 -/* drm_plane_helper_funcs->atomic_async_check() is available */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 +/* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state + arg */ +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -915,7 +952,7 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* sysfs_emit() and sysfs_emit_at are available */ +/* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 /* interval_tree_insert have struct rb_root_cached */ From deb5ecc757302e6052fa4c45e037543a6e40494d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 20 Aug 2021 17:45:09 +0800 Subject: [PATCH 0664/2070] drm/amdkcl: fake drm_gem_mmap for drm_gem_prime_mmap for legacy ps This is caused by following commits: 71df0368e9b6 drm/amdgpu: Implement mmap as GEM object function 47d35c1c40d5 drm: Set vm_ops to GEM object's values during mmap Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 48 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 + drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/include/kcl/kcl_amdgpu_drm_gem.h | 49 ++++++ drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 149 ++++++++++++++++++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 77 +++++++++ include/drm/ttm/ttm_bo.h | 14 ++ include/drm/ttm/ttm_device.h | 18 +++ 12 files changed, 454 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 89e90afd122fc..03dcd8b7fdc16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -44,6 +44,54 @@ #include #include +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation + * @obj: GEM BO + * @vma: Virtual memory area + * + * Sets up a userspace mapping of the BO's memory in the given + * virtual memory area. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + unsigned asize = amdgpu_bo_size(bo); + int ret; + + if (!vma->vm_file) + return -ENODEV; + + if (adev == NULL) + return -ENODEV; + + /* Check for valid size. */ + if (asize < vma->vm_end - vma->vm_start) + return -EINVAL; + + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || + (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { + return -EPERM; + } + vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; + + /* prime mmap does not need to check access, so allow here */ + ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); + if (ret) + return ret; + + ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); + drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); + + return ret; +} +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) static int __dma_resv_make_exclusive(struct dma_resv *obj) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index f7a7492b68f55..dbc9384febd43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -54,6 +54,12 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); +#endif + + extern const struct dma_buf_ops amdgpu_dmabuf_ops; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 2a9f4a1504fa4..4e0fb7e5100b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3074,7 +3074,7 @@ static const struct file_operations amdgpu_driver_kms_fops = { .flush = amdgpu_flush, .release = amdgpu_drm_release, .unlocked_ioctl = amdgpu_drm_ioctl, - .mmap = drm_gem_mmap, + .mmap = amdkcl_drm_gem_mmap, .poll = drm_poll, .read = drm_read, #ifdef CONFIG_COMPAT @@ -3204,7 +3204,8 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_vunmap = drm_gem_ttm_vunmap, #endif - .gem_prime_mmap = drm_gem_prime_mmap, + .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, + .name = DRIVER_NAME, .desc = DRIVER_DESC, .major = KMS_DRIVER_MAJOR, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5a91dbdf4f73f..3f56584d17241 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -187,6 +187,27 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entit return amdgpu_job_submit(job); } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_verify_access - Verify access for a mmap call + * + * @bo: The buffer object to map + * @filp: The file pointer from the process performing the mmap + * + * This is called by ttm_bo_mmap() to verify whether a process + * has the right to mmap a BO to their process space. + */ +static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) +{ + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); + + if (amdgpu_ttm_tt_get_usermm(bo->ttm)) + return -EPERM; + return drm_vma_node_verify_access(&abo->tbo.base.vma_node, + filp->private_data); +} +#endif + /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @entity: entity to run the window setup job @@ -1944,6 +1965,9 @@ static struct ttm_device_funcs amdgpu_bo_driver = { .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, .move = &amdgpu_bo_move, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .verify_access = &amdgpu_verify_access, +#endif .delete_mem_notify = &amdgpu_bo_delete_mem_notify, .release_notify = &amdgpu_bo_release_notify, .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, @@ -2978,6 +3002,66 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, DMA_RESV_USAGE_BOOKKEEP); } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vma->vm_private_data; +#else +static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vmf->vma->vm_private_data; +#endif + vm_fault_t ret; + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_reserve(bo, vmf, vma); +#else + ret = ttm_bo_vm_reserve(bo, vmf); +#endif + if (ret) + return ret; + + ret = amdgpu_bo_fault_reserve_notify(bo); + if (ret) + goto unlock; + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_fault_reserved(vmf, vma, vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); +#else + ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); +#endif + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) + return ret; + +unlock: + dma_resv_unlock(amdkcl_ttm_resvp(bo)); + return ret; +} + +static struct vm_operations_struct amdgpu_ttm_vm_ops = { + .fault = amdgpu_ttm_fault, + .open = ttm_bo_vm_open, + .close = ttm_bo_vm_close, + .access = ttm_bo_vm_access +}; + +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *file_priv = filp->private_data; + struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); + int r; + + r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); + if (unlikely(r != 0)) + return r; + + vma->vm_ops = &amdgpu_ttm_vm_ops; + return 0; +} +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + int amdgpu_copy_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, uint64_t src_offset, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index cfb10ecf74047..1c9d811c6e65b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -203,6 +203,10 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, struct dma_fence **f, u64 k_job_id); +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); +#endif + int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index ba3805d29cbc3..fa78abd428129 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o + kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 06e34a8321b0d..a3680a9030c43 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -65,6 +65,7 @@ #include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_drm_aperture.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h new file mode 100644 index 0000000000000..9ad60a7646fa0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h @@ -0,0 +1,49 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return _kcl_drm_gem_mmap(filp, vma); +} + + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return _kcl_drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c new file mode 100644 index 0000000000000..328395cbd0125 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -0,0 +1,149 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "amdgpu_ttm.h" +#include "amdgpu_dma_buf.h" + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return amdgpu_mmap(filp, vma); +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return amdgpu_gem_prime_mmap(obj, vma); +} + +#else +static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + struct vm_area_struct *vma) +{ + int ret; + + /* Check for valid size. */ + if (obj_size < vma->vm_end - vma->vm_start) + return -EINVAL; + + /* Take a ref for this mapping of the object, so that the fault + * handler can dereference the mmap offset's pointer to the object. + * This reference is cleaned up by the corresponding vm_close + * (which should happen whether the vma was created by this call, or + * by a vm_open due to mremap or partial unmap or whatever). + */ + drm_gem_object_get(obj); + + vma->vm_private_data = obj; + vma->vm_ops = obj->funcs->vm_ops; + + if (obj->funcs->mmap) { + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; + WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (!vma->vm_ops) { + ret = -EINVAL; + goto err_drm_gem_object_put; + } + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + } + + return 0; + +err_drm_gem_object_put: + drm_gem_object_put(obj); + return ret; +} + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + struct drm_file *priv = filp->private_data; + struct drm_device *dev = priv->minor->dev; + struct drm_gem_object *obj = NULL; + struct drm_vma_offset_node *node; + int ret; + + if (drm_dev_is_unplugged(dev)) + return -ENODEV; + + drm_vma_offset_lock_lookup(dev->vma_offset_manager); + node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, + vma->vm_pgoff, + vma_pages(vma)); + if (likely(node)) { + obj = container_of(node, struct drm_gem_object, vma_node); + /* + * When the object is being freed, after it hits 0-refcnt it + * proceeds to tear down the object. In the process it will + * attempt to remove the VMA offset and so acquire this + * mgr->vm_lock. Therefore if we find an object with a 0-refcnt + * that matches our range, we know it is in the process of being + * destroyed and will be freed as soon as we release the lock - + * so we have to check for the 0-refcnted object and treat it as + * invalid. + */ + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); + + if (!obj) + return -EINVAL; + + if (!drm_vma_node_is_allowed(node, priv)) { + drm_gem_object_put(obj); + return -EACCES; + } + + if (node->readonly) { + if (vma->vm_flags & VM_WRITE) { + drm_gem_object_put(obj); + return -EINVAL; + } + + vma->vm_flags &= ~VM_MAYWRITE; + } + + ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, + vma); + + drm_gem_object_put(obj); + + return ret; + +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + if (obj->funcs && obj->funcs->mmap) { + vma->vm_ops = obj->funcs->vm_ops; + } + return drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 35c5c94f997fa..a60019a2d730e 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -517,6 +517,83 @@ static const struct vm_operations_struct ttm_bo_vm_ops = { .access = ttm_bo_vm_access, }; +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +static struct ttm_buffer_object *ttm_bo_vm_lookup(struct ttm_device *bdev, + unsigned long offset, + unsigned long pages) +{ + struct drm_vma_offset_node *node; + struct ttm_buffer_object *bo = NULL; + + drm_vma_offset_lock_lookup(bdev->vma_manager); + + node = drm_vma_offset_lookup_locked(bdev->vma_manager, offset, pages); + if (likely(node)) { + bo = container_of(node, struct ttm_buffer_object, + base.vma_node); + bo = ttm_bo_get_unless_zero(bo); + } + + drm_vma_offset_unlock_lookup(bdev->vma_manager); + + if (!bo) + pr_err("Could not find buffer object to map\n"); + + return bo; +} + +static void ttm_bo_mmap_vma_setup(struct ttm_buffer_object *bo, struct vm_area_struct *vma) +{ + vma->vm_ops = &ttm_bo_vm_ops; + + /* + * Note: We're transferring the bo reference to + * vma->vm_private_data here. + */ + + vma->vm_private_data = bo; + + /* + * We'd like to use VM_PFNMAP on shared mappings, where + * (vma->vm_flags & VM_SHARED) != 0, for performance reasons, + * but for some reason VM_PFNMAP + x86 PAT + write-combine is very + * bad for performance. Until that has been sorted out, use + * VM_MIXEDMAP on all mappings. See freedesktop.org bug #75719 + */ + vma->vm_flags |= VM_PFNMAP; + vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; +} + +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_device *bdev) +{ + struct ttm_buffer_object *bo; + int ret; + + if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET_START)) + return -EINVAL; + + bo = ttm_bo_vm_lookup(bdev, vma->vm_pgoff, vma_pages(vma)); + if (unlikely(!bo)) + return -EINVAL; + + if (unlikely(!bo->bdev->funcs->verify_access)) { + ret = -EPERM; + goto out_unref; + } + ret = bo->bdev->funcs->verify_access(bo, filp); + if (unlikely(ret != 0)) + goto out_unref; + + ttm_bo_mmap_vma_setup(bo, vma); + return 0; +out_unref: + ttm_bo_put(bo); + return ret; +} +EXPORT_SYMBOL(ttm_bo_mmap); +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + /** * ttm_bo_mmap_obj - mmap memory backed by a ttm buffer object. * diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 71ed1026d0933..8da654b4aac5c 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -430,6 +430,20 @@ void *ttm_bo_kmap_try_from_panic(struct ttm_buffer_object *bo, unsigned long pag int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map); void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map); int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct ttm_buffer_object *bo); + +/** + * ttm_bo_mmap - mmap out of the ttm device address space. + * + * @filp: filp as input from the mmap method. + * @vma: vma as input from the mmap method. + * @bdev: Pointer to the ttm_device with the address space manager. + * + * This function is intended to be called by the device mmap method. + * if the device address space is to be backed by the bo manager. + */ +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_device *bdev); + s64 ttm_bo_swapout(struct ttm_device *bdev, struct ttm_operation_ctx *ctx, struct ttm_resource_manager *man, gfp_t gfp_flags, s64 target); diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h index 5618aef462f21..b8df427c05b7a 100644 --- a/include/drm/ttm/ttm_device.h +++ b/include/drm/ttm/ttm_device.h @@ -152,6 +152,24 @@ struct ttm_device_funcs { struct ttm_resource *new_mem, struct ttm_place *hop); +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + /** + * struct ttm_bo_driver_member verify_access + * + * @bo: Pointer to a buffer object. + * @filp: Pointer to a struct file trying to access the object. + * + * Called from the map / write / read methods to verify that the + * caller is permitted to access the buffer object. + * This member may be set to NULL, which will refuse this kind of + * access for all buffer objects. + * This function should return 0 if access is granted, -EPERM otherwise. + */ + int (*verify_access)(struct ttm_buffer_object *bo, + struct file *filp); +#endif + + /** * Hook to notify driver about a resource delete. */ From d4f0392239d5800f9dfaab294e980b29f3d5cf7e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 10:22:00 +0800 Subject: [PATCH 0665/2070] drm/amdkcl: wrap the code under macro drmm_add_action_or_reset This is caused by 267d51d77fda "drm/amdgpu: Implement mmap as GEM object function" v5.13-rc1-231-g267d51d77fda Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index a60019a2d730e..a3c28b76a1a43 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -329,9 +329,11 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) return VM_FAULT_OOM; /* Set the page to be freed using drmm release action */ +#ifdef drmm_add_action_or_reset if (drmm_add_action_or_reset(bo->base.dev, ttm_bo_release_dummy_page, page)) return VM_FAULT_OOM; +#endif pfn = page_to_pfn(page); From d81a0581cf85a21b261f736de7d8854743ce9e88 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 11:06:02 +0800 Subject: [PATCH 0666/2070] drm/amdkcl: Test whether dma_buf_unpin() is available This is caused by a448cb003edc "drm/amdgpu: implement amdgpu_gem_prime_move_notify v2" v5.6-rc2-339-ga448cb003edc Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 | 34 ++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b09ed112c96af..bffcb0cb94be7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1049,8 +1049,10 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; +#ifdef HAVE_DMA_BUF_UNPIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_unpin(bo->tbo.base.import_attach); +#endif if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 new file mode 100644 index 0000000000000..4c07a856211f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.6-rc2-335-gbb42df4662a4 +dnl # dma-buf: add dynamic DMA-buf handling v15 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_UNPIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_unpin(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_UNPIN, 1, + [dma_buf_unpin() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->unpin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_UNPIN, 1, + [struct dma_buf_ops->unpin() is available]) + ]) + ]) +]) + + + + From ae6c12d44247520e5274a453f41995408416c923 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 12:46:55 +0800 Subject: [PATCH 0667/2070] drm/amdkcl: Test whether linux/pgtable.h is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ drivers/gpu/drm/ttm/ttm_module.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5c9cf41e67120..05687ebbd1ec7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -56,4 +56,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/aperture: Add infrastructure for aperture ownership dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + + dnl # + dnl # v5.7-13141-gca5999fde0a1 + dnl # mm: introduce include/linux/pgtable.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index aa137ead5cc59..bf00d0ff320f5 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -31,7 +31,9 @@ */ #include #include +#ifdef HAVE_LINUX_PGTABLE_H #include +#endif #include #include #include From b61f3e348a1bf0ee3102beeeeaaf2bef885f944f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 14:23:20 +0800 Subject: [PATCH 0668/2070] drm/amdkcl: wrap the code under macro HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index acca2cdc77e90..7173e73cea38a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -416,6 +416,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, drm_exec_fini(&exec); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); @@ -436,6 +437,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#endif #ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { From b7fc1bd9b48a0aebc163aeca351c31f0be17bb4d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 11:02:08 +0800 Subject: [PATCH 0669/2070] drm/amdkcl: adapt code for remove_conflicting_pci_framebuffers with argument numbers Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 6 +++ drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../m4/remove-conflicting-pci-framebuffers.m4 | 26 ++++++++++++ include/kcl/kcl_drm_fb.h | 14 +++++++ 5 files changed, 87 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index b3fa22920b7f2..99c29f3b4c803 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -126,7 +126,13 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const #ifdef HAVE_VGA_REMOVE_VGACON #if IS_REACHABLE(CONFIG_FB) + +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG ret = remove_conflicting_pci_framebuffers(pdev, name); +#else + ret = remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif + #endif if (ret == 0) ret = vga_remove_vgacon(pdev); diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 11a2fe7ab066e..18f2a20d821da 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -15,6 +15,44 @@ /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) + +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + struct apertures_struct *ap; + bool primary = false; + int err, idx, bar; + + for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + idx++; + } + + ap = alloc_apertures(idx); + if (!ap) + return -ENOMEM; + + for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + ap->ranges[idx].base = pci_resource_start(pdev, bar); + ap->ranges[idx].size = pci_resource_len(pdev, bar); + pci_dbg(pdev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, + (unsigned long)pci_resource_start(pdev, bar), + (unsigned long)pci_resource_end(pdev, bar)); + idx++; + } + +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & + IORESOURCE_ROM_SHADOW; +#endif + err = remove_conflicting_framebuffers(ap, name, primary); + kfree(ap); + return err; +} +#else /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) { struct apertures_struct *ap; @@ -39,5 +77,7 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const kfree(ap); return err; } +#endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ + EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b09c2a2973053..385bb8188945a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -125,6 +125,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_BUF_UNPIN AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..06241044fe4d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.3-rc1-540-g0a8459693238 +dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers +dnl # +AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + remove_conflicting_pci_framebuffers(NULL, NULL); + ],[ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG, 1, + [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG, 1, + [remove_conflicting_pci_framebuffers() is available and has res_id arg]) + ]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 9bc9148fc5854..fcc020c4d6e97 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -76,14 +76,24 @@ __and(IS_MODULE(option), __is_defined(MODULE))) #endif /*IS_REACHABLE*/ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name); +#else extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name); +#endif + static inline int _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { #if IS_REACHABLE(CONFIG_FB) +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG + return remove_conflicting_pci_framebuffers(pdev, name); +#else return remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif #else return 0; #endif @@ -93,7 +103,11 @@ static inline int _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); +#endif } #endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ From f4820b3b4f8ed4d2319ec1ac1cbab19c36b99d2d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 13:22:55 +0800 Subject: [PATCH 0670/2070] drm/amdkcl: fake drm_dev_{enter, exit, is_unplugged} for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 | 19 +++++ .../drm/amd/dkms/m4/drm-dev-is-unplugged.m4 | 21 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_drv.h | 66 +++++++++++++++++ 8 files changed, 184 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 create mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 200f718370bd0..ef4f57f9cfeeb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,6 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o + kcl_drm_drv.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c new file mode 100644 index 0000000000000..8014069a7c654 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -0,0 +1,73 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef HAVE_DRM_DEV_ENTER +#include +#include + +DEFINE_STATIC_SRCU(drm_unplug_srcu); + +/** + * drm_dev_enter - Enter device critical section + * @dev: DRM device + * @idx: Pointer to index that will be passed to the matching drm_dev_exit() + * + * This function marks and protects the beginning of a section that should not + * be entered after the device has been unplugged. The section end is marked + * with drm_dev_exit(). Calls to this function can be nested. + * + * Returns: + * True if it is OK to enter the section, false otherwise. + */ +bool drm_dev_enter(struct drm_device *dev, int *idx) +{ + *idx = srcu_read_lock(&drm_unplug_srcu); + + if (atomic_read(&dev->unplugged)) { + srcu_read_unlock(&drm_unplug_srcu, *idx); + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_dev_enter); + +/** + * drm_dev_exit - Exit device critical section + * @idx: index returned from drm_dev_enter() + * + * This function marks the end of a section that should not be entered after + * the device has been unplugged. + */ +void drm_dev_exit(int idx) +{ + srcu_read_unlock(&drm_unplug_srcu, idx); +} +EXPORT_SYMBOL(drm_dev_exit); + +#endif /* HAVE_DRM_DEV_ENTER */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a3680a9030c43..fee37fd522eac 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 new file mode 100644 index 0000000000000..4ac5579c0f5c2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 +dnl # drm: Use srcu to protect drm_device.unplugged +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_ENTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ], [ + drm_dev_enter(NULL, NULL); + ], [drm_dev_enter], [drivers/gpu/drm/drm_drv.c], [ + AC_DEFINE(HAVE_DRM_DEV_ENTER, 1, [drm_dev_enter() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 new file mode 100644 index 0000000000000..4a05d157649e4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 +dnl # drm: Use srcu to protect drm_device.unplugged +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_IS_UNPLUGGED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #ifdef HAVE_DRM_DRM_DRV_H + #include + #endif + ], [ + drm_dev_is_unplugged(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DEV_IS_UNPLUGGED, 1, + [drm_dev_is_unplugged() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 385bb8188945a..8de8884b83ff0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -126,6 +126,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_DEV_ENTER + AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index d7a9bfaa2ae11..1bb8e2c0efaa4 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h new file mode 100644 index 0000000000000..b4e923bfa1465 --- /dev/null +++ b/include/kcl/kcl_drm_drv.h @@ -0,0 +1,66 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __KCL_KCL_DRM_DRV_H__ +#define __KCL_KCL_DRM_DRV_H__ + +#include +#include + +#ifndef HAVE_DRM_DEV_ENTER +/* Copied from include/drm/drm_drv.h*/ + +bool drm_dev_enter(struct drm_device *dev, int *idx); +void drm_dev_exit(int idx); + +#ifndef HAVE_DRM_DEV_IS_UNPLUGGED +/** + * drm_dev_is_unplugged - is a DRM device unplugged + * @dev: DRM device + * + * This function can be called to check whether a hotpluggable is unplugged. + * Unplugging itself is singalled through drm_dev_unplug(). If a device is + * unplugged, these two functions guarantee that any store before calling + * drm_dev_unplug() is visible to callers of this function after it completes + * + * WARNING: This function fundamentally races against drm_dev_unplug(). It is + * recommended that drivers instead use the underlying drm_dev_enter() and + * drm_dev_exit() function pairs. + */ +static inline bool drm_dev_is_unplugged(struct drm_device *dev) +{ + int idx; + + if (drm_dev_enter(dev, &idx)) { + drm_dev_exit(idx); + return false; + } + + return true; +} +#endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ +#endif /* HAVE_DRM_DEV_ENTER */ + +#endif From 18f6ddcd4a88b9341a4adbd323c663f5a494f99d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 13:52:05 +0800 Subject: [PATCH 0671/2070] drm/amdkcl: replace dma_resv_get_list with dma_resv_shared_list Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 5bb5b8b68e64e..bad215a62e54d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -164,7 +164,7 @@ void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fenc { struct dma_resv_list *old, *fobj = obj->staged; - old = dma_resv_get_list(obj); + old = dma_resv_shared_list(obj); obj->staged = NULL; if (!fobj) From 68d9052d918b661523fe731ee394b971ee733f36 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 17:29:29 +0800 Subject: [PATCH 0672/2070] drm/amdkcl: REWORKME: config.h Signed-off-by: Leslie Shi Change-Id: Id383189a33e53194d9b6f98879bf1e95a6987243 --- drivers/gpu/drm/amd/dkms/config/config.h | 43 +++++++++++++++++------- 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3e9eeb36639ee..4a34223864145 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -82,6 +82,9 @@ /* dma_buf dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ +/* dma_buf_unpin() is available */ +#define HAVE_DMA_BUF_UNPIN 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -207,6 +210,9 @@ /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 +/* struct drm_connector_state has hdr_output_metadata member */ +#define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 + /* drm_connector_unreference() is available */ /* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ @@ -246,6 +252,12 @@ /* drm_dev_dbg() is available */ #define HAVE_DRM_DEV_DBG 1 +/* drm_dev_enter() is available */ +#define HAVE_DRM_DEV_ENTER 1 + +/* drm_dev_is_unplugged() is availablea */ +#define HAVE_DRM_DEV_IS_UNPLUGGED 1 + /* drm_dev_put() is available */ #define HAVE_DRM_DEV_PUT 1 @@ -277,10 +289,10 @@ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 /* drm_dp_link_train_channel_eq_delay() has 2 args */ -/* #undef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS */ +#define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 /* drm_dp_link_train_clock_recovery_delay() has 2 args */ -/* #undef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS */ +#define HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS 1 /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 @@ -473,9 +485,6 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gem_prime_mmap() is available */ -/* #undef HAVE_DRM_GEM_PRIME_MMAP */ - /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 @@ -663,8 +672,8 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 -/* kmap_local_page_prot() is available */ -#define HAVE_KMAP_LOCAL_PAGE_PROT 1 +/* kmap_local_* is available */ +#define HAVE_KMAP_LOCAL 1 /* kref_read() function is available */ #define HAVE_KREF_READ 1 @@ -747,6 +756,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PGTABLE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_MM_H 1 @@ -852,11 +864,12 @@ /* remove_conflicting_framebuffers() returns int */ #define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 -/* request_firmware_direct() is available */ -#define HAVE_REQUEST_FIRMWARE_DIRECT 1 +/* remove_conflicting_pci_framebuffers() is available and doesn't have res_id + arg */ +#define HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG 1 -/* reservation_object->staged is available */ -/* #undef HAVE_RESERVATION_OBJECT_STAGED */ +/* remove_conflicting_pci_framebuffers() is available and has res_id arg */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG */ /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 @@ -882,6 +895,9 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 +/* struct dma_buf_ops->unpin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_UNPIN 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 @@ -938,7 +954,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -967,6 +983,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_remove_vgacon() is available */ +#define HAVE_VGA_REMOVE_VGACON 1 + /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ From a9708a7d3cd589d0e890fb3cf58387b978afeeb9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 10:25:27 +0800 Subject: [PATCH 0673/2070] drm/amdkcl: Test whether struct drm_device has pdev member This is caused by 5c0cd6459c5a "drm/amdkcl: init the ddev->pdev for legacy os" v5.13-2411-g5c0cd6459c5a Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-device-pdev.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4e0fb7e5100b1..44abd6f18c0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2472,7 +2472,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, goto err_free; #endif +#ifdef HAVE_DRM_DEVICE_PDEV ddev->pdev = pdev; +#endif pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a34223864145..5f7555027b12b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -249,6 +249,9 @@ /* drm_device->open_count is int */ /* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ +/* struct drm_device has pdev member */ +/* #undef HAVE_DRM_DEVICE_PDEV */ + /* drm_dev_dbg() is available */ #define HAVE_DRM_DEV_DBG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 new file mode 100644 index 0000000000000..25f5b1ca72eca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit b347e04452ff6382ace8fba9c81f5bcb63be17a6 +dnl # drm: Remove pdev field from struct drm_device +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + struct drm_device *pdd = NULL; + pdd->pdev = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_PDEV, 1, [struct drm_device has pdev member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8de8884b83ff0..5aab2bed2a5aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -128,6 +128,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED + AC_AMDGPU_DRM_DEVICE_PDEV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 08b06f51f2bd0e5b5615edc2364b146b0ee9bdb4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 10:43:19 +0800 Subject: [PATCH 0674/2070] drm/amdkcl: call dma_resv_init for legacy os This is caused by d02117f8efaa "drm/ttm: remove special handling for non GEM drivers" v5.12-rc3-374-gd02117f8efaa Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 9375e31f76d7e..8dcc6b2c55485 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -949,6 +949,11 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, amdkcl_ttm_resvp(bo) = resv; else amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); + +#ifndef HAVE_DRM_GEM_OBJECT_RESV + dma_resv_init(&amdkcl_ttm_resv(bo)); +#endif + atomic_inc(&ttm_glob.bo_count); /* From d762fe8273dc6103a03c36209e0d8db46335292d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 14:05:33 +0800 Subject: [PATCH 0675/2070] drm/amdkcl: wrap the code under macro PCI_IRQ_MSI Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 82bc6d657e5a0..35d3449fb1af4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -368,7 +368,11 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev) free_irq(adev->irq.irq, adev_to_drm(adev)); adev->irq.installed = false; if (adev->irq.msi_enabled) +#ifdef PCI_IRQ_MSI pci_free_irq_vectors(adev->pdev); +#else + pci_disable_msi(adev->pdev); +#endif } amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); From c131aa15158c90eb536986ab010835b64c79c394 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 14:08:04 +0800 Subject: [PATCH 0676/2070] drm/amdkcl: drop dma_resv rcu postfix This is caused by d3fae3b3daac "dma-buf: drop the _rcu postfix on function names v3" v5.13-rc3-854-gd3fae3b3daac Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 03dcd8b7fdc16..84710a8680e89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -960,7 +960,7 @@ int amdgpu_gem_prime_pin(struct drm_gem_object *obj) * Wait for all shared fences to complete before we switch to future * use of exclusive fence on this prime shared bo. */ - ret = dma_resv_wait_timeout_rcu(bo->tbo.resv, true, false, + ret = dma_resv_wait_timeout(bo->tbo.resv, true, false, MAX_SCHEDULE_TIMEOUT); if (unlikely(ret < 0)) { DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); From 98b9ae6e2edb641964d7cad6b600bc28c06a0ee6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 15:14:25 +0800 Subject: [PATCH 0677/2070] drm/amdkcl: add vma parameter for ttm_bo_vm_dummy_page() to adapt legacy os This is caused by 267d51d77fda "drm/ttm: Remap all page faults to per process dummy page." v5.13-rc1-231-g267d51d77fda Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 15 +++++++++++---- drivers/gpu/drm/ttm/ttm_bo_vm.c | 9 +++++++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 7173e73cea38a..7ae72b299de7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -115,9 +115,16 @@ amdgpu_gem_update_timeline_node(struct drm_file *filp, #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK void amdgpu_gem_object_free(struct drm_gem_object *gobj) #else + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) { - struct ttm_buffer_object *bo = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#endif + struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret; int idx; @@ -133,12 +140,12 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) goto unlock; } - ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT); + ret = ttm_bo_vm_fault_reserved(vmf, vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); drm_dev_exit(idx); } else { - ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); + ret = ttm_bo_vm_dummy_page(vmf, vma->vm_page_prot); } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index a3c28b76a1a43..3497d1a566557 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -314,9 +314,14 @@ static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res) __free_page(dummy_page); } +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, struct vm_area_struct *vma, pgprot_t prot) +{ +#else vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; vm_fault_t ret = VM_FAULT_NOPAGE; unsigned long address; @@ -377,7 +382,11 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) #endif drm_dev_exit(idx); } else { +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_dummy_page(vmf, vma, prot); +#else ret = ttm_bo_vm_dummy_page(vmf, prot); +#endif } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; From a693344424106fb1809efb2f7740882ff26ab2c1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 31 Aug 2021 11:52:31 +0800 Subject: [PATCH 0678/2070] drm/amdkcl: fake drm_gem_ttm_mmap function Signed-off-by: Leslie Shi --- .../include/kcl/kcl_drm_gem_ttm_helper.h | 10 +++++++++ .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 22 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index 10d002f55b191..e9d8d3fd9d9d8 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -34,4 +34,14 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); #endif +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma); +static inline +int drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { + return _kcl_drm_gem_ttm_mmap(gem, vma); +} +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 5acf8485888f7..b5fb22fa5a50a 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -38,3 +38,25 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, } EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); #endif + +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { + + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + int ret; + + ret = ttm_bo_mmap_obj(vma, bo); + if (ret < 0) + return ret; + + /* + * ttm has its own object refcounting, so drop gem reference + * to avoid double accounting counting. + */ + drm_gem_object_put(gem); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_mmap); +#endif From 721d519c8d2300fd278927089e7c43eca9059075 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Tue, 3 Aug 2021 14:44:31 -0400 Subject: [PATCH 0679/2070] drm/amdkfd: add parameter force in kfd_process_evict_queues It is to differenciate case scenario for proper behavior when calling evict queues, such as GPU reset doesn't need to roll back restoring partial evicted queues. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 ++++++------ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 18 ++++++++++-------- 6 files changed, 26 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 7dbeae47decba..3d4e78849f0e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -260,7 +260,7 @@ void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) if (adev->in_s0ix) kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); else - kgd2kfd_suspend(adev->kfd.dev, suspend_proc); + kgd2kfd_suspend(adev->kfd.dev, suspend_proc, true); } } @@ -281,7 +281,7 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) { if (adev->kfd.dev) - kgd2kfd_suspend_process(adev->kfd.dev); + kgd2kfd_suspend_process(adev->kfd.dev, true); } int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index e95014cf30784..f26cfc77c379f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -460,9 +460,9 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); bool kgd2kfd_device_init(struct kfd_dev *kfd, const struct kgd2kfd_shared_resources *gpu_resources); void kgd2kfd_device_exit(struct kfd_dev *kfd); -void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc); +void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force); int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc); -void kgd2kfd_suspend_process(struct kfd_dev *kfd); +void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force); int kgd2kfd_resume_process(struct kfd_dev *kfd); int kgd2kfd_pre_reset(struct kfd_dev *kfd, struct amdgpu_reset_context *reset_context); @@ -509,7 +509,7 @@ static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) { } -static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) +static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force) { } @@ -518,7 +518,7 @@ static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) return 0; } -static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd) +static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force) { } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index d162e65cdbf89..1ce0ce75ba786 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2694,7 +2694,7 @@ static int criu_restore(struct file *filep, * Set the process to evicted state to avoid running any new queues before all the memory * mappings are ready. */ - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_RESTORE); if (ret) goto exit_unlock; @@ -2813,7 +2813,7 @@ static int criu_process_info(struct file *filep, goto err_unlock; } - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); if (ret) goto err_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 7c92227129914..fc52e5bd1ca96 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1002,7 +1002,7 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd, kfd_smi_event_update_gpu_reset(node, false, reset_context); } - kgd2kfd_suspend(kfd, true); + kgd2kfd_suspend(kfd, true, true); for (i = 0; i < kfd->num_nodes; i++) kfd_signal_reset_event(kfd->nodes[i]); @@ -1070,7 +1070,7 @@ bool kfd_is_locked(struct kfd_dev *kfd) return false; } -void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) +void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force) { struct kfd_node *node; int i; @@ -1079,7 +1079,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) return; if (suspend_proc) - kgd2kfd_suspend_process(kfd); + kgd2kfd_suspend_process(kfd, force); for (i = 0; i < kfd->num_nodes; i++) { node = kfd->nodes[i]; @@ -1106,7 +1106,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) return ret; } -void kgd2kfd_suspend_process(struct kfd_dev *kfd) +void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force) { if (!kfd->init_complete) return; @@ -1114,7 +1114,7 @@ void kgd2kfd_suspend_process(struct kfd_dev *kfd) mutex_lock(&kfd_processes_mutex); /* For first KFD device suspend all the KFD processes */ if (++kfd_locked == 1) - kfd_suspend_all_processes(); + kfd_suspend_all_processes(force); mutex_unlock(&kfd_processes_mutex); } @@ -1203,7 +1203,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) return -ESRCH; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); - r = kfd_process_evict_queues(p, trigger); + r = kfd_process_evict_queues(p, true, trigger); kfd_unref_process(p); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index e0f5875f9eb03..24f75e3f31f8c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1137,9 +1137,9 @@ static inline struct kfd_process_device *kfd_process_device_from_gpuidx( } void kfd_unref_process(struct kfd_process *p); -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger); int kfd_process_restore_queues(struct kfd_process *p); -void kfd_suspend_all_processes(void); +void kfd_suspend_all_processes(bool force); int kfd_resume_all_processes(void); struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 75a2b15995077..c64881f8100b6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2112,9 +2112,9 @@ struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id) * Eviction is reference-counted per process-device. This means multiple * evictions from different sources can be nested safely. */ -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger) { - int r = 0; + int r = 0, r_tmp = 0; int i; unsigned int n_evicted = 0; @@ -2125,15 +2125,17 @@ int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) kfd_smi_event_queue_eviction(pdd->dev, p->lead_thread->pid, trigger); - r = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, + r_tmp = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, &pdd->qpd); /* evict return -EIO if HWS is hang or asic is resetting, in this case * we would like to set all the queues to be in evicted state to prevent * them been add back since they actually not be saved right now. */ - if (r && r != -EIO) { + if (r_tmp && r_tmp != -EIO) { dev_err(dev, "Failed to evict process queues\n"); - goto fail; + r = r_tmp; + if (!force) + goto fail; } n_evicted++; @@ -2337,7 +2339,7 @@ static void evict_process_worker(struct work_struct *work) p->last_evict_timestamp = get_jiffies_64(); pr_debug("Started evicting process pid %d\n", p->lead_thread->pid); - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { /* If another thread already signaled the eviction fence, * they are responsible stopping the queues and scheduling @@ -2420,7 +2422,7 @@ static void restore_process_worker(struct work_struct *work) } } -void kfd_suspend_all_processes(void) +void kfd_suspend_all_processes(bool force) { struct kfd_process *p; unsigned int temp; @@ -2428,7 +2430,7 @@ void kfd_suspend_all_processes(void) WARN(debug_evictions, "Evicting all processes"); hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { - if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) + if (kfd_process_evict_queues(p, force, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) pr_err("Failed to suspend process pid %d\n", p->lead_thread->pid); signal_eviction_fence(p); } From f4fa91107694902314b2af22854be644495c0ca2 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Tue, 3 Aug 2021 16:10:43 -0400 Subject: [PATCH 0680/2070] drm/amdgpu: Fix bad page address calculation on Aldebaran Fix normalized address to physical address calculation during page retirement, by using the channel index table instead of channel instance. While at it, do general cleanup, use macros instead of function to fetch UMC instance and channel instance from MCA registers. Signed-off-by: Mukul Joshi Reviewed-by: John Clements --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d9f4ae071e1d9..e4de7d4d32d2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -133,11 +133,6 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define BYPASS_INITIALIZATION_ADDRESS 0x1 #ifdef HAVE_SMCA_UMC_V2 -#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) -#define GET_UMC_INST_NIBBLE(m) (((m) >> 20) & 0xF) -#define GET_CHAN_INDEX_NIBBLE(m) (((m) >> 12) & 0xF) -#define GPU_ID_OFFSET 8 - static bool notifier_registered = false; static void amdgpu_register_bad_pages_mca_notifier(void); #endif From f7cbaa0fe8b018838194db4bff329547c97443fe Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 4 Aug 2021 16:38:11 -0500 Subject: [PATCH 0681/2070] drm/amdkcl: Fix the macro for HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER The code body that is used to determine if compile time macro HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER should be enabled or not is incorrect. It references the wrong structure. The correct struct to reference is dma_buf_attach_ops not dma_buf_ops Signed-off-by: Ramesh Errabolu Reviewed-by: Flora Cui Change-Id: I735de6e7aa30ee86159b67846fa5b4de056375a8 --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5f7555027b12b..ba08fce502a5f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -893,7 +893,7 @@ #define HAVE_STRSCPY 1 /* struct dma_buf_ops->allow_peer2peer is available */ -/* #undef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER */ +#define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index 3f408896f437b..e402bf57f2ec6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -7,12 +7,12 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - struct dma_buf_ops *ptr = NULL; + struct dma_buf_attach_ops *ptr = NULL; ptr->allow_peer2peer = false; ],[ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, 1, - [struct dma_buf_ops->allow_peer2peer is available]) + [struct dma_buf_attach_ops->allow_peer2peer is available]) ],[ dnl # dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided From 23eac949e2918347aea1714bc5f0282d2f4f8f0a Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 12 Aug 2021 12:17:30 -0400 Subject: [PATCH 0682/2070] drm/amdkcl: Add XEC macro v2 v2: Change header from kcl_xec.h to kcl_mce.h Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_mce.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_mce.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index fee37fd522eac..26cbd71386a4a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -68,6 +68,7 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" +#include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h new file mode 100644 index 0000000000000..037fb0c1b3e37 --- /dev/null +++ b/include/kcl/kcl_mce.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MCE_H +#define AMDKCL_MCE_H + +#include +/* Copied from asm/mce.h */ +#ifndef XEC +#define XEC(x, mask) (((x) >> 16) & mask) +#endif + +#endif From 8ffcbb02260ec6695007784b40f089a5b29f69cf Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Thu, 12 Aug 2021 20:09:20 -0500 Subject: [PATCH 0683/2070] Use DMABUF for remote VRAM BOs only if CONFIG_PCI_P2PDMA is SET Without CONFIG_PCI_P2PDMA, pci_p2pdma_distance_many will always fail. This will cause DMABUF implementation to migrate VRAM BOs to GTT domain. Therefore, use DMABuf for remote VRAM mappings only if CONFIG_PCI_P2PDMA is enabled. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 99ad1cec3657a..caa1a925d7943 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -877,7 +877,7 @@ static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, { int ret = 0; -#ifdef CONFIG_DMABUF_MOVE_NOTIFY +#if defined(CONFIG_DMABUF_MOVE_NOTIFY) && defined(CONFIG_PCI_P2PDMA) attachment->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, bo); pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); From 18daba3806dde8d327c7526abc7913fdbc026f4d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 16 Aug 2021 17:04:36 +0800 Subject: [PATCH 0684/2070] drm/amdkcl: add DMA_FENCE_FLAG_USER_BITS macro This is caused by de7515d43659f852590645a688f8d493e4a18141 "drm/amd/amdgpu embed hw_fence into amdgpu_job" v5.13-2021-gde7515d43659 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- include/kcl/kcl_fence.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 947efbf7e38aa..88a2d1a425ec2 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -27,6 +27,7 @@ #define DMA_FENCE_TRACE FENCE_TRACE #define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT #define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT +#define DMA_FENCE_FLAG_USER_BITS FENCE_FLAG_USER_BITS #define dma_fence_wait fence_wait #define dma_fence_get fence_get #define dma_fence_put fence_put From 23987a64457cb4daca9ff60890a62b4fdce12460 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Sep 2021 18:52:10 +0800 Subject: [PATCH 0685/2070] drm/amdkcl: add macro INTEL_FAM6_ROCKETLAKE It's caused by 857d1b24aa8d97a7e1cb50ed3b02773a159a8c4d "drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform" v5.13-2160-g857d1b24aa8d Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_intel_family.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/kcl/kcl_intel_family.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 26cbd71386a4a..baa606ea02d12 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -70,5 +70,6 @@ #include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h new file mode 100644 index 0000000000000..20781af676d6b --- /dev/null +++ b/include/kcl/kcl_intel_family.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_INTEL_FAMILY_H +#define AMDKCL_INTEL_FAMILY_H + +#include +/* Copied froma asm/intel-family.h*/ +#ifndef INTEL_FAM6_ROCKETLAKE +#define INTEL_FAM6_ROCKETLAKE 0xA7 +#endif + +#endif + From c752c4f950f05af5b784d4fa619e449e87cf0748 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Sep 2021 10:50:25 +0800 Subject: [PATCH 0686/2070] drm/amdkcl: Avoid array out of bounds This is caused by bb892cd603b7 "drm/amdgpu: [hybrid] add direct gma(dgma) support" v5.13-2077-gbb892cd603b7 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3f56584d17241..2f65cba0064a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2198,6 +2198,7 @@ static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_si spin_lock_init(&mgr->lock); atomic64_set(&mgr->available, p_size); + BUG_ON(AMDGPU_PL_DGMA_IMPORT >= TTM_NUM_MEM_TYPES); ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); ttm_resource_manager_set_used(man, true); return 0; From a8295828cc112f138f60204f9defb9b37f7e5236 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 14 Sep 2021 10:20:43 +0800 Subject: [PATCH 0687/2070] drm/amdkcl: retain explicit creation and destruction of sysfs attributes for legacy os It's caused by 35bba8313b95a5cd074fc910a9c2670b4a1b105d "drm/amdgpu: Convert driver sysfs attributes to static attributes" v5.13-rc1-237-g35bba8313b95 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Change-Id: Id4d05534e1329859546cc642d0ee1536e47114b0 --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 16 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 23 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 18 +++++++++++++++ .../drm/amd/dkms/m4/pci-driver-dev-groups.m4 | 8 +++---- 5 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 763f2b8dcf13a..0ab3f4e9bfe8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1830,6 +1830,7 @@ static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vbios_version_attrs[] = { &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL }; @@ -1853,6 +1854,7 @@ const struct attribute_group amdgpu_vbios_version_attr_group = { .attrs = amdgpu_vbios_version_attrs, .is_visible = amdgpu_vbios_version_attrs_is_visible, }; +#endif int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) { @@ -1882,6 +1884,9 @@ void amdgpu_atombios_fini(struct amdgpu_device *adev) adev->mode_info.atom_context = NULL; kfree(adev->mode_info.atom_card_info); adev->mode_info.atom_card_info = NULL; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_vbios_version); +#endif } /** @@ -1898,6 +1903,9 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) { struct card_info *atom_card_info = kzalloc(sizeof(struct card_info), GFP_KERNEL); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif if (!atom_card_info) return -ENOMEM; @@ -1929,6 +1937,14 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) amdgpu_atombios_allocate_fb_scratch(adev); } +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_vbios_version); + if (ret) { + DRM_ERROR("Failed to create device file for VBIOS version\n"); + return ret; + } +#endif + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 44abd6f18c0f3..cf57fe76034dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3245,12 +3245,14 @@ static struct pci_error_handlers amdgpu_pci_err_handler = { .resume = amdgpu_pci_resume, }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static const struct attribute_group *amdgpu_sysfs_groups[] = { &amdgpu_vram_mgr_attr_group, &amdgpu_gtt_mgr_attr_group, &amdgpu_flash_attr_group, NULL, }; +#endif static struct pci_driver amdgpu_kms_pci_driver = { .name = DRIVER_NAME, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 9b0bcf6aca445..34a103289f5de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -78,6 +78,7 @@ static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO, static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO, amdgpu_mem_info_gtt_used_show, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_gtt_mgr_attributes[] = { &dev_attr_mem_info_gtt_total.attr, &dev_attr_mem_info_gtt_used.attr, @@ -87,6 +88,7 @@ static struct attribute *amdgpu_gtt_mgr_attributes[] = { const struct attribute_group amdgpu_gtt_mgr_attr_group = { .attrs = amdgpu_gtt_mgr_attributes }; +#endif /** * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space @@ -324,6 +326,9 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) { struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; struct ttm_resource_manager *man = &mgr->manager; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif man->use_tt = true; man->func = &amdgpu_gtt_mgr_func; @@ -333,6 +338,19 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) drm_mm_init(&mgr->mm, 0, adev->gmc.gart_size >> PAGE_SHIFT); spin_lock_init(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_total\n"); + return ret; + } + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_used); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_used\n"); + return ret; + } +#endif + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); ttm_resource_manager_set_used(man, true); return 0; @@ -361,7 +379,10 @@ void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev) spin_lock(&mgr->lock); drm_mm_takedown(&mgr->mm); spin_unlock(&mgr->lock); - +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total); + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 9d934c07fa6b8..2ad7009578190 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -214,7 +214,11 @@ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO, static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO, amdgpu_mem_info_vram_vendor, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vram_mgr_attributes[] = { +#else +static const struct attribute *amdgpu_vram_mgr_attributes[] = { +#endif &dev_attr_mem_info_vram_total.attr, &dev_attr_mem_info_vis_vram_total.attr, &dev_attr_mem_info_vram_used.attr, @@ -223,6 +227,7 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = { NULL }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int i) { @@ -244,6 +249,7 @@ const struct attribute_group amdgpu_vram_mgr_attr_group = { .attrs = amdgpu_vram_mgr_attributes, .is_visible = amdgpu_vram_attrs_is_visible }; +#endif /** * amdgpu_vram_mgr_vis_size - Calculate visible block size @@ -916,6 +922,9 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; struct ttm_resource_manager *man = &mgr->manager; int err; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size); if (IS_ERR(man->cg)) @@ -928,6 +937,12 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) INIT_LIST_HEAD(&mgr->reserved_pages); INIT_LIST_HEAD(&mgr->allocated_vres_list); mgr->default_page_size = PAGE_SIZE; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + /* Add the two VRAM-related sysfs files */ + ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); + if (ret) + DRM_ERROR("Failed to register sysfs\n"); +#endif man->func = &amdgpu_vram_mgr_func; err = drm_buddy_init(&mgr->mm, man->size, PAGE_SIZE); @@ -972,6 +987,9 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) drm_buddy_fini(&mgr->mm); mutex_unlock(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + sysfs_remove_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL); } diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 index 7a673c73d6b1c..dfb7bd92cade1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -4,12 +4,12 @@ dnl # PCI: Add support for dev_groups to struct pci_driver dnl # AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_driver pd; - pd.dev_groups = NULL; - ], [], [], [ + struct pci_driver *pd = NULL; + pd->dev_groups = NULL; + ], [ AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) ]) ]) From 070c2a54223b91218cf63fdfadd302d646387441 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 10:22:22 +0800 Subject: [PATCH 0688/2070] drm/amdkcl: update config.h Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ba08fce502a5f..73f61f0409ec3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -/* #undef HAVE_ACPI_PUT_TABLE */ +#define HAVE_ACPI_PUT_TABLE 1 /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 @@ -35,7 +35,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ +#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -71,7 +71,7 @@ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ /* dev_pagemap->owner is available */ -#define HAVE_DEV_PAGEMAP_OWNER 1 +/* #undef HAVE_DEV_PAGEMAP_OWNER */ /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -176,10 +176,10 @@ #define HAVE_DRM_COLOR_LUT_SIZE 1 /* drm_connector_atomic_hdr_metadata_equal() is available */ -/* #undef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL */ +#define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 /* drm_connector_attach_hdr_output_metadata_property() is available */ -/* #undef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY */ +#define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -258,7 +258,7 @@ /* drm_dev_enter() is available */ #define HAVE_DRM_DEV_ENTER 1 -/* drm_dev_is_unplugged() is availablea */ +/* drm_dev_is_unplugged() is available */ #define HAVE_DRM_DEV_IS_UNPLUGGED 1 /* drm_dev_put() is available */ @@ -660,6 +660,9 @@ /* io_mapping_map_local_wc() is available */ #define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 +/* io_mapping_map_wc() has size argument */ +#define HAVE_IO_MAPPING_MAP_WC_HAS_SIZE_ARG 1 + /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 @@ -790,7 +793,7 @@ #define HAVE_MEM_ENCRYPT_ACTIVE 1 /* migrate_vma->pgmap_owner is available */ -#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 +/* #undef HAVE_MIGRATE_VMA_PGMAP_OWNER */ /* mmgrab() is available */ #define HAVE_MMGRAB 1 @@ -957,7 +960,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -1022,6 +1025,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* is_device_page is available */ +/* #undef HAVE_ZONE_DEVICE_PUBLIC */ + /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 From a0fa4c38af316c639921eafa301d543ddb4a3446 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 10:20:41 +0800 Subject: [PATCH 0689/2070] drm/amdkcl: fix test for is_cow_mapping Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 index c0bf84f081f2a..116779b2674f0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -1,10 +1,10 @@ dnl # -dnl # commit 97a7e4733b9b221d012ae68fcd3b3251febf6341 +dnl # commit v5.12-rc2-346-g97a7e4733b9b dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow dnl # AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ], [ is_cow_mapping(VM_SHARED); From bcc6a703bf64b7571837abe2441cbec9200567d5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 15:59:24 +0800 Subject: [PATCH 0690/2070] drm/amdkcl: fix test for drm_plane_helper_funcs->atomic_check() Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 73f61f0409ec3..3e90ee3b7a36d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -960,7 +960,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 3f28dbaae58fe..c5e0918674904 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -6,7 +6,7 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_ #include ], [ struct drm_plane_helper_funcs *funcs = NULL; - funcs->atomic_check((struct drm_crtc *)NULL, (struct drm_atomic_state *)NULL); + funcs->atomic_check(NULL, (struct drm_atomic_state *)NULL); ], [ AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) From aa51004ec95d0417f489da08fd8a96884c02fa9a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 10 Sep 2021 11:44:49 +0800 Subject: [PATCH 0691/2070] drm/amdkcl: fake a dummy mmput_async v2: fix the missing ; HAVE_MMPUT_ASYNC must be defined for monolithic build Signed-off-by: Flora Cui Reviewed-and-tested-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 12 ++++++++++++ include/kcl/backport/kcl_mm_backport.h | 4 ++++ include/kcl/kcl_mm.h | 4 ++++ 6 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index e60ac00cba573..9d7534002b7e1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -6,6 +6,19 @@ */ #include +#ifndef HAVE_MMPUT_ASYNC +void (*_kcl_mmput_async)(struct mm_struct *mm); +EXPORT_SYMBOL(_kcl_mmput_async); + +void __kcl_mmput_async(struct mm_struct *mm) +{ + pr_warn_once("This kernel version not support API: mmput_async !\n"); +} +#endif + void amdkcl_mm_init(void) { +#ifndef HAVE_MMPUT_ASYNC + _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3e90ee3b7a36d..6a921f616f3c9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -798,6 +798,9 @@ /* mmgrab() is available */ #define HAVE_MMGRAB 1 +/* mmput_async() is available */ +#define HAVE_MMPUT_ASYNC 1 + /* mmu_notifier_call_srcu() is available */ /* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5aab2bed2a5aa..2439d0a15c444 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -108,6 +108,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_STRUCT_XARRAY + AC_AMDGPU_MMPUT_ASYNC AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 new file mode 100644 index 0000000000000..2c8863597781f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v4.14-rc3-117-ga1b2289cef92 android: binder: drop lru lock in isolate callback +dnl # v4.13-4372-g212925802454 mm: oom: let oom_reap_task and exit_mmap run concurrently +dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from the oom reaper context +dnl # +AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([mmput_async], [kernel/fork.c], [ + AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 3fc317a922a8d..48312d64e5869 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -5,6 +5,10 @@ #include #include +#ifndef HAVE_MMPUT_ASYNC +#define mmput_async _kcl_mmput_async +#endif + #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 856be87fc0043..ec9c971d7950e 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -22,6 +22,10 @@ #define untagged_addr(addr) (addr) #endif +#ifndef HAVE_MMPUT_ASYNC +extern void (*_kcl_mmput_async)(struct mm_struct *mm); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From cdb62763433957d35a07aaab56e3cfde358353da Mon Sep 17 00:00:00 2001 From: Jingwen Chen Date: Tue, 7 Sep 2021 11:12:06 +0800 Subject: [PATCH 0692/2070] drm/amd/amdgpu: use ordered workqueue for tdr in SRIOV [Why] When two job timedout happens during a very close time, the job bailing will happen. As drm scheduler will delete the bad job from pending list when entering the tdr and add it back when calling drm_sched_stop during tdr handling, the bailing job will be deleted from pending list but it will directly return before calling drm_sched_stop as the first job has already sets the in_gpu_reset. So this bailing job will not be added back ever. And this can lead to this job never be finished. [How] 1. Use an ordered_workqueue as the timeout_wq for all tdr. As there will only be one tdr work at the same time, the bailing will never happen. 2. Use mdelay in sriov flr work to make sure the polling flr won't exceeds the default ring timeout. v2: Add detailed description. Use gpu_recovery=2 for SRIOV v3: split recovery mode and mdelay into seperate patch Based on: https://patchwork.freedesktop.org/patch/msgid/20210630062751.2832545-3-boris.brezillon@collabora.com Signed-off-by: Jingwen Chen Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b19372bcca01c..49c2b74c6ccc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1031,6 +1031,7 @@ struct amdgpu_device { bool ib_pool_ready; struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; + struct workqueue_struct *timeout_wq; /* interrupts */ struct amdgpu_irq irq; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a25694f4e9ce5..537ba57d208f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4716,6 +4716,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* init the mode config */ drm_mode_config_init(adev_to_drm(adev)); + if (amdgpu_sriov_vf(adev)) { + adev->timeout_wq = alloc_ordered_workqueue("amdgpu_ring_timeout_wq", 0); + if (!adev->timeout_wq) + dev_warn(adev->dev, "alloc_ordered_workqueue failed\n"); + } + r = amdgpu_device_ip_init(adev); if (r) { dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); From 8c96c74dc2276b33a3c2272d71c5726e21ec0ce6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:48:10 +0800 Subject: [PATCH 0693/2070] drm/amdkcl: Resolve target kernel 4.14 amdgpu_dm build issue invalid operands to binary - (have 'struct timeval' and 'ktime_t' {aka long long int}') frame_duration = vblank->time - previous_timestamp; incompatible type for argument 2 of 'atomic64_set' atomic64_set(irq_params->previous_timestamp, vblank->time) v2: create separated KCL macro for vblank field time of type ktime_t or timeval v3: fix typo in new m4 configuration v4: use initialized variable in m4 configuration file Signed-off-by: Nikola Prica Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: I539392044b24600278315f09323974dc0ef36ba7 Signed-off-by: Asher Song --- .../gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h | 11 +++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 10 ++-------- .../dkms/m4/drm_vblank_use_ktime_t_time_field.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 38 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 30313214c72d2..29f666e6c2bcc 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -44,4 +44,15 @@ static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, u } #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ +#if defined(HAVE_DRM_VBLANK_USE_KTIME_T) +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { + return vblank->time; +} +#else +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { + return timeval_to_ns(&vblank->time); +} +#endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ + + #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a2982f5017105..de9709320487a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -576,6 +576,12 @@ static void schedule_dc_vmin_vmax(struct amdgpu_device *adev, queue_work(system_wq, &offload_work->work); } +#ifndef HAVE_KTIME_IS_UNION +static inline ktime_t get_drm_vblank_crtc_time(struct drm_vblank_crtc *vblank) +{ + return kcl_amdgpu_get_vblank_time_ns(vblank); +} +#endif static void dm_vupdate_high_irq(void *interrupt_params) { @@ -598,13 +604,14 @@ static void dm_vupdate_high_irq(void *interrupt_params) drm_dev = acrtc->base.dev; vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); - frame_duration_ns = vblank->time - previous_timestamp; + frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; if (frame_duration_ns > 0) { trace_amdgpu_refresh_rate_track(acrtc->base.index, frame_duration_ns, ktime_divns(NSEC_PER_SEC, frame_duration_ns)); - atomic64_set(&irq_params->previous_timestamp, vblank->time); + atomic64_set(&irq_params->previous_timestamp, + get_drm_vblank_crtc_time(vblank)); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6a921f616f3c9..dfa30159548dd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -339,14 +339,8 @@ /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ -/* drm_driver->get_scanout_position() return bool */ -/* #undef HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL */ - -/* drm_driver->get_vblank_timestamp() return bool */ -/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL */ - -/* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ -/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ +/* drm_vblank struct use ktime_t for time field */ +#define HAVE_DRM_VBLANK_USE_KTIME_T 1 /* drm_driver->release() is available */ #define HAVE_DRM_DRIVER_RELEASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 new file mode 100644 index 0000000000000..1107aa2219eca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vblank_crtc *vblank = NULL; + vblank->time = 0; + ], [ + AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, + [drm_vblank->time uses ktime_t type]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2439d0a15c444..a445db487666e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -130,6 +130,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV + AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 871d513af69e823379567a84695985ecd5e1a233 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Sat, 9 Oct 2021 15:21:18 +0800 Subject: [PATCH 0694/2070] drm/amdkcl: adapt code of ktime_t api for legacy os Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h | 4 +++- .../drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 | 9 +++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 29f666e6c2bcc..a799268fb1754 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -50,7 +50,9 @@ static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vbla } #else static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { - return timeval_to_ns(&vblank->time); + struct timeval tv; + drm_crtc_vblank_count_and_time(vblank, &tv); + return timeval_to_ktime(tv); } #endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 index 1107aa2219eca..b846cb2f57a41 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 @@ -1,12 +1,17 @@ dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval +dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #else #include + #endif + #include ], [ struct drm_vblank_crtc *vblank = NULL; - vblank->time = 0; + vblank->time = ns_to_ktime(0); ], [ AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, [drm_vblank->time uses ktime_t type]) From f052dd90ec37c92835cb19263c2fc7edb3d6ffa7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Oct 2021 14:50:16 +0800 Subject: [PATCH 0695/2070] drm/amdkcl: fix dependency for HSA_AMD_SVM Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b1eecc92ebfb3..ef8bfe38400f5 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -159,9 +159,11 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) +ifdef CONFIG_DEVICE_PRIVATE export CONFIG_HSA_AMD_SVM=y subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif +endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP From 9ff1f996419b1bc9170b103d81901be1bac477e7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Oct 2021 14:49:42 +0800 Subject: [PATCH 0696/2070] drm/amdkcl: fix mmu_notifier_range_blockable on rhel8.5 Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- include/kcl/kcl_mmu_notifier.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/kcl/kcl_mmu_notifier.h b/include/kcl/kcl_mmu_notifier.h index 1af9433bdbfe5..eb18197778b02 100644 --- a/include/kcl/kcl_mmu_notifier.h +++ b/include/kcl/kcl_mmu_notifier.h @@ -4,16 +4,25 @@ #include -#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) && \ - defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) /* Copied from v5.1-10225-g4a83bfe916f3 include/linux/mmu_notifier.h */ -#ifdef CONFIG_MMU_NOTIFIER +#if defined(CONFIG_MMU_NOTIFIER) && \ + defined(HAVE_2ARGS_INVALIDATE_RANGE_START) static inline bool mmu_notifier_range_blockable(const struct mmu_notifier_range *range) { +/* + * It's for rhel8.5 which has the latest struct mmu_notifier_range + * and no mmu_notifier_range_blockable + */ +#ifdef MMU_NOTIFIER_RANGE_BLOCKABLE + return (range->flags & MMU_NOTIFIER_RANGE_BLOCKABLE); +#else return range->blockable; +#endif } #else +struct mmu_notifier_range; static inline bool mmu_notifier_range_blockable(const struct mmu_notifier_range *range) { From c7ba195ea4c861f1d41d5fe0e8d90c35137c2cf8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Oct 2021 19:12:08 +0800 Subject: [PATCH 0697/2070] drm/amdkcl: fake drm_connector_set_panel_orientation_with_quirk() It's caused by 01265b703af5e7cd99545319bc88aba22ab7b95f "amd/display: enable panel orientation quirks" v5.13-2450-g01265b703af5 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 11 +++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ ...connector-set-panel-orientation-with-quirk.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 16 ++++++++++++++++ 5 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index 79c907264d709..a4a4e8d2e9acf 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -78,3 +78,14 @@ int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn } EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); #endif + +#if !defined(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK) +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return drm_connector_init_panel_orientation_property(connector, width, height); +} +EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dfa30159548dd..7424837367348 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -207,6 +207,9 @@ /* connector reference counting is available */ #define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 +/* drm_connector_set_panel_orientation_with_quirk() is available */ +#define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 + /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 new file mode 100644 index 0000000000000..463767cb7e3a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v5.5-rc2-1360-g69654c632d80 +dnl # drm/connector: Split out orientation quirk detection (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_set_panel_orientation_with_quirk], + [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, + [drm_connector_set_panel_orientation_with_quirk() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a445db487666e..470d9e108f4e1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -131,6 +131,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_VBLANK_USE_KTIME_T + AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 02b2633b0c66f..f14a5f2790201 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -92,4 +92,20 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); #endif +#ifndef HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height); + +static inline +int drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return _kcl_drm_connector_set_panel_orientation_with_quirk(connector, panel_orientation, width, height); +} +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From a87f239b676ceca3541c1813d5dd31424343ab83 Mon Sep 17 00:00:00 2001 From: Marko Zekovic Date: Mon, 11 Oct 2021 15:03:35 +0200 Subject: [PATCH 0698/2070] drm/amdkcl: fix issue with dirver unloading Fix issue with driver unloading on kernel 5.4. Backported from 5.11 version of driver. Signed-off-by: Marko Zekovic Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index cf57fe76034dc..85c521ec8c0dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2602,6 +2602,9 @@ amdgpu_pci_remove(struct pci_dev *pdev) kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC + amdkcl_drm_dev_release(dev); +#endif } #ifndef HAVE_DRM_DRM_MANAGED_H From 9c37853dca198837a2b0d1ccede8b2ae4cbff7bc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 15 Oct 2021 16:13:34 +0800 Subject: [PATCH 0699/2070] drm/amdkcl: add arguments of function amdgpu_ttm_tt_affect_userptr() It's caused by 2d3ad5529663465fd1443f9cf8230ec2bba2cd77 "drm/amdkfd: unregistered svm range not overlap with TTM range" v5.13-2731-g2d3ad5529663 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 9 ++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index a55a9ef8726d4..a1ecaa032272d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -258,10 +258,11 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, { struct amdgpu_bo *bo; long r; + unsigned long userptr; list_for_each_entry(bo, &node->bos, mn_list) { - if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end, &userptr)) continue; r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), @@ -330,6 +331,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); struct interval_tree_node *it; unsigned long end; + unsigned long userptr; /* notification is exclusive, but interval is inclusive */ end = range->end - 1; @@ -350,7 +352,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, range->start, - end)) + end, &userptr)) amdgpu_amdkfd_evict_userptr(mem, range->mm); } } @@ -440,6 +442,7 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); struct interval_tree_node *it; + unsigned long userptr; /* notification is exclusive, but interval is inclusive */ end -= 1; @@ -463,7 +466,7 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct kgd_mem *mem = bo->kfd_bo; if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, - start, end)) + start, end, &userptr)) amdgpu_amdkfd_evict_userptr(mem, mm); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 2f65cba0064a1..ac560f3567a53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1621,7 +1621,7 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) * */ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, - unsigned long end) + unsigned long end, unsigned long *userptr) { struct amdgpu_ttm_tt *gtt = (void *)ttm; struct amdgpu_ttm_gup_task_list *entry; @@ -1651,6 +1651,9 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, atomic_inc(>t->mmu_invalidations); + if (userptr) + *userptr = gtt->userptr; + return true; } From 9417118c149bae107bda7254d1c80a77fd0d05d0 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 22 Oct 2021 12:08:37 -0400 Subject: [PATCH 0700/2070] drm/amdkcl: Set PAGEMAP_OWNER for in-tree build PAGEMAP_OWNER should be defined in config.h for in-tree build on 5.13 kernel. This fixes "failed to register HMM device memory" error when loading amdgpu driver where a 5.13 monolithic kernel is used. Signed-off-by: Amber Lin Reviewed-by: Philip Yang Change-Id: I5a09a4ec30649c202096fa1f95248ad802e9fdd7 --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7424837367348..30f8c501eca31 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -71,7 +71,7 @@ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ /* dev_pagemap->owner is available */ -/* #undef HAVE_DEV_PAGEMAP_OWNER */ +#define HAVE_DEV_PAGEMAP_OWNER 1 /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -790,7 +790,7 @@ #define HAVE_MEM_ENCRYPT_ACTIVE 1 /* migrate_vma->pgmap_owner is available */ -/* #undef HAVE_MIGRATE_VMA_PGMAP_OWNER */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 /* mmgrab() is available */ #define HAVE_MMGRAB 1 From b321f1841c64bd2c76021928bc1c6461e862ed95 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Oct 2021 17:00:24 +0800 Subject: [PATCH 0701/2070] drm/amdkcl: add forward declaration of task_struct v5.12-rc3-304-gf7b21a0e4117 fixes a build error when linux/fb.h is used outside of the kernel tree. This patch adds forward declaration of task_struct to adapt legacy os. Reviewed-by: Flora Cui --- .../m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 | 1 + .../gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 index ec30c7ffa874c..ee6e915098f5c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ dnl # video/fb: Propagate error code from failing to unregister conflicting fb dnl # AC_KERNEL_TRY_COMPILE_SYMBOL([ + struct task_struct; #include ], [ int ret = remove_conflicting_framebuffers(NULL, NULL, false); diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 index 06241044fe4d4..bde011042303f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ],[ remove_conflicting_pci_framebuffers(NULL, NULL); @@ -13,6 +14,7 @@ AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) ],[ AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ], [ remove_conflicting_pci_framebuffers(NULL, 0, NULL); From 5b6a20d369a216ae6e7485a01188a4e5addc1159 Mon Sep 17 00:00:00 2001 From: Jingwen Chen Date: Fri, 29 Oct 2021 18:04:05 +0800 Subject: [PATCH 0702/2070] drm/amdkcl: fix minor index not removed after unload driver [Why] In kernel 5.4, current driver will not remove minor->index from drm_minors_idr during unload driver. Which will lead to minor index increase after reload amdgpu. [How] As there's no drm_managed.h to call drm_minor_alloc_release when release dev, add drm_dev_fini to amdgpu_driver_release_kms Signed-off-by: Jingwen Chen Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 27632f9a1e40f..b788a5ae51bc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1652,6 +1652,10 @@ void amdgpu_driver_release_kms(struct drm_device *dev) amdgpu_device_fini_sw(adev); pci_set_drvdata(adev->pdev, NULL); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(dev); + kfree(adev); +#endif } /* From b7d936861d8f89979e91de9d47e97874e1be326c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 2 Nov 2021 10:07:22 +0800 Subject: [PATCH 0703/2070] drm/amdkcl: Fix DKMS makefile include path filter As of Ubuntu 20.04.4, the given paths from LINUXINCLUDE variable would be filtered incorrectly as each token is considered a word and done independently. This would lead to the case where two '-include' switches would appear in sequence causing later switches to be parsed incorrectly. When the kconfig file is filtered out, it should be filtered out together with the preceding '-include', so adding quotes fixes this. v1: add quotes to filter out the specific string v2: handle the extra space with "-I " Signed-off-by: George Cave Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ef8bfe38400f5..b9f423b84ddaf 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -124,9 +124,10 @@ endif export OS_NAME OS_VERSION +_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ - $(filter-out -I%/uapi -include %/kconfig.h,$(LINUXINCLUDE)) -USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(LINUXINCLUDE)) + $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) LINUXINCLUDE := \ -I$(src)/include \ From be20d3da6b52c86abf379c5f195fa6ff8718bfa7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 3 Nov 2021 11:54:40 +0800 Subject: [PATCH 0704/2070] drm/amdkcl: fake drm_simple_encoder_init It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../amd/amdkcl/kcl_drm_simple_kms_helper.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 12 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_simple_kms_helper.h | 22 +++++++++++++++++ 7 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 create mode 100644 include/kcl/kcl_drm_simple_kms_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ef4f57f9cfeeb..085c8a47f19c9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o - kcl_drm_drv.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c new file mode 100644 index 0000000000000..7a44428ce88e2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_simple_kms_helper.c and modified for KCL */ +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +static const struct drm_encoder_funcs drm_simple_encoder_funcs_cleanup = { + .destroy = drm_encoder_cleanup, +}; + +int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return drm_encoder_init(dev, encoder, + &drm_simple_encoder_funcs_cleanup, + encoder_type, NULL); +} +EXPORT_SYMBOL(_kcl_drm_simple_encoder_init); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index baa606ea02d12..344b372447d6d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -71,5 +71,6 @@ #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 30f8c501eca31..65d6c0f60c79e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -570,6 +570,9 @@ /* drm_printer->prefix is available */ #define HAVE_DRM_PRINTER_PREFIX 1 +/* drm_simple_encoder is available */ +#define HAVE_DRM_SIMPLE_ENCODER_INIT 1 + /* drm_syncobj_fence_get() is available */ /* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 new file mode 100644 index 0000000000000..0ffcd218e5a99 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v5.6-rc2-359-g63170ac6f2e8 +dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_simple_encoder_init], + [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 470d9e108f4e1..d553ca218fe00 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -132,6 +132,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK + AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_simple_kms_helper.h b/include/kcl/kcl_drm_simple_kms_helper.h new file mode 100644 index 0000000000000..51a6699486da0 --- /dev/null +++ b/include/kcl/kcl_drm_simple_kms_helper.h @@ -0,0 +1,22 @@ +/*SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include +#include +#include +#include + +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +extern int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type); +static inline +int drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return _kcl_drm_simple_encoder_init(dev,encoder,encoder_type); +} +#endif From 05a497734aca5928231f7300ec859643571f8a91 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Nov 2021 12:27:34 +0800 Subject: [PATCH 0705/2070] drm/amdkcl: convert ktime_t to adapt legacy os It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 4c4849b793905..8045f8afc3e3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -102,9 +102,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - if (WARN_ON(*vblank_time == vblank->time)) + if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; - /* * To prevent races we roll the hrtimer forward before we do any * interrupt processing - this is how real hw works (the interrupt is @@ -112,8 +111,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, * the vblank core expects. Therefore we need to always correct the * timestampe by one frame. */ - *vblank_time -= output->period_ns; + *vblank_time = ktime_sub(*vblank_time, output->period_ns); return true; } From 68d51249c6fcd416675c321ef10736467f6e54f9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 20 Aug 2021 18:58:21 +0800 Subject: [PATCH 0706/2070] drm/amdkcl: wrap the code under macro HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 8045f8afc3e3a..5af32c6d1fe9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -123,9 +123,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .enable_vblank = amdgpu_vkms_enable_vblank, .disable_vblank = amdgpu_vkms_disable_vblank, .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, +#endif }; static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, From 0fee62476e18fb67b5c068351fe9a2d48a16dda6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 3 Nov 2021 12:48:17 +0800 Subject: [PATCH 0707/2070] drm/amdkcl: test atomic_enable function in drm_crtc_helper_funcs and its argument type It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 16 +++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 7 +++- .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 33 +++++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 5af32c6d1fe9d..783ee9498736e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -131,19 +131,31 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { }; static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { drm_crtc_vblank_on(crtc); } static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { drm_crtc_vblank_off(crtc); } static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { unsigned long flags; if (crtc->state->event) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 65d6c0f60c79e..3ecbea3bf5536 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -234,9 +234,14 @@ /* drm_crtc_from_index() is available */ #define HAVE_DRM_CRTC_FROM_INDEX 1 -/* drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg */ +/* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants + struct drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct + drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 + /* drm_crtc_init_with_planes() wants name */ #define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 index 7f43ce7a2f5e2..5bfb416a8ed5e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -1,6 +1,9 @@ dnl # -dnl # commit v5.2-rc2-529-g6f3b62781bbd -dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # v5.10-rc2-260-g29b77ad7b9ca +dnl # drm/atomic: Pass the full state to CRTC atomic_check +dnl +dnl # v5.10-rc2-261-gf6ebe9f9c923 +dnl # drm/atomic: Pass the full state to CRTC atomic begin and flush dnl # AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ @@ -12,7 +15,31 @@ AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ p->atomic_check(NULL, (struct drm_atomic_state*)NULL); ], [ AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, - [drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + [drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg]) ]) ]) ]) + +dnl # +dnl # v5.9-rc5-1161-g351f950db4ab +dnl # drm/atomic: Pass the full state to CRTC atomic enable/disable +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_enable(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct drm_atomic_state arg]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d553ca218fe00..a5a80c4011dbc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -98,7 +98,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG - AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE From 9acda4487f10e91fc4872f20c09d8094d43e855f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Nov 2021 21:41:40 +0800 Subject: [PATCH 0708/2070] drm/amdkcl: wrap code under macro AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 783ee9498736e..7994dfc3929cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -275,16 +275,26 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { }; static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *old_state) +#else + struct drm_plane_state *old_state) +#endif { return; } static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state) +{ + struct drm_atomic_state *state = new_plane_state->state; +#endif struct drm_crtc_state *crtc_state; int ret; @@ -293,6 +303,7 @@ static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); + if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); From af4e20bb7bc32234dbba6f69acc4d0962c969108 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Sat, 6 Nov 2021 20:01:37 +0800 Subject: [PATCH 0709/2070] drm/amdkcl: update sources file to include kfd_sysfs.h Fix: 1aefe844453b("drm/amdkfd: Add sysfs bitfields and enums to uAPI") Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/sources | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index a1b74441203de..da9e9612a23fb 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -28,3 +28,4 @@ include/drm/amd_rdma.h include/drm/ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ +include/uapi/linux/kfd_sysfs.h include/uapi/linux/ From d25f189f7b55596af4d9eaef127a0c1cc2fd163b Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 8 Nov 2021 14:58:25 +0800 Subject: [PATCH 0710/2070] drm/amdkcl: guard amdgpu_driver_release_kms by HAVE_DRM_DRIVER_RELEASE Fix: 1776040c6227("drm/amd/amdkcl: fix minor index not removed after unload driver") Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index b788a5ae51bc5..3a594c304cd6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1645,7 +1645,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } - void amdgpu_driver_release_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); From 07d8d444b437d29b3c2042edb9bd16e47b79186b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 8 Nov 2021 10:55:23 +0800 Subject: [PATCH 0711/2070] drm/amdkcl: drop drmP.h in kcl_drm_simple_encoder_init.h Fix a intree build error caused by 925fd65464c80f28ed1bea7357c7389acbb618ea "drm/amdkcl: fake drm_simple_encoder_init" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- include/kcl/kcl_drm_simple_kms_helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_simple_kms_helper.h b/include/kcl/kcl_drm_simple_kms_helper.h index 51a6699486da0..f6a5ac0c15d00 100644 --- a/include/kcl/kcl_drm_simple_kms_helper.h +++ b/include/kcl/kcl_drm_simple_kms_helper.h @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include From 9e31e5170c9cbf40caf959ca9e429da72835862d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 1 Nov 2021 20:18:06 +0800 Subject: [PATCH 0712/2070] drm/amdkcl: assign dpms for amdgpu_vkms_crtc_helper_funcs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In drm_helper_disable_unused_functions(), when !crtc->enable is false, a NULL pointer crtc_funcs->dpms may occur. To avoid this, assign dpms for amdgpu_vkms_crtc_helper_funcs. Call Trace: __drm_helper_disable_unused_functions+0xac/0xe0 [drm_kms_helper] drm_helper_disable_unused_functions+0x38/0x60 [drm_kms_helper] amdgpu_fbdev_init+0xf6/0x100 [amdgpu] amdgpu_device_init+0x13d4/0x1f10 [amdgpu] Fixes: ba5317109d0ce ("drm/amdgpu: create amdgpu_vkms (v4)") Ackded-by：Guchun Chen Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 7994dfc3929cf..56c1c1f97dbcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -172,7 +172,33 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } +static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + unsigned type; + + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_crtc->enabled = true; + /* Make sure VBLANK interrupts are still enabled */ + type = amdgpu_display_crtc_idx_to_irq_type(adev, + amdgpu_crtc->crtc_id); + amdgpu_irq_update(adev, &adev->crtc_irq, type); + drm_crtc_vblank_on(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + drm_crtc_vblank_off(crtc); + amdgpu_crtc->enabled = false; + break; + } +} + static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { + .dpms = amdgpu_vkms_crtc_dpms, .atomic_flush = amdgpu_vkms_crtc_atomic_flush, .atomic_enable = amdgpu_vkms_crtc_atomic_enable, .atomic_disable = amdgpu_vkms_crtc_atomic_disable, From 7a7c20706a496ef06875e06dd7394c0bc97d0209 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Tue, 26 Oct 2021 17:35:34 -0500 Subject: [PATCH 0713/2070] drm/amdkfd: Pin MMIO/DOORBELL BO's in GTT domain MMIO/DOORBELL BOs encode control data and should be pinned in GTT domain before enabling PCIe connected peer devices in accessing it Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 23 ++++++++++++++++++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 3 ++- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index f26cfc77c379f..841c4bdcbf47c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -343,7 +343,28 @@ struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, uint32_t *flags); void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); -int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo); +/** + * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria + * @bo: Handle of buffer object being pinned + * @domain: Domain into which BO should be pinned + * + * - USERPTR BOs are UNPINNABLE and will return error + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count incremented. It is valid to PIN a BO multiple times + * + * Return: ZERO if successful in pinning, Non-Zero in case of error. + * Will return -EINVAL if input BO parameter is a USERPTR type. + */ +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); + +/** + * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria + * @bo: Handle of buffer object being unpinned + * + * - Is a illegal request for USERPTR BOs and is ignored + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count decremented. Calls to UNPIN must balance calls to PIN + */ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index caa1a925d7943..edd80db079c79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1941,6 +1941,23 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (offset) *offset = amdgpu_bo_mmap_offset(bo); + if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { + ret = amdgpu_amdkfd_bo_validate(bo, AMDGPU_GEM_DOMAIN_GTT, false); + if (ret) { + pr_err("Validating MMIO/DOORBELL BO during ALLOC FAILED\n"); + goto err_node_allow; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); + goto err_node_allow; + } + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + } + return 0; allocate_init_user_pages_failed: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 27fe96b788de6..f8c89ba5ff86b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -261,7 +261,8 @@ static int amd_get_pages(unsigned long addr, size_t size, int write, int force, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo); + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo, + mem_context->bo->kfd_bo->domain); if (ret) { pr_err("Pinning of buffer failed.\n"); return ret; From e2419e371263e87fedef48c98dff9b6aa351e116 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Nov 2021 17:49:38 +0800 Subject: [PATCH 0714/2070] drm/amdkcl: nuke dpms callback Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 56c1c1f97dbcf..d6c9618fd1074 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -174,27 +174,7 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) { - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - unsigned type; - - switch (mode) { - case DRM_MODE_DPMS_ON: - amdgpu_crtc->enabled = true; - /* Make sure VBLANK interrupts are still enabled */ - type = amdgpu_display_crtc_idx_to_irq_type(adev, - amdgpu_crtc->crtc_id); - amdgpu_irq_update(adev, &adev->crtc_irq, type); - drm_crtc_vblank_on(crtc); - break; - case DRM_MODE_DPMS_STANDBY: - case DRM_MODE_DPMS_SUSPEND: - case DRM_MODE_DPMS_OFF: - drm_crtc_vblank_off(crtc); - amdgpu_crtc->enabled = false; - break; - } + return; } static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { From db6345d5eeed4988a44052334bb5e96544245c4a Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 10 Nov 2021 15:04:58 -0600 Subject: [PATCH 0715/2070] drm/amdgpu: Fix error handling path while allocating MMIO/DOORBELL BOs MMIO/DOORBELL BOs are pinned as part allocation procedure. The patch fixes a bug in error handling part of pinning MMIO/DOORBELL BO Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 841c4bdcbf47c..44f2db76ba87c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -353,7 +353,6 @@ void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); * PIN count incremented. It is valid to PIN a BO multiple times * * Return: ZERO if successful in pinning, Non-Zero in case of error. - * Will return -EINVAL if input BO parameter is a USERPTR type. */ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index edd80db079c79..93ceb3ad753e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1943,16 +1943,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { - ret = amdgpu_amdkfd_bo_validate(bo, AMDGPU_GEM_DOMAIN_GTT, false); - if (ret) { - pr_err("Validating MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_node_allow; - } - ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); if (ret) { pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_node_allow; + goto err_pin_bo; } bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; From 8e146a95e29d92c0c1cd83a4d2e808465db3660a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 14:09:46 +0800 Subject: [PATCH 0716/2070] drm/amdkcl: check whether drm_fbdev_generic_setup() is available It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3ecbea3bf5536..4cb776d5f2faa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -441,6 +441,9 @@ /* drm_encoder_find() wants file_priv */ #define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 +/* drm_fbdev_generic_setup() is available */ +#define HAVE_DRM_FBDEV_GENERIC_SETUP 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 new file mode 100644 index 0000000000000..cfd16b033ccbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.18-rc3-614-g9060d7f49376 +dnl # drm/fb-helper: Finish the generic fbdev emulation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_fbdev_generic_setup(NULL, 0); + ], [drm_fbdev_generic_setup], [drivers/gpu/drm/drm_fb_helper.c],[ + AC_DEFINE(HAVE_DRM_FBDEV_GENERIC_SETUP, 1, + [drm_fbdev_generic_setup() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a5a80c4011dbc..6d84dc33e5f70 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -133,6 +133,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From ce062d807d755da9de0659944455c10b6c94dcd7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 15:07:23 +0800 Subject: [PATCH 0717/2070] drm/amdkcl: check whether struct drm_device has fb_helper member It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 29 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ------ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/drm-device-fb-helper.m4 | 21 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 7 files changed, 58 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 7fea74ffe51d6..a3fbe1610da0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -51,7 +51,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ - amdgpu_gem.o amdgpu_ring.o \ + amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \ atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 8210c0bc5ccb6..31526082c3b58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -24,6 +24,8 @@ * David Airlie */ +#ifndef HAVE_DRM_DEVICE_FB_HELPER + #include #include #include @@ -402,3 +404,4 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; return false; } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 623f31939885c..9f754950a7743 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -231,6 +231,11 @@ struct amdgpu_i2c_chan { struct mutex mutex; }; + +#ifndef HAVE_DRM_DEVICE_FB_HELPER +struct amdgpu_fbdev; +#endif + struct amdgpu_afmt { bool enabled; int offset; @@ -310,6 +315,15 @@ struct amdgpu_framebuffer { uint64_t address; }; +#ifndef HAVE_DRM_DEVICE_FB_HELPER +struct amdgpu_fbdev { + struct drm_fb_helper helper; + struct amdgpu_framebuffer rfb; + struct list_head fbdev_list; + struct amdgpu_device *adev; +}; +#endif + struct amdgpu_mode_info { struct atom_context *atom_context; struct card_info *atom_card_info; @@ -334,6 +348,10 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; +#ifndef HAVE_DRM_DEVICE_FB_HELPER + /* pointer to fbdev info structure */ + struct amdgpu_fbdev *rfbdev; +#endif /* firmware flags */ u32 firmware_flags; /* pointer to backlight encoder */ @@ -701,6 +719,17 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +#ifndef HAVE_DRM_DEVICE_FB_HELPER +/* fbdev layer */ +int amdgpu_fbdev_init(struct amdgpu_device *adev); +void amdgpu_fbdev_fini(struct amdgpu_device *adev); +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); +int amdgpu_fbdev_total_size(struct amdgpu_device *adev); +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); +#endif + /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 15d0ee425f106..ba8b99566094c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -893,10 +893,6 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, mutex_unlock(&mgr->lock); } drm_connector_unregister(connector); -#ifdef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS - if (adev->mode_info.rfbdev) - drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); -#endif drm_connector_put(connector); } #endif @@ -917,11 +913,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); - if (adev->mode_info.rfbdev) - drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); - else - DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); - drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4cb776d5f2faa..c82541ab86b9c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -251,6 +251,9 @@ /* dev_device->driver_features is available */ #define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 +/* struct drm_device has fb_helper member */ +#define HAVE_DRM_DEVICE_FB_HELPER 1 + /* drm_device->filelist_mutex is available */ #define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 new file mode 100644 index 0000000000000..b5e24caf0a842 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.14-rc3-575-g29ad20b22c8f +dnl # drm: Add drm_device->fb_helper pointer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_FB_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #ifdef HAVE_DRM_DRM_DEVICE_H + #include + #endif + ], [ + struct drm_device *pdd = NULL; + pdd->fb_helper = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_FB_HELPER, 1, [struct drm_device has fb_helper member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6d84dc33e5f70..5b5d3363db6fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,6 +134,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP + AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From afb2d7dbe662f48444f65a7cdf5f5dbfbd413ebe Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Fri, 12 Nov 2021 12:40:38 -0500 Subject: [PATCH 0718/2070] drm/amdkfd: remove unused variable in alloc gpuvm Unused "int mem_type" got removed in drm-next during alloc gpuvm update but not in dkms staging for whatever reason. Remove it to silence the usused variable warning during compile. Signed-off-by: Jonathan Kim Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index c64881f8100b6..28b9ab0919c14 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -755,7 +755,6 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, { struct kfd_node *kdev = pdd->dev; int err; - unsigned int mem_type; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, pdd->drm_priv, mem, NULL, From 7bd735a5ad723cfabe261135edf075e8bad37387 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 15 Nov 2021 17:38:07 +0800 Subject: [PATCH 0719/2070] drm/amdgpu: fix amdgpu_vkms support otherwise adev->mode_info.crtcs[] & adev->mode_info.funcs are NULL and would trigger NULL pointer error Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 67 ++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index d6c9618fd1074..a74740e8b88c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -518,6 +518,73 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + return 0; +} + +static void amdgpu_vkms_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) +{ + return; +} + +static int amdgpu_vkms_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + *vbl = 0; + *position = 0; + + return -EINVAL; +} + +static bool amdgpu_vkms_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return true; +} + +static void amdgpu_vkms_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return; +} + +static u32 amdgpu_vkms_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return 0; +} + +static void amdgpu_vkms_bandwidth_update(struct amdgpu_device *adev) +{ + return; +} + +static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { + .bandwidth_update = &amdgpu_vkms_bandwidth_update, + .vblank_get_counter = &amdgpu_vkms_vblank_get_counter, + .backlight_set_level = NULL, + .backlight_get_level = NULL, + .hpd_sense = &amdgpu_vkms_hpd_sense, + .hpd_set_polarity = &amdgpu_vkms_hpd_set_polarity, + .hpd_get_gpio_reg = &amdgpu_vkms_hpd_get_gpio_reg, + .page_flip = &amdgpu_vkms_page_flip, + .page_flip_get_scanoutpos = &amdgpu_vkms_crtc_get_scanoutpos, + .add_encoder = NULL, + .add_connector = NULL, +}; + +static int amdgpu_vkms_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + + adev->mode_info.num_hpd = 1; + adev->mode_info.num_dig = 1; + return 0; +} + const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, .atomic_check = drm_atomic_helper_check, From 7009d2133dca0e117765005548eb6116d688ab69 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 15:55:39 +0800 Subject: [PATCH 0720/2070] drm/amdkcl: check whether drm_dp_update_payload_part1() has start_slot argument It's caused by cf95d5c0c94100fd76bb590657ceb94db4097c42 "drm: Update MST First Link Slot Information Based on Encoding Format" v5.13-2803-gcf95d5c0c941 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ ...drm-up-update-payload-part1-start-slot-arg.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c82541ab86b9c..502e4bf5398d1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -347,6 +347,9 @@ /* drm_dp_start_crc() is available */ #define HAVE_DRM_DP_START_CRC 1 +/* drm_dp_update_payload_part1() function has start_slot argument */ +#define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 + /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 new file mode 100644 index 0000000000000..1b341003bb985 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-2803-gcf95d5c0c941 +dnl # drm: Update MST First Link Slot Information Based on Encoding Format +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_update_payload_part1(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG, 1, + [drm_dp_update_payload_part1() function has start_slot argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5b5d3363db6fc..654f12ec083ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,7 +134,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP - AC_AMDGPU_DRM_DEVICE_FB_HELPER + AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 3bf89db97e8e6bd2b9c7bbef820c2811c5c7b5da Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Nov 2021 13:03:51 +0800 Subject: [PATCH 0721/2070] drm/amdkcl: test whether struct drm_dp_mst_topology_state has member total_avail_slots It's caused by cf95d5c0c94100fd76bb590657ceb94db4097c42 "drm: Update MST First Link Slot Information Based on Encoding Format" v5.13-2803-gcf95d5c0c941 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index de9709320487a..687e7c6eb0f2b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12845,6 +12845,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { struct amdgpu_dm_connector *aconnector; @@ -12864,7 +12865,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } - +#endif /** * Streams and planes are reset when there are changes that affect * bandwidth. Anything that affects bandwidth needs to go through diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 502e4bf5398d1..1e70591bea1d3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -341,6 +341,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* struct drm_dp_mst_topology_state has member total_avail_slots */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 new file mode 100644 index 0000000000000..9684ef25199df --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.15-rc2-1075-gd6c6a76f80a1 +dnl # Update MST First Link Slot Information Based on Encoding Format +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + mst_state->total_avail_slots = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS, 1, + [struct drm_dp_mst_topology_state has member total_avail_slots]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 654f12ec083ce..a85f7142a5952 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -135,6 +135,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From f45277ae2e49d826ffcbf6c38c908ee7c43537ea Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 12 Nov 2021 11:22:38 -0500 Subject: [PATCH 0722/2070] drm/amdkcl: use autoconf to tarck amdgpu version Change-Id: Idef567dd18760272fbc5e4b7fda76d35f47062d0 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/dkms/configure.ac | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 85c521ec8c0dc..46a1b7ae03205 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -132,7 +132,6 @@ #define KMS_DRIVER_MINOR 64 #define KMS_DRIVER_PATCHLEVEL 0 -#define AMDGPU_VERSION "19.10.9.418" /* * amdgpu.debug module options. Are all disabled by default */ diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index b367e452d4cbb..71855ccd6e523 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 19.40) +AC_INIT(amdgpu-dkms, 5.13.5) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a85f7142a5952..98d8fc1c4a519 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -144,6 +144,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_SUBST(KERNEL_MAKE) AH_BOTTOM([#include "config-amd-chips.h"]) + AH_BOTTOM([#define AMDGPU_VERSION PACKAGE_VERSION]) ]) dnl # From 0206c1ecf776232f49e1ebb0cd872956a09becfa Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 18 Nov 2021 09:59:29 -0500 Subject: [PATCH 0723/2070] drm/amdkcl/dkms: Version strings in DKMS config.h Correct version strings in config.h and add AMDGPU_VERSION macro to fix in-tree kernel build. Other diffs observed in the file after regeneration are pointing to problematic tests that may affect DKMS functionality. They have to be re-visited and fixed. The list of suspicious test results is: HAVE_ACPI_PUT_TABLE HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS Change-Id: I5afb975182c029d047f71356098514196b719aee Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1e70591bea1d3..843235a303f41 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1073,7 +1073,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 19.40" +#define PACKAGE_STRING "amdgpu-dkms 5.13.6" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1082,6 +1082,8 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "19.40" +#define PACKAGE_VERSION "5.13.6" #include "config-amd-chips.h" + +#define AMDGPU_VERSION PACKAGE_VERSION From 211fb6015a1c02289f4c8f2e3b5eb29f10f57b02 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:17:34 +0800 Subject: [PATCH 0724/2070] drm/amdkcl: guard CONFIG_X86 for x86 related stuff Signed-off-by: Flora Cui Tested-by: Emily.Deng Reviewed-by: Leslie Shi --- include/kcl/kcl_intel_family.h | 4 +++- include/kcl/kcl_mce.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index 20781af676d6b..a4d7693bf0b0b 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -2,11 +2,13 @@ #ifndef AMDKCL_INTEL_FAMILY_H #define AMDKCL_INTEL_FAMILY_H +#ifdef CONFIG_X86 + #include /* Copied froma asm/intel-family.h*/ #ifndef INTEL_FAM6_ROCKETLAKE #define INTEL_FAM6_ROCKETLAKE 0xA7 #endif +#endif /* CONFIG_X86 */ #endif - diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 037fb0c1b3e37..5418ec9351e36 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -2,10 +2,14 @@ #ifndef AMDKCL_MCE_H #define AMDKCL_MCE_H +#ifdef CONFIG_X86 + #include + /* Copied from asm/mce.h */ #ifndef XEC #define XEC(x, mask) (((x) >> 16) & mask) #endif +#endif /* CONFIG_X86 */ #endif From 1a2df9820851d35f7797de79454b834d78a0c77e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:18:34 +0800 Subject: [PATCH 0725/2070] drm/amdkcl: misc fix for autoconf test Signed-off-by: Flora Cui Tested-by: Emily.Deng Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/access-ok.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 index 066bd767ddf78..70a1ec664ef7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - access_ok(1, 1); + access_ok(0, 0); ],[ AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, [whether access_ok(x, x) is available]) From 51cadd269aecc1e8023401ff9acafa1fba767cf1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 22 Jan 2024 16:05:41 +0800 Subject: [PATCH 0726/2070] drm/amdkcl: fix vkms hrtimer settings Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 62 +++++++++++++++++++++--- include/kcl/backport/kcl_drm_backport.h | 8 +++ 2 files changed, 63 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index a74740e8b88c8..0037748caf1a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -46,6 +46,7 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) { struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); struct drm_crtc *crtc = &amdgpu_crtc->base; + struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); u64 ret_overrun; bool ret; @@ -101,7 +102,6 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, } *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; /* @@ -172,13 +172,8 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } -static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) -{ - return; -} static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { - .dpms = amdgpu_vkms_crtc_dpms, .atomic_flush = amdgpu_vkms_crtc_atomic_flush, .atomic_enable = amdgpu_vkms_crtc_atomic_enable, .atomic_disable = amdgpu_vkms_crtc_atomic_disable, @@ -214,12 +209,33 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, return ret; } +#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY +static int +amdgpu_vkms_connector_dpms(struct drm_connector *connector, int mode) +{ + return 0; +} + + +static int +amdgpu_vkms_connector_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + return 0; +} +#endif + static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = drm_atomic_helper_connector_reset, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY + .set_property = amdgpu_vkms_connector_set_property, + .dpms = amdgpu_vkms_connector_dpms, +#endif }; static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) @@ -518,6 +534,7 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) { return 0; @@ -574,16 +591,47 @@ static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { .add_connector = NULL, }; +static int amdgpu_vkms_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + if (type > AMDGPU_CRTC_IRQ_VBLANK6) + return -EINVAL; + + if (type >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[type]) { + DRM_DEBUG("invalid crtc %d\n", type); + return -EINVAL; + } + + adev->mode_info.crtcs[type]->vsync_timer_enabled = state; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + amdgpu_vkms_enable_vblank(&adev->mode_info.crtcs[type]->base); + else + amdgpu_vkms_disable_vblank(&adev->mode_info.crtcs[type]->base); + + return 0; +} + +static const struct amdgpu_irq_src_funcs amdgpu_vkms_crtc_irq_funcs = { + .set = amdgpu_vkms_set_crtc_irq_state, + .process = NULL, +}; + static int amdgpu_vkms_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + adev->crtc_irq.num_types = adev->mode_info.num_crtc; + adev->crtc_irq.funcs = &amdgpu_vkms_crtc_irq_funcs; + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; adev->mode_info.num_hpd = 1; adev->mode_info.num_dig = 1; return 0; } +#endif const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 668fa168e20bd..c17c10af84c09 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -22,4 +22,12 @@ #define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE #endif +/* + * commit v4.13-rc2-365-g144a7999d633 + * drm: Handle properties in the core for atomic drivers + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 14, 0) +#define AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY +#endif + #endif/*AMDKCL_DRM_BACKPORT_H*/ From 7082e0d55e85464f47fba8725f19c4e9eebd85ac Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:25:45 +0800 Subject: [PATCH 0727/2070] drm/amdkcl: update related flags for atomic unsupported case Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 46a1b7ae03205..9bec337813297 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2413,6 +2413,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, return -ENODEV; } + if (flags == 0) { + DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); + return -ENODEV; + } + if (amdgpu_virtual_display || amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) supports_atomic = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 31526082c3b58..c83d8cc07d80f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -359,7 +359,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev) } /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!amdgpu_device_has_dc_support(adev)) + if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) drm_helper_disable_unused_functions(adev_to_drm(adev)); drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); From 24cab339bc7daa7dd75c9c3646955c3a946c82f7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 19 Nov 2021 10:34:32 +0800 Subject: [PATCH 0728/2070] drm/amdkcl: add strict restriction when calling drm_fbdev_generic_setup It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 13 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 +++---- .../drm/amd/dkms/m4/drm-device-fb-helper.m4 | 21 ------------------- include/kcl/backport/kcl_drm_fb.h | 6 ++++++ 7 files changed, 37 insertions(+), 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 537ba57d208f7..f4832b7c8adfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4750,6 +4750,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + amdgpu_fbdev_init(adev); +#endif /* * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. * Otherwise the mgpu fan boost feature will be skipped due to the @@ -4916,6 +4919,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_device_sys_interface_fini(adev); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + amdgpu_fbdev_fini(adev); +#endif /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 42d8852ac5ea1..65eccbb058c1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1780,6 +1780,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } +#ifdef AMDKCL_DRM_FBDEV_GENERIC static bool amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { @@ -1794,6 +1795,7 @@ amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; } +#endif int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { @@ -1833,6 +1835,16 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) continue; robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + /* don't unpin kernel fb objects */ + if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { + r = amdgpu_bo_reserve(robj, true); + if (r == 0) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + } +#else if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { @@ -1840,6 +1852,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) amdgpu_bo_unreserve(robj); } } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index c83d8cc07d80f..d0d99d095f96e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -24,7 +24,7 @@ * David Airlie */ -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC #include #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 7ae72b299de7c..b855f760fd1a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1356,6 +1356,7 @@ int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, return ret; } +#ifdef AMDKCL_DRM_FBDEV_GENERIC static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, @@ -1381,6 +1382,7 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, aligned &= ~pitch_mask; return aligned * cpp; } +#endif int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -1404,8 +1406,13 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, if (adev->mman.buffer_funcs_enabled) flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; +#ifdef AMDKCL_DRM_FBDEV_GENERIC args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); +#else + args->pitch = amdgpu_align_pitch(adev, args->width, + DIV_ROUND_UP(args->bpp, 8), 0); +#endif args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 9f754950a7743..304e8d3fccb1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -232,7 +232,7 @@ struct amdgpu_i2c_chan { }; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC struct amdgpu_fbdev; #endif @@ -315,7 +315,7 @@ struct amdgpu_framebuffer { uint64_t address; }; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC struct amdgpu_fbdev { struct drm_fb_helper helper; struct amdgpu_framebuffer rfb; @@ -348,7 +348,7 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC /* pointer to fbdev info structure */ struct amdgpu_fbdev *rfbdev; #endif @@ -719,7 +719,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC /* fbdev layer */ int amdgpu_fbdev_init(struct amdgpu_device *adev); void amdgpu_fbdev_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 deleted file mode 100644 index b5e24caf0a842..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-575-g29ad20b22c8f -dnl # drm: Add drm_device->fb_helper pointer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEVICE_FB_HELPER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #endif - #ifdef HAVE_DRM_DRM_DEVICE_H - #include - #endif - ], [ - struct drm_device *pdd = NULL; - pdd->fb_helper = NULL; - ], [ - AC_DEFINE(HAVE_DRM_DEVICE_FB_HELPER, 1, [struct drm_device has fb_helper member]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index c83d4ffd135b4..1e29f3cd082f0 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -28,4 +28,10 @@ #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) #define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers #endif + +#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ + DRM_VERSION_CODE >= DRM_VERSION(5, 13, 0) +#define AMDKCL_DRM_FBDEV_GENERIC +#endif + #endif From 4d164b0b4372cfb1e96fed823e7572b289c71ff1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Nov 2021 14:52:04 +0800 Subject: [PATCH 0729/2070] drm/amdkfd: replace kgd_dev with amdgpu_device Modified definitions: - amdgpu_amdkfd_copy_mem_to_mem - amdgpu_amdkfd_send_close_event_drain_irq - amdgpu_amdkfd_gfx_off_ctrl - amdgpu_amdkfd_gpuvm_get_sg_table - amdgpu_amdkfd_gpuvm_export_ipc_obj - amdgpu_amdkfd_debug_mem_fence - amdgpu_amdkfd_rlc_spm_cntl - amdgpu_amdkfd_rlc_spm_acquire - amdgpu_amdkfd_rlc_spm_release - amdgpu_amdkfd_rlc_spm_set_rdptr - kgd_aldebaran_enable_debug_trap - kgd_aldebaran_disable_debug_trap - kgd_aldebaran_set_wave_launch_trap_override - kgd_aldebaran_set_wave_launch_mode - kgd_aldebaran_set_precise_mem_ops - kgd_gfx_v10_enable_debug_trap - kgd_gfx_v10_disable_debug_trap - kgd_gfx_v10_set_wave_launch_trap_override - kgd_gfx_v10_set_wave_launch_mode - kgd_gfx_v10_set_address_watch - kgd_gfx_v10_clear_address_watch - kgd_gfx_v10_set_precise_mem_ops - kgd_gfx_v10_get_iq_wait_times - kgd_gfx_v10_build_grace_period_packet_info - kgd_gfx_v9_enable_debug_trap - kgd_gfx_v9_disable_debug_trap - kgd_gfx_v9_set_wave_launch_trap_override - kgd_gfx_v9_set_wave_launch_mode - kgd_gfx_v9_set_address_watch - kgd_gfx_v9_clear_address_watch - kgd_gfx_v9_set_precise_mem_ops - kgd_gfx_v9_get_iq_wait_times - kgd_gfx_v9_build_grace_period_packet_info Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 15 +++++----- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 ++---- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 12 +++----- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 6 ++-- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 28 +++++++++---------- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 8 files changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 44f2db76ba87c..a78a278b4782a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -366,7 +366,7 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); */ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); -int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint32_t flags, uint64_t offset, uint64_t size, struct device *dma_dev, enum dma_data_direction dir, @@ -375,7 +375,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, struct sg_table *sg); -int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, @@ -387,7 +387,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); -int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, uint32_t flags); @@ -449,12 +449,11 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif -void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl); -int amdgpu_amdkfd_rlc_spm(struct kgd_dev *kgd, void *args); -int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl); +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size); -void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm); -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr); +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr); void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); #if IS_ENABLED(CONFIG_HSA_AMD_SVM) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 93ceb3ad753e7..c609b611ab130 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2539,13 +2539,12 @@ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, return 0; } -int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint32_t flags, uint64_t offset, uint64_t size, struct device *dma_dev, enum dma_data_direction dir, struct sg_table **ret_sg) { - struct amdgpu_device *adev = get_amdgpu_device(kgd); struct sg_table *sg = NULL; struct scatterlist *s; struct page **pages; @@ -2789,19 +2788,17 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } -int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, uint32_t flags) { - struct amdgpu_device *adev = NULL; struct dma_buf *dmabuf; int r = 0; - if (!kgd || !vm || !mem) + if (!adev || !vm || !mem) return -EINVAL; - adev = get_amdgpu_device(kgd); mutex_lock(&mem->lock); if (mem->ipc_obj) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index eeaca9d1e02b9..1dd189536c764 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -25,9 +25,8 @@ #include #include "amdgpu_ids.h" -void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; spin_lock(&adev->gfx.kiq.ring_lock); @@ -40,9 +39,8 @@ void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) spin_unlock(&adev->gfx.kiq.ring_lock); } -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; spin_lock(&adev->gfx.kiq.ring_lock); @@ -52,9 +50,8 @@ void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) spin_unlock(&adev->gfx.kiq.ring_lock); } -int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; int r; @@ -77,9 +74,8 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 return r; } -void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm) +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; /* stop spm stream and interrupt */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index b5d89265d3c2d..b7208b22ad883 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -136,7 +136,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; } - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, mmap_offset); @@ -157,7 +157,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return 0; err_free: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; @@ -252,7 +252,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, } mem = (struct kgd_mem *)kfd_bo->mem; - r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, &ipc_obj, flags); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index f8c89ba5ff86b..09cf783e460d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -320,7 +320,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, /* Build sg_table for buffer being exported, including DMA mapping */ ret = amdgpu_amdkfd_gpuvm_get_sg_table( - mem_context->dev->kgd, mem_context->bo, mem_context->flags, + mem_context->dev->adev, mem_context->bo, mem_context->flags, mem_context->offset, mem_context->size, dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); if (ret) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 28b9ab0919c14..01cd4b34255f7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1077,7 +1077,7 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); + peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } run_rdma_free_callback(buf_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index ceabdb3680a64..b1fc5ace4015d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -147,7 +147,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } exit: - amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->kgd, spm->ring_rptr); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); return ret; } @@ -176,7 +176,7 @@ void kfd_spm_init_process_device(struct kfd_process_device *pdd) pdd->spm_cntr = NULL; } -static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { int ret = 0; @@ -200,7 +200,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; pdd->spm_cntr->has_user_buf = false; - ret = amdgpu_amdkfd_alloc_gtt_mem(kgd, + ret = amdgpu_amdkfd_alloc_gtt_mem(adev, pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, false, false); @@ -208,7 +208,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->drm_priv, + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, pdd->drm_priv, pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -230,7 +230,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: mutex_lock(&pdd->spm_mutex); @@ -242,7 +242,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) return ret; } -static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; @@ -259,8 +259,8 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(kgd, pdd->drm_priv); - amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_rlc_spm_release(adev, pdd->drm_priv); + amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); kfree(pdd->spm_cntr); @@ -330,7 +330,7 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, return ret; } -static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *kgd, void *data) +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { struct kfd_ioctl_spm_args *user_spm_data; struct kfd_spm_cntr *spm; @@ -378,7 +378,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *k /* Start SPM */ if (spm->is_spm_started == false) { - amdgpu_amdkfd_rlc_spm_cntl(kgd, 1); + amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -389,7 +389,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *k schedule_work(&pdd->spm_work); } } else { - amdgpu_amdkfd_rlc_spm_cntl(kgd, 0); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -419,13 +419,13 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) switch (args->op) { case KFD_IOCTL_SPM_OP_ACQUIRE: dev->spm_pasid = p->pasid; - return kfd_acquire_spm(pdd, dev->kgd); + return kfd_acquire_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_RELEASE: - return kfd_release_spm(pdd, dev->kgd); + return kfd_release_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_SET_DEST_BUF: - return kfd_set_dest_buffer(pdd, dev->kgd, data); + return kfd_set_dest_buffer(pdd, dev->adev, data); default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 9ea0d9cd8c91a..f0aba1eccc620 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -314,7 +314,7 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, if (mem->gpu) { if (kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; - used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->kgd); + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->adev); return sysfs_show_64bit_val(buffer, offs, used_mem); } /* TODO: Report APU/CPU-allocated memory; For now return 0 */ From 6ed12034f877e3892140dfd8fe5edb6140141058 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 25 Nov 2021 22:25:12 +0800 Subject: [PATCH 0730/2070] drm/amdgpu: correct RLC_SPM_INT_CNTL register address should count on gc base address Signed-off-by: Hawking Zhang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index bea110c04fb23..b96cedea1030a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7201,10 +7201,10 @@ static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, { switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - WREG32(mmRLC_SPM_INT_CNTL, 0); + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); break; case AMDGPU_IRQ_STATE_ENABLE: - WREG32(mmRLC_SPM_INT_CNTL, 1); + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); break; default: break; From 805259035a2a81008db1a4d688f232c58866bb43 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 17 Nov 2021 19:44:55 -0500 Subject: [PATCH 0731/2070] drm/amdkfd: Fix amdgpu_read_lock lockdep errors The amdgpu_read_lock must be taken inside the p->mutex to avoid circular lock dependencies between these two locks. Move locking from IPC and dmabuf import ioctls into kfd_import_dmabuf_create_kfd_bo to satisfy this constraint. Signed-off-by: Felix Kuehling Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index b7208b22ad883..c1f5f7dc6c5d7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -129,11 +129,14 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return -EINVAL; mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { r = PTR_ERR(pdd); - goto err_unlock; + goto err_read_unlock; } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, @@ -141,7 +144,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, (struct kgd_mem **)&mem, &size, mmap_offset); if (r) - goto err_unlock; + goto err_read_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, va_addr, size, 0, 0); @@ -150,6 +153,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_free; } + amdgpu_read_unlock(dev->ddev); mutex_unlock(&p->mutex); *handle = MAKE_HANDLE(gpu_id, idr_handle); @@ -158,6 +162,8 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); +err_read_unlock: + amdgpu_read_unlock(dev->ddev); err_unlock: mutex_unlock(&p->mutex); return r; From dd5e8838e2b0f336f4361566a4f71141189d01ff Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Tue, 30 Nov 2021 11:58:39 +0800 Subject: [PATCH 0732/2070] amd/amdgpu: Fix build issue on arm platform On arm platform, couldn't support float build. And for container it doesn't need dcn. So directly remove dcn parts. Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: Ic01a003271a9481c4e04fb1eb15fbc1162d6ccc6 --- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b9f423b84ddaf..340258b04f0aa 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -149,7 +149,9 @@ export CONFIG_DRM_AMDGPU_CIK=y export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y +ifndef CONFIG_ARM64 export CONFIG_DRM_AMD_DC_DCN1_0=y +endif subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL @@ -157,7 +159,9 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +ifndef CONFIG_ARM64 subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +endif ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE @@ -173,11 +177,13 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 # if core2 isn't in the compiler flags +ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN2_x=y export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x endif +endif obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From d999f0e72907eb5e965bcc734451abd4fd1e4485 Mon Sep 17 00:00:00 2001 From: Jiange Zhao Date: Thu, 29 Jul 2021 13:36:19 +0800 Subject: [PATCH 0733/2070] drm/amdkcl: Make dkms package compile and run on arm64 4.19 kernel Resolve the compile error about access ok Signed-off-by: Jiange Zhao Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: I703025483dd8e5fb30f5004162c3de19fe04b12c --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 ++++++------ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 2 +- include/kcl/backport/kcl_uaccess_backport.h | 10 +++++----- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1ce0ce75ba786..538e4c5edfe14 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -208,7 +208,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; @@ -229,27 +229,27 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, return -EINVAL; } - if (!access_ok((const void __user *) args->read_pointer_address, + if (!kcl_access_ok((const void __user *) args->read_pointer_address, sizeof(uint32_t))) { pr_err("Can't access read pointer\n"); return -EFAULT; } - if (!access_ok((const void __user *) args->write_pointer_address, + if (!kcl_access_ok((const void __user *) args->write_pointer_address, sizeof(uint32_t))) { pr_err("Can't access write pointer\n"); return -EFAULT; } if (args->eop_buffer_address && - !access_ok((const void __user *) args->eop_buffer_address, + !kcl_access_ok((const void __user *) args->eop_buffer_address, sizeof(uint32_t))) { pr_debug("Can't access eop buffer"); return -EFAULT; } if (args->ctx_save_restore_address && - !access_ok((const void __user *) args->ctx_save_restore_address, + !kcl_access_ok((const void __user *) args->ctx_save_restore_address, sizeof(uint32_t))) { pr_debug("Can't access ctx save restore buffer"); return -EFAULT; @@ -470,7 +470,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index d2bc169e84b0b..66b84d1040c81 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -129,7 +129,7 @@ static ssize_t kfd_smi_ev_write(struct file *filep, const char __user *user, struct kfd_smi_client *client = filep->private_data; uint64_t events; - if (!access_ok(user, size) || size < sizeof(events)) + if (!kcl_access_ok(user, size) || size < sizeof(events)) return -EFAULT; if (copy_from_user(&events, user, sizeof(events))) return -EFAULT; diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h index c7466949cad39..5e358c64a8fce 100644 --- a/include/kcl/backport/kcl_uaccess_backport.h +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -3,12 +3,12 @@ #define AMDKCL_UACCESS_BACKPORT_H #include -#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) -static inline int _kcl_access_ok(unsigned long addr, unsigned long size) +static inline int kcl_access_ok(unsigned long addr, unsigned long size) { +#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) return access_ok(VERIFY_WRITE, (addr), (size)); -} -#undef access_ok -#define access_ok _kcl_access_ok +#else + return access_ok((addr), (size)); #endif +} #endif From 9812484b90870f58be45507502fcb35873883a22 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 12 Nov 2021 15:39:32 -0600 Subject: [PATCH 0734/2070] drm/amdgpu: Fix config macro HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER Logic determining status of HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER is incorrect. Code body should reference struct dma_buf_attach_ops. Rename macro as HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER Signed-off-by: Ramesh Errabolu Acked-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++--- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 84710a8680e89..5e638e46e85df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -285,7 +285,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) attach->peer2peer = false; -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; @@ -388,7 +388,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; @@ -891,7 +891,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, #endif .move_notify = amdgpu_dma_buf_move_notify diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 843235a303f41..e120130f95795 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -918,6 +918,9 @@ /* struct dma_buf_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 +/* struct dma_buf_attach_ops->allow_peer2peer is available */ +#define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 + /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index e402bf57f2ec6..5f773c28a1b9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -10,7 +10,7 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ struct dma_buf_attach_ops *ptr = NULL; ptr->allow_peer2peer = false; ],[ - AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, + AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_attach_ops->allow_peer2peer is available]) ],[ From 1c477ccb4c5a6876b4b6f612ef72360e990d87c2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 3 Dec 2021 11:11:58 +0800 Subject: [PATCH 0735/2070] drm/amdkcl: fix dma-buf related check Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 9 ++++++++- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 5e638e46e85df..6e501f79e4947 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -135,8 +135,7 @@ __dma_resv_make_exclusive(struct dma_resv *obj) return -ENOMEM; } -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) /** * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation * @dma_buf: Shared DMA buffer @@ -559,8 +558,7 @@ static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map } const struct dma_buf_ops amdgpu_dmabuf_ops = { -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) .attach = amdgpu_dma_buf_map_attach, .detach = amdgpu_dma_buf_map_detach, .map_dma_buf = drm_gem_map_dma_buf, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9bec337813297..7444f1dc9aa5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3202,8 +3202,7 @@ static struct drm_driver amdgpu_kms_driver = { #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e120130f95795..95b97270829e5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -79,9 +79,12 @@ /* dev_pm_set_driver_flags() is available */ #define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 -/* dma_buf dynamic_mapping is available */ +/* dma_buf->dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ +/* dma_buf->dynamic_mapping is not available */ +/* #undef HAVE_DMA_BUF_OPS_LEGACY */ + /* dma_buf_unpin() is available */ #define HAVE_DMA_BUF_UNPIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index 5f773c28a1b9e..d4f139e428849 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -13,6 +13,10 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_attach_ops->allow_peer2peer is available]) + + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) ],[ dnl # dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided @@ -44,8 +48,11 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ dma_buf_ops->dynamic_mapping = true; ],[ AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, - [dma_buf dynamic_mapping is available]) + [dma_buf->dynamic_mapping is available]) ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, + [dma_buf->dynamic_mapping is not available]) + AC_AMDGPU_DRM_GEM_MAP_ATTACH ]) ]) From eab7716f248a7884932a12a1b2ea240c211c8bad Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 3 Dec 2021 11:23:06 +0800 Subject: [PATCH 0736/2070] drm/amdkcl: drop test for dma_buf_unpin It's the same with test for dma_buf_pin Signed-off-by: Flora Cui Reviewed-by: Yuan Perry --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 ---- drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 | 34 -------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 -- 4 files changed, 1 insertion(+), 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index bffcb0cb94be7..b467a3e276192 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1049,7 +1049,7 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; -#ifdef HAVE_DMA_BUF_UNPIN +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_unpin(bo->tbo.base.import_attach); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 95b97270829e5..1b275dba91292 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -85,9 +85,6 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ -/* dma_buf_unpin() is available */ -#define HAVE_DMA_BUF_UNPIN 1 - /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -927,9 +924,6 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 -/* struct dma_buf_ops->unpin() is available */ -#define HAVE_STRUCT_DMA_BUF_OPS_UNPIN 1 - /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 deleted file mode 100644 index 4c07a856211f9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 +++ /dev/null @@ -1,34 +0,0 @@ -dnl # -dnl # v5.6-rc2-335-gbb42df4662a4 -dnl # dma-buf: add dynamic DMA-buf handling v15 -dnl # -AC_DEFUN([AC_AMDGPU_DMA_BUF_UNPIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - dma_buf_unpin(NULL); - ],[ - AC_DEFINE(HAVE_DMA_BUF_UNPIN, 1, - [dma_buf_unpin() is available]) - ]) - ]) -]) - -AC_DEFUN([AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct dma_buf_ops *ptr = NULL; - ptr->unpin(NULL); - ],[ - AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_UNPIN, 1, - [struct dma_buf_ops->unpin() is available]) - ]) - ]) -]) - - - - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 98d8fc1c4a519..a4e3955488c38 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -123,8 +123,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY - AC_AMDGPU_DMA_BUF_UNPIN - AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER From 1b646ff70d5734649955cf49c351c63d9e0766fa Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 6 Dec 2021 04:02:25 -0500 Subject: [PATCH 0737/2070] drm/amdkfd: fix build error by replacing asic_name with asic type The patch will fix the build error which was caused by below commit: f31e07ea10f1 amdkfd: replace asic_family with asic_type v5.13-2961-gf31e07ea10f1 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui drm/amdkfd: fix coding style problem The patch fix the code format for the below patch. b751ff5666 drm/amdkfd: fix build error by replacing asic_name with asic type Signed-off-by: Perry Yuan Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 +-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index fc52e5bd1ca96..d823e7512a347 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -595,12 +595,12 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } - if ((kfd->device_info->asic_family == CHIP_VEGA10 + if ((kfd->adev->asic_type == CHIP_VEGA10 && kfd->mec2_fw_version < 0x81b6) - || (kfd->device_info->asic_family >= CHIP_VEGA12 - && kfd->device_info->asic_family <= CHIP_RAVEN + || (kfd->adev->asic_type >= CHIP_VEGA12 + && kfd->adev->asic_type <= CHIP_RAVEN && kfd->mec2_fw_version < 0x1b6) - || (kfd->device_info->asic_family == CHIP_ARCTURUS + || (kfd->adev->asic_type == CHIP_ARCTURUS && kfd->mec2_fw_version < 0x30)) kfd->gws_debug_workaround = true; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index f0aba1eccc620..fab95d1d884a6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1282,8 +1282,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, /* checkout source dev has atomics support on root. */ if (dev->gpu && (!dev->gpu->pci_atomic_requested || - dev->gpu->device_info->asic_family == - CHIP_HAWAII)) { + dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; return; From 8c017f3d78d3d08c50fda25849f9a792e0f14f2b Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 8 Dec 2021 04:56:12 -0500 Subject: [PATCH 0738/2070] drm/amdkcl: fix build error by adding drm_display_info.is_hdmi check The build failure caused by below commit, the patch will check if the is_hdmi is available on the current kernel. dfbe9bf067 drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi v5.13-3121-gdfbe9bf067a2 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 26 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 8 ++++++ .../gpu/drm/amd/amdgpu/atombios_encoders.c | 12 +++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm-connector-display-info-hdmi.m4 | 18 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 6486c50a8b1ce..287ea6da5a87f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -109,7 +109,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -117,7 +121,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -126,7 +134,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) dig_connector = amdgpu_connector->con_priv; if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector->display_info.is_hdmi) { +#else + drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -150,7 +162,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; } +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at @@ -1274,7 +1290,11 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector * we use the HDMI encoder mode of the display HW, * so we should verify against the max HDMI clock here. */ - if (connector->display_info.is_hdmi) +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) + if (connector->display_info.is_hdmi) +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) +#endif max_digital_pixel_clock_khz = max_hdmi_pixel_clock; if (mode->clock > max_digital_pixel_clock_khz) @@ -1571,7 +1591,11 @@ static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { return amdgpu_atombios_dp_mode_valid_helper(connector, mode); } else { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 65eccbb058c1a..bac87e4a85709 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1576,7 +1576,11 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector && connector->display_info.is_hdmi && +#else + drm_detect_hdmi_monitor(to_amdgpu_connector(connector)->edid) && +#endif amdgpu_display_is_hdtv_mode(mode)))) { if (amdgpu_encoder->underscan_hborder != 0) amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 3aaeed2d35620..dbd12456ff5fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -222,7 +222,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (pixel_clock > 340000) return true; else @@ -244,7 +248,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, return false; else { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (pixel_clock > 340000) return true; else diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 34644cab6cff5..df7fe6c474ca9 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -466,7 +466,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_connector->use_digital && (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else if (amdgpu_connector->use_digital) @@ -485,7 +489,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else @@ -503,7 +511,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) } else if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 9294956f9a500..32cff405ca943 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -137,7 +137,12 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; +#else + edid_caps->edid_hdmi = drm_detect_hdmi_monitor( + (struct edid *) edid->raw_edid); +#endif if (edid_caps->edid_hdmi) populate_hdmi_info_from_connector(&connector->display_info.hdmi, edid_caps); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1b275dba91292..3f7a0b1575a2f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -287,6 +287,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 new file mode 100644 index 0000000000000..7c3454c843d50 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # dfbe9bf0 introduce this change +dnl # drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi +dnl # v5.13-3121-gdfbe9bf067a2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->is_hdmi = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_IS_HDMI, 1, + [display_info->is_hdmi is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a4e3955488c38..29fa620e0df37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,6 +134,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS + AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 9a06277a24f6f9977bbdfaf6cdbe5a3d8178e195 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 8 Dec 2021 10:45:57 -0500 Subject: [PATCH 0739/2070] drm/amdkcl: fix build error of debugfs entry dp_set_mst_en_for_sst_ops wrap the dp_set_mst_en_for_sst_ops debug entry code, the build error was caused by below commit : ad9601f002 drm/amd/display: Add Debugfs Entry to Force in SST Sequence v5.13-3122-gad9601f00296 Signed-off-by: Perry Yuan Reviewed-by: Shi, Leslie --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 06fff21e5f473..2bab031ef9235 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4211,9 +4211,10 @@ static int dp_force_sst_get(void *data, u64 *val) return 0; } + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); - /* * Force DP2 sequence without VESA certified cable. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id @@ -4237,6 +4238,7 @@ static int dp_ignore_cable_id_get(void *data, u64 *val) } DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, dp_ignore_cable_id_set, "%llu\n"); +#endif /* * Sets the DC visual confirm debug option from the given string. @@ -4389,12 +4391,12 @@ void dtn_debugfs_init(struct amdgpu_device *adev) adev, &capabilities_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, &dp_set_mst_en_for_sst_ops); debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); - -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); From 005da8810922272f36141e94618853d6e7a17c88 Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Mon, 13 Dec 2021 16:28:57 -0600 Subject: [PATCH 0740/2070] drm/amdkfd: explicitly create/destroy queue attributes under /sys When application is about finish it destroys queues it has created by an ioctl. Driver deletes queue entry(/sys/class/kfd/kfd/proc/pid/queues/queueid/) which is directory including this queue all attributes. Low level kernel code deletes all attributes under this directory. The lock from kernel is on queue entry, not its attributes. At meantime another user space application can read the attributes. There is possibility that the application can hold/read the attributes while kernel is deleting the queue entry, cause the application have invalid memory access, then killed by kernel. Driver changes: explicitly create/destroy each attribute for each queue, let kernel put lock on each attribute too. Signed-off-by: Xiaogang Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 24f75e3f31f8c..1e014e6ead1a2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -650,6 +650,9 @@ struct queue { /* procfs */ struct kobject kobj; + struct attribute attr_guid; + struct attribute attr_size; + struct attribute attr_type; void *gang_ctx_bo; uint64_t gang_ctx_gpu_addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 01cd4b34255f7..4448e2889d7f1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -87,6 +87,8 @@ static void evict_process_worker(struct work_struct *work); static void restore_process_worker(struct work_struct *work); static void kfd_process_device_destroy_cwsr_dgpu(struct kfd_process_device *pdd); +static void kfd_sysfs_create_file(struct kobject *kobj, struct attribute *attr, + char *name); struct kfd_procfs_tree { struct kobject *kobj; @@ -552,6 +554,10 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } + kfd_sysfs_create_file(&q->kobj, &q->attr_guid, "guid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); + kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); + return 0; } @@ -696,6 +702,10 @@ void kfd_procfs_del_queue(struct queue *q) if (!q) return; + sysfs_remove_file(&q->kobj, &q->attr_guid); + sysfs_remove_file(&q->kobj, &q->attr_size); + sysfs_remove_file(&q->kobj, &q->attr_type); + kobject_del(&q->kobj); kobject_put(&q->kobj); } From d8e01ff50e0100d6a7833cc7d681cd7f42382f6b Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 13 Dec 2021 03:34:27 -0500 Subject: [PATCH 0741/2070] drm/amdkcl: define macro of HDMI FRL feature for legacy os * Add some micro definition missing when building on ubuntu 5.8 kernel version * wrap DSC code with DSC support micro 8808f3ffb14 drm/amd/display: Add DP-HDMI FRL PCON Support in DC v5.13-3064-g8808f3ffb14d Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 54 +++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 7fb0da12e569b..d92383908edc8 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -207,4 +207,58 @@ enum drm_dp_phy { #endif +/* + * v5.10-rc2-482-gce32a6239de6 + * drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON + */ +#ifndef DP_PCON_HDMI_POST_FRL_STATUS + +/* PCON CONFIGURE-1 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A +# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) +# define DP_PCON_ENABLE_MAX_BW_0GBPS 0 +# define DP_PCON_ENABLE_MAX_BW_9GBPS 1 +# define DP_PCON_ENABLE_MAX_BW_18GBPS 2 +# define DP_PCON_ENABLE_MAX_BW_24GBPS 3 +# define DP_PCON_ENABLE_MAX_BW_32GBPS 4 +# define DP_PCON_ENABLE_MAX_BW_40GBPS 5 +# define DP_PCON_ENABLE_MAX_BW_48GBPS 6 +# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) +# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) +# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) +# define DP_PCON_ENABLE_HPD_READY (1 << 6) +# define DP_PCON_ENABLE_HDMI_LINK (1 << 7) + +/* PCON CONFIGURE-2 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B +# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) +# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) +# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) +# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) +# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) +# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) +# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) +# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) + +/* PCON HDMI LINK STATUS */ +#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B +# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) +# define DP_PCON_FRL_READY (1 << 1) + +/* PCON HDMI POST FRL STATUS */ +#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 +# define DP_PCON_HDMI_LINK_MODE (1 << 0) +# define DP_PCON_HDMI_MODE_TMDS 0 +# define DP_PCON_HDMI_MODE_FRL 1 +# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) +# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) +# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) +# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) +# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) +# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) +# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 4cd6601b9c66f6474a65eb8929238e4af1812ba6 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Fri, 10 Dec 2021 21:31:38 -0500 Subject: [PATCH 0742/2070] drm/amd/display: Fix Compile Error for DCE Guard the new debugfs entry to DCN only Follow-up fix for: drm/amd/display: Add Debugfs Entry to Force in SST Sequence Signed-off-by: Fangzhi Zuo Reviewed-by: Nicholas Choi Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 2bab031ef9235..08086b7aaa034 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4215,6 +4215,7 @@ static int dp_force_sst_get(void *data, u64 *val) #if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); + /* * Force DP2 sequence without VESA certified cable. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id From b3d679803137a2ce2645628e50f2ee679ed9b648 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 14 Dec 2021 00:22:48 -0500 Subject: [PATCH 0743/2070] drm/amdkcl: add definition of DP_DPCD_REV_XX to kcl_drm_dp_helper The patch add some missing micro definition of DP_DPCD_REV_XX to drm kcl header kcl_drm_dp_helper.h to resolve some dependency case. original commit: 0597017cd1 drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper v4.16-rc7-1860-g0597017cd18d Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index d92383908edc8..ec52d89063426 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -260,5 +260,20 @@ enum drm_dp_phy { # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) #endif +/* + * v4.16-rc7-1860-g0597017cd18d + * drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper + */ + +/* DPCD Field Address Mapping */ + +/* Receiver Capability */ +#ifndef DP_DPCD_REV_14 +# define DP_DPCD_REV_10 0x10 +# define DP_DPCD_REV_11 0x11 +# define DP_DPCD_REV_12 0x12 +# define DP_DPCD_REV_13 0x13 +# define DP_DPCD_REV_14 0x14 +#endif #endif /* _KCL_DRM_DP_HELPER_H_ */ From 60cf2163a9a9bc50c93bb390f748a13c5c22999d Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 15 Dec 2021 03:25:57 -0500 Subject: [PATCH 0744/2070] drm/amdkcl: fake bitmap_alloc(), bitmap_zalloc() and bitmap_free() It's squashed by drm/amdkcl: rename the bitmap function prefix for definition conflicts drm/amdkcl: cleanup kcl_bitmap_xxx drm/amdkcl: fix test for bitmap_xxx api drm/amdkfd: Remove useless #ifdefs This patch will fix the below patch building dependency issue on some old kernels version. 1a48fbd4 drm/amdkfd: Use bitmap_zalloc() when applicable v5.13-3049-g1a48fbd4ce19 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui Reviewed-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/drm-bitmap-functions.m4 | 20 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_bitmap.h | 34 +++++++++++++ include/kcl/kcl_bitmap.h | 42 ++++++++++++++++ 8 files changed, 150 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 create mode 100644 include/kcl/backport/kcl_bitmap.h create mode 100644 include/kcl/kcl_bitmap.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 085c8a47f19c9..ca4de7dbcca7f 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o - kcl_drm_drv.o kcl_drm_simple_kms_helper.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c new file mode 100644 index 0000000000000..946b29d66408b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -0,0 +1,48 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef HAVE_BITMAP_FUNCS + +#include +#include +#include +#include + +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags) +{ + return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), + flags); +} +EXPORT_SYMBOL(kcl_bitmap_alloc); + +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags) +{ + return kcl_bitmap_alloc(nbits, flags | __GFP_ZERO); +} +EXPORT_SYMBOL(kcl_bitmap_zalloc); + +void kcl_bitmap_free(const unsigned long *bitmap) +{ + kfree(bitmap); +} +EXPORT_SYMBOL(kcl_bitmap_free); +#endif /* HAVE_BITMAP_FUNCS */ + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 344b372447d6d..372f5fdf4b89d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -72,5 +72,6 @@ #include "kcl/kcl_drm_aperture.h" #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3f7a0b1575a2f..e07b102adda5b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1054,6 +1054,9 @@ /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 +/* bitmap_free() is available */ +#define HAVE_BITMAP_FUNCS 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 new file mode 100644 index 0000000000000..c5a71aac5af1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit c42b65e363ce introduce this change +dnl # v4.17-3-gc42b65e363ce +dnl # bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_free(NULL); + bitmap_alloc(0, 0); + bitmap_zalloc(0, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_FUNCS, + 1, + [bitmap_free(),bitmap_alloc(),bitmap_zalloc is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 29fa620e0df37..12b1fbd22cda4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -135,6 +135,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI + AC_AMDGPU_DRM_BITMAP_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_bitmap.h b/include/kcl/backport/kcl_bitmap.h new file mode 100644 index 0000000000000..5871f13aff831 --- /dev/null +++ b/include/kcl/backport/kcl_bitmap.h @@ -0,0 +1,34 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_BITMAP_H_ +#define __KCL_BACKPORT_KCL_BITMAP_H_ + +#include +#include + +#ifndef HAVE_BITMAP_FUNCS +#define bitmap_alloc kcl_bitmap_alloc +#define bitmap_zalloc kcl_bitmap_zalloc +#define bitmap_free kcl_bitmap_free +#endif /* HAVE_BITMAP_FUNCS */ + +#endif /* KCL_BITMAP_H */ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h new file mode 100644 index 0000000000000..f65fa8fbcc56d --- /dev/null +++ b/include/kcl/kcl_bitmap.h @@ -0,0 +1,42 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef KCL_BITMAP_H +#define KCL_BITMAP_H + +#ifndef HAVE_BITMAP_FUNCS +/* Copied from include/linux/bitmap.h*/ + +/* + * v4.17-3-gc42b65e363ce + * bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() + */ + +/* + * Allocation and deallocation of bitmap. + * Provided in lib/bitmap.c to avoid circular dependency. + */ +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags); +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags); +void kcl_bitmap_free(const unsigned long *bitmap); +#endif /* HAVE_BITMAP_FUNCS */ + +#endif /* KCL_BITMAP_H */ From de8431ad681793a406d91aabb78cb3c67ae6da2a Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Fri, 17 Dec 2021 10:42:35 -0500 Subject: [PATCH 0745/2070] drm/amdkcl: Remove REMAKE_INITRD from dkms This is deprecated and causes issues during installation of the amdgpu-dkms package on RHEL. For manual testing, please use dracut manually to regenerate initrd. Fixes SWDEV-315476 SWDEV-314875 Signed-off-by: Jeremy Newton Change-Id: If2ab6bf7d00aa2689ffe543134e1291b0b95f5da --- drivers/gpu/drm/amd/dkms/dkms.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 7a6075f32cb5a..146f1b4db6148 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,7 +1,6 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -REMAKE_INITRD="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" # not work with RHEL DKMS From c33a87703cf22956405b0b2ed8a65686da147a86 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 27 Dec 2021 21:50:08 -0500 Subject: [PATCH 0746/2070] drm/amdkcl/dkms: remove the duplicated amdgpu_amdkfd_gpuvm_pin_bo call The patch fix the amdgpu bo released twice kernel warning [ 604.329614] Workqueue: kfd_process_wq kfd_process_wq_release [amdgpu] [ 604.329752] RIP: 0010:ttm_bo_release+0x2f6/0x320 [amdttm] [ 604.329757] Code: e8 2f 68 e8 d4 e9 9e fd ff ff 48 8b 7b 94 b9 4c 1d 00 00 31 d2 be 01 00 00 00 e8 65 23 36 00 48 8b 7b e4 eb 9d 4c 89 e7 eb 98 <0f> 0b e9 2e fd ff ff e8 6e 60 e8 d4 e9 ed fe ff ff be 03 00 00 00 [ 604.329758] RSP: 0018:ffffaebec0c8fc40 EFLAGS: 00010202 [ 604.329759] RAX: 0000000000000001 RBX: ffff971f8716adbc RCX: 0000000080400039 [ 604.329760] RDX: 0000000000000001 RSI: 0000000080400039 RDI: ffff971f8716adbc [ 604.329761] RBP: ffffaebec0c8fc68 R08: ffff971f8716adbc R09: ffffffffc053b900 [ 604.329762] R10: ffff971fee794540 R11: 0000000000000001 R12: ffff971f93c65368 [ 604.329762] R13: ffff971f8db13038 R14: ffff971f8716ac58 R15: dead000000000100 [ 604.329763] FS: 0000000000000000(0000) GS:ffff97268edc0000(0000) knlGS:0000000000000000 [ 604.329764] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 604.329765] CR2: 0000000620cdc258 CR3: 000000051c610005 CR4: 00000000003706e0 [ 604.329766] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 604.329767] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 604.329767] Call Trace: [ 604.329769] amdttm_bo_put+0x30/0x50 [amdttm] [ 604.329772] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 604.329856] amdgpu_gem_object_free+0x8c/0x160 [amdgpu] [ 604.329939] drm_gem_object_free+0x1d/0x30 [drm] [ 604.329956] amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x35e/0x3b0 [amdgpu] [ 604.330071] ? preempt_schedule_common+0x18/0x30 [ 604.330074] kfd_process_device_free_bos+0xda/0x120 [amdgpu] [ 604.330183] kfd_process_wq_release+0x2a4/0x360 [amdgpu] [ 604.330289] process_one_work+0x220/0x3c0 [ 604.330291] worker_thread+0x4d/0x3f0 [ 604.330292] ? process_one_work+0x3c0/0x3c0 [ 604.330293] kthread+0x12b/0x150 [ 604.330295] ? set_kthread_struct+0x40/0x40 [ 604.330297] ret_from_fork+0x22/0x30 [ 604.330300] ---[ end trace acd84dcb8e491ccb ]--- It was caused by below commit deffdd3f09 drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain v5.13-2965-gdeffdd3f0971 Signed-off-by: Perry Yuan Reviewed-by: Guchun Chen Change-Id: Ica29a250dae065f9999803d94f858f8dda6840aa --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c609b611ab130..c4eb5f4dc9b93 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1941,17 +1941,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (offset) *offset = amdgpu_bo_mmap_offset(bo); - if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | - KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { - ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); - if (ret) { - pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_pin_bo; - } - bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; - bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; - } - return 0; allocate_init_user_pages_failed: From 3c2317dc27be1279b64ccd89b40283b47317e4a6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Dec 2021 12:26:09 +0800 Subject: [PATCH 0747/2070] drm/amdkcl: refactor code for drm_aperture.h Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 5 +++-- drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/header/drm/drm_aperture.h | 9 +++++++++ include/kcl/kcl_drm_aperture.h | 4 ++-- 5 files changed, 14 insertions(+), 21 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 create mode 100644 include/kcl/header/drm/drm_aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index 99c29f3b4c803..f91a4d60ffd11 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_APERTURE +#ifndef HAVE_DRM_APERTURE_H + #include #include #include @@ -142,4 +143,4 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const } EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); -#endif /* HAVE_DRM_APERTURE */ +#endif /* HAVE_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 deleted file mode 100644 index 532e9149653c9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 2916059147ea38f76787d7b38dee883da2e9def2 -dnl # drm/aperture: Add infrastructure for aperture ownership -dnl # -AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_aperture_remove_conflicting_pci_framebuffers(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_APERTURE, 1, - [drm_aperture_remove_* is availablea]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 12b1fbd22cda4..baddbf8f99b2e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -112,7 +112,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON - AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_AMDGPU_DRM_DISPLAY_INFO AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL diff --git a/include/kcl/header/drm/drm_aperture.h b/include/kcl/header/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/include/kcl/header/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h index 5c402e251a5d9..e1af88ce1ba85 100644 --- a/include/kcl/kcl_drm_aperture.h +++ b/include/kcl/kcl_drm_aperture.h @@ -2,7 +2,7 @@ #ifndef KCL_KCL_DRM_APERTURE_H #define KCL_KCL_DRM_APERTURE_H -#ifndef HAVE_DRM_APERTURE +#ifndef HAVE_DRM_DRM_APERTURE_H #include @@ -20,6 +20,6 @@ int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); -#endif /* HAVE_DRM_APERTURE */ +#endif /* HAVE_DRM_DRM_APERTURE_H */ #endif From 8b6a23ad836e168bb241698e07b930ed49e4d663 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Wed, 5 Jan 2022 13:33:44 -0500 Subject: [PATCH 0748/2070] drm/amdgpu: Re-enable GFX RAS by default This was disabled due to issues on A+A but these have been addressed. Re-enable GFX RAS by default and remove the requirement on ras_mask=0xe Signed-off-by: Kent Russell Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e4de7d4d32d2f..a89f34efd15f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4147,14 +4147,9 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); - /* This is temporary workaround to leverage ras_mask - * to allow nable GFX RAS manually. Should be removed later - */ - if (amdgpu_ras_enable && - (amdgpu_ras_mask == 0xe)) - adev->ras_hw_enabled |= 1 << AMDGPU_RAS_BLOCK__GFX; + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | + 1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } /* apply asic specific settings (vega20 only for now) */ From 95595b1002210ec55cd80f689c3f85f672518931 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 20 Dec 2021 16:06:19 -0500 Subject: [PATCH 0749/2070] drm/amdkfd: switch debugger asic type checks to ip version checks The rest of the driver now uses IP version checks so have the debugger code do the same. Signed-off-by: Jonathan Kim Reviewed-by: Graham Sider --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index d823e7512a347..610702f70c124 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -595,12 +595,14 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } - if ((kfd->adev->asic_type == CHIP_VEGA10 - && kfd->mec2_fw_version < 0x81b6) - || (kfd->adev->asic_type >= CHIP_VEGA12 - && kfd->adev->asic_type <= CHIP_RAVEN - && kfd->mec2_fw_version < 0x1b6) - || (kfd->adev->asic_type == CHIP_ARCTURUS + if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) + && kfd->mec2_fw_version < 0x81b6) || + (KFD_GC_VERSION(kfd) >= IP_VERSION(9, 1, 0) + && KFD_GC_VERSION(kfd) <= IP_VERSION(9, 2, 2) + && kfd->mec2_fw_version < 0x1b6) || + (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) + && kfd->mec2_fw_version < 0x1b6) || + (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) && kfd->mec2_fw_version < 0x30)) kfd->gws_debug_workaround = true; From 993b104b0e03d75031aeafe3a3a76363a9da235f Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 5 Jan 2022 20:54:22 -0600 Subject: [PATCH 0750/2070] drm/amdkcl: test for full HMM support in kernel Make sure HMM is fully supported in the current kernel version. Some Kernels that were HMM back ported, have missing implementation. Ex. RHEL 8.5 with Kernel 4.18. Signed-off-by: Alex Sierra Suggested-by: Flora Cui Acked-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index c175fd6289702..72147cbe68a28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ ]) dnl # +dnl # v5.1-10231-gbf198b2b34bf: mm/mmu_notifier: pass down vma and reasons why mmu notifier is happening dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 @@ -53,10 +54,14 @@ AC_DEFUN([AC_AMDGPU_HMM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ], [ #ifdef CONFIG_HMM_MIRROR struct hmm_range *range = NULL; + struct mmu_notifier_range *mmu_range = NULL; + range->notifier = NULL; + mmu_range->vma = NULL; #else #error CONFIG_HMM_MIRROR not enabled #endif From abe8514fa555863fa36832980d89754771fab0b4 Mon Sep 17 00:00:00 2001 From: majun Date: Wed, 12 Jan 2022 14:16:44 +0800 Subject: [PATCH 0751/2070] drm/amdkcl: Fix the compile error caused by struct kobj_type The patch (drm/amdgpu: use default_groups in kobj_type) introduced a new member "default_groups" in struct kobj_type. To fix the compile errors cuased by this patch, a new kcl macro is added. Reviewed-by: Guchun Chen Signed-off-by: majun Change-Id: If536c7cddfafd17be652a7f15cb68f2e7b4a80d4 --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_kobj_type.m4 | 19 +++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 08731d4be1776..9375e3f647848 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -407,7 +407,9 @@ static struct attribute *amdgpu_xgmi_hive_attrs[] = { &amdgpu_xgmi_hive_id, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); +#endif static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, struct attribute *attr, char *buf) @@ -440,7 +442,11 @@ static const struct sysfs_ops amdgpu_xgmi_hive_ops = { static const struct kobj_type amdgpu_xgmi_hive_type = { .release = amdgpu_xgmi_hive_release, .sysfs_ops = &amdgpu_xgmi_hive_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = amdgpu_xgmi_hive_groups, +#else + .default_attrs = amdgpu_xgmi_hive_attrs, +#endif }; static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e07b102adda5b..30b58c1a8b952 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1072,6 +1072,9 @@ /* __print_array is available */ #define HAVE___PRINT_ARRAY 1 +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index baddbf8f99b2e..c6569f9660023 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -135,6 +135,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS + AC_AMDGPU_STRUCT_KOBJ_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 new file mode 100644 index 0000000000000..a698f80362f2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit aa30f47cf666111f6bbfd15f290a27e8a7b9d854 +dnl # kobject: Add support for default attribute groups to kobj_type +dnl # + +AC_DEFUN([AC_AMDGPU_STRUCT_KOBJ_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct kobj_type *k_type = NULL; + k_type->default_groups = NULL; + ],[ + AC_DEFINE(HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE, 1, + [kobj_type->default_groups is available]) + ],[ + ]) + ]) +]) From 10e1ca1e421ac340c87f96f2c2f22e0ed8e42496 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 18 Jan 2022 02:06:39 -0500 Subject: [PATCH 0752/2070] drm/amdkcl: Fix for CAP_CHECKPOINT_RESTORE not defined Fix for CAP_CHECKPOINT_RESTORE not defined on kernels before 5.9 Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_capability.h | 31 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/kcl/kcl_capability.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 372f5fdf4b89d..75df94b147761 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -73,5 +73,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h new file mode 100644 index 0000000000000..2cc984db5ac19 --- /dev/null +++ b/include/kcl/kcl_capability.h @@ -0,0 +1,31 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _KCL_KCL_CAPABILITY_H +#define _KCL_KCL_CAPABILITY_H + +#include + +#ifndef CAP_CHECKPOINT_RESTORE +#define CAP_CHECKPOINT_RESTORE CAP_SYS_ADMIN +#endif + +#endif From e4ff9c036fa7cc2a7ae4aa80aeae170dd62ac52b Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 18 Jan 2022 02:06:40 -0500 Subject: [PATCH 0753/2070] drm/amdkcl: fix for close_fd not defined Use ksys_close instead of close_fd on older kernels Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling (rajneesh: removed new line EOF warning) Signed-off-by: Rajneesh Bhardwaj Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 | 15 +++++++++++++++ include/kcl/kcl_fdtable.h | 10 ++++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 create mode 100644 include/kcl/kcl_fdtable.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 75df94b147761..3dba6356cadd8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -74,5 +74,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 30b58c1a8b952..99efdaeecc0cf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1075,6 +1075,9 @@ /* kobj_type->default_groups is available */ #define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c6569f9660023..42e051506b41c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -136,6 +136,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_CLOSE_FD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 new file mode 100644 index 0000000000000..59eb3c9632fdc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit 8760c909f54a82aaa6e76da19afe798a0c77c3c3 +dnl # file: Rename __close_fd to close_fd and remove the files parameter +dnl # +AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + close_fd(0); + ], [ + AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_fdtable.h b/include/kcl/kcl_fdtable.h new file mode 100644 index 0000000000000..0a4b97605e146 --- /dev/null +++ b/include/kcl/kcl_fdtable.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_FDTABLE_H +#define _KCL_FDTABLE_H + +#ifndef HAVE_KERNEL_CLOSE_FD +#include +#define close_fd ksys_close +#endif + +#endif From 4e19ca7962e8bf3950bb286c08f0a7ebdf6a99a6 Mon Sep 17 00:00:00 2001 From: majun Date: Wed, 19 Jan 2022 19:28:44 +0800 Subject: [PATCH 0754/2070] drm/amdkcl: Fix the compile bug of ksys_close missing Fix the bug caused by ksys_close missing in some kernels. Reviewed-by: Flora Cui Signed-off-by: majun Change-Id: Ibc94fdac9392b642f1f748c1dacff076f524a8ce --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 | 12 ++++++++++++ include/kcl/kcl_fdtable.h | 4 ++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 99efdaeecc0cf..a4a4dd45044b3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1078,6 +1078,9 @@ /* close_fd() is available */ #define HAVE_KERNEL_CLOSE_FD 1 +/* ksys_close() is available */ +#define HAVE_KSYS_CLOSE_FD 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 index 59eb3c9632fdc..82b1e366bd09a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -10,6 +10,18 @@ AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ close_fd(0); ], [ AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ], [ + dnl # + dnl # commit 16a78543a1d3537645de737934b9387c42bfb53b + dnl # drm/amdkcl: fix for close_fd not defined + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_close(0); + ], [ + AC_DEFINE(HAVE_KSYS_CLOSE_FD, 1, [ksys_fd() is available]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_fdtable.h b/include/kcl/kcl_fdtable.h index 0a4b97605e146..f6829418719c5 100644 --- a/include/kcl/kcl_fdtable.h +++ b/include/kcl/kcl_fdtable.h @@ -4,7 +4,11 @@ #ifndef HAVE_KERNEL_CLOSE_FD #include +#ifdef HAVE_KSYS_CLOSE_FD #define close_fd ksys_close +#else +#define close_fd sys_close +#endif #endif #endif From 4c8907d3c5d8972b654792fc6ade165bf75f84a7 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 19 Jan 2022 10:34:09 -0500 Subject: [PATCH 0755/2070] drm/amdkfd: Fix ipc_import_handle to use user_gpu_id Change kfd_ioctl_ipc_import_handle to use user_gpu_id. When a process is checkpointed and restored using CRIU on a different server, pdd->dev->id could be different on the restored server. So we use pdd->user_gpu_id as it remains the same throughout the life of kfd_process. Reviewed-by: Rajneesh Bhardwaj Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 538e4c5edfe14..2983923985a0f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1695,14 +1695,16 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, void *data) { struct kfd_ioctl_ipc_import_handle_args *args = data; - struct kfd_dev *dev = NULL; + struct kfd_process_device *pdd; int r; - dev = kfd_device_by_id(args->gpu_id); - if (!dev) + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) return -EINVAL; - r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, + r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, &args->mmap_offset, &args->flags); if (r) From 987727d7f99ed7656eea2d70fa3ee4789e383176 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 20 Jan 2022 14:59:05 +0800 Subject: [PATCH 0756/2070] drm/amdkcl: defer to enable generic FB setup by drm version >=5.15 This is workaround, and will be dropped when rooting cause it. Below are the collected failures from drm_fb_helper_damage_work on different kernels. In 5.13.0-27-generic kernel: amdgpu 0000:03:00.0: Damage blitter failed: ret=-22 In 5.13.0-22-generic: BUG: unable to handle page fault for address: 0000000100000008 Signed-off-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_drm_fb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 1e29f3cd082f0..858fc68db807f 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -30,7 +30,7 @@ #endif #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ - DRM_VERSION_CODE >= DRM_VERSION(5, 13, 0) + DRM_VERSION_CODE >= DRM_VERSION(5, 15, 0) #define AMDKCL_DRM_FBDEV_GENERIC #endif From ba3aabfaf428b4bc13e9bafb74886ed5be501ab5 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:49:29 +0800 Subject: [PATCH 0757/2070] drm/amdkcl: Resolve build issue with kcl_amdgpu_get_vblank_time_ns Fix incompatible pointer type passed as argument 1 of 'drm_crtc_vblank_count_and_time'. Access time field of drm_vblank_crtc structure depending on the field type, defined by HAVE_DRM_VBLANK_USE_KTIME_T or HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD. v2: merge tests for drm_vblank_crtc->time, drop checking if drm_vblank_struct exists and fix test for checking if time is array based on test on centos7.3 v3: switch HAVE_DRM_VBLANK_USE_KTIME_T to be tested first and unset HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD Signed-off-by: Danijel Slivka Reviewed-by: Flora Cui Signed-off-by: Asher Song --- .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 12 ++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../m4/drm_vblank_use_ktime_t_time_field.m4 | 20 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 2 insertions(+), 34 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index a799268fb1754..33bf87c0568bd 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -44,17 +44,9 @@ static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, u } #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ -#if defined(HAVE_DRM_VBLANK_USE_KTIME_T) -static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) +{ return vblank->time; } -#else -static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { - struct timeval tv; - drm_crtc_vblank_count_and_time(vblank, &tv); - return timeval_to_ktime(tv); -} -#endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ - #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a4a4dd45044b3..9ed0faf190928 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -362,9 +362,6 @@ /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 -/* drm_driver->release() is available */ -#define HAVE_DRM_DRIVER_RELEASE 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 deleted file mode 100644 index b846cb2f57a41..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval -AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - #include - ], [ - struct drm_vblank_crtc *vblank = NULL; - vblank->time = ns_to_ktime(0); - ], [ - AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, - [drm_vblank->time uses ktime_t type]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 42e051506b41c..675cb82f3a50f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -127,7 +127,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV - AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP From f79ff4b9af9d0bacfe1c812aa6efe5a3fc7cee07 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Jan 2022 19:38:00 +0800 Subject: [PATCH 0758/2070] drm/amdkcl: fix macro name error Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index f91a4d60ffd11..c81b1cadf0099 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_APERTURE_H +#ifndef HAVE_DRM_DRM_APERTURE_H #include #include From a16bdeb0479accc37c508d815a1fa127c5e8c7ca Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Jan 2022 19:42:09 +0800 Subject: [PATCH 0759/2070] drm/amdkcl: no need to export remove_conflicting_pci_framebuffers it's not used by amdgpu Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 18f2a20d821da..42cb82d7db3e2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -79,5 +79,4 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const } #endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ -EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif From f51a911344cf3202f8b73bb01800b3b58e66b6e2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 14:01:56 +0800 Subject: [PATCH 0760/2070] drm/amdkcl: include drm_ttm_helper.ko into dkms package Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 8 ++++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 4 ++++ drivers/gpu/drm/amd/dkms/sources | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index a5a39207c730e..6cc9587ebc525 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 340258b04f0aa..e7b791c8195f0 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -186,4 +186,12 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x endif endif +export CONFIG_DRM_TTM_HELPER=m +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o + obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 146f1b4db6148..bd79232132f60 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -22,6 +22,10 @@ BUILT_MODULE_NAME[3]="amd-sched" BUILT_MODULE_LOCATION[3]="scheduler" DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" +BUILT_MODULE_NAME[4]="amddrm_ttm_helper" +BUILT_MODULE_LOCATION[4]="." +DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" + # Find out how many CPU cores can be use if we pass appropriate -j option to make. # DKMS could use all cores on multicore systems to build the kernel module. num_cpu_cores() diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index da9e9612a23fb..60563cf6abf8e 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -29,3 +29,5 @@ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ include/uapi/linux/kfd_sysfs.h include/uapi/linux/ +drivers/gpu/drm/drm_gem_ttm_helper.c . +include/drm/drm_gem_ttm_helper.h include/drm/ From c2d3cd00309da0f596dccefc1f38bb58b6a3cd00 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 25 Jan 2022 10:24:15 +0800 Subject: [PATCH 0761/2070] drm/amdkcl: add kcl copy of drm_printf_indent Signed-off-by: Flora Cui --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 6dea17070b5de..3c4e6b62a6e15 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -159,4 +159,10 @@ static inline bool drm_debug_enabled(unsigned int category) } #endif /* HAVE_DRM_DEBUG_ENABLED */ +/* Copied from v4.14-rc3-610-gbf6234a294c5 include/drm/drm_print.h */ +#ifndef drm_printf_indent +#define drm_printf_indent(printer, indent, fmt, ...) \ + drm_printf((printer), "%.*s" fmt, (indent), "\t\t\t\t\tX", ##__VA_ARGS__) +#endif + #endif From c665be7a5e5d38436acebc5c72eb0ad10e4515d9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 25 Jan 2022 11:44:18 +0800 Subject: [PATCH 0762/2070] drm/amdkcl: add kcl copy drm_print_bits Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 25 +++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 | 26 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 3 +- drivers/gpu/drm/ttm/backport/backport.h | 2 +- include/kcl/backport/kcl_drm_print.h | 51 +++++++++++++++++++ include/kcl/kcl_drm_print.h | 5 ++ 9 files changed, 118 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 create mode 100644 include/kcl/backport/kcl_drm_print.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index b5d9e1a9113a3..907a902c5f204 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -23,6 +23,7 @@ * Rob Clark */ #include +#include #include #if !defined(HAVE_DRM_DRM_PRINT_H) @@ -102,3 +103,27 @@ void kcl_drm_err(const char *format, ...) EXPORT_SYMBOL(kcl_drm_err); #endif + +#ifndef HAVE_DRM_PRINT_BITS +/* Copied from v5.3-rc1-684-g141f6357f45c drivers/gpu/drm/drm_print.c */ +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + bool first = true; + unsigned int i; + + if (WARN_ON_ONCE(nbits > BITS_PER_TYPE(value))) + nbits = BITS_PER_TYPE(value); + + for_each_set_bit(i, &value, nbits) { + if (WARN_ON_ONCE(!bits[i])) + continue; + drm_printf(p, "%s%s", first ? "" : ",", + bits[i]); + first = false; + } + if (first) + drm_printf(p, "(none)"); +} +EXPORT_SYMBOL(drm_print_bits); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3dba6356cadd8..92d2aabbce2e6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -40,7 +40,7 @@ #endif #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9ed0faf190928..a9324217ab08d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -587,6 +587,12 @@ /* drm_printer->prefix is available */ #define HAVE_DRM_PRINTER_PREFIX 1 +/* drm_print_bits() is available */ +#define HAVE_DRM_PRINT_BITS 1 + +/* drm_print_bits() has 4 args */ +#define HAVE_DRM_PRINT_BITS_4ARGS 1 + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 new file mode 100644 index 0000000000000..62209f24b90e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.3-rc1-684-g141f6357f45c +dnl # drm: tweak drm_print_bits() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_print_bits(NULL, 0, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS_4ARGS, 1, + [drm_print_bits() has 4 args]) + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ], [ + dnl # v5.3-rc1-622-g2dc5d44ccc5e + dnl # drm: add drm_print_bits + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_print_bits], + [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 675cb82f3a50f..dc3feceea4e2e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -60,6 +60,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_PRINTER + AC_AMDGPU_DRM_PRINT_BITS AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 6ca5e362390fd..de169d5752a83 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -5,5 +5,6 @@ #include #include #include -#include +#include + #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 1bb8e2c0efaa4..419e528fd874c 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_print.h b/include/kcl/backport/kcl_drm_print.h new file mode 100644 index 0000000000000..379308c2563d4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_print.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ + + +// Copied from include/drm/drm_print.h +#ifndef _KCL_BACKPORT_KCL__DRM_PRINT_H__H_ +#define _KCL_BACKPORT_KCL__DRM_PRINT_H__H_ + +#include +#include + +#if !defined(HAVE_DRM_PRINT_BITS_4ARGS) && \ + defined(HAVE_DRM_PRINT_BITS) +static inline +void _kcl_drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + unsigned int from, to; + + from = ffs(value); + to = fls(value); + WARN_ON_ONCE(to > nbits); + + drm_print_bits(p, value, bits, from, nbits); +} +#define drm_print_bits _kcl_drm_print_bits +#endif + +#endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 3c4e6b62a6e15..d92e4744fea4b 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -165,4 +165,9 @@ static inline bool drm_debug_enabled(unsigned int category) drm_printf((printer), "%.*s" fmt, (indent), "\t\t\t\t\tX", ##__VA_ARGS__) #endif +#ifndef HAVE_DRM_PRINT_BITS +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits); +#endif + #endif From 22b003a1b5d06550738f60126bb7bea40e1a73e5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Jan 2022 17:04:10 +0800 Subject: [PATCH 0763/2070] drm/amdkcl: rework kcl stuff for drm_ttm_helper.ko Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +++ .../include/kcl/kcl_drm_gem_ttm_helper.h | 33 +++---------------- .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 30 ++--------------- drivers/gpu/drm/amd/dkms/config/config.h | 9 ++--- .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 33 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 ---- .../drm/amd/dkms/m4/drm_gem_object_funcs.m4 | 28 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- include/kcl/header/drm/drm_gem_ttm_helper.h | 9 ----- 10 files changed, 51 insertions(+), 109 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 delete mode 100644 include/kcl/header/drm/drm_gem_ttm_helper.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7444f1dc9aa5a..b8502fd503606 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3208,8 +3208,8 @@ static struct drm_driver amdgpu_kms_driver = { #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK - .gem_prime_vmap = drm_gem_ttm_vmap, - .gem_prime_vunmap = drm_gem_ttm_vunmap, + .gem_prime_vmap = amdgpu_gem_prime_vmap, + .gem_prime_vunmap = amdgpu_gem_prime_vunmap, #endif .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index b855f760fd1a5..c9b5ba712939c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -452,8 +452,13 @@ const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#else + .vmap = amdgpu_gem_prime_vmap, + .vunmap = amdgpu_gem_prime_vunmap, +#endif .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index e9d8d3fd9d9d8..ae25af4cbc8c5 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -1,29 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* Copied from include/drm/drm_gem_ttm_helper.h */ - #ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H #define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H #include +#include -#ifndef HAVE_DRM_GEM_TTM_VMAP -void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr); - -void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj); - -static inline -void drm_gem_ttm_vunmap(struct drm_gem_object *gem, - void *vaddr) -{ - _kcl_drm_gem_ttm_vunmap(gem, vaddr); -} - -static inline -void *drm_gem_ttm_vmap(struct drm_gem_object *obj) -{ - return _kcl_drm_gem_ttm_vmap(obj); -} +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK @@ -34,14 +19,4 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); #endif -#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK -int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma); -static inline -int drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma) { - return _kcl_drm_gem_ttm_mmap(gem, vma); -} -#endif - #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index b5fb22fa5a50a..2cef03209d156 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -14,8 +14,8 @@ container_of(gem_obj, struct ttm_buffer_object, base) #endif -#ifndef HAVE_DRM_GEM_TTM_VMAP -void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); struct dma_buf_map map; @@ -23,9 +23,8 @@ void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) ttm_bo_vmap(bo, &map); return map.vaddr; } -EXPORT_SYMBOL(_kcl_drm_gem_ttm_vmap); -void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); @@ -36,27 +35,4 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, ttm_bo_vunmap(bo, &map); } -EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); -#endif - -#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK -int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma) { - - struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - int ret; - - ret = ttm_bo_mmap_obj(vma, bo); - if (ret < 0) - return ret; - - /* - * ttm has its own object refcounting, so drop gem reference - * to avoid double accounting counting. - */ - drm_gem_object_put(gem); - - return 0; -} -EXPORT_SYMBOL(_kcl_drm_gem_ttm_mmap); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a9324217ab08d..9bcdc759d3fa5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -402,9 +402,6 @@ */ #define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_GEM_TTM_HELPER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 @@ -490,6 +487,9 @@ /* drm_gem_map_attach() wants 2 arguments */ /* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ +/* drm_gem_object_funcs->vmap() has 2 args */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 + /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 @@ -502,9 +502,6 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gem_ttm_vmap() is available */ -#define HAVE_DRM_GEM_TTM_VMAP 1 - /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 new file mode 100644 index 0000000000000..cb583a5e9dafd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -0,0 +1,33 @@ +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # commit v5.10-rc2-329-g49a3f51dfeee + dnl # drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + funcs->vmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS, 1, [drm_gem_object_funcs->vmap() has 2 args]) + ],[ + dnl # commit v5.9-rc5-1077-gd693def4fd1c + dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 05687ebbd1ec7..b3b69a3e8dea7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -39,13 +39,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) - dnl # - dnl # v5.3-rc1-623-gff540b76f14a - dnl # drm/ttm: add drm gem ttm helpers, - dnl # starting with drm_gem_ttm_print_info() - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) - dnl # dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro dnl # diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 deleted file mode 100644 index 353a678db52d7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 +++ /dev/null @@ -1,28 +0,0 @@ -dnl # -dnl # commit v4.9-rc8-1739-g6d1b81d8e25d -dnl # drm: add crtc helper drm_crtc_from_index() -dnl # commit v5.9-rc5-1077-gd693def4fd1c -dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_TTM_VMAP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_ttm_vmap], [drivers/gpu/drm/drm_gem_ttm_helper.c], [ - AC_DEFINE(HAVE_DRM_GEM_TTM_VMAP, 1, [drm_gem_ttm_vmap() is available]) - ],[ - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - ],[ - struct drm_driver *drv = NULL; - drv->gem_open_object = NULL; - ],[ - AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, - [drm_gem_open_object is defined in struct drm_drv]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dc3feceea4e2e..041f5de11ff63 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -100,7 +100,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS - AC_AMDGPU_DRM_GEM_TTM_VMAP + AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_SYSFS_EMIT diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h deleted file mode 100644 index 5612902e4958d..0000000000000 --- a/include/kcl/header/drm/drm_gem_ttm_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ -#define _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ - -#ifdef HAVE_DRM_DRM_GEM_TTM_HELPER_H -#include_next -#endif - -#endif From 7cd9f76f4177cd86dab73e9e8ac3c14d74937e3b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 15:29:52 +0800 Subject: [PATCH 0764/2070] drm/amdkcl: drop trict restriction for drm_fbdev_generic_setup Signed-off-by: Flora Cui --- include/kcl/backport/kcl_drm_fb.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 858fc68db807f..b2b3277a94e33 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -29,8 +29,7 @@ #define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers #endif -#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ - DRM_VERSION_CODE >= DRM_VERSION(5, 15, 0) +#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) #define AMDKCL_DRM_FBDEV_GENERIC #endif From cf178f8a6034fce4c62d89ee69335a62742816d3 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 31 Jan 2022 22:10:31 -0500 Subject: [PATCH 0765/2070] drm/amdkfd: CRIU Update attributes during resume KFD_IOCTL_SVM_ATTR_CLR_FLAGS is not available for querying via get_attr interface but we must clear the flags during restore as there might be some default flags set when the prange is created. Also fix for invalid PREFETCH atribute values saved during checkpoint by replacing them with another dummy KFD_IOCTL_SVM_ATTR_SET_FLAGS attribute. Change-Id: Ibbe573ac5d7cffee80e08668d829b46f6b6aa688 Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index f79b4ebbda6a5..9f2eff1f0fb94 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -4087,6 +4087,24 @@ int kfd_criu_resume_svm(struct kfd_process *p) set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; set_attr[num_attrs].value = ~set_flags; + /* CLR_FLAGS is not available via get_attr during checkpoint but + * it needs to be inserted before restoring the ranges so + * allocate extra space for it before calling set_attr + */ + set_attr_size = sizeof(struct kfd_ioctl_svm_attribute) * + (num_attrs + 1); + set_attr = krealloc(set_attr, set_attr_size, + GFP_KERNEL); + if (!set_attr) { + ret = -ENOMEM; + goto exit; + } + + memcpy(set_attr, criu_svm_md->data.attrs, num_attrs * + sizeof(struct kfd_ioctl_svm_attribute)); + set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; + set_attr[num_attrs].value = ~set_flags; + ret = svm_range_set_attr(p, mm, criu_svm_md->data.start_addr, criu_svm_md->data.size, num_attrs + 1, set_attr); From c5e9985d50ee701744804044474dbac2ab8c7125 Mon Sep 17 00:00:00 2001 From: majun Date: Fri, 28 Jan 2022 11:53:21 +0800 Subject: [PATCH 0766/2070] drm/amdkcl: Check if pm_suspend_target_state is defined Fixed the compile error caused by pm_suspend_target_state which is not defined in some legacy kernel versions. v3: - Fix the wrong return value v2: - Modify the patch subject - Fix the return value for APU Signed-off-by: majun Change-Id: Idc26e7045132b61130d9cc9e555729c85ae238b6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/pm_suspend_target_state.m4 | 17 +++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 02d5abf9df2ba..37a4adb12b761 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1540,8 +1540,12 @@ void amdgpu_acpi_release(void) */ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return !(adev->flags & AMD_IS_APU) || (pm_suspend_target_state == PM_SUSPEND_MEM); +#else + return true; +#endif } /** @@ -1553,9 +1557,13 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) */ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE if (!(adev->flags & AMD_IS_APU) || (pm_suspend_target_state != PM_SUSPEND_TO_IDLE)) return false; +#else + return false; +#endif if (adev->asic_type < CHIP_RAVEN) return false; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9bcdc759d3fa5..61c2c1f01c1ad 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1081,6 +1081,9 @@ /* ksys_close() is available */ #define HAVE_KSYS_CLOSE_FD 1 +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 new file mode 100644 index 0000000000000..7f4394902241d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit edf3ad32f18b0ea7d27ea9420f3bb9b2c850b48b +dnl # drm/amd: Warn users about potential s0ix problems +dnl # +AC_DEFUN([AC_AMDGPU_PM_SUSPEND_TARGET_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_suspend_target_state = PM_SUSPEND_TO_IDLE; + ],[ + AC_DEFINE(HAVE_PM_SUSPEND_TARGET_STATE, + 1, + [pm_suspend_target_state is available]) + ]) + ]) +]) From 3a8339bfa26855e9aa93395603ac3d381fbec50b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 6 Jan 2022 12:39:56 +0800 Subject: [PATCH 0767/2070] drm/amdkcl: wrap the code under macro CONFIG_DRM_LEGACY The following patch hides the DRM midlayer behind CONFIG_DRM_LEGACY c1736b9008cb "drm: IRQ midlayer is now legacy" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b8502fd503606..96e64b4044b64 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3171,7 +3171,9 @@ static struct drm_driver amdgpu_kms_driver = { .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, #endif +#ifdef CONFIG_DRM_LEGACY .irq_handler = amdgpu_irq_handler, +#endif .ioctls = amdgpu_ioctls_kms, #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_free_object_unlocked = amdgpu_gem_object_free, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 35d3449fb1af4..fed9902c95c0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -197,7 +197,10 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev) * Returns: * result of handling the IRQ, as defined by &irqreturn_t */ -static irqreturn_t amdgpu_irq_handler(int irq, void *arg) +#ifndef CONFIG_DRM_LEGACY +static +#endif +irqreturn_t amdgpu_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; struct amdgpu_device *adev = drm_to_adev(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index af72405a72262..3633019100867 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -122,6 +122,9 @@ enum interrupt_node_id_per_aid { extern const int node_id_to_phys_map[NODEID_MAX]; void amdgpu_irq_disable_all(struct amdgpu_device *adev); +#ifdef CONFIG_DRM_LEGACY +irqreturn_t amdgpu_irq_handler(int irq, void *arg); +#endif int amdgpu_irq_init(struct amdgpu_device *adev); void amdgpu_irq_fini_sw(struct amdgpu_device *adev); From 24738893c3c9aadf294ce2582cd420f7a5de414c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 14 Jan 2022 16:03:54 +0800 Subject: [PATCH 0768/2070] drm/amdkcl: test whether struct drm_vma_offset_node has member readonly This is cause by f425821b946847282708121600fffc20344183a0 "drm/vma: Add a driver_private member to vma_node." v5.13-rc3-1382-gf425821b9468 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 2 ++ .../m4/drm-vma-offset-node-readonly-field.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c index 328395cbd0125..359099cb8af9e 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -121,6 +121,7 @@ int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { return -EACCES; } +#ifdef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD if (node->readonly) { if (vma->vm_flags & VM_WRITE) { drm_gem_object_put(obj); @@ -129,6 +130,7 @@ int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { vma->vm_flags &= ~VM_MAYWRITE; } +#endif ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, vma); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 new file mode 100644 index 0000000000000..06ca73cc0fe91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-rc3-1382-gf425821b9468 +dnl # drm/vma: Add a driver_private member to vma_node. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vma_offset_node *node = NULL; + node->readonly = false; + ], [ + AC_DEFINE(HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD, 1, [struct drm_vma_offset_node has readonly field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 041f5de11ff63..3852eb45fa7cc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -137,6 +137,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD + AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From f973eee4fdd59180f37ec9db3265d81b2cbd6ec1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 10:34:10 +0800 Subject: [PATCH 0769/2070] drm/amdkcl: Test whether ww_mutex_trylock() has context argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 | 16 ++++++++++ include/kcl/backport/kcl_ww_mutex.h | 29 +++++++++++++++++++ include/kcl/kcl_dma-resv.h | 1 + 5 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 create mode 100644 include/kcl/backport/kcl_ww_mutex.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 61c2c1f01c1ad..beee928217687 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1048,6 +1048,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* ww_mutex_trylock() has context arg */ +#define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 + /* is_device_page is available */ /* #undef HAVE_ZONE_DEVICE_PUBLIC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3852eb45fa7cc..f61fa40461817 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -138,6 +138,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD + AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 new file mode 100644 index 0000000000000..e3018a1b798e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.15-rc1-1-g12235da8c80a +dnl # kernel/locking: Add context to ww_mutex_trylock() +dnl # +AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int r = ww_mutex_trylock(NULL, NULL); + ], [ + AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, + [ww_mutex_trylock() has context arg]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_ww_mutex.h b/include/kcl/backport/kcl_ww_mutex.h new file mode 100644 index 0000000000000..101a5b8aacafa --- /dev/null +++ b/include/kcl/backport/kcl_ww_mutex.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Wound/Wait Mutexes: blocking mutual exclusion locks with deadlock avoidance + * + * Original mutex implementation started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar + * + * Wait/Die implementation: + * Copyright (C) 2013 Canonical Ltd. + * Choice of algorithm: + * Copyright (C) 2018 WMWare Inc. + * + * This file contains the main data structure and API definitions. + */ +#ifndef __KCL_BACKPORT_KCL_WW_MUTEX_H__ +#define __KCL_BACKPORT_KCL_WW_MUTEX_H__ + +#include + +#ifndef HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG +static inline int _kcl_ww_mutex_trylock(struct ww_mutex *lock) +{ + return ww_mutex_trylock(lock); +} +#define ww_mutex_trylock(MUTEX, CTX) _kcl_ww_mutex_trylock(MUTEX) +#endif + +#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 680f1fe9c1757..0d0ccbbb5d043 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -48,6 +48,7 @@ #include #include +#include #include struct dma_resv_list; From f392a4f074a25aa22f56bdb80f4cc5108ca9cdca Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 12:03:59 +0800 Subject: [PATCH 0770/2070] drm/amdkcl: Test whether drm_aperture_remove_conflicting_pci_framebuffers() has drm_driver argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ ...ture-remove-conflicting-pci-framebuffers.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index c81b1cadf0099..c597046dee062 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -107,7 +107,12 @@ EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); * Returns: * 0 on success, or a negative errno code otherwise */ +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const struct drm_driver *req_driver) +#else int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +#endif { resource_size_t base, size; int bar, ret = 0; @@ -128,11 +133,15 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const #ifdef HAVE_VGA_REMOVE_VGACON #if IS_REACHABLE(CONFIG_FB) +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name); +#else #ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG ret = remove_conflicting_pci_framebuffers(pdev, name); #else ret = remove_conflicting_pci_framebuffers(pdev, 0, name); #endif +#endif /* HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ #endif if (ret == 0) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index beee928217687..ab7ab796cb97e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -130,6 +130,10 @@ /* drm_aperture_remove_* is availablea */ #define HAVE_DRM_APERTURE 1 +/* drm_aperture_remove_conflicting_pci_framebuffers() second arg is + drm_driver* */ +#define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 + /* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are available */ #define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..50cfd872b53b3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.13-rc3-1543-g97c9bfe3f660 +dnl # drm/aperture: Pass DRM driver structure instead of driver name +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct drm_driver; + ], [ + const struct drm_driver *drv = NULL; + drm_aperture_remove_conflicting_pci_framebuffers(NULL, drv); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG, 1, + [drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver*]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f61fa40461817..d2f33512c713d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From cb37a49667ff71a60482b1302220cddab646d178 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 12:41:56 +0800 Subject: [PATCH 0771/2070] drm/amdkcl: Test whether synchronize_shrinkers() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +-- drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c | 31 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/synchronize-shrinkers.m4 | 13 ++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_shrinker.h | 10 ++++++ 7 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 create mode 100644 include/kcl/kcl_shrinker.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ca4de7dbcca7f..a542ecd7cb11b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,8 +11,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c new file mode 100644 index 0000000000000..fb57e87ff981b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Swap reorganised 29.12.95, Stephen Tweedie. + * kswapd added: 7.1.96 sct + * Removed kswapd_ctl limits, and swap out as many pages as needed + * to bring the system back to freepages.high: 2.4.97, Rik van Riel. + * Zone aware kswapd started 02/00, Kanoj Sarcar (kanoj@sgi.com). + * Multiqueue VM started 5.8.00, Rik van Riel. + */ +#include + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +static DECLARE_RWSEM(shrinker_rwsem); + +/** + * synchronize_shrinkers - Wait for all running shrinkers to complete. + * + * This is equivalent to calling unregister_shrink() and register_shrinker(), + * but atomically and with less overhead. This is useful to guarantee that all + * shrinker invocations have seen an update, before freeing memory, similar to + * rcu. + */ +void synchronize_shrinkers(void) +{ + down_write(&shrinker_rwsem); + up_write(&shrinker_rwsem); +} +EXPORT_SYMBOL(synchronize_shrinkers); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ab7ab796cb97e..3a428b4d7721e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1001,6 +1001,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* synchronize_shrinkers() is available */ +#define HAVE_SYNCHRONIZE_SHRINKERS 1 + /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d2f33512c713d..272aa6aa2d85d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -140,6 +140,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 new file mode 100644 index 0000000000000..3abf21e7f2b67 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.14-rc3-760-g880121be1179 +dnl # mm/vmscan: add sync_shrinkers function v3 +dnl # +AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([synchronize_shrinkers], + [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 419e528fd874c..20a2fd60b82d2 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -18,5 +18,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h new file mode 100644 index 0000000000000..d8704a749d2dd --- /dev/null +++ b/include/kcl/kcl_shrinker.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef AMDKCL_SHRINKER_H +#define AMDKCL_SHRINKER_H + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +extern void synchronize_shrinkers(void); +#endif + +#endif From a386d3d5366b9837fd55ef183c005a578767196c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 13:00:54 +0800 Subject: [PATCH 0772/2070] drm/amdkcl: Test whether krealloc_array() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 18 +++++++++ include/kcl/backport/kcl_fence_backport.h | 1 + include/kcl/kcl_slab.h | 37 +++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 create mode 100644 include/kcl/kcl_slab.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3a428b4d7721e..88a4c78c96727 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -705,6 +705,9 @@ /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 +/* krealloc_array() is available */ +#define HAVE_KREALLOC_ARRAY 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 272aa6aa2d85d..05a5d9b3ee855 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_AMDGPU_SYNCHRONIZE_SHRINKERS + AC_AMDGPU_KREALLOC_ARRAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 new file mode 100644 index 0000000000000..f9f0fa0a1862f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.10-13-gf0dbd2bd1c22 +dnl # mm: slab: provide krealloc_array() +dnl # +AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + void *p = krealloc_array(NULL, 0, 0, GFP_KERNEL); + (void)p; + ], [ + AC_DEFINE(HAVE_KREALLOC_ARRAY, 1, + [krealloc_array() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 7e3e1ab42138b..a29c3293c6c88 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_FENCE_BACKPORT_H #define AMDKCL_FENCE_BACKPORT_H #include +#include /* * commit v4.18-rc2-533-g418cc6ca0607 diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h new file mode 100644 index 0000000000000..e095f8a46088e --- /dev/null +++ b/include/kcl/kcl_slab.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Written by Mark Hemment, 1996 (markhe@nextd.demon.co.uk). + * + * (C) SGI 2006, Christoph Lameter + * Cleaned up and restructured to ease the addition of alternative + * implementations of SLAB allocators. + * (C) Linux Foundation 2008-2013 + * Unified interface for all slab allocators + */ +#ifndef AMDKCL_SLAB_H +#define AMDKCL_SLAB_H + +#include +#include + +#ifndef HAVE_KREALLOC_ARRAY +/** + * krealloc_array - reallocate memory for an array. + * @p: pointer to the memory chunk to reallocate + * @new_n: new number of elements to alloc + * @new_size: new size of a single member of the array + * @flags: the type of memory to allocate (see kmalloc) + */ +static __must_check inline void * +krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) +{ + size_t bytes; + + if (unlikely(check_mul_overflow(new_n, new_size, &bytes))) + return NULL; + + return krealloc(p, bytes, flags); +} +#endif + +#endif From b1563a710aebe4a3746d421c1af2935c376bf77b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 13:27:47 +0800 Subject: [PATCH 0773/2070] drm/amdkcl: Test whether vga_client_register() don't pass cookie argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 ++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/vga-client-register.m4 | 18 ++++++++++++++++++ 4 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f4832b7c8adfd..2a9ab2adee3c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2095,11 +2095,18 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) * Enable/disable vga decode (all asics). * Returns VGA resource flags. */ +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, bool state) +#else +static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) +#endif { +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); - +#else + struct amdgpu_device *adev = cookie; +#endif amdgpu_asic_set_vga_state(adev, state); if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | @@ -4811,7 +4818,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, * ignore it */ if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); +#else + vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); +#endif px = amdgpu_device_supports_px(adev); @@ -4992,7 +5003,11 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) vga_switcheroo_fini_domain_pm_ops(adev->dev); if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_unregister(adev->pdev); +#else + vga_client_register(adev->pdev, NULL, NULL, NULL); +#endif if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 88a4c78c96727..65457b4a0732a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1019,8 +1019,8 @@ /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 -/* Define to 1 if you have the header file. */ -#define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_client_register() don't pass a cookie */ +#define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 /* vga_remove_vgacon() is available */ #define HAVE_VGA_REMOVE_VGACON 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 05a5d9b3ee855..6859bf482ff95 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -142,6 +142,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY + AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 new file mode 100644 index 0000000000000..603da40bd05db --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.13-rc3-1630-gbf44e8cecc03 +dnl # vgaarb: don't pass a cookie to vga_client_register +dnl # +AC_DEFUN([AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct pci_dev; + ], [ + unsigned int (*callback)(struct pci_dev *, bool) = NULL; + vga_client_register(NULL, callback); + ], [ + AC_DEFINE(HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE, 1, + [vga_client_register() don't pass a cookie]) + ]) + ]) +]) From a3fbdf5b8e790aa53c2184a04894897a07a3261b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:51:31 +0800 Subject: [PATCH 0774/2070] drm/amdkcl: Test whether vma_lookup() is available Signed-off-by: Leslie Shi Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 16 ++++++++++++++++ include/kcl/kcl_mm.h | 20 ++++++++++++++++++++ 4 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 65457b4a0732a..e1de35ed41dc1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1028,6 +1028,9 @@ /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ +/* vma_lookup() is available */ +#define HAVE_VMA_LOOKUP 1 + /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6859bf482ff95..a3035e7ed0eaf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -143,6 +143,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE + AC_AMDGPU_VMA_LOOKUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 new file mode 100644 index 0000000000000..1eb0129ff303c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-105-gce6d42f2e4a2 +dnl # mm: add vma_lookup(), update find_vma_intersection() comments +dnl # +AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_lookup(NULL, 0); + ], [ + AC_DEFINE(HAVE_VMA_LOOKUP, 1, + [vma_lookup() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index ec9c971d7950e..e0ccb3247704a 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -55,4 +55,24 @@ static inline bool is_cow_mapping(vm_flags_t flags) } #endif /* HAVE_IS_COW_MAPPING */ +#ifndef HAVE_VMA_LOOKUP +/** + * vma_lookup() - Find a VMA at a specific address + * @mm: The process address space. + * @addr: The user address. + * + * Return: The vm_area_struct at the given address, %NULL otherwise. + */ +static inline +struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) +{ + struct vm_area_struct *vma = find_vma(mm, addr); + + if (vma && addr < vma->vm_start) + vma = NULL; + + return vma; +} +#endif /* HAVE_VMA_LOOKUP */ + #endif /* AMDKCL_MM_H */ From 2593e444b3a7133d4beab0b32dea6d99220774b4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 14:24:31 +0800 Subject: [PATCH 0775/2070] drm/amdkcl: Test whether generic_handle_domain_irq() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/generic_handle_domain_irq.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +++ 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index fed9902c95c0b..c5eb38ca11618 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -512,7 +512,11 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { +#ifdef HAVE_GENERIC_HANDLE_DOMAIN_IRQ generic_handle_domain_irq(adev->irq.domain, src_id); +#else + generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); +#endif } else if (!adev->irq.client[client_id].sources) { dev_dbg(adev->dev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e1de35ed41dc1..f2cdd9ef73367 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -642,6 +642,9 @@ /* drm_driver->gem_free_object_unlocked() is available */ /* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ +/* generic_handle_domain_irq() is available */ +#define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 + /* get_user_pages() wants 6 args */ /* #undef HAVE_GET_USER_PAGES_6ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 new file mode 100644 index 0000000000000..d02f0f7f60014 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-rc4-24-g8240ef50d486 +dnl # genirq: Add generic_handle_domain_irq() helper +dnl # +AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + generic_handle_domain_irq(NULL, 0); + ], [ + AC_DEFINE(HAVE_GENERIC_HANDLE_DOMAIN_IRQ, 1, + [generic_handle_domain_irq() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a3035e7ed0eaf..982bc964e724d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -144,6 +144,9 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_AMDGPU_VMA_LOOKUP + AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC + AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From f4d8c8417b4d8d86e97547990e799589d68bd925 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 15:17:19 +0800 Subject: [PATCH 0776/2070] drm/amdkcl: Test whether linux/stdarg.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/stdarg.h | 11 +++++++++++ 4 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/stdarg.h diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 04b8b798dfff6..9e6ff518b6785 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -28,8 +28,6 @@ */ #include -#include - #include "dm_services.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f2cdd9ef73367..67e388c2a403f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -804,6 +804,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_TASK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_STDARG_H 1 + /* list_bulk_move_tail() is available */ #define HAVE_LIST_BULK_MOVE_TAIL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 3701b776bd191..17cf63dcc0664 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -66,4 +66,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + + dnl # + dnl # v5.14-rc5-11-gc0891ac15f04 + dnl # isystem: ship and use stdarg.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) ]) diff --git a/include/kcl/header/linux/stdarg.h b/include/kcl/header/linux/stdarg.h new file mode 100644 index 0000000000000..c7564aec2d86d --- /dev/null +++ b/include/kcl/header/linux/stdarg.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_STDARG_H_H +#define _KCL_HEADER_LINUX_STDARG_H_H + +#if defined(HAVE_LINUX_STDARG_H) +#include_next +#else +#include +#endif + +#endif From 7f730572db310262b1d066679f228e6bd1a753f4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 12:41:13 +0800 Subject: [PATCH 0777/2070] drm/amdkcl: access resv field using amdkcl_ttm_resv Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 3bd5c663501a8..0ffe77d741b34 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -226,7 +226,7 @@ static void ttm_transfered_destroy(struct ttm_buffer_object *bo) struct ttm_transfer_obj *fbo; fbo = container_of(bo, struct ttm_transfer_obj, base); - dma_resv_fini(&fbo->base.base._resv); + dma_resv_fini(&amdkcl_ttm_resv(&fbo->base)); ttm_bo_put(fbo->bo); kfree(fbo); } From b8decbe1b78c71bfa02169c7ded4503678e08394 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 13:18:16 +0800 Subject: [PATCH 0778/2070] drm/amdkcl: add rcu_replace_pointer macro for legacy os Signed-off-by: Leslie Shi --- include/kcl/kcl_rcupdate.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h index da63bf6d4f9e0..d2b09177e7c56 100644 --- a/include/kcl/kcl_rcupdate.h +++ b/include/kcl/kcl_rcupdate.h @@ -26,4 +26,26 @@ #define rcu_pointer_handoff(p) (p) #endif +#ifndef rcu_replace_pointer +#if defined(rcu_dereference_protected) && defined(rcu_assign_pointer) +/** + * rcu_replace_pointer() - replace an RCU pointer, returning its old value + * @rcu_ptr: RCU pointer, whose old value is returned + * @ptr: regular pointer + * @c: the lockdep conditions under which the dereference will take place + * + * Perform a replacement, where @rcu_ptr is an RCU-annotated + * pointer and @c is the lockdep argument that is passed to the + * rcu_dereference_protected() call used to read that pointer. The old + * value of @rcu_ptr is returned, and @rcu_ptr is set to @ptr. + */ +#define rcu_replace_pointer(rcu_ptr, ptr, c) \ +({ \ + typeof(ptr) __tmp = rcu_dereference_protected((rcu_ptr), (c)); \ + rcu_assign_pointer((rcu_ptr), (ptr)); \ + __tmp; \ +}) +#endif +#endif + #endif /* AMDKCL_RCUPDATE_H */ From 8f1fc5ff916430499ef7a9e912207e1b9f8bc4ce Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 14:05:53 +0800 Subject: [PATCH 0779/2070] drm/amdkcl: Test whether dma_fence_chain is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 261 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 6 + .../gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 34 +++ include/kcl/kcl_dma_fence_chain.h | 123 +++++++++ include/kcl/kcl_fence.h | 2 + 7 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 create mode 100644 include/kcl/kcl_dma_fence_chain.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a542ecd7cb11b..c4374f3eb8e8c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c new file mode 100644 index 0000000000000..86420a8e73b90 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) + +#include + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); + +/** + * dma_fence_chain_get_prev - use RCU to get a reference to the previous fence + * @chain: chain node to get the previous node from + * + * Use dma_fence_get_rcu_safe to get a reference to the previous fence of the + * chain node. + */ +static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain) +{ + struct dma_fence *prev; + + rcu_read_lock(); + prev = dma_fence_get_rcu_safe(&chain->prev); + rcu_read_unlock(); + return prev; +} + +/** + * dma_fence_chain_walk - chain walking function + * @fence: current chain node + * + * Walk the chain to the next node. Returns the next fence or NULL if we are at + * the end of the chain. Garbage collects chain nodes which are already + * signaled. + */ +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) +{ + struct dma_fence_chain *chain, *prev_chain; + struct dma_fence *prev, *replacement, *tmp; + + chain = to_dma_fence_chain(fence); + if (!chain) { + dma_fence_put(fence); + return NULL; + } + + while ((prev = dma_fence_chain_get_prev(chain))) { + + prev_chain = to_dma_fence_chain(prev); + if (prev_chain) { + if (!dma_fence_is_signaled(prev_chain->fence)) + break; + + replacement = dma_fence_chain_get_prev(prev_chain); + } else { + if (!dma_fence_is_signaled(prev)) + break; + + replacement = NULL; + } + + tmp = cmpxchg((struct dma_fence __force **)&chain->prev, + prev, replacement); + if (tmp == prev) + dma_fence_put(tmp); + else + dma_fence_put(replacement); + dma_fence_put(prev); + } + + dma_fence_put(fence); + return prev; +} +EXPORT_SYMBOL(dma_fence_chain_walk); + +/** + * dma_fence_chain_find_seqno - find fence chain node by seqno + * @pfence: pointer to the chain node where to start + * @seqno: the sequence number to search for + * + * Advance the fence pointer to the chain node which will signal this sequence + * number. If no sequence number is provided then this is a no-op. + * + * Returns EINVAL if the fence is not a chain node or the sequence number has + * not yet advanced far enough. + */ +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) +{ + struct dma_fence_chain *chain; + + if (!seqno) + return 0; + + chain = to_dma_fence_chain(*pfence); + if (!chain || chain->base.seqno < seqno) + return -EINVAL; + + dma_fence_chain_for_each(*pfence, &chain->base) { + if ((*pfence)->context != chain->base.context || + to_dma_fence_chain(*pfence)->prev_seqno < seqno) + break; + } + dma_fence_put(&chain->base); + + return 0; +} +EXPORT_SYMBOL(dma_fence_chain_find_seqno); + +static const char *dma_fence_chain_get_driver_name(struct dma_fence *fence) +{ + return "dma_fence_chain"; +} + +static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) +{ + return "unbound"; +} + +static void dma_fence_chain_irq_work(struct irq_work *work) +{ + struct dma_fence_chain *chain; + + chain = container_of(work, typeof(*chain), work); + + /* Try to rearm the callback */ + if (!dma_fence_chain_enable_signaling(&chain->base)) + /* Ok, we are done. No more unsignaled fences left */ + dma_fence_signal(&chain->base); + dma_fence_put(&chain->base); +} + +static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) +{ + struct dma_fence_chain *chain; + + chain = container_of(cb, typeof(*chain), cb); + init_irq_work(&chain->work, dma_fence_chain_irq_work); + irq_work_queue(&chain->work); + dma_fence_put(f); +} + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_chain *head = to_dma_fence_chain(fence); + + dma_fence_get(&head->base); + dma_fence_chain_for_each(fence, &head->base) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + dma_fence_get(f); + if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { + dma_fence_put(fence); + return true; + } + dma_fence_put(f); + } + dma_fence_put(&head->base); + return false; +} + +static bool dma_fence_chain_signaled(struct dma_fence *fence) +{ + dma_fence_chain_for_each(fence, fence) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + if (!dma_fence_is_signaled(f)) { + dma_fence_put(fence); + return false; + } + } + + return true; +} + +static void dma_fence_chain_release(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *prev; + + /* Manually unlink the chain as much as possible to avoid recursion + * and potential stack overflow. + */ + while ((prev = rcu_dereference_protected(chain->prev, true))) { + struct dma_fence_chain *prev_chain; + + if (kref_read(&prev->refcount) > 1) + break; + + prev_chain = to_dma_fence_chain(prev); + if (!prev_chain) + break; + + /* No need for atomic operations since we hold the last + * reference to prev_chain. + */ + chain->prev = prev_chain->prev; + RCU_INIT_POINTER(prev_chain->prev, NULL); + dma_fence_put(prev); + } + dma_fence_put(prev); + + dma_fence_put(chain->fence); + dma_fence_free(fence); +} + +const struct dma_fence_ops dma_fence_chain_ops = { + .use_64bit_seqno = true, + .get_driver_name = dma_fence_chain_get_driver_name, + .get_timeline_name = dma_fence_chain_get_timeline_name, + .enable_signaling = dma_fence_chain_enable_signaling, + .signaled = dma_fence_chain_signaled, + .release = dma_fence_chain_release, +}; +EXPORT_SYMBOL(dma_fence_chain_ops); + +/** + * dma_fence_chain_init - initialize a fence chain + * @chain: the chain node to initialize + * @prev: the previous fence + * @fence: the current fence + * @seqno: the sequence number to use for the fence chain + * + * Initialize a new chain node and either start a new chain or add the node to + * the existing chain of the previous fence. + */ +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno) +{ + struct dma_fence_chain *prev_chain = to_dma_fence_chain(prev); + uint64_t context; + + spin_lock_init(&chain->lock); + rcu_assign_pointer(chain->prev, prev); + chain->fence = fence; + chain->prev_seqno = 0; + + /* Try to reuse the context of the previous chain node. */ + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { + context = prev->context; + chain->prev_seqno = prev->seqno; + } else { + context = dma_fence_context_alloc(1); + /* Make sure that we always have a valid sequence number. */ + if (prev_chain) + seqno = max(prev->seqno, seqno); + } + + dma_fence_init(&chain->base, &dma_fence_chain_ops, + &chain->lock, context, seqno); +} +EXPORT_SYMBOL(dma_fence_chain_init); +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 92d2aabbce2e6..1995618d3d9fc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -75,5 +75,7 @@ #include #include #include +#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 67e388c2a403f..281c5078f4f3d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -85,6 +85,9 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ +/* dma_fence_chain_alloc() is available */ +#define HAVE_DMA_FENCE_CHAIN_ALLOC 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -940,6 +943,9 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 +/* struct dma_fence_chain is available */ +#define HAVE_STRUCT_DMA_FENCE_CHAIN 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 new file mode 100644 index 0000000000000..34231d5d2028d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.13-rc3-1424-g440d0f12b52a +dnl # dma-buf: add dma_fence_chain_alloc/free v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_alloc(); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, + [dma_fence_chain_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # v5.0-1331-g7bf60c52e093 +dnl # dma-buf: add new dma_fence_chain container v7 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_chain *chain = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, + [struct dma_fence_chain is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h new file mode 100644 index 0000000000000..4cde69227a3f1 --- /dev/null +++ b/include/kcl/kcl_dma_fence_chain.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ +#ifndef AMDKCL_DMA_FENCE_CHAIN_H +#define AMDKCL_DMA_FENCE_CHAIN_H + + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) +#ifdef HAVE_LINUX_DMA_FENCE_H +#include +#else +#include +#endif +#include +#include + +/** + * struct dma_fence_chain - fence to represent an node of a fence chain + * @base: fence base class + * @prev: previous fence of the chain + * @prev_seqno: original previous seqno before garbage collection + * @fence: encapsulated fence + * @lock: spinlock for fence handling + */ +struct dma_fence_chain { + struct dma_fence base; + struct dma_fence __rcu *prev; + u64 prev_seqno; + struct dma_fence *fence; + union { + /** + * @cb: callback for signaling + * + * This is used to add the callback for signaling the + * complection of the fence chain. Never used at the same time + * as the irq work. + */ + struct dma_fence_cb cb; + + /** + * @work: irq work item for signaling + * + * Irq work structure to allow us to add the callback without + * running into lock inversion. Never used at the same time as + * the callback. + */ + struct irq_work work; + }; + spinlock_t lock; +}; + +extern const struct dma_fence_ops dma_fence_chain_ops; + +/** + * to_dma_fence_chain - cast a fence to a dma_fence_chain + * @fence: fence to cast to a dma_fence_array + * + * Returns NULL if the fence is not a dma_fence_chain, + * or the dma_fence_chain otherwise. + */ +static inline struct dma_fence_chain * +to_dma_fence_chain(struct dma_fence *fence) +{ + if (!fence || fence->ops != &dma_fence_chain_ops) + return NULL; + + return container_of(fence, struct dma_fence_chain, base); +} + +/** + * dma_fence_chain_for_each - iterate over all fences in chain + * @iter: current fence + * @head: starting point + * + * Iterate over all fences in the chain. We keep a reference to the current + * fence while inside the loop which must be dropped when breaking out. + */ +#define dma_fence_chain_for_each(iter, head) \ + for (iter = dma_fence_get(head); iter; \ + iter = dma_fence_chain_walk(iter)) + +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence); +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno); +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno); + +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) || !defined(HAVE_DMA_FENCE_CHAIN_ALLOC) +/** + * dma_fence_chain_alloc + * + * Returns a new struct dma_fence_chain object or NULL on failure. + */ +static inline struct dma_fence_chain *dma_fence_chain_alloc(void) +{ + return kmalloc(sizeof(struct dma_fence_chain), GFP_KERNEL); +}; + +/** + * dma_fence_chain_free + * @chain: chain node to free + * + * Frees up an allocated but not used struct dma_fence_chain object. This + * doesn't need an RCU grace period since the fence was never initialized nor + * published. After dma_fence_chain_init() has been called the fence must be + * released by calling dma_fence_put(), and not through this function. + */ +static inline void dma_fence_chain_free(struct dma_fence_chain *chain) +{ + kfree(chain); +}; + +#endif + +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 88a2d1a425ec2..ec9f6c83ab8da 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -40,6 +40,8 @@ #define dma_fence_remove_callback fence_remove_callback #define dma_fence_enable_sw_signaling fence_enable_sw_signaling #define dma_fence_default_wait fence_default_wait +#define dma_fence_free fence_free +#define dma_fence_get_rcu_safe fence_get_rcu #define dma_fence_set_error fence_set_error #endif From 4c7b09b2ce7bda3971ecff1838226fb8a44f3fbd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 13:35:38 +0800 Subject: [PATCH 0780/2070] drm/amdkcl: Test whether struct dma_fence_ops has use_64bit_seqno field Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index 86420a8e73b90..853c470a7e77a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -211,7 +211,9 @@ static void dma_fence_chain_release(struct dma_fence *fence) } const struct dma_fence_ops dma_fence_chain_ops = { +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO .use_64bit_seqno = true, +#endif .get_driver_name = dma_fence_chain_get_driver_name, .get_timeline_name = dma_fence_chain_get_timeline_name, .enable_signaling = dma_fence_chain_enable_signaling, @@ -244,7 +246,11 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, chain->prev_seqno = 0; /* Try to reuse the context of the previous chain node. */ +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { +#else + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno)) { +#endif context = prev->context; chain->prev_seqno = prev->seqno; } else { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 281c5078f4f3d..b8fa804bd3ee7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -91,6 +91,9 @@ /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 +/* struct dma_fence_ops has use_64bit_seqno field */ +#define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 + /* dma_fence_set_error() is available */ #define HAVE_DMA_FENCE_SET_ERROR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 new file mode 100644 index 0000000000000..c10c92dfb503e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_ops *ops = NULL; + ops->use_64bit_seqno = false; + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO, 1, + [struct dma_fence_ops has use_64bit_seqno field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 982bc964e724d..a7cdbaebbdfd4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -146,6 +146,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMA_LOOKUP AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_KERNEL_WAIT From 0e7c5dcc020a59325d29ffa10590af94033ed7a1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 14:04:37 +0800 Subject: [PATCH 0781/2070] drm/amdkcl: Test whether linux/dma-fence-chain.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/dma-fence-chain.h | 9 +++++++++ 4 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/dma-fence-chain.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index d6ae9974c952e..8858dd9ffb021 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -29,8 +29,6 @@ * Christian König */ -#include - #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_amdkfd.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b8fa804bd3ee7..8d0b0246bf81b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -771,6 +771,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_BUF_MAP_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 17cf63dcc0664..b14c93e6be716 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -72,4 +72,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # isystem: ship and use stdarg.h dnl # AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) + + dnl # + dnl # v5.0-1331-g7bf60c52e093 + dnl # dma-buf: add new dma_fence_chain container v7 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) ]) diff --git a/include/kcl/header/linux/dma-fence-chain.h b/include/kcl/header/linux/dma-fence-chain.h new file mode 100644 index 0000000000000..ff429da204f75 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-chain.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_CHAIN_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_CHAIN_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_CHAIN_H) +#include_next +#endif + +#endif From 050ff79b058194a937751dfb1bd9b12996712b6d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 14:44:13 +0800 Subject: [PATCH 0782/2070] drm/amdkcl: wrap the code under macro HAVE_DRM_GEM_OBJECT_RESV Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index bd7936c03da2a..c09452710e9a5 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -980,6 +980,7 @@ int drm_sched_job_add_resv_dependencies(struct drm_sched_job *job, } EXPORT_SYMBOL(drm_sched_job_add_resv_dependencies); +#ifdef HAVE_DRM_GEM_OBJECT_RESV /** * drm_sched_job_add_implicit_dependencies - adds implicit dependencies as job * dependencies @@ -1003,6 +1004,7 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, dma_resv_usage_rw(write)); } EXPORT_SYMBOL(drm_sched_job_add_implicit_dependencies); +#endif /** * drm_sched_job_has_dependency - check whether fence is the job's dependency From 3a2a1536a5bbfb74dfab95981507bd4f53189345 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 16:36:08 +0800 Subject: [PATCH 0783/2070] drm/amdkcl: wrap the code under HAVE_STRUCT_XARRAY for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 7 +++++++ drivers/gpu/drm/scheduler/sched_main.c | 10 ++++++++-- include/drm/gpu_scheduler.h | 5 +++++ include/kcl/header/linux/xarray.h | 9 +++++++++ 4 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/xarray.h diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index fe174a4857be7..e95e6f6abb273 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -463,6 +463,9 @@ drm_sched_job_dependency(struct drm_sched_job *job, struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) { +#ifndef HAVE_STRUCT_XARRAY + struct drm_gpu_scheduler *sched = entity->rq->sched; +#endif struct drm_sched_job *sched_job; sched_job = drm_sched_entity_queue_peek(entity); @@ -470,7 +473,11 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) return NULL; while ((entity->dependency = +#ifdef HAVE_STRUCT_XARRAY drm_sched_job_dependency(sched_job, entity))) { +#else + sched->ops->dependency(sched_job, entity))) { +#endif if (drm_sched_entity_add_dependency_cb(entity, sched_job)) return NULL; } diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index c09452710e9a5..e4021399b4136 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -830,8 +830,9 @@ int drm_sched_job_init(struct drm_sched_job *job, return -ENOMEM; INIT_LIST_HEAD(&job->list); - +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&job->dependencies, XA_FLAGS_ALLOC); +#endif return 0; } @@ -870,6 +871,7 @@ void drm_sched_job_arm(struct drm_sched_job *job) } EXPORT_SYMBOL(drm_sched_job_arm); +#ifdef HAVE_STRUCT_XARRAY /** * drm_sched_job_add_dependency - adds the fence as a job dependency * @job: scheduler job to add the dependencies to @@ -1028,6 +1030,7 @@ bool drm_sched_job_has_dependency(struct drm_sched_job *job, return false; } EXPORT_SYMBOL(drm_sched_job_has_dependency); +#endif /* HAVE_STRUCR_XARRAY */ /** * drm_sched_job_cleanup - clean up scheduler job resources @@ -1047,8 +1050,10 @@ EXPORT_SYMBOL(drm_sched_job_has_dependency); */ void drm_sched_job_cleanup(struct drm_sched_job *job) { +#ifdef HAVE_STRUCT_XARRAY struct dma_fence *fence; unsigned long index; +#endif if (kref_read(&job->s_fence->finished.refcount)) { /* The job has been processed by the scheduler, i.e., @@ -1065,11 +1070,12 @@ void drm_sched_job_cleanup(struct drm_sched_job *job) job->s_fence = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&job->dependencies, index, fence) { dma_fence_put(fence); } xa_destroy(&job->dependencies); - +#endif } EXPORT_SYMBOL(drm_sched_job_cleanup); diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 78e07c2507c7a..8dd05a0b7d1c5 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -359,8 +359,10 @@ struct drm_sched_job { enum drm_sched_priority s_priority; u32 credits; +#ifdef HAVE_STRUCT_XARRAY /** @last_dependency: tracks @dependencies as they signal */ unsigned int last_dependency; +#endif atomic_t karma; struct spsc_node queue_node; @@ -384,7 +386,9 @@ struct drm_sched_job { * drm_sched_job_add_dependency() and * drm_sched_job_add_implicit_dependencies(). */ +#ifdef HAVE_STRUCT_XARRAY struct xarray dependencies; +#endif }; /** @@ -659,6 +663,7 @@ int drm_sched_job_init(struct drm_sched_job *job, u64 drm_client_id); void drm_sched_job_arm(struct drm_sched_job *job); void drm_sched_entity_push_job(struct drm_sched_job *sched_job); + int drm_sched_job_add_dependency(struct drm_sched_job *job, struct dma_fence *fence); int drm_sched_job_add_syncobj_dependency(struct drm_sched_job *job, diff --git a/include/kcl/header/linux/xarray.h b/include/kcl/header/linux/xarray.h new file mode 100644 index 0000000000000..3df793f177365 --- /dev/null +++ b/include/kcl/header/linux/xarray.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_LINUX_XARRAY_H_H +#define _KCL_HEADER_LINUX_XARRAY_H_H + +#ifdef HAVE_STRUCT_XARRAY +#include_next +#endif + +#endif From 0e386b1589bf443475b34e1d54aa217af04acf0a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 11:58:32 +0800 Subject: [PATCH 0784/2070] drm/amdkcl: add macro DP_PSR2_SU_X_GRANULARITY for legacy os Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index ec52d89063426..10b162b5c4693 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -276,4 +276,16 @@ enum drm_dp_phy { # define DP_DPCD_REV_14 0x14 #endif +/* + * v4.20-rc3-897-g71b15621f097 + * drm: Add the PSR SU granularity registers offsets + */ +#ifndef DP_PSR2_SU_X_GRANULARITY +#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ +#endif +#ifndef DP_PSR2_SU_Y_GRANULARITY +#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ +#endif + + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 34589e566133b830a558a0d51e980eefa49e489d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 15:35:09 +0800 Subject: [PATCH 0785/2070] drm/amdkcl: include kcl_kref.h for drm scheduler code Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index de169d5752a83..5c3a31abb6713 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -6,5 +6,6 @@ #include #include #include +#include #endif From 73c4e7981e5606f961d105bc7a481ea93caa782e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 15:59:05 +0800 Subject: [PATCH 0786/2070] drm/amdkcl: test whether __dma_fence_is_later() is available Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 7 ++-- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 30 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fence.h | 35 +++++++++++++++++++ 5 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index 853c470a7e77a..aef948cfe4ad2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -9,6 +9,7 @@ #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) +#include #include static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8d0b0246bf81b..4aabedb936a2e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1088,8 +1088,11 @@ /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 -/* bitmap_free() is available */ -#define HAVE_BITMAP_FUNCS 1 +/* __dma_fence_is_later() is available and has 2 args */ +/* #undef HAVE__DMA_FENCE_IS_LATER_2ARGS */ + +/* __dma_fence_is_later() is available and has ops arg */ +#define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 new file mode 100644 index 0000000000000..bbc3eb8117f9c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -0,0 +1,30 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct dma_fence_ops *ops = NULL; + __dma_fence_is_later(0, 0, ops); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, + [__dma_fence_is_later() is available and has ops arg]) + ], [ + dnl # + dnl # v4.20-rc4-931-gb312d8ca3a7c + dnl # dma-buf: make fence sequence numbers 64 bit v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + __dma_fence_is_later(0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, + [__dma_fence_is_later() is available and has 2 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a7cdbaebbdfd4..38ec52be4fae2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -148,6 +148,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ + AC_AMDGPU__DMA_FENCE_IS_LATER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index ec9f6c83ab8da..addd6733ff680 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -46,6 +46,41 @@ #define dma_fence_set_error fence_set_error #endif +#if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) + +#if !defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) +static inline bool __dma_fence_is_later(u64 f1, u64 f2) +{ + + /* This is for backward compatibility with drivers which can only handle + * 32bit sequence numbers. Use a 64bit compare when any of the higher + * bits are none zero, otherwise use a 32bit compare with wrap around + * handling. + */ + if (upper_32_bits(f1) || upper_32_bits(f2)) + return f1 > f2; + + return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; +} + +#elif !defined(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG) && \ + defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) +static inline bool __dma_fence_is_later(u64 f1, u64 f2, + const struct dma_fence_ops *ops) +{ + /* This is for backward compatibility with drivers which can only handle + * 32bit sequence numbers. Use a 64bit compare when the driver says to + * do so. + */ + if (ops->use_64bit_seqno) + return f1 > f2; + + return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; +} + +#endif +#endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ + /* commit v4.5-rc3-715-gb47bcb93bbf2 * fall back to HAVE_LINUX_DMA_FENCE_H check directly * as it's hard to detect the implementation in kernel From 663208793eb61d73275808709cd4a26a4f08b25d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 16:31:28 +0800 Subject: [PATCH 0787/2070] drm/amdkcl: test whether pci_irq_vector() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1995618d3d9fc..7aae4d91fec3c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -77,5 +77,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ From 11663a223c41221d0e6af517ccc661b7fe9b5aa3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 20 Jan 2022 10:43:24 +0800 Subject: [PATCH 0788/2070] drm/amdkcl: add macro DP_PSR2_SU_GRANULARITY_REQUIRED Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 10b162b5c4693..f32ad22d172db 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -287,5 +287,15 @@ enum drm_dp_phy { #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ #endif +/* + * v4.10-rc3-483-gd0ce90629120 + * drm : adds Y-coordinate and Colorimetry Format + */ +#ifndef DP_PSR2_SU_Y_COORDINATE_REQUIRED +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ +# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ +#endif + + #endif /* _KCL_DRM_DP_HELPER_H_ */ From fc30e439749877f4e48c87fc74947a8c54fbda9e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 20 Jan 2022 15:53:46 +0800 Subject: [PATCH 0789/2070] drm/amdkcl: test whether linux/xarray.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 +++++++ include/kcl/header/linux/xarray.h | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4aabedb936a2e..0ecb74e3a749f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -816,6 +816,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_XARRAY_H 1 + /* list_bulk_move_tail() is available */ #define HAVE_LIST_BULK_MOVE_TAIL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index b14c93e6be716..c6c1a30dc28e7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -78,4 +78,11 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-buf: add new dma_fence_chain container v7 dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) + + + dnl # + dnl # v4.16-11455-gf6bb2a2c0b81 + dnl # xarray: add the xa_lock to the radix_tree_root + dnl # + AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) ]) diff --git a/include/kcl/header/linux/xarray.h b/include/kcl/header/linux/xarray.h index 3df793f177365..80d73c2ed9065 100644 --- a/include/kcl/header/linux/xarray.h +++ b/include/kcl/header/linux/xarray.h @@ -2,7 +2,7 @@ #ifndef _KCL_HEADER_LINUX_XARRAY_H_H #define _KCL_HEADER_LINUX_XARRAY_H_H -#ifdef HAVE_STRUCT_XARRAY +#ifdef HAVE_LINUX_XARRAY_H #include_next #endif From 95011a03e528945ae22726516c097154ac481912 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 20 Dec 2021 22:44:06 -0500 Subject: [PATCH 0790/2070] drm/amdkcl: wrap drm_edid_get_monitor_name with macro HAVE_DRM_EDID_GET_MONITOR_NAME This patch will check if the drm_edid_get_monitor_name exist in the some old kernel to avoid build dependency failure. b5f640ae7a0 drm/amdgpu: use drm_edid_get_monitor_name() instead of duplicating the code v5.13-3120-gb5f640ae7a0a Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0ecb74e3a749f..1290eba98aa13 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1097,6 +1097,9 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* drm_edid_get_monitor_name is available*/ +#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 From def49d23aebf1241b6fbab08c8d885f7b94295bf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 11:01:46 +0800 Subject: [PATCH 0791/2070] drm/amdkcl: Test whether linux/container_of.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 ++++++- include/kcl/header/linux/container_of.h | 10 ++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/linux/container_of.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1290eba98aa13..6d8aef36b6da4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -765,6 +765,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CONTAINER_OF_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index c6c1a30dc28e7..71de840d4a3c9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -79,10 +79,15 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) - dnl # dnl # v4.16-11455-gf6bb2a2c0b81 dnl # xarray: add the xa_lock to the radix_tree_root dnl # AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) + + dnl # + dnl # v5.15-272-gd2a8ebbf8192 + dnl # kernel.h: split out container_of() and typeof_member() macros + dnl # + AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) ]) diff --git a/include/kcl/header/linux/container_of.h b/include/kcl/header/linux/container_of.h new file mode 100644 index 0000000000000..cf1f8a85f216f --- /dev/null +++ b/include/kcl/header/linux/container_of.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CONTAINER_OF_H_H +#define _KCL_HEADER_LINUX_CONTAINER_OF_H_H + +#if defined(HAVE_LINUX_CONTAINER_OF_H) +#include_next +#endif + +#endif + From 67a2e4515a8ce43b1939c9c23cf1fa0854f16d34 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 11:13:51 +0800 Subject: [PATCH 0792/2070] drm/amdkcl: Test whether linux/cc_platform.h is available It's caused by v6.7-rc3-802-g71ce046327cf drm/ttm: Make sure the mapped tt pages are decrypted when needed Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/header/linux/cc_platform.h | 10 +++ include/kcl/kcl_cc_platform.h | 66 ++++++++++++++++++++ 6 files changed, 87 insertions(+) create mode 100644 include/kcl/header/linux/cc_platform.h create mode 100644 include/kcl/kcl_cc_platform.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7aae4d91fec3c..477e63ef5d402 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -78,5 +78,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6d8aef36b6da4..c19ef6217ee28 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -762,6 +762,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CC_PLATFORM_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 71de840d4a3c9..a55316db51fb7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -90,4 +90,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # kernel.h: split out container_of() and typeof_member() macros dnl # AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) + + dnl # + dnl # v5.15-rc4-2-g46b49b12f3fc + dnl # arch/cc: Introduce a function to check for confidential computing features + dnl # + AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) ]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 20a2fd60b82d2..b4ed7c672dcd8 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/header/linux/cc_platform.h b/include/kcl/header/linux/cc_platform.h new file mode 100644 index 0000000000000..cea7cc0c28876 --- /dev/null +++ b/include/kcl/header/linux/cc_platform.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CC_PLATFORM_H_H +#define _KCL_HEADER_LINUX_CC_PLATFORM_H_H + +#if defined(HAVE_LINUX_CC_PLATFORM_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_cc_platform.h b/include/kcl/kcl_cc_platform.h new file mode 100644 index 0000000000000..8a2d455442e4f --- /dev/null +++ b/include/kcl/kcl_cc_platform.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Confidential Computing Platform Capability checks + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ +#ifndef AMDKCL_CC_PLATFORM_H +#define AMDKCL_CC_PLATFORM_H + +#ifndef HAVE_LINUX_CC_PLATFORM_H +/** + * enum cc_attr - Confidential computing attributes + * + * These attributes represent confidential computing features that are + * currently active. + */ +enum cc_attr { + /** + * @CC_ATTR_MEM_ENCRYPT: Memory encryption is active + * + * The platform/OS is running with active memory encryption. This + * includes running either as a bare-metal system or a hypervisor + * and actively using memory encryption or as a guest/virtual machine + * and actively using memory encryption. + * + * Examples include SME, SEV and SEV-ES. + */ + CC_ATTR_MEM_ENCRYPT, + + /** + * @CC_ATTR_HOST_MEM_ENCRYPT: Host memory encryption is active + * + * The platform/OS is running as a bare-metal system or a hypervisor + * and actively using memory encryption. + * + * Examples include SME. + */ + CC_ATTR_HOST_MEM_ENCRYPT, + + /** + * @CC_ATTR_GUEST_MEM_ENCRYPT: Guest memory encryption is active + * + * The platform/OS is running as a guest/virtual machine and actively + * using memory encryption. + * + * Examples include SEV and SEV-ES. + */ + CC_ATTR_GUEST_MEM_ENCRYPT, + + /** + * @CC_ATTR_GUEST_STATE_ENCRYPT: Guest state encryption is active + * + * The platform/OS is running as a guest/virtual machine and actively + * using memory encryption and register state encryption. + * + * Examples include SEV-ES. + */ + CC_ATTR_GUEST_STATE_ENCRYPT, +}; + +static inline bool cc_platform_has(enum cc_attr attr) { return false; } + +#endif /* HAVE_LINUX_CC_PLATFORM_H */ +#endif From 7c0e5e3e67893fe0d6dcc7ca72b3d6348a59a0fb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 13:22:14 +0800 Subject: [PATCH 0793/2070] drm/amdkcl: Test whether drm_firmware_drivers_only() is available Signed-off-by: Leslie Shi drm/amdkcl: rework kcl implementation drm_firmware_drivers_only() Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_firmware_drivers_only.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_drv.h | 6 ++++++ include/kcl/kcl_drm_drv.h | 4 ++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c19ef6217ee28..50979fb3a1e09 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -488,6 +488,9 @@ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 +/* drm_firmware_drivers_only() is available */ +#define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 + /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 new file mode 100644 index 0000000000000..3d95cd4406fe2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.16-rc1-268-g6a2d2ddf2c34 +dnl # drm: Move nomodeset kernel parameter to the DRM subsystem +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_firmware_drivers_only(); + ], [ + AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, + [drm_firmware_drivers_only() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 38ec52be4fae2..17b5f3042758a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -149,6 +149,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER + AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_drv.h b/include/kcl/backport/kcl_drm_drv.h index dcc5c195b2d08..2fd32a57bb5d5 100644 --- a/include/kcl/backport/kcl_drm_drv.h +++ b/include/kcl/backport/kcl_drm_drv.h @@ -27,6 +27,7 @@ #ifndef __KCL_BACKPORT_KCL_DRM_DRV_H__ #define __KCL_BACKPORT_KCL_DRM_DRV_H__ +#include /* * v5.1-rc5-1150-gbd53280ef042 drm/drv: Fix incorrect resolution of merge conflict * v5.1-rc2-5-g3f04e0a6cfeb drm: Fix drm_release() and device unplug @@ -49,4 +50,9 @@ void _kcl_drm_dev_unplug(struct drm_device *dev) #define drm_dev_unplug _kcl_drm_dev_unplug #endif + +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY +#define drm_firmware_drivers_only vgacon_text_force +#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ + #endif diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h index b4e923bfa1465..0360a07613727 100644 --- a/include/kcl/kcl_drm_drv.h +++ b/include/kcl/kcl_drm_drv.h @@ -63,4 +63,8 @@ static inline bool drm_dev_is_unplugged(struct drm_device *dev) #endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ #endif /* HAVE_DRM_DEV_ENTER */ +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY +extern bool drm_firmware_drivers_only(void); +#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ + #endif From 3b154d04f0c0f612f797dd324855822f7b0f19f8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 14:00:35 +0800 Subject: [PATCH 0794/2070] drm/amdkcl: Test whether dma_resv_describe() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/dma-fence-describe.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fence.h | 4 ++++ 5 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 1376705d31822..1969d6e0f289c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -244,3 +244,21 @@ void amdkcl_fence_init(void) _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); #endif } + +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +/** + * dma_fence_describe - Dump fence describtion into seq_file + * @fence: the 6fence to describe + * @seq: the seq_file to put the textual description into + * + * Dump a textual description of the fence and it's state into the seq_file. + */ +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq) +{ + seq_printf(seq, "%s %s seq %llu %ssignalled\n", + fence->ops->get_driver_name(fence), + fence->ops->get_timeline_name(fence), fence->seqno, + dma_fence_is_signaled(fence) ? "" : "un"); +} +EXPORT_SYMBOL(dma_fence_describe); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 50979fb3a1e09..a7b5ba99bc6f2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -88,6 +88,9 @@ /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 +/* dma_fence_describe() is available */ +#define HAVE_DMA_FENCE_DESCRIBE 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 new file mode 100644 index 0000000000000..e82d65e149645 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc2-1312-ga25efb3863d0 +dnl # dma-buf: add dma_fence_describe and dma_resv_describe v2 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DESCRIBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_describe(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_DESCRIBE, 1, + [dma_fence_describe() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 17b5f3042758a..5653d25637237 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -150,6 +150,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY + AC_AMDGPU_DMA_FENCE_DESCRIBE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index addd6733ff680..e8adf7bef1c57 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -186,4 +186,8 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f); #define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL #endif +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); +#endif + #endif /* AMDKCL_FENCE_H */ From bc699eca510eaf48be9fc81a86e71c71aec5d3bc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 13 Jan 2022 12:39:35 +0800 Subject: [PATCH 0795/2070] drm/amdgpu: remove code access prime_shared_count field of struct amdgpu_bo commit "drm/amdgpu: rework dma_resv handling v3" removes the `prime_shared_count` field of struct amdgpu_bo Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 6e501f79e4947..ea223ddd36bcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -191,8 +191,6 @@ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, if (r) goto error_unreserve; - if (attach->dev->driver != adev->dev->driver) - bo->prime_shared_count++; error_unreserve: amdgpu_bo_unreserve(bo); @@ -224,8 +222,6 @@ static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, goto error; amdgpu_bo_unpin(bo); - if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) - bo->prime_shared_count--; amdgpu_bo_unreserve(bo); error: @@ -713,11 +709,6 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bo->tbo.ttm->sg = sg; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) - if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) -#endif - bo->prime_shared_count = 1; - dma_resv_unlock(resv); return &bo->tbo.base; @@ -968,8 +959,6 @@ int amdgpu_gem_prime_pin(struct drm_gem_object *obj) /* pin buffer into GTT */ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); - if (likely(ret == 0)) - bo->prime_shared_count++; amdgpu_bo_unreserve(bo); return ret; @@ -985,8 +974,6 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) return; amdgpu_bo_unpin(bo); - if (bo->prime_shared_count) - bo->prime_shared_count--; amdgpu_bo_unreserve(bo); } #endif From 2b9e27567f969505e7212c2c745831c1193db824 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Feb 2022 13:50:54 +0800 Subject: [PATCH 0796/2070] drm/amdkcl: Test whether drm_kms_helper_connector_hotplug_event() is available This is cause by fc320a6f64044f12128519ca98404b641340d136 "amdgpu: use drm_kms_helper_connector_hotplug_event" v5.15-rc2-1276-gfc320a6f6404 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-kms-helper-hotplug-event.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 687e7c6eb0f2b..a2d7876bfc981 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4136,7 +4136,11 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else if (debounce_required) { /* * HDMI disconnect detected - schedule delayed work instead of @@ -4179,7 +4183,11 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } } } @@ -4312,7 +4320,11 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else { bool ret = false; @@ -4331,7 +4343,11 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 08086b7aaa034..00f2e645dc849 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1509,7 +1509,11 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else if (param[0] == 0) { if (!aconnector->dc_link) goto unlock; @@ -1535,7 +1539,11 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } unlock: diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7b5ba99bc6f2..d2980cb4201d3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -539,6 +539,9 @@ /* drm_is_current_master() is available */ #define HAVE_DRM_IS_CURRENT_MASTER 1 +/* drm_kms_helper_connector_hotplug_event() function is available */ +#define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 + /* drm_kms_helper_is_poll_worker() is available */ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 new file mode 100644 index 0000000000000..2bb2ec7fade6e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.15-rc2-1274-g710074bb8ab0 +dnl # drm/probe-helper: add drm_kms_helper_connector_hotplug_event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_kms_helper_connector_hotplug_event(NULL); + ], [ + AC_DEFINE(HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT, 1, + [drm_kms_helper_connector_hotplug_event() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5653d25637237..40cf09fbb32f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -151,6 +151,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU__DMA_FENCE_IS_LATER AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE + AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 771f9bce33737f95ae568bca43b52715bf35bba7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Feb 2022 10:50:25 +0800 Subject: [PATCH 0797/2070] drm/amdkcl: fake macro MODULE_IMPORT_NS for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_module.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 include/kcl/kcl_module.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 477e63ef5d402..f9ce487c5d716 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -79,5 +79,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_module.h b/include/kcl/kcl_module.h new file mode 100644 index 0000000000000..2265f3bed4091 --- /dev/null +++ b/include/kcl/kcl_module.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Dynamic loading of modules into the kernel. + * + * Rewritten by Richard Henderson Dec 1996 + * Rewritten again by Rusty Russell, 2002 + */ +#ifndef _KCL_KCL_LINUX_MODULE_H_H +#define _KCL_KCL_LINUX_MODULE_H_H + +#include + +/* Copied from v5.3-11739-g3e4d890a26d5 include/linux/module.h */ +#ifndef MODULE_IMPORT_NS +#define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, #ns) +#endif + +#endif From 838f0ae65167f84d3fe2b4d5ec51ef88c6358e90 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Feb 2022 11:08:18 +0800 Subject: [PATCH 0798/2070] drm/amdkcl: wrap the code under HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE for legacy os This is caused by 5fea167ec0a13 "drm/amdkfd: use default_groups in kobj_type" v5.16-rc5-1299-g5fea167ec0a1 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 2f032a7d8e82b..3dd6f009e1c62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -929,7 +929,9 @@ static struct ip_hw_instance_attr ip_hw_attr[] = { }; static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_hw_instance); +#endif #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) @@ -961,7 +963,11 @@ static void ip_hw_instance_release(struct kobject *kobj) static const struct kobj_type ip_hw_instance_ktype = { .release = ip_hw_instance_release, .sysfs_ops = &ip_hw_instance_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_hw_instance_groups, +#else + .default_attrs = ip_hw_instance_attrs, +#endif }; /* -------------------------------------------------- */ @@ -1010,7 +1016,9 @@ static struct attribute *ip_die_entry_attrs[] = { &num_ips_attr.attr, NULL, }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ +#endif #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) @@ -1043,7 +1051,11 @@ static const struct sysfs_ops ip_die_entry_sysfs_ops = { static const struct kobj_type ip_die_entry_ktype = { .release = ip_die_entry_release, .sysfs_ops = &ip_die_entry_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_die_entry_groups, +#else + .default_attrs = ip_die_entry_attrs, +#endif }; static const struct kobj_type die_kobj_ktype = { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 4448e2889d7f1..95374e6dda6d1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -504,7 +504,9 @@ static struct attribute *procfs_queue_attrs[] = { &attr_queue_gpuid, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(procfs_queue); +#endif static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, @@ -512,7 +514,11 @@ static const struct sysfs_ops procfs_queue_ops = { static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = procfs_queue_groups, +#else + .default_attrs = procfs_queue_attrs, +#endif }; static const struct sysfs_ops procfs_stats_ops = { From 4ae4a453f64c2f5dba0eea1101f0c4715b2c5e9f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 15:08:07 +0800 Subject: [PATCH 0799/2070] drm/amdkcl: access resv field using amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ac560f3567a53..36fc570bf1328 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1786,7 +1786,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * If true, then return false as any KFD process needs all its BOs to * be resident to run successfully */ - dma_resv_for_each_fence(&resv_cursor, bo->base.resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, f) { if (amdkfd_fence_check_mm(f, current->mm) && !(place->flags & TTM_PL_FLAG_CONTIGUOUS)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 9bc473745974c..20a53a4627f81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -427,7 +427,7 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, if (!amdgpu_vm_is_bo_always_valid(vm, bo)) return; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move); if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) @@ -1782,7 +1782,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, if (!bo) return bo_va; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) { bo_va->is_xgmi = true; /* Power up XGMI if it can be potentially used */ @@ -2220,10 +2220,10 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_vm_bo_base **base; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); if (bo) { - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_vm_is_bo_always_valid(vm, bo)) ttm_bo_set_bulk_move(&bo->tbo, NULL); From 6e1747db7bac3f9b0163c29780c71c6022753a54 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 10:44:56 +0800 Subject: [PATCH 0800/2070] drm/amdkcl: replace with for_each_crtc_in_state for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a2d7876bfc981..a2b4c6e91ec8f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12758,7 +12758,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#if !defined(for_each_new_crtc_in_state) + for_each_crtc_in_state(state, crtc, new_crtc_state, i) { +#else for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->mpo_requested) drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); From 18abb8018308150ee7d6de57da43ac72b793115b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 22 Feb 2022 17:16:40 +0800 Subject: [PATCH 0801/2070] drm/amdkcl: Test whether pcie_aspm_enabled() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 | 16 ++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2a9ab2adee3c4..a8a2e4afb8b60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2082,7 +2082,11 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) return false; if (amdgpu_device_aspm_support_quirk(adev)) return false; +#ifdef HAVE_PCIE_ASPM_ENABLED return pcie_aspm_enabled(adev->pdev); +#else + return false; +#endif } /* if we get transitioned to only one device, take VGA back */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d2980cb4201d3..5378cf0f6d604 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -882,6 +882,9 @@ /* num_u32_u32 is available */ #define HAVE_MUL_U32_U32 1 +/* pcie_aspm_enabled() is available */ +#define HAVE_PCIE_ASPM_ENABLED 1 + /* pcie_bandwidth_available() is available */ #define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 40cf09fbb32f3..31576d85e1e80 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -152,6 +152,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT + AC_AMDGPU_PCIE_ASPM_ENABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 new file mode 100644 index 0000000000000..32927a35d28f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.3-rc4-1-gaccd2dd72c8f +dnl # PCI/ASPM: Add pcie_aspm_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_ASPM_ENABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pcie_aspm_enabled(NULL); + ], [ + AC_DEFINE(HAVE_PCIE_ASPM_ENABLED, 1, + [pcie_aspm_enabled() is available]) + ]) + ]) +]) From 4c34e0c61bb88075bdcfe70c44fb740a4c221252 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 21 Feb 2022 16:24:22 +0800 Subject: [PATCH 0802/2070] drm/amdkcl: Implement drm_WARN_ONCE for older versions of kernel Implement drm_WARN_ONCE function for older versions of kernel Otherwise,there are compile errors. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I4c85aa289dad6577bf04e7d1a5069af833b7a641 --- include/kcl/kcl_drm_print.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index d92e4744fea4b..a7ef405b97cdc 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -93,6 +93,13 @@ void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) _DRM_PRINTK(_once, WARNING, fmt, ##__VA_ARGS__) #endif +#ifndef drm_WARN_ONCE +#define drm_WARN_ONCE(drm, condition, format, arg...) \ + WARN_ONCE(condition, "%s %s: " format, \ + dev_driver_string((drm)->dev), \ + dev_name((drm)->dev), ## arg) +#endif + #ifndef DRM_NOTE #define DRM_NOTE(fmt, ...) \ _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) From 4feed3b98202914e8561f6aa9cce6e823b0c083a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 23 Feb 2022 10:15:32 +0800 Subject: [PATCH 0803/2070] drm/amdkcl: Test whether linux/processor.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/processor.h | 10 ++++++++++ 3 files changed, 19 insertions(+) create mode 100644 include/kcl/header/linux/processor.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5378cf0f6d604..2499529c3649f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -819,6 +819,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PGTABLE_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PROCESSOR_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_MM_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index a55316db51fb7..7fe93986495ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -96,4 +96,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # arch/cc: Introduce a function to check for confidential computing features dnl # AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) + + dnl # + dnl # v4.12-rc3-120-gfd851a3cdc19 + dnl # spin loop primitives for busy waiting + dnl # + AC_KERNEL_CHECK_HEADERS([linux/processor.h]) ]) diff --git a/include/kcl/header/linux/processor.h b/include/kcl/header/linux/processor.h new file mode 100644 index 0000000000000..873ab8368cb12 --- /dev/null +++ b/include/kcl/header/linux/processor.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PROCESSOR_H_H +#define _KCL_HEADER_LINUX_PROCESSOR_H_H + +#if defined(HAVE_LINUX_PROCESSOR_H) +#include_next +#endif + +#endif + From 634fc50a7406a02d539bd51ec30345c25b9045dd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 11 Feb 2022 11:01:14 +0800 Subject: [PATCH 0804/2070] drm/amdkfd: add removed amdgpu_amdkfd_get_vram_usage() function This is removed by v5.16-rc5-1294-gffb378fb3069 "drm/amdkfd: remove unused function" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 3d4e78849f0e3..b1be1de6bb04e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -593,6 +593,12 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, return r; } +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) +{ + + return amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); +} + int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) { int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index a78a278b4782a..3d02229fa3e7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -267,6 +267,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t *bo_size, void *metadata_buffer, size_t buffer_size, uint32_t *metadata_size, uint32_t *flags, int8_t *xcp_id); +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev); int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, uint32_t *payload); From 75eee131ee647db8923cc0f378b3f3343118169a Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 9 Feb 2022 17:07:22 -0600 Subject: [PATCH 0805/2070] drm/amdkfd: Protect BO during acquisition of its IPC handle Ensure the process of acquiring IPC handle of a BO is safe i.e. BO is not exposed from being destroyed. This is done by serializing user accesses to BO's of a process Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index c1f5f7dc6c5d7..1e3d9af012651 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -241,30 +241,33 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, if (!dev || !ipc_handle) return -EINVAL; + /* Protect kgd_mem object from being deleted by another thread */ mutex_lock(&p->mutex); pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - mutex_unlock(&p->mutex); pr_err("Failed to get pdd\n"); - return PTR_ERR(pdd); + r = PTR_ERR(pdd); + goto unlock; } kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); - mutex_unlock(&p->mutex); if (!kfd_bo) { pr_err("Failed to get bo"); - return -EINVAL; + r = -EINVAL; + goto unlock; } mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, &ipc_obj, flags); if (r) - return r; + goto unlock; memcpy(ipc_handle, ipc_obj->share_handle, sizeof(ipc_obj->share_handle)); +unlock: + mutex_unlock(&p->mutex); return r; } From ef6c8096a3255dc07fa0a4e338ca5b98609b5a53 Mon Sep 17 00:00:00 2001 From: Rui Teng Date: Mon, 28 Feb 2022 16:08:43 +0800 Subject: [PATCH 0806/2070] drm/amdkcl: Bump AMDGPU version to 5.16.0 Signed-off-by: Rui Teng Change-Id: I708952a593cbd3205227c065e98f4fee4add4a01 --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 71855ccd6e523..3feca735c2140 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.13.5) +AC_INIT(amdgpu-dkms, 5.16.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From c1342ba52eae5fb60d9cedd14c7e1774b5c79d5a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Feb 2022 16:34:52 +0800 Subject: [PATCH 0807/2070] drm/amdkcl: rework drm_aperture_remove_conflicting_pci_framebuffers() Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 153 ++---------------- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 70 +++----- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 38 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 22 +-- ...per-remove-conflicting-pci-framebuffers.m4 | 57 ------- ...ure_remove_conflicting_pci_framebuffers.m4 | 38 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- .../m4/remove-conflicting-pci-framebuffers.m4 | 28 ---- include/kcl/backport/kcl_drm_fb.h | 4 - include/kcl/kcl_drm_aperture.h | 8 - include/kcl/kcl_drm_fb.h | 57 ------- 11 files changed, 118 insertions(+), 360 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index c597046dee062..91f2508079ff1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -3,153 +3,28 @@ #ifndef HAVE_DRM_DRM_APERTURE_H #include -#include #include -#include -#include -#include - -struct drm_aperture { - struct drm_device *dev; - resource_size_t base; - resource_size_t size; - struct list_head lh; - void (*detach)(struct drm_device *dev); -}; - -static LIST_HEAD(drm_apertures); -static DEFINE_MUTEX(drm_apertures_lock); - -static bool overlap(resource_size_t base1, resource_size_t end1, - resource_size_t base2, resource_size_t end2) -{ - return (base1 < end2) && (end1 > base2); -} - - -static void drm_aperture_detach_drivers(resource_size_t base, resource_size_t size) -{ - resource_size_t end = base + size; - struct list_head *pos, *n; - - mutex_lock(&drm_apertures_lock); - list_for_each_safe(pos, n, &drm_apertures) { - struct drm_aperture *ap = - container_of(pos, struct drm_aperture, lh); - struct drm_device *dev = ap->dev; - - if (WARN_ON_ONCE(!dev)) - continue; - - if (!overlap(base, end, ap->base, ap->base + ap->size)) - continue; - - ap->dev = NULL; /* detach from device */ - list_del(&ap->lh); - - ap->detach(dev); - } - - mutex_unlock(&drm_apertures_lock); -} - - -/** - * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range - * @base: the aperture's base address in physical memory - * @size: aperture size in bytes - * @primary: also kick vga16fb if present - * @name: requesting driver name - * - * This function removes graphics device drivers which use memory range described by - * @base and @size. - * - * Returns: - * 0 on success, or a negative errno code otherwise - */ -int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, - bool primary, const char *name) -{ -#if IS_REACHABLE(CONFIG_FB) - struct apertures_struct *a; - int ret; - - a = alloc_apertures(1); - if (!a) - return -ENOMEM; - - a->ranges[0].base = base; - a->ranges[0].size = size; - - ret = remove_conflicting_framebuffers(a, name, primary); - kfree(a); - - if (ret) - return ret; -#endif - - drm_aperture_detach_drivers(base, size); - - return 0; -} -EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); +#include +#include +#include "kcl_fbmem.h" -/** - * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices - * @pdev: PCI device - * @name: requesting driver name - * - * This function removes graphics device drivers using memory range configured - * for any of @pdev's memory bars. The function assumes that PCI device with - * shadowed ROM drives a primary display and so kicks out vga16fb. - * - * Returns: - * 0 on success, or a negative errno code otherwise - */ -#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG -int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const struct drm_driver *req_driver) -#else int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -#endif { - resource_size_t base, size; - int bar, ret = 0; + int ret = 0; - for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - base = pci_resource_start(pdev, bar); - size = pci_resource_len(pdev, bar); - drm_aperture_detach_drivers(base, size); - } - - /* - * WARNING: Apparently we must kick fbdev drivers before vgacon, - * otherwise the vga fbdev driver falls over. - */ - -#ifdef HAVE_VGA_REMOVE_VGACON + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ #if IS_REACHABLE(CONFIG_FB) - -#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG - ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name); -#else -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG - ret = remove_conflicting_pci_framebuffers(pdev, name); -#else - ret = remove_conflicting_pci_framebuffers(pdev, 0, name); + ret = _kcl_remove_conflicting_pci_framebuffers(pdev, name); #endif -#endif /* HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ - -#endif - if (ret == 0) - ret = vga_remove_vgacon(pdev); +#ifdef HAVE_VGA_REMOVE_VGACON + if (ret == 0) + ret = vga_remove_vgacon(pdev); #endif - - return ret; + return ret; } EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); - -#endif /* HAVE_DRM_APERTURE_H */ +#endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 42cb82d7db3e2..8f7aec3673231 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -14,69 +14,41 @@ #include /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) - -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -{ - struct apertures_struct *ap; - bool primary = false; - int err, idx, bar; - - for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - idx++; - } - - ap = alloc_apertures(idx); - if (!ap) - return -ENOMEM; - - for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - ap->ranges[idx].base = pci_resource_start(pdev, bar); - ap->ranges[idx].size = pci_resource_len(pdev, bar); - pci_dbg(pdev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, - (unsigned long)pci_resource_start(pdev, bar), - (unsigned long)pci_resource_end(pdev, bar)); - idx++; - } - -#ifdef CONFIG_X86 - primary = pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW; -#endif - err = remove_conflicting_framebuffers(ap, name, primary); - kfree(ap); - return err; -} -#else /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ -int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) { struct apertures_struct *ap; bool primary = false; - int err = 0; + int err, idx, bar; + + for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + idx++; + } - ap = alloc_apertures(1); + ap = alloc_apertures(idx); if (!ap) return -ENOMEM; - ap->ranges[0].base = pci_resource_start(pdev, res_id); - ap->ranges[0].size = pci_resource_len(pdev, res_id); + for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + ap->ranges[idx].base = pci_resource_start(pdev, bar); + ap->ranges[idx].size = pci_resource_len(pdev, bar); + dev_dbg(&pdev->dev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, + (unsigned long)pci_resource_start(pdev, bar), + (unsigned long)pci_resource_end(pdev, bar)); + idx++; + } + #ifdef CONFIG_X86 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; #endif -#ifdef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT err = remove_conflicting_framebuffers(ap, name, primary); -#else - remove_conflicting_framebuffers(ap, name, primary); -#endif kfree(ap); return err; } -#endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ - +EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h new file mode 100644 index 0000000000000..de4bdea92fa7f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AMDKCL_KCL_FBMEM_H_ +#define _AMDKCL_KCL_FBMEM_H_ + +#include +#include + +/* Copied from include/linux/fb.h */ +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name); +#endif +static inline +int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP + /** + * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures + * handle bar 0 directly. + * as remove_conflicting_pci_framebuffers() for bar 2/5 fails on rhel7.9 + int bar, err; + + for (bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + err = remove_conflicting_pci_framebuffers(pdev, bar, name); + if (err) + return err; + } + */ + pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return remove_conflicting_pci_framebuffers(pdev, name); +#endif +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2499529c3649f..9b6c8382b4eda 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -479,15 +479,6 @@ /* whether drm_fb_helper_lastclose() is available */ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 -/* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - -/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ - -/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ - /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 @@ -936,15 +927,14 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 -/* remove_conflicting_framebuffers() returns int */ -#define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 +/* remove_conflicting_pci_framebuffers() is available */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ -/* remove_conflicting_pci_framebuffers() is available and doesn't have res_id - arg */ -#define HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG 1 +/* remove_conflicting_pci_framebuffers() wants p,i,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ -/* remove_conflicting_pci_framebuffers() is available and has res_id arg */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG */ +/* remove_conflicting_pci_framebuffers() wants p,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 deleted file mode 100644 index ee6e915098f5c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ /dev/null @@ -1,57 +0,0 @@ -dnl # -dnl # commit v5.3-rc1-541-g35616a4aa919 -dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit v4.19-rc1-110-g4d18975c78f2 - dnl # Author: Michał Mirosław - dnl # Date: Sat Sep 1 16:08:45 2018 +0200 - dnl # fbdev: add remove_conflicting_pci_framebuffers() - dnl # - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 - dnl # video/fb: Propagate error code from failing to unregister conflicting fb - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - struct task_struct; - #include - ], [ - int ret = remove_conflicting_framebuffers(NULL, NULL, false); - ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, - [remove_conflicting_framebuffers() returns int]) - ]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 new file mode 100644 index 0000000000000..50e28229344bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -0,0 +1,38 @@ +dnl # +dnl # v5.12-rc3-332-g603dc7ed917f drm/aperture: Inline fbdev conflict helpers into aperture helpers +dnl # v5.12-rc3-330-g2916059147ea drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_DRM_DRM_APERTURE_H = x ], [ + dnl # + dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # v4.19-rc1-110-g4d18975c78f2 fbdev: add remove_conflicting_pci_framebuffers() + dnl # + AC_KERNEL_TRY_COMPILE([ + struct task_struct; + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [remove_conflicting_pci_framebuffers() wants p,i,p args]) + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [remove_conflicting_pci_framebuffers() is available]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 31576d85e1e80..c4f656825ea2f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -49,7 +49,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED - AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS @@ -124,7 +124,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA - AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 deleted file mode 100644 index bde011042303f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 +++ /dev/null @@ -1,28 +0,0 @@ -dnl # -dnl # v5.3-rc1-540-g0a8459693238 -dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers -dnl # -AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ],[ - remove_conflicting_pci_framebuffers(NULL, NULL); - ],[ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG, 1, - [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) - ],[ - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ], [ - remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG, 1, - [remove_conflicting_pci_framebuffers() is available and has res_id arg]) - ]) - ]) - ]) -]) - diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index b2b3277a94e33..e14f228fc86fb 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,10 +25,6 @@ #include #include -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) -#define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers -#endif - #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) #define AMDKCL_DRM_FBDEV_GENERIC #endif diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h index e1af88ce1ba85..d4ca18d5c1792 100644 --- a/include/kcl/kcl_drm_aperture.h +++ b/include/kcl/kcl_drm_aperture.h @@ -6,18 +6,10 @@ #include -/* Copied from uapi/linux/pci_regs.h */ -#ifndef PCI_STD_NUM_BARS -#define PCI_STD_NUM_BARS 6 -#endif - /* Copied from drm/drm_aperture.h */ struct drm_device; struct pci_dev; -int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, - bool primary, const char *name); - int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); #endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index fcc020c4d6e97..bdba6873f3689 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -54,63 +54,6 @@ .fb_pan_display = drm_fb_helper_pan_display #endif -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) -#if !defined(IS_REACHABLE) -/* Copied from include/linux/kconfig.h */ -#define __ARG_PLACEHOLDER_1 0, -#define __take_second_arg(__ignored, val, ...) val - -/* - * The use of "&&" / "||" is limited in certain expressions. - * The followings enable to calculate "and" / "or" with macro expansion only. - */ -#define __and(x, y) ___and(x, y) -#define ___and(x, y) ____and(__ARG_PLACEHOLDER_##x, y) -#define ____and(arg1_or_junk, y) __take_second_arg(arg1_or_junk y, 0) - -#define __or(x, y) ___or(x, y) -#define ___or(x, y) ____or(__ARG_PLACEHOLDER_##x, y) -#define ____or(arg1_or_junk, y) __take_second_arg(arg1_or_junk 1, y) - -#define IS_REACHABLE(option) __or(IS_BUILTIN(option), \ - __and(IS_MODULE(option), __is_defined(MODULE))) -#endif /*IS_REACHABLE*/ - -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name); -#else -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, - const char *name); -#endif - -static inline int -_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name) -{ -#if IS_REACHABLE(CONFIG_FB) -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG - return remove_conflicting_pci_framebuffers(pdev, name); -#else - return remove_conflicting_pci_framebuffers(pdev, 0, name); -#endif -#else - return 0; -#endif -} -#elif !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) -static inline int -_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name) -{ -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG - return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); -#else - return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); -#endif -} -#endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - #ifndef HAVE_DRM_FB_HELPER_FILL_INFO void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper *fb_helper, From 83aef6b6d24bcef96bd19f03ae34104b7dc56ac0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Feb 2022 19:24:56 +0800 Subject: [PATCH 0808/2070] drm/amdkcl: fix kcl implementation for remove_conflicting_pci_framebuffers Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 8f7aec3673231..006b8336abdca 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -14,7 +14,8 @@ #include /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ + !defined(HAVE_DRM_DRM_APERTURE_H) int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { struct apertures_struct *ap; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h index de4bdea92fa7f..b734ca7c3d36a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -6,7 +6,8 @@ #include /* Copied from include/linux/fb.h */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ + !defined(HAVE_DRM_DRM_APERTURE_H) extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); #endif From 86263313ed01c2405e7c23d157a42b33ab1240a8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Feb 2022 18:44:26 +0800 Subject: [PATCH 0809/2070] drm/amdkcl: Add the PSR related macro definition Add DP_PSR2_SU_Y_GRANULARITY definition for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I3badfeb16886544c2548597e2f1eb085e58e7c5d --- include/kcl/kcl_drm_dp_helper.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index f32ad22d172db..60b18feee18f4 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -296,6 +296,4 @@ enum drm_dp_phy { # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ #endif - - #endif /* _KCL_DRM_DP_HELPER_H_ */ From 7a393488f65bb9a1c9ed70af80b2723c6ed2419e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:59:11 +0800 Subject: [PATCH 0810/2070] drm/amdkcl: drm/amd/display: Use adjusted DCN301 watermarks the patch was not applied completely in the rebase. Original patch is 808643ea56a2 - drm/amd/display: Use adjusted DCN301 watermarks Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- .../gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 483f665dd0a31..ef02cf0045ba2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1398,7 +1398,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, From 0c66b3e4cb3bfc214f8e0388fcad4b6c6ff5b540 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 15:55:07 +0800 Subject: [PATCH 0811/2070] drm/amdkcl: undef REG_SET/REG_GET in display part fix warning for REG_SET/REG_GET redefined in display/dmub part Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index 123d1704670ee..b314e60714ee2 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -28,6 +28,14 @@ #include "../inc/dmub_cmd.h" +#ifdef REG_SET +#undef REG_SET +#endif + +#ifdef REG_GET +#undef REG_GET +#endif + struct dmub_srv; /* Register offset and field lookup. */ From 60209a6d3487a283d86aacd940378f67bb3012d2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 13:55:12 +0800 Subject: [PATCH 0812/2070] drm/amdkcl: move __dma_resv_make_exclusive near to its caller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix warning: ‘__dma_resv_make_exclusive’ defined but not used [-Wunused-function] Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index ea223ddd36bcf..ad6c11800333c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -93,6 +93,7 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, #endif #if defined(AMDKCL_AMDGPU_DMABUF_OPS) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -135,7 +136,6 @@ __dma_resv_make_exclusive(struct dma_resv *obj) return -ENOMEM; } -#if defined(HAVE_DMA_BUF_OPS_LEGACY) /** * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation * @dma_buf: Shared DMA buffer From 6f1a00549118d8156abbe6d55df2084af2052775 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:19:08 +0800 Subject: [PATCH 0813/2070] drm/amdkcl: fix warning in amdgpu_ras.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:133:13: warning: ‘amdgpu_register_bad_pages_mca_notifier’ declared ‘static’ but never defined [-Wunused-function] 133 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:138:38: warning: ‘mce_adev_list’ defined but not used [-Wunused-variable] 138 | static struct mce_notifier_adev_list mce_adev_list; | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:44:13: warning: ‘notifier_registered’ defined but not used [-Wunused-variable] 44 | static bool notifier_registered; | ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a89f34efd15f5..8a95c73a6deae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -46,8 +46,10 @@ #ifdef CONFIG_X86_MCE_AMD #include +#ifdef HAVE_SMCA_UMC_V2 static bool notifier_registered; #endif +#endif static const char *RAS_FS_NAME = "ras"; const char *ras_error_string[] = { @@ -132,11 +134,6 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define BYPASS_ALLOCATED_ADDRESS 0x0 #define BYPASS_INITIALIZATION_ADDRESS 0x1 -#ifdef HAVE_SMCA_UMC_V2 -static bool notifier_registered = false; -static void amdgpu_register_bad_pages_mca_notifier(void); -#endif - enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -154,6 +151,7 @@ static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev); static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev); #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); static void amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev); @@ -163,6 +161,7 @@ struct mce_notifier_adev_list { }; static struct mce_notifier_adev_list mce_adev_list; #endif +#endif void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { From 0119f7b3b5391c084a50a26d019240e4c5f00e49 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:24:50 +0800 Subject: [PATCH 0814/2070] drm/amdkcl: drop unused var in amdgpu_vkms_vblank_simulate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c: In function ‘amdgpu_vkms_vblank_simulate’: drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c:48:24: warning: unused variable ‘adev’ [-Wunused-variable] 48 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); | ^~~~ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 0037748caf1a6..5ecc9892fd657 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -46,7 +46,6 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) { struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); struct drm_crtc *crtc = &amdgpu_crtc->base; - struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); u64 ret_overrun; bool ret; From 1a801bee667e5db81829c1d8a59c48f476bea8c7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 15:53:44 +0800 Subject: [PATCH 0815/2070] drm/amdkcl: fix warning in amdgpu_display_get_fb_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:1153:44: warning: passing argument 1 of ‘drm_gem_fb_get_obj’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 1153 | rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index bac87e4a85709..c481ed6f0fe9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1175,7 +1175,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&((struct amdgpu_framebuffer *)amdgpu_fb)->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { From 28e84022cdabff9b40a0096ba07eded84323c567 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Mar 2022 16:24:54 -0500 Subject: [PATCH 0816/2070] drm/amdkfd: Fixup rebase errors in CRIU code Signed-off-by: Felix Kuehling Acked-by: Guchun Chen Reviewed-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 14 +++++++------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 +++++++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 ------------------ 5 files changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2983923985a0f..1272009fabe13 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1205,7 +1205,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - args->va_addr, args->size, cpuva, mem_type); + args->va_addr, args->size, cpuva, mem_type, -1); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1951,11 +1951,11 @@ static uint32_t get_process_num_bos(struct kfd_process *p) /* Run over all PDDs of the process */ for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; - void *mem; + struct kfd_bo *buf_obj; int id; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { - struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kgd_mem *kgd_mem = (struct kgd_mem *)buf_obj->mem; if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) num_of_bos++; @@ -2021,7 +2021,7 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct kfd_criu_bo_priv_data *bo_privs; struct file **files = NULL; int ret = 0, pdd_index, bo_index = 0, id; - void *mem; + struct kfd_bo *buf_obj; bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); if (!bo_buckets) @@ -2044,12 +2044,12 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct amdgpu_bo *dumper_bo; struct kgd_mem *kgd_mem; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { struct kfd_criu_bo_bucket *bo_bucket; struct kfd_criu_bo_priv_data *bo_priv; int i, dev_idx = 0; - kgd_mem = (struct kgd_mem *)mem; + kgd_mem = (struct kgd_mem *)buf_obj->mem; dumper_bo = kgd_mem->bo; /* Skip checkpointing BOs that are used for Trap handler diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 1e3d9af012651..e0a41feb7966f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -147,7 +147,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_read_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0); + va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 1e014e6ead1a2..7b2e344934fef 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1169,7 +1169,8 @@ void kfd_process_notifier_release_internal(struct kfd_process *p); int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type); + unsigned int mem_type, + int preferred_id); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 95374e6dda6d1..32fc14bd8b225 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1938,7 +1938,8 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type) + unsigned int mem_type, + int preferred_id) { int handle; struct kfd_bo *buf_obj; @@ -1960,7 +1961,11 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; - handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + if (preferred_id < 0) + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + else + handle = idr_alloc(&pdd->alloc_idr, buf_obj, preferred_id, + preferred_id + 1, GFP_KERNEL); if (handle < 0) kfree(buf_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 9f2eff1f0fb94..f79b4ebbda6a5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -4087,24 +4087,6 @@ int kfd_criu_resume_svm(struct kfd_process *p) set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; set_attr[num_attrs].value = ~set_flags; - /* CLR_FLAGS is not available via get_attr during checkpoint but - * it needs to be inserted before restoring the ranges so - * allocate extra space for it before calling set_attr - */ - set_attr_size = sizeof(struct kfd_ioctl_svm_attribute) * - (num_attrs + 1); - set_attr = krealloc(set_attr, set_attr_size, - GFP_KERNEL); - if (!set_attr) { - ret = -ENOMEM; - goto exit; - } - - memcpy(set_attr, criu_svm_md->data.attrs, num_attrs * - sizeof(struct kfd_ioctl_svm_attribute)); - set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; - set_attr[num_attrs].value = ~set_flags; - ret = svm_range_set_attr(p, mm, criu_svm_md->data.start_addr, criu_svm_md->data.size, num_attrs + 1, set_attr); From b42841624877b116941fc12a0b13927b6ed0614f Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Mar 2022 16:47:00 -0500 Subject: [PATCH 0817/2070] drm/amdkcl: Add support for kernels with MIGRATE_PFN_LOCKED MIGRATE_PFN_LOCKED was removed in commit ab09243aa95a ("mm/migrate.c: remove MIGRATE_PFN_LOCKED"). This patch restores compatibility with older kernels that still require this bit. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Acked-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_migrate.h | 14 ++++++++++++++ 3 files changed, 17 insertions(+) create mode 100644 include/kcl/backport/kcl_migrate.h diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 458d1611ed3ae..9ed4a2e174ddf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -319,6 +319,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); svm_migrate_get_vram_page(prange, migrate->dst[i]); migrate->dst[i] = migrate_pfn(migrate->dst[i]); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; mpages++; } spage = migrate_pfn_to_page(migrate->src[i]); @@ -666,6 +667,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, dst[i] >> PAGE_SHIFT, page_to_pfn(dpage)); migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; j++; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f9ce487c5d716..5ddbc172de9d3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -34,6 +34,7 @@ #include #include #include +#include #include #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ #include diff --git a/include/kcl/backport/kcl_migrate.h b/include/kcl/backport/kcl_migrate.h new file mode 100644 index 0000000000000..55a817d8cf2aa --- /dev/null +++ b/include/kcl/backport/kcl_migrate.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_MIGRATE_H +#define _KCL_BACKPORT_KCL_MIGRATE_H + +#include + +/* Compatibility with kernels before ab09243aa95a ("mm/migrate.c: remove + * MIGRATE_PFN_LOCKED") + */ +#ifndef MIGRATE_PFN_LOCKED +#define MIGRATE_PFN_LOCKED 0 +#endif + +#endif From c362ab39dc8fdf38a2040efc1b8947fac7737f11 Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Mon, 13 Dec 2021 16:28:57 -0600 Subject: [PATCH 0818/2070] drm/amdkfd: explicitly create/destroy queue attributes under /sys This patch was not applied completely in the rebase. Original patch description follows. When application is about finish it destroys queues it has created by an ioctl. Driver deletes queue entry(/sys/class/kfd/kfd/proc/pid/queues/queueid/) which is directory including this queue all attributes. Low level kernel code deletes all attributes under this directory. The lock from kernel is on queue entry, not its attributes. At meantime another user space application can read the attributes. There is possibility that the application can hold/read the attributes while kernel is deleting the queue entry, cause the application have invalid memory access, then killed by kernel. Driver changes: explicitly create/destroy each attribute for each queue, let kernel put lock on each attribute too. Signed-off-by: Xiaogang Chen Reviewed-by: Felix Kuehling Acked-by: Guchun Chen Reviewed-by: Xiaogang.Chen --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 30 ------------------------ 1 file changed, 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 32fc14bd8b225..df2e34ffbf0ac 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -483,42 +483,12 @@ static ssize_t kfd_sysfs_counters_show(struct kobject *kobj, return 0; } -static struct attribute attr_queue_size = { - .name = "size", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_type = { - .name = "type", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_gpuid = { - .name = "gpuid", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute *procfs_queue_attrs[] = { - &attr_queue_size, - &attr_queue_type, - &attr_queue_gpuid, - NULL -}; -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE -ATTRIBUTE_GROUPS(procfs_queue); -#endif - static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, }; static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE - .default_groups = procfs_queue_groups, -#else - .default_attrs = procfs_queue_attrs, -#endif }; static const struct sysfs_ops procfs_stats_ops = { From 53fee571623317a77d67c7d80c871017d1e9097b Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 4 Mar 2022 19:11:53 -0500 Subject: [PATCH 0819/2070] drm/amdkfd: Hold mmap_read_lock for find_vma find_vma throws a warning if them mmap_read_lock is not held. Hold the lock as long as the vma returned by the call is needed. Once the lock is dropped, the VMA can become invalid. Signed-off-by: Felix Kuehling Reviewed-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1272009fabe13..2c3f57c1b3d8d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1147,12 +1147,14 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, * space will be oblivious of this and will use this doorbell * BO as a regular userptr BO */ + mmap_read_lock(current->mm); vma = find_vma(current->mm, args->mmap_offset); if (vma && args->mmap_offset >= vma->vm_start && (vma->vm_flags & VM_IO)) { unsigned long pfn; err = follow_pfn(vma, args->mmap_offset, &pfn); + mmap_read_unlock(current->mm); if (err) { pr_debug("Failed to get PFN: %ld\n", err); goto err_unlock; @@ -1161,6 +1163,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; offset = (pfn << PAGE_SHIFT); } else { + mmap_read_unlock(current->mm); if (offset & (PAGE_SIZE - 1)) { pr_debug("Unaligned userptr address:%llx\n", offset); From bfdea7cbddd465ab02af4b25aebb8b205752dc12 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Mar 2022 12:03:23 +0800 Subject: [PATCH 0820/2070] drm/amdkcl: fix warning for unused variable in amdgpu_connector.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_update_scratch_regs’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:252:6: warning: unused variable ‘i’ [-Wunused-variable] 252 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_find_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:275:6: warning: unused variable ‘i’ [-Wunused-variable] 275 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_best_single_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:393:6: warning: unused variable ‘i’ [-Wunused-variable] 393 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_dvi_detect’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1148:7: warning: unused variable ‘i’ [-Wunused-variable] 1148 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_dvi_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1204:6: warning: unused variable ‘i’ [-Wunused-variable] 1204 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_encoder_get_dp_bridge_encoder_id’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1372:6: warning: unused variable ‘i’ [-Wunused-variable] 1372 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_encoder_is_hbr2’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1397:6: warning: unused variable ‘i’ [-Wunused-variable] 1397 | int i; | ^ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 287ea6da5a87f..afa58eb51172d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -235,7 +235,9 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif best_encoder = connector_funcs->best_encoder(connector); @@ -258,7 +260,9 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -349,7 +353,9 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif /* pick the first one */ #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS @@ -1136,7 +1142,9 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1191,7 +1199,9 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1398,7 +1408,9 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1423,7 +1435,9 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif bool found = false; #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS From 5e3351ef2a42e03ab5aa94d965af5649acdfc7c6 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 3 Mar 2022 14:48:19 -0500 Subject: [PATCH 0821/2070] drm/amdkfd: CRIU Add support for IPC handles Add support for checkpointing/restoring BOs with IPC handles. Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 110 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 103 +++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 + 6 files changed, 191 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 3d02229fa3e7c..2ef9ac31f31e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -391,7 +391,9 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, - uint32_t flags); + uint32_t flags, + uint32_t *restore_handle); + void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c4eb5f4dc9b93..3302d812dda52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2780,7 +2780,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, - uint32_t flags) + uint32_t flags, + uint32_t *restore_handle) { struct dma_buf *dmabuf; int r = 0; @@ -2801,7 +2802,7 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, goto unlock_out; } - r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags); + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); if (r) dma_buf_put(dmabuf); else diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2c3f57c1b3d8d..bd17283cc9f9e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1709,7 +1709,7 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, - &args->mmap_offset, &args->flags); + &args->mmap_offset, &args->flags, false); if (r) pr_err("Failed to import IPC handle\n"); @@ -2106,8 +2106,18 @@ static int criu_checkpoint_bos(struct kfd_process *p, bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; } - pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" + if (kgd_mem->ipc_obj) { + bo_priv->ipc_flags = kgd_mem->ipc_obj->flags; + bo_priv->is_imported = kgd_mem->is_imported; + + memcpy(bo_priv->ipc_share_handle, + kgd_mem->ipc_obj->share_handle, + sizeof(kgd_mem->ipc_obj->share_handle)); + } + + pr_debug("[%d]bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx" "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", + bo_index, bo_bucket->size, bo_bucket->addr, bo_bucket->offset, @@ -2415,6 +2425,93 @@ static int criu_restore_devices(struct kfd_process *p, return ret; } +static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, + struct kfd_criu_bo_bucket *bo_bucket, + struct kfd_criu_bo_priv_data *bo_priv, + struct kgd_mem **kgd_mem) +{ + uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); + struct kfd_dev *dev = pdd->dev; + struct kfd_bo *kfd_bo; + int ret, idr_handle; + uint64_t offset; + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, &offset, NULL, true); + if (ret) { + unsigned int mem_type; + + if (ret != -EINVAL) { + pr_err("Failed to import IPC handle ret:%d\n", ret); + return ret; + } + + /* kfd_ipc_import_handle returns -EINVAL if the ipc share_handle does not exist. + * In that case create a new BO and create a new ipc share_handle by calling + * amdgpu_amdkfd_gpuvm_export_ipc_obj. + */ + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, + bo_bucket->size, pdd->drm_priv, + NULL, kgd_mem, &offset, + bo_bucket->alloc_flags, true); + if (ret) { + pr_err("Could not create the BO\n"); + return ret; + } + + pr_debug("New IPC BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", + bo_bucket->size, bo_bucket->addr, offset); + + mem_type = bo_bucket->alloc_flags & + (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, + bo_bucket->size, 0, mem_type, + bo_priv->idr_handle); + if (idr_handle < 0) { + pr_err("Could not allocate idr\n"); + + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, pdd->drm_priv, + NULL); + return -ENOMEM; + } + + ret = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, *kgd_mem, + &(*kgd_mem)->ipc_obj, bo_priv->ipc_flags, + bo_priv->ipc_share_handle); + if (ret == -EINVAL) { + /* This is a race condition. The other process that owns this same IPC + * handle created the handle before this process. Delete BO and re-use + * import IPC handle created by the other process. + */ + ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, + pdd->drm_priv, NULL); + if (ret) + return ret; + + kfd_process_device_remove_obj_handle(pdd, idr_handle); + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, + bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, + &offset, NULL, true); + if (ret) + return ret; + } + } + + kfd_bo = kfd_process_device_find_bo(pdd, bo_priv->idr_handle); + *kgd_mem = kfd_bo->mem; + (*kgd_mem)->is_imported = bo_priv->is_imported; + + bo_bucket->restored_offset = offset; + if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) + /* Update the VRAM usage count */ + WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + + return 0; +} + static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, struct kfd_criu_bo_bucket *bo_bucket, struct kfd_criu_bo_priv_data *bo_priv, @@ -2489,11 +2586,14 @@ static int criu_restore_bo(struct kfd_process *p, struct kfd_criu_bo_priv_data *bo_priv, struct file **file) { + const uint32_t zero_handle[4] = { 0, 0, 0, 0 }; struct kfd_process_device *pdd; struct kgd_mem *kgd_mem; int ret; int j; + BUILD_BUG_ON(sizeof_field(struct kfd_ipc_obj, share_handle) != sizeof(zero_handle)); + pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, bo_priv->idr_handle); @@ -2504,7 +2604,11 @@ static int criu_restore_bo(struct kfd_process *p, return -ENODEV; } - ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (memcmp(bo_priv->ipc_share_handle, zero_handle, sizeof(zero_handle))) + ret = criu_restore_memory_of_gpu_ipc(pdd, bo_bucket, bo_priv, &kgd_mem); + else + ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index e0a41feb7966f..6021077f7199b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -42,7 +42,7 @@ static struct kfd_ipc_handles { #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, - uint32_t flags) + uint32_t flags, uint32_t *restore_handle) { struct kfd_ipc_obj *obj; @@ -50,6 +50,30 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, if (!obj) return -ENOMEM; + if (restore_handle) + memcpy(obj->share_handle, restore_handle, sizeof(obj->share_handle)); + else + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + if (restore_handle) { + struct kfd_ipc_obj *entry; + + /* When doing CRIU restore, we may have a race condition where two processes try + * to insert handles with the same key. Make sure this key does not already exist + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)], node) { + if (!memcmp(entry->share_handle, + obj->share_handle, + sizeof(entry->share_handle))) { + mutex_unlock(&kfd_ipc_handles.lock); + kfree(obj); + return -EINVAL; + } + } + } + /* The initial ref belongs to the allocator process. * The IPC object store itself does not hold a ref since * there is no specific moment in time where that ref should @@ -59,12 +83,9 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, */ kref_init(&obj->ref); obj->dmabuf = dmabuf; - get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); obj->flags = flags; - mutex_lock(&kfd_ipc_handles.lock); - hlist_add_head(&obj->node, - &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); mutex_unlock(&kfd_ipc_handles.lock); if (ipc_obj) @@ -114,10 +135,10 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, uint32_t gpu_id, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) + uint64_t *mmap_offset, bool restore) { int r; - void *mem; + struct kgd_mem *mem; uint64_t size; int idr_handle; struct kfd_process_device *pdd = NULL; @@ -128,44 +149,34 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, if (!dev) return -EINVAL; - mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; + if (restore) + idr_handle = GET_IDR_HANDLE(*handle); + else + idr_handle = -1; pdd = kfd_bind_process_to_device(dev, p); - if (IS_ERR(pdd)) { - r = PTR_ERR(pdd); - goto err_read_unlock; - } + if (IS_ERR(pdd)) + return PTR_ERR(pdd); r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, - va_addr, pdd->drm_priv, - (struct kgd_mem **)&mem, &size, - mmap_offset); + va_addr, pdd->drm_priv, + &mem, &size, mmap_offset); if (r) - goto err_read_unlock; + return r; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0, -1); + va_addr, size, 0, 0, idr_handle); if (idr_handle < 0) { r = -EFAULT; goto err_free; } - amdgpu_read_unlock(dev->ddev); - mutex_unlock(&p->mutex); - *handle = MAKE_HANDLE(gpu_id, idr_handle); return 0; err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); -err_read_unlock: - amdgpu_read_unlock(dev->ddev); -err_unlock: - mutex_unlock(&p->mutex); return r; } @@ -181,8 +192,19 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, if (!dmabuf) return -EINVAL; + mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, - va_addr, handle, mmap_offset); + va_addr, handle, mmap_offset, false); + + amdgpu_read_unlock(dev->ddev); + +err_unlock: + mutex_unlock(&p->mutex); + dma_buf_put(dmabuf); return r; } @@ -190,7 +212,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, uint32_t *pflags) + uint64_t *mmap_offset, uint32_t *pflags, bool restore) { int r; struct kfd_ipc_obj *entry, *found = NULL; @@ -214,15 +236,32 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); + if (!restore) { + mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; + } + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->dmabuf, found, - va_addr, handle, mmap_offset); + va_addr, handle, mmap_offset, + restore); + if (!restore) { + amdgpu_read_unlock(dev->ddev); + mutex_unlock(&p->mutex); + } if (r) goto error_unref; - *pflags = found->flags; + if (pflags) + *pflags = found->flags; + return r; +err_unlock: + mutex_unlock(&p->mutex); + error_unref: kfd_ipc_obj_put(&found); return r; @@ -260,7 +299,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, - &ipc_obj, flags); + &ipc_obj, flags, NULL); if (r) goto unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 7915b8cad13db..be0bf2b388194 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -42,7 +42,7 @@ struct kfd_ipc_obj { int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, uint32_t *pflags); + uint64_t *mmap_offset, uint32_t *pflags, bool restore); int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, @@ -52,7 +52,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t flags); int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, - uint32_t flags); + uint32_t flags, uint32_t *restore_handle); void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 7b2e344934fef..46f24b00c1e40 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1327,6 +1327,11 @@ struct kfd_criu_bo_priv_data { uint64_t user_addr; uint32_t idr_handle; uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; + + /* IPC related variables */ + uint32_t is_imported; + uint32_t ipc_flags; + uint32_t ipc_share_handle[4]; }; /* From d8511ae8405f4cb32508a41d2db6b28866d61d9b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 9 Mar 2022 15:54:38 +0800 Subject: [PATCH 0822/2070] drm/amdkcl: Add the sizeof_field() macro definition Add the sizeof_field() macro definiton for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I94d722db8c9fbfed92f07a3bd926e4fdaa7a8de3 --- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/kcl_stddef.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_stddef.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5ddbc172de9d3..d842f1a2ce76a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -81,5 +81,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_stddef.h b/include/kcl/kcl_stddef.h new file mode 100644 index 0000000000000..dc455e1423ab1 --- /dev/null +++ b/include/kcl/kcl_stddef.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_STDDEF_H_ +#define _KCL_KCL_STDDEF_H_ + +#include +#ifndef sizeof_field +/** + * sizeof_field() - Report the size of a struct field in bytes + * + * @TYPE: The structure containing the field of interest + * @MEMBER: The field to return the size of + */ +#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) +#endif + +#endif From 7ca0c21073ef95892d4e898ea17acb509931eff2 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 10 Mar 2022 12:34:39 -0500 Subject: [PATCH 0823/2070] drm/amdkfd: Fix incorrect identation and compile warning Fix incorrect indentation and compile warning Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index bd17283cc9f9e..0a6eaa653acba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1253,7 +1253,6 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; struct kfd_bo *buf_obj; - struct kfd_dev *dev; int ret; uint64_t size = 0; From d06cdbe2b8e1fab3b2f12c5ad9626e872ea98c7e Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Mon, 14 Mar 2022 14:41:36 -0400 Subject: [PATCH 0824/2070] drm/amdkfd: fix a bug on creating gpuid sysfs entry Correct guid to gpuid to make kfd_procfs_queue_show() return a valid value. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 46f24b00c1e40..3b45fd2697d7c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -650,7 +650,7 @@ struct queue { /* procfs */ struct kobject kobj; - struct attribute attr_guid; + struct attribute attr_gpuid; struct attribute attr_size; struct attribute attr_type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index df2e34ffbf0ac..86c0e5e18cf92 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -530,7 +530,7 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } - kfd_sysfs_create_file(&q->kobj, &q->attr_guid, "guid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_gpuid, "gpuid"); kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); @@ -678,7 +678,7 @@ void kfd_procfs_del_queue(struct queue *q) if (!q) return; - sysfs_remove_file(&q->kobj, &q->attr_guid); + sysfs_remove_file(&q->kobj, &q->attr_gpuid); sysfs_remove_file(&q->kobj, &q->attr_size); sysfs_remove_file(&q->kobj, &q->attr_type); From 42fb24931c2b06a06b82df0ae3ff4268c8b1b423 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 14 Mar 2022 11:44:14 +0800 Subject: [PATCH 0825/2070] drm/amdkcl: fix test for drm_gem_object_put Signed-off-by: Flora Cui Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/dkms/config/config.h | 8 ++--- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 29 ++++++++----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- include/kcl/backport/kcl_drm_gem.h | 4 +-- include/kcl/kcl_drm_gem.h | 8 ++--- 5 files changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9b6c8382b4eda..45dcd4a9f578f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -500,11 +500,11 @@ /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 -/* drm_gem_object_put_locked() is available */ -#define HAVE_DRM_GEM_OBJECT_PUT_LOCKED 1 +/* drm_gem_object_put() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT 1 -/* drm_gem_object_put_unlocked() is available */ -/* #undef HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED */ +/* drm_gem_object_put() is exported */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index f73dc8440b756..c4d2a03ec81c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -3,25 +3,20 @@ dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlock dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED], [ +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_gem_object_put_locked], [drivers/gpu/drm/drm_gem.c], - [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_LOCKED, 1, - [drm_gem_object_put_locked() is available]) + AC_KERNEL_TRY_COMPILE([ + #include ], [ - dnl # - dnl # commit v4.10-rc8-1302-ge6b62714e87c - dnl # drm: Introduce drm_gem_object_{get,put}() - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_gem_object_put_unlocked(NULL); - ], [drm_gem_object_put_unlocked], [drivers/gpu/drm/drm_gem.c], [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED, 1, - [drm_gem_object_put_unlocked() is available]) + drm_gem_object_put(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, + [drm_gem_object_put() is available]) + + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_object_put], + [drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c4f656825ea2f..2d1c9fab64ad5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,7 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED - AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED + AC_AMDGPU_DRM_GEM_OBJECT_PUT AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE diff --git a/include/kcl/backport/kcl_drm_gem.h b/include/kcl/backport/kcl_drm_gem.h index 373e3719b4c57..6f04e71ca35fd 100644 --- a/include/kcl/backport/kcl_drm_gem.h +++ b/include/kcl/backport/kcl_drm_gem.h @@ -36,8 +36,8 @@ #include -#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) -#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) #define drm_gem_object_put _kcl_drm_gem_object_put #endif #endif diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index a0f90deb18b06..cded9b424aa89 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,13 +35,14 @@ #define __KCL_KCL_DRM_GEM_H__ #include -#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) -#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) static inline void _kcl_drm_gem_object_put(struct drm_gem_object *obj) { return drm_gem_object_put_unlocked(obj); } +#endif #else static inline void drm_gem_object_put(struct drm_gem_object *obj) @@ -54,7 +55,6 @@ drm_gem_object_get(struct drm_gem_object *obj) { kref_get(&obj->refcount); } -#endif -#endif /* HAVE_DRM_GEM_OBJECT_PUT_LOCKED */ +#endif /* HAVE_DRM_GEM_OBJECT_PUT */ #endif From becdca37f15e1e4263a18b57d1b7bd2c8d1ccfc6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:17:42 +0800 Subject: [PATCH 0826/2070] drm/amdkcl: fix CC CFLAGS check Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +-- .../drm/amd/dkms/m4/kernel_single_target.m4 | 25 ++++++++----------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2d1c9fab64ad5..27c1c4ef29f20 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -411,7 +411,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) AS_IF( - [AC_TRY_COMMAND($CC $CFLAGS -o conftest.o conftest.c) >/dev/null && AC_TRY_COMMAND([$2])], + [AC_TRY_COMMAND(eval $CC $CFLAGS) > /dev/null && AC_TRY_COMMAND([$2])], [$3], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] ) @@ -426,7 +426,7 @@ dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [test -s conftest.o], + [test -s conftest.o || test -s .tmp_conftest.o], [$3], [$4]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index b4af835c8928f..7fd86cef1e099 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -3,28 +3,25 @@ dnl # extract cc, cflags, cppflags dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ AS_IF([test -s .conftest.o.cmd], [ - _base_cflags="-DKBUILD_BASENAME='\"conftest\"' -DKBUILD_MODNAME='\"conftest\"'" - _base_dir=$(basename $PWD) _conftest_cmd=$(head -1 .conftest.o.cmd) CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CFLAGS=$(echo $_conftest_cmd | \ - sed -e 's| -|\n&|g' | \ - sed -e "s|\./|${LINUX_OBJ}/|" \ - -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|" \ - -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|" \ - -e '/conftest/d' \ - -e '/KBUILD_/d' \ - -e "/$_base_dir/d" | \ - xargs) + cut -d ' ' -f 4- | \ + sed -e "s|\./|${LINUX_OBJ}/|g" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ + -e "s|$PWD|\${PWD}|g") + CPPFLAGS=$(echo $CFLAGS | \ + cut -d ';' -f 1 | \ sed 's| -|\n&|g' | \ - sed -n '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + sed -n -e '/conftest/d' \ + -e '/KBUILD/d' \ + -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ xargs) - CFLAGS="$CFLAGS $_base_cflags" - CPPFLAGS="$CPPFLAGS $_base_cflags" - AC_SUBST(CC) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) From 48746269501e3034fd52c3dbefb7574f0099f914 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:28:03 +0800 Subject: [PATCH 0827/2070] drm/amdkcl: add missing AC_AMDGPU_PM_SUSPEND_TARGET_STATE Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 27c1c4ef29f20..304cf05daaf53 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -152,6 +152,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED + AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2cbab2d88faaf8ba02c35cfbee381d8073c36d55 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Mar 2022 13:15:35 +0800 Subject: [PATCH 0828/2070] drm/amdkcl: Test whether smca_get_bank_type() is exported v2: add CONFIG_X86_MCE_AMD guard v3: remove CONFIG_X86 guard v4: improve test for struct smca_bank and kcl implementation of smca_get_bank_type() Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 42 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 | 27 ++++++++++++ include/kcl/kcl_mce.h | 13 +++++- 6 files changed, 88 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c new file mode 100644 index 0000000000000..30e62d94fbead --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * (c) 2005-2016 Advanced Micro Devices, Inc. + * + * Written by Jacob Shin - AMD, Inc. + * Maintained by: Borislav Petkov + * + * All MC4_MISCi registers are shared between cores on a node. + */ + + +#ifdef CONFIG_X86_MCE_AMD +#include + +#ifndef HAVE_SMCA_GET_BANK_TYPE + +/* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ +#ifdef HAVE_SMCA_BANK_STRUCT +enum smca_bank_types smca_get_bank_type(unsigned int bank) +{ + struct smca_bank *b; + + if (bank >= MAX_NR_BANKS) + return N_SMCA_BANK_TYPES; + + b = &smca_banks[bank]; + if (!b->hwid) + return N_SMCA_BANK_TYPES; + + return b->hwid->bank_type; +} +#else +int smca_get_bank_type(unsigned int bank) +{ + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; +} +#endif /* HAVE_SMCA_BANK_STRUCT */ +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif /* HAVE_SMCA_GET_BANK_TYPE */ + +#endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d842f1a2ce76a..43a3040bfaf35 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -82,4 +82,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 45dcd4a9f578f..a4cfe0db97b12 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -948,6 +948,9 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 +/* smca_get_bank_type() is available */ +#define HAVE_SMCA_GET_BANK_TYPE 1 + /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ @@ -1030,6 +1033,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* struct smca_bank is available */ +/* #undef HAVE_STRUCT_SMCA_BANK */ + /* struct xarray is available */ #define HAVE_STRUCT_XARRAY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 304cf05daaf53..355f24b21adf3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -153,6 +153,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED AC_AMDGPU_PM_SUSPEND_TARGET_STATE + AC_AMDGPU_SMCA_GET_BANK_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 new file mode 100644 index 0000000000000..2ed1eef7d5149 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # +dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([smca_get_bank_type], + [arch/x86/kernel/cpu/mce/amd.c], [ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE, 1, + [smca_get_bank_type() is available]) + ], [ + dnl # + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 5418ec9351e36..fee8c17c7d8fc 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -2,7 +2,7 @@ #ifndef AMDKCL_MCE_H #define AMDKCL_MCE_H -#ifdef CONFIG_X86 +#ifdef CONFIG_X86_MCE_AMD #include @@ -11,5 +11,14 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#endif /* CONFIG_X86 */ + +#if !defined(HAVE_SMCA_GET_BANK_TYPE) && defined(HAVE_SMCA_BANK_STRUCT) +enum smca_bank_types smca_get_bank_type(unsigned int bank); +#endif + +#ifndef HAVE_MCE_PRIO_UC +#define MCE_PRIO_UC MCE_PRIO_SRAO +#endif + +#endif /* CONFIG_X86_MCE_AMD */ #endif From 1b7f702466d959869ed7a9fe8a0c6707a2f9da90 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Mar 2022 14:56:32 +0800 Subject: [PATCH 0829/2070] drm/amdkcl: Test whether enum MCE_PRIO_UC is available v2: define MCE_PRIO_UC macro if HAVE_MCE_PRIO_UC is not defined Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 15 +++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a4cfe0db97b12..77c1a9cf2ab98 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -837,6 +837,9 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 +/* enum MCE_PRIO_UC is available */ +#define HAVE_MCE_PRIO_UC 1 + /* memalloc_nofs_{save,restore}() are available */ #define HAVE_MEMALLOC_NOFS_SAVE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 355f24b21adf3..217ef3d6eb5fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -154,6 +154,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_ASPM_ENABLED AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE + AC_AMDGPU_MCE_PRIO_UC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 new file mode 100644 index 0000000000000..ac2a78006ea2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # +dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again +dnl # +AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) +]) From bf6b7c74d3bdffd78aff474f9e2a831ee351d06d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:28:28 +0800 Subject: [PATCH 0830/2070] drm/amdkcl: fix test for generic_handle_domain_irq Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 index d02f0f7f60014..01d095dd14cb8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ], [ generic_handle_domain_irq(NULL, 0); ], [ From a385778242609a7472a6e19dfc95488d3f55017b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 28 Mar 2022 09:52:24 +0800 Subject: [PATCH 0831/2070] drm/amdkcl: Add drm_dbg_* related definition Add the drm_dbg_state, drm_dbg_vbl and related macro definition for older versions of kernel. Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ia5766e1b9d51b2ceedd1f42b1866a6c836c729d6 --- include/kcl/kcl_drm_print.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a7ef405b97cdc..f4a7ee6d44a16 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -125,6 +125,14 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ +#if !defined(DRM_UT_STATE) +#define DRM_UT_STATE 0x40 +#endif + +#if !defined(DRM_UT_VBL) +#define DRM_UT_VBL 0x20 +#endif + #if !defined(DRM_DEV_DEBUG) #define DRM_DEV_DEBUG(dev, fmt, ...) \ DRM_DEBUG(fmt, ##__VA_ARGS__) @@ -136,7 +144,6 @@ void kcl_drm_err(const char *format, ...); #endif #ifndef DRM_DEBUG_VBL -#define DRM_UT_VBL 0x20 #define DRM_DEBUG_VBL(fmt, args...) \ do { \ if (unlikely(drm_debug & DRM_UT_VBL)) \ @@ -153,6 +160,16 @@ void drm_dev_dbg(const struct device *dev, int category, const char *format, ... drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_state) +#define drm_dbg_state(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_STATE, fmt, ##__VA_ARGS__) +#endif + +#if !defined(drm_dbg_vbl) +#define drm_dbg_vbl(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_VBL, fmt, ##__VA_ARGS__) +#endif + #if !defined(drm_dbg_kms) #define drm_dbg_kms(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) From 3b2647ecd5bea0d5473c7aba558f05abda13b3b1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 6 Apr 2022 13:18:51 +0800 Subject: [PATCH 0832/2070] drm/amdkcl: fix kcl of smca_get_bank_type() Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_mce.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index fee8c17c7d8fc..80625b60944b7 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,9 +11,12 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif - -#if !defined(HAVE_SMCA_GET_BANK_TYPE) && defined(HAVE_SMCA_BANK_STRUCT) +#if !defined(HAVE_SMCA_GET_BANK_TYPE) +#ifdef HAVE_SMCA_BANK_STRUCT enum smca_bank_types smca_get_bank_type(unsigned int bank); +#else +int smca_get_bank_type(unsigned int bank); +#endif #endif #ifndef HAVE_MCE_PRIO_UC From 40a52c11dfecd7e976459d9a3debc5e668a4ba91 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 12 Apr 2022 10:34:35 +0800 Subject: [PATCH 0833/2070] drm/amdkcl: Add support for ullong type module parameter Add support for ullong type module parameter in older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ief04a76fb56a00632df15041df612d0e3256e5c4 --- drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c | 4 ++++ include/kcl/kcl_moduleparam.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c index d350a6bd07769..10fe1c5d9d9c4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -27,3 +27,7 @@ #ifdef _kcl_param_check_hexint STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); #endif + +#ifdef _kcl_param_check_ullong +STANDARD_PARAM_DEF(ullong, unsigned long long, "%llu", kstrtoull); +#endif \ No newline at end of file diff --git a/include/kcl/kcl_moduleparam.h b/include/kcl/kcl_moduleparam.h index 427abe45ea8af..e579efe182bbd 100644 --- a/include/kcl/kcl_moduleparam.h +++ b/include/kcl/kcl_moduleparam.h @@ -14,4 +14,12 @@ extern int param_get_hexint(char *buffer, const struct kernel_param *kp); #define param_check_hexint(name, p) param_check_uint(name, p) #endif /* param_check_hexint */ +#ifndef param_check_ullong +#define _kcl_param_check_ullong +extern const struct kernel_param_ops param_ops_ullong; +extern int param_set_ullong(const char *val, const struct kernel_param *kp); +extern int param_get_ullong(char *buffer, const struct kernel_param *kp); +#define param_check_ullong(name, p) __param_check(name, p, unsigned long long) +#endif /* param_check_ullong */ + #endif From bb4584c9e024787340d0191669fdaa752254530c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 12 Apr 2022 20:01:00 +0800 Subject: [PATCH 0834/2070] drm/amdkcl: Add PSR2 related macro Add PSR2 related macro definition for older versions of kernle. Signed-off-by: Ma Jun Change-Id: Id2d7ed0934faaaa2e91678426ea396cb99cbc54e --- include/kcl/kcl_drm_dp_helper.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 60b18feee18f4..74163ac1e0e2a 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -287,6 +287,20 @@ enum drm_dp_phy { #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ #endif +/* + * drm: Add PSR version 3 macro + */ +#ifndef DP_PSR2_WITH_Y_COORD_IS_SUPPORTED +# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ +#endif + +/* + * drm: add PSR2 support and capability definition as per eDP 1.5 + */ +#ifndef DP_PSR2_WITH_Y_COORD_ET_SUPPORTED +# define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */ +#endif + /* * v4.10-rc3-483-gd0ce90629120 * drm : adds Y-coordinate and Colorimetry Format From 3063977a7ef0d8d4db623284b4b77d020ae50b4b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 19 Apr 2022 17:40:47 +0800 Subject: [PATCH 0835/2070] drm/amdkcl: add task_struct forward declaration Signed-off-by: Leslie Shi --- .../dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 index 50e28229344bf..87f2f1c951581 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -9,6 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers dnl # AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ], [ remove_conflicting_pci_framebuffers(NULL, NULL); From b559bcae12e326c02482b969ef4896426b1c0df2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 7 May 2022 15:53:28 +0800 Subject: [PATCH 0836/2070] drm/amdkcl:Add the INTEL_FAM6_ALDERLAKE definition Add the INTEL_FAM6_ALDERLAKE definition for older verisons of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I3e88fe0aa0f6b7be48bcd23be5b5dc63edf7274e --- include/kcl/kcl_intel_family.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index a4d7693bf0b0b..90793a772861b 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -10,5 +10,9 @@ #define INTEL_FAM6_ROCKETLAKE 0xA7 #endif +#ifndef INTEL_FAM6_ALDERLAKE +#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ +#endif + #endif /* CONFIG_X86 */ #endif From 39c12f1e982d6b00a751c475ce62ea62c38d1b58 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 7 May 2022 16:17:00 +0800 Subject: [PATCH 0837/2070] drm/amdkcl:Add DRM_DEV_INFO macro definition Add DRM_DEV_INFO macro definition for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I0337286e68f45420232e652f3c42cf0cb340260e --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index f4a7ee6d44a16..bba9e048cf699 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -143,6 +143,12 @@ void kcl_drm_err(const char *format, ...); DRM_ERROR(fmt, ##__VA_ARGS__) #endif +#ifndef DRM_DEV_INFO +/* NOTE: this is deprecated in favor of drm_info() or dev_info(). */ +#define DRM_DEV_INFO(dev, fmt, ...) \ + DRM_INFO(fmt, ##__VA_ARGS__) +#endif + #ifndef DRM_DEBUG_VBL #define DRM_DEBUG_VBL(fmt, args...) \ do { \ From 2282853b9b50b39c22c15cd65860592ec8ead5ec Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 16 May 2022 12:04:45 +0800 Subject: [PATCH 0838/2070] drm/amdkcl: fix access_ok prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix warning drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.c: In function ‘kfd_smi_ev_write’: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.c:128:21: warning: passing argument 1 of ‘kcl_access_ok’ makes integer from pointer without a cast [-Wint-conversion] Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_uaccess_backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h index 5e358c64a8fce..e781a42201f49 100644 --- a/include/kcl/backport/kcl_uaccess_backport.h +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -3,7 +3,7 @@ #define AMDKCL_UACCESS_BACKPORT_H #include -static inline int kcl_access_ok(unsigned long addr, unsigned long size) +static inline int kcl_access_ok(const void __user *addr, unsigned long size) { #if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) return access_ok(VERIFY_WRITE, (addr), (size)); From 64a163359561e31c1f897da943ec09884010f131 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 11 May 2022 10:39:14 +0800 Subject: [PATCH 0839/2070] drm/amdkcl: Add the DP_PHY_REPEATER_128B132B_RATES definition Add the macro definiton of DP_PHY_REPEATER_128B132B_RATES for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: If48731e99796af81c36599f26d6497ab11f7aa18 --- include/kcl/kcl_drm_dp_helper.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 74163ac1e0e2a..e379e156b74d9 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -158,6 +158,11 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +#ifndef DP_PHY_REPEATER_128B132B_RATES +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ +#endif + /* v5.9-rc4-979-g9782f52ab5d6 * drm/dp: Add LTTPR helpers */ From 714ac45fecd0eb3e2282242d167aa42a9362e9fd Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 13 Apr 2022 13:14:29 -0500 Subject: [PATCH 0840/2070] drm/amdgpu: Access MMIO/DOORBELL BO's of peer devices when IOMMU is ON Current design does not allow a GPU to access MMIO/DOORBELL memory of a peer device when IOMMU is turned ON. Changes made by this patch relax this constraint i.e. it allows GPU's to access MMIO/DOORBELL memory of peer devices without regard to IOMMU being ON or OFF. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 42 +++++++++++-------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 3302d812dda52..24a0693d8e095 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -997,10 +997,24 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, &bo[i], attachment[i]); if (ret) goto unwind; + + /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ + } else if ((mem->bo->tbo.type == ttm_bo_type_sg) && + ((mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + attachment[i]->type = KFD_MEM_ATT_SG; + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); + if (ret) + goto unwind; } else { +#ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; goto unwind; +#endif + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); } drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); @@ -2468,35 +2482,27 @@ void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) /** * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance - * of scatter gather table (sg_table) for BO's that represent MMIO or - * DOORBELL memory. An example of this is the MMIO BO that is used to - * surface HDP registers. + * of scatter gather table (sg_table) for a MMIO/DOORBELL BO. An example + * of this is the MMIO BO that's used to surface HDP registers. * - * @note: Per current design and implementation MMIO or DOORBELL BO's - * use only one scatterlist node in their sg_table. This is because - * the size of backing memory is relatively small (e.g. 4096 bytes - * for MMIO BO surfacing HDP registers). Implementation of this method - * relies on this design choice. + * @note: This method will only work as long as the address encapsulated + * by MMIO/DOORBELL BO is not a DMA mapped address * * The method does the following: * Acquire address to use in building scatterlist nodes * Acquire size of memory to use in building scatterlist nodes - * Invoke DMA Map service to obtain DMA'able address + * Invoke DMA Map service to obtain DMA mapped address * Access sg_table construction service with above parameters * Return the handle of scatter gather table * - * @adev: GPU device whose MMIO address needs to be exported - * @bo: Buffer object representing MMIO/DOORBELL memory e.g. HDP registers - * @dma_dev: Handle of peer PCIe device that wishes to access BO's memory + * @adev: GPU device whose MMIO/DOORBELL BO is being exported + * @bo: Handle of MMIO/DOORBELL BO e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access * @dir: Direction of data movement from peer PCIe devices perspective * * @sgt: Output parameter that is built and returned * * Return: zero if successful, non-zero otherwise - * - * @FIXME: This will only work as long as bo->tbo.sg->sgl->dma_address - * is not a DMA address but a physical BAR address. This will be reworked - * later when we add DMA mapping support for doorbell and MMIO BOs */ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, @@ -2524,8 +2530,8 @@ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, /* Update output parameter with a new sg_table */ pr_debug("MMIO/Doorbell BO size: %d\n", size); pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); - *sgt = create_doorbell_sg(dma_addr, size); - return 0; + *sgt = create_sg_table(dma_addr, size); + return (*sgt) ? 0 : -ENOMEM; } int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, From 04c824f22a218e9742478b418f8ad01428891e9c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 2 Jun 2022 09:16:22 +0800 Subject: [PATCH 0841/2070] drm/amdkcl: Add macro definition for some new plane formats Add macro definition for some new plane formats Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Change-Id: I290eefb6c39114a4790fde869429539957578e32 --- include/kcl/kcl_drm_fourcc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 25cf40f897b23..959f64bb803a6 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -96,6 +96,14 @@ * 55:36 - Reserved for future use, must be zero */ +#ifndef AMD_FMT_MOD_TILE_VER_GFX11 +#define AMD_FMT_MOD_TILE_VER_GFX11 4 +#endif + +#ifndef AMD_FMT_MOD_TILE_GFX11_256K_R_X +#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 +#endif + #if !defined(AMD_FMT_MOD) #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) From 2d21b55c135a4d1f0c9f0be1a05d3c954e01a97a Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 10 Jun 2022 20:43:25 +0800 Subject: [PATCH 0842/2070] drm/amdkcl: Check if display_info->edid_hdmi_rgb444_dc_modes is defined Check if display_info->edid_hdmi_rgb444_dc_modes is defined introduced in v4.9-rc1-522171951761153172c75b94ae1f4bc9ab631745 Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun Change-Id: Ic2659a288fae2af696cf2c3d20c3e97491341c5f --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index afa58eb51172d..7b9da8c3a89f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -192,7 +192,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { +#ifndef HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES + if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && +#else if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && +#endif (mode_clock * 5/4 <= max_tmds_clock)) bpc = 10; else diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77c1a9cf2ab98..7137c5880a34a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -291,6 +291,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* display_info->edid_hdmi_rgb444_dc_modes is available */ +#define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 + /* display_info->hdmi.scdc.scrambling are available */ #define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 61eef3b454776..2cdb134bfa734 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -1,3 +1,22 @@ +dnl # +dnl # commit v5.16-rc5-908-g4adc33f36d80 +dnl # drm/edid: Split deep color modes between RGB and YUV444 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->edid_hdmi_rgb444_dc_modes = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES, 1, + [display_info->edid_hdmi_rgb444_dc_modes is available]) + ]) + ]) +]) + + dnl # dnl # commit v5.6-rc2-1062-ga1d11d1efe4d dnl # drm/edid: Add function to parse EDID descriptors for monitor range @@ -18,5 +37,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ ]) AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE ]) From 8523a4858ecba639a46faaa9ea6a46c1a3304882 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sun, 12 Jun 2022 16:58:46 +0800 Subject: [PATCH 0843/2070] drm/amdkcl: Check if cancel_work is defined Check and add cancel_work() function Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I002962a0476e253cbad2f4f414965c95b96b2d78 --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c | 41 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 17 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_workqueue_backport.h | 13 ++++++ 8 files changed, 82 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 create mode 100644 include/kcl/backport/kcl_workqueue_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index c4374f3eb8e8c..2b5951157cf48 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,6 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o + kcl_workqueue.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c new file mode 100644 index 0000000000000..461066e047ac3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -0,0 +1,41 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_CANCEL_WORK +bool (*_kcl_cancel_work)(struct work_struct *work); +EXPORT_SYMBOL(_kcl_cancel_work); + +bool _kcl_cancel_work_stub(struct work_struct *work) +{ + pr_warn_once("cancel_work function is not supported\n"); + return false; +} +#endif + +void amdkcl_workqueue_init(void) +{ +#ifndef HAVE_CANCEL_WORK + _kcl_cancel_work = amdkcl_fp_setup("cancel_work", _kcl_cancel_work_stub); +#endif /* HAVE_CANCEL_WORK */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 7e6b682cbc483..8304f79c8f18c 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -11,6 +11,7 @@ extern void amdkcl_mm_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_numa_init(void); +extern void amdkcl_workqueue_init(void); int __init amdkcl_init(void) { @@ -23,6 +24,7 @@ int __init amdkcl_init(void) amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_numa_init(); + amdkcl_workqueue_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 43a3040bfaf35..b83b0b1047220 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -83,4 +83,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7137c5880a34a..790f76a9f424f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -49,6 +49,12 @@ /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 +/* bitmap_free() is available */ +#define HAVE_BITMAP_FUNCS 1 + +/* cancel_work() is available */ +#define HAVE_CANCEL_WORK 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 new file mode 100644 index 0000000000000..f4df5913ba4e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.18-rc5-2003-g73b4b53276a1 +dnl # Revert "workqueue: remove unused cancel_work()" +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cancel_work(NULL); + ], [ + AC_DEFINE(HAVE_CANCEL_WORK, 1, + [cancel_work() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 217ef3d6eb5fb..228c0ef0c9eb8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -155,6 +155,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC + AC_AMDGPU_CANCEL_WORK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h new file mode 100644 index 0000000000000..3e6adabc0f08c --- /dev/null +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_WORKQUEUE_BACKPORT_H +#define KCL_LINUX_WORKQUEUE_BACKPORT_H + +#include + +#ifndef HAVE_CANCEL_WORK +extern bool (*_kcl_cancel_work)(struct work_struct *work); +#define cancel_work _kcl_cancel_work +#endif + +#endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From 2342f939d66371e5b091de390a7d09dfc6b1d380 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 8 Jun 2022 10:13:16 -0500 Subject: [PATCH 0844/2070] drm/amdgpu: Reduce P2P code divergence in DRM vs DKMS branches Cleans up the DKMS-version of P2P to reduce differences from the upstream implementation (DRM-version) without breaking the P2P functionality supported on the DKMS branch. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Change-Id: I6de18c791a6def548024d03526de695b6032adff --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16 +++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 3 files changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 49c2b74c6ccc1..7450dded51c17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -226,6 +226,7 @@ extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; extern int amdgpu_use_xgmi_p2p; +extern bool pcie_p2p; extern int amdgpu_mtype_local; extern int amdgpu_enforce_isolation; #ifdef CONFIG_HSA_AMD diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 24a0693d8e095..b78f6684f609e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -864,7 +864,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, * * Implementation determines if access to VRAM BO would employ DMABUF * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config - * option DMABUF_MOVE_NOTIFY enabled. Employ Shared BO mechanism if above + * option HSA_AMD_P2P enabled. Employ Shared BO mechanism if above * config option is not set. It is important to note that a Shared BO * cannot be used to enable peer acces if system has IOMMU enabled * @@ -877,7 +877,7 @@ static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, { int ret = 0; -#if defined(CONFIG_DMABUF_MOVE_NOTIFY) && defined(CONFIG_PCI_P2PDMA) +#ifdef CONFIG_HSA_AMD_P2P attachment->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, bo); pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); @@ -991,21 +991,11 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); #endif /* Enable peer acces to VRAM BO's */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && - mem->bo->tbo.type == ttm_bo_type_device) { + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { ret = kfd_mem_attach_vram_bo(adev, mem, &bo[i], attachment[i]); if (ret) goto unwind; - - /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ - } else if ((mem->bo->tbo.type == ttm_bo_type_sg) && - ((mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || - (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { - attachment[i]->type = KFD_MEM_ATT_SG; - ret = create_dmamap_sg_bo(adev, mem, &bo[i]); - if (ret) - goto unwind; } else { #ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a8a2e4afb8b60..1405d4e373f1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include From ea590147cc8d01ecef21918a14ca4786d14b4fbf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Jun 2022 16:02:27 +0800 Subject: [PATCH 0845/2070] drm/amdkcl: Fix 64 bit wraparound resulting in illegal drm mode [Why] For m = drm_display_mode{.clock = 533250, .htotal = 4000, .vtotal = 2222}, common_rates[i] = 60000, the result of target_vtotal is 2221. This cause wraparound of variable target_vtotal_diff. [How] Skip the loop if target_vtotal less than m->vtotal Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a2b4c6e91ec8f..835b6785126e0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8851,6 +8851,10 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) num = (unsigned long long)m->clock * 1000 * 1000; den = common_rates[i] * (unsigned long long)m->htotal; target_vtotal = div_u64(num, den); + + if (target_vtotal < m->vtotal) + continue; + target_vtotal_diff = target_vtotal - m->vtotal; /* Check for illegal modes */ From 850fb42c0f4b47fd768e26e4f9667a7083a33c77 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 24 Jun 2022 09:02:20 +0800 Subject: [PATCH 0846/2070] drm/amdkcl: Change the temp build dir name Changing the build-XXXXXXXX to build.XXXXXXXX to fix the CFLAGS parse error in case of using build-Ixxx as temp dir name. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I92ef6e3aaafae103b48d12786f3eac15b6bab708 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 228c0ef0c9eb8..8f7c1817e8b06 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -377,7 +377,7 @@ dnl # AC_KERNEL_TMP_BUILD_DIR dnl # $1: contents to be executed in a temporary directory dnl # AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ - build_dir=$(mktemp -d -t build-XXXXXXXX -p $build_dir_root) + build_dir=$(mktemp -d -t build_XXXXXXXX -p $build_dir_root) cd $build_dir $1 AS_IF([test -s confdefs.h], [ From af99feca810e4b869874f1eb711afdec936c4a2a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 13:43:48 +0800 Subject: [PATCH 0847/2070] drm/amdkcl: add kcl/kcl_iosys-map.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 5 +- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 + drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- include/kcl/header/linux/iosys-map.h | 9 + include/kcl/kcl_dma-buf-map.h | 2 + include/kcl/kcl_iosys-map.h | 179 +++++++++++++++++++ 8 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/iosys-map.h create mode 100644 include/kcl/kcl_iosys-map.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b83b0b1047220..6bf1170bde505 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 790f76a9f424f..74b7576a20b95 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -784,7 +784,7 @@ /* #undef HAVE_LINUX_DMA_ATTRS_H */ /* Define to 1 if you have the header file. */ -#define HAVE_LINUX_DMA_BUF_MAP_H 1 +/* #undef HAVE_LINUX_DMA_BUF_MAP_H */ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 @@ -798,6 +798,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_FENCE_ARRAY_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IOSYS_MAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 7fe93986495ad..7240333bce56b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -67,6 +67,12 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + dnl # + dnl # 7938f4218168 + dnl # dma-buf: dma-buf-map: Rename to iosys-map + dnl # + AC_KERNEL_CHECK_HEADERS([linux/iosys-map.h]) + dnl # dnl # v5.14-rc5-11-gc0891ac15f04 dnl # isystem: ship and use stdarg.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index b4ed7c672dcd8..be45e938ed821 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 0ffe77d741b34..be989c5751c47 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -123,7 +123,7 @@ void ttm_move_memcpy(bool clear, if (!src_map.is_iomem && !dst_map.is_iomem) { memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE); } else if (!src_map.is_iomem) { - dma_buf_map_memcpy_to(&dst_map, src_map.vaddr, + iosys_map_memcpy_to(&dst_map, 0, src_map.vaddr, PAGE_SIZE); } else if (!dst_map.is_iomem) { memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem, diff --git a/include/kcl/header/linux/iosys-map.h b/include/kcl/header/linux/iosys-map.h new file mode 100644 index 0000000000000..a96b1547378c6 --- /dev/null +++ b/include/kcl/header/linux/iosys-map.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___IOSYS_MAP_H___H_ +#define _KCL_HEADER___IOSYS_MAP_H___H_ + +#ifdef HAVE_LINUX_IOSYS_MAP_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h index 4ce925f647ec5..c3112da74c090 100644 --- a/include/kcl/kcl_dma-buf-map.h +++ b/include/kcl/kcl_dma-buf-map.h @@ -7,7 +7,9 @@ #ifndef _KCL_KCL__DMA_BUF_MAP_H__H__ #define _KCL_KCL__DMA_BUF_MAP_H__H__ +#ifndef HAVE_LINUX_IOSYS_MAP_H #include +#endif #ifndef HAVE_LINUX_DMA_BUF_MAP_H #include diff --git a/include/kcl/kcl_iosys-map.h b/include/kcl/kcl_iosys-map.h new file mode 100644 index 0000000000000..d35ce3a8f5c58 --- /dev/null +++ b/include/kcl/kcl_iosys-map.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer abstraction for IO/system memory + * Copied from include/kcl/iosys-map.h + */ + +#ifndef _KCL_KCL__IOSYS_MAP_H__H__ +#define _KCL_KCL__IOSYS_MAP_H__H__ + +#include + +#ifndef HAVE_LINUX_IOSYS_MAP_H +#include +#include + +/** + * struct iosys_map - Pointer to IO/system memory + * @vaddr_iomem: The buffer's address if in I/O memory + * @vaddr: The buffer's address if in system memory + * @is_iomem: True if the buffer is located in I/O memory, or false + * otherwise. + */ +struct iosys_map { + union { + void __iomem *vaddr_iomem; + void *vaddr; + }; + bool is_iomem; +}; + +/** + * IOSYS_MAP_INIT_VADDR - Initializes struct iosys_map to an address in system memory + * @vaddr_: A system-memory address + */ +#define IOSYS_MAP_INIT_VADDR(vaddr_) \ + { \ + .vaddr = (vaddr_), \ + .is_iomem = false, \ + } + + +/** + * iosys_map_set_vaddr - Sets a iosys mapping structure to an address in system memory + * @map: The iosys_map structure + * @vaddr: A system-memory address + * + * Sets the address and clears the I/O-memory flag. + */ +static inline void iosys_map_set_vaddr(struct iosys_map *map, void *vaddr) +{ + map->vaddr = vaddr; + map->is_iomem = false; +} + +/** + * iosys_map_set_vaddr_iomem - Sets a iosys mapping structure to an address in I/O memory + * @map: The iosys_map structure + * @vaddr_iomem: An I/O-memory address + * + * Sets the address and the I/O-memory flag. + */ +static inline void iosys_map_set_vaddr_iomem(struct iosys_map *map, + void __iomem *vaddr_iomem) +{ + map->vaddr_iomem = vaddr_iomem; + map->is_iomem = true; +} + +/** + * iosys_map_is_equal - Compares two iosys mapping structures for equality + * @lhs: The iosys_map structure + * @rhs: A iosys_map structure to compare with + * + * Two iosys mapping structures are equal if they both refer to the same type of memory + * and to the same address within that memory. + * + * Returns: + * True is both structures are equal, or false otherwise. + */ +static inline bool iosys_map_is_equal(const struct iosys_map *lhs, + const struct iosys_map *rhs) +{ + if (lhs->is_iomem != rhs->is_iomem) + return false; + else if (lhs->is_iomem) + return lhs->vaddr_iomem == rhs->vaddr_iomem; + else + return lhs->vaddr == rhs->vaddr; +} + +/** + * iosys_map_is_null - Tests for a iosys mapping to be NULL + * @map: The iosys_map structure + * + * Depending on the state of struct iosys_map.is_iomem, tests if the + * mapping is NULL. + * + * Returns: + * True if the mapping is NULL, or false otherwise. + */ +static inline bool iosys_map_is_null(const struct iosys_map *map) +{ + if (map->is_iomem) + return !map->vaddr_iomem; + return !map->vaddr; +} + +/** + * iosys_map_is_set - Tests if the iosys mapping has been set + * @map: The iosys_map structure + * + * Depending on the state of struct iosys_map.is_iomem, tests if the + * mapping has been set. + * + * Returns: + * True if the mapping is been set, or false otherwise. + */ +static inline bool iosys_map_is_set(const struct iosys_map *map) +{ + return !iosys_map_is_null(map); +} + +/** + * iosys_map_clear - Clears a iosys mapping structure + * @map: The iosys_map structure + * + * Clears all fields to zero, including struct iosys_map.is_iomem, so + * mapping structures that were set to point to I/O memory are reset for + * system memory. Pointers are cleared to NULL. This is the default. + */ +static inline void iosys_map_clear(struct iosys_map *map) +{ + if (map->is_iomem) { + map->vaddr_iomem = NULL; + map->is_iomem = false; + } else { + map->vaddr = NULL; + } +} + +/** + * iosys_map_memcpy_to - Memcpy into offset of iosys_map + * @dst: The iosys_map structure + * @dst_offset: The offset from which to copy + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a iosys_map with an offset. The source buffer is in + * system memory. Depending on the buffer's location, the helper picks the + * correct method of accessing the memory. + */ +static inline void iosys_map_memcpy_to(struct iosys_map *dst, size_t dst_offset, + const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem + dst_offset, src, len); + else + memcpy(dst->vaddr + dst_offset, src, len); +} + +/** + * iosys_map_incr - Increments the address stored in a iosys mapping + * @map: The iosys_map structure + * @incr: The number of bytes to increment + * + * Increments the address stored in a iosys mapping. Depending on the + * buffer's location, the correct value will be updated. + */ +static inline void iosys_map_incr(struct iosys_map *map, size_t incr) +{ + if (map->is_iomem) + map->vaddr_iomem += incr; + else + map->vaddr += incr; +} + +#endif /* HAVE_LINUX_IOSYS_MAP_H */ + +#endif From 77cdc3d1a52c00d78aab97b7c28563f2e9b3b2ee Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 14:01:45 +0800 Subject: [PATCH 0848/2070] drm/amdkcl: test for drm/dp/drm_dp_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 | 4 ++++ .../amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 4 ++++ .../dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/backport/kcl_drm_dp_helper_backport.h | 1 - include/kcl/header/drm/dp/drm_dp_helper.h | 9 +++++++++ include/kcl/kcl_drm_dp_cec.h | 4 ++++ include/kcl/kcl_drm_dp_helper.h | 4 ++++ 11 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/dp/drm_dp_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 74b7576a20b95..d4475a6d244c4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -327,6 +327,9 @@ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DP_DRM_DP_HELPER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index d851ad71eab97..49994828e0873 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 3ded1ff2015a2..552e94c063fb0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_cec_register_connector(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 664b63498814e..e6713844783e2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 4d8e0f733eb7e..af98096981e77 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index c15c7d3d88eb9..f49bd33a93a19 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b3b69a3e8dea7..da4ac4556d9b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -50,6 +50,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 8a932361c9e0e..4c541b78127d7 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -3,7 +3,6 @@ #define _KCL_DRM_DP_HELPER_BACKPORT_H_ #include -#include /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/header/drm/dp/drm_dp_helper.h b/include/kcl/header/drm/dp/drm_dp_helper.h new file mode 100644 index 0000000000000..9aac78ed61294 --- /dev/null +++ b/include/kcl/header/drm/dp/drm_dp_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ + +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 7dc38a930f543..62ee302a586be 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,7 +8,11 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include +#else #include +#endif /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index e379e156b74d9..6168671062032 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,7 +30,11 @@ #include #include +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include +#else #include +#endif #include /* From 34761a9cb3ca81b15615b4f17616c7c03f36738d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 14:06:15 +0800 Subject: [PATCH 0849/2070] drm/amdkcl: test for drm/dp/drm_dp_mst_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 8 ++++++++ drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 6 +++++- .../amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 12 ++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 8 ++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ .../m4/drm-up-update-payload-part1-start-slot-arg.m4 | 4 ++++ .../drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 ++++ .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 4 ++++ include/kcl/header/drm/dp/drm_dp_mst_helper.h | 9 +++++++++ 17 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/dp/drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d4475a6d244c4..c4df22ff9c601 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -330,6 +330,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DP_DRM_DP_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 index 448c9066f274a..65b49ae69f164 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); @@ -18,7 +22,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots dnl # AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index d168a591bcd23..8dc9ef9c8dd48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else + #include + #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1d4564270d065..1f637c137dad1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index dc4167e33a865..df6b3450485e0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 17422c2217f46..65d24257c4d25 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 4198140ed6a0e..913f4586acf6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 06d77b61ab828..4c48b47b4c9bf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_dsc_aux_for_port(NULL); ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index f08316600fcbd..5540428fc8b49 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,7 +4,11 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->hotplug(NULL); @@ -24,7 +28,11 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->register_connector(NULL); @@ -40,7 +48,11 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->destroy_connector(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 3c491e182062e..039132d5081d7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_topology_mgr_resume(NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 9684ef25199df..3ab8397ab8481 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; mst_state->total_avail_slots = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 2eee635844c96..309cbc4f0f964 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -15,7 +15,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_get_port_malloc(NULL); drm_dp_mst_put_port_malloc(NULL); @@ -30,7 +34,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index da4ac4556d9b7..db107edff41aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -56,6 +56,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 1b341003bb985..0c25016be1da4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_update_payload_part1(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 98d2982594b7c..ca29f48cb467a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); ], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 183e49a5ba766..2412859be272a 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,7 +22,11 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ +#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#include +#else #include +#endif /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ #if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) diff --git a/include/kcl/header/drm/dp/drm_dp_mst_helper.h b/include/kcl/header/drm/dp/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..116be51b87c2c --- /dev/null +++ b/include/kcl/header/drm/dp/drm_dp_mst_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ + +#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#include_next +#endif + +#endif From 8a4c7ab4066125d15c27b00e8c9b9e6ce406ce40 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 16:28:32 +0800 Subject: [PATCH 0850/2070] drm/amdkcl: Test whether dma_fence_is_container() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/dma-fence-is-container.m4 | 15 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma-resv.h | 1 + include/kcl/kcl_dma_fence.h | 46 +++++++++++++++++++ include/kcl/kcl_dma_fence_chain.h | 3 ++ include/kcl/kcl_fence_array.h | 11 +++++ 7 files changed, 80 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 create mode 100644 include/kcl/kcl_dma_fence.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c4df22ff9c601..a3a029521555f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -100,6 +100,9 @@ /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 +/* dma_fence_is_container() is available */ +#define HAVE_DMA_FENCE_IS_CONTAINER 1 + /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 new file mode 100644 index 0000000000000..7c07948aa5205 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.17-rc2-229-g976b6d97c623 +dnl # dma-buf: consolidate dma_fence subclass checking +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_CONTAINER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_container(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_CONTAINER, 1, [dma_fence_is_container() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8f7c1817e8b06..64eb48fe318a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -156,6 +156,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 0d0ccbbb5d043..0c4850cd6bf95 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -50,6 +50,7 @@ #include #include #include +#include struct dma_resv_list; diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h new file mode 100644 index 0000000000000..cbf594a40d4de --- /dev/null +++ b/include/kcl/kcl_dma_fence.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ + +#ifndef AMDKCL_DMA_FENCE_H +#define AMDKCL_DMA_FENCE_H + +#ifndef HAVE_DMA_FENCE_IS_CONTAINER +#include +#include + +/** + * dma_fence_is_chain - check if a fence is from the chain subclass + * @fence: the fence to test + * + * Return true if it is a dma_fence_chain and false otherwise. + */ +static inline bool dma_fence_is_chain(struct dma_fence *fence) +{ + return fence->ops == &dma_fence_chain_ops; +} + +/** + * dma_fence_is_container - check if a fence is a container for other fences + * @fence: the fence to test + * + * Return true if this fence is a container for other fences, false otherwise. + * This is important since we can't build up large fence structure or otherwise + * we run into recursion during operation on those fences. + */ +static inline bool dma_fence_is_container(struct dma_fence *fence) +{ + return dma_fence_is_array(fence) || dma_fence_is_chain(fence); +} + +#endif /* HAVE_DMA_FENCE_IS_CONTAINER */ + +#endif diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index 4cde69227a3f1..eafcd818c1da3 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -9,6 +9,9 @@ #ifndef AMDKCL_DMA_FENCE_CHAIN_H #define AMDKCL_DMA_FENCE_CHAIN_H +#ifdef HAVE_LINUX_DMA_FENCE_CHAIN_H +#include +#endif #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #ifdef HAVE_LINUX_DMA_FENCE_H diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h index 1e8f37c5864d3..060edd1567fda 100644 --- a/include/kcl/kcl_fence_array.h +++ b/include/kcl/kcl_fence_array.h @@ -76,6 +76,17 @@ static inline struct fence_array *to_fence_array(struct fence *fence) struct fence_array *fence_array_create(int num_fences, struct fence **fences, u64 context, unsigned seqno, bool signal_on_any); +/** + * dma_fence_is_array - check if a fence is from the array subclass + * @fence: the fence to test + * + * Return true if it is a dma_fence_array and false otherwise. + */ +static inline bool dma_fence_is_array(struct dma_fence *fence) +{ + return false; +} + #endif #endif From c6dc08d689e9dffcb20596bf26c99fc86ce847c4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 16:57:30 +0800 Subject: [PATCH 0851/2070] drm/amdkcl: Test whether str_yes_no() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 | 16 ++++++++++++ include/kcl/kcl_string_helpers.h | 30 +++++++++++++++++++++++ 5 files changed, 52 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 create mode 100644 include/kcl/kcl_string_helpers.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6bf1170bde505..a782accbb0435 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -85,4 +85,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a3a029521555f..a9817b5da7569 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1066,6 +1066,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* str_yes_no() is defined */ +#define HAVE_STR_YES_NO 1 + /* synchronize_shrinkers() is available */ #define HAVE_SYNCHRONIZE_SHRINKERS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 64eb48fe318a8..47c3792366fda 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -157,6 +157,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER + AC_AMDGPU_STR_YES_NO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 new file mode 100644 index 0000000000000..9ca6f08ae00e7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ea4692c75e1c63926e4fb0728f5775ef0d733888 +dnl # lib/string_helpers: Consolidate string helpers implementation +dnl # +AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str = str_yes_no(true); + ], [ + AC_DEFINE(HAVE_STR_YES_NO, 1, + [str_yes_no() is defined]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h new file mode 100644 index 0000000000000..ceac153f44bfd --- /dev/null +++ b/include/kcl/kcl_string_helpers.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_STRING_HELPERS_H +#define AMDKCL_STRING_HELPERS_H + + +/* Copied from v5.17-rc2-224-gea4692c75e1c linux/string_helpers.h */ + +#ifndef HAVE_STR_YES_NO +static inline const char *str_yes_no(bool v) +{ + return v ? "yes" : "no"; +} + +static inline const char *str_on_off(bool v) +{ + return v ? "on" : "off"; +} + +static inline const char *str_enable_disable(bool v) +{ + return v ? "enable" : "disable"; +} + +static inline const char *str_enabled_disabled(bool v) +{ + return v ? "enabled" : "disabled"; +} + +#endif /* HAVE_STR_YES_NO */ +#endif From b865ef23b2cf85fbda81183c959aad3662cddaa8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 11:27:12 +0800 Subject: [PATCH 0852/2070] drm/amdkcl: Test whether struct drm_mode_config has member fb_modifiers_not_supported Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: I37f2cbc1e506f97d09a4850d0b92dabcf4121a88 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 9 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index c481ed6f0fe9e..325ccf79e6762 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1063,7 +1063,11 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) int ret; unsigned int i, block_width, block_height, block_size_log2; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (rfb->base.dev->mode_config.fb_modifiers_not_supported) +#else + if (!rfb->base.dev->mode_config.allow_fb_modifiers) +#endif return 0; for (i = 0; i < format_info->num_planes; ++i) { @@ -1291,7 +1295,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { +#else + if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) { +#endif drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); ret = check_tiling_flags_gfx6(rfb); @@ -1299,7 +1307,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (!dev->mode_config.fb_modifiers_not_supported && +#else + if (dev->mode_config.allow_fb_modifiers && +#endif !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ret = convert_tiling_flags_to_modifier_gfx12(rfb); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 8fac16311a54a..6ad793264dd0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2815,7 +2815,9 @@ static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 9c8fbf8e3f82e..5a1fe581e02d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2764,7 +2764,9 @@ static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.max_height = 16384; adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 476838197a375..34e5b3e0ffff6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2733,7 +2733,9 @@ static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block) else adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 835b6785126e0..d543e879e49a6 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8414,7 +8414,6 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) return 0; } #endif - static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 1bcbc658b7c3d..c9ad578ea9b01 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1901,8 +1901,10 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, return res; #endif +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; +#endif res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, &dm_plane_funcs, formats, num_formats, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a9817b5da7569..8404e8d161fd1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -566,6 +566,9 @@ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 +/* drm_mode_config->fb_modifiers_not_supported is available */ +#define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 + /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 new file mode 100644 index 0000000000000..add5633e0f26f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -0,0 +1,18 @@ +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_modifiers_not_supported = true; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED, 1, + [drm_mode_config->fb_modifiers_not_supported is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ + AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 47c3792366fda..1f11bb84d1e4e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -88,6 +88,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From 731a7259b04d4d8cca44a1cf426ba27bdebc166f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 22 Jun 2022 13:12:12 +0800 Subject: [PATCH 0853/2070] drm/amdkcl: Test whether dma_fence_chain_contained is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_chain.h | 17 +++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8404e8d161fd1..a0634b8db8361 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -996,6 +996,9 @@ /* struct dma_fence_chain is available */ #define HAVE_STRUCT_DMA_FENCE_CHAIN 1 +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 34231d5d2028d..7867a6283d95f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -32,3 +32,20 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ ]) ]) +dnl # +dnl # v5.17-rc2-233-g18f5fad275ef +dnl # dma-buf: add dma_fence_chain_contained helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_contained(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_CONTAINED, 1, + [dma_fence_chain_contained() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1f11bb84d1e4e..c93e18a73e7d8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -159,6 +159,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index eafcd818c1da3..b7b66a3b93c90 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -123,4 +123,21 @@ static inline void dma_fence_chain_free(struct dma_fence_chain *chain) #endif +#ifndef HAVE_DMA_FENCE_CHAIN_CONTAINED +/** + * dma_fence_chain_contained - return the contained fence + * @fence: the fence to test + * + * If the fence is a dma_fence_chain the function returns the fence contained + * inside the chain object, otherwise it returns the fence itself. + */ +static inline struct dma_fence * +dma_fence_chain_contained(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + + return chain ? chain->fence : fence; +} +#endif /* HAVE_DMA_FENCE_CHAIN_CONTAINED */ + #endif From 041403ed77aa53519fd2e99d8e58bef11e912407 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 23 Jun 2022 14:59:24 +0800 Subject: [PATCH 0854/2070] drm/amdkcl: add DRM_COLOR_FORMAT_YCRCB enums This is caused by c03d0b52ff71 "drm/connector: Fix typo in output format" v5.16-rc5-909-gc03d0b52ff71 Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_connector.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index f14a5f2790201..ee8d72d7a4d72 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -108,4 +108,16 @@ int drm_connector_set_panel_orientation_with_quirk( } #endif +#ifndef DRM_COLOR_FORMAT_YCBCR444 +#define DRM_COLOR_FORMAT_YCBCR444 (1<<1) +#endif + +#ifndef DRM_COLOR_FORMAT_YCBCR422 +#define DRM_COLOR_FORMAT_YCBCR422 (1<<2) +#endif + +#ifndef DRM_COLOR_FORMAT_YCBCR420 +#define DRM_COLOR_FORMAT_YCBCR420 (1<<3) +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 3ae2ed6f72171ca83f63fbba24f3d928e67ac651 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Mar 2024 12:24:06 +0800 Subject: [PATCH 0855/2070] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: I319776ac36ade90de99d03e520d6426efd7c31c4 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 9 ++++- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 +++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +++++++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++ .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +++ drivers/gpu/drm/amd/display/dc/dc.h | 4 +++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++ drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 5 ++- .../display/dc/dcn201/dcn201_link_encoder.c | 2 ++ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 ++ .../display/dc/dio/dcn20/dcn20_link_encoder.c | 8 ++++- .../display/dc/dio/dcn20/dcn20_link_encoder.h | 2 ++ .../dc/dio/dcn20/dcn20_stream_encoder.c | 7 +++- .../dc/dio/dcn30/dcn30_dio_link_encoder.c | 2 ++ .../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 4 +++ .../dc/dio/dcn31/dcn31_dio_link_encoder.c | 4 +++ .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 4 +++ .../dc/dio/dcn32/dcn32_dio_link_encoder.c | 2 ++ .../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 3 ++ .../dc/dio/dcn321/dcn321_dio_link_encoder.c | 2 ++ .../dc/dio/virtual/virtual_stream_encoder.c | 8 +++++ .../amd/display/dc/dml/display_mode_enums.h | 2 ++ .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 3 +- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 ++ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 ++ .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 ++ .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 3 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 ++ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 3 +- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 2 ++ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 +++ .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 +++++ .../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 2 ++ .../amd/display/dc/hwss/dcn20/dcn20_init.c | 4 +++ .../amd/display/dc/hwss/dcn21/dcn21_init.c | 2 ++ .../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 ++ .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 ++ .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 +++ .../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 ++ .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 3 +- .../gpu/drm/amd/display/dc/inc/core_types.h | 5 ++- .../drm/amd/display/dc/inc/hw/link_encoder.h | 4 +++ .../amd/display/dc/inc/hw/timing_generator.h | 2 ++ .../dc/link/protocols/link_dp_training_dpia.c | 2 ++ .../amd/display/dc/optc/dcn20/dcn20_optc.c | 9 +++++ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 2 ++ .../amd/display/dc/optc/dcn201/dcn201_optc.c | 2 ++ .../amd/display/dc/optc/dcn30/dcn30_optc.c | 4 +++ .../amd/display/dc/optc/dcn30/dcn30_optc.h | 2 ++ .../amd/display/dc/optc/dcn314/dcn314_optc.c | 2 ++ .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 ++ .../dc/resource/dcn20/dcn20_resource.c | 36 +++++++++++++++---- .../dc/resource/dcn20/dcn20_resource.h | 2 ++ .../dc/resource/dcn201/dcn201_resource.c | 2 ++ .../dc/resource/dcn21/dcn21_resource.c | 15 +++++++- .../dc/resource/dcn30/dcn30_resource.c | 22 ++++++++++++ .../dc/resource/dcn301/dcn301_resource.c | 2 ++ .../dc/resource/dcn314/dcn314_resource.c | 10 ++++++ .../dc/resource/dcn315/dcn315_resource.c | 14 ++++++++ .../dc/resource/dcn316/dcn316_resource.c | 15 ++++++++ .../dc/resource/dcn32/dcn32_resource.c | 10 ++++++ .../resource/dcn32/dcn32_resource_helpers.c | 2 ++ 65 files changed, 311 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d543e879e49a6..9c63f0d8eeadc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12530,10 +12530,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; - +#endif trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -12868,6 +12869,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { @@ -12888,6 +12890,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } +#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 00f2e645dc849..111b81acdc1c9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1367,6 +1367,7 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static int dp_dsc_fec_support_show(struct seq_file *m, void *data) { struct drm_connector *connector = m->private; @@ -1422,6 +1423,7 @@ static int dp_dsc_fec_support_show(struct seq_file *m, void *data) return ret; } +#endif /* function: Trigger virtual HPD redetection on connector * @@ -1567,6 +1569,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, * 1 - means that DSC is currently enabled * 0 - means that DSC is disabled */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -2537,7 +2540,7 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, kfree(rd_buf); return result; } - +#endif /* * function description: Read max_requested_bpc property from the connector @@ -3003,6 +3006,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, .read = dp_dsc_clock_en_read, @@ -3054,6 +3058,7 @@ static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { .read = dp_dsc_slice_bpg_offset_read, .llseek = default_llseek }; +#endif static const struct file_operations trigger_hotplug_debugfs_fops = { .owner = THIS_MODULE, @@ -3127,6 +3132,8 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, +#endif + {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, {"is_mst_connector", &dp_is_mst_connector_fops}, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 32cff405ca943..81d5ae267aefb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -654,6 +654,7 @@ bool dm_helpers_execute_fused_io( return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, bool is_write_cmd, unsigned char cmd, @@ -831,7 +832,9 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( return ret; } +#endif +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, @@ -914,6 +917,7 @@ bool dm_helpers_dp_write_dsc_enable( return ret; } +#endif bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ba8b99566094c..41a09c85bfbec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -268,6 +268,8 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -302,9 +304,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 u8 *dsc_branch_dec_caps = NULL; -#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); -#endif /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -359,6 +359,8 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } +#endif +#endif static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c17f065a88d4f..0b7c25953308f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -66,7 +66,9 @@ #include "dc_dmub_srv.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" +#endif #include "vm_helper.h" @@ -678,7 +680,9 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_end = crc_window->windowb_y_end; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; +#endif param.odm_mode = pipe->next_odm_pipe ? 1:0; /* Default to the union of both windows */ @@ -3016,8 +3020,10 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( if (stream_update->wb_update) su_flags->bits.wb_update = 1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) su_flags->bits.dsc_changed = 1; +#endif if (stream_update->mst_bw_update) su_flags->bits.mst_bw = 1; @@ -3245,7 +3251,9 @@ static void copy_stream_update_to_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *update) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_context *dc_ctx = dc->ctx; +#endif if (update == NULL || stream == NULL) return; @@ -3349,6 +3357,8 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->writeback_info[i] = update->wb_update->writeback_info[i]; } + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3374,6 +3384,7 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } +#endif if (update->scaler_sharpener_update) stream->scaler_sharpener_update = *update->scaler_sharpener_update; if (update->sharpening_required) @@ -3767,8 +3778,10 @@ static void commit_planes_do_stream_update(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) dc->link_srv->update_dsc_config(pipe_ctx); +#endif if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update->is_increase) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index c9fbb64d706a2..f07119365ed0a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -4090,7 +4090,11 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) if (dc->res_pool == NULL) return false; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT return dc->res_pool->res_cap->num_dsc > 0; +#else + return 0; +#endif } static bool planes_changed_for_existing_stream(struct dc_state *context, @@ -5011,8 +5015,10 @@ bool pipe_need_reprogram( false == pipe_ctx_old->stream->dpms_off) return true; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) return true; +#endif if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 191f6435e7c64..83c0b98d9b600 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -111,6 +111,7 @@ bool dc_stream_construct(struct dc_stream_state *stream, /* EDID CAP translation for HDMI 2.0 */ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); stream->timing.dsc_cfg.num_slices_h = 0; stream->timing.dsc_cfg.num_slices_v = 0; @@ -119,6 +120,7 @@ bool dc_stream_construct(struct dc_stream_state *stream, stream->timing.dsc_cfg.linebuf_depth = 9; stream->timing.dsc_cfg.version_minor = 2; stream->timing.dsc_cfg.ycbcr422_simple = 0; +#endif update_stream_signal(stream, dc_sink_data); @@ -864,6 +866,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream) @@ -874,6 +877,7 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, return DC_NO_DSC_RESOURCE; } } +#endif struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 32fcbedd82d4f..5fa2d2942899c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1019,6 +1019,7 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_dsc_power_gate; bool disable_optc_power_gate; bool disable_hpo_power_gate; @@ -1027,6 +1028,7 @@ struct dc_debug_options { bool disable_dio_power_gate; int dsc_min_slice_height_override; int dsc_bpp_increment_div; +#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -2634,6 +2636,7 @@ struct dc_container_id { }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps { // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'false' if they are sink's DSC caps @@ -2643,6 +2646,7 @@ struct dc_sink_dsc_caps { bool is_dsc_passthrough_supported; struct dsc_dec_dpcd_caps dsc_dec_caps; }; +#endif struct dc_sink_hblank_expansion_caps { // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 86394203cee79..baf6e9d9eeeaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -486,9 +486,11 @@ bool dc_stream_remove_writeback(struct dc *dc, struct dc_stream_state *stream, uint32_t dwb_pipe_inst); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); +#endif bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index d2e60480fb2be..4ca9934ce6ffa 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -550,7 +550,9 @@ enum dc_infoframe_type { DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_DP_INFOFRAME_TYPE_PPS = 0x10, +#endif }; struct dc_info_packet { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 87af4fdc04a6f..9ef725ec2ea8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -379,8 +379,9 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); - +#endif /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. @@ -393,6 +394,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode || psr_context->os_request_force_ffu; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && @@ -405,6 +407,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_2)))) copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; else +#endif copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 9459e8f283384..3628a949db90a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -77,7 +77,9 @@ static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc) } static const struct link_encoder_funcs dcn201_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index 36456c9971c84..bce7b78b254fa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -298,7 +298,9 @@ static void dcn21_link_encoder_disable_output(struct link_encoder *enc, static const struct link_encoder_funcs dcn21_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index 3bd35f3392dcc..2fccdb983b0aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -173,8 +173,10 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { void enc2_fec_set_enable(struct link_encoder *enc, bool enable) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_LOG_DSC("%s FEC at link encoder inst %d", enable ? "Enabling" : "Disabling", enc->id.enum_id); +#endif REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); } @@ -194,7 +196,8 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } - + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -207,6 +210,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } +#endif static bool update_cfg_data( struct dcn10_link_encoder *enc10, @@ -356,7 +360,9 @@ void enc2_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn20_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h index 762c579fcb44d..39a5f6882cf95 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h @@ -342,7 +342,9 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); bool enc2_fec_is_active(struct link_encoder *enc); void enc2_hw_init(struct link_encoder *enc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); +#endif void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index bec0b4aaeb2b9..d4adc6630c135 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,7 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, @@ -365,6 +365,7 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif /* Set Dynamic Metadata-configuration. * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME @@ -460,8 +461,10 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) { bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !timing->dsc_cfg.ycbcr422_simple); +#endif return two_pix; } @@ -632,9 +635,11 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, .dp_set_dsc_config = enc2_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index 57b9ae5fca1dc..0915a1e660520 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -56,7 +56,9 @@ bool dcn30_link_encoder_validate_output_with_stream( } static const struct link_encoder_funcs dcn30_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index e93be7b6d9b03..106e963256c44 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -295,6 +295,7 @@ void enc3_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC14_LINE, 0); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -401,6 +402,7 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( struct stream_encoder *enc, @@ -865,9 +867,11 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc3_read_state, .dp_set_dsc_config = enc3_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index de58d5886054d..2c8e1e4eb00da 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -487,7 +487,9 @@ void dcn31_link_encoder_enable_dp_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); +#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); @@ -534,7 +536,9 @@ void dcn31_link_encoder_enable_dp_mst_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); +#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 3e85e9c3d2cb2..10b307c5173a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -384,6 +384,7 @@ void enc314_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -418,6 +419,7 @@ void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -469,9 +471,11 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index 65d28cb07b046..a9bddb1206ff3 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -204,7 +204,9 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, static const struct link_encoder_funcs dcn32_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 3523d1cdc1a35..5982bc43b08b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -346,6 +346,7 @@ void enc32_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -380,6 +381,7 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -458,6 +460,7 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc32_read_state, .dp_set_dsc_config = enc32_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index 968f89295b64c..e87ba3c04b3d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -60,7 +60,9 @@ dm_write_reg(CTX, AUX_REG(reg_name), val) static const struct link_encoder_funcs dcn321_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c index c5d2e9404d943..e6bbc96c1d158 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c @@ -83,10 +83,12 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( struct stream_encoder *enc) {} +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_enc_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) {} +#endif static void virtual_dig_connect_to_otg( struct stream_encoder *enc, @@ -99,16 +101,20 @@ static void virtual_setup_stereo_sync( bool enable) {} +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_stream_encoder_set_dsc_pps_info_packet( struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) {} +#endif static const struct stream_encoder_funcs virtual_str_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_odm_combine = virtual_enc_dp_set_odm_combine, +#endif .dp_set_stream_attribute = virtual_stream_encoder_dp_set_stream_attribute, .hdmi_set_stream_attribute = @@ -135,7 +141,9 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .dig_connect_to_otg = virtual_dig_connect_to_otg, .setup_stereo_sync = virtual_setup_stereo_sync, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet, +#endif }; bool virtual_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index d5831a34f5a19..8975cd1529fa3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -174,7 +174,9 @@ enum dm_validation_status { DML_FAIL_DIO_SUPPORT, DML_FAIL_NOT_ENOUGH_DSC, DML_FAIL_DSC_CLK_REQUIRED, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DML_FAIL_DSC_VALIDATION_FAILURE, +#endif DML_FAIL_URGENT_LATENCY, DML_FAIL_REORDERING_BUFFER, DML_FAIL_DISPCLK_DPPCLK, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index ef75eb7d5adc3..e14e11ccf7d08 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "rc_calc_fpu.h" #include "qp_tables.h" @@ -257,4 +258,4 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h index d7cd8cc247583..0b70eb9bcc6b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __RC_CALC_FPU_H__ #define __RC_CALC_FPU_H__ @@ -88,3 +89,4 @@ void _do_calc_rc_params(struct rc_params *rc, int minor_version); #endif +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 5b3584ad5b6b3..49ef90b1fe5bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -22,6 +22,7 @@ * Author: AMD */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include #include "dc_hw_types.h" @@ -1457,3 +1458,4 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->slice_height_granularity = 1; options->force_dsc_when_not_needed = false; } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 242f1e6f0d8f7..dc741b65b2c0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include "reg_helper.h" @@ -774,3 +775,4 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index 2337c3a972357..c61b13208a9e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -21,6 +21,7 @@ * Authors: AMD * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __DCN20_DSC_H__ #define __DCN20_DSC_H__ @@ -616,4 +617,4 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 64cee8c80110c..d61b6430a6409 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -1,3 +1,4 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2017 Advanced Micro Devices, Inc. @@ -62,3 +63,4 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) DC_FP_END(); #endif } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 59864130cf83b..b01295c412b1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -1,3 +1,4 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2012-17 Advanced Micro Devices, Inc. * @@ -119,4 +120,4 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 759b453385c46..7b181d4f959b2 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -564,7 +564,9 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet( /* Load PPS into infoframe (SDP) registers */ pps_sdp.valid = true; pps_sdp.hb0 = 0; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; +#endif pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 5243177c1faad..7ccfcde03fa76 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -49,7 +49,9 @@ #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" +#endif #include "dio/dcn10/dcn10_dio.h" #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" @@ -680,6 +682,7 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); @@ -736,6 +739,7 @@ void dcn10_log_hw_state(struct dc *dc, } } DTN_INFO("\n"); +#endif DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 307e8f8060e6d..ea1f6a24af210 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -32,7 +32,9 @@ #include "dcn20/dcn20_resource.h" #include "dcn20_hwseq.h" #include "dce/dce_hwseq.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn20/dcn20_optc.h" #include "abm.h" #include "clk_mgr.h" @@ -456,6 +458,7 @@ void dcn20_init_blank( hws->funcs.wait_for_blank_complete(opp); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -532,6 +535,7 @@ void dcn20_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } +#endif void dcn20_dpp_pg_control( struct dce_hwseq *hws, @@ -2598,6 +2602,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2609,10 +2614,12 @@ void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } +#endif } void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2624,6 +2631,7 @@ void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } +#endif } void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h index 9d1ad3b29ca52..1424a0f2c09d8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h @@ -130,10 +130,12 @@ void dcn20_init_vm_ctx( void dcn20_set_flip_control_gsl( struct pipe_ctx *pipe_ctx, bool flip_immediate); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +#endif void dcn20_fpga_init_hw(struct dc *dc); bool dcn20_wait_for_blank_complete( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index ad253c586ea1a..8ad1455284fc9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -129,7 +129,11 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#else + .dsc_pg_control = NULL, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c index c7701a8b574aa..46b06ea163ced 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c @@ -132,7 +132,9 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 5cbae0cdda962..e091a7ccd42b6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -139,7 +139,9 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 183db4e247d32..afdb0f665ec3b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -363,8 +363,10 @@ void dcn31_enable_power_gating_plane( REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; +#endif /* DCS0/1/2/3/4/5 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 3e239124c17d8..f636f2009c512 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -222,6 +222,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -292,6 +293,7 @@ void dcn314_dsc_pg_control( } } +#endif void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { @@ -312,8 +314,10 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; +#endif /* DCS0/1/2/3/4 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 9900c87b4567f..98ae42d954542 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -145,7 +145,9 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .dpp_pg_control = dcn314_dpp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn314_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index a0aaa727e9fa3..6fef403ec4a02 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -67,6 +67,7 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -132,7 +133,7 @@ void dcn32_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - +#endif void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 43579b0e14825..bdae9bfc82299 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -201,10 +201,11 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); +#endif void (*add_phantom_pipes)( struct dc *dc, @@ -267,7 +268,9 @@ struct resource_pool { unsigned int gsl_2:1; } gsl_groups; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dscs[MAX_PIPES]; +#endif unsigned int pipe_count; unsigned int underlay_pipe_index; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 5abbf485d273e..5abc18564ad54 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -95,6 +95,7 @@ struct link_encoder { bool usbc_combo_phy; }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct link_enc_state { uint32_t dphy_fec_en; @@ -103,6 +104,7 @@ struct link_enc_state { uint32_t dp_link_training_complete; }; +#endif enum encoder_type_select { ENCODER_TYPE_DIG = 0, @@ -111,8 +113,10 @@ enum encoder_type_select { }; struct link_encoder_funcs { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); +#endif bool (*validate_output_with_stream)( struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 2f70bb476c97b..0ca7e3be1f8cd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -142,7 +142,9 @@ struct crc_params { enum crc_selection selection; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT uint8_t dsc_mode; +#endif uint8_t odm_mode; bool continuous_mode; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index 603537ffd1284..04fdc70ae6da3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -101,7 +101,9 @@ static enum link_training_result dpia_configure_link( struct link_training_settings *lt_settings) { enum dc_status status; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool fec_enable; +#endif DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", __func__, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index e7a90a437fffb..d3d3fadce5dab 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -124,6 +124,7 @@ void optc2_set_gsl_source_select( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -145,6 +146,7 @@ void optc2_set_dsc_config(struct timing_generator *optc, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, dsc_slice_width); } +#endif /* Get DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format @@ -487,9 +489,14 @@ bool optc2_configure_crc(struct timing_generator *optc, { struct optc *optc1 = DCN10TG_FROM_TG(optc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT REG_SET_2(OTG_CRC_CNTL2, 0, OTG_CRC_DSC_MODE, params->dsc_mode, OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); +#else + REG_SET(OTG_CRC_CNTL2, 0, + OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); +#endif return optc1_configure_crc(optc, params); } @@ -548,7 +555,9 @@ static const struct timing_generator_funcs dcn20_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = optc2_set_dwb_source, .set_odm_bypass = optc2_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 928e110b95fb5..09f16dc1c5048 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -98,10 +98,12 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc2_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); +#endif void optc2_get_dsc_status(struct timing_generator *optc, uint32_t *dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c index 772a8bfb949c1..fcc5d6138e5a6 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c @@ -172,7 +172,9 @@ static const struct timing_generator_funcs dcn201_tg_funcs = { .clear_optc_underflow = optc1_clear_optc_underflow, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, +#endif .set_dwb_source = NULL, .get_optc_source = optc201_get_optc_source, .set_vtg_params = optc1_set_vtg_params, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index ee4665aa49e9f..ddf112c87267d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -176,6 +176,7 @@ void optc3_set_vtotal_change_limit(struct timing_generator *optc, } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -191,6 +192,7 @@ void optc3_set_dsc_config(struct timing_generator *optc, optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); } +#endif void optc3_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) @@ -400,7 +402,9 @@ static const struct timing_generator_funcs dcn30_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index e2303f9eaf13b..f3ca2df9a3a00 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -348,10 +348,12 @@ void optc3_program_blank_color(struct timing_generator *optc, void optc3_set_vtotal_change_limit(struct timing_generator *optc, uint32_t limit); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc3_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); +#endif void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index 43ff957288b27..d94b1edd6d87d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -237,7 +237,9 @@ static const struct timing_generator_funcs dcn314_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .get_optc_source = optc2_get_optc_source, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 3dcb0d0c931cf..2cda3517e7caf 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -342,7 +342,9 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc32_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 6731544f0981b..20da3ae307bec 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -618,6 +618,7 @@ static int map_transmitter_id_to_phy_instance( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -639,6 +640,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dccg_registers dccg_regs = { DCCG_REG_LIST_DCN2() @@ -662,7 +664,9 @@ static const struct resource_caps res_cap_nv10 = { .num_dwb = 1, .num_ddc = 6, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -700,7 +704,9 @@ static const struct resource_caps res_cap_nv14 = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, +#endif }; static const struct dc_debug_options debug_defaults_drv = { @@ -1057,7 +1063,7 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1078,7 +1084,7 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) kfree(container_of(*dsc, struct dcn20_dsc, base)); *dsc = NULL; } - +#endif static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { @@ -1091,10 +1097,12 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1322,7 +1330,7 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1372,8 +1380,6 @@ void dcn20_release_dsc(struct resource_context *res_ctx, } } - - enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) @@ -1429,7 +1435,7 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, else return DC_OK; } - +#endif enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1440,9 +1446,11 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, if (result == DC_OK) result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); +#endif if (result == DC_OK) result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); @@ -1455,7 +1463,9 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ { enum dc_status result = DC_OK; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); +#endif return result; } @@ -1494,7 +1504,9 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT next_odm_pipe->stream_res.dsc = NULL; +#endif if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; @@ -1521,12 +1533,14 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); ASSERT(next_odm_pipe->stream_res.dsc); if (next_odm_pipe->stream_res.dsc == NULL) return false; } +#endif return true; } @@ -1550,7 +1564,9 @@ void dcn20_split_stream_for_mpc( secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT secondary_pipe->stream_res.dsc = NULL; +#endif if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -1641,6 +1657,7 @@ void dcn20_set_mcif_arb_params( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1676,6 +1693,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) } return true; } +#endif struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, @@ -1779,8 +1797,10 @@ void dcn20_merge_pipes_for_validate( odm_pipe->bottom_pipe = NULL; odm_pipe->prev_odm_pipe = NULL; odm_pipe->next_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (odm_pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); +#endif /* Clear plane_res and stream_res */ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); @@ -2224,7 +2244,9 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, @@ -2693,6 +2715,7 @@ static bool dcn20_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn20_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2701,6 +2724,7 @@ static bool dcn20_resource_construct( goto create_fail; } } +#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h index e997d35a8b86e..072bfaa3185c8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h @@ -132,7 +132,9 @@ int dcn20_validate_apply_pipe_split_flags( void dcn20_release_dsc(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); +#endif void dcn20_split_stream_for_mpc( struct resource_context *res_ctx, const struct resource_pool *pool, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index 90d38631f63a0..a4b7e56dc6bdb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1073,7 +1073,9 @@ static struct resource_funcs dcn201_res_pool_funcs = { .validate_bandwidth = dcn20_validate_bandwidth, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = NULL, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 107612595db60..834eddbb74c99 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -362,6 +362,7 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -383,6 +384,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif #define ipp_regs(id)\ [id] = {\ @@ -578,7 +580,9 @@ static const struct resource_caps res_cap_rn = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -664,10 +668,12 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -900,12 +906,14 @@ bool dcn21_fast_validate_bw(struct dc *dc, ASSERT(0); } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif *vlevel_out = vlevel; @@ -1086,7 +1094,7 @@ static void read_dce_straps( } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1101,6 +1109,7 @@ static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) { @@ -1369,7 +1378,9 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .validate_bandwidth = dcn21_validate_bandwidth, .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, @@ -1655,6 +1666,7 @@ static bool dcn21_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1663,6 +1675,7 @@ static bool dcn21_resource_construct( goto create_fail; } } +#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 6cfdc37dab588..10c4b75ebbc07 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -46,7 +46,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -511,6 +513,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN20(0), dsc_regsDCN20(1), @@ -527,6 +530,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -677,7 +681,9 @@ static const struct resource_caps res_cap_dcn3 = { .num_ddc = 6, .num_vmid = 16, .num_mpc_3dlut = 3, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1084,10 +1090,12 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1265,6 +1273,7 @@ static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn30_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1279,6 +1288,7 @@ static struct display_stream_compressor *dcn30_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1539,7 +1549,9 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT sec_pipe->stream_res.dsc = NULL; +#endif if (odm) { if (pri_pipe->next_odm_pipe) { ASSERT(pri_pipe->next_odm_pipe != sec_pipe); @@ -1561,12 +1573,14 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->stream_res.opp = pool->opps[pipe_idx]; else sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (sec_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) return false; } +#endif } else { if (pri_pipe->bottom_pipe) { ASSERT(pri_pipe->bottom_pipe != sec_pipe); @@ -1741,8 +1755,10 @@ noinline bool dcn30_internal_validate_bw( pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); +#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); repopulate_pipes = true; @@ -1861,11 +1877,13 @@ noinline bool dcn30_internal_validate_bw( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif if (repopulate_pipes) pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); @@ -2242,7 +2260,9 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2536,6 +2556,7 @@ static bool dcn30_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2544,6 +2565,7 @@ static bool dcn30_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn30_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index ef02cf0045ba2..4dcd20ed09412 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1404,7 +1404,9 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 5f0fe6e5bd821..ed52cddd3f37f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -574,6 +574,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN314(0), dsc_regsDCN314(1), @@ -588,6 +589,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -1444,10 +1446,12 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1621,6 +1625,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn314_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1635,6 +1640,7 @@ static struct display_stream_compressor *dcn314_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn314_destroy_resource_pool(struct resource_pool **pool) { @@ -1772,7 +1778,9 @@ static struct resource_funcs dcn314_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2068,6 +2076,7 @@ static bool dcn314_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn314_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2076,6 +2085,7 @@ static bool dcn314_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 3ae787a377b18..df48398b3e8a0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -49,7 +49,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -566,6 +568,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -584,6 +587,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -823,7 +827,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1386,10 +1392,12 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1564,6 +1572,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1578,6 +1587,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn315_destroy_resource_pool(struct resource_pool **pool) { @@ -1836,7 +1846,9 @@ static struct resource_funcs dcn315_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2093,6 +2105,7 @@ static bool dcn315_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2101,6 +2114,7 @@ static bool dcn315_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 4b8668458f038..2284a9e9de861 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -49,7 +49,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -557,6 +559,8 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -575,6 +579,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -818,7 +823,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1381,10 +1388,12 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1556,6 +1565,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1570,6 +1580,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn316_destroy_resource_pool(struct resource_pool **pool) { @@ -1712,7 +1723,9 @@ static struct resource_funcs dcn316_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -1960,6 +1973,7 @@ static bool dcn316_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1968,6 +1982,7 @@ static bool dcn316_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index a55078458ba54..036e197075b7d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -438,6 +438,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { #define dsc_regsDCN20_init(id)\ DSC_REG_LIST_DCN20_RI(id) +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = { @@ -447,6 +448,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static struct dcn30_mpc_registers mpc_regs; @@ -1391,10 +1393,12 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1562,6 +1566,7 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1586,6 +1591,7 @@ static struct display_stream_compressor *dcn32_dsc_create( return &dsc->base; } +#endif static void dcn32_destroy_resource_pool(struct resource_pool **pool) { @@ -2102,7 +2108,9 @@ static struct resource_funcs dcn32_res_pool_funcs = { .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2450,6 +2458,7 @@ static bool dcn32_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSCs */ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn32_dsc_create(ctx, i); @@ -2459,6 +2468,7 @@ static bool dcn32_resource_construct( goto create_fail; } } +#endif /* DWB */ if (!dcn32_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index f5a4e97c40ced..eb78191838c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -128,8 +128,10 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc, pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); +#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { From 2d5d3e753c8e427dab82a5d9b1cccf6b4371b8b9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Jun 2022 11:16:02 +0800 Subject: [PATCH 0856/2070] drm/amdkfd: remove redundant sg_table* argument This is caused by dropping of patch v5.16-1998-g1d11a577d7f0 "drm/amdkfd: Add CMA API" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 0a6eaa653acba..e9f244e1accc3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2451,7 +2451,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - NULL, kgd_mem, &offset, + kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); From 0e1d1bf33e4cc9aa4e2d9cdf9c94b82c160b6aea Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 7 Mar 2022 16:42:59 +0800 Subject: [PATCH 0857/2070] Revert "drm/amdkfd: add reset lock protection for kfd entry functions" This reverts commit f09bc5e4580c1aa0c2d7eb43b762f58dbd239423. Signed-off-by: Ma Jun Change-Id: I7e7c136bb9831224bb0fc749f2f109b6f9e8d976 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 14 -------------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 - 3 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e9f244e1accc3..057b310b7e776 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1278,7 +1278,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, GET_IDR_HANDLE(args->handle)); if (!buf_obj) { ret = -EINVAL; - goto err_unlock; + goto err_pdd; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, @@ -1382,6 +1382,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ((struct kgd_mem *)mem)->domain); + goto map_memory_to_gpu_failed; } args->n_success = i+1; @@ -1510,7 +1511,6 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, mutex_unlock(&p->mutex); kfree(devices_arr); - return 0; bind_process_to_device_failed: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 6021077f7199b..9cb5155809752 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -193,18 +193,11 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, return -EINVAL; mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, va_addr, handle, mmap_offset, false); - amdgpu_read_unlock(dev->ddev); - -err_unlock: mutex_unlock(&p->mutex); - dma_buf_put(dmabuf); return r; } @@ -238,9 +231,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!restore) { mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; } r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, @@ -248,7 +238,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, va_addr, handle, mmap_offset, restore); if (!restore) { - amdgpu_read_unlock(dev->ddev); mutex_unlock(&p->mutex); } if (r) @@ -259,9 +248,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, return r; -err_unlock: - mutex_unlock(&p->mutex); - error_unref: kfd_ipc_obj_put(&found); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 86c0e5e18cf92..7455ac0c6e616 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1066,7 +1066,6 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } - run_rdma_free_callback(buf_obj); amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); From 983fe24cacbd2c638a63823e2d0353c9ab35df51 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Jun 2022 17:38:36 +0800 Subject: [PATCH 0858/2070] drm/amdkcl: fake drm_gem_ttm_vmap which the type of second arg is dma_buf_map pointer Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++- .../include/kcl/kcl_drm_gem_ttm_helper.h | 20 +++++++++- .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 38 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 21 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 84 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c9b5ba712939c..33ebbc27029bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -452,9 +452,12 @@ const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, -#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#elif defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) + .vmap = amdgpu_drm_gem_ttm_vmap, + .vunmap = amdgpu_drm_gem_ttm_vunmap, #else .vmap = amdgpu_gem_prime_vmap, .vunmap = amdgpu_gem_prime_vunmap, diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index ae25af4cbc8c5..aa89982b0c2c7 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -5,10 +5,28 @@ #include #include -#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +#if !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr); void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +static inline +void amdgpu_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + _kcl_drm_gem_ttm_vunmap(gem, map); +} + +static inline +int amdgpu_drm_gem_ttm_vmap(struct drm_gem_object *obj, + struct dma_buf_map *map) +{ + return _kcl_drm_gem_ttm_vmap(obj, map); +} #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 2cef03209d156..04b308171928f 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #ifndef drm_gem_ttm_of_gem @@ -18,7 +19,7 @@ void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); - struct dma_buf_map map; + struct iosys_map map; ttm_bo_vmap(bo, &map); return map.vaddr; @@ -28,11 +29,44 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - struct dma_buf_map map; + struct iosys_map map; map.vaddr = vaddr; map.is_iomem = bo->resource->bus.is_iomem; ttm_bo_vunmap(bo, &map); } +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) + +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + int r; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + r = ttm_bo_vmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; + return r; +} + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + ttm_bo_vunmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; +} #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a0634b8db8361..1248b6b2a1b32 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -515,6 +515,9 @@ /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 +/* drm_gem_object_funcs.vmap hsa iosys_map arg */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 + /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 index cb583a5e9dafd..6631ba066edcf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -31,3 +31,24 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ ]) ]) ]) + + +dnl # +dnl # commit v5.17-rc2-157-g7938f4218168 +dnl # dma-buf-map: Rename to iosys-map +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + struct iosys_map *map = NULL; + funcs->vmap(NULL, map); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG, 1, + [drm_gem_object_funcs.vmap hsa iosys_map arg]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c93e18a73e7d8..b1b8aca5a67bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -160,6 +160,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED + AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 40cfebe29263944eee10fb4cbd946254f22205c3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 29 Jun 2022 14:11:03 +0800 Subject: [PATCH 0859/2070] drm/amdkcl: Test whether drm_memcpy_from_wc argument type is struct iosys_map Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- .../gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 | 17 ++++++++++++++--- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1248b6b2a1b32..37194b7709bdd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -558,7 +558,10 @@ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 /* drm_memcpy_from_wc() is availablea */ -#define HAVE_DRM_MEMCPY_FROM_WC 1 +/* #undef HAVE_DRM_MEMCPY_FROM_WC */ + +/* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ +#define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 /* whether drm_mm_insert_mode is available */ #define HAVE_DRM_MM_INSERT_MODE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 index 491ada31c112a..8ab4aaf2521dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -6,11 +6,22 @@ AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ], [ - drm_memcpy_from_wc(NULL, NULL, 0); + struct iosys_map *dst = NULL, *src = NULL; + drm_memcpy_from_wc(dst, src, 0); ], [ - AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, - [drm_memcpy_from_wc() is availablea]) + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG, 1, + [drm_memcpy_from_wc() is availablea and has struct iosys_map* arg]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index be989c5751c47..31451bb23ffb1 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -117,7 +117,7 @@ void ttm_move_memcpy(bool clear, dst_ops->map_local(dst_iter, &dst_map, i); src_ops->map_local(src_iter, &src_map, i); -#ifdef HAVE_DRM_MEMCPY_FROM_WC +#ifdef HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE); #else if (!src_map.is_iomem && !dst_map.is_iomem) { From 0e2d2e410a5f3157646a6f4ca649963bd1d82eca Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 4 Jul 2022 13:54:52 +0800 Subject: [PATCH 0860/2070] drm/amdkfd: using TTM provided vram usage function Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index b1be1de6bb04e..fb2be29c61be9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -596,7 +596,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) { - return amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); + return ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); } int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) From d278fbaeb8e6bbe7e8a048c4eae1ee145807899e Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Fri, 20 Aug 2021 12:53:14 -0500 Subject: [PATCH 0861/2070] drm/amdkfd: ref count init for device pages Ref counter from device pages is init to zero during memmap init zone. The first time a new device page is allocated to migrate data into it, its ref counter needs to be initialized to one. Signed-off-by: Alex Sierra Reviewed-by: Felix Kuehling drm/amdkfd: Fix DEVICE_PRIVATE page leak on 5.18 commit 27674ef6c73f ("mm: remove the extra ZONE_DEVICE struct page refcount") removed an extra reference count for ZONE_DEVICE pages. This requires a corresponding driver change (which was part of that patch). For DKMS builds, conditionally get a page reference only on old kernels without this patch. CONFIG_DEV_PAGEMAP_OPS is a suitable indicator, because this option was removed by the patch, and was previously selected by CONFIG_DEVICE_PRIVATE. Signed-off-by: Felix Kuehling Reviewed-by: Alex Sierra drm/amdkfd: Remove deprecated references to ZONE_DEVICE_PUBLIC This was replaced by ZONE_DEVICE_COHERENT in the final upstream version. Signed-off-by: Felix Kuehling Reviewed-by: Alex Sierra drm/amdkfd: Fix HMM migrations on monolithic builds Use the new zone_device_page_init KCL helper, which encapsulates all the logic around locking and reference counting device pages. This makes the DKMS branch code in svm_migrate_get_vram_page look the same as upstream. Cc: Flora Cui Signed-off-by: Felix Kuehling Reviewed-and-tested-by: Guchun Chen From cfeef78790130961f04237fc4190548987d997df Mon Sep 17 00:00:00 2001 From: George Cave Date: Tue, 5 Jul 2022 17:56:04 -0400 Subject: [PATCH 0862/2070] drm/amdkcl: Add directory to included header path As of RedHat 9.1, building the DKMS module fails due to it being unable to find a stdarg.h header. This file is available in a directory that is not included via the compiler, but can be by adding the subdirectory it resides in at the include point. Signed-off-by: George Cave Reviewed-by: Flora Cui flora.cui@amd.com --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 907a902c5f204..9e0c95502367c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -24,7 +24,7 @@ */ #include #include -#include +#include #if !defined(HAVE_DRM_DRM_PRINT_H) void drm_printf(struct drm_printer *p, const char *f, ...) From 2b7f550a9dfc5846fb81f10d48f46febdb015a8a Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:10:31 -0400 Subject: [PATCH 0863/2070] drm/amdkfd: Add CMA API This is similar to Cross Memory Attach, except that it uses SDMA to copy data between processes, and can access GPU memory that's not CPU accessible. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 86 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 841 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 32 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- include/uapi/linux/kfd_ioctl.h | 35 + 6 files changed, 998 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 2ef9ac31f31e8..8df3abc999192 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -182,6 +182,11 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, + uint64_t src_offset, struct kgd_mem *dst_mem, + uint64_t dest_offset, uint64_t size, struct dma_fence **f, + uint64_t *actual_size); + bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, @@ -317,7 +322,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint8_t xcp_id); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct kgd_mem **mem, + void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index b78f6684f609e..138ef4e909fba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1784,13 +1784,12 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct kgd_mem **mem, + void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume) { struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); enum ttm_bo_type bo_type = ttm_bo_type_device; - struct sg_table *sg = NULL; uint64_t user_addr = 0; struct amdgpu_bo *bo; struct drm_gem_object *gobj = NULL; @@ -1853,6 +1852,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; + if (sg) { + alloc_domain = AMDGPU_GEM_DOMAIN_CPU; + bo_type = ttm_bo_type_sg; + } *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); if (!*mem) { ret = -ENOMEM; @@ -3589,6 +3592,85 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, + uint64_t src_offset, struct kgd_mem *dst_mem, + uint64_t dst_offset, uint64_t size, + struct dma_fence **f, uint64_t *actual_size) +{ + struct amdgpu_device *adev = NULL; + struct amdgpu_copy_mem src, dst; + struct ww_acquire_ctx ticket; + struct list_head list, duplicates; + struct ttm_validate_buffer resv_list[2]; + struct dma_fence *fence = NULL; + int i, r; + + if (!kgd || !src_mem || !dst_mem || !actual_size) + return -EINVAL; + + *actual_size = 0; + + adev = get_amdgpu_device(kgd); + INIT_LIST_HEAD(&list); + INIT_LIST_HEAD(&duplicates); + + src.bo = &src_mem->bo->tbo; + dst.bo = &dst_mem->bo->tbo; + src.mem = &src.bo->mem; + dst.mem = &dst.bo->mem; + src.offset = src_offset; + dst.offset = dst_offset; + + resv_list[0].bo = src.bo; + resv_list[1].bo = dst.bo; + + for (i = 0; i < 2; i++) { + resv_list[i].num_shared = 1; + list_add_tail(&resv_list[i].head, &list); + } + + r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); + if (r) { + pr_err("Copy buffer failed. Unable to reserve bo (%d)\n", r); + return r; + } + + /* The process to which the Source and Dest BOs belong to could be + * evicted and the BOs invalidated. So validate BOs before use + */ + r = amdgpu_amdkfd_bo_validate(src_mem->bo, src_mem->domain, false); + if (r) { + pr_err("CMA fail: SRC BO validate failed %d\n", r); + goto validate_fail; + } + + + r = amdgpu_amdkfd_bo_validate(dst_mem->bo, dst_mem->domain, false); + if (r) { + pr_err("CMA fail: DST BO validate failed %d\n", r); + goto validate_fail; + } + + + r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, size, false, NULL, + &fence); + if (r) + pr_err("Copy buffer failed %d\n", r); + else + *actual_size = size; + if (fence) { + amdgpu_bo_fence(src_mem->bo, fence, true); + amdgpu_bo_fence(dst_mem->bo, fence, true); + } + if (f) + *f = dma_fence_get(fence); + dma_fence_put(fence); + +validate_fail: + ttm_eu_backoff_reservation(&ticket, &list); + return r; +} + /* Returns GPU-specific tiling mode information */ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 057b310b7e776..b2351b10718d8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1196,7 +1196,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->adev, args->va_addr, args->size, - pdd->drm_priv, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, NULL, (struct kgd_mem **) &mem, &offset, flags, false); if (err) @@ -1715,6 +1715,843 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, return r; } +/* Maximum number of entries for process pages array which lives on stack */ +#define MAX_PP_STACK_COUNT 16 +/* Maximum number of pages kmalloc'd to hold struct page's during copy */ +#define MAX_KMALLOC_PAGES (PAGE_SIZE * 2) +#define MAX_PP_KMALLOC_COUNT (MAX_KMALLOC_PAGES/sizeof(struct page *)) + +static void kfd_put_sg_table(struct sg_table *sg) +{ + unsigned int i; + struct scatterlist *s; + + for_each_sg(sg->sgl, s, sg->nents, i) + put_page(sg_page(s)); +} + + +/* Create a sg table for the given userptr BO by pinning its system pages + * @bo: userptr BO + * @offset: Offset into BO + * @mm/@task: mm_struct & task_struct of the process that holds the BO + * @size: in/out: desired size / actual size which could be smaller + * @sg_size: out: Size of sg table. This is ALIGN_UP(@size) + * @ret_sg: out sg table + */ +static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, + int64_t offset, int cma_write, + struct mm_struct *mm, + struct task_struct *task, + uint64_t *size, + uint64_t *sg_size, + struct sg_table **ret_sg) +{ + int ret, locked = 1; + struct sg_table *sg = NULL; + unsigned int i, offset_in_page, flags = 0; + unsigned long nents, n; + unsigned long pa = (bo->cpuva + offset) & PAGE_MASK; + unsigned int cur_page = 0; + struct scatterlist *s; + uint64_t sz = *size; + struct page **process_pages; + + *sg_size = 0; + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) + return -ENOMEM; + + offset_in_page = offset & (PAGE_SIZE - 1); + nents = (sz + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; + + ret = sg_alloc_table(sg, nents, GFP_KERNEL); + if (unlikely(ret)) { + ret = -ENOMEM; + goto sg_alloc_fail; + } + process_pages = kmalloc_array(nents, sizeof(struct pages *), + GFP_KERNEL); + if (!process_pages) { + ret = -ENOMEM; + goto page_alloc_fail; + } + + if (cma_write) + flags = FOLL_WRITE; + locked = 1; + mmap_read_lock(mm); + n = get_user_pages_remote(mm, pa, nents, flags, process_pages, + NULL, &locked); + if (locked) + mmap_read_unlock(mm); + if (n <= 0) { + pr_err("CMA: Invalid virtual address 0x%lx\n", pa); + ret = -EFAULT; + goto get_user_fail; + } + if (n != nents) { + /* Pages pinned < requested. Set the size accordingly */ + *size = (n * PAGE_SIZE) - offset_in_page; + pr_debug("Requested %lx but pinned %lx\n", nents, n); + } + + sz = 0; + for_each_sg(sg->sgl, s, n, i) { + sg_set_page(s, process_pages[cur_page], PAGE_SIZE, + offset_in_page); + sg_dma_address(s) = page_to_phys(process_pages[cur_page]); + offset_in_page = 0; + cur_page++; + sz += PAGE_SIZE; + } + *ret_sg = sg; + *sg_size = sz; + + kfree(process_pages); + return 0; + +get_user_fail: + kfree(process_pages); +page_alloc_fail: + sg_free_table(sg); +sg_alloc_fail: + kfree(sg); + return ret; +} + +static void kfd_free_cma_bos(struct cma_iter *ci) +{ + struct cma_system_bo *cma_bo, *tmp; + + list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { + struct kfd_dev *dev = cma_bo->dev; + + /* sg table is deleted by free_memory_of_gpu */ + if (cma_bo->sg) + kfd_put_sg_table(cma_bo->sg); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); + list_del(&cma_bo->list); + kfree(cma_bo); + } +} + +/* 1 second timeout */ +#define CMA_WAIT_TIMEOUT msecs_to_jiffies(1000) + +static int kfd_cma_fence_wait(struct dma_fence *f) +{ + int ret; + + ret = dma_fence_wait_timeout(f, false, CMA_WAIT_TIMEOUT); + if (likely(ret > 0)) + return 0; + if (!ret) + ret = -ETIME; + return ret; +} + +/* Put previous (old) fence @pf but it waits for @pf to signal if the context + * of the current fence @cf is different. + */ +static int kfd_fence_put_wait_if_diff_context(struct dma_fence *cf, + struct dma_fence *pf) +{ + int ret = 0; + + if (pf && cf && cf->context != pf->context) + ret = kfd_cma_fence_wait(pf); + dma_fence_put(pf); + return ret; +} + +#define MAX_SYSTEM_BO_SIZE (512*PAGE_SIZE) + +/* Create an equivalent system BO for the given @bo. If @bo is a userptr then + * create a new system BO by pinning underlying system pages of the given + * userptr BO. If @bo is in Local Memory then create an empty system BO and + * then copy @bo into this new BO. + * @bo: Userptr BO or Local Memory BO + * @offset: Offset into bo + * @size: in/out: The size of the new BO could be less than requested if all + * the pages couldn't be pinned or size > MAX_SYSTEM_BO_SIZE. This would + * be reflected in @size + * @mm/@task: mm/task to which @bo belongs to + * @cma_bo: out: new system BO + */ +static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, + uint64_t *size, uint64_t offset, + int cma_write, struct kfd_process *p, + struct mm_struct *mm, + struct task_struct *task, + struct cma_system_bo **cma_bo) +{ + int ret; + struct kfd_process_device *pdd = NULL; + struct cma_system_bo *cbo; + uint64_t bo_size = 0; + struct dma_fence *f; + + uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | + KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; + + *cma_bo = NULL; + cbo = kzalloc(sizeof(**cma_bo), GFP_KERNEL); + if (!cbo) + return -ENOMEM; + + INIT_LIST_HEAD(&cbo->list); + if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) + bo_size = min_t(uint64_t, *size, MAX_SYSTEM_BO_SIZE); + else if (bo->cpuva) { + ret = kfd_create_sg_table_from_userptr_bo(bo, offset, + cma_write, mm, task, + size, &bo_size, + &cbo->sg); + if (ret) { + pr_err("CMA: BO create with sg failed %d\n", ret); + goto sg_fail; + } + } else { + WARN_ON(1); + ret = -EINVAL; + goto sg_fail; + } + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(kdev, p); + if (!pdd) { + mutex_unlock(&p->mutex); + pr_err("Process device data doesn't exist\n"); + ret = -EINVAL; + goto pdd_fail; + } + + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, + pdd->drm_priv, cbo->sg, + &cbo->mem, NULL, flags); + mutex_unlock(&p->mutex); + if (ret) { + pr_err("Failed to create shadow system BO %d\n", ret); + goto pdd_fail; + } + + if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, + offset, cbo->mem, 0, + bo_size, &f, size); + if (ret) { + pr_err("CMA: Intermediate copy failed %d\n", ret); + goto copy_fail; + } + + /* Wait for the copy to finish as subsequent copy will be done + * by different device + */ + ret = kfd_cma_fence_wait(f); + dma_fence_put(f); + if (ret) { + pr_err("CMA: Intermediate copy timed out %d\n", ret); + goto copy_fail; + } + } + + cbo->dev = kdev; + *cma_bo = cbo; + + return ret; + +copy_fail: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); +pdd_fail: + if (cbo->sg) { + kfd_put_sg_table(cbo->sg); + sg_free_table(cbo->sg); + kfree(cbo->sg); + } +sg_fail: + kfree(cbo); + return ret; +} + +/* Update cma_iter.cur_bo with KFD BO that is assocaited with + * cma_iter.array.va_addr + */ +static int kfd_cma_iter_update_bo(struct cma_iter *ci) +{ + struct kfd_memory_range *arr = ci->array; + uint64_t va_end = arr->va_addr + arr->size - 1; + + mutex_lock(&ci->p->mutex); + ci->cur_bo = kfd_process_find_bo_from_interval(ci->p, arr->va_addr, + va_end); + mutex_unlock(&ci->p->mutex); + + if (!ci->cur_bo || va_end > ci->cur_bo->it.last) { + pr_err("CMA failed. Range out of bounds\n"); + return -EFAULT; + } + return 0; +} + +/* Advance iter by @size bytes. */ +static int kfd_cma_iter_advance(struct cma_iter *ci, unsigned long size) +{ + int ret = 0; + + ci->offset += size; + if (WARN_ON(size > ci->total || ci->offset > ci->array->size)) + return -EFAULT; + ci->total -= size; + /* If current range is copied, move to next range if available. */ + if (ci->offset == ci->array->size) { + + /* End of all ranges */ + if (!(--ci->nr_segs)) + return 0; + + ci->array++; + ci->offset = 0; + ret = kfd_cma_iter_update_bo(ci); + if (ret) + return ret; + } + ci->bo_offset = (ci->array->va_addr + ci->offset) - + ci->cur_bo->it.start; + return ret; +} + +static int kfd_cma_iter_init(struct kfd_memory_range *arr, unsigned long segs, + struct kfd_process *p, struct mm_struct *mm, + struct task_struct *task, struct cma_iter *ci) +{ + int ret; + int nr; + + if (!arr || !segs) + return -EINVAL; + + memset(ci, 0, sizeof(*ci)); + INIT_LIST_HEAD(&ci->cma_list); + ci->array = arr; + ci->nr_segs = segs; + ci->p = p; + ci->offset = 0; + ci->mm = mm; + ci->task = task; + for (nr = 0; nr < segs; nr++) + ci->total += arr[nr].size; + + /* Valid but size is 0. So copied will also be 0 */ + if (!ci->total) + return 0; + + ret = kfd_cma_iter_update_bo(ci); + if (!ret) + ci->bo_offset = arr->va_addr - ci->cur_bo->it.start; + return ret; +} + +static bool kfd_cma_iter_end(struct cma_iter *ci) +{ + if (!(ci->nr_segs) || !(ci->total)) + return true; + return false; +} + +/* Copies @size bytes from si->cur_bo to di->cur_bo BO. The function assumes + * both source and dest. BOs are userptr BOs. Both BOs can either belong to + * current process or one of the BOs can belong to a differnt + * process. @Returns 0 on success, -ve on failure + * + * @si: Source iter + * @di: Dest. iter + * @cma_write: Indicates if it is write to remote or read from remote + * @size: amount of bytes to be copied + * @copied: Return number of bytes actually copied. + */ +static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, + bool cma_write, uint64_t size, + uint64_t *copied) +{ + int i, ret = 0, locked; + unsigned int nents, nl; + unsigned int offset_in_page; + struct page *pp_stack[MAX_PP_STACK_COUNT]; + struct page **process_pages = pp_stack; + unsigned long rva, lva = 0, flags = 0; + uint64_t copy_size, to_copy = size; + struct cma_iter *li, *ri; + + if (cma_write) { + ri = di; + li = si; + flags |= FOLL_WRITE; + } else { + li = di; + ri = si; + } + /* rva: remote virtual address. Page aligned to start page. + * rva + offset_in_page: Points to remote start address + * lva: local virtual address. Points to the start address. + * nents: computes number of remote pages to request + */ + offset_in_page = ri->bo_offset & (PAGE_SIZE - 1); + rva = (ri->cur_bo->cpuva + ri->bo_offset) & PAGE_MASK; + lva = li->cur_bo->cpuva + li->bo_offset; + + nents = (size + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; + + copy_size = min_t(uint64_t, size, PAGE_SIZE - offset_in_page); + *copied = 0; + + if (nents > MAX_PP_STACK_COUNT) { + /* For reliability kmalloc only 2 pages worth */ + process_pages = kmalloc(min_t(size_t, MAX_KMALLOC_PAGES, + sizeof(struct pages *)*nents), + GFP_KERNEL); + + if (!process_pages) + return -ENOMEM; + } + + while (nents && to_copy) { + nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); + locked = 1; + mmap_read_lock(ri->mm); + nl = get_user_pages_remote(ri->mm, rva, nl, + flags, process_pages, NULL, + &locked); + if (locked) + mmap_read_unlock(ri->mm); + if (nl <= 0) { + pr_err("CMA: Invalid virtual address 0x%lx\n", rva); + ret = -EFAULT; + break; + } + + for (i = 0; i < nl; i++) { + unsigned int n; + void *kaddr = kmap(process_pages[i]); + + if (cma_write) { + n = copy_from_user(kaddr+offset_in_page, + (void *)lva, copy_size); + set_page_dirty(process_pages[i]); + } else { + n = copy_to_user((void *)lva, + kaddr+offset_in_page, + copy_size); + } + kunmap(kaddr); + if (n) { + ret = -EFAULT; + break; + } + to_copy -= copy_size; + if (!to_copy) + break; + lva += copy_size; + rva += (copy_size + offset_in_page); + WARN_ONCE(rva & (PAGE_SIZE - 1), + "CMA: Error in remote VA computation"); + offset_in_page = 0; + copy_size = min_t(uint64_t, to_copy, PAGE_SIZE); + } + + for (i = 0; i < nl; i++) + put_page(process_pages[i]); + + if (ret) + break; + nents -= nl; + } + + if (process_pages != pp_stack) + kfree(process_pages); + + *copied = (size - to_copy); + return ret; + +} + +static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, + struct kfd_process *p, struct kgd_mem **mem) +{ + int ret; + struct kfd_process_device *pdd = NULL; + uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | + KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; + + if (!mem || !size || !p || !kdev) + return -EINVAL; + + *mem = NULL; + + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(kdev, p); + if (!pdd) { + mutex_unlock(&p->mutex); + pr_err("Process device data doesn't exist\n"); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, + pdd->drm_priv, NULL, + mem, NULL, flags); + mutex_unlock(&p->mutex); + if (ret) { + pr_err("Failed to create shadow system BO %d\n", ret); + return -EINVAL; + } + + return 0; +} + +static int kfd_destroy_kgd_mem(struct kgd_mem *mem) +{ + if (!mem) + return -EINVAL; + + /* param adev is not used*/ + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); +} + +/* Copies @size bytes from si->cur_bo to di->cur_bo starting at their + * respective offset. + * @si: Source iter + * @di: Dest. iter + * @cma_write: Indicates if it is write to remote or read from remote + * @size: amount of bytes to be copied + * @f: Return the last fence if any + * @copied: Return number of bytes actually copied. + */ +static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, + int cma_write, uint64_t size, + struct dma_fence **f, uint64_t *copied, + struct kgd_mem **tmp_mem) +{ + int err = 0; + struct kfd_bo *dst_bo = di->cur_bo, *src_bo = si->cur_bo; + uint64_t src_offset = si->bo_offset, dst_offset = di->bo_offset; + struct kgd_mem *src_mem = src_bo->mem, *dst_mem = dst_bo->mem; + struct kfd_dev *dev = dst_bo->dev; + int d2d = 0; + + *copied = 0; + if (f) + *f = NULL; + if (src_bo->cpuva && dst_bo->cpuva) + return kfd_copy_userptr_bos(si, di, cma_write, size, copied); + + /* If either source or dest. is userptr, create a shadow system BO + * by using the underlying userptr BO pages. Then use this shadow + * BO for copy. src_offset & dst_offset are adjusted because the new BO + * is only created for the window (offset, size) requested. + * The shadow BO is created on the other device. This means if the + * other BO is a device memory, the copy will be using that device. + * The BOs are stored in cma_list for deferred cleanup. This minimizes + * fence waiting just to the last fence. + */ + if (src_bo->cpuva) { + dev = dst_bo->dev; + err = kfd_create_cma_system_bo(dev, src_bo, &size, + si->bo_offset, cma_write, + si->p, si->mm, si->task, + &si->cma_bo); + src_mem = si->cma_bo->mem; + src_offset = si->bo_offset & (PAGE_SIZE - 1); + list_add_tail(&si->cma_bo->list, &si->cma_list); + } else if (dst_bo->cpuva) { + dev = src_bo->dev; + err = kfd_create_cma_system_bo(dev, dst_bo, &size, + di->bo_offset, cma_write, + di->p, di->mm, di->task, + &di->cma_bo); + dst_mem = di->cma_bo->mem; + dst_offset = di->bo_offset & (PAGE_SIZE - 1); + list_add_tail(&di->cma_bo->list, &di->cma_list); + } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { + /* This indicates that atleast on of the BO is in local mem. + * If both are in local mem of different devices then create an + * intermediate System BO and do a double copy + * [VRAM]--gpu1-->[System BO]--gpu2-->[VRAM]. + * If only one BO is in VRAM then use that GPU to do the copy + */ + if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM && + dst_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + dev = dst_bo->dev; + size = min_t(uint64_t, size, MAX_SYSTEM_BO_SIZE); + d2d = 1; + + if (*tmp_mem == NULL) { + if (kfd_create_kgd_mem(src_bo->dev, + MAX_SYSTEM_BO_SIZE, + si->p, + tmp_mem)) + return -EINVAL; + } + + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, + src_bo->mem, si->bo_offset, + *tmp_mem, 0, + size, f, &size)) + /* tmp_mem will be freed in caller.*/ + return -EINVAL; + + kfd_cma_fence_wait(*f); + dma_fence_put(*f); + + src_mem = *tmp_mem; + src_offset = 0; + } else if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) + dev = src_bo->dev; + /* else already set to dst_bo->dev */ + } + + if (err) { + pr_err("Failed to create system BO %d", err); + return -EINVAL; + } + + err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, + dst_mem, dst_offset, size, f, + copied); + /* The tmp_bo allocates additional memory. So it is better to wait and + * delete. Also since multiple GPUs are involved the copies are + * currently not pipelined. + */ + if (*tmp_mem && d2d) { + if (!err) { + kfd_cma_fence_wait(*f); + dma_fence_put(*f); + *f = NULL; + } + } + return err; +} + +/* Copy single range from source iterator @si to destination iterator @di. + * @si will move to next range and @di will move by bytes copied. + * @return : 0 for success or -ve for failure + * @f: The last fence if any + * @copied: out: number of bytes copied + */ +static int kfd_copy_single_range(struct cma_iter *si, struct cma_iter *di, + bool cma_write, struct dma_fence **f, + uint64_t *copied, struct kgd_mem **tmp_mem) +{ + int err = 0; + uint64_t copy_size, n; + uint64_t size = si->array->size; + struct kfd_bo *src_bo = si->cur_bo; + struct dma_fence *lfence = NULL; + + if (!src_bo || !di || !copied) + return -EINVAL; + *copied = 0; + if (f) + *f = NULL; + + while (size && !kfd_cma_iter_end(di)) { + struct dma_fence *fence = NULL; + + copy_size = min(size, (di->array->size - di->offset)); + + err = kfd_copy_bos(si, di, cma_write, copy_size, + &fence, &n, tmp_mem); + if (err) { + pr_err("CMA %d failed\n", err); + break; + } + + if (fence) { + err = kfd_fence_put_wait_if_diff_context(fence, + lfence); + lfence = fence; + if (err) + break; + } + + size -= n; + *copied += n; + err = kfd_cma_iter_advance(si, n); + if (err) + break; + err = kfd_cma_iter_advance(di, n); + if (err) + break; + } + + if (f) + *f = dma_fence_get(lfence); + dma_fence_put(lfence); + + return err; +} + +static int kfd_ioctl_cross_memory_copy(struct file *filep, + struct kfd_process *local_p, void *data) +{ + struct kfd_ioctl_cross_memory_copy_args *args = data; + struct kfd_memory_range *src_array, *dst_array; + struct kfd_process *remote_p; + struct task_struct *remote_task; + struct mm_struct *remote_mm; + struct pid *remote_pid; + struct dma_fence *lfence = NULL; + uint64_t copied = 0, total_copied = 0; + struct cma_iter di, si; + const char *cma_op; + int err = 0; + struct kgd_mem *tmp_mem = NULL; + + /* Check parameters */ + if (args->src_mem_range_array == 0 || args->dst_mem_range_array == 0 || + args->src_mem_array_size == 0 || args->dst_mem_array_size == 0) + return -EINVAL; + args->bytes_copied = 0; + + /* Allocate space for source and destination arrays */ + src_array = kmalloc_array((args->src_mem_array_size + + args->dst_mem_array_size), + sizeof(struct kfd_memory_range), + GFP_KERNEL); + if (!src_array) + return -ENOMEM; + dst_array = &src_array[args->src_mem_array_size]; + + if (copy_from_user(src_array, (void __user *)args->src_mem_range_array, + args->src_mem_array_size * + sizeof(struct kfd_memory_range))) { + err = -EFAULT; + goto copy_from_user_fail; + } + if (copy_from_user(dst_array, (void __user *)args->dst_mem_range_array, + args->dst_mem_array_size * + sizeof(struct kfd_memory_range))) { + err = -EFAULT; + goto copy_from_user_fail; + } + + /* Get remote process */ + remote_pid = find_get_pid(args->pid); + if (!remote_pid) { + pr_err("Cross mem copy failed. Invalid PID %d\n", args->pid); + err = -ESRCH; + goto copy_from_user_fail; + } + + remote_task = get_pid_task(remote_pid, PIDTYPE_PID); + if (!remote_pid) { + pr_err("Cross mem copy failed. Invalid PID or task died %d\n", + args->pid); + err = -ESRCH; + goto get_pid_task_fail; + } + + /* Check access permission */ + remote_mm = mm_access(remote_task, PTRACE_MODE_ATTACH_REALCREDS); + if (!remote_mm || IS_ERR(remote_mm)) { + err = IS_ERR(remote_mm) ? PTR_ERR(remote_mm) : -ESRCH; + if (err == -EACCES) { + pr_err("Cross mem copy failed. Permission error\n"); + err = -EPERM; + } else + pr_err("Cross mem copy failed. Invalid task %d\n", + err); + goto mm_access_fail; + } + + remote_p = kfd_get_process(remote_task); + if (IS_ERR(remote_p)) { + pr_err("Cross mem copy failed. Invalid kfd process %d\n", + args->pid); + err = -EINVAL; + goto kfd_process_fail; + } + /* Initialise cma_iter si & @di with source & destination range. */ + if (KFD_IS_CROSS_MEMORY_WRITE(args->flags)) { + cma_op = "WRITE"; + pr_debug("CMA WRITE: local -> remote\n"); + err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, + remote_p, remote_mm, remote_task, &di); + if (err) + goto kfd_process_fail; + err = kfd_cma_iter_init(src_array, args->src_mem_array_size, + local_p, current->mm, current, &si); + if (err) + goto kfd_process_fail; + } else { + cma_op = "READ"; + pr_debug("CMA READ: remote -> local\n"); + + err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, + local_p, current->mm, current, &di); + if (err) + goto kfd_process_fail; + err = kfd_cma_iter_init(src_array, args->src_mem_array_size, + remote_p, remote_mm, remote_task, &si); + if (err) + goto kfd_process_fail; + } + + /* Copy one si range at a time into di. After each call to + * kfd_copy_single_range() si will move to next range. di will be + * incremented by bytes copied + */ + while (!kfd_cma_iter_end(&si) && !kfd_cma_iter_end(&di)) { + struct dma_fence *fence = NULL; + + err = kfd_copy_single_range(&si, &di, + KFD_IS_CROSS_MEMORY_WRITE(args->flags), + &fence, &copied, &tmp_mem); + total_copied += copied; + + if (err) + break; + + /* Release old fence if a later fence is created. If no + * new fence is created, then keep the preivous fence + */ + if (fence) { + err = kfd_fence_put_wait_if_diff_context(fence, + lfence); + lfence = fence; + if (err) + break; + } + } + + /* Wait for the last fence irrespective of error condition */ + if (lfence) { + err = kfd_cma_fence_wait(lfence); + dma_fence_put(lfence); + if (err) + pr_err("CMA %s failed. BO timed out\n", cma_op); + } + + if (tmp_mem) + kfd_destroy_kgd_mem(tmp_mem); + + kfd_free_cma_bos(&si); + kfd_free_cma_bos(&di); + +kfd_process_fail: + mmput(remote_mm); +mm_access_fail: + put_task_struct(remote_task); +get_pid_task_fail: + put_pid(remote_pid); +copy_from_user_fail: + kfree(src_array); + + /* An error could happen after partial copy. In that case this will + * reflect partial amount of bytes copied + */ + args->bytes_copied = total_copied; + return err; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -3537,6 +4374,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY, + kfd_ioctl_cross_memory_copy, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 3b45fd2697d7c..7690289f76695 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -415,6 +415,38 @@ struct kfd_bo { unsigned int mem_type; }; +struct cma_system_bo { + struct kgd_mem *mem; + struct sg_table *sg; + struct kfd_dev *dev; + struct list_head list; +}; + +/* Similar to iov_iter */ +struct cma_iter { + /* points to current entry of range array */ + struct kfd_memory_range *array; + /* total number of entries in the initial array */ + unsigned long nr_segs; + /* total amount of data pointed by kfd array*/ + unsigned long total; + /* offset into the entry pointed by cma_iter.array */ + unsigned long offset; + struct kfd_process *p; + struct mm_struct *mm; + struct task_struct *task; + /* current kfd_bo associated with cma_iter.array.va_addr */ + struct kfd_bo *cur_bo; + /* offset w.r.t cur_bo */ + unsigned long bo_offset; + /* If cur_bo is a userptr BO, then a shadow system BO is created + * using its underlying pages. cma_bo holds this BO. cma_list is a + * list cma_bos created in one session + */ + struct cma_system_bo *cma_bo; + struct list_head cma_list; +}; + enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 7455ac0c6e616..c415adb179dc7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -743,7 +743,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, mem, NULL, + pdd->drm_priv, NULL, &mem, NULL, flags, false); if (err) goto err_alloc_mem; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index bf6e0832d7cdd..755512489136a 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -846,6 +846,37 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; +struct kfd_memory_range { + __u64 va_addr; + __u64 size; +}; + +/* flags definitions + * BIT0: 0: read operation, 1: write operation. + * This also identifies if the src or dst array belongs to remote process + */ +#define KFD_CROSS_MEMORY_RW_BIT (1 << 0) +#define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) +#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) +#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) + +struct kfd_ioctl_cross_memory_copy_args { + /* to KFD: Process ID of the remote process */ + __u32 pid; + /* to KFD: See above definition */ + __u32 flags; + /* to KFD: Source GPU VM range */ + __u64 src_mem_range_array; + /* to KFD: Size of above array */ + __u64 src_mem_array_size; + /* to KFD: Destination GPU VM range */ + __u64 dst_mem_range_array; + /* to KFD: Size of above array */ + __u64 dst_mem_array_size; + /* from KFD: Total amount of bytes copied */ + __u64 bytes_copied; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1795,7 +1826,11 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) +#define AMDKFD_IOC_CROSS_MEMORY_COPY \ + AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) + #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 + #endif From ff2bb7bef0dc27ae3de0ed0e2047bf432f35315d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 12 Jul 2022 16:30:02 +0800 Subject: [PATCH 0864/2070] drm/amdkcl: test for drm/display/drm_dp_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 6 ++++-- .../dkms/m4/drm-dp-cec-correlation-functions.m4 | 4 +++- .../dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 6 ++++-- .../m4/drm-dp-link-train-clock-recovery-delay.m4 | 4 +++- .../amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 6 ++++-- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/display/drm_dp_helper.h | 14 ++++++++++++++ include/kcl/kcl_drm_dp_cec.h | 4 +++- include/kcl/kcl_drm_dp_helper.h | 4 +++- 10 files changed, 48 insertions(+), 11 deletions(-) create mode 100644 include/kcl/header/drm/display/drm_dp_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 37194b7709bdd..1d4600cb8a0d4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -300,6 +300,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 @@ -331,7 +334,7 @@ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DP_DRM_DP_HELPER_H 1 +/* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index 49994828e0873..a20efecd2b022 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 552e94c063fb0..3ba925a8e076f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index e6713844783e2..5dc461c4db3df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index af98096981e77..4d0c1a7e21313 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index f49bd33a93a19..27b63066be2dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index db107edff41aa..b4a3e320a016d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -62,6 +62,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/header/drm/display/drm_dp_helper.h b/include/kcl/header/drm/display/drm_dp_helper.h new file mode 100644 index 0000000000000..83269a83e90ba --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include_next +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include_next +#else +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 62ee302a586be..8da102789f02e 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,7 +8,9 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 6168671062032..2d6d15d2bedb8 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,7 +30,9 @@ #include #include -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include From 8b38137631f20d93575ec9703bcc54311c0fdcab Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 12 Jul 2022 16:34:47 +0800 Subject: [PATCH 0865/2070] drm/amdkcl: test for drm/display/drm_dp_mst_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- .../amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 8 ++++++-- .../gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 12 +++++++----- .../dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 4 +++- .../amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 4 +++- .../drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 12 +++++++++--- .../amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 4 +++- .../drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 | 4 +++- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 8 ++++++-- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ .../drm-up-update-payload-part1-start-slot-arg.m4 | 4 +++- .../amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 +++- .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 4 +++- include/kcl/header/drm/display/drm_dp_mst_helper.h | 14 ++++++++++++++ 17 files changed, 82 insertions(+), 23 deletions(-) create mode 100644 include/kcl/header/drm/display/drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1d4600cb8a0d4..48f1b1608ecc3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -303,6 +303,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 @@ -337,7 +340,7 @@ /* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 +/* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 index 65b49ae69f164..10cfe8e436f12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -22,7 +24,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots dnl # AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index 8dc9ef9c8dd48..eabc0261dd0be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H - #include - #else - #include - #endif + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1f637c137dad1..42d7b5595403a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index df6b3450485e0..318f729096712 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 65d24257c4d25..806158f1562a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 913f4586acf6c..7c01c0479075e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 4c48b47b4c9bf..522d9e0e4b565 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 5540428fc8b49..683d563cfc7bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,7 +4,9 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -28,7 +30,9 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -48,7 +52,9 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 039132d5081d7..961c150fe148e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 3ab8397ab8481..16c25dc496d18 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 309cbc4f0f964..c0651dfe03701 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -15,7 +15,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -34,7 +36,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b4a3e320a016d..ccdc2e200d0a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -68,6 +68,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 0c25016be1da4..7839b7b00baee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index ca29f48cb467a..66d1beb0b8a34 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 2412859be272a..5623abd34416b 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,7 +22,9 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ -#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/include/kcl/header/drm/display/drm_dp_mst_helper.h b/include/kcl/header/drm/display/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..35221a4f00645 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include_next +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include_next +#else +#include_next +#endif + +#endif + From 4898e1561a8dead0b386b12d33ac1916508a3b12 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 13 Jul 2022 15:06:51 +0800 Subject: [PATCH 0866/2070] drm/amdkcl: test for drm_* headers moved into drm/display directory Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 15 +++++++++++++++ .../dkms/m4/drm-hdcp-update-content-protection.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/display/drm_dsc.h | 12 ++++++++++++ include/kcl/header/drm/display/drm_dsc_helper.h | 10 ++++++++++ include/kcl/header/drm/display/drm_hdcp.h | 11 +++++++++++ include/kcl/header/drm/display/drm_hdcp_helper.h | 10 ++++++++++ include/kcl/header/drm/display/drm_hdmi_helper.h | 10 ++++++++++ include/kcl/kcl_drm_hdcp.h | 2 +- 9 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/display/drm_dsc.h create mode 100644 include/kcl/header/drm/display/drm_dsc_helper.h create mode 100644 include/kcl/header/drm/display/drm_hdcp.h create mode 100644 include/kcl/header/drm/display/drm_hdcp_helper.h create mode 100644 include/kcl/header/drm/display/drm_hdmi_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 48f1b1608ecc3..61c3a0956df45 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -306,6 +306,21 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index 5b8c871002830..f91f55f90ced8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #include + #else #include + #endif ], [ drm_hdcp_update_content_protection(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ccdc2e200d0a0..17fb837a138c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -74,6 +74,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/header/drm/display/drm_dsc.h b/include/kcl/header/drm/display/drm_dsc.h new file mode 100644 index 0000000000000..7b4f143d14323 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dsc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_dsc_helper.h b/include/kcl/header/drm/display/drm_dsc_helper.h new file mode 100644 index 0000000000000..162730616ccb2 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dsc_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_hdcp.h b/include/kcl/header/drm/display/drm_hdcp.h new file mode 100644 index 0000000000000..a3c3aad2a794d --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdcp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/drm/display/drm_hdcp_helper.h b/include/kcl/header/drm/display/drm_hdcp_helper.h new file mode 100644 index 0000000000000..047decb7fc695 --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdcp_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_HDCP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_HDCP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_hdmi_helper.h b/include/kcl/header/drm/display/drm_hdmi_helper.h new file mode 100644 index 0000000000000..da7492d32e946 --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdmi_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_HDMI_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_HDMI_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index b3f6318e1f652..76c7823fe6f88 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -9,7 +9,7 @@ #define AMDKCL_DRM_HDCP_H #ifdef CONFIG_DRM_AMD_DC_HDCP -#include +#include #include /* changed in v4.16-rc7-1717-gb8e47d87be65 From d01b5fa3e8ba114183ad6de68e9ba0fd9a1d100c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 19 Jul 2022 18:12:49 +0800 Subject: [PATCH 0867/2070] drm/amdkcl: fix build error by adding missing arguments Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index da86d76624d0b..6fc290608baeb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -271,7 +271,7 @@ static int init_user_queue(struct process_queue_manager *pqm, &(*q)->gang_ctx_bo, &(*q)->gang_ctx_gpu_addr, &(*q)->gang_ctx_cpu_ptr, - false); + false, true); if (retval) { pr_err("failed to allocate gang context bo\n"); goto cleanup; From 0b193b0abf2cfd068d23c617d54361bdaa471a4b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:13:33 +0800 Subject: [PATCH 0868/2070] drm/amdkcl: wrap the code under HAVE_KTIME_IS_UNION for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c index b349bb3676d5f..e6bc424d5debd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c @@ -115,8 +115,13 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file) stats[TTM_PL_TT].drm.private) / 1024UL); for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { +#ifdef HAVE_KTIME_IS_UNION + if (!usage[hw_ip].tv64) + continue; +#else if (!usage[hw_ip]) continue; +#endif drm_printf(p, "drm-engine-%s:\t%lld ns\n", amdgpu_ip_name[hw_ip], ktime_to_ns(usage[hw_ip])); From e92e69c9d0c2e23d42846f0fd880868dfd14ff42 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:31:08 +0800 Subject: [PATCH 0869/2070] drm/amdkcl: fix compile error if DEFINE_DEBUGFS_ATTRIBUTE not defined Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 111b81acdc1c9..1a1348b6fd50c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4286,7 +4286,6 @@ DEFINE_SHOW_ATTRIBUTE(mst_topo); #ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); -#endif /* @@ -4321,6 +4320,7 @@ static int skip_detection_link_training_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, skip_detection_link_training_get, skip_detection_link_training_set, "%llu\n"); +#endif /* * Dumps the DCC_EN bit for each pipe. From 7ccf0a49b6df17da5a179cc7f8bb1f10ddf542fd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:46:50 +0800 Subject: [PATCH 0870/2070] drm/amdkcl: include linux/debugfs.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index ea623aa273321..666907102cbb4 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include From b687348883ef9c8857fd0d0f2f5b7dcbd2959ae0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 15:11:01 +0800 Subject: [PATCH 0871/2070] drm/amdkcl: adjust vblank_lock position of struct amdgpu_display_manager Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 5998b6f055f10..f37529b88f778 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -511,6 +511,13 @@ struct amdgpu_display_manager { */ bool audio_registered; + /** + * @vblank_lock: + * + * Guards access to deferred vblank work state. + */ + spinlock_t vblank_lock; + /** * @irq_handler_list_low_tab: * From a18d2d828cb31527cdbb5ad8dd488fdbf0acf3ee Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 13 Jul 2022 16:09:52 +0800 Subject: [PATCH 0872/2070] drm/amdkcl: fake dma_resv api using legacy structure Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 841 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 7 +- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 20 + drivers/gpu/drm/amd/dkms/pre-build.sh | 8 +- include/kcl/kcl_dma-resv.h | 151 ++++ 5 files changed, 1024 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c new file mode 100644 index 0000000000000..e3525a0973f71 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include +#include +#include +#include +#include +#include + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + +/** + * DOC: Reservation Object Overview + * + * The reservation object provides a mechanism to manage a container of + * dma_fence object associated with a resource. A reservation object + * can have any number of fences attaches to it. Each fence carries an usage + * parameter determining how the operation represented by the fence is using the + * resource. The RCU mechanism is used to protect read access to fences from + * locked write-side updates. + * + * See struct dma_resv for more details. + */ + +extern struct ww_class reservation_ww_class; + +/** + * dma_resv_list_alloc - allocate fence list + * @shared_max: number of fences we need space for + * + * Allocate a new dma_resv_list and make sure to correctly initialize + * shared_max. + */ +static struct dma_resv_list *dma_resv_list_alloc(unsigned int shared_max) +{ + struct dma_resv_list *list; + + list = kmalloc(struct_size(list, shared, shared_max), GFP_KERNEL); + if (!list) + return NULL; + + list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) / + sizeof(*list->shared); + + return list; +} + +/** + * dma_resv_list_free - free fence list + * @list: list to free + * + * Free a dma_resv_list and make sure to drop all references. + */ +static void dma_resv_list_free(struct dma_resv_list *list) +{ + unsigned int i; + + if (!list) + return; + + for (i = 0; i < list->shared_count; ++i) + dma_fence_put(rcu_dereference_protected(list->shared[i], true)); + + kfree_rcu(list, rcu); +} + +/** + * dma_resv_init - initialize a reservation object + * @obj: the reservation object + */ +void dma_resv_init(struct dma_resv *obj) +{ + ww_mutex_init(&obj->lock, &reservation_ww_class); + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + + RCU_INIT_POINTER(obj->fence, NULL); + RCU_INIT_POINTER(obj->fence_excl, NULL); +} +EXPORT_SYMBOL(dma_resv_init); + +/** + * dma_resv_fini - destroys a reservation object + * @obj: the reservation object + */ +void dma_resv_fini(struct dma_resv *obj) +{ + struct dma_resv_list *fobj; + struct dma_fence *excl; + + /* + * This object should be dead and all references must have + * been released to it, so no need to be protected with rcu. + */ + excl = rcu_dereference_protected(obj->fence_excl, 1); + if (excl) + dma_fence_put(excl); + + fobj = rcu_dereference_protected(obj->fence, 1); + dma_resv_list_free(fobj); + ww_mutex_destroy(&obj->lock); +} +EXPORT_SYMBOL(dma_resv_fini); + +/** + * dma_resv_reserve_fences - Reserve space to add shared fences to + * a dma_resv. + * @obj: reservation object + * @num_fences: number of fences we want to add + * + * Should be called before dma_resv_add_shared_fence(). Must + * be called with @obj locked through dma_resv_lock(). + * + * Note that the preallocated slots need to be re-reserved if @obj is unlocked + * at any time before calling dma_resv_add_shared_fence(). This is validated + * when CONFIG_DEBUG_MUTEXES is enabled. + * + * RETURNS + * Zero for success, or -errno + */ +int dma_resv_reserve_fences(struct dma_resv *obj, unsigned int num_fences) +{ + struct dma_resv_list *old, *new; + unsigned int i, j, k, max; + + dma_resv_assert_held(obj); + + old = dma_resv_shared_list(obj); + if (old && old->shared_max) { + if ((old->shared_count + num_fences) <= old->shared_max) + return 0; + max = max(old->shared_count + num_fences, old->shared_max * 2); + } else { + max = max(4ul, roundup_pow_of_two(num_fences)); + } + + new = dma_resv_list_alloc(max); + if (!new) + return -ENOMEM; + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = max; i < (old ? old->shared_count : 0); ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + if (dma_fence_is_signaled(fence)) + RCU_INIT_POINTER(new->shared[--k], fence); + else + RCU_INIT_POINTER(new->shared[j++], fence); + } + new->shared_count = j; + + /* + * We are not changing the effective set of fences here so can + * merely update the pointer to the new array; both existing + * readers and new readers will see exactly the same set of + * active (unsignaled) shared fences. Individual fences and the + * old array are protected by RCU and so will not vanish under + * the gaze of the rcu_read_lock() readers. + */ + rcu_assign_pointer(obj->fence, new); + + if (!old) + return 0; + + /* Drop the references to the signaled fences */ + for (i = k; i < max; ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(new->shared[i], + dma_resv_held(obj)); + dma_fence_put(fence); + } + kfree_rcu(old, rcu); + + return 0; +} +EXPORT_SYMBOL(dma_resv_reserve_fences); + +#ifdef CONFIG_DEBUG_MUTEXES +/** + * dma_resv_reset_max_fences - reset shared fences for debugging + * @obj: the dma_resv object to reset + * + * Reset the number of pre-reserved shared slots to test that drivers do + * correct slot allocation using dma_resv_reserve_fences(). See also + * &dma_resv_list.shared_max. + */ +void dma_resv_reset_max_fences(struct dma_resv *obj) +{ + struct dma_resv_list *fences = dma_resv_shared_list(obj); + + dma_resv_assert_held(obj); + + /* Test shared fence slot reservation */ + if (fences) + fences->shared_max = fences->shared_count; +} +EXPORT_SYMBOL(dma_resv_reset_max_fences); +#endif + +/** + * dma_resv_add_shared_fence - Add a fence to a shared slot + * @obj: the reservation object + * @fence: the shared fence to add + * + * Add a fence to a shared slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +static void dma_resv_add_shared_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_resv_list *fobj; + struct dma_fence *old; + unsigned int i, count; + + dma_fence_get(fence); + + dma_resv_assert_held(obj); + + /* Drivers should not add containers here, instead add each fence + * individually. + */ + WARN_ON(dma_fence_is_container(fence)); + + fobj = dma_resv_shared_list(obj); + count = fobj->shared_count; + + write_seqcount_begin(&obj->seq); + + for (i = 0; i < count; ++i) { + + old = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + if (old->context == fence->context || + dma_fence_is_signaled(old)) + goto replace; + } + + BUG_ON(fobj->shared_count >= fobj->shared_max); + old = NULL; + count++; + +replace: + RCU_INIT_POINTER(fobj->shared[i], fence); + /* pointer update must be visible before we extend the shared_count */ + smp_store_mb(fobj->shared_count, count); + + write_seqcount_end(&obj->seq); + dma_fence_put(old); +} + +/** + * dma_resv_replace_fences - replace fences in the dma_resv obj + * @obj: the reservation object + * @context: the context of the fences to replace + * @replacement: the new fence to use instead + * @usage: how the new fence is used, see enum dma_resv_usage + * + * Replace fences with a specified context with a new fence. Only valid if the + * operation represented by the original fence has no longer access to the + * resources represented by the dma_resv object when the new fence completes. + * + * And example for using this is replacing a preemption fence with a page table + * update fence which makes the resource inaccessible. + */ +void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, + struct dma_fence *replacement, + enum dma_resv_usage usage) +{ + struct dma_resv_list *list; + struct dma_fence *old; + unsigned int i; + + /* Only readers supported for now */ + WARN_ON(usage != DMA_RESV_USAGE_READ); + + dma_resv_assert_held(obj); + + write_seqcount_begin(&obj->seq); + + old = dma_resv_excl_fence(obj); + if (old->context == context) { + RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); + dma_fence_put(old); + } + + list = dma_resv_shared_list(obj); + for (i = 0; list && i < list->shared_count; ++i) { + old = rcu_dereference_protected(list->shared[i], + dma_resv_held(obj)); + if (old->context != context) + continue; + + rcu_assign_pointer(list->shared[i], dma_fence_get(replacement)); + dma_fence_put(old); + } + + write_seqcount_end(&obj->seq); +} +EXPORT_SYMBOL(dma_resv_replace_fences); + +/** + * dma_resv_add_excl_fence - Add an exclusive fence. + * @obj: the reservation object + * @fence: the exclusive fence to add + * + * Add a fence to the exclusive slot. @obj must be locked with dma_resv_lock(). + * See also &dma_resv.fence_excl for a discussion of the semantics. + */ +static void dma_resv_add_excl_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_fence *old_fence = dma_resv_excl_fence(obj); + + dma_resv_assert_held(obj); + + dma_fence_get(fence); + + write_seqcount_begin(&obj->seq); + /* write_seqcount_begin provides the necessary memory barrier */ + RCU_INIT_POINTER(obj->fence_excl, fence); + write_seqcount_end(&obj->seq); + + dma_fence_put(old_fence); +} + +/** + * dma_resv_add_fence - Add a fence to the dma_resv obj + * @obj: the reservation object + * @fence: the fence to add + * @usage: how the fence is used, see enum dma_resv_usage + * + * Add a fence to a slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, + enum dma_resv_usage usage) +{ + if (usage == DMA_RESV_USAGE_WRITE) + dma_resv_add_excl_fence(obj, fence); + else + dma_resv_add_shared_fence(obj, fence); +} +EXPORT_SYMBOL(dma_resv_add_fence); + +/* Restart the iterator by initializing all the necessary fields, but not the + * relation to the dma_resv object. */ +static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) +{ + cursor->seq = read_seqcount_begin(&cursor->obj->seq); + cursor->index = -1; + cursor->shared_count = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) { + cursor->fences = dma_resv_shared_list(cursor->obj); + if (cursor->fences) + cursor->shared_count = cursor->fences->shared_count; + } else { + cursor->fences = NULL; + } + cursor->is_restarted = true; +} + +/* Walk to the next not signaled fence and grab a reference to it */ +static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) +{ + struct dma_resv *obj = cursor->obj; + + do { + /* Drop the reference from the previous round */ + dma_fence_put(cursor->fence); + + if (cursor->index == -1) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + + } else if (!cursor->fences || + cursor->index >= cursor->shared_count) { + cursor->fence = NULL; + break; + + } else { + struct dma_resv_list *fences = cursor->fences; + unsigned int idx = cursor->index++; + + cursor->fence = rcu_dereference(fences->shared[idx]); + } + cursor->fence = dma_fence_get_rcu(cursor->fence); + if (!cursor->fence || !dma_fence_is_signaled(cursor->fence)) + break; + } while (true); +} + +/** + * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_first() whenver possible. + * + * Returns the first fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) +{ + rcu_read_lock(); + do { + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_first_unlocked); + +/** + * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_next() whenver possible. + * + * Returns the next fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) +{ + bool restart; + + rcu_read_lock(); + cursor->is_restarted = false; + restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); + do { + if (restart) + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + restart = true; + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_next_unlocked); + +/** + * dma_resv_iter_first - first fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Return the first fence in the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) +{ + struct dma_fence *fence; + + dma_resv_assert_held(cursor->obj); + + cursor->index = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) + cursor->fences = dma_resv_shared_list(cursor->obj); + else + cursor->fences = NULL; + + fence = dma_resv_excl_fence(cursor->obj); + if (!fence) + fence = dma_resv_iter_next(cursor); + + cursor->is_restarted = true; + return fence; +} +EXPORT_SYMBOL_GPL(dma_resv_iter_first); + +/** + * dma_resv_iter_next - next fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Return the next fences from the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) +{ + unsigned int idx; + + dma_resv_assert_held(cursor->obj); + + cursor->is_restarted = false; + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) + return NULL; + + idx = cursor->index++; + return rcu_dereference_protected(cursor->fences->shared[idx], + dma_resv_held(cursor->obj)); +} +EXPORT_SYMBOL_GPL(dma_resv_iter_next); + +/** + * dma_resv_copy_fences - Copy all fences from src to dst. + * @dst: the destination reservation object + * @src: the source reservation object + * + * Copy all fences from src to dst. dst-lock must be held. + */ +int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + struct dma_resv_iter cursor; + struct dma_resv_list *list; + struct dma_fence *f, *excl; + + dma_resv_assert_held(dst); + + list = NULL; + excl = NULL; + + dma_resv_iter_begin(&cursor, src, DMA_RESV_USAGE_READ); + dma_resv_for_each_fence_unlocked(&cursor, f) { + + if (dma_resv_iter_is_restarted(&cursor)) { + dma_resv_list_free(list); + dma_fence_put(excl); + + if (cursor.shared_count) { + list = dma_resv_list_alloc(cursor.shared_count); + if (!list) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + + list->shared_count = 0; + + } else { + list = NULL; + } + excl = NULL; + } + + dma_fence_get(f); + if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE) + excl = f; + else + RCU_INIT_POINTER(list->shared[list->shared_count++], f); + } + dma_resv_iter_end(&cursor); + + write_seqcount_begin(&dst->seq); + excl = rcu_replace_pointer(dst->fence_excl, excl, dma_resv_held(dst)); + list = rcu_replace_pointer(dst->fence, list, dma_resv_held(dst)); + write_seqcount_end(&dst->seq); + + dma_resv_list_free(list); + dma_fence_put(excl); + + return 0; +} +EXPORT_SYMBOL(dma_resv_copy_fences); + +/** + * dma_resv_get_fences - Get an object's shared and exclusive + * fences without update side lock held + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @num_fences: the number of fences returned + * @fences: the array of fence ptrs returned (array is krealloc'd to the + * required size, and must be freed by caller) + * + * Retrieve all fences from the reservation object. + * Returns either zero or -ENOMEM. + */ +int dma_resv_get_fences(struct dma_resv *obj, enum dma_resv_usage usage, + unsigned int *num_fences, struct dma_fence ***fences) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + *num_fences = 0; + *fences = NULL; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + if (dma_resv_iter_is_restarted(&cursor)) { + unsigned int count; + + while (*num_fences) + dma_fence_put((*fences)[--(*num_fences)]); + + count = cursor.shared_count + 1; + + /* Eventually re-allocate the array */ + *fences = krealloc_array(*fences, count, + sizeof(void *), + GFP_KERNEL); + if (count && !*fences) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + } + + (*fences)[(*num_fences)++] = dma_fence_get(fence); + } + dma_resv_iter_end(&cursor); + + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_fences); + +/** + * dma_resv_get_singleton - Get a single fence for all the fences + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @fence: the resulting fence + * + * Get a single fence representing all the fences inside the resv object. + * Returns either 0 for success or -ENOMEM. + * + * Warning: This can't be used like this when adding the fence back to the resv + * object since that can lead to stack corruption when finalizing the + * dma_fence_array. + * + * Returns 0 on success and negative error values on failure. + */ +int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, + struct dma_fence **fence) +{ + struct dma_fence_array *array; + struct dma_fence **fences; + unsigned count; + int r; + + r = dma_resv_get_fences(obj, usage, &count, &fences); + if (r) + return r; + + if (count == 0) { + *fence = NULL; + return 0; + } + + if (count == 1) { + *fence = fences[0]; + kfree(fences); + return 0; + } + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), + 1, false); + if (!array) { + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; + } + + *fence = &array->base; + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_singleton); + +/** + * dma_resv_wait_timeout - Wait on reservation's objects + * shared and/or exclusive fences. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @intr: if true, do interruptible wait + * @timeout: timeout value in jiffies or zero to return immediately + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already + * RETURNS + * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or + * greater than zer on success. + */ +long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage, + bool intr, unsigned long timeout) +{ + long ret = timeout ? timeout : 1; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + ret = dma_fence_wait_timeout(fence, intr, ret); + if (ret <= 0) { + dma_resv_iter_end(&cursor); + return ret; + } + } + dma_resv_iter_end(&cursor); + + return ret; +} +EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); + +/** + * dma_resv_test_signaled - Test if a reservation object's fences have been + * signaled. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already. + * + * RETURNS + * + * True if all fences signaled, else false. + */ +bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + dma_resv_iter_end(&cursor); + return false; + } + dma_resv_iter_end(&cursor); + return true; +} +EXPORT_SYMBOL_GPL(dma_resv_test_signaled); + +/** + * dma_resv_describe - Dump description of the resv object into seq_file + * @obj: the reservation object + * @seq: the seq_file to dump the description into + * + * Dump a textual description of the fences inside an dma_resv object into the + * seq_file. + */ +void dma_resv_describe(struct dma_resv *obj, struct seq_file *seq) +{ + static const char *usage[] = { "write", "read" }; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_for_each_fence(&cursor, obj, DMA_RESV_USAGE_READ, fence) { + seq_printf(seq, "\t%s fence:", + usage[dma_resv_iter_usage(&cursor)]); + dma_fence_describe(fence, seq); + } +} +EXPORT_SYMBOL_GPL(dma_resv_describe); + +#if IS_ENABLED(CONFIG_LOCKDEP) +static int __init dma_resv_lockdep(void) +{ + struct mm_struct *mm = mm_alloc(); + struct ww_acquire_ctx ctx; + struct dma_resv obj; + struct address_space mapping; + int ret; + + if (!mm) + return -ENOMEM; + + dma_resv_init(&obj); + address_space_init_once(&mapping); + + mmap_read_lock(mm); + ww_acquire_init(&ctx, &reservation_ww_class); + ret = dma_resv_lock(&obj, &ctx); + if (ret == -EDEADLK) + dma_resv_lock_slow(&obj, &ctx); + fs_reclaim_acquire(GFP_KERNEL); + /* for unmap_mapping_range on trylocked buffer objects in shrinkers */ + i_mmap_lock_write(&mapping); + i_mmap_unlock_write(&mapping); +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#else + __dma_fence_might_wait(); +#endif + fs_reclaim_release(GFP_KERNEL); + ww_mutex_unlock(&obj.lock); + ww_acquire_fini(&ctx); + mmap_read_unlock(mm); + + mmput(mm); + + return 0; +} +subsys_initcall(dma_resv_lockdep); +#endif + + + + +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 61c3a0956df45..a017b4a391307 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -115,11 +115,14 @@ /* dma_map_sgtable() is enabled */ #define HAVE_DMA_MAP_SGTABLE 1 +/* dma_resv->fences is available */ +#define HAVE_DMA_RESV_FENCES 1 + /* dma_resv->seq is available */ -#define HAVE_DMA_RESV_SEQ 1 +/* #undef HAVE_DMA_RESV_SEQ */ /* dma_resv->seq is seqcount_ww_mutex_t */ -#define HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T 1 +/* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 1ede56611c58d..9d11fb99c397a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -41,6 +41,25 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ ]) ]) +dnl # +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_resv *resv = NULL; + resv->fences = NULL; + ], [ + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1, + [dma_resv->fences is available]) + ]) + ]) +]) + + dnl # dnl # v4.19-rc6-1514-g27836b641c1b dnl # dma-buf: remove shared fence staging in reservation object @@ -63,5 +82,6 @@ AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_SEQ + AC_AMDGPU_DMA_RESV_FENCES AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7d481851f944d..81a0d5da5c8bd 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -41,7 +41,9 @@ done sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h + -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h \ + -e '/struct dma_resv_iter {/, /}/d' $INC/linux/dma-resv.h \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h # add amd prefix to exported symbols for file in $FILES; do @@ -71,3 +73,7 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file done fi + +if ! grep -q 'define HAVE_DMA_RESV_FENCES' $SRC/config/config.h; then + sed -i 's|dma-buf/dma-resv.o|kcl_dma-resv.o|' amd/amdkcl/Makefile +fi diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 0c4850cd6bf95..39a4e3b5e67f1 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -54,6 +54,125 @@ struct dma_resv_list; +enum dma_resv_usage { + /** + * @DMA_RESV_USAGE_KERNEL: For in kernel memory management only. + * + * This should only be used for things like copying or clearing memory + * with a DMA hardware engine for the purpose of kernel memory + * management. + * + * Drivers *always* must wait for those fences before accessing the + * resource protected by the dma_resv object. The only exception for + * that is when the resource is known to be locked down in place by + * pinning it previously. + */ + DMA_RESV_USAGE_KERNEL, + + /** + * @DMA_RESV_USAGE_WRITE: Implicit write synchronization. + * + * This should only be used for userspace command submissions which add + * an implicit write dependency. + */ + DMA_RESV_USAGE_WRITE, + + /** + * @DMA_RESV_USAGE_READ: Implicit read synchronization. + * + * This should only be used for userspace command submissions which add + * an implicit read dependency. + */ + DMA_RESV_USAGE_READ, + + /** + * @DMA_RESV_USAGE_BOOKKEEP: No implicit sync. + * + * This should be used by submissions which don't want to participate in + * implicit synchronization. + * + * The most common case are preemption fences as well as page table + * updates and their TLB flushes. + */ + DMA_RESV_USAGE_BOOKKEEP +}; + +#if defined(HAVE_DMA_RESV_FENCES) +struct dma_resv { + struct ww_mutex lock; + struct dma_resv_list __rcu *fences; +}; + +struct dma_resv_iter { + /** @obj: The dma_resv object we iterate over */ + struct dma_resv *obj; + + /** @usage: Return fences with this usage or lower. */ + enum dma_resv_usage usage; + + /** @fence: the currently handled fence */ + struct dma_fence *fence; + + /** @fence_usage: the usage of the current fence */ + enum dma_resv_usage fence_usage; + + /** @index: index into the shared fences */ + unsigned int index; + + /** @fences: the shared fences; private, *MUST* not dereference */ + struct dma_resv_list *fences; + + /** @num_fences: number of fences */ + unsigned int num_fences; + + /** @is_restarted: true if this is the first returned fence */ + bool is_restarted; +}; + +#else + +/** + * struct dma_resv_list - a list of shared fences + * @rcu: for internal use + * @shared_count: table of shared fences + * @shared_max: for growing shared fence table + * @shared: shared fence table + */ +struct dma_resv_list { + struct rcu_head rcu; + u32 shared_count, shared_max; + struct dma_fence __rcu *shared[]; +}; + +struct dma_resv_iter { + /** @obj: The dma_resv object we iterate over */ + struct dma_resv *obj; + + /** @usage: Return fences with this usage or lower. */ + enum dma_resv_usage usage; + + /** @fence: the currently handled fence */ + struct dma_fence *fence; + + /** @fence_usage: the usage of the current fence */ + enum dma_resv_usage fence_usage; + + /** @seq: sequence number to check for modifications */ + unsigned int seq; + + /** @index: index into the shared fences */ + unsigned int index; + + /** @fences: the shared fences; private, *MUST* not dereference */ + struct dma_resv_list *fences; + + /** @shared_count: number of shared fences */ + unsigned int shared_count; + + /** @is_restarted: true if this is the first returned fence */ + bool is_restarted; +}; + #if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) struct dma_resv { struct ww_mutex lock; @@ -81,6 +200,38 @@ struct dma_resv { }; #endif +/** + * dma_resv_excl_fence - return the object's exclusive fence + * @obj: the reservation object + * + * Returns the exclusive fence (if any). Caller must either hold the objects + * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(), + * or one of the variants of each + * + * RETURNS + * The exclusive fence or NULL + */ +static inline struct dma_fence * +dma_resv_excl_fence(struct dma_resv *obj) +{ + return rcu_dereference_check(obj->fence_excl, lockdep_is_held(&(obj)->lock.base)); +} + +/** + * dma_resv_shared_list - get the reservation object's shared fence list + * @obj: the reservation object + * + * Returns the shared fence list. Caller must either hold the objects + * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(), + * or one of the variants of each + */ +static inline struct dma_resv_list *dma_resv_shared_list(struct dma_resv *obj) +{ + return rcu_dereference_check(obj->fence, lockdep_is_held(&(obj)->lock.base)); +} + +#endif /* !defined(HAVE_DMA_RESV_FENCES) */ + #if !defined(smp_store_mb) #define smp_store_mb set_mb #endif From fbf459f2404b310784607934b8d458299042ac7d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 10:30:52 +0800 Subject: [PATCH 0873/2070] drm/amdkcl: replace dma_resv_add_excl_fence with dma_resv_add_fence Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index ad6c11800333c..85f34e7b3d7e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -104,14 +104,14 @@ __dma_resv_make_exclusive(struct dma_resv *obj) if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ return 0; - r = dma_resv_get_fences(obj, NULL, &count, &fences); + r = dma_resv_get_fences(obj, DMA_RESV_USAGE_READ, &count, &fences); if (r) return r; if (count == 0) { /* Now that was unexpected. */ } else if (count == 1) { - dma_resv_add_excl_fence(obj, fences[0]); + dma_resv_add_fence(obj, fences[0], DMA_RESV_USAGE_WRITE); dma_fence_put(fences[0]); kfree(fences); } else { @@ -123,7 +123,7 @@ __dma_resv_make_exclusive(struct dma_resv *obj) if (!array) goto err_fences_put; - dma_resv_add_excl_fence(obj, &array->base); + dma_resv_add_fence(obj, &array->base, DMA_RESV_USAGE_WRITE); dma_fence_put(&array->base); } From c4563652a0ff3e990baf5b2d608cab33aaebc9c8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 12:58:52 +0800 Subject: [PATCH 0874/2070] drm/amdkcl: use DMA_RESV_USAGE_KERNEL as DMA_REV_USAGE_WRITE for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index e3525a0973f71..5cd7528f0c2a7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -380,7 +380,7 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, enum dma_resv_usage usage) { - if (usage == DMA_RESV_USAGE_WRITE) + if (usage == DMA_RESV_USAGE_WRITE || usage == DMA_RESV_USAGE_KERNEL) dma_resv_add_excl_fence(obj, fence); else dma_resv_add_shared_fence(obj, fence); From 50a6e27f25f12891356d999ea012a7eaa981bf6b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 13:00:56 +0800 Subject: [PATCH 0875/2070] drm/amdkcl: fix NULL pointer check Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 5cd7528f0c2a7..db40a6e5f035a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -321,7 +321,7 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, write_seqcount_begin(&obj->seq); old = dma_resv_excl_fence(obj); - if (old->context == context) { + if (old && old->context == context) { RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); dma_fence_put(old); } From 668f1047f6629580596f2bb449156447821e3d83 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 22:33:58 +0800 Subject: [PATCH 0876/2070] drm/amdkcl: remove useless header Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ic20beeebc180c41f7b6f0a7510c3f03aa4370985 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c63f0d8eeadc..98de078a36a18 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -96,9 +96,6 @@ #include #include #include -#ifdef CONFIG_DRM_AMD_DC_HDCP -#include -#endif #include #include From 34c1490b68ade5814f6943930b5c299116277798 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 25 Jul 2022 10:21:47 +0800 Subject: [PATCH 0877/2070] drm/amdkcl: drop DRM_AMD_DC_DCN{1_0/2_x/3_x} Signed-off-by: Leslie Shi Change-Id: I6e3f9d20a8573901fabcc13538abc988936d803e Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index e7b791c8195f0..1fc960e3cae03 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -149,9 +149,6 @@ export CONFIG_DRM_AMDGPU_CIK=y export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y -ifndef CONFIG_ARM64 -export CONFIG_DRM_AMD_DC_DCN1_0=y -endif subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL @@ -159,9 +156,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC -ifndef CONFIG_ARM64 -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -endif ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE @@ -179,10 +173,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_DCN2_x=y -export CONFIG_DRM_AMD_DC_DCN3_x=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x +export CONFIG_DRM_AMD_DC_DCN=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN endif endif From 8498546c3ae933f3a38cb96590d7d600a22e164e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 27 Jul 2022 18:56:58 +0800 Subject: [PATCH 0878/2070] drm/amdkcl: Test if drm_private_obj is defined Test if drm_private_obj is defined in struct drm_dp_mst_topology_mrg Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: I9daeac36f316b5183cd732aa13a7283be43ea097 --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 26 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1a1348b6fd50c..84ade928ad7c4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -2837,6 +2837,7 @@ static int target_backlight_show(struct seq_file *m, void *unused) * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector * */ +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static int dp_is_mst_connector_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -2873,6 +2874,7 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) return 0; } +#endif /* * function description: Read out the mst progress status @@ -3001,7 +3003,9 @@ DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); DEFINE_SHOW_ATTRIBUTE(replay_capability); DEFINE_SHOW_ATTRIBUTE(psr_capability); +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); +#endif DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); @@ -3136,7 +3140,9 @@ static const struct { {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"is_mst_connector", &dp_is_mst_connector_fops}, +#endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a017b4a391307..d6fa56b319d54 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -393,6 +393,9 @@ /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ +/* struct drm_dp_mst_topology_mgr.base is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 + /* drm_dp_mst_topology_mgr_init() wants drm_device arg */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 new file mode 100644 index 0000000000000..06cdbe40de8cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # commit v4.14-rc1-a4370c7774 +dnl # drm/atomic: Make private objs proper objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + #include + ], [ + struct drm_dp_mst_topology_mgr *mst_mgr = 0; + int i = 0; + if ((&mst_mgr->base) && (&mst_mgr->base.lock)) + i++; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE, 1, + [struct drm_dp_mst_topology_mgr.base is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b1b8aca5a67bd..2eed887481ca4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -161,6 +161,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STR_YES_NO AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From b180812fa05381858fef008ddfe706b688db6ce1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 29 Jul 2022 13:54:21 +0800 Subject: [PATCH 0879/2070] drm/amdkcl: refactor kcl implementation for drm/display header change Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_drm_dp_mst_helper_backport.h | 6 ------ include/kcl/header/drm/display/drm_dp_helper.h | 4 ++-- include/kcl/header/drm/display/drm_dp_mst_helper.h | 4 ++-- include/kcl/header/drm/dp/drm_dp_helper.h | 9 --------- include/kcl/header/drm/dp/drm_dp_mst_helper.h | 9 --------- include/kcl/kcl_drm_dp_cec.h | 6 ------ include/kcl/kcl_drm_dp_helper.h | 6 ------ 7 files changed, 4 insertions(+), 40 deletions(-) delete mode 100644 include/kcl/header/drm/dp/drm_dp_helper.h delete mode 100644 include/kcl/header/drm/dp/drm_dp_mst_helper.h diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 5623abd34416b..9be8ef18696a1 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,13 +22,7 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ -#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) -#include -#else -#include -#endif /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ #if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) diff --git a/include/kcl/header/drm/display/drm_dp_helper.h b/include/kcl/header/drm/display/drm_dp_helper.h index 83269a83e90ba..3435bd45d5669 100644 --- a/include/kcl/header/drm/display/drm_dp_helper.h +++ b/include/kcl/header/drm/display/drm_dp_helper.h @@ -5,9 +5,9 @@ #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include_next #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include_next +#include #else -#include_next +#include #endif #endif diff --git a/include/kcl/header/drm/display/drm_dp_mst_helper.h b/include/kcl/header/drm/display/drm_dp_mst_helper.h index 35221a4f00645..c667873640a00 100644 --- a/include/kcl/header/drm/display/drm_dp_mst_helper.h +++ b/include/kcl/header/drm/display/drm_dp_mst_helper.h @@ -5,9 +5,9 @@ #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include_next #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) -#include_next +#include #else -#include_next +#include #endif #endif diff --git a/include/kcl/header/drm/dp/drm_dp_helper.h b/include/kcl/header/drm/dp/drm_dp_helper.h deleted file mode 100644 index 9aac78ed61294..0000000000000 --- a/include/kcl/header/drm/dp/drm_dp_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ -#define _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ - -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H -#include_next -#endif - -#endif diff --git a/include/kcl/header/drm/dp/drm_dp_mst_helper.h b/include/kcl/header/drm/dp/drm_dp_mst_helper.h deleted file mode 100644 index 116be51b87c2c..0000000000000 --- a/include/kcl/header/drm/dp/drm_dp_mst_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ -#define _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ - -#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H -#include_next -#endif - -#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 8da102789f02e..a50c290cc7248 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,13 +8,7 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include -#else -#include -#endif /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 2d6d15d2bedb8..43ddfa2ed899d 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,13 +30,7 @@ #include #include -#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include -#else -#include -#endif #include /* From 5b1e9b474a90951bdca80625cc38ee735cbc8767 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 3 Aug 2022 10:29:12 +0800 Subject: [PATCH 0880/2070] drm/amdkcl: enable CONFIG_HSA_AMD_P2P Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 1fc960e3cae03..a00c632cc588f 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -167,6 +167,11 @@ endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +ifeq ($(call _is_kcl_macro_defined,HAVE_LINUX_PCI_P2PDMA_H),y) +export CONFIG_HSA_AMD_P2P=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P +endif + # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 From 3e482bef7e6da63db24664b32f17d7285d2138e6 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 13 Jul 2022 09:54:49 -0400 Subject: [PATCH 0881/2070] drm/amdkcl: test for available memory Do not kick off new background compiling processes if amount of available system memory less than 20%. It prevents from killing the driver installation on the systems with small amount of memory. SWDEV-336154 Change-Id: Idaf71093526ce2a4a734c5c168a239c927d543b3 Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2eed887481ca4..6831bfd78ece6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -548,6 +548,22 @@ AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) ]) +dnl # +dnl # AC_KERNEL_FREE_MEM +dnl # return true if available memory >20% +dnl # +AC_DEFUN([AC_KERNEL_FREE_MEM], [ + free_mem=$(free -t | awk '/^Total:/ { + printf("%d\n", $[4] / $[2] * 100) + }') + + AS_IF([[[ $free_mem -gt 20 ]]], [ + $1 + ], [ + $2 + ]) +]) + dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed @@ -556,6 +572,17 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ do_background() { AC_KERNEL_TMP_BUILD_DIR([$1]) } + + while : + do + AC_KERNEL_FREE_MEM([rc=0], [rc=1]) + if test $rc -ne 0; then : + sleep 1 + else : + break + fi + done + do_background & procs="$! $procs" ]) From f38f79270f0d735e890f23f803ddf94c283cb612 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 10 Aug 2022 11:47:47 +0800 Subject: [PATCH 0882/2070] Revert "drm/amdkfd: Add CMA API" This reverts commit 4397c7e24bdd5a65ab131266c1acbe6078235e74. CMA is not supported anymore. So revert this patch Signed-off-by: Ma Jun Change-Id: I341df8470a1666cdd37e1c167dad139aafb4dc08 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 86 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 842 +----------------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 32 - drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- include/uapi/linux/kfd_ioctl.h | 35 - 6 files changed, 5 insertions(+), 999 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 8df3abc999192..2ef9ac31f31e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -182,11 +182,6 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, - uint64_t src_offset, struct kgd_mem *dst_mem, - uint64_t dest_offset, uint64_t size, struct dma_fence **f, - uint64_t *actual_size); - bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, @@ -322,7 +317,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint8_t xcp_id); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 138ef4e909fba..b78f6684f609e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1784,12 +1784,13 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume) { struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); enum ttm_bo_type bo_type = ttm_bo_type_device; + struct sg_table *sg = NULL; uint64_t user_addr = 0; struct amdgpu_bo *bo; struct drm_gem_object *gobj = NULL; @@ -1852,10 +1853,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; - if (sg) { - alloc_domain = AMDGPU_GEM_DOMAIN_CPU; - bo_type = ttm_bo_type_sg; - } *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); if (!*mem) { ret = -ENOMEM; @@ -3592,85 +3589,6 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, - uint64_t src_offset, struct kgd_mem *dst_mem, - uint64_t dst_offset, uint64_t size, - struct dma_fence **f, uint64_t *actual_size) -{ - struct amdgpu_device *adev = NULL; - struct amdgpu_copy_mem src, dst; - struct ww_acquire_ctx ticket; - struct list_head list, duplicates; - struct ttm_validate_buffer resv_list[2]; - struct dma_fence *fence = NULL; - int i, r; - - if (!kgd || !src_mem || !dst_mem || !actual_size) - return -EINVAL; - - *actual_size = 0; - - adev = get_amdgpu_device(kgd); - INIT_LIST_HEAD(&list); - INIT_LIST_HEAD(&duplicates); - - src.bo = &src_mem->bo->tbo; - dst.bo = &dst_mem->bo->tbo; - src.mem = &src.bo->mem; - dst.mem = &dst.bo->mem; - src.offset = src_offset; - dst.offset = dst_offset; - - resv_list[0].bo = src.bo; - resv_list[1].bo = dst.bo; - - for (i = 0; i < 2; i++) { - resv_list[i].num_shared = 1; - list_add_tail(&resv_list[i].head, &list); - } - - r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); - if (r) { - pr_err("Copy buffer failed. Unable to reserve bo (%d)\n", r); - return r; - } - - /* The process to which the Source and Dest BOs belong to could be - * evicted and the BOs invalidated. So validate BOs before use - */ - r = amdgpu_amdkfd_bo_validate(src_mem->bo, src_mem->domain, false); - if (r) { - pr_err("CMA fail: SRC BO validate failed %d\n", r); - goto validate_fail; - } - - - r = amdgpu_amdkfd_bo_validate(dst_mem->bo, dst_mem->domain, false); - if (r) { - pr_err("CMA fail: DST BO validate failed %d\n", r); - goto validate_fail; - } - - - r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, size, false, NULL, - &fence); - if (r) - pr_err("Copy buffer failed %d\n", r); - else - *actual_size = size; - if (fence) { - amdgpu_bo_fence(src_mem->bo, fence, true); - amdgpu_bo_fence(dst_mem->bo, fence, true); - } - if (f) - *f = dma_fence_get(fence); - dma_fence_put(fence); - -validate_fail: - ttm_eu_backoff_reservation(&ticket, &list); - return r; -} - /* Returns GPU-specific tiling mode information */ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b2351b10718d8..55f896ca7eae2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1196,7 +1196,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->adev, args->va_addr, args->size, - pdd->drm_priv, NULL, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, (struct kgd_mem **) &mem, &offset, flags, false); if (err) @@ -1715,843 +1715,6 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, return r; } -/* Maximum number of entries for process pages array which lives on stack */ -#define MAX_PP_STACK_COUNT 16 -/* Maximum number of pages kmalloc'd to hold struct page's during copy */ -#define MAX_KMALLOC_PAGES (PAGE_SIZE * 2) -#define MAX_PP_KMALLOC_COUNT (MAX_KMALLOC_PAGES/sizeof(struct page *)) - -static void kfd_put_sg_table(struct sg_table *sg) -{ - unsigned int i; - struct scatterlist *s; - - for_each_sg(sg->sgl, s, sg->nents, i) - put_page(sg_page(s)); -} - - -/* Create a sg table for the given userptr BO by pinning its system pages - * @bo: userptr BO - * @offset: Offset into BO - * @mm/@task: mm_struct & task_struct of the process that holds the BO - * @size: in/out: desired size / actual size which could be smaller - * @sg_size: out: Size of sg table. This is ALIGN_UP(@size) - * @ret_sg: out sg table - */ -static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, - int64_t offset, int cma_write, - struct mm_struct *mm, - struct task_struct *task, - uint64_t *size, - uint64_t *sg_size, - struct sg_table **ret_sg) -{ - int ret, locked = 1; - struct sg_table *sg = NULL; - unsigned int i, offset_in_page, flags = 0; - unsigned long nents, n; - unsigned long pa = (bo->cpuva + offset) & PAGE_MASK; - unsigned int cur_page = 0; - struct scatterlist *s; - uint64_t sz = *size; - struct page **process_pages; - - *sg_size = 0; - sg = kmalloc(sizeof(*sg), GFP_KERNEL); - if (!sg) - return -ENOMEM; - - offset_in_page = offset & (PAGE_SIZE - 1); - nents = (sz + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; - - ret = sg_alloc_table(sg, nents, GFP_KERNEL); - if (unlikely(ret)) { - ret = -ENOMEM; - goto sg_alloc_fail; - } - process_pages = kmalloc_array(nents, sizeof(struct pages *), - GFP_KERNEL); - if (!process_pages) { - ret = -ENOMEM; - goto page_alloc_fail; - } - - if (cma_write) - flags = FOLL_WRITE; - locked = 1; - mmap_read_lock(mm); - n = get_user_pages_remote(mm, pa, nents, flags, process_pages, - NULL, &locked); - if (locked) - mmap_read_unlock(mm); - if (n <= 0) { - pr_err("CMA: Invalid virtual address 0x%lx\n", pa); - ret = -EFAULT; - goto get_user_fail; - } - if (n != nents) { - /* Pages pinned < requested. Set the size accordingly */ - *size = (n * PAGE_SIZE) - offset_in_page; - pr_debug("Requested %lx but pinned %lx\n", nents, n); - } - - sz = 0; - for_each_sg(sg->sgl, s, n, i) { - sg_set_page(s, process_pages[cur_page], PAGE_SIZE, - offset_in_page); - sg_dma_address(s) = page_to_phys(process_pages[cur_page]); - offset_in_page = 0; - cur_page++; - sz += PAGE_SIZE; - } - *ret_sg = sg; - *sg_size = sz; - - kfree(process_pages); - return 0; - -get_user_fail: - kfree(process_pages); -page_alloc_fail: - sg_free_table(sg); -sg_alloc_fail: - kfree(sg); - return ret; -} - -static void kfd_free_cma_bos(struct cma_iter *ci) -{ - struct cma_system_bo *cma_bo, *tmp; - - list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { - struct kfd_dev *dev = cma_bo->dev; - - /* sg table is deleted by free_memory_of_gpu */ - if (cma_bo->sg) - kfd_put_sg_table(cma_bo->sg); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); - list_del(&cma_bo->list); - kfree(cma_bo); - } -} - -/* 1 second timeout */ -#define CMA_WAIT_TIMEOUT msecs_to_jiffies(1000) - -static int kfd_cma_fence_wait(struct dma_fence *f) -{ - int ret; - - ret = dma_fence_wait_timeout(f, false, CMA_WAIT_TIMEOUT); - if (likely(ret > 0)) - return 0; - if (!ret) - ret = -ETIME; - return ret; -} - -/* Put previous (old) fence @pf but it waits for @pf to signal if the context - * of the current fence @cf is different. - */ -static int kfd_fence_put_wait_if_diff_context(struct dma_fence *cf, - struct dma_fence *pf) -{ - int ret = 0; - - if (pf && cf && cf->context != pf->context) - ret = kfd_cma_fence_wait(pf); - dma_fence_put(pf); - return ret; -} - -#define MAX_SYSTEM_BO_SIZE (512*PAGE_SIZE) - -/* Create an equivalent system BO for the given @bo. If @bo is a userptr then - * create a new system BO by pinning underlying system pages of the given - * userptr BO. If @bo is in Local Memory then create an empty system BO and - * then copy @bo into this new BO. - * @bo: Userptr BO or Local Memory BO - * @offset: Offset into bo - * @size: in/out: The size of the new BO could be less than requested if all - * the pages couldn't be pinned or size > MAX_SYSTEM_BO_SIZE. This would - * be reflected in @size - * @mm/@task: mm/task to which @bo belongs to - * @cma_bo: out: new system BO - */ -static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, - uint64_t *size, uint64_t offset, - int cma_write, struct kfd_process *p, - struct mm_struct *mm, - struct task_struct *task, - struct cma_system_bo **cma_bo) -{ - int ret; - struct kfd_process_device *pdd = NULL; - struct cma_system_bo *cbo; - uint64_t bo_size = 0; - struct dma_fence *f; - - uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; - - *cma_bo = NULL; - cbo = kzalloc(sizeof(**cma_bo), GFP_KERNEL); - if (!cbo) - return -ENOMEM; - - INIT_LIST_HEAD(&cbo->list); - if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - bo_size = min_t(uint64_t, *size, MAX_SYSTEM_BO_SIZE); - else if (bo->cpuva) { - ret = kfd_create_sg_table_from_userptr_bo(bo, offset, - cma_write, mm, task, - size, &bo_size, - &cbo->sg); - if (ret) { - pr_err("CMA: BO create with sg failed %d\n", ret); - goto sg_fail; - } - } else { - WARN_ON(1); - ret = -EINVAL; - goto sg_fail; - } - mutex_lock(&p->mutex); - pdd = kfd_get_process_device_data(kdev, p); - if (!pdd) { - mutex_unlock(&p->mutex); - pr_err("Process device data doesn't exist\n"); - ret = -EINVAL; - goto pdd_fail; - } - - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, - pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags); - mutex_unlock(&p->mutex); - if (ret) { - pr_err("Failed to create shadow system BO %d\n", ret); - goto pdd_fail; - } - - if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, - offset, cbo->mem, 0, - bo_size, &f, size); - if (ret) { - pr_err("CMA: Intermediate copy failed %d\n", ret); - goto copy_fail; - } - - /* Wait for the copy to finish as subsequent copy will be done - * by different device - */ - ret = kfd_cma_fence_wait(f); - dma_fence_put(f); - if (ret) { - pr_err("CMA: Intermediate copy timed out %d\n", ret); - goto copy_fail; - } - } - - cbo->dev = kdev; - *cma_bo = cbo; - - return ret; - -copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); -pdd_fail: - if (cbo->sg) { - kfd_put_sg_table(cbo->sg); - sg_free_table(cbo->sg); - kfree(cbo->sg); - } -sg_fail: - kfree(cbo); - return ret; -} - -/* Update cma_iter.cur_bo with KFD BO that is assocaited with - * cma_iter.array.va_addr - */ -static int kfd_cma_iter_update_bo(struct cma_iter *ci) -{ - struct kfd_memory_range *arr = ci->array; - uint64_t va_end = arr->va_addr + arr->size - 1; - - mutex_lock(&ci->p->mutex); - ci->cur_bo = kfd_process_find_bo_from_interval(ci->p, arr->va_addr, - va_end); - mutex_unlock(&ci->p->mutex); - - if (!ci->cur_bo || va_end > ci->cur_bo->it.last) { - pr_err("CMA failed. Range out of bounds\n"); - return -EFAULT; - } - return 0; -} - -/* Advance iter by @size bytes. */ -static int kfd_cma_iter_advance(struct cma_iter *ci, unsigned long size) -{ - int ret = 0; - - ci->offset += size; - if (WARN_ON(size > ci->total || ci->offset > ci->array->size)) - return -EFAULT; - ci->total -= size; - /* If current range is copied, move to next range if available. */ - if (ci->offset == ci->array->size) { - - /* End of all ranges */ - if (!(--ci->nr_segs)) - return 0; - - ci->array++; - ci->offset = 0; - ret = kfd_cma_iter_update_bo(ci); - if (ret) - return ret; - } - ci->bo_offset = (ci->array->va_addr + ci->offset) - - ci->cur_bo->it.start; - return ret; -} - -static int kfd_cma_iter_init(struct kfd_memory_range *arr, unsigned long segs, - struct kfd_process *p, struct mm_struct *mm, - struct task_struct *task, struct cma_iter *ci) -{ - int ret; - int nr; - - if (!arr || !segs) - return -EINVAL; - - memset(ci, 0, sizeof(*ci)); - INIT_LIST_HEAD(&ci->cma_list); - ci->array = arr; - ci->nr_segs = segs; - ci->p = p; - ci->offset = 0; - ci->mm = mm; - ci->task = task; - for (nr = 0; nr < segs; nr++) - ci->total += arr[nr].size; - - /* Valid but size is 0. So copied will also be 0 */ - if (!ci->total) - return 0; - - ret = kfd_cma_iter_update_bo(ci); - if (!ret) - ci->bo_offset = arr->va_addr - ci->cur_bo->it.start; - return ret; -} - -static bool kfd_cma_iter_end(struct cma_iter *ci) -{ - if (!(ci->nr_segs) || !(ci->total)) - return true; - return false; -} - -/* Copies @size bytes from si->cur_bo to di->cur_bo BO. The function assumes - * both source and dest. BOs are userptr BOs. Both BOs can either belong to - * current process or one of the BOs can belong to a differnt - * process. @Returns 0 on success, -ve on failure - * - * @si: Source iter - * @di: Dest. iter - * @cma_write: Indicates if it is write to remote or read from remote - * @size: amount of bytes to be copied - * @copied: Return number of bytes actually copied. - */ -static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, - bool cma_write, uint64_t size, - uint64_t *copied) -{ - int i, ret = 0, locked; - unsigned int nents, nl; - unsigned int offset_in_page; - struct page *pp_stack[MAX_PP_STACK_COUNT]; - struct page **process_pages = pp_stack; - unsigned long rva, lva = 0, flags = 0; - uint64_t copy_size, to_copy = size; - struct cma_iter *li, *ri; - - if (cma_write) { - ri = di; - li = si; - flags |= FOLL_WRITE; - } else { - li = di; - ri = si; - } - /* rva: remote virtual address. Page aligned to start page. - * rva + offset_in_page: Points to remote start address - * lva: local virtual address. Points to the start address. - * nents: computes number of remote pages to request - */ - offset_in_page = ri->bo_offset & (PAGE_SIZE - 1); - rva = (ri->cur_bo->cpuva + ri->bo_offset) & PAGE_MASK; - lva = li->cur_bo->cpuva + li->bo_offset; - - nents = (size + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; - - copy_size = min_t(uint64_t, size, PAGE_SIZE - offset_in_page); - *copied = 0; - - if (nents > MAX_PP_STACK_COUNT) { - /* For reliability kmalloc only 2 pages worth */ - process_pages = kmalloc(min_t(size_t, MAX_KMALLOC_PAGES, - sizeof(struct pages *)*nents), - GFP_KERNEL); - - if (!process_pages) - return -ENOMEM; - } - - while (nents && to_copy) { - nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); - locked = 1; - mmap_read_lock(ri->mm); - nl = get_user_pages_remote(ri->mm, rva, nl, - flags, process_pages, NULL, - &locked); - if (locked) - mmap_read_unlock(ri->mm); - if (nl <= 0) { - pr_err("CMA: Invalid virtual address 0x%lx\n", rva); - ret = -EFAULT; - break; - } - - for (i = 0; i < nl; i++) { - unsigned int n; - void *kaddr = kmap(process_pages[i]); - - if (cma_write) { - n = copy_from_user(kaddr+offset_in_page, - (void *)lva, copy_size); - set_page_dirty(process_pages[i]); - } else { - n = copy_to_user((void *)lva, - kaddr+offset_in_page, - copy_size); - } - kunmap(kaddr); - if (n) { - ret = -EFAULT; - break; - } - to_copy -= copy_size; - if (!to_copy) - break; - lva += copy_size; - rva += (copy_size + offset_in_page); - WARN_ONCE(rva & (PAGE_SIZE - 1), - "CMA: Error in remote VA computation"); - offset_in_page = 0; - copy_size = min_t(uint64_t, to_copy, PAGE_SIZE); - } - - for (i = 0; i < nl; i++) - put_page(process_pages[i]); - - if (ret) - break; - nents -= nl; - } - - if (process_pages != pp_stack) - kfree(process_pages); - - *copied = (size - to_copy); - return ret; - -} - -static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, - struct kfd_process *p, struct kgd_mem **mem) -{ - int ret; - struct kfd_process_device *pdd = NULL; - uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; - - if (!mem || !size || !p || !kdev) - return -EINVAL; - - *mem = NULL; - - mutex_lock(&p->mutex); - pdd = kfd_get_process_device_data(kdev, p); - if (!pdd) { - mutex_unlock(&p->mutex); - pr_err("Process device data doesn't exist\n"); - return -EINVAL; - } - - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, - pdd->drm_priv, NULL, - mem, NULL, flags); - mutex_unlock(&p->mutex); - if (ret) { - pr_err("Failed to create shadow system BO %d\n", ret); - return -EINVAL; - } - - return 0; -} - -static int kfd_destroy_kgd_mem(struct kgd_mem *mem) -{ - if (!mem) - return -EINVAL; - - /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); -} - -/* Copies @size bytes from si->cur_bo to di->cur_bo starting at their - * respective offset. - * @si: Source iter - * @di: Dest. iter - * @cma_write: Indicates if it is write to remote or read from remote - * @size: amount of bytes to be copied - * @f: Return the last fence if any - * @copied: Return number of bytes actually copied. - */ -static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, - int cma_write, uint64_t size, - struct dma_fence **f, uint64_t *copied, - struct kgd_mem **tmp_mem) -{ - int err = 0; - struct kfd_bo *dst_bo = di->cur_bo, *src_bo = si->cur_bo; - uint64_t src_offset = si->bo_offset, dst_offset = di->bo_offset; - struct kgd_mem *src_mem = src_bo->mem, *dst_mem = dst_bo->mem; - struct kfd_dev *dev = dst_bo->dev; - int d2d = 0; - - *copied = 0; - if (f) - *f = NULL; - if (src_bo->cpuva && dst_bo->cpuva) - return kfd_copy_userptr_bos(si, di, cma_write, size, copied); - - /* If either source or dest. is userptr, create a shadow system BO - * by using the underlying userptr BO pages. Then use this shadow - * BO for copy. src_offset & dst_offset are adjusted because the new BO - * is only created for the window (offset, size) requested. - * The shadow BO is created on the other device. This means if the - * other BO is a device memory, the copy will be using that device. - * The BOs are stored in cma_list for deferred cleanup. This minimizes - * fence waiting just to the last fence. - */ - if (src_bo->cpuva) { - dev = dst_bo->dev; - err = kfd_create_cma_system_bo(dev, src_bo, &size, - si->bo_offset, cma_write, - si->p, si->mm, si->task, - &si->cma_bo); - src_mem = si->cma_bo->mem; - src_offset = si->bo_offset & (PAGE_SIZE - 1); - list_add_tail(&si->cma_bo->list, &si->cma_list); - } else if (dst_bo->cpuva) { - dev = src_bo->dev; - err = kfd_create_cma_system_bo(dev, dst_bo, &size, - di->bo_offset, cma_write, - di->p, di->mm, di->task, - &di->cma_bo); - dst_mem = di->cma_bo->mem; - dst_offset = di->bo_offset & (PAGE_SIZE - 1); - list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { - /* This indicates that atleast on of the BO is in local mem. - * If both are in local mem of different devices then create an - * intermediate System BO and do a double copy - * [VRAM]--gpu1-->[System BO]--gpu2-->[VRAM]. - * If only one BO is in VRAM then use that GPU to do the copy - */ - if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM && - dst_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - dev = dst_bo->dev; - size = min_t(uint64_t, size, MAX_SYSTEM_BO_SIZE); - d2d = 1; - - if (*tmp_mem == NULL) { - if (kfd_create_kgd_mem(src_bo->dev, - MAX_SYSTEM_BO_SIZE, - si->p, - tmp_mem)) - return -EINVAL; - } - - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, - src_bo->mem, si->bo_offset, - *tmp_mem, 0, - size, f, &size)) - /* tmp_mem will be freed in caller.*/ - return -EINVAL; - - kfd_cma_fence_wait(*f); - dma_fence_put(*f); - - src_mem = *tmp_mem; - src_offset = 0; - } else if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - dev = src_bo->dev; - /* else already set to dst_bo->dev */ - } - - if (err) { - pr_err("Failed to create system BO %d", err); - return -EINVAL; - } - - err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, - dst_mem, dst_offset, size, f, - copied); - /* The tmp_bo allocates additional memory. So it is better to wait and - * delete. Also since multiple GPUs are involved the copies are - * currently not pipelined. - */ - if (*tmp_mem && d2d) { - if (!err) { - kfd_cma_fence_wait(*f); - dma_fence_put(*f); - *f = NULL; - } - } - return err; -} - -/* Copy single range from source iterator @si to destination iterator @di. - * @si will move to next range and @di will move by bytes copied. - * @return : 0 for success or -ve for failure - * @f: The last fence if any - * @copied: out: number of bytes copied - */ -static int kfd_copy_single_range(struct cma_iter *si, struct cma_iter *di, - bool cma_write, struct dma_fence **f, - uint64_t *copied, struct kgd_mem **tmp_mem) -{ - int err = 0; - uint64_t copy_size, n; - uint64_t size = si->array->size; - struct kfd_bo *src_bo = si->cur_bo; - struct dma_fence *lfence = NULL; - - if (!src_bo || !di || !copied) - return -EINVAL; - *copied = 0; - if (f) - *f = NULL; - - while (size && !kfd_cma_iter_end(di)) { - struct dma_fence *fence = NULL; - - copy_size = min(size, (di->array->size - di->offset)); - - err = kfd_copy_bos(si, di, cma_write, copy_size, - &fence, &n, tmp_mem); - if (err) { - pr_err("CMA %d failed\n", err); - break; - } - - if (fence) { - err = kfd_fence_put_wait_if_diff_context(fence, - lfence); - lfence = fence; - if (err) - break; - } - - size -= n; - *copied += n; - err = kfd_cma_iter_advance(si, n); - if (err) - break; - err = kfd_cma_iter_advance(di, n); - if (err) - break; - } - - if (f) - *f = dma_fence_get(lfence); - dma_fence_put(lfence); - - return err; -} - -static int kfd_ioctl_cross_memory_copy(struct file *filep, - struct kfd_process *local_p, void *data) -{ - struct kfd_ioctl_cross_memory_copy_args *args = data; - struct kfd_memory_range *src_array, *dst_array; - struct kfd_process *remote_p; - struct task_struct *remote_task; - struct mm_struct *remote_mm; - struct pid *remote_pid; - struct dma_fence *lfence = NULL; - uint64_t copied = 0, total_copied = 0; - struct cma_iter di, si; - const char *cma_op; - int err = 0; - struct kgd_mem *tmp_mem = NULL; - - /* Check parameters */ - if (args->src_mem_range_array == 0 || args->dst_mem_range_array == 0 || - args->src_mem_array_size == 0 || args->dst_mem_array_size == 0) - return -EINVAL; - args->bytes_copied = 0; - - /* Allocate space for source and destination arrays */ - src_array = kmalloc_array((args->src_mem_array_size + - args->dst_mem_array_size), - sizeof(struct kfd_memory_range), - GFP_KERNEL); - if (!src_array) - return -ENOMEM; - dst_array = &src_array[args->src_mem_array_size]; - - if (copy_from_user(src_array, (void __user *)args->src_mem_range_array, - args->src_mem_array_size * - sizeof(struct kfd_memory_range))) { - err = -EFAULT; - goto copy_from_user_fail; - } - if (copy_from_user(dst_array, (void __user *)args->dst_mem_range_array, - args->dst_mem_array_size * - sizeof(struct kfd_memory_range))) { - err = -EFAULT; - goto copy_from_user_fail; - } - - /* Get remote process */ - remote_pid = find_get_pid(args->pid); - if (!remote_pid) { - pr_err("Cross mem copy failed. Invalid PID %d\n", args->pid); - err = -ESRCH; - goto copy_from_user_fail; - } - - remote_task = get_pid_task(remote_pid, PIDTYPE_PID); - if (!remote_pid) { - pr_err("Cross mem copy failed. Invalid PID or task died %d\n", - args->pid); - err = -ESRCH; - goto get_pid_task_fail; - } - - /* Check access permission */ - remote_mm = mm_access(remote_task, PTRACE_MODE_ATTACH_REALCREDS); - if (!remote_mm || IS_ERR(remote_mm)) { - err = IS_ERR(remote_mm) ? PTR_ERR(remote_mm) : -ESRCH; - if (err == -EACCES) { - pr_err("Cross mem copy failed. Permission error\n"); - err = -EPERM; - } else - pr_err("Cross mem copy failed. Invalid task %d\n", - err); - goto mm_access_fail; - } - - remote_p = kfd_get_process(remote_task); - if (IS_ERR(remote_p)) { - pr_err("Cross mem copy failed. Invalid kfd process %d\n", - args->pid); - err = -EINVAL; - goto kfd_process_fail; - } - /* Initialise cma_iter si & @di with source & destination range. */ - if (KFD_IS_CROSS_MEMORY_WRITE(args->flags)) { - cma_op = "WRITE"; - pr_debug("CMA WRITE: local -> remote\n"); - err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, - remote_p, remote_mm, remote_task, &di); - if (err) - goto kfd_process_fail; - err = kfd_cma_iter_init(src_array, args->src_mem_array_size, - local_p, current->mm, current, &si); - if (err) - goto kfd_process_fail; - } else { - cma_op = "READ"; - pr_debug("CMA READ: remote -> local\n"); - - err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, - local_p, current->mm, current, &di); - if (err) - goto kfd_process_fail; - err = kfd_cma_iter_init(src_array, args->src_mem_array_size, - remote_p, remote_mm, remote_task, &si); - if (err) - goto kfd_process_fail; - } - - /* Copy one si range at a time into di. After each call to - * kfd_copy_single_range() si will move to next range. di will be - * incremented by bytes copied - */ - while (!kfd_cma_iter_end(&si) && !kfd_cma_iter_end(&di)) { - struct dma_fence *fence = NULL; - - err = kfd_copy_single_range(&si, &di, - KFD_IS_CROSS_MEMORY_WRITE(args->flags), - &fence, &copied, &tmp_mem); - total_copied += copied; - - if (err) - break; - - /* Release old fence if a later fence is created. If no - * new fence is created, then keep the preivous fence - */ - if (fence) { - err = kfd_fence_put_wait_if_diff_context(fence, - lfence); - lfence = fence; - if (err) - break; - } - } - - /* Wait for the last fence irrespective of error condition */ - if (lfence) { - err = kfd_cma_fence_wait(lfence); - dma_fence_put(lfence); - if (err) - pr_err("CMA %s failed. BO timed out\n", cma_op); - } - - if (tmp_mem) - kfd_destroy_kgd_mem(tmp_mem); - - kfd_free_cma_bos(&si); - kfd_free_cma_bos(&di); - -kfd_process_fail: - mmput(remote_mm); -mm_access_fail: - put_task_struct(remote_task); -get_pid_task_fail: - put_pid(remote_pid); -copy_from_user_fail: - kfree(src_array); - - /* An error could happen after partial copy. In that case this will - * reflect partial amount of bytes copied - */ - args->bytes_copied = total_copied; - return err; -} - static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -4373,9 +3536,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), - - AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY, - kfd_ioctl_cross_memory_copy, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 7690289f76695..3b45fd2697d7c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -415,38 +415,6 @@ struct kfd_bo { unsigned int mem_type; }; -struct cma_system_bo { - struct kgd_mem *mem; - struct sg_table *sg; - struct kfd_dev *dev; - struct list_head list; -}; - -/* Similar to iov_iter */ -struct cma_iter { - /* points to current entry of range array */ - struct kfd_memory_range *array; - /* total number of entries in the initial array */ - unsigned long nr_segs; - /* total amount of data pointed by kfd array*/ - unsigned long total; - /* offset into the entry pointed by cma_iter.array */ - unsigned long offset; - struct kfd_process *p; - struct mm_struct *mm; - struct task_struct *task; - /* current kfd_bo associated with cma_iter.array.va_addr */ - struct kfd_bo *cur_bo; - /* offset w.r.t cur_bo */ - unsigned long bo_offset; - /* If cur_bo is a userptr BO, then a shadow system BO is created - * using its underlying pages. cma_bo holds this BO. cma_list is a - * list cma_bos created in one session - */ - struct cma_system_bo *cma_bo; - struct list_head cma_list; -}; - enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index c415adb179dc7..7455ac0c6e616 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -743,7 +743,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, &mem, NULL, + pdd->drm_priv, mem, NULL, flags, false); if (err) goto err_alloc_mem; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 755512489136a..bf6e0832d7cdd 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -846,37 +846,6 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; -struct kfd_memory_range { - __u64 va_addr; - __u64 size; -}; - -/* flags definitions - * BIT0: 0: read operation, 1: write operation. - * This also identifies if the src or dst array belongs to remote process - */ -#define KFD_CROSS_MEMORY_RW_BIT (1 << 0) -#define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) -#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) -#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) - -struct kfd_ioctl_cross_memory_copy_args { - /* to KFD: Process ID of the remote process */ - __u32 pid; - /* to KFD: See above definition */ - __u32 flags; - /* to KFD: Source GPU VM range */ - __u64 src_mem_range_array; - /* to KFD: Size of above array */ - __u64 src_mem_array_size; - /* to KFD: Destination GPU VM range */ - __u64 dst_mem_range_array; - /* to KFD: Size of above array */ - __u64 dst_mem_array_size; - /* from KFD: Total amount of bytes copied */ - __u64 bytes_copied; -}; - /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1826,11 +1795,7 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) -#define AMDKFD_IOC_CROSS_MEMORY_COPY \ - AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) - #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 - #endif From 38bbb8ea1d398004de5c2bc88dde1cce9eef9ffc Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Fri, 5 Aug 2022 17:10:44 +0800 Subject: [PATCH 0883/2070] drm/amdgpu: relax the check in amdgpu_device_is_peer_accessible To support p2p feature on old kernels without defining CONFIG_PCI_P2PDMA, amdgpu_device_is_peer_accessible needs to return true in such scenario. So relax the requirement from upstream. Suggested-by: Ramesh Errabolu Suggested-by: Felix Kuehling Signed-off-by: Leslie Shi Signed-off-by: Guchun Chen Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 1405d4e373f1d..a7fae3071d890 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6913,17 +6913,20 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) { -#ifdef CONFIG_HSA_AMD_P2P - bool p2p_access = + bool p2p_access = true; + bool p2p_addressable = false; + bool is_large_bar = adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + +#ifdef CONFIG_PCI_P2PDMA + p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); if (!p2p_access) dev_info(adev->dev, "PCIe P2P access from peer device %s is not supported by the chipset\n", pci_name(peer_adev->pdev)); - - bool is_large_bar = adev->gmc.visible_vram_size && - adev->gmc.real_vram_size == adev->gmc.visible_vram_size; - bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev); + p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev); +#endif if (!p2p_addressable) { uint64_t address_mask = peer_adev->dev->dma_mask ? @@ -6935,9 +6938,6 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, aper_limit & address_mask); } return pcie_p2p && is_large_bar && p2p_access && p2p_addressable; -#else - return false; -#endif } int amdgpu_device_baco_enter(struct amdgpu_device *adev) From a1328643292bf194da8deeacee6dec0aa595564e Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 8 Aug 2022 10:06:03 +0800 Subject: [PATCH 0884/2070] drm/amdgpu: drop compiler guard for pcie_p2p CONFIG_HSA_AMD_P2P is not needed as a build option for pcie_p2p, as p2p feature needs to be always supported on dkms branch, otherwise, intree build fails once CONFIG_HSA_AMD_P2P is not defined. Also drop redundant extern of pcie_p2p in amdgpu.h. Fixes: af428201b20e("drm/amdgpu: relax the check in amdgpu_device_is_peer_accessible") Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7450dded51c17..f73ac297f17d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -241,9 +241,6 @@ static const bool __maybe_unused debug_evictions; /* = false */ static const bool __maybe_unused no_system_mem_limit; static const int __maybe_unused halt_if_hws_hang; #endif -#ifdef CONFIG_HSA_AMD_P2P -extern bool pcie_p2p; -#endif extern int amdgpu_tmz; extern int amdgpu_reset_method; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 96e64b4044b64..6ab8cdeb5c590 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -871,11 +871,9 @@ module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); * DOC: pcie_p2p (bool) * Enable PCIe P2P (requires large-BAR). Default value: true (on) */ -#ifdef CONFIG_HSA_AMD_P2P bool pcie_p2p = true; module_param(pcie_p2p, bool, 0444); MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); -#endif /** * DOC: dcfeaturemask (uint) From 418ec07e98ede579a091224bc99422ad813214ef Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 8 Aug 2022 10:49:08 +0800 Subject: [PATCH 0885/2070] drm/amdgpu: enable CONFIG_HSA_AMD_P2P when PCI_P2PDMA and DMABUF_MOVENOTIFY are set Suggested-by: Felix Kuehling Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a00c632cc588f..ff7758499d54d 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -167,9 +167,11 @@ endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP -ifeq ($(call _is_kcl_macro_defined,HAVE_LINUX_PCI_P2PDMA_H),y) -export CONFIG_HSA_AMD_P2P=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P +ifeq (y,$(CONFIG_PCI_P2PDMA)) + ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) + export CONFIG_HSA_AMD_P2P=y + subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P + endif endif # Trying to enable DCN2/3 with core2 optimizations will result in From d41e2991c0acca91750b4e3a57e69487758b41d5 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 17:38:51 -0400 Subject: [PATCH 0886/2070] drm/amdkfd: Fix VRAM attachment Use kfd_mem_attach_vram_bo instead of kfd_mem_attach_dmabuf. Signed-off-by: Felix Kuehling Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index b78f6684f609e..47ad52ad9c5e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -981,9 +981,8 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; #ifdef AMDKCL_AMDGPU_DMABUF_OPS - /* Enable acces to GTT and VRAM BOs of peer devices */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || - mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { + /* Enable acces to GTT BOs of peer devices */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { attachment[i]->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) From 9072e971001d51a86fa49d3d686bc1d18190cf7b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 6 Jul 2022 09:56:55 +0800 Subject: [PATCH 0887/2070] drm/amdkcl: Fix the CFLAGS_xx process script Only remove the AMDDALPATH with prefix CFLAGS_ Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I9be3fe482ccb1da0226572e2726c025d5487205c --- drivers/gpu/drm/amd/dkms/pre-build.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 81a0d5da5c8bd..07df3f07ea532 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -67,10 +67,11 @@ done export KERNELVER (cd $SRC && ./configure) -# rename CFLAGS_target.o to CFLAGS_target.o +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then for file in $(grep -rl 'CFLAGS_' amd/display/); do - sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi From da7088671e6b800592347a994d2a652e907de358 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Jul 2022 14:09:09 +0800 Subject: [PATCH 0888/2070] drm/amdkcl: Fix the bug when get gcc version Fix the bug when get gcc version Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Change-Id: If49e6bb007c382cdd1e35e0597a4d9e77287f099 --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ff7758499d54d..64171883b4bb2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -19,7 +19,7 @@ endif ifdef CONFIG_CC_IS_GCC GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) -GCCPAT=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) From bc23cfd66089a1f44a1b612ce456f00ce7b81948 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Jul 2022 10:46:54 +0800 Subject: [PATCH 0889/2070] drm/amdkcl: Export gcc related config Check and export CONFIG_CC_IS_GCC and CONFIG_GCC_VERSION for the kernels which has no these config. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Id2f5da8b515a11bde8e40b8cc4a694b0b249ab47 --- drivers/gpu/drm/amd/dkms/Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 64171883b4bb2..6178008b48339 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -16,16 +16,22 @@ ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) $(error dma_resv->seq is missing., exit...) endif -ifdef CONFIG_CC_IS_GCC +ifeq ($(CC), gcc) GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) +ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") $(warning "This may cause unexpected and hard-to-isolate compiler-related issues") endif +else +export CONFIG_CC_IS_GCC=y +export CONFIG_GCC_VERSION=$(GCCSTR) +$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") +endif endif DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) From 0cddfa38762b9fb70063618099fe227042dcc7d2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Aug 2022 16:50:39 +0800 Subject: [PATCH 0890/2070] drm/amdkcl: fix ttm debugfs dir name Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index d3bfb9a696a74..9a676a28a1180 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -80,7 +80,7 @@ static int ttm_global_init(void) si_meminfo(&si); - ttm_debugfs_root = debugfs_create_dir("ttm", NULL); + ttm_debugfs_root = debugfs_create_dir(TTM_NAME, NULL); if (IS_ERR(ttm_debugfs_root)) { ttm_debugfs_root = NULL; } From 2cb58b5575a1da1f8faaa7ea8b12de64409bd646 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 15 Aug 2022 22:07:12 +0800 Subject: [PATCH 0891/2070] drm/amdkcl: fake macro for_each_cpu_wrap and function cpumask_next_wrap It's caused by 78231f639e2eec3f14de8bb8309f459413ca86b4 drm/amdkfd: Try to schedule bottom half on same core Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c | 38 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cpumask.h | 43 ++++++++++++++++++++++++ 4 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c create mode 100644 include/kcl/kcl_cpumask.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 2b5951157cf48..f669d870d0ffd 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o - kcl_workqueue.o + kcl_workqueue.o kcl_cpumask.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c new file mode 100644 index 0000000000000..fe36b386ff52b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#ifndef for_each_cpu_wrap +/* copied from lib/cpumask.c +/** + * cpumask_next_wrap - helper to implement for_each_cpu_wrap + * @n: the cpu prior to the place to search + * @mask: the cpumask pointer + * @start: the start point of the iteration + * @wrap: assume @n crossing @start terminates the iteration + * + * Returns >= nr_cpu_ids on completion + * + * Note: the @wrap argument is required for the start condition when + * we cannot assume @start is set in @mask. + */ +int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, int start, bool wrap) +{ + int next; + +again: + next = cpumask_next(n, mask); + + if (wrap && n < start && next >= start) { + return nr_cpumask_bits; + + } else if (next >= nr_cpumask_bits) { + wrap = true; + n = -1; + goto again; + } + + return next; +} +EXPORT_SYMBOL(_kcl_cpumask_next_wrap); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a782accbb0435..af9b4a884d160 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -86,5 +86,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cpumask.h b/include/kcl/kcl_cpumask.h new file mode 100644 index 0000000000000..aee779d6ec5f2 --- /dev/null +++ b/include/kcl/kcl_cpumask.h @@ -0,0 +1,43 @@ +/*SPDX-License-Identifier: GPL-2.0*/ + +#include +#include +#include +#include +#include + +#ifndef for_each_cpu_wrap + +extern int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, + int start, bool wrap); + +static inline +int cpumask_next_wrap(int n, const struct cpumask *mask, + int start, bool wrap) +{ +return _kcl_cpumask_next_wrap(n, mask, start, wrap); +} + +/* Copied from include/linux/cpumask.h */ +#if NR_CPUS == 1 +#define for_each_cpu_wrap(cpu, mask, start) \ + for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)(start)) +#else +/** + * for_each_cpu_wrap - iterate over every cpu in a mask, starting at a specified location + * @cpu: the (optionally unsigned) integer iterator + * @mask: the cpumask pointer + * @start: the start location + * + * The implementation does not assume any bit in @mask is set (including @start). + * + * After the loop, cpu is >= nr_cpu_ids. + */ +#define for_each_cpu_wrap(cpu, mask, start) \ + for ((cpu) = cpumask_next_wrap((start)-1, (mask), (start), false); \ + (cpu) < nr_cpumask_bits; \ + (cpu) = cpumask_next_wrap((cpu), (mask), (start), true)) + +#endif +#endif + From be5cd764d097c061e9dc95bdda67216ee0c0adac Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 18 Aug 2022 16:42:51 +0800 Subject: [PATCH 0892/2070] drm/amdkcl: Optimize the make command of dkms The parameter -j${num_cpu_cores} will be added by dkms, so remove this param here. Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Reviewed-by: Flora Cui Change-Id: I4346afa99a0a06126bb21873e5c9d0c9c5059131 --- drivers/gpu/drm/amd/dkms/dkms.conf | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index bd79232132f60..a4fde02caa219 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -26,18 +26,7 @@ BUILT_MODULE_NAME[4]="amddrm_ttm_helper" BUILT_MODULE_LOCATION[4]="." DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" -# Find out how many CPU cores can be use if we pass appropriate -j option to make. -# DKMS could use all cores on multicore systems to build the kernel module. -num_cpu_cores() -{ - if [ -x /usr/bin/nproc ]; then - nproc - else - echo "1" - fi -} - -MAKE[0]="make -j$(num_cpu_cores) TTM_NAME=${BUILT_MODULE_NAME[1]} \ +MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$dkms_tree/$module/$module_version/build" From 21916f007fd7a6a6c8f745118fc71c442f557499 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 23 Aug 2022 17:01:32 +0800 Subject: [PATCH 0893/2070] drm/amdkcl: Fix the compile error of drm_for_each_fb Fix the redefintion error of drm_for_each_fb. Because the drm_framebuffer.h is not include in drm_crtc.h anymore. Signed-off-by: Ma Jun Change-Id: Ie68880609d4ceba4aaddbf074b2682d0fc0ee577 --- include/kcl/kcl_drm_crtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 2f01179d0c2b1..3911fa0faaa04 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -48,9 +48,9 @@ #ifndef KCL_KCL_DRM_CRTC_H #define KCL_KCL_DRM_CRTC_H -#include #include #include +#include /* Copied from include/drm/drm_mode.h */ #ifndef DRM_MODE_ROTATE_0 From c78b59584de751d6aa84788857621cb5e1832ac4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 14 Jul 2022 16:40:51 +0800 Subject: [PATCH 0894/2070] drm/amdkcl: fix redefined pr_fmt warning Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_device.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 9a676a28a1180..1700f0dc51504 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -25,8 +25,6 @@ * Authors: Christian König */ -#define pr_fmt(fmt) "[TTM DEVICE] " fmt - #include #include #include @@ -40,6 +38,11 @@ #include "ttm_module.h" #include "ttm_bo_internal.h" +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "[TTM DEVICE] " fmt + /* * ttm_global_mutex - protecting the global state */ From 72ced8d6f16a258259983a0a1a828c136a8ac3c8 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 19 Aug 2022 21:40:12 -0400 Subject: [PATCH 0895/2070] drm/amdkfd: Fix the criu restore regression The logic to create the IDR handles was broken, this fixes the issue seen during criu restore. Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 55f896ca7eae2..f998c1b2087b2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2519,6 +2519,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, int idr_handle; int ret; const bool criu_resume = true; + unsigned int mem_type = 0; u64 offset; if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { @@ -2555,13 +2556,22 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, bo_bucket->size, bo_bucket->addr, offset); /* Restore previous IDR handle */ - pr_debug("Restoring old IDR handle for the BO"); - idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, - bo_priv->idr_handle + 1, GFP_KERNEL); + mem_type = bo_bucket->alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, + bo_bucket->addr, + bo_bucket->size, + 0, mem_type, + bo_priv->idr_handle); if (idr_handle < 0) { pr_err("Could not allocate idr\n"); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, + pdd->drm_priv, NULL); return -ENOMEM; } From 812b992d854b04c849db21db75eeaf86756dafba Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 22 Aug 2022 12:17:43 -0400 Subject: [PATCH 0896/2070] drm/amdkfd: Fix some coding indentation Recently introduced patch to fix a criu regression due to a rebase, had some off indentation and extra newline. Fix that to stay close to the upstream version. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index f998c1b2087b2..a42d67f80eccc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2560,7 +2560,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | - KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, @@ -2570,8 +2570,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, if (idr_handle < 0) { pr_err("Could not allocate idr\n"); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, - pdd->drm_priv, + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, NULL); return -ENOMEM; } From 04df9c6b9550354ac8a09e2ac74d19bc8dfea68b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 29 Jul 2022 16:20:27 +0800 Subject: [PATCH 0897/2070] drm/amdkcl: enable DRM_AMD_DC_DSC_SUPPORT by default v2: remove redundant check Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6178008b48339..3b41a6d897f59 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -191,6 +191,9 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN endif endif +export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT + export CONFIG_DRM_TTM_HELPER=m subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ From 4c391d82b09f31b99b01610964b3fc633a0e8fde Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 10:54:21 +0800 Subject: [PATCH 0898/2070] drm/amdkcl: fake macro in drm/display/dsc_dp.h for legacy os v2: also include drm_dp_helper.h when drm_dp.h not exist v3: drop kcl_drm_dp.h and add some missing macros in kcl_drm_dp_helper.h for legacy os Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 1 + include/kcl/header/drm/display/drm_dp.h | 16 ++++++++++++++++ include/kcl/kcl_drm_dp_helper.h | 11 +++++++++++ 4 files changed, 31 insertions(+) create mode 100644 include/kcl/header/drm/display/drm_dp.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d6fa56b319d54..bcba6b0f99d69 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -303,6 +303,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 17fb837a138c4..b9977c77c0f81 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp.h]) dnl # dnl # v5.7-13141-gca5999fde0a1 diff --git a/include/kcl/header/drm/display/drm_dp.h b/include/kcl/header/drm/display/drm_dp.h new file mode 100644 index 0000000000000..fc1cc1a4bac8e --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_H) +#include_next +#elif defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 43ddfa2ed899d..cecb273e97d8a 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -158,6 +158,17 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +#ifndef DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED +# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 +# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ +#endif + +#ifndef DP_UHBR10 +# define DP_UHBR10 (1 << 0) +# define DP_UHBR20 (1 << 1) +# define DP_UHBR13_5 (1 << 2) +#endif + #ifndef DP_PHY_REPEATER_128B132B_RATES /* See DP_128B132B_SUPPORTED_LINK_RATES for values */ #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ From 9e68e0a49439f0dc24b9c8389acd20acd3e3fe74 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 12:31:33 +0800 Subject: [PATCH 0899/2070] drm/amdkcl: define macro DRM_MODESET_ACQUIRE_INTERRUPTIBLE for legacy os v2: include Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_modeset_lock.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/kcl/kcl_drm_modeset_lock.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index af9b4a884d160..69ddd2d30b8b8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -87,5 +87,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_modeset_lock.h b/include/kcl/kcl_drm_modeset_lock.h new file mode 100644 index 0000000000000..009e4af7a4c00 --- /dev/null +++ b/include/kcl/kcl_drm_modeset_lock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_DRM_MODESET_LOCK_H_H_ +#define _KCL_KCL_DRM_MODESET_LOCK_H_H_ + +#include /* stackdepot.h is not self-contained */ +#include + +#ifndef DRM_MODESET_ACQUIRE_INTERRUPTIBLE +#define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0) +#endif + +#endif From 9527f4c01aebc290169c644c07f0201604a46be4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 14:42:09 +0800 Subject: [PATCH 0900/2070] drm/amdkcl: Test whether struct drm_dsc_config has member simple_422 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 5 +++++ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index dc741b65b2c0c..c9dab816865e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -298,7 +298,9 @@ void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *p DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); +#endif DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); DC_LOG_DSC("\tpic_height %d", pps->pic_height); @@ -436,7 +438,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); +#endif calc_rc_params(&rc, &dsc_reg_vals->pps); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index d61b6430a6409..1699a57ab7cb1 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -48,9 +48,14 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) int slice_width = pps->slice_width; int slice_height = pps->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : (pps->native_422 ? CM_422 : pps->native_420 ? CM_420 : CM_444)); +#else + mode = pps->convert_rgb ? CM_RGB : (pps->native_422 ? CM_422 : + pps->native_420 ? CM_420 : CM_444); +#endif bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) ? BPC_10 : BPC_12; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index b01295c412b1d..13fc27926468f 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -34,7 +34,9 @@ static void copy_pps_fields(struct drm_dsc_config *to, const struct drm_dsc_conf to->convert_rgb = from->convert_rgb; to->slice_width = from->slice_width; to->slice_height = from->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 to->simple_422 = from->simple_422; +#endif to->native_422 = from->native_422; to->native_420 = from->native_420; to->pic_width = from->pic_width; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bcba6b0f99d69..d29b2e98d417b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1183,6 +1183,9 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + /* drm_edid_get_monitor_name is available*/ #define HAVE_DRM_EDID_GET_MONITOR_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 new file mode 100644 index 0000000000000..c5c3c2c4418bb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.20-rc3-804-g19fd5adbb595 +dnl # drm/dsc: Define VESA Display Stream Compression Capabilities +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) + #include + #else + #include + #endif + ], [ + struct drm_dsc_config *conf = NULL; + conf->simple_422 = true; + ], [ + AC_DEFINE(HAVE_DRM_DSC_CONFIG_SIMPLE_422, 1, + [struct drm_dsc_config has member simple_422]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6831bfd78ece6..3f3dc1cccc4c2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -162,6 +162,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE + AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 31c5e891bd2d151351f54b6a9d72ae2d09895635 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 17:06:15 +0800 Subject: [PATCH 0901/2070] drm/amdkcl: Test whether drm_dsc_pps_payload_pack() is available Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 203 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../amd/dkms/m4/drm_dsc_pps_payload_pack.m4 | 20 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_dsc_helper.h | 18 ++ 7 files changed, 247 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 create mode 100644 include/kcl/kcl_drm_dsc_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f669d870d0ffd..13174dc68bf06 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o - kcl_workqueue.o kcl_cpumask.o + kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c new file mode 100644 index 0000000000000..d54ef86bceaf4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -0,0 +1,203 @@ +/** + * drm_dsc_pps_payload_pack() - Populates the DSC PPS + * + * @pps_payload: + * Bitwise struct for DSC Picture Parameter Set. This is defined + * by &struct drm_dsc_picture_parameter_set + * @dsc_cfg: + * DSC Configuration data filled by driver as defined by + * &struct drm_dsc_config + * + * DSC source device sends a picture parameter set (PPS) containing the + * information required by the sink to decode the compressed frame. Driver + * populates the DSC PPS struct using the DSC configuration parameters in + * the order expected by the DSC Display Sink device. For the DSC, the sink + * device expects the PPS payload in big endian format for fields + * that span more than 1 byte. + */ + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, + const struct drm_dsc_config *dsc_cfg) +{ + int i; + + /* Protect against someone accidentally changing struct size */ + BUILD_BUG_ON(sizeof(*pps_payload) != + DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); + + memset(pps_payload, 0, sizeof(*pps_payload)); + + /* PPS 0 */ + pps_payload->dsc_version = + dsc_cfg->dsc_version_minor | + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; + + /* PPS 1, 2 is 0 */ + + /* PPS 3 */ + pps_payload->pps_3 = + dsc_cfg->line_buf_depth | + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; + + /* PPS 4 */ + pps_payload->pps_4 = + ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT) | + dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 + dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | +#endif + dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | + dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; + + /* PPS 5 */ + pps_payload->bits_per_pixel_low = + (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); + + /* + * The DSC panel expects the PPS packet to have big endian format + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert + * to big endian format. If format is little endian, it will swap + * bytes to convert to Big endian else keep it unchanged. + */ + + /* PPS 6, 7 */ + pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); + + /* PPS 8, 9 */ + pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); + + /* PPS 10, 11 */ + pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); + + /* PPS 12, 13 */ + pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); + + /* PPS 14, 15 */ + pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); + + /* PPS 16 */ + pps_payload->initial_xmit_delay_high = + ((dsc_cfg->initial_xmit_delay & + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 17 */ + pps_payload->initial_xmit_delay_low = + (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); + + /* PPS 18, 19 */ + pps_payload->initial_dec_delay = + cpu_to_be16(dsc_cfg->initial_dec_delay); + + /* PPS 20 is 0 */ + + /* PPS 21 */ + pps_payload->initial_scale_value = + dsc_cfg->initial_scale_value; + + /* PPS 22, 23 */ + pps_payload->scale_increment_interval = + cpu_to_be16(dsc_cfg->scale_increment_interval); + + /* PPS 24 */ + pps_payload->scale_decrement_interval_high = + ((dsc_cfg->scale_decrement_interval & + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 25 */ + pps_payload->scale_decrement_interval_low = + (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); + + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ + + /* PPS 27 */ + pps_payload->first_line_bpg_offset = + dsc_cfg->first_line_bpg_offset; + + /* PPS 28, 29 */ + pps_payload->nfl_bpg_offset = + cpu_to_be16(dsc_cfg->nfl_bpg_offset); + + /* PPS 30, 31 */ + pps_payload->slice_bpg_offset = + cpu_to_be16(dsc_cfg->slice_bpg_offset); + + /* PPS 32, 33 */ + pps_payload->initial_offset = + cpu_to_be16(dsc_cfg->initial_offset); + + /* PPS 34, 35 */ + pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); + + /* PPS 36 */ + pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; + + /* PPS 37 */ + pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; + + /* PPS 38, 39 */ + pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size); + + /* PPS 40 */ + pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + + /* PPS 41 */ + pps_payload->rc_quant_incr_limit0 = + dsc_cfg->rc_quant_incr_limit0; + + /* PPS 42 */ + pps_payload->rc_quant_incr_limit1 = + dsc_cfg->rc_quant_incr_limit1; + + /* PPS 43 */ + pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | + DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; + + /* PPS 44 - 57 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) + pps_payload->rc_buf_thresh[i] = + dsc_cfg->rc_buf_thresh[i]; + + /* PPS 58 - 87 */ + /* + * For DSC sink programming the RC Range parameter fields + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] + */ + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + pps_payload->rc_range_parameters[i] = + cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << + DSC_PPS_RC_RANGE_MINQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_max_qp << + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_bpg_offset)); + } + + /* PPS 88 */ + pps_payload->native_422_420 = dsc_cfg->native_422 | + dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; + + /* PPS 89 */ + pps_payload->second_line_bpg_offset = + dsc_cfg->second_line_bpg_offset; + + /* PPS 90, 91 */ + pps_payload->nsl_bpg_offset = + cpu_to_be16(dsc_cfg->nsl_bpg_offset); + + /* PPS 92, 93 */ + pps_payload->second_line_offset_adj = + cpu_to_be16(dsc_cfg->second_line_offset_adj); + + /* PPS 94 - 127 are O */ +} +EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +#endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ + +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 69ddd2d30b8b8..6529a8a9b6076 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -88,5 +88,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d29b2e98d417b..ab338de5cd7ab 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1186,6 +1186,9 @@ /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + /* drm_edid_get_monitor_name is available*/ #define HAVE_DRM_EDID_GET_MONITOR_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 new file mode 100644 index 0000000000000..624e489e45e3a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) + #include + #else + #include + #endif + ], [ + drm_dsc_pps_payload_pack(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_PPS_PAYLOAD_PACK, 1, + [drm_dsc_pps_payload_pack() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3f3dc1cccc4c2..e5b34cbd00ad8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -163,6 +163,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h new file mode 100644 index 0000000000000..d7b02f62b5ed1 --- /dev/null +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef _KCL_KCL_DRM_DSC_HELPER_H +#define _KCL_KCL_DRM_DSC_HELPER_H + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, + const struct drm_dsc_config *dsc_cfg); +#endif + +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +#endif /* _KCL_KCL_DRM_DSC_HELPER_H */ + From bbf2cc9b87a6d3511a8b5508445e189c4beb1555 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 11:09:19 +0800 Subject: [PATCH 0902/2070] drm/amdkcl: Test whether drm_dsc_compute_rc_parameters() is available Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 134 +++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 6 + .../dkms/m4/drm_dsc_compute_rc_parameters.m4 | 20 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_dsc_helper.h | 4 + 5 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c index d54ef86bceaf4..f5546b4049608 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -15,9 +15,11 @@ * device expects the PPS payload in big endian format for fields * that span more than 1 byte. */ - #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + +#include #include +#include #include #ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK @@ -200,4 +202,134 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, EXPORT_SYMBOL(drm_dsc_pps_payload_pack); #endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } else { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else if (vdsc_cfg->native_422) + num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 3 * (4 * vdsc_cfg->bits_per_component) - 2; + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -ERANGE; + } + + final_scale = (vdsc_cfg->rc_model_size * 8) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset) * + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ab338de5cd7ab..624707df51479 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -502,6 +502,12 @@ /* drm_gem_prime_export() with p,i arg is available */ #define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 +/* drm_drv_uses_atomic_modeset() is available */ +#define HAVE_DRM_DRV_USES_ATOMIC_MODESET 1 + +/* drm_dsc_compute_rc_parameters() is available */ +#define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 + /* drm_edid_to_eld() are available */ /* #undef HAVE_DRM_EDID_TO_ELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 new file mode 100644 index 0000000000000..57d179067d66b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) + #include + #else + #include + #endif + ], [ + drm_dsc_compute_rc_parameters(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS, 1, + [drm_dsc_compute_rc_parameters() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e5b34cbd00ad8..8127073589e1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -164,6 +164,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK + AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h index d7b02f62b5ed1..207bc76eb1195 100644 --- a/include/kcl/kcl_drm_dsc_helper.h +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -13,6 +13,10 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); #endif +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); +#endif + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* _KCL_KCL_DRM_DSC_HELPER_H */ From e745c192cb3011bfeb3064b1e8576c58ed4c3c47 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:00:10 +0800 Subject: [PATCH 0903/2070] drm/amdkcl: adjust macro to fix build error Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 98de078a36a18..527b468f25ed2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12915,6 +12915,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); @@ -12925,6 +12926,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } #endif +#endif #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 41a09c85bfbec..41f410b660b84 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -269,7 +269,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { }; #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) -#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -296,6 +295,7 @@ static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_m return false; } +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) { struct dc_sink *dc_sink = aconnector->dc_sink; From 9772c82eebb26171aabd4169f3c094aefe1c1619 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:00:43 +0800 Subject: [PATCH 0904/2070] drm/amdkcl: remove useless macro wrapper Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Change-Id: Id09116daf768f3e17026e6db0826dbfb7bc179ee --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 527b468f25ed2..8f7c9d898009f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8389,7 +8389,6 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } -#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { @@ -8410,7 +8409,7 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) } return 0; } -#endif + static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) From 38eb7574d03c06a479f5eb7edb6de7fd30497c2d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:54:31 +0800 Subject: [PATCH 0905/2070] drm/amdkcl: fix unused variable warning Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8f7c9d898009f..80eb8dc3cbc47 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12527,7 +12527,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS struct drm_dp_mst_topology_mgr *mgr; +#endif struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; #endif From 3de9797f362f1ff03fdbb13e3329ad5c84b90e26 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 24 Aug 2022 11:35:44 +0800 Subject: [PATCH 0906/2070] drm/amdkcl: Check if drm_buddy.h is exist Signed-off-by: Ma Jun Change-Id: I0981cffaa5da7fcd75273e8adc09051bb966037e --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 624707df51479..4b8bc3f8cea99 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -484,6 +484,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_BUDDY_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_UTIL_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b9977c77c0f81..055736d17b86a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -86,4 +86,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # mm: introduce include/linux/pgtable.h dnl # AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) + + dnl # + dnl # v5.19-rc1- c9cad937c0 + dnl # drm/amdgpu: add drm buddy support to amdgpu + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) ]) From f6fd97b911ef027a30cb3c2263afd493da25dab1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 09:43:28 +0800 Subject: [PATCH 0907/2070] drm/amdkcl: Remove the redundant reference of header file Signed-off-by: Ma Jun Change-Id: I257d7940e5770ce5399d72039ab47328cc3b105b --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 80eb8dc3cbc47..41c693cc8dfca 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -95,7 +95,6 @@ #include #include #include -#include #include #include From c717954e9b258d3fb7458dfa6de7cd558bcc85f7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 10:04:40 +0800 Subject: [PATCH 0908/2070] drm/amdkcl: Test if drm_gem_plane_helper_prepare_fb() is defined Signed-off-by: Ma Jun Change-Id: Ie8eee916043ff4e7a52a256f548d6b89782259bc --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ .../dkms/m4/drm_gem_plane_helper_prepare_fb.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_gem_atomic_helper.h | 9 +++++++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 create mode 100644 include/kcl/header/drm/drm_gem_atomic_helper.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index c9ad578ea9b01..a50f7de6c99cd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -989,9 +989,11 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, goto error_unpin; } +#ifdef HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB r = drm_gem_plane_helper_prepare_fb(plane, new_state); if (unlikely(r != 0)) goto error_unpin; +#endif amdgpu_bo_unreserve(rbo); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4b8bc3f8cea99..787b145629bb6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -548,6 +548,10 @@ /* whether struct drm_framebuffer have format */ #define HAVE_DRM_FRAMEBUFFER_FORMAT 1 + + /* drm_gem_plane_helper_prepare_fb() is available */ + #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 + /* drm_gem_map_attach() wants 2 arguments */ /* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 new file mode 100644 index 0000000000000..e0311f6ebd145 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_plane_helper_prepare_fb(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB, 1, + [drm_gem_plane_helper_prepare_fb() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8127073589e1e..9f883facbf954 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -165,6 +165,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS + AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/drm_gem_atomic_helper.h b/include/kcl/header/drm/drm_gem_atomic_helper.h new file mode 100644 index 0000000000000..ba17f457edc4f --- /dev/null +++ b/include/kcl/header/drm/drm_gem_atomic_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ +#define _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ + +#if defined(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB) +#include_next +#endif + +#endif From 2fbb0667d24c081725d889c46951ca3deda54805 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 19 Jul 2022 21:00:28 -0400 Subject: [PATCH 0909/2070] drm/amdkfd: Add placeholder for deprecated CMA ioctl Implement a dummy ioctl to avoid undefined behaviour. Signed-off-by: Felix Kuehling Change-Id: I0cd535d891c64022d72aa4dc1b724944f558a219 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++++++ include/uapi/linux/kfd_ioctl.h | 21 +++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a42d67f80eccc..f9d9ec61bdc63 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1767,6 +1767,13 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated CMA API */ +static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; +} + /* Handle requests for watching SMI events */ static int kfd_ioctl_smi_events(struct file *filep, struct kfd_process *p, void *data) @@ -3545,6 +3552,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, + kfd_ioctl_cross_memory_copy_deprecated, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index bf6e0832d7cdd..2eb3e7df52820 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -846,6 +846,23 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; +struct kfd_ioctl_cross_memory_copy_deprecated_args { + /* to KFD: Process ID of the remote process */ + __u32 pid; + /* to KFD: See above definition */ + __u32 flags; + /* to KFD: Source GPU VM range */ + __u64 src_mem_range_array; + /* to KFD: Size of above array */ + __u64 src_mem_array_size; + /* to KFD: Destination GPU VM range */ + __u64 dst_mem_range_array; + /* to KFD: Size of above array */ + __u64 dst_mem_array_size; + /* from KFD: Total amount of bytes copied */ + __u64 bytes_copied; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1792,6 +1809,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) + +#define AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED \ + AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_deprecated_args) + #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) From be99139c6e7eba9e18c399dba0f21ecf29db931d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:30:33 +0800 Subject: [PATCH 0910/2070] drm/amdkcl: Wrap the code with macro HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED Mainly fix the build error on legacy os by wrapping the code with macro HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED Signed-off-by: Ma Jun Change-Id: I3f0a1c1e86f82153930eefde88ad3e7d904308e2 --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 325ccf79e6762..c955c3272d25e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -578,6 +578,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, return domain; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static const struct drm_format_info dcc_formats[] = { { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, @@ -670,7 +671,7 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier) /* returning NULL will cause the default format structs to be used. */ return NULL; } - +#endif /* * Tries to extract the renderable DCC offset from the opaque metadata attached diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a50f7de6c99cd..312a4e07e1ea9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -95,10 +95,12 @@ enum dm_micro_swizzle { MICRO_SWIZZLE_R = 3 }; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { return amdgpu_lookup_format_info(pixel_format, modifier); } +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, @@ -1561,6 +1563,7 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct return &dm_plane_state->base; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, uint64_t modifier) @@ -1622,6 +1625,7 @@ static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, return true; } +#endif static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) From bd734f1baa1460a662f3cfcde06e805309b40a48 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 14:29:07 +0800 Subject: [PATCH 0911/2070] drm/amdkcl: Wrap the code with kcl macro Wrap the code with macro HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE to avoid build error on legacy os. Signed-off-by: Ma Jun Change-Id: I761a11a9a270c08295807bb7f3a0bc340e82e416 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 41c693cc8dfca..fe80eaef28ac2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8413,6 +8413,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) struct drm_atomic_state *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -8477,6 +8478,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, drm_dbg_atomic(connector->dev, "failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; } +#endif return 0; } From 023042f9a22c5de3f9a5a259026e725af98dd953 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:46:45 +0800 Subject: [PATCH 0912/2070] drm/amdkcl: Fix the error caused by drm_gem_object->resv Use the amdkcl_ttm_resvp(bo) instead of drm_gem_object->resv Signed-off-by: Ma Jun Change-Id: Iada5d30f196ef81d4ea5148db6d1df84c96d9f90 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 312a4e07e1ea9..e8245edd980f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -966,7 +966,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); goto error_unlock; From 0ef4c6df535086b816f7c40d571bcc91a4e9c5d6 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:44:44 +0800 Subject: [PATCH 0913/2070] drm/amdkcl: Implement the bitmap_to_arr32() Implement the bitmap_to_arr32() for legacy os Signed-off-by: Ma Jun Change-Id: I9802dd45c5ce57a7bd4c83ea12e0c7ad689a83a6 --- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 29 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++--- .../gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_bitmap.h | 4 +++ include/kcl/kcl_bitmap.h | 12 ++++++++ 6 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c index 946b29d66408b..2b0c29936bc96 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -19,9 +19,10 @@ * DEALINGS IN THE SOFTWARE. */ +#include + #ifndef HAVE_BITMAP_FUNCS -#include #include #include #include @@ -46,3 +47,29 @@ void kcl_bitmap_free(const unsigned long *bitmap) EXPORT_SYMBOL(kcl_bitmap_free); #endif /* HAVE_BITMAP_FUNCS */ +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +/** + * kcl_bitmap_to_arr32 - copy the contents of bitmap to a u32 array of bits + * @buf: array of u32 (in host byte order), the dest bitmap + * @bitmap: array of unsigned longs, the source bitmap + * @nbits: number of bits in @bitmap + */ +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, unsigned int nbits) +{ + unsigned int i, halfwords; + + halfwords = DIV_ROUND_UP(nbits, 32); + for (i = 0; i < halfwords; i++) { + buf[i] = (u32) (bitmap[i/2] & UINT_MAX); + if (++i < halfwords) + buf[i] = (u32) (bitmap[i/2] >> 32); + } + + /* Clear tail bits in last element of array beyond nbits. */ + if (nbits % BITS_PER_LONG) + buf[halfwords - 1] &= (u32) (UINT_MAX >> ((-nbits) & 31)); +} +EXPORT_SYMBOL(kcl_bitmap_to_arr32); +#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 787b145629bb6..3af4cf396badb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -52,6 +52,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* bitmap_to_arr32() is available */ +#define HAVE_BITMAP_TO_ARR32 1 + /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 @@ -545,10 +548,6 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 -/* whether struct drm_framebuffer have format */ -#define HAVE_DRM_FRAMEBUFFER_FORMAT 1 - - /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 new file mode 100644 index 0000000000000..3c981e3fa9518 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc1-22-525d6515604e +dnl # drm/amd/pm: use bitmap_{from,to}_arr32 where appropriate +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_TO_ARR32], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_to_arr32(NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_TO_ARR32, 1, + [bitmap_to_arr32() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f883facbf954..3c32e6b8be445 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -166,6 +166,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB + AC_AMDGPU_BITMAP_TO_ARR32 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_bitmap.h b/include/kcl/backport/kcl_bitmap.h index 5871f13aff831..1382530929001 100644 --- a/include/kcl/backport/kcl_bitmap.h +++ b/include/kcl/backport/kcl_bitmap.h @@ -31,4 +31,8 @@ #define bitmap_free kcl_bitmap_free #endif /* HAVE_BITMAP_FUNCS */ +#ifndef HAVE_BITMAP_TO_ARR32 +#define bitmap_to_arr32 kcl_bitmap_to_arr32 +#endif /* HAVE_BITMAP_TO_ARR32 */ + #endif /* KCL_BITMAP_H */ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index f65fa8fbcc56d..f2c0863b7b7d8 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -39,4 +39,16 @@ unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags); void kcl_bitmap_free(const unsigned long *bitmap); #endif /* HAVE_BITMAP_FUNCS */ +/* copy form bitmap.h */ +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, + unsigned int nbits); +#else +#define kcl_bitmap_to_arr32(buf, bitmap, nbits) \ + bitmap_copy_clear_tail((unsigned long *) (buf), \ + (const unsigned long *) (bitmap), (nbits)) +#endif +#endif /* HAVE_BITMAP_TO_ARR32 */ + #endif /* KCL_BITMAP_H */ From e0e21fa8b475fe5efd37bb02c0552785b73402d4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 24 Aug 2022 13:37:09 +0800 Subject: [PATCH 0914/2070] drm/amdkcl: Fix missing execl fence copy in dma_resv_copy_fences() add back dma_resv_iter_is_exclusive() to test current fence is excl fence Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- include/kcl/kcl_dma-resv.h | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index db40a6e5f035a..e6c4b9ef220d1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -584,7 +584,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) } dma_fence_get(f); - if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE) + if (dma_resv_iter_is_exclusive(&cursor)) excl = f; else RCU_INIT_POINTER(list->shared[list->shared_count++], f); diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 39a4e3b5e67f1..4fe1fe0afac9d 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -230,6 +230,17 @@ static inline struct dma_resv_list *dma_resv_shared_list(struct dma_resv *obj) return rcu_dereference_check(obj->fence, lockdep_is_held(&(obj)->lock.base)); } +/** + * dma_resv_iter_is_exclusive - test if the current fence is the exclusive one + * @cursor: the cursor of the current position + * + * Returns true if the currently returned fence is the exclusive one. + */ +static inline bool dma_resv_iter_is_exclusive(struct dma_resv_iter *cursor) +{ + return cursor->index == 0; +} + #endif /* !defined(HAVE_DMA_RESV_FENCES) */ #if !defined(smp_store_mb) From aff79068c86c5022b6daef61e795a26cc3ea7346 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 26 Aug 2022 15:05:52 +0800 Subject: [PATCH 0915/2070] drm/amdkcl: Check if dma_resv->seq is available Check if dma_resv->seq is available for kernel version >= 5.18.0 Signed-off-by: Ma Jun Change-Id: I17151eddb9bf97500d8abd28320505f4026b2291 --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 17 +++++++++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 3b41a6d897f59..4755cde423517 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,7 +12,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) $(error dma_resv->seq is missing., exit...) endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3af4cf396badb..340905d544a66 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -127,6 +127,9 @@ /* dma_resv->seq is seqcount_ww_mutex_t */ /* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ +/* bug for missing dma_resv->seq */ +/* #undef HAVE_DMA_RESV_SEQ_BUG */ + /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 9d11fb99c397a..93c6dbc25ae22 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -36,6 +36,23 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ ], [ AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, [dma_resv->seq is available]) + ],[ + dnl # + dnl # dma_resv->seq is dropped since kernle 5.18.0 + dnl # So trigger the bug only for the kernel_version < 5.18.0 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) + int this_is_bug = 0; + #else + this_is_not_bug(); + #endif + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, + [bug for missing dma_resv->seq]) + ]) ]) ]) ]) From e38dc5c773f69bbe2a214a350d4636018e6a91d1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 16 Aug 2022 17:05:25 +0800 Subject: [PATCH 0916/2070] drm/amdkcl: add buffer cache as available memory [Why] For system cache large amount of file buffer, free memory occupancy calculated from patch "f32b51764601 drm/amdkcl: test for available memory" will smaller than 20% and will hang the dkms install process. [How] consider buffer cache also as available memory Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3c32e6b8be445..90852e62f36fd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -558,8 +558,8 @@ dnl # AC_KERNEL_FREE_MEM dnl # return true if available memory >20% dnl # AC_DEFUN([AC_KERNEL_FREE_MEM], [ - free_mem=$(free -t | awk '/^Total:/ { - printf("%d\n", $[4] / $[2] * 100) + free_mem=$(free -t | awk '/^Mem:/ { BUF_MEM=$[6]} /^Total:/ { TOTAL_MEM=$[2];FREE_MEM=$[4] } END { + printf("%d\n", (BUF_MEM + FREE_MEM) / TOTAL_MEM * 100) }') AS_IF([[[ $free_mem -gt 20 ]]], [ From 7c55ef39148513e822cc1fcd4a6e1feaeab98fc8 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Wed, 24 Aug 2022 22:09:58 +0800 Subject: [PATCH 0917/2070] drm/amdgpu: create p2p links unconditionally in dkms P2P needs to be enabled on old kernels without setting CONFIG_HSA_AMD_P2P, so p2p links needs to be created unconditionally. This also releases build option from upstream. Suggested-by: Ramesh Errabolu Signed-off-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index fab95d1d884a6..cd0d2eb770526 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1579,7 +1579,6 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g return ret; } -#if defined(CONFIG_HSA_AMD_P2P) static int kfd_add_peer_prop(struct kfd_topology_device *kdev, struct kfd_topology_device *peer, int from, int to) { @@ -1647,16 +1646,12 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev, return ret; } -#endif static int kfd_dev_create_p2p_links(void) { struct kfd_topology_device *dev; struct kfd_topology_device *new_dev; -#if defined(CONFIG_HSA_AMD_P2P) - uint32_t i; -#endif - uint32_t k; + uint32_t i, k; int ret = 0; k = 0; @@ -1677,7 +1672,6 @@ static int kfd_dev_create_p2p_links(void) goto out; /* create p2p links */ -#if defined(CONFIG_HSA_AMD_P2P) i = 0; list_for_each_entry(dev, &topology_device_list, list) { if (dev == new_dev) @@ -1699,7 +1693,6 @@ static int kfd_dev_create_p2p_links(void) next: i++; } -#endif out: return ret; From 71b5951ccfc75371e64abee42ede4b0ed74b5d50 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 26 Aug 2022 17:10:21 +0800 Subject: [PATCH 0918/2070] drm/amdkcl: Test whether smca_get_bank_type() has two arguments It's caused by 91f75eb481cfaee5c4ed8fb5214bf2fbfa04bd7b "x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 29 +++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++- .../gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 | 52 +++++++++++++------ include/kcl/kcl_mce.h | 8 ++- 5 files changed, 70 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 8a95c73a6deae..a1b40c9b51aa1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4947,7 +4947,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ - if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && + if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) return NOTIFY_DONE; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c index 30e62d94fbead..bd90d447713f5 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -12,10 +12,19 @@ #ifdef CONFIG_X86_MCE_AMD #include -#ifndef HAVE_SMCA_GET_BANK_TYPE +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(cpu, bank); +} +#elif defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} /* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ -#ifdef HAVE_SMCA_BANK_STRUCT +#elif defined(HAVE_STRUCT_SMCA_BANK) enum smca_bank_types smca_get_bank_type(unsigned int bank) { struct smca_bank *b; @@ -29,14 +38,24 @@ enum smca_bank_types smca_get_bank_type(unsigned int bank) return b->hwid->bank_type; } +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} + #else int smca_get_bank_type(unsigned int bank) { pr_warn_once("smca_get_bank_type is not supported\n"); return 0; } -#endif /* HAVE_SMCA_BANK_STRUCT */ -EXPORT_SYMBOL_GPL(smca_get_bank_type); -#endif /* HAVE_SMCA_GET_BANK_TYPE */ + +int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} + +#endif +EXPORT_SYMBOL_GPL(kcl_smca_get_bank_type); #endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 340905d544a66..517c391f9d3bb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1026,8 +1026,11 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 -/* smca_get_bank_type() is available */ -#define HAVE_SMCA_GET_BANK_TYPE 1 +/* smca_get_bank_type(x) is available */ +/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ + +/* whether smca_get_bank_type(x, x) is available */ +#define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 index 2ed1eef7d5149..4dbfe78524f84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -1,27 +1,49 @@ dnl # -dnl # -dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration dnl # AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([smca_get_bank_type], - [arch/x86/kernel/cpu/mce/amd.c], [ - AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE, 1, - [smca_get_bank_type() is available]) - ], [ - dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + unsigned int a = 0, b = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a, b); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS, 1, + [whether smca_get_bank_type(x, x) is available]) + ],[ dnl # - dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol dnl # AC_KERNEL_TRY_COMPILE([ + #include #include - ], [ - struct smca_bank *b = NULL; - b->id = 0; - ], [ - AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, - [struct smca_bank is available]) + ],[ + unsigned int a = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT, 1, + [smca_get_bank_type(x) is available]) + ],[ + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + ]) ]) + ]) ]) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 80625b60944b7..fd6098c99a240 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,12 +11,10 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#if !defined(HAVE_SMCA_GET_BANK_TYPE) -#ifdef HAVE_SMCA_BANK_STRUCT -enum smca_bank_types smca_get_bank_type(unsigned int bank); +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) || defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); #else -int smca_get_bank_type(unsigned int bank); -#endif +int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); #endif #ifndef HAVE_MCE_PRIO_UC From b72c1f81635ed620166deac4f790d9790ac8579e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 8 Sep 2022 12:37:59 -0400 Subject: [PATCH 0919/2070] drm/amdkcl: limit number of tests to number of CPU Limit the number of tests to be executed in parallel to the number of processors available in the system. Checking for available memory may cause a hang in the infinite loop on the system with small amount of the system memory. Change-Id: Ia7cc2e56d068c642975026c2e1b577128970c563 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 32 ++++++++------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 90852e62f36fd..2645671a3d9ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -553,22 +553,6 @@ AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) ]) -dnl # -dnl # AC_KERNEL_FREE_MEM -dnl # return true if available memory >20% -dnl # -AC_DEFUN([AC_KERNEL_FREE_MEM], [ - free_mem=$(free -t | awk '/^Mem:/ { BUF_MEM=$[6]} /^Total:/ { TOTAL_MEM=$[2];FREE_MEM=$[4] } END { - printf("%d\n", (BUF_MEM + FREE_MEM) / TOTAL_MEM * 100) - }') - - AS_IF([[[ $free_mem -gt 20 ]]], [ - $1 - ], [ - $2 - ]) -]) - dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed @@ -578,14 +562,16 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ AC_KERNEL_TMP_BUILD_DIR([$1]) } - while : + AC_CHECK_PROG(NPROC, nproc, yes) + AS_IF([test x"$NPROC" != x"yes"], [ + ncpu=1 + ], [ + ncpu=$(nproc) + ]) + + while [[ $(jobs | wc -l) -gt $ncpu ]] do - AC_KERNEL_FREE_MEM([rc=0], [rc=1]) - if test $rc -ne 0; then : - sleep 1 - else : - break - fi + sleep 0.1 done do_background & From a94a9933fd73750e5405d339948910cecf6f119e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 12:24:25 +0800 Subject: [PATCH 0920/2070] drm/amdkcl: wrap code under macro HAVE_CHUNK_ID_SYNOBJ_IN_OUT and HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL It's caused by 253c2b45dfa82a18530076bb743f67355948550c "drm/amdgpu: cleanup CS init/fini and pass1" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 9d2ea8e8b26d4..8d4c0ff66b39f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1515,11 +1515,15 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) amdgpu_sync_free(&parser->sync); drm_exec_fini(&parser->exec); +#if defined(HAVE_CHUNK_ID_SYNOBJ_IN_OUT) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) kfree(parser->post_deps[i].chain); +#endif } kfree(parser->post_deps); +#endif dma_fence_put(parser->fence); From 152dbdd3bd74654bc6922eff2bbc89bc573516d4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 15:35:09 +0800 Subject: [PATCH 0921/2070] drm/amdkcl: wrap code under macro HAVE_CHUNK_ID_SYNOBJ_IN_OUT, HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES It's caused by d8ede49db6249fb8d274dde7475e7b33d2ab126c "drm/amdgpu: reorder CS code" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 8d4c0ff66b39f..606104f725648 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -456,7 +456,6 @@ static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p, } return 0; } - static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p, uint32_t handle, u64 point, u64 flags) @@ -540,7 +539,9 @@ static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p, drm_syncobj_find(p->filp, deps[i].handle); if (!p->post_deps[i].syncobj) return -EINVAL; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) p->post_deps[i].chain = NULL; +#endif p->post_deps[i].point = 0; p->num_post_deps++; } @@ -570,14 +571,14 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, for (i = 0; i < num_deps; ++i) { struct amdgpu_cs_post_dep *dep = &p->post_deps[i]; - +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) dep->chain = NULL; if (syncobj_deps[i].point) { dep->chain = dma_fence_chain_alloc(); if (!dep->chain) return -ENOMEM; } - +#endif dep->syncobj = drm_syncobj_find(p->filp, syncobj_deps[i].handle); if (!dep->syncobj) { @@ -590,7 +591,6 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, return 0; } -#endif static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, struct amdgpu_cs_chunk *chunk) @@ -629,7 +629,9 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) return r; break; case AMDGPU_CHUNK_ID_DEPENDENCIES: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif r = amdgpu_cs_p2_dependencies(p, chunk); if (r) return r; @@ -644,6 +646,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk); if (r) @@ -654,6 +657,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: r = amdgpu_cs_p2_shadow(p, chunk); if (r) @@ -1515,7 +1519,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) amdgpu_sync_free(&parser->sync); drm_exec_fini(&parser->exec); -#if defined(HAVE_CHUNK_ID_SYNOBJ_IN_OUT) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); #if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) @@ -1523,7 +1526,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) #endif } kfree(parser->post_deps); -#endif dma_fence_put(parser->fence); From 33dc40be7365c9621e1a9ce6e1aa58674fcd601c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 17:27:20 +0800 Subject: [PATCH 0922/2070] drm/amdkcl: test whether drm_gem_object->resv is available It's caused by 708a6179d00f1d6cc060afcf7b5b6dc4e75d3ed6 "drm/amdgpu: use DMA_RESV_USAGE_BOOKKEEP v2" dd37405b55736ee33410ad653b8c2c9a2b2700c9 "drm/amdgpu: reorder CS code" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 47ad52ad9c5e9..f917c7da407bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1536,7 +1536,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(vm->root.bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), &vm->process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(vm->root.bo); @@ -3474,7 +3474,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * if (mem->bo->tbo.pin_count) continue; - dma_resv_add_fence(mem->bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&mem->bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3483,7 +3483,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * vm_list_node) { struct amdgpu_bo *bo = peer_vm->root.bo; - dma_resv_add_fence(bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3538,7 +3538,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(gws_bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&gws_bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(gws_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 36805dcfa1598..2c0fcd3095e2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -128,7 +128,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, swap(p->vm->last_unlocked, tmp); dma_fence_put(tmp); } else { - dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, + dma_resv_add_fence(amdkcl_ttm_resvp(&p->vm->root.bo->tbo), f, DMA_RESV_USAGE_BOOKKEEP); } From 84a6be466972f19b770f9f097e2472f1d18e22c9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 20 Sep 2022 15:17:48 +0800 Subject: [PATCH 0923/2070] drm/amdkcl: regard DMA_RESV_USAGE_BOOKKEEP usage as read fence for legacy os For legacy os, the new usage DMA_RESV_USAGE_BOOKKEEP is regarded same as DMA_RESV_USAGE_READ Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index e6c4b9ef220d1..1477c6349dad7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -314,7 +314,7 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, unsigned int i; /* Only readers supported for now */ - WARN_ON(usage != DMA_RESV_USAGE_READ); + WARN_ON(usage != DMA_RESV_USAGE_READ && usage != DMA_RESV_USAGE_BOOKKEEP); dma_resv_assert_held(obj); From 048b72a7cc61be1a74d51f4e9e7607c73b251e5a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 15 Sep 2022 14:20:19 +0800 Subject: [PATCH 0924/2070] drm/amdkcl: test whether drm_gem_object->resv is available It's caused by e406606fb782b811b6bfb6f51b5fc9e0c8f5d1bf "drm/amdgpu: SDMA update use unlocked iterator" Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 2c0fcd3095e2c..00878c3524d6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -229,7 +229,7 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, int r; /* Wait for PD/PT moves to be completed */ - dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); + dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); r = drm_sched_job_add_dependency(&p->job->base, fence); From 7fd2442d8363ac9088015fa326f0e56f9139fdfe Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Sep 2022 14:16:27 +0800 Subject: [PATCH 0925/2070] drm/amdkcl: Optimize cancel_work() test Search the __cancel_work() instead of cancel_work() to optimize the cancel_work() test. Suggested-by: Flora Cui Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Reviewed-by: Flora Cui Change-Id: I595e947b5c98bc601b7e173fbd2ceed4ccd9f7f8 --- drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c | 13 +++++++++---- include/kcl/backport/kcl_workqueue_backport.h | 4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c index 461066e047ac3..7c9b248df0e27 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -22,20 +22,25 @@ #include #ifndef HAVE_CANCEL_WORK -bool (*_kcl_cancel_work)(struct work_struct *work); -EXPORT_SYMBOL(_kcl_cancel_work); +static bool (*_kcl_cancel_work)(struct work_struct *work, bool is_dwork); -bool _kcl_cancel_work_stub(struct work_struct *work) +bool _kcl_cancel_work_stub(struct work_struct *work, bool is_dwork) { pr_warn_once("cancel_work function is not supported\n"); return false; } + +bool kcl_cancel_work(struct work_struct *work) +{ + return _kcl_cancel_work(work, false); +} +EXPORT_SYMBOL(kcl_cancel_work); #endif void amdkcl_workqueue_init(void) { #ifndef HAVE_CANCEL_WORK - _kcl_cancel_work = amdkcl_fp_setup("cancel_work", _kcl_cancel_work_stub); + _kcl_cancel_work = amdkcl_fp_setup("__cancel_work", _kcl_cancel_work_stub); #endif /* HAVE_CANCEL_WORK */ } diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h index 3e6adabc0f08c..ac9ffbddd468c 100644 --- a/include/kcl/backport/kcl_workqueue_backport.h +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -6,8 +6,8 @@ #include #ifndef HAVE_CANCEL_WORK -extern bool (*_kcl_cancel_work)(struct work_struct *work); -#define cancel_work _kcl_cancel_work +extern bool kcl_cancel_work(struct work_struct *work); +#define cancel_work kcl_cancel_work #endif #endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From 25dddbb8b93f321f78e5b0cc68ac8a5be4963f3c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 22 Sep 2022 15:48:21 +0800 Subject: [PATCH 0926/2070] drm/amdgpu: [hybrid] revise semaphore object support Due to struct amdgpu_cs_parser change, revise semaphore object support. It's caused by "e89b45235fe6edd94595a3c437beaef0dbf762ca" drm/amdgpu: add gang submit frontend v6 Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 606104f725648..690be407bcb83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -666,7 +666,12 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } - return amdgpu_sem_add_cs(p->ctx, p->entity, &p->job->sync); + for (i = 0; i < p->gang_size; ++i) { + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->jobs[i]->sync); + if (r) + return r; + } + return 0; } /* Convert microseconds to bytes. */ From 88a0dffb150c0eccd0ce8e4e1d1138d15121cf7a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 26 Sep 2022 15:44:12 +0800 Subject: [PATCH 0927/2070] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by ac2e8b34b24ac3966df28d289fc2c03825bc8f1f drm/amd/display: Fix various dynamic ODM transitions on DCN32 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 6fef403ec4a02..a7ecc8a82c196 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1519,6 +1519,7 @@ bool dcn32_dsc_pg_status( return pwr_status == 0; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable) @@ -1541,6 +1542,7 @@ void dcn32_update_dsc_pg(struct dc *dc, } } } +#endif void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index 0303a59536737..644d141cd01e7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -107,9 +107,11 @@ bool dcn32_dsc_pg_status( struct dce_hwseq *hws, unsigned int dsc_inst); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable); +#endif void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 849dae18b7384..f1d777c9ce831 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -115,7 +115,9 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast, .update_phantom_vp_position = dcn32_update_phantom_vp_position, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .update_dsc_pg = dcn32_update_dsc_pg, +#endif .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, From 22dc1544ca33481598bb5bbac4db6557572c0671 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 27 Sep 2022 13:43:38 +0800 Subject: [PATCH 0928/2070] drm/amdkcl: Test whether linux/dma-map-ops.h exist Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/dma-map-ops.h | 11 +++++++++++ 3 files changed, 20 insertions(+) create mode 100644 include/kcl/header/linux/dma-map-ops.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 517c391f9d3bb..e7f72213603d9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -855,6 +855,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_MAP_OPS_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_RESV_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 7240333bce56b..379b6e4e9c766 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -108,4 +108,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # spin loop primitives for busy waiting dnl # AC_KERNEL_CHECK_HEADERS([linux/processor.h]) + + dnl # + dnl # v5.9-rc6-311-g0a0f0d8be76d + dnl # dma-mapping: split + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) ]) diff --git a/include/kcl/header/linux/dma-map-ops.h b/include/kcl/header/linux/dma-map-ops.h new file mode 100644 index 0000000000000..0bda5e05b7eb1 --- /dev/null +++ b/include/kcl/header/linux/dma-map-ops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_MAP_OPS_H_H_ +#define _KCL_HEADER__LINUX_DMA_MAP_OPS_H_H_ + +#if defined(HAVE_LINUX_DMA_MAP_OPS_H) +#include_next +#else +#include +#endif + +#endif From 5116524d078039a4df45a957b88e68f6aca9b0b0 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 30 Sep 2022 17:32:20 -0500 Subject: [PATCH 0929/2070] drm/amdgpu: Query P2PDMA distance only if CONFIG_HSA_AMD_P2P is defined CONFIG_HSA_AMD_P2P indicates the requirements that are needed for P2P DMA Mappings. It is important to note that enabling CONFIG_HSA_AMD_P2P is a necessary but insufficient condition. It is possible to encounter runtime errors - e.g. CPU's do not support Inter-CPU transport of PCIe transaction packets i.e. P2PDMA distance API may return error Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a7fae3071d890..c3f36e92907f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6909,6 +6909,12 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) * Return true if @peer_adev can access (DMA) @adev through the PCIe * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of * @peer_adev. + * + * @note: CONFIG_HSA_AMD_P2P indicates support for P2P DMA mappings. Query + * P2PDMA distance only if the kernel has all the prerequisites for P2P DMA + * support. Otherwise fall back to the less reliable legacy P2P support to + * avoid regressions. + * */ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) @@ -6918,7 +6924,7 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, bool is_large_bar = adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size; -#ifdef CONFIG_PCI_P2PDMA +#ifdef CONFIG_HSA_AMD_P2P p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); From 0fba6748b0a6cdc37d12d5f9affa9fc091148567 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Oct 2022 10:24:53 +0800 Subject: [PATCH 0930/2070] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT and HAVE_DRM_DP_MST_ATOMIC_CHECK It's caused by a7bfbdb0578e89ae380eeffdb2949bd0162e1cb1 "drm/amd/display: Validate DSC After Enable All New CRTCs" 64fbeb725d23878bea621dfddbd3c64a4b0868fe "drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resources" Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fe80eaef28ac2..4743934c7ab56 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12746,12 +12746,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = pre_validate_dsc(state, &dm_state, vars); if (ret != 0) goto fail; } +#endif #endif /* Run this here since we want to validate the streams we created */ From c895bbe67b30c5bf58fcc9659a7a881d996cd620 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 12 Oct 2022 16:29:57 +0800 Subject: [PATCH 0931/2070] drm/amdgpu: [hybrid] fix dgma Signed-off-by: Flora Cui Tested-by: Andy Dong Reviewed-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 176 +----------------------- 2 files changed, 10 insertions(+), 172 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3a594c304cd6c..457d742e3d35a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1192,6 +1192,12 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&cap, 0, sizeof(cap)); if (amdgpu_no_evict) cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + + if (amdgpu_direct_gma_size) { + cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; + cap.direct_gma_size = amdgpu_direct_gma_size; + } + return copy_to_user(out, &cap, min((size_t)size, sizeof(cap))) ? -EFAULT : 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 36fc570bf1328..9a13c36472fa3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -68,11 +68,6 @@ MODULE_IMPORT_NS("DMA_BUF"); #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) -struct amdgpu_dgma_node { - struct ttm_buffer_object *tbo; - struct ttm_range_mgr_node base; -}; - static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); @@ -687,11 +682,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, break; case AMDGPU_PL_DGMA_IMPORT: { - struct amdgpu_dgma_node *node; struct amdgpu_bo *abo; - node = container_of(mem, struct amdgpu_dgma_node, base.base); - abo = ttm_to_amdgpu_bo(node->tbo); + abo = ttm_to_amdgpu_bo(mem->bo); mem->bus.addr = abo->dgma_addr; mem->bus.offset = abo->dgma_import_base; mem->bus.is_iomem = true; @@ -2175,168 +2168,6 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } -static inline struct amdgpu_dgma_import_mgr *to_dgma_import_mgr(struct ttm_resource_manager *man) -{ - return container_of(man, struct amdgpu_dgma_import_mgr, manager); -} - -static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func; -/** - * amdgpu_dgma_import_mgr_init - init DGMA_import manager and DRM MM - * - * @adev: amdgpu_device pointer - * @dgma_size: maximum size of DGMA - * - * Allocate and initialize the DGMA manager. - */ -static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_size) -{ - struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; - struct ttm_resource_manager *man = &mgr->manager; - - man->func = &amdgpu_dgma_import_mgr_func; - - ttm_resource_manager_init(man, &adev->mman.bdev, p_size); - drm_mm_init(&mgr->mm, 0, p_size); - spin_lock_init(&mgr->lock); - atomic64_set(&mgr->available, p_size); - - BUG_ON(AMDGPU_PL_DGMA_IMPORT >= TTM_NUM_MEM_TYPES); - ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); - ttm_resource_manager_set_used(man, true); - return 0; -} - -/** - * amdgpu_dgma_import_mgr_fini - free and destroy DGMA import manager - * - * @adev: amdgpu_device pointer - * - * Destroy and free the DGMA import manager, returns -EBUSY if ranges are still - * allocated inside it. - */ -static void amdgpu_dgma_import_mgr_fini(struct amdgpu_device *adev) -{ - struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; - struct ttm_resource_manager *man = &mgr->manager; - int ret; - - ttm_resource_manager_set_used(man, false); - - ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); - if (ret) - return; - - spin_lock(&mgr->lock); - drm_mm_takedown(&mgr->mm); - spin_unlock(&mgr->lock); - ttm_resource_manager_cleanup(man); - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); -} - -/** - * amdgpu_dgma_import_mgr_new - allocate a new node - * - * @man: TTM memory type manager - * @tbo: TTM BO we need this range for - * @place: placement flags and restrictions - * @mem: the resulting mem object - */ -static int amdgpu_dgma_import_mgr_new(struct ttm_resource_manager *man, - struct ttm_buffer_object *tbo, - const struct ttm_place *place, - struct ttm_resource **res) -{ - struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); - uint32_t num_pages = PFN_UP(tbo->base.size); - struct amdgpu_dgma_node *node; - unsigned long lpfn; - int r; - - spin_lock(&mgr->lock); - if (atomic64_read(&mgr->available) < num_pages) { - spin_unlock(&mgr->lock); - return -ENOSPC; - } - atomic64_sub(num_pages, &mgr->available); - spin_unlock(&mgr->lock); - - lpfn = place->lpfn; - if (!lpfn) - lpfn = man->size; - - node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); - if (!node) { - r = -ENOMEM; - goto err_out; - } - - node->tbo = tbo; - ttm_resource_init(tbo, place, &node->base.base); - - spin_lock(&mgr->lock); - r = drm_mm_insert_node_in_range(&mgr->mm, &node->base.mm_nodes[0], num_pages, - tbo->page_alignment, 0, place->fpfn, - lpfn, DRM_MM_INSERT_BEST); - spin_unlock(&mgr->lock); - - if (unlikely(r)) - goto err_free; - - *res = &node->base.base; - (*res)->start = node->base.mm_nodes[0].start; - - return 0; - -err_free: - kfree(node); - -err_out: - atomic64_add(num_pages, &mgr->available); - - return r; -} - -/** - * amdgpu_dgma_import_mgr_del - free ranges - * - * @man: TTM memory type manager - * @mem: TTM memory object - * - * Free the allocated node. - */ -static void amdgpu_dgma_import_mgr_del(struct ttm_resource_manager *man, - struct ttm_resource *mem) -{ - struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); - struct amdgpu_dgma_node *node = container_of(mem, struct amdgpu_dgma_node, base.base); - - if (node) { - spin_lock(&mgr->lock); - drm_mm_remove_node(&node->base.mm_nodes[0]); - spin_unlock(&mgr->lock); - kfree(node); - } - - atomic64_add(mem->num_pages, &mgr->available); -} - -static void amdgpu_dgma_import_mgr_debug(struct ttm_resource_manager *man, - struct drm_printer *printer) -{ - struct amdgpu_dgma_import_mgr *rman = to_dgma_import_mgr(man); - - spin_lock(&rman->lock); - drm_mm_print(&rman->mm, printer); - spin_unlock(&rman->lock); -} - -static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func = { - .alloc = amdgpu_dgma_import_mgr_new, - .free = amdgpu_dgma_import_mgr_del, - .debug = amdgpu_dgma_import_mgr_debug -}; - static int amdgpu_direct_gma_init(struct amdgpu_device *adev) { struct amdgpu_bo *abo; @@ -2382,7 +2213,8 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) if (unlikely(r)) goto error_put_node; - r = amdgpu_dgma_import_mgr_init(adev, size >> PAGE_SHIFT); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, + false, size >> PAGE_SHIFT); if (unlikely(r)) goto error_release_mm; @@ -2411,8 +2243,8 @@ static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) if (amdgpu_direct_gma_size == 0) return; + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); - amdgpu_dgma_import_mgr_fini(adev); r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); if (r == 0) { From ce88a3c9cf682c749cb3d172db149e50e4be2e5f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Oct 2022 16:25:34 +0800 Subject: [PATCH 0932/2070] drm/amdkcl: fix uninitialized bo_dev variable When bo is NULL pointer, the bo_dev variable will be used uninitialized. This is caused by 292718775885 "drm/amdkcl: fix pytorch test memory page fault" v5.18-2828-g292718775885 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 20a53a4627f81..d722067b1412b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1289,7 +1289,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t flags; bool uncached; int r; - struct amdgpu_device *bo_adev; + struct amdgpu_device *bo_adev = adev; amdgpu_sync_create(&sync); if (clear) { From bfd15beac5110a055387ae02be9acc54f3d0db08 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 31 Oct 2022 19:27:32 +0800 Subject: [PATCH 0933/2070] drm/amdkcl: test register_shrinker whether has two arguments Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/register_shrinker.m4 | 19 +++++++++++++++++++ include/kcl/kcl_shrinker.h | 10 ++++++++++ 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e7f72213603d9..2eeea91fa5a70 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1008,6 +1008,9 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* whether register_shrinker(x, x) is available */ +#define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 + /* remove_conflicting_pci_framebuffers() is available */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2645671a3d9ab..1dace00ed1172 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -167,6 +167,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 + AC_AMDGPU_REGISTER_SHRINKER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 new file mode 100644 index 0000000000000..903f100bf18bd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration +dnl # +AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ],[ + struct shrinker *a = NULL; + const char *b = NULL; + register_shrinker(a, b); + ],[ + AC_DEFINE(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS, 1, + [whether register_shrinker(x, x) is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index d8704a749d2dd..c237de4b867cf 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -7,4 +7,14 @@ extern void synchronize_shrinkers(void); #endif +static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker, + const char *fmt, ...) +{ +#if defined(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS) + return register_shrinker(shrinker, fmt); +#else + return register_shrinker(shrinker); +#endif +} + #endif From 0bb8671e6659f50dd0d055ea8388688751f378da Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 12 Aug 2022 16:10:19 +0800 Subject: [PATCH 0934/2070] drm/amdkcl: test whether struct drm_dp_mst_port has member passthrough_aux It's caused by 0087990a9f572c6dd9533c973fe1072458f54b7a "drm/amd/display: consider DSC pass-through during mode validation" 99d08a5d1ad7fb76b33aabae46cd88bc7e6e6df4 "drm/amd/display: implement DSC pass-through support" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 16 ++++++++++--- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 81d5ae267aefb..140aa454fbe0f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -840,16 +840,20 @@ bool dm_helpers_dp_write_dsc_enable( const struct dc_stream_state *stream, bool enable) { + struct amdgpu_dm_connector *aconnector = + (struct amdgpu_dm_connector *)stream->dm_stream_context; + struct drm_device *dev = aconnector->base.dev; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) static const uint8_t DSC_DISABLE; static const uint8_t DSC_DECODING = 0x01; static const uint8_t DSC_PASSTHROUGH = 0x02; - struct amdgpu_dm_connector *aconnector = - (struct amdgpu_dm_connector *)stream->dm_stream_context; - struct drm_device *dev = aconnector->base.dev; struct drm_dp_mst_port *port; uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; +#else + uint8_t enable_dsc = enable ? 1 : 0; +#endif uint8_t ret = 0; if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { @@ -862,6 +866,7 @@ bool dm_helpers_dp_write_dsc_enable( return write_dsc_enable_synaptics_non_virtual_dpcd_mst( aconnector->dsc_aux, stream, enable_dsc); +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) port = aconnector->mst_output_port; if (enable) { @@ -899,6 +904,11 @@ bool dm_helpers_dp_write_dsc_enable( ret); } } +#else + ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); + DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); +#endif + } if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 41f410b660b84..a900a2fca9fcc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2095,6 +2095,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } + #endif return DC_OK; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2eeea91fa5a70..b632ddea183e0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -393,6 +393,9 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* struct drm_dp_mst_port has passthrough_aux member */ +/* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ + /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 new file mode 100644 index 0000000000000..a1f26ca53e149 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v5.18-2579-g3af4b1f1d6e7 +dnl # "drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_port *dp_mst_port = NULL; + dp_mst_port->passthrough_aux = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX, 1, + [struct drm_dp_mst_port has passthrough_aux member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1dace00ed1172..58d1cf5780a20 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -168,6 +168,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 8ce9295443978bf53c99604ad4596353211b55ae Mon Sep 17 00:00:00 2001 From: Bob zhou Date: Fri, 28 Oct 2022 16:36:06 +0800 Subject: [PATCH 0935/2070] drm/amdkcl: test whether display_info->max_dsc_bpp is available It's caused by cb4f0334768bb60ff144dd8ec1cd212dc09dcf6d "Revert "drm/amd/display: Limit max DSC target bpp for specific monitors"" affba10c1048d56a146cbb6b4ae13d0bf644a7b5 "drm/amd/display: use max_dsc_bpp in amdgpu_dm" Signed-off-by: Bob zhou Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 +- .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 19 +++++++++ 5 files changed, 71 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4743934c7ab56..9eaad60ed1710 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7147,8 +7147,15 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, struct dc *dc = sink->ctx->dc; u32 max_supported_bw_in_kbps, timing_bw_in_kbps; u32 dsc_max_supported_bw_in_kbps; +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP u32 max_dsc_target_bpp_limit_override = drm_connector->display_info.max_dsc_bpp; +#else + u32 max_dsc_target_bpp_limit_override = 0; + if (stream->link && stream->link->local_sink) + max_dsc_target_bpp_limit_override = + stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit; +#endif struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(dc, &dsc_options); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 140aa454fbe0f..13c1adce3f4ae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -49,6 +49,41 @@ #include "ddc_service_types.h" #include "clk_mgr.h" +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP +struct monitor_patch_info { + unsigned int manufacturer_id; + unsigned int product_id; + void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param); + unsigned int patch_param; +}; +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param); + +static const struct monitor_patch_info monitor_patch_table[] = { +{0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15}, +{0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15}, +}; + +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param) +{ + if (edid_caps) + edid_caps->panel_patch.max_dsc_target_bpp_limit = param; +} + +static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++) + if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id) + && (edid_caps->product_id == monitor_patch_table[i].product_id)) { + monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param); + ret++; + } + + return ret; +} +#endif + static u32 edid_extract_panel_id(struct edid *edid) { return (u32)edid->mfg_id[0] << 24 | @@ -178,6 +213,10 @@ enum dc_edid_status dm_helpers_parse_edid_caps( kfree(sads); kfree(sadb); +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP + amdgpu_dm_patch_edid_caps(edid_caps); +#endif + return result; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a900a2fca9fcc..1fddb84a73468 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1084,7 +1084,11 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); dc_dsc_compute_config( diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b632ddea183e0..9b752738df567 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -345,8 +345,8 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 -/* display_info->is_hdmi is available */ -#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 +/* display_info->max_dsc_bpp is available */ +/* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 2cdb134bfa734..987e9979b30d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -36,7 +36,26 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ ]) ]) +dnl # +dnl # commit v5.18-3347-g721ed0ae5acf +dnl # drm/edid: add a quirk for two LG monitors to get them to work on 10bpc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->max_dsc_bpp=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP, 1, + [display_info->max_dsc_bpp is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE + AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP ]) From ab4cf431407c1ee8789978bee75a4817ceee7eae Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:46:45 +0800 Subject: [PATCH 0936/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP It's caused by 13ba1f22181d90f4d62f9103351581b94d2442b2 "drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Wayne Lin --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 1fddb84a73468..4cdae3dfb29d7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1974,6 +1974,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( { #if defined(CONFIG_DRM_AMD_DC_FP) int branch_max_throughput_mps = 0; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) && defined(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP) struct dc_link_settings cur_link_settings; uint32_t end_to_end_bw_in_kbps = 0; uint32_t root_link_bw_in_kbps = 0; @@ -2099,7 +2100,41 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } +#else + int pbn; + /* Check if mode could be supported within max slot + * number of current mst link and full_pbn of mst links. + */ + int pbn_div, slot_num, max_slot_num; + enum dc_link_encoding_format link_encoding; + uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( + &stream->timing, + dc_link_get_highest_encoding_format(stream->link)); + + pbn = kbps_to_peak_pbn(stream_kbps); + pbn_div = dm_mst_get_pbn_divider(stream->link); + slot_num = DIV_ROUND_UP(pbn, pbn_div); + + link_encoding = dc_link_get_highest_encoding_format(stream->link); + if (link_encoding == DC_LINK_ENCODING_DP_8b_10b) + max_slot_num = 63; + else if (link_encoding == DC_LINK_ENCODING_DP_128b_132b) + max_slot_num = 64; + else { + DRM_DEBUG_DRIVER("Invalid link encoding format\n"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } + if (slot_num > max_slot_num || +#ifdef HAVE_DRM_DP_MST_PORT_FULL_PBN + pbn > aconnector->mst_output_port->full_pbn) { +#else + pbn > aconnector->mst_output_port->available_pbn) { +#endif + DRM_DEBUG_DRIVER("Mode can not be supported within mst links!"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } +#endif #endif return DC_OK; } From 8798ebb0a577938dfddbe494c23a79fd4fc12915 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 10:34:23 +0800 Subject: [PATCH 0937/2070] drm/amdkcl: Test whether struct drm_dp_mst_port has full_pbn member Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9b752738df567..2c5ceb00d4b18 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -396,6 +396,9 @@ /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 new file mode 100644 index 0000000000000..dc2ce8bd06835 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v5.6-rc5-4-gfcf463807596 +dnl # drm/dp_mst: Use full_pbn instead of available_pbn for bandwidth checks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_port *mst_port = NULL; + mst_port->full_pbn = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_FULL_PBN, 1, + [drm_dp_mst_port struct has full_pbn member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 58d1cf5780a20..94aecb5ec6fda 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -169,6 +169,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX + AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 8b34b8e40d55ad9a9444c45186028c72dd78f562 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 20 Oct 2022 14:06:45 +0800 Subject: [PATCH 0938/2070] drm/amdkcl: fake kmap_local_* It's caused by f7e8a8be4361c6cba23fd5df693a830e8351402c "drm/amd/amdgpu: Replace kmap() with kmap_local_page()" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6529a8a9b6076..84b24e7384955 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -89,5 +89,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ From dc4a121a8bbfd0cd30110d9eb205545c1114ecda Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 26 Oct 2022 14:31:13 +0800 Subject: [PATCH 0939/2070] drm/amdkcl: wrap code under macro HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED It's caused by 7a462295e26244d5d21d101b9d8b33cd327e95f1 "drm/amdgpu: set fb_modifiers_not_supported in vkms" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 5ecc9892fd657..322f0b0794919 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -658,7 +658,9 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) From b63792303ee8bbb1d9f4ba04ab6f701619b14f39 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 26 Oct 2022 15:31:13 +0800 Subject: [PATCH 0940/2070] drm/amdkcl: Modify CONFIG_DRM_AMD_DC_DSC_SUPPORT enable condition According to the Kconfig file, the CONFIG_DRM_AMD_DC_DSC_SUPPORT is selected by CONFIG_DRM_AMD_DC_DCN. So, we should enable them together. Or else, there maybe are compile errors on phantoms or the arm64 platform Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ia2e3f15195cf01f7521a8c0c50553484c155e842 --- drivers/gpu/drm/amd/dkms/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4755cde423517..f7fa3166cdb33 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -188,11 +188,11 @@ ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN -endif -endif export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT +endif +endif export CONFIG_DRM_TTM_HELPER=m subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER From 0f295bcb88c11244136bd4fc9d68491372725072 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 26 Oct 2022 12:27:04 +0800 Subject: [PATCH 0941/2070] drm/amdkcl: join multiple exclusive fences instead of overwriting old fence If old exclusive fence is not signaled, use dma_fence_chain to join old and new fence together. Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 1477c6349dad7..67f67bcd4e2b4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -34,6 +34,7 @@ */ #include #include +#include #include #include #include @@ -353,9 +354,21 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) { struct dma_fence *old_fence = dma_resv_excl_fence(obj); + struct dma_fence_chain *chain; dma_resv_assert_held(obj); + if (old_fence && !dma_fence_is_signaled(old_fence)) { + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) + pr_err("dma_resv_add_excl_fence OOM\n"); + else { + dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); + fence = &chain->base; + } + } + dma_fence_get(fence); write_seqcount_begin(&obj->seq); From d975963c46ab284732f01d98dab1807b20e66b5e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 27 Oct 2022 17:14:12 +0800 Subject: [PATCH 0942/2070] drm/amdkcl: Add drm buddy Add drm_buddy.c as a new module Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I945c93d973c6bb9e6a401acce79789c80b58a2da --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 4 ++++ drivers/gpu/drm/amd/dkms/sources | 2 ++ 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 6cc9587ebc525..20534a90dbb86 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_buddy.c" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f7fa3166cdb33..eec0d7868d7c2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -202,4 +202,10 @@ CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ amddrm_ttm_helper-y := drm_gem_ttm_helper.o obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o +export CONFIG_DRM_BUDDY=m +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o + obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index a4fde02caa219..caa34f979ef96 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -26,6 +26,10 @@ BUILT_MODULE_NAME[4]="amddrm_ttm_helper" BUILT_MODULE_LOCATION[4]="." DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" +BUILT_MODULE_NAME[5]="amddrm_buddy" +BUILT_MODULE_LOCATION[5]="." +DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" + MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 60563cf6abf8e..373b38d0d2325 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -31,3 +31,5 @@ include/kcl/reservation.h include/linux/ include/uapi/linux/kfd_sysfs.h include/uapi/linux/ drivers/gpu/drm/drm_gem_ttm_helper.c . include/drm/drm_gem_ttm_helper.h include/drm/ +drivers/gpu/drm/drm_buddy.c . +include/drm/drm_buddy.h include/drm/ From 91464bc5e167f8cf55325e0613a4f7959d4a5274 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 8 Nov 2022 12:59:15 +0800 Subject: [PATCH 0943/2070] drm/amdkcl: Fix reference counting error of dma_fence_chain that causing memory leak In the code path of creating a new dma_fence_chain object, the dma_fence_chain_init() function has initialized the reference count. The additional incorrect dma_fence_get(fence) call will increase the reference count from 1 to 2. This will lead to memory leak of dma_fence_chain objects. This fix patch "be5685d2b0f9 drm/amdkcl: join multiple exclusive fences instead of overwriting old fence" Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 67f67bcd4e2b4..8edf3fccac3e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -367,9 +367,10 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); fence = &chain->base; } + } else { + dma_fence_get(fence); } - dma_fence_get(fence); write_seqcount_begin(&obj->seq); /* write_seqcount_begin provides the necessary memory barrier */ From 96eb53d604624e3980d3d460fac42f3b2e3693bc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 8 Nov 2022 14:41:20 +0800 Subject: [PATCH 0944/2070] drm/amdkcl: Wrap the code under macro CONFIG_DRM_AMD_DC_DCN Wrap the code under macro CONFIG_DRM_AMD_DC_DCN to fix the compile error. Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: I3488aa2fe6d706f69e8741e1cb908cdda0e02bf4 --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 0b7c25953308f..1db97b9cf6208 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1433,10 +1433,12 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ +#ifdef CONFIG_DRM_AMD_DC_DCN if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); } +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 2cda3517e7caf..72b1d85ca0a2f 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -307,7 +307,9 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, +#ifdef CONFIG_DRM_AMD_DC_DCN .disable_phantom_crtc = optc32_disable_phantom_otg, +#endif /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = optc1_is_counter_moving, .get_position = optc1_get_position, From bf0d4f8ce3c5539dc63376d7a252aad03ff3a553 Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Tue, 15 Nov 2022 17:50:11 -0500 Subject: [PATCH 0945/2070] drm/amdkcl/dkms: Disable weak module updates This is not supported on some OS, such as RHEL and Fedora, so we should disable it since it's harmless to disable for all OS. Signed-off-by: Jeremy Newton Reviewed-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index caa34f979ef96..bf06588ea6b9c 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,6 +2,8 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" +# not all OS supports weak module updates +NO_WEAK_MODULES="yes" # not work with RHEL DKMS #MODULES_CONF[0]="blacklist radeon" From effbd3c8b947025d3cc6092799c0d39cc1254351 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 29 Aug 2022 22:28:18 -0400 Subject: [PATCH 0946/2070] drm/amdkfd: disable cooperative launch in gfx11 debug mode Since SA1 must be disabled during GFX11 debug mode, cooperative launch may shader hang on an indefinite barrier wait due to assymetrically enabled SEs. Prevent the debugger from attaching to a GWS using process or having the attached process create GWS using queues. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 610702f70c124..3ffd214b973ef 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -603,7 +603,9 @@ static int kfd_gws_init(struct kfd_node *node) (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) && kfd->mec2_fw_version < 0x1b6) || (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) - && kfd->mec2_fw_version < 0x30)) + && kfd->mec2_fw_version < 0x30) || + (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && + KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) kfd->gws_debug_workaround = true; return ret; From d60ac1ecfdefd13126582784fb09286de6e11d77 Mon Sep 17 00:00:00 2001 From: Bob zhou Date: Mon, 14 Nov 2022 15:34:16 +0800 Subject: [PATCH 0947/2070] drm/amdkcl: Test whether drm_mode_init() is available Signed-off-by: Bob zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_modes.h | 4 ++++ 5 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c index bf57f999e4fc2..e01b01bd4ae09 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -39,3 +39,15 @@ amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, const struct drm_display_info *display, const struct drm_display_mode *mode) #endif + +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) +{ + struct list_head head = dst->head; + + memset(dst, 0, sizeof(*dst)); + *dst = *src; + dst->head = head; +} +EXPORT_SYMBOL(drm_mode_init); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2c5ceb00d4b18..1fa50f3f50403 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -638,8 +638,8 @@ /* drm_mode_is_420_xxx() is available */ #define HAVE_DRM_MODE_IS_420_XXX 1 -/* enum drm_mode_subconnector is available */ -/* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ +/* drm_mode_init() is available */ +#define HAVE_DRM_MODE_INTT 1 /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 new file mode 100644 index 0000000000000..9a220e320f721 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.17-rc2-403-g2d3eec897033 +dnl # drm: Add drm_mode_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_init(NULL, NULL); + ], [drm_mode_init], [drivers/gpu/drm/drm_modes.c], [ + AC_DEFINE(HAVE_DRM_MODE_INIT, 1, + [drm_mode_init() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 94aecb5ec6fda..9561f682f7792 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -77,6 +77,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX + AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index c47d691ca6e7a..efd58502aad15 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -36,4 +36,8 @@ bool drm_mode_is_420_also(const struct drm_display_info *display, const struct drm_display_mode *mode); #endif +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); +#endif + #endif From ce1d0c0444da06e082a6ea270e235d3d8fdb7d3a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 19:35:54 +0800 Subject: [PATCH 0948/2070] drm/amdkcl: Check if DECLARE_DYNDBG_CLASSMAP is defined Check if DECLARE_DYNDBG_CLASSMAP is defined. This macro definition is introduced in dyndbg: add DECLARE_DYNDBG_CLASSMAP macro Signed-off-by: Ma Jun Change-Id: I4877b8610c0134b96183697a047eeae3d4ffe4da --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_dynamic_debug.h | 64 +++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/kcl/kcl_dynamic_debug.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 84b24e7384955..12da3154c86ec 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -90,4 +90,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_dynamic_debug.h b/include/kcl/kcl_dynamic_debug.h new file mode 100644 index 0000000000000..6c6f7296eba94 --- /dev/null +++ b/include/kcl/kcl_dynamic_debug.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMDKCL_DYNAMIC_DEBUG_H +#define AMDKCL_DYNAMIC_DEBUG_H + +#ifndef DECLARE_DYNDBG_CLASSMAP +enum class_map_type { + DD_CLASS_TYPE_DISJOINT_BITS, + /** + * DD_CLASS_TYPE_DISJOINT_BITS: classes are independent, one per bit. + * expecting hex input. Built for drm.debug, basis for other types. + */ + DD_CLASS_TYPE_LEVEL_NUM, + /** + * DD_CLASS_TYPE_LEVEL_NUM: input is numeric level, 0-N. + * N turns on just bits N-1 .. 0, so N=0 turns all bits off. + */ + DD_CLASS_TYPE_DISJOINT_NAMES, + /** + * DD_CLASS_TYPE_DISJOINT_NAMES: input is a CSV of [+-]CLASS_NAMES, + * classes are independent, like _DISJOINT_BITS. + */ + DD_CLASS_TYPE_LEVEL_NAMES, + /** + * DD_CLASS_TYPE_LEVEL_NAMES: input is a CSV of [+-]CLASS_NAMES, + * intended for names like: INFO,DEBUG,TRACE, with a module prefix + * avoid EMERG,ALERT,CRIT,ERR,WARNING: they're not debug + */ +}; + +struct ddebug_class_map { + struct list_head link; + struct module *mod; + const char *mod_name; /* needed for builtins */ + const char **class_names; + const int length; + const int base; /* index of 1st .class_id, allows split/shared space */ + enum class_map_type map_type; +}; + +/** + * DECLARE_DYNDBG_CLASSMAP - declare classnames known by a module + * @_var: a struct ddebug_class_map, passed to module_param_cb + * @_type: enum class_map_type, chooses bits/verbose, numeric/symbolic + * @_base: offset of 1st class-name. splits .class_id space + * @classes: class-names used to control class'd prdbgs + */ +#define DECLARE_DYNDBG_CLASSMAP(_var, _maptype, _base, ...) \ + static const char *_var##_classnames[] = { __VA_ARGS__ }; \ + static struct ddebug_class_map __aligned(8) __used \ + __section("__dyndbg_classes") _var = { \ + .mod = THIS_MODULE, \ + .mod_name = KBUILD_MODNAME, \ + .base = _base, \ + .map_type = _maptype, \ + .length = NUM_TYPE_ARGS(char*, __VA_ARGS__), \ + .class_names = _var##_classnames, \ + } +#define NUM_TYPE_ARGS(eltype, ...) \ + (sizeof((eltype[]){__VA_ARGS__}) / sizeof(eltype)) + +#endif + +#endif /* AMDKCL_DYNAMIC_DEBUG_H */ From c867e360b0bac54447a79fc84bf65a919707a690 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:12:05 +0800 Subject: [PATCH 0949/2070] drm/amdkcl: Check if acpi_video_backlight_use_native() is implemented check if acpi_video_backlight_use_native is implemented Signed-off-by: Ma Jun Change-Id: I3c1fd6875436808205d7f6e6dbcf7d59a4722d3a --- .../gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index df7fe6c474ca9..046c0d011ceed 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -186,10 +186,12 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) goto register_acpi_backlight; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(dev, "Skipping amdgpu atom DIG backlight registration\n"); goto register_acpi_backlight; } +#endif pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL); if (!pdata) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1fa50f3f50403..07f0e04e7a6c1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -15,6 +15,9 @@ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + +/* acpi_video_backlight_use_native() is available */ +#define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 new file mode 100644 index 0000000000000..69f2cc28f537c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit: v6.1-rc1-17-da11ef832972 +dnl # drm/amdgpu: Don't register backlight when another +dnl # backlight should be used (v3) + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_backlight_use_native(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE, 1, + [acpi_video_backlight_use_native() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ + AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9561f682f7792..a1d560db7022b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -171,6 +171,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN + AC_AMDGPU_ACPI_VIDEO_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 4bca86a9169875fd255d74058e582e5cedb0bf6f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:28:02 +0800 Subject: [PATCH 0950/2070] drm/amdkcl: check if acpi_video_register_backlight() is implemented check if acpi_video_register_backlight() is implemented Signed-off-by: Ma Jun Change-Id: I3e3930f01cf382a84fe2c0366b865c75d34febe6 --- .../gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ .../gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 046c0d011ceed..2bd00a0b27b3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -230,7 +230,9 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode register_acpi_backlight: /* Try registering an ACPI video backlight device instead. */ +#ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#endif } void diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 07f0e04e7a6c1..bb6fcc402fa52 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -19,6 +19,10 @@ /* acpi_video_backlight_use_native() is available */ #define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 + +/* acpi_video_register_backlight() is available */ +#define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 index 69f2cc28f537c..d2a957a3c28a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -16,7 +16,26 @@ AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ ]) ]) +dnl # +dnl # commit: v6.1-rc1-161-c0f50c5de93b +dnl # drm/amdgpu: Register ACPI video backlight when +dnl # skipping amdgpu backlight registration + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_register_backlight(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT, 1, + [acpi_video_register_backlight() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE + AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT ]) From 7a2491ceee37fc1f0a769f7842a02aeb2c883e5c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 10:49:51 +0800 Subject: [PATCH 0951/2070] drm/amdkcl: Check if DRM_PLANE_NO_SCALING is defined Check if DRM_PLANE_NO_SCALING is defined Signed-off-by: Ma Jun Change-Id: Iaa3041b8bf4765b992f57837bf8c7e69cf34a3f1 Signed-off-by: Asher Song --- include/kcl/kcl_drm_atomic_helper.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 208a5e9edf330..7bedeace08ad0 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -34,6 +34,11 @@ #include #include +/* drm/atomic-helper: Remove _HELPER_ infix from DRM_PLANE_HELPER_NO_SCALING */ +#ifndef DRM_PLANE_NO_SCALING +#define DRM_PLANE_NO_SCALING (1<<16) +#endif + /* * v4.19-rc1-206-ge267364a6e1b * drm/atomic: Initialise planes with opaque alpha values From dfcc9a798464e89c6715c11ace2e1e95734b9191 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:47:11 +0800 Subject: [PATCH 0952/2070] drm/amdkcl: Remove redundant macro DRM_UT_STATE This macro is defined in enum class_map_type now. Signed-off-by: Ma Jun Change-Id: Iadbbab2a0abafb3a83b918537a56296e083a2f20 --- include/kcl/kcl_drm_print.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index bba9e048cf699..80d51e8721236 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -125,10 +125,6 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ -#if !defined(DRM_UT_STATE) -#define DRM_UT_STATE 0x40 -#endif - #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From 3b0c95b915c64208ccac13efa9ec8d69590bd1e1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:49:42 +0800 Subject: [PATCH 0953/2070] drm/amdkcl: Wrap code under HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE Signed-off-by: Ma Jun Change-Id: Ia7819db796197c1c00ccfd848dfc8b84372e32b0 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9eaad60ed1710..9949ca9174754 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5259,12 +5259,14 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) if (aconnector->bl_idx == -1) return; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(drm, "Skipping amdgpu DM backlight registration\n"); /* Try registering an ACPI video backlight device instead. */ acpi_video_register_backlight(); return; } +#endif caps = &dm->backlight_caps[aconnector->bl_idx]; if (get_brightness_range(caps, &min, &max)) { From d98e41ecd6cc6a62e3df0047f1d77c5d46f99c02 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 09:57:18 +0800 Subject: [PATCH 0954/2070] drm/amdkcl: Check if drm_plane_helper_destroy() is implemented Check if drm_plane_helper_destroy is implemented Signed-off-by: Ma Jun Change-Id: Iaed7658f55768048ea9534aaeed12dd4cba70e8a --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-plane-helper-funcs.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_plane_helper.h | 15 +++++++++++++ 5 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 create mode 100644 include/kcl/kcl_drm_plane_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 12da3154c86ec..d1d1b6560ee39 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -91,4 +91,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bb6fcc402fa52..004c9939c00bf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -657,6 +657,9 @@ /* drm_plane_helper_check_state is available */ /* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ +/* drm_plane_helper_destroy() is available */ +/* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ + /* drm_plane_mask is available */ #define HAVE_DRM_PLANE_MASK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 new file mode 100644 index 0000000000000..e4a2a7d627810 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit: v6.1-rc1-27-30c637151cfa +dnl # drm/plane-helper: Export individual helpers +dnl # + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_DESTROY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_plane_helper_destroy(NULL); + ], [ + AC_DEFINE(HAVE_DRM_PLANE_HELPER_DESTROY, 1, + [drm_plane_helper_destroy() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_DRM_PLANE_HELPER_DESTROY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a1d560db7022b..3f4bee16d85aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -172,6 +172,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS + AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_plane_helper.h b/include/kcl/kcl_drm_plane_helper.h new file mode 100644 index 0000000000000..d1bc40bcebb4d --- /dev/null +++ b/include/kcl/kcl_drm_plane_helper.h @@ -0,0 +1,15 @@ +#ifndef AMDKCL_DRM_PLANE_HELPER_H +#define AMDKCL_DRM_PLANE_HELPER_H + +#include + +#ifndef HAVE_DRM_PLANE_HELPER_DESTROY +static void kcl_drm_plane_helper_destroy(struct drm_plane *plane) +{ + drm_plane_cleanup(plane); + kfree(plane); +} + +#define drm_plane_helper_destroy kcl_drm_plane_helper_destroy +#endif +#endif \ No newline at end of file From e3606f32909ed0487b859443f215ea6d13b64149 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 10:11:25 +0800 Subject: [PATCH 0955/2070] drm/amdkcl: Check if display_info->luminance_range is defined check if display_info->luminance_range is defined Signed-off-by: Ma Jun Change-Id: I39fab65c8347df82fd857b6aa8a45bd50002244b --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9949ca9174754..846a7d4c6b70a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3783,7 +3783,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) struct amdgpu_dm_backlight_caps *caps; struct drm_connector *conn_base; struct amdgpu_device *adev; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE struct drm_luminance_range_info *luminance_range; +#endif struct drm_device *drm; if (aconnector->bl_idx == -1 || @@ -3813,6 +3815,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) if (caps->aux_support) aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE luminance_range = &conn_base->display_info.luminance_range; if (luminance_range->max_luminance) @@ -3824,6 +3827,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_min_input_signal = luminance_range->min_luminance; else caps->aux_min_input_signal = 1; +#endif panel_backlight_quirk = drm_get_panel_backlight_quirk(aconnector->drm_edid); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 004c9939c00bf..fb2d3b5baeaa5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -352,6 +352,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->luminance_range is available */ +/* #undef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE */ + /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 987e9979b30d4..d744dcc9b127a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -54,8 +54,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a61bb3422e8d +dnl # drm/amdgpu_dm: Rely on split out luminance calculation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->luminance_range=NULL; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, + [display_info->luminance_range is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP + AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE ]) From fc5d272dd0ed182536ce93348625c883e3d1dd6e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 11:09:31 +0800 Subject: [PATCH 0956/2070] drm/amdkcl: Rename the drm-dp-atomic-find-vcpi-slots.m4 Rename drm-dp-atomic-find-vcpi-slots.m4 to drm-dp-atomic-funcs.m4 for better compatability Signed-off-by: Ma Jun Change-Id: I1bda63ad4526270fd0850801a10d969a621946fd --- ...rm-dp-atomic-find-vcpi-slots.m4 => drm-dp-atomic-funcs.m4} | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) rename drivers/gpu/drm/amd/dkms/m4/{drm-dp-atomic-find-vcpi-slots.m4 => drm-dp-atomic-funcs.m4} (94%) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 similarity index 94% rename from drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 rename to drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 10cfe8e436f12..336e89b2a2874 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -43,3 +43,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) ]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3f4bee16d85aa..7e5e3e3323572 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -52,7 +52,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE - AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FUNCS AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME From 9249f17ce40d253eca9e0364ee05379e12583c33 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 11:17:26 +0800 Subject: [PATCH 0957/2070] drm/amdkcl: Check and implement the drm_dp_atomic_find_time_slots() Check and implement the drm_dp_atomic_find_time_slots() func Signed-off-by: Ma Jun Change-Id: I5fc1dd70ab3bbf0f62586136ccd999ef52606956 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fb2d3b5baeaa5..3ff44f40e11a0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -358,6 +358,9 @@ /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ +/* drm_dp_atomic_find_time_slots() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 336e89b2a2874..9f766ab7f8fc1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -44,6 +44,25 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, + [drm_dp_atomic_find_time_slots() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS ]) From 2d8ee35faff90834442d100ce68cf49b0808dcc3 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 12:41:17 +0800 Subject: [PATCH 0958/2070] drm/amdkcl: Implement the func drm_dp_atomic_find_time_slots() Signed-off-by: Ma Jun Change-Id: I4c07fabde6050973e25c0516166bc0e6ac256514 --- .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 9be8ef18696a1..6a5e6961228bb 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -65,6 +65,18 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) +static inline +int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div) +{ + return 0; +} +#define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots +#endif + #ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS static inline int _kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, From 87743762f433c8548aa876e65ef9ce0abdb9b5cc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 12:51:30 +0800 Subject: [PATCH 0959/2070] drm/amdkcl: Check if drm_dp_mst_atomic_setup_commit() is available Check if drm_dp_mst_atomic_setup_commit() is available Signed-off-by: Ma Jun Change-Id: I5653a9e25f19242d7b53c905efd1a92666b400a5 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 20 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 846a7d4c6b70a..a8ec9e99510cc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3774,7 +3774,9 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, +#endif }; static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3ff44f40e11a0..7ea1c14effb45 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -361,6 +361,9 @@ /* drm_dp_atomic_find_time_slots() is available */ /* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ +/* drm_dp_mst_atomic_setup_commit() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 9f766ab7f8fc1..0e5b9a432aa01 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -62,7 +62,27 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_setup_commit(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_SETUP_COMMIT, 1, + [drm_dp_mst_atomic_setup_commit() is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT ]) From 84b23f292cbd1ffb488e50fd4239442118a3e1a5 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:00:44 +0800 Subject: [PATCH 0960/2070] drm/amdkcl: Check if drm_dp_mst_atomic_wait_for_dependencies() is available Check if drm_dp_mst_atomic_wait_for_dependencies() is available Signed-off-by: Ma Jun Change-Id: Ibcfd90165754d5d8a0abbbaba850e5567e39bab4 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 21 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7ea1c14effb45..28dddbb3d7bbf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -364,6 +364,9 @@ /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ +/* drm_dp_mst_atomic_wait_for_dependencies() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 0e5b9a432aa01..bb74fab63718a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -80,9 +80,30 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ ]) ]) +drm_dp_mst_atomic_wait_for_dependencies + +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_wait_for_dependencies(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, + [drm_dp_mst_atomic_wait_for_dependencies() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT + AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES ]) From 89e92d751f4996eac4d59fe8883e984429344e8a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:15:48 +0800 Subject: [PATCH 0961/2070] drm/amdkcl: Check if drm_dp_mst_root_conn_atomic_check() is available Check if drm_dp_mst_root_conn_atomic_check() is available Signed-off-by: Ma Jun Change-Id: I3b91f33e2fd780e3b2c952aa2c5c95bcaae78a52 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 18 ++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a8ec9e99510cc..b4adb31a2b951 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8296,7 +8296,9 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; struct drm_crtc_state *new_crtc_state; +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); +#endif int ret; if (WARN_ON(unlikely(!old_con_state || !new_con_state))) @@ -8305,9 +8307,11 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, trace_amdgpu_dm_connector_atomic_check(new_con_state); if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); if (ret < 0) return ret; +#endif } if (!crtc) @@ -8367,6 +8371,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } #endif + static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 28dddbb3d7bbf..b8ee032d51221 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -415,6 +415,9 @@ /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +/* drm_dp_mst_root_conn_atomic_check() is available */ +/* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ + /* drm_dp_mst_port struct has full_pbn member */ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index bb74fab63718a..c28aae7a0814a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -100,10 +100,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK, 1, + [drm_dp_mst_root_conn_atomic_check() is available]) + ]) + ]) +]) AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES + AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ]) From 824189081d1919297b13c80cbfd4dbacd957e4fc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:25:40 +0800 Subject: [PATCH 0962/2070] drm/amdkcl: Check if drm_dp_atomic_release_time_slots() is available Check if drm_dp_atomic_release_time_slots() is available Signed-off-by: Ma Jun Change-Id: I1fa8e5977f98a88d638dd93c7fb2398fdf447147 --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4cdae3dfb29d7..a0053e6187029 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -625,11 +625,15 @@ dm_dp_mst_detect(struct drm_connector *connector, static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { +#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); +#else + return 0; +#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b8ee032d51221..ee7e2f7b9c95e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -370,6 +370,9 @@ /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 +/* drm_dp_atomic_release_time_slots() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ + /* drm_dp_atomic_find_vcpi_slots() wants 5args */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index c28aae7a0814a..a67dc29ccbeb2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -118,10 +118,29 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS ]) From c754b16f88b631540af7b37a12586ad92d084183 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:38:58 +0800 Subject: [PATCH 0963/2070] drm/amdkcl: Using amdkcl_ttm_resvp() to get bo->resv Using amdkcl_ttm_resvp() to get bo->resv Signed-off-by: Ma Jun Change-Id: I11553784cdba0f2a1c91d3bf41b274d14a843d3e --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 8dcc6b2c55485..b185c3a2626bd 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -983,7 +983,7 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, err_unlock: if (!resv) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); err_put: ttm_bo_put(bo); diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 31451bb23ffb1..cbc6afff927b8 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -519,7 +519,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map) struct ttm_resource *mem = bo->resource; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); ret = ttm_mem_io_reserve(bo->bdev, mem); if (ret) @@ -584,7 +584,7 @@ void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map) { struct ttm_resource *mem = bo->resource; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (iosys_map_is_null(map)) return; From cf35dbeb2068752e4c3bf41fbc262ddc8933790e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:48:06 +0800 Subject: [PATCH 0964/2070] drm/amdkcl: Rename idr-remove.m4 Rename idr-remove.m4 as idr.m4 for better compatability Signed-off-by: Ma Jun Change-Id: Iacfdba39cf4fd2224e51d8b3f018cb5dfcdbd5bd --- drivers/gpu/drm/amd/dkms/m4/{idr-remove.m4 => idr.m4} | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) rename drivers/gpu/drm/amd/dkms/m4/{idr-remove.m4 => idr.m4} (90%) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 similarity index 90% rename from drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 rename to drivers/gpu/drm/amd/dkms/m4/idr.m4 index 397c76a73ed8e..0801f227c6421 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -17,3 +17,7 @@ AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ ]) ]) ]) + +AC_DEFUN([AC_AMDGPU_IDR], [ + AC_AMDGPU_IDR_REMOVE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7e5e3e3323572..3bc34c78ba32f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_SUPPORTED_AMD_CHIPS - AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_IDR AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS From 7716ff210af2524fcf55f040fc5eb7c30e52ca9c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:54:45 +0800 Subject: [PATCH 0965/2070] drm/amdkcl: Check and implement idr_init_base() Check and implement idr_init_base() Signed-off-by: Ma Jun Change-Id: Idb8feda0a5dd39b22b1e65e2cafec0c108640f4e --- drivers/gpu/drm/amd/dkms/m4/idr.m4 | 39 ++++++++++++++++++++++++++++++ include/kcl/kcl_idr.h | 16 ++++++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 0801f227c6421..7816e84901c5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -18,6 +18,45 @@ AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-c4f306e31632 +dnl # drm/amdgpu: use idr_init_base() to initialize fpriv->bo_list_handles +dnl # +AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void *i; + i = idr_init_base(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_INIT_BASE, 1, + [idr_init_base() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v4.16-rc1~25-6ce711f27500 +dnl # idr: Make 1-based IDRs more efficient +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_IDE_IDR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct idr *idr = NULL; + idr->idr_base = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_IDE_IDR_BASE, 1, + [ide->idr_base is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_IDR], [ AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_IDR_INIT_BASE + AC_AMDGPU_STRUCT_IDE_IDR_BASE ]) diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h index 63473317c2ead..1cdea5ec45d67 100644 --- a/include/kcl/kcl_idr.h +++ b/include/kcl/kcl_idr.h @@ -35,4 +35,20 @@ static inline void *_kcl_idr_remove(struct idr *idr, int id) #define idr_remove _kcl_idr_remove #endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ +#ifndef HAVE_IDR_INIT_BASE +#ifdef HAVE_STRUCT_IDE_IDR_BASE +static inline void kc_idr_init_base(struct idr *idr, int base) +{ + INIT_RADIX_TREE(&idr->idr_rt, IDR_RT_MARKER); + idr->idr_base = base; + idr->idr_next = 0; +} +#else +static inline void kc_idr_init_base(struct idr *idr, int base) +{ + idr_init(idr); +} +#endif +#define idr_init_base kc_idr_init_base +#endif #endif /* AMDKCL_IDR_H */ From ee4e16c1b82951358557c9f36190360ddbc42dc5 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 24 Nov 2022 15:18:34 +0800 Subject: [PATCH 0966/2070] drm/amdkcl: change label from error_abort to error_unlock It's caused by 4624459c84d71e0d5f94ea6a7b2c4eec4f1d122b drm/amdgpu: add gang submit frontend v6 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 690be407bcb83..6e3e19e2136db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1460,7 +1460,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { r = -ERESTARTSYS; - goto error_abort; + goto error_unlock; } } #endif From db285b1210441f59bbd95ea2d3c416d79b455ac9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 16:43:31 +0800 Subject: [PATCH 0967/2070] drm/amdkcl: Declare amdgpu_display_gem_fb_init() Declare amdgpu_display_gem_fb_init because this function still being used Signed-off-by: Ma Jun Change-Id: I5184237ba51dcd6623ca64c49118db63ed7211a7 --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 304e8d3fccb1d..04e069038c84e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -703,6 +703,11 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); + int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); void amdgpu_enc_destroy(struct drm_encoder *encoder); From e783a889f89083777cdba0961d768066547ebfd5 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 23 Nov 2022 16:11:22 +0800 Subject: [PATCH 0968/2070] drm/amdkcl: rename the function name for HMM handling It's caused 735e66c12ec98751474db9e700c80e65355c1290 "drm/amdgpu: rename the files for HMM handling" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6e3e19e2136db..1c85d8fc8cb09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -42,6 +42,7 @@ #include "amdgpu_ras.h" #include "amdgpu_hmm.h" #include "amdgpu_display.h" +#include "amdgpu_hmm.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index a1ecaa032272d..9b0087a55ee4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -589,7 +589,7 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, } /** - * amdgpu_mn_register - register a BO for notifier updates + * amdgpu_hmm_register - register a BO for notifier updates * * @bo: amdgpu buffer object * @addr: userptr addr we should monitor @@ -597,7 +597,7 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, * Registers an MMU notifier for the given BO at the specified address. * Returns 0 on success, -ERRNO if anything goes wrong. */ -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) { unsigned long end = addr + amdgpu_bo_size(bo) - 1; struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -656,7 +656,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) * * Remove any registration of MMU notifier updates from the buffer object. */ -void amdgpu_mn_unregister(struct amdgpu_bo *bo) +void amdgpu_hmm_unregister(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_mn *amn; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index f2d02bb057c94..8df46f967cd09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -42,8 +42,8 @@ void amdgpu_mn_lock(struct amdgpu_mn *mn); void amdgpu_mn_unlock(struct amdgpu_mn *mn); struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, enum amdgpu_mn_type type); -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); -void amdgpu_mn_unregister(struct amdgpu_bo *bo); +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else /* !CONFIG_MMU_NOTIFIER */ static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} @@ -52,11 +52,11 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, { return NULL; } -static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) { return -ENODEV; } -static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} #endif /* CONFIG_MMU_NOTIFIER */ #else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include From 08076e34be4f443ab5cc99f6cc689c120421ac10 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 23 Nov 2022 14:32:31 +0800 Subject: [PATCH 0969/2070] drm/amdkcl: modify fake function for amdgpu_ttm_tt_get_user_pages It's caused by 3da41b3e6f43161b0878d71c4b92211e6495a1c3 "drm/amdgpu: fix userptr HMM range handling v2" Signed-off-by: bobzhou Reviewed-by: Leslie Shi Change-Id: I5455256f52b011df8e0d100ca2d4ab01975fd9f8 --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 148 +++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +- 3 files changed, 78 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f917c7da407bd..9ba5e1349bd9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1174,7 +1174,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -2971,7 +2971,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { mem->user_pages[0] = NULL; pr_info("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 1c85d8fc8cb09..a438b05e7f862 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -957,80 +957,80 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, } } #else - while (1) { - struct list_head need_pages; - - r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, - &duplicates); - if (unlikely(r != 0)) { - if (r != -ERESTARTSYS) - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); - goto error_free_pages; - } - - INIT_LIST_HEAD(&need_pages); - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - - if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, - &e->user_invalidated) && e->user_pages) { - - /* We acquired a page array, but somebody - * invalidated it. Free it and try again - */ - release_pages(e->user_pages, - bo->tbo.ttm->num_pages); - kvfree(e->user_pages); - e->user_pages = NULL; - } - - if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && - !e->user_pages) { - list_del(&e->tv.head); - list_add(&e->tv.head, &need_pages); - - amdgpu_bo_unreserve(bo); - } - } - - if (list_empty(&need_pages)) - break; - - /* Unreserve everything again. */ - ttm_eu_backoff_reservation(&p->ticket, &p->validated); - - /* We tried too many times, just abort */ - if (!--tries) { - r = -EDEADLK; - DRM_ERROR("deadlock in %s\n", __func__); - goto error_free_pages; - } - - /* Fill the page arrays for all userptrs. */ - list_for_each_entry(e, &need_pages, tv.head) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - - e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, - sizeof(struct page*), - GFP_KERNEL | __GFP_ZERO); - if (!e->user_pages) { - r = -ENOMEM; - DRM_ERROR("calloc failure in %s\n", __func__); - goto error_free_pages; - } - - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); - if (r) { - DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); - kvfree(e->user_pages); - e->user_pages = NULL; - goto error_free_pages; - } - } - - /* And try again. */ - list_splice(&need_pages, &p->validated); - } + while (1) { + struct list_head need_pages; + + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, + &duplicates); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); + goto error_free_pages; + } + + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { + + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } + } + + /* And try again. */ + list_splice(&need_pages, &p->validated); + } #endif amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 9a13c36472fa3..4ee3cc93612af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -837,7 +837,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; From 25535748f89dc3934ef36e9776507f6b621af6b5 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 28 Nov 2022 13:01:24 +0800 Subject: [PATCH 0970/2070] drm/amdkcl: fix macro for amdgpu_dm_mst_connector_early_unregister It's caused by m4 macro didn't align HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER and HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER Signed-off-by: Aurabindo Pillai Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ee7e2f7b9c95e..1c6bb3a3f03d3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -144,10 +144,10 @@ #define HAVE_DOWN_WRITE_KILLABLE 1 /* drm_dp_mst_connector_early_unregister() is available */ -#define HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 /* drm_dp_mst_connector_late_register() is available */ -#define HAVE_DP_MST_CONNECTOR_LATE_REGISTER 1 +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 /* drm_accurate_vblank_count() is available */ /* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index c0651dfe03701..cf4afe7538011 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -47,9 +47,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); ], [ - AC_DEFINE(HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ drm_dp_mst_connector_early_unregister() is available]) - AC_DEFINE(HAVE_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ drm_dp_mst_connector_late_register() is available]) ]) ]) From 1d4a6beaace3b8d5cddc9c63aa4e4c0a9ffb376a Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 28 Nov 2022 14:14:40 +0800 Subject: [PATCH 0971/2070] drm/amdkcl: update documentation of amdgpu_hmm_unregister Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9b0087a55ee4c..7364124a2afec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -650,7 +650,7 @@ int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) } /** - * amdgpu_mn_unregister - unregister a BO for notifier updates + * amdgpu_hmm_unregister - unregister a BO for notifier updates * * @bo: amdgpu buffer object * From 591fb8736a52a8c6166a87b0e41cc9e8399bb6de Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Dec 2022 15:10:47 +0800 Subject: [PATCH 0972/2070] drm/amdkcl: Fix the type of function kcl_drm_plane_helper_destroy Fix the type of the function kcl_drm_plane_helper_destroy Signed-off-by: Ma Jun Change-Id: Ic2bdbbcd518581b3b5cd2ddd30997b8e7c9ba196 --- include/kcl/kcl_drm_plane_helper.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_plane_helper.h b/include/kcl/kcl_drm_plane_helper.h index d1bc40bcebb4d..6b3798e0da151 100644 --- a/include/kcl/kcl_drm_plane_helper.h +++ b/include/kcl/kcl_drm_plane_helper.h @@ -4,12 +4,11 @@ #include #ifndef HAVE_DRM_PLANE_HELPER_DESTROY -static void kcl_drm_plane_helper_destroy(struct drm_plane *plane) +static inline void kcl_drm_plane_helper_destroy(struct drm_plane *plane) { drm_plane_cleanup(plane); kfree(plane); } - #define drm_plane_helper_destroy kcl_drm_plane_helper_destroy #endif #endif \ No newline at end of file From 611113cfeeee55031fe51e6b52e62c29633bb8d8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Dec 2022 16:29:19 +0800 Subject: [PATCH 0973/2070] drm/amdkcl: Fix the warning of comment Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: If5721c8156ae7b147c90bb6dd2d9aff283b22ac6 --- drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c index fe36b386ff52b..f740a9626cd10 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -2,7 +2,7 @@ #include #ifndef for_each_cpu_wrap -/* copied from lib/cpumask.c +/* copied from lib/cpumask.c */ /** * cpumask_next_wrap - helper to implement for_each_cpu_wrap * @n: the cpu prior to the place to search From 0bc2c5db1a7bac108d4d5543cbd9f76884431d63 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 5 Dec 2022 15:22:49 +0800 Subject: [PATCH 0974/2070] drm/amdkcl: Add support for drm_plane_enable_fb_damage_clips before v5.13 It's caused by 1f35cc57ec8c39b023bc1cfc4a29483e09fbbc89 "drm/amd/display: add FB_DAMAGE_CLIPS support" drm_plane_enable_fb_damage_clips is moved into core in v5.13-rc3-1669-gba6cd766e0bf Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d1d1b6560ee39..f427bb1ff73f0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -92,4 +92,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ From e6eb31ae6244e703c20446042ec05aff31e91e12 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 8 Dec 2022 13:27:23 +0800 Subject: [PATCH 0975/2070] drm/amdkcl/dkms: Using the AS_HELPER_STRING intead of AC_HELP_STRING AC_HELP_STRING is deprecated now. So using the AS_HELPER_STRING intead of AC_HELP_STRING Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I144d13752fccf00f01a1a0dc4542603cebb9323f --- drivers/gpu/drm/amd/dkms/m4/config.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 index e22a4a49a5233..d66b31b9b3536 100644 --- a/drivers/gpu/drm/amd/dkms/m4/config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -1,6 +1,6 @@ AC_DEFUN([AC_AMDGPU_CONFIG], [ AC_ARG_ENABLE([linux-builtin], - [AC_HELP_STRING([--enable-linux-builtin], + [AS_HELP_STRING([--enable-linux-builtin], [Configure for builtin kernel modules @<:@default=no@:>@])], [], [enable_linux_builtin=no]) From a97990a72922b8b9b4c6e36c9cd9e4d1d39abfda Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 9 Dec 2022 10:29:36 +0800 Subject: [PATCH 0976/2070] drm/amdkcl: Add missing comments in backport.h for drm_plane_enable_fb_damage_clips Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f427bb1ff73f0..06d5ae44325a4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -92,5 +92,11 @@ #include #include #include +/* + * v5.13-rc3-1669-gba6cd766e0bf + * ("drm/plane: Move drm_plane_enable_fb_damage_clips into core") + * move drm_plane_enable_fb_damage_clips() to drm_planer.h. + * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. + */ #include #endif /* AMDGPU_BACKPORT_H */ From 8c811106f9936f3340b1e930dbf1adacf4ae05ed Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Wed, 21 Dec 2022 15:58:36 +0800 Subject: [PATCH 0977/2070] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE It's caused by d090329b677c2f158755e886199c20b1acf93eb5 "drm/amd/display: save restore hdcp state when display is unplugged from mst hub" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b4adb31a2b951..42cbf44ee48b9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10828,6 +10828,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) enable_encryption = true; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_link && aconnector->dc_sink && aconnector->dc_link->type == dc_connection_mst_branch) { struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; @@ -10839,6 +10840,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) hdcp_w->content_protection[connector->index] = new_con_state->content_protection; } +#endif if (new_crtc_state && new_crtc_state->mode_changed && new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a0053e6187029..abe7ef9c24293 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -488,6 +488,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) * plugged back with same display index, its hdcp properties * will be retrieved from hdcp_work within dm_dp_mst_get_modes */ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_sink && connector->state) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -503,6 +504,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) hdcp_w->content_protection[connector->index]; } } +#endif if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( From e5a2b87dd41403bbd96ed0443ca68969dc7b4c5f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 5 Jan 2023 09:53:55 +0800 Subject: [PATCH 0978/2070] drm/amdkcl: Fix the compile warning when check dma_resv->seq Fix the compile warning when check dma_resv->seq Change-Id: I2580b66ff02a1991ce6e6b1b046365bc9cbfcb01 Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index eec0d7868d7c2..9d2de6369b657 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -13,7 +13,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing., exit...) +$(error dma_resv->seq is missing. exit...) endif ifeq ($(CC), gcc) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 93c6dbc25ae22..8cf888eb3a6b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -45,7 +45,8 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ #include ], [ #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) - int this_is_bug = 0; + int this_is_bug; + this_is_bug = 0; #else this_is_not_bug(); #endif From 8a2dd85c3c514cc9389f55e2d073a00721606c5b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 15 Dec 2022 16:58:43 +0800 Subject: [PATCH 0979/2070] drm/amdkcl: Return only kernel fences when iterating dma_resv with DMA_RESV_USAGE_KERNEL Avoid returning unnecessary write fences when extracting DMA_RESV_USAGE_KERNEL fences that could impact performance v2: dma_fence_put kernel_iter when iter restart v3: simplify code Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 174 ++++++++++++++++------ include/kcl/kcl_dma-resv.h | 6 + 2 files changed, 132 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 8edf3fccac3e9..dc92c2d10f23d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -342,44 +342,6 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, } EXPORT_SYMBOL(dma_resv_replace_fences); -/** - * dma_resv_add_excl_fence - Add an exclusive fence. - * @obj: the reservation object - * @fence: the exclusive fence to add - * - * Add a fence to the exclusive slot. @obj must be locked with dma_resv_lock(). - * See also &dma_resv.fence_excl for a discussion of the semantics. - */ -static void dma_resv_add_excl_fence(struct dma_resv *obj, - struct dma_fence *fence) -{ - struct dma_fence *old_fence = dma_resv_excl_fence(obj); - struct dma_fence_chain *chain; - - dma_resv_assert_held(obj); - - if (old_fence && !dma_fence_is_signaled(old_fence)) { - - chain = dma_fence_chain_alloc(); - if (unlikely(!chain)) - pr_err("dma_resv_add_excl_fence OOM\n"); - else { - dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); - fence = &chain->base; - } - } else { - dma_fence_get(fence); - } - - - write_seqcount_begin(&obj->seq); - /* write_seqcount_begin provides the necessary memory barrier */ - RCU_INIT_POINTER(obj->fence_excl, fence); - write_seqcount_end(&obj->seq); - - dma_fence_put(old_fence); -} - /** * dma_resv_add_fence - Add a fence to the dma_resv obj * @obj: the reservation object @@ -394,10 +356,28 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, enum dma_resv_usage usage) { - if (usage == DMA_RESV_USAGE_WRITE || usage == DMA_RESV_USAGE_KERNEL) - dma_resv_add_excl_fence(obj, fence); - else + struct dma_fence_chain *chain; + + if (usage >= DMA_RESV_USAGE_READ) { dma_resv_add_shared_fence(obj, fence); + return; + } + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) { + /* We are out of memory, block as last resort */ + dma_fence_wait(fence, false); + return; + } + dma_fence_chain_init(chain, dma_resv_excl_fence(obj), dma_fence_get(fence), 1); + + /* Store the usage in the user bit to retrieve it later on */ + chain->base.flags |= usage << DMA_FENCE_FLAG_USER_BITS; + + /* Install the exclusive fence manually */ + write_seqcount_begin(&obj->seq); + RCU_INIT_POINTER(obj->fence_excl, &chain->base); + write_seqcount_end(&obj->seq); } EXPORT_SYMBOL(dma_resv_add_fence); @@ -408,6 +388,8 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) cursor->seq = read_seqcount_begin(&cursor->obj->seq); cursor->index = -1; cursor->shared_count = 0; + cursor->excl_fence = NULL; + cursor->kernel_iter = NULL; if (cursor->usage >= DMA_RESV_USAGE_READ) { cursor->fences = dma_resv_shared_list(cursor->obj); if (cursor->fences) @@ -422,17 +404,55 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) { struct dma_resv *obj = cursor->obj; + struct dma_fence_chain *chain; + struct dma_fence *f; + enum dma_resv_usage usage; do { /* Drop the reference from the previous round */ dma_fence_put(cursor->fence); if (cursor->index == -1) { - cursor->fence = dma_resv_excl_fence(obj); - cursor->index++; - if (!cursor->fence) - continue; - + if (cursor->usage >= DMA_RESV_USAGE_WRITE) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + } else { + cursor->fence = NULL; + /* Only return KERNEL fences */ + if (!cursor->excl_fence) { + cursor->excl_fence = dma_resv_excl_fence(obj); + if (!cursor->excl_fence) + break; + + cursor->excl_fence = dma_fence_get(cursor->excl_fence); + cursor->kernel_iter = dma_fence_get(cursor->excl_fence); + } + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && !dma_fence_is_signaled(chain->fence)) + cursor->fence = chain->fence; + + cursor->kernel_iter = dma_fence_chain_walk(f); + + if (cursor->fence) + break; + } + + if (!cursor->fence) { + dma_fence_put(cursor->excl_fence); + cursor->excl_fence = NULL; + break; + } + } } else if (!cursor->fences || cursor->index >= cursor->shared_count) { cursor->fence = NULL; @@ -464,10 +484,18 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) */ struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) { + bool restart = false; + rcu_read_lock(); do { + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + } dma_resv_iter_restart_unlocked(cursor); dma_resv_iter_walk_unlocked(cursor); + restart = true; } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); rcu_read_unlock(); @@ -493,8 +521,13 @@ struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) cursor->is_restarted = false; restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); do { - if (restart) + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + dma_resv_iter_restart_unlocked(cursor); + } dma_resv_iter_walk_unlocked(cursor); restart = true; } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); @@ -515,7 +548,9 @@ EXPORT_SYMBOL(dma_resv_iter_next_unlocked); */ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) { - struct dma_fence *fence; + struct dma_fence *fence, *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; dma_resv_assert_held(cursor->obj); @@ -525,11 +560,34 @@ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) else cursor->fences = NULL; + cursor->kernel_iter = NULL; fence = dma_resv_excl_fence(cursor->obj); if (!fence) fence = dma_resv_iter_next(cursor); + else if (cursor->usage == DMA_RESV_USAGE_KERNEL) { + cursor->kernel_iter = dma_fence_get(fence); + fence = NULL; + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL) + fence = chain->fence; + + if (fence) + break; + } + } cursor->is_restarted = true; + return fence; } EXPORT_SYMBOL_GPL(dma_resv_iter_first); @@ -544,10 +602,30 @@ EXPORT_SYMBOL_GPL(dma_resv_iter_first); struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) { unsigned int idx; + struct dma_fence *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; dma_resv_assert_held(cursor->obj); cursor->is_restarted = false; + + if (cursor->usage == DMA_RESV_USAGE_KERNEL && cursor->kernel_iter != NULL) { + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && chain->fence) + return chain->fence; + } + } + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) return NULL; diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 4fe1fe0afac9d..a6b8ab359aa0d 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -171,6 +171,12 @@ struct dma_resv_iter { /** @is_restarted: true if this is the first returned fence */ bool is_restarted; + + /** @excl_fence: keep a reference to excl_fence when begin iterating kernel fences */ + struct dma_fence *excl_fence; + + /** @kernel_iter: next kernel fence pointer when iterating kernel fences */ + struct dma_fence *kernel_iter; }; #if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) From 2f9f8c91d5fabc3c3f600840ec640382cf70ba50 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Tue, 17 Jan 2023 18:23:23 +0800 Subject: [PATCH 0980/2070] drm/amdkcl: add macro DP_128B132B_TRAINING_AUX_RD_INTERVAL and DP_128B132B_SUPPORTED_LINK_RATES It's cause by 'commit 568c97c25cdb ("drm/amd/display: move dp link training logic to link_dp_training")' v6.0-2248-g568c97c25cdb Signed-off-by: Horatio Zhang Reviewed-by: Asher Song --- include/kcl/kcl_drm_dp_helper.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index cecb273e97d8a..4d3a14e7df501 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -326,4 +326,20 @@ enum drm_dp_phy { # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ #endif +/* + * v5.15-rc1-244-gba3078dad140 + * drm/dp: add helpers to read link training delays + */ +#ifndef DP_128B132B_TRAINING_AUX_RD_INTERVAL +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ +#endif + +/* + * v5.9-rc5-1031-g7d56927efac7 + * drm/dp: add a number of DP 2.0 DPCD definitions + */ +#ifndef DP_128B132B_SUPPORTED_LINK_RATES +#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From ab3af8fed88d8ebbab7272612b6ffa2f633e7e7d Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 10:45:54 +0800 Subject: [PATCH 0981/2070] drm/amdkcl: wrap code under macro HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT It's caused by 2f21ecf75a71b8aad4e28ce05758fb3f74eff4d1 "drm/amd/display: force connector state when bpc changes during compliance" Signed-off-by: bobzhou2 Reviewed-by: Flora Cui drm/amdkcl: Implement the drm_kms_helper_connector_hotplug_event() Implement the drm_kms_helper_connector_hotplug_event() for legacy os Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +----------------- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 -------- include/kcl/backport/kcl_drm_probe_helper.h | 16 ++++++++++++++++ 4 files changed, 18 insertions(+), 25 deletions(-) create mode 100644 include/kcl/backport/kcl_drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 06d5ae44325a4..3f13eff9ba0d1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -99,4 +99,5 @@ * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. */ #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 42cbf44ee48b9..3e78ed1b0f5b5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1558,7 +1558,7 @@ static void force_connector_state( mutex_unlock(&connector->dev->mode_config.mutex); mutex_lock(&aconnector->hpd_lock); - drm_kms_helper_connector_hotplug_event(connector); + drm_kms_helper_connector_hotplug_event(connector); mutex_unlock(&aconnector->hpd_lock); } @@ -4138,11 +4138,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else if (debounce_required) { /* * HDMI disconnect detected - schedule delayed work instead of @@ -4185,11 +4181,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } } } @@ -4322,11 +4314,7 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else { bool ret = false; @@ -4345,11 +4333,7 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 84ade928ad7c4..b45f2d6bd18ee 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1511,11 +1511,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else if (param[0] == 0) { if (!aconnector->dc_link) goto unlock; @@ -1541,11 +1537,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } unlock: diff --git a/include/kcl/backport/kcl_drm_probe_helper.h b/include/kcl/backport/kcl_drm_probe_helper.h new file mode 100644 index 0000000000000..3ac7310361bb4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_probe_helper.h @@ -0,0 +1,16 @@ +#ifndef AMDKCL_BACKPORT_DRM_PROBE_HELPER_H +#define AMDKCL_BACKPORT_DRM_PROBE_HELPER_H + +#include + +#ifndef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT +static inline void _kcl_drm_kms_helper_connector_hotplug_event(struct drm_connector *connector) +{ + drm_kms_helper_hotplug_event(connector->dev); +} + +#define drm_kms_helper_connector_hotplug_event _kcl_drm_kms_helper_connector_hotplug_event + + +#endif +#endif From fedb336496f05c908e41e515a5e0391cd1dfc383 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 12 Jan 2023 17:19:59 +0800 Subject: [PATCH 0982/2070] drm/amdkcl: Use debugfs_remove_recursive to remove ttm directory Use debugfs_remove_recursive to remove the /sys/kernel/debug/ttm directory for better compatibility. Becuase debugfs_remove fails on older kernel. Change-Id: Ifcf180d18592a64b038c768c2257200416ef860b Signed-off-by: Ma Jun Reviewed-by: GuChun Chen --- drivers/gpu/drm/ttm/ttm_device.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 1700f0dc51504..4c4e167955729 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -62,7 +62,13 @@ static void ttm_global_release(void) goto out; ttm_pool_mgr_fini(); - debugfs_remove(ttm_debugfs_root); + + /* + * Replace the debugfs_remove() with debugfs_remove_recursive() for dkms code. + * debugfs_remove() can't remove the ttm/ directory in legacy kernel. + * So use the debugfs_remove_recursive() here. + */ + debugfs_remove_recursive(ttm_debugfs_root); __free_page(glob->dummy_read_page); memset(glob, 0, sizeof(*glob)); From a9234608d33b22558f5904693db04520487224a7 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 13:23:45 +0800 Subject: [PATCH 0983/2070] drm/amdkcl: wrap code under CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by a966a85e03653371931c13496e6a1c7638606666 "drm/amd/display: move eDP panel control logic to link_edp_panel_control" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- .../amd/display/dc/link/protocols/link_edp_panel_control.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 5b2c1a4911cf0..35fb431d8a47e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -376,10 +376,14 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link)); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!crtc_timing->flags.DSC) edp_decide_link_settings(link, &link_setting, req_bw); else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); +#else + decide_edp_link_settings(link, &link_setting, req_bw); +#endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { From a1d5956e00a944ae5fda4e18a221d8a994ee7a23 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 16:02:02 +0800 Subject: [PATCH 0984/2070] drm/amdkcl: add macro DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 It's caused by d9659c5e79a59264f633fbfec65d76a26bb8a274 "drm/amd/display: Enable AdaptiveSync in DC interface" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 4d3a14e7df501..9f921c3d9db24 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -342,4 +342,12 @@ enum drm_dp_phy { #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ #endif +/* + * v6.0-2085-gbdf4b00bee5d + * drm/display: Add missing Adaptive Sync DPCD definitions + */ +#ifndef DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 2e8fce453ec5d0e0acf813eb8d4ed2fe55c58cb8 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Tue, 31 Jan 2023 14:07:03 +0800 Subject: [PATCH 0985/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by 92ffdc98c5f71750ab18b01fd4a67c055127e59f "drm/amd/display: Enable Freesync over PCon" Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3e78ed1b0f5b5..af5f60e991011 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13396,8 +13396,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } From ee3690545f08e09128daa290d08e78d49bbcc4ba Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Tue, 31 Jan 2023 15:30:55 +0800 Subject: [PATCH 0986/2070] drm/amdkcl: fix redefine issue due to backport.h It's caused by 92ffdc98c5f71750ab18b01fd4a67c055127e59f "drm/amd/display: Enable Freesync over PCon" Redefine fuction get_reg_field_value_ex and FD(reg_field). When backport.h includes dm_services.h, It shouldn't define get_reg_field_value_ex and FD(reg_field). Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c | 7 +++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c index ca0c8a54b635e..88bf59ee5fea7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c @@ -63,11 +63,18 @@ static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, } } +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask, uint8_t shift) { return (mask & reg_value) >> shift; } +#endif void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index b314e60714ee2..10a87a277be22 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -50,7 +50,14 @@ struct dmub_srv; #define REG(reg) (REGS)->offset.reg +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field +#endif #define FN(reg_name, field) FD(reg_name##__##field) From 8fe2c49c2ebfa0abebd8c539ce127fb22ced8b60 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 15 Dec 2022 23:52:10 +0800 Subject: [PATCH 0987/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DEV_DBG Since the function drm_dev_dbg() is available on oldest supported OS REL7.9, remove drm_dev_dbg check. Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 25 ---------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 | 11 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_print.h | 4 ---- 5 files changed, 44 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 9e0c95502367c..95e75be1d5ee8 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -59,31 +59,6 @@ void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) EXPORT_SYMBOL(__drm_printfn_debug); #endif -#if !defined(HAVE_DRM_DEV_DBG) -void drm_dev_dbg(const struct device *dev, int category, - const char *format, ...) -{ - struct va_format vaf; - va_list args; - - if (!drm_debug_enabled(category)) - return; - - va_start(args, format); - vaf.fmt = format; - vaf.va = &args; - - if (dev) - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); - else - printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); - - va_end(args); -} -EXPORT_SYMBOL(drm_dev_dbg); -#endif #if !defined(HAVE_DRM_ERR_MACRO) void kcl_drm_err(const char *format, ...) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1c6bb3a3f03d3..b2760b10ca15e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -301,9 +301,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_dbg() is available */ -#define HAVE_DRM_DEV_DBG 1 - /* drm_dev_enter() is available */ #define HAVE_DRM_DEV_ENTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 deleted file mode 100644 index dfcc85e60e4bf..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 +++ /dev/null @@ -1,11 +0,0 @@ -dnl # -dnl # v4.16-rc1-493-gdb8708649258 -dnl # drm: Reduce object size of DRM_DEV_ uses -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_DBG], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_dev_dbg], [drivers/gpu/drm/drm_print.c], [ - AC_DEFINE(HAVE_DRM_DEV_DBG, 1, [drm_dev_dbg() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3bc34c78ba32f..c07ba21ed205e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,7 +66,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET - AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 80d51e8721236..a726abd73190d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -153,10 +153,6 @@ void kcl_drm_err(const char *format, ...); } while (0) #endif -#if !defined(HAVE_DRM_DEV_DBG) -void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); -#endif - #if !defined(drm_dbg_atomic) #define drm_dbg_atomic(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) From 157eae40a379a70fe0a25823e8f499cccdcf7afc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 12 Dec 2022 16:34:58 +0800 Subject: [PATCH 0988/2070] drm/amdkcl: test whether MEMORY_DEVICE_COHERENT and MIGRATE_VMA_SELECT_DEVICE_PRIVATE is defined It's caused by 8dd9f5d2d0e4c14387e41c5231c3cff5a474b561 drm/amdkfd: add SPM support for SVM Signed-off-by: Felix Kuehling Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 | 22 ++++++++++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 9ed4a2e174ddf..6c92cd7e44c74 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -726,9 +726,11 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.end = end; #ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else +#endif migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; #elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b2760b10ca15e..b58409176c2ad 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -80,6 +80,9 @@ /* devcgroup_check_permission() is available */ #define HAVE_DEVCGROUP_CHECK_PERMISSION 1 +/* MEMORY_DEVICE_COHERENT is availablea */ +#define HAVE_DEVICE_COHERENT 1 + /* devm_memremap_pages() wants struct dev_pagemap */ #define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c07ba21ed205e..c72e6d181312b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -172,6 +172,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS AC_AMDGPU_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 new file mode 100644 index 0000000000000..786ce2c5590ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit f25cbb7a95a24ff9a2a3bebd308e303942ae6b2c +dnl # mm: add zone device coherent type memory support +dnl # +dnl # commit dd19e6d8ffaa1289d75d7833de97faf1b6b2c8e4 +dnl # mm: add device coherent vma selection for memory migration +dnl # +AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int v = MEMORY_DEVICE_COHERENT; + int w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + ], [ + AC_DEFINE(HAVE_DEVICE_COHERENT, 1, + [MEMORY_DEVICE_COHERENT is availablea]) + ]) + ]) +]) + From 97c864088c183d5be1ed2a3e43cc9a80ab82379b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 11:09:33 +0800 Subject: [PATCH 0989/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" This patch is used to implent legacy payload code Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 153 +++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 25 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 179 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 13c1adce3f4ae..966d6d05a94a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -220,6 +220,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( return result; } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void fill_dc_mst_payload_table_from_drm(struct dc_link *link, bool enable, @@ -270,6 +271,44 @@ fill_dc_mst_payload_table_from_drm(struct dc_link *link, /* Overwrite the old table */ *table = new_table; } +#else +static void +fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, + struct dc_dp_mst_stream_allocation_table *proposed_table) +{ + int i; + struct drm_dp_mst_topology_mgr *mst_mgr = + &aconnector->mst_port->mst_mgr; + + mutex_lock(&mst_mgr->payload_lock); + + proposed_table->stream_count = 0; + + /* number of active streams */ + for (i = 0; i < mst_mgr->max_payloads; i++) { + if (mst_mgr->payloads[i].num_slots == 0) + break; /* end of vcp_id table */ + + ASSERT(mst_mgr->payloads[i].payload_state != + DP_PAYLOAD_DELETE_LOCAL); + + if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || + mst_mgr->payloads[i].payload_state == + DP_PAYLOAD_REMOTE) { + + struct dc_dp_mst_stream_allocation *sa = + &proposed_table->stream_allocations[ + proposed_table->stream_count]; + + sa->slot_count = mst_mgr->payloads[i].num_slots; + sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; + proposed_table->stream_count++; + } + } + + mutex_unlock(&mst_mgr->payload_lock); +} +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, @@ -318,9 +357,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( bool enable) { struct amdgpu_dm_connector *aconnector; + struct drm_dp_mst_topology_mgr *mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; - struct drm_dp_mst_topology_mgr *mst_mgr; +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct dm_connector_state *dm_conn_state; +#endif + struct drm_dp_mst_port *mst_port; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int slots = 0; +#endif + bool ret; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int clock; + int bpp = 0; + int pbn = 0; +#endif + u8 link_coding_cap = DP_8b_10b_ENCODING; +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; /* Accessing the connector state is required for vcpi_slots allocation @@ -333,6 +389,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( return false; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); @@ -356,7 +413,83 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( * sequence. copy DRM MST allocation to dc */ fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + dm_conn_state = to_dm_connector_state(aconnector->base.state); +#endif + if (!mst_mgr->mst_state) + return false; + mst_port = aconnector->port; + +#if defined(CONFIG_DRM_AMD_DC_DCN) + link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); +#endif + + if (enable) { + +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + clock = stream->timing.pix_clk_100hz / 10; + + switch (stream->timing.display_color_depth) { + + case COLOR_DEPTH_666: + bpp = 6; + break; + case COLOR_DEPTH_888: + bpp = 8; + break; + case COLOR_DEPTH_101010: + bpp = 10; + break; + case COLOR_DEPTH_121212: + bpp = 12; + break; + case COLOR_DEPTH_141414: + bpp = 14; + break; + case COLOR_DEPTH_161616: + bpp = 16; + break; + default: + ASSERT(bpp != 0); + break; + } + + bpp = bpp * 3; + + /* TODO need to know link rate */ + pbn = drm_dp_calc_pbn_mode(clock, bpp, false); + + slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, + slots); +#else + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, + dm_conn_state->pbn, + dm_conn_state->vcpi_slots); +#endif + if (!ret) + return false; + + } else { + drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); + } + + /* It's OK for this to fail */ +#ifdef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1); +#else + drm_dp_update_payload_part1(mst_mgr); +#endif + + /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or + * AUX message. The sequence is slot 1-63 allocated sequence for each + * stream. AMD ASIC stream slot allocation should follow the same + * sequence. copy DRM MST allocation to dc */ + + fill_dc_mst_payload_table_from_drm(aconnector, proposed_table); +#endif return true; } @@ -411,9 +544,13 @@ void dm_helpers_dp_mst_send_payload_allocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; - struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_atomic_payload *new_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif + struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; int ret = 0; @@ -424,11 +561,21 @@ void dm_helpers_dp_mst_send_payload_allocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); - ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + mst_port = aconnector->port; + if (!mst_mgr->mst_state) + return; +#endif +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) + ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + ret = drm_dp_update_payload_part2(mst_mgr); +#endif if (ret) { amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, false); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b58409176c2ad..3c943ac54536e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -442,6 +442,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* struct drm_dp_mst_topology_state has member payloads */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 + /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 16c25dc496d18..c277169c1c66c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -22,3 +22,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ ]) ]) + +dnl # +dnl # commit 8366f01fb15a54281c193658d1a916f6f2d5eb1e +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + struct list_head payloads; + payloads = mst_state->payloads; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS, 1, + [struct drm_dp_mst_topology_state has member payloads]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c72e6d181312b..67aa2cad60f1c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -173,6 +173,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_VIDEO_FUNCS AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_MEMORY_DEVICE_COHERENT + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From c667acfe0d2b904aaff812523b4da1e4fb8039bb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Feb 2023 11:15:13 +0800 Subject: [PATCH 0990/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 22 +++++++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index af5f60e991011..6a89b240b2617 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8425,7 +8425,9 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV struct drm_dp_mst_topology_state *mst_state; +#endif enum dc_color_depth color_depth; int clock, bpp = 0; bool is_y420 = false; @@ -8456,11 +8458,13 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#endif if (!state->duplicated) { int max_bpc = conn_state->max_requested_bpc; @@ -12876,6 +12880,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ @@ -12898,6 +12903,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, drm_connector_list_iter_end(&iter); } #endif +#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index abe7ef9c24293..c228f66973e54 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1122,11 +1122,18 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + int pbn_per_timeslot; +#endif int link_timeslots_used; int fair_pbn_alloc; int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); +#endif + for (i = 0; i < count; i++) { if (vars[i + k].dsc_enabled) { initial_slack[i] = @@ -1157,10 +1164,21 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, link_timeslots_used = 0; for (i = 0; i < count; i++) - link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div)); + link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + dfixed_trunc(mst_state->pbn_div) +#else + pbn_per_timeslot +#endif + ); fair_pbn_alloc = - (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div); + (63 - link_timeslots_used) / remaining_to_increase * +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + dfixed_trunc(mst_state->pbn_div); +#else + pbn_per_timeslot; +#endif if (initial_slack[next_index] > fair_pbn_alloc) { vars[next_index].pbn += fair_pbn_alloc; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3c943ac54536e..7facf916e5b8d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -445,6 +445,9 @@ /* struct drm_dp_mst_topology_state has member payloads */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 +/* struct drm_dp_mst_topology_state has member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV 1 + /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index c277169c1c66c..44804d21ee9ff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -47,3 +47,30 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ ]) ]) ]) + + +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + int pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV, 1, + [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 67aa2cad60f1c..5d694f8596d97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -174,6 +174,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 09578c0198229eb60c3f7b52edf710e0a77135a1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 13:27:02 +0800 Subject: [PATCH 0991/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 54 +++++++++++++++---- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 8 ++- .../backport/kcl_drm_dp_mst_helper_backport.h | 2 +- 5 files changed, 59 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6a89b240b2617..b2cbea5394d01 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8481,7 +8481,11 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, - dm_new_connector_state->pbn); + dm_new_connector_state->pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(aconnector->dc_link) +#endif + ); if (dm_new_connector_state->vcpi_slots < 0) { drm_dbg_atomic(connector->dev, "failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index c228f66973e54..659302d5b2f44 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1185,7 +1185,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1197,7 +1201,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1206,7 +1214,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1218,7 +1230,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1281,7 +1297,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) { DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", __func__, __LINE__, next_index, ret); @@ -1300,7 +1320,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) { DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", __func__, __LINE__, next_index, ret); @@ -1422,7 +1446,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, - vars[i + k].pbn); + vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } @@ -1444,7 +1472,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = true; vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } else { @@ -1452,7 +1484,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7facf916e5b8d..7094aafa572c6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -359,7 +359,7 @@ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ /* drm_dp_atomic_find_time_slots() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ +#define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index a67dc29ccbeb2..f19d5bf4ea976 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -51,10 +51,16 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; - ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0, 0); + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, [drm_dp_atomic_find_time_slots() is available]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 6a5e6961228bb..edac58606beb9 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -72,7 +72,7 @@ int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port, int pbn, int pbn_div) { - return 0; + return drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn, pbn_div); } #define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots #endif From 3fe0f89fac4d78331d9d4308e95ab033d916dfad Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Feb 2023 11:36:14 +0800 Subject: [PATCH 0992/2070] drm/amdkcl: wrap code under marco HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 ++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 659302d5b2f44..6b38436e9821b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -965,7 +965,12 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); aconnector->mst_mgr.cbs = &dm_mst_cbs; drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), - &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); + &aconnector->dm_dp_aux.aux, 16, 4, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), +#endif + aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7094aafa572c6..7a04583f85af3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -439,6 +439,9 @@ /* drm_dp_mst_topology_mgr_init() wants drm_device arg */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 +/* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ + /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 From c246dacd41d8cc05a193eb85506cdbebddd1a948 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 14:17:39 +0800 Subject: [PATCH 0993/2070] drm/amdkcl: check drm_dp_mst_atomic_enable_dsc whether has four arguments It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 22 +++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b2cbea5394d01..d991ffb3efd4e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8561,14 +8561,22 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, dm_conn_state->vcpi_slots = slot_num; ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, - dm_conn_state->pbn, false); + dm_conn_state->pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + false); if (ret < 0) return ret; continue; } - vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); + vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + true); if (vcpi < 0) return vcpi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7a04583f85af3..4a14c4f882552 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -406,6 +406,9 @@ /* drm_dp_mst_atomic_enable_dsc() is available */ #define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 +/* drm_dp_mst_atomic_enable_dsc() wants 5args */ +/* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 806158f1562a8..0019f393b38f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -17,6 +17,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, [drm_dp_mst_atomic_enable_dsc() is available]) + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS, 1, + [drm_dp_mst_atomic_enable_dsc() wants 5args]) + ],[ + dnl # + dnl # commit 4d07b0bc403403438d9cf88450506240c5faf92f + dnl # drm/display/dp_mst: Move all payload info into the atomic state + dnl # + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + int vcpi; + vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) ]) ]) ]) From c192091696e0cb592e9e8840c2d4c2adf7c24ad0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 6 Jan 2023 09:23:42 +0800 Subject: [PATCH 0994/2070] drm/amdkcl: Check the gcc and kernel version before the compilation starts Check the gcc and kernel version before the compilation starts. This is mainly used for some special application scenarios. For example, Some customers use kernel 5.4 and gcc 4.8.5 This will cause the compilations failure. So we check this case and provide a hint. Change-Id: I448d9c289ea66da701291df42bed504ed4dfb782 Signed-off-by: Ma Jun Suggested-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 52 ++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 9d2de6369b657..2e8db344899bd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,27 +1,24 @@ -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - ifeq ($(CC), gcc) GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) + +KERNEL_MAJ=$(VERSION) +KERNEL_PATCHLEVEL=$(PATCHLEVEL) +KERNEL_SUBLEVEL=$(SUBLEVEL) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL), $(KERNEL_SUBLEVEL)) + +kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifeq ($(call cc-ifversion, -le, 0408, y), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") @@ -32,6 +29,25 @@ export CONFIG_CC_IS_GCC=y export CONFIG_GCC_VERSION=$(GCCSTR) $(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") endif + +endif + +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) +$(error dma_resv->seq is missing. exit...) endif DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) From 5a8fb463184c484ad230b9e217380dd068075588 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Mon, 30 Jan 2023 16:52:42 +0800 Subject: [PATCH 0995/2070] drm/amdkcl: wrap code under CONFIG_DRM_AMD_DC_DSC_SUPPORT and CONFIG_DRM_AMD_DC_DCN It's cause by 'commit 05c1deaaaa92 ("drm/amd/display: move dp capability related logic to link_dp_capability")' 'commit 9a29f20c0621 ("drm/amd/display: move dp link training logic to link_dp_training")' Missing macro during code movement. link_dp_capability - missing CONFIG_DRM_AMD_DC_DCN macro link_dp_training - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_dp_training_8b_10b - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_dp_training_dpia - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from link_dp_dpia.c Signed-off-by: Horatio Zhang --- .../amd/display/dc/link/protocols/link_dp_capability.c | 8 +++++++- .../drm/amd/display/dc/link/protocols/link_dp_training.c | 3 +++ .../display/dc/link/protocols/link_dp_training_8b_10b.c | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index e12bf3dd3e464..279024773a422 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -161,11 +161,12 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) { /* Calculate offset for LTTPR closest to DPTX which is highest in the chain - * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 + * Offset is 1 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 */ return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } +#if defined(CONFIG_DRM_AMD_DC_DCN) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -185,6 +186,7 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) return 0; } +#endif static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) { @@ -249,6 +251,7 @@ static union dp_cable_id intersect_cable_id( return out; } +#if defined(CONFIG_DRM_AMD_DC_DCN) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -278,6 +281,7 @@ static uint32_t intersect_frl_link_bw_support( return supported_bw_in_kbps; } +#endif static enum clock_source_id get_clock_source_id(struct dc_link *link) { @@ -1244,6 +1248,7 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); +#if defined(CONFIG_DRM_AMD_DC_DCN) if (link->dc->caps.dp_hdmi21_pcon_support) { link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = @@ -1255,6 +1260,7 @@ static void get_active_converter_info( if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; } +#endif if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 08e2b572e0ff6..5bd7b68bc9314 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -777,8 +777,11 @@ void override_training_settings( lt_settings->pattern_for_eq = *overrides->pattern_for_eq; if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; +#endif /* Check DP tunnel LTTPR mode debug option. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 66d0fb1b9b9d2..ee1a1c755332c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -136,7 +136,9 @@ void decide_8b_10b_training_settings( lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); lt_settings->enhanced_framing = 1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT lt_settings->should_set_fec_ready = true; +#endif lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); From fc15642b53e652d2de3c3ef068eeeb6594b4d244 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Tue, 31 Jan 2023 12:53:17 +0800 Subject: [PATCH 0996/2070] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's cause by 'commit 05c1deaaaa92 ("drm/amd/display: move dp capability related logic to link_dp_capability")' Missing macro during code movement. link_dp_capability - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_edp_panel_control - fuction "decide_edp_link_settings" is changed to "dc_link_decide_edp_link_settings" Signed-off-by: Horatio Zhang --- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ++++++ .../drm/amd/display/dc/link/protocols/link_dp_capability.h | 2 ++ .../amd/display/dc/link/protocols/link_edp_panel_control.c | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 279024773a422..a1333e2c3e789 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -474,6 +474,7 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) return lttpr_max_link_rate; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) { enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; @@ -493,6 +494,7 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) return cable_max_link_rate; } +#endif static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) { @@ -837,6 +839,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -965,6 +968,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } return false; } +#endif static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) { @@ -2013,6 +2017,7 @@ static bool retrieve_link_cap(struct dc_link *link) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); @@ -2080,6 +2085,7 @@ static bool retrieve_link_cap(struct dc_link *link) } else link->wa_flags.dpia_forced_tbt3_mode = false; } +#endif if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 6e17f72a752f3..83c580791a62e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -81,10 +81,12 @@ bool link_decide_link_settings( bool edp_decide_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, enum dc_link_rate max_link_rate); +#endif enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 35fb431d8a47e..2fd602fbc2e8f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -382,7 +382,7 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); #else - decide_edp_link_settings(link, &link_setting, req_bw); + dc_link_decide_edp_link_settings(link, &link_setting, req_bw); #endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || From 6966b42ed0d048db699171fa683284e4f4e77bee Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 17:02:38 +0800 Subject: [PATCH 0997/2070] drm/amdkcl: update kcl macro for amdgpu_dm_atomic_check() It's caused by 52be8da751ab9476a0adfcd71d112850dae8248c "drm/amdgpu/display/mst: Fix mst_state->pbn_div and slot count assignments" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d991ffb3efd4e..bb83c8038f419 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12550,9 +12550,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS struct drm_dp_mst_topology_mgr *mgr; -#endif struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; #endif @@ -12892,7 +12890,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ @@ -12902,6 +12899,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + if (!mgr->mst_state ) + continue; +#endif drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { if (connector->index == mst_state->mgr->conn_base_id) { From a2abeda6586d4f03d871aa2ec263c37746cdc32e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 7 Feb 2023 17:24:27 +0800 Subject: [PATCH 0998/2070] drm/amdkcl: modify the naming of mst_port and port for kcl code It's caused by d6daeede3abe864d0dca1c74edf1af5a3a018297 "drm/amdgpu/display/mst: adjust the naming of mst_port and port of aconnector" The term (i.e. port & mst_port) are renamed to mst_output_port & mst_root respectively. So some code under kcl macro need to be renamed. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 966d6d05a94a8..c12e86321a002 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -278,7 +278,7 @@ fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, { int i; struct drm_dp_mst_topology_mgr *mst_mgr = - &aconnector->mst_port->mst_mgr; + &aconnector->mst_root->mst_mgr; mutex_lock(&mst_mgr->payload_lock); @@ -420,7 +420,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( if (!mst_mgr->mst_state) return false; - mst_port = aconnector->port; + mst_port = aconnector->mst_output_port; #if defined(CONFIG_DRM_AMD_DC_DCN) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); @@ -566,7 +566,7 @@ void dm_helpers_dp_mst_send_payload_allocation( new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); #else - mst_port = aconnector->port; + mst_port = aconnector->mst_output_port; if (!mst_mgr->mst_state) return; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 6b38436e9821b..7a46a7b7962a2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -148,13 +148,13 @@ static enum drm_connector_status dm_dp_mst_detect(struct drm_connector *connector, bool force) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - struct amdgpu_dm_connector *master = aconnector->mst_port; + struct amdgpu_dm_connector *master = aconnector->mst_root; enum drm_connector_status status = drm_dp_mst_detect_port( connector, &master->mst_mgr, - aconnector->port); + aconnector->mst_output_port); return status; } @@ -887,7 +887,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", - aconnector, connector->base.id, aconnector->mst_port); + aconnector, connector->base.id, aconnector->mst_root); if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps(connector, NULL); From 27b39bb1cdeee1c14e5566c50dfc440e61c8c5c9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 13:03:24 +0800 Subject: [PATCH 0999/2070] drm/amdkcl: check drm/drm_fbdev_generic.h whether exist It's caused by 8ab59da26bc0ae0abfcaabc4218c74827d154256 "drm/fb-helper: Move generic fbdev emulation into separate source file" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 055736d17b86a..ccdccb0e48d30 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -92,4 +92,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/amdgpu: add drm buddy support to amdgpu dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) + + dnl # + dnl # v6.1-rc2-542-g8ab59da26bc0 + dnl # drm/fb-helper: Move generic fbdev emulation into separate source file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + ]) From e0ea1cf69d63a17ceec9ad775f597a7059a9d3fc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 13:04:54 +0800 Subject: [PATCH 1000/2070] drm/amdkcl: for instance of ttm_resource struct, change member num_pages to size It's caused by 0f9cd1ea10d307cad221d6693b648a8956e812b0 "drm/ttm: fix bulk move handling v2" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 33ebbc27029bd..5fe0d8c16fc62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -683,11 +683,11 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, return r; abo = gem_to_amdgpu_bo(gobj); - dma_addr = kmalloc_array(abo->tbo.resource->num_pages, sizeof(dma_addr_t), GFP_KERNEL); + dma_addr = kmalloc_array(PFN_UP(abo->tbo.resource->size), sizeof(dma_addr_t), GFP_KERNEL); if (unlikely(dma_addr == NULL)) goto release_object; - for (i = 0; i < abo->tbo.resource->num_pages; i++) + for (i = 0; i < PFN_UP(abo->tbo.resource->size); i++) dma_addr[i] = args->addr + i * PAGE_SIZE; abo->dgma_import_base = args->addr; abo->dgma_addr = (void *)dma_addr; From 0246976749bf138c7422c518ea834373b10512bc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 16:45:45 +0800 Subject: [PATCH 1001/2070] drm/amdkcl: test struct migrate_vma whether has member fault_page It's caused by 16ce101db85d "mm/memory.c: fix race when faulting a device private page" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/migrate_vma_fault_page.m4 | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6c92cd7e44c74..7b959bcdef62c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -744,7 +744,9 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.src = buf; migrate.dst = migrate.src + npages; +#ifdef HAVE_MIGRATE_VMA_FAULT_PAGE migrate.fault_page = fault_page; +#endif scratch = (dma_addr_t *)(migrate.dst + npages); kfd_smi_event_migration_start(node, p->lead_thread->pid, diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5d694f8596d97..58dc39fad794f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -175,6 +175,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 new file mode 100644 index 0000000000000..406fa50e310c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v6.0-rc3-595-g16ce101db85d +dnl # mm/memory.c: fix race when faulting a device private page +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma mig = {0}; + struct page *fault_page; + mig.fault_page = fault_page; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, + [struct migrate_vma has fault_page]) + ]) + ]) +]) + From bd5c10045fe623a8bb281dba58a416e2634060e2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 2 Feb 2023 16:36:38 +0800 Subject: [PATCH 1002/2070] drm/amdkcl: move drm_buddy and drm_ttm_helper compile config from Makefile to subfile Create new files Makefile.drm_buddy and Makefile.drm_ttm_helper, and move drm_buddy and drm_ttm_helper compile config into them. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 16 +++------------- drivers/gpu/drm/amd/dkms/Makefile.drm_buddy | 6 ++++++ drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper | 8 ++++++++ 3 files changed, 17 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_buddy create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 2e8db344899bd..a0e67352e5b38 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -210,18 +210,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT endif endif -export CONFIG_DRM_TTM_HELPER=m -subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER -CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ - -include $(src)/include/kcl/backport/kcl_drm_gem.h \ - -DHAVE_CONFIG_H -amddrm_ttm_helper-y := drm_gem_ttm_helper.o -obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o - -export CONFIG_DRM_BUDDY=m -subdir-ccflags-y += -DCONFIG_DRM_BUDDY -CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H -amddrm_buddy-y := drm_buddy.o -obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o +include $(src)/amd/dkms/Makefile.drm_ttm_helper + +include $(src)/amd/dkms/Makefile.drm_buddy obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy new file mode 100644 index 0000000000000..208c05b48758d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy @@ -0,0 +1,6 @@ +export CONFIG_DRM_BUDDY=m + +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper new file mode 100644 index 0000000000000..b76db38d020a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper @@ -0,0 +1,8 @@ +export CONFIG_DRM_TTM_HELPER=m + +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o From 3e343649325c4240fcddb4a1f96863d250637691 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Feb 2023 17:48:59 +0800 Subject: [PATCH 1003/2070] drm/admkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by def6ddd09e22c65b4367fbf56310a8ed329a713a "drm/amd/display: break down dc_link.c" [why] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. [how] Restore macro CONFIG_DRM_AMD_DC_DSC_SUPPORT for these new file. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi drm/admkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by f57b3411356d482078ad46aadece1847e74e4c83 "drm/amd/display: do not set RX back to SST mode for non 0 mst stream count" A part of disable_link() is moved into disable_link_dp(), so these kcl macro is restored. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 13 ++++++++++++- .../gpu/drm/amd/display/dc/link/link_validation.c | 7 ++++++- .../drm/amd/display/dc/link/protocols/link_dp_phy.c | 2 ++ .../drm/amd/display/dc/link/protocols/link_dp_phy.h | 1 - 4 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index b4f46408a0005..4ffdaea679812 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -632,6 +632,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; @@ -644,6 +645,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); return result; } +#endif static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) { @@ -873,6 +875,7 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) { struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; @@ -896,6 +899,7 @@ bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) out: return result; } +#endif bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) { @@ -1720,7 +1724,9 @@ static void disable_link_dp(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_link_settings link_settings = link->cur_link_settings; +#endif if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->mst_stream_alloc_table.stream_count > 0) @@ -1737,12 +1743,13 @@ static void disable_link_dp(struct dc_link *link, if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, link_res, false); dp_set_fec_ready(link, link_res, false); } +#endif } static void disable_link(struct dc_link *link, @@ -2394,11 +2401,13 @@ void link_set_dpms_on( * will be automatically set at a later time when the video is enabled * (DP_VID_STREAM_EN = 1). */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) link_set_dsc_enable(pipe_ctx, true); } +#endif if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) dp_setup_replay(link, stream); @@ -2447,6 +2456,7 @@ void link_set_dpms_on( dc->hwss.enable_stream(pipe_ctx); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DPS PPS SDP (AKA "info frames") */ if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || @@ -2455,6 +2465,7 @@ void link_set_dpms_on( link_set_dsc_pps_packet(pipe_ctx, true, true); } } +#endif if (dc_is_dp_signal(pipe_ctx->stream->signal)) dp_set_hblank_reduction_on_rx(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index acdc162de5353..937586151e78e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -144,10 +144,13 @@ static bool dp_active_dongle_validate_timing( return false; } } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { +#else + if (dongle_caps->dfp_cap_ext.supported) { +#endif if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; @@ -242,10 +245,12 @@ uint32_t dp_link_bandwidth_kbps( */ link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dp_should_enable_fec(link)) { total_data_bw_efficiency_x10000 /= 100; total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; } +#endif break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c index 49521ac4b0e85..4ac00f9a2c183 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c @@ -135,6 +135,7 @@ void dp_set_drive_settings( dpcd_set_lane_settings(link, lt_settings, DPRX); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) { /* FEC has to be "set ready" before the link training. @@ -176,6 +177,7 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource return status; } +#endif void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h index 58e1544945825..3d70e9bd4a81d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h @@ -48,7 +48,6 @@ void dp_set_drive_settings( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings); - enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready); From 0c338d6a37f43c0da9360116905073e6f27a89e7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 18 Feb 2023 14:59:16 +0800 Subject: [PATCH 1004/2070] drm/amdkcl: add kcl_rbtee.h It's caused by 08fb97de03aa2205c6791301bd83a095abc1949c "drm/sched: Add FIFO sched policy to run queue" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/rbtree.m4 | 19 +++++ include/drm/gpu_scheduler.h | 1 + include/kcl/kcl_rbtree.h | 99 +++++++++++++++++++++++++ 5 files changed, 121 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/rbtree.m4 create mode 100644 include/kcl/kcl_rbtree.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3f13eff9ba0d1..33955b477811e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -100,4 +100,5 @@ */ #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 58dc39fad794f..f09e7488371ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -176,6 +176,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE + AC_AMDGPU_RB_ADD_CACHED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 new file mode 100644 index 0000000000000..0a29c2b864323 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_RB_ADD_CACHED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + rb_add_cached(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_RB_ADD_CACHED, 1, + [rb_add_cached is available]) + ]) + ]) +]) + + + diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 8dd05a0b7d1c5..c2bdee34f631c 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -29,6 +29,7 @@ #include #include #include +#include #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h new file mode 100644 index 0000000000000..6d3bf91f7b4f9 --- /dev/null +++ b/include/kcl/kcl_rbtree.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef AMDKCL_LINUX_RBTREE_H +#define AMDKCL_LINUX_RBTREE_H + +#include + +#ifndef HAVE_RB_ROOT_CACHED +/* + * Leftmost-cached rbtrees. + * + * We do not cache the rightmost node based on footprint + * size vs number of potential users that could benefit + * from O(1) rb_last(). Just not worth it, users that want + * this feature can always implement the logic explicitly. + * Furthermore, users that want to cache both pointers may + * find it a bit asymmetric, but that's ok. + */ +struct rb_root_cached { + struct rb_root rb_root; + struct rb_node *rb_leftmost; +}; + +#define RB_ROOT_CACHED (struct rb_root_cached) { {NULL, }, NULL } +#define rb_first_cached(root) (root)->rb_leftmost + +static inline struct rb_node * +rb_erase_cached(struct rb_node *node, struct rb_root_cached *root) +{ + struct rb_node *leftmost = NULL; + + if (root->rb_leftmost == node) + leftmost = root->rb_leftmost = rb_next(node); + + rb_erase(node, &root->rb_root); + + return leftmost; +} + +static inline void rb_insert_color_cached(struct rb_node *node, + struct rb_root_cached *root, + bool leftmost) +{ + if (leftmost) + root->rb_leftmost = node; + rb_insert_color(node, &root->rb_root); +} +#endif + +#ifndef HAVE_RB_ADD_CACHED +/* + * The below helper functions use 2 operators with 3 different + * calling conventions. The operators are related like: + * + * comp(a->key,b) < 0 := less(a,b) + * comp(a->key,b) > 0 := less(b,a) + * comp(a->key,b) == 0 := !less(a,b) && !less(b,a) + * + * If these operators define a partial order on the elements we make no + * guarantee on which of the elements matching the key is found. See + * rb_find(). + * + * The reason for this is to allow the find() interface without requiring an + * on-stack dummy object, which might not be feasible due to object size. + */ + +/** + * rb_add_cached() - insert @node into the leftmost cached tree @tree + * @node: node to insert + * @tree: leftmost cached tree to insert @node into + * @less: operator defining the (partial) node order + * + * Returns @node when it is the new leftmost, or NULL. + */ +static __always_inline struct rb_node * +rb_add_cached(struct rb_node *node, struct rb_root_cached *tree, + bool (*less)(struct rb_node *, const struct rb_node *)) +{ + struct rb_node **link = &tree->rb_root.rb_node; + struct rb_node *parent = NULL; + bool leftmost = true; + + while (*link) { + parent = *link; + if (less(node, parent)) { + link = &parent->rb_left; + } else { + link = &parent->rb_right; + leftmost = false; + } + } + + rb_link_node(node, parent, link); + rb_insert_color_cached(node, tree, leftmost); + + return leftmost ? node : NULL; +} +#endif + +#endif From 715692c2ca1cf5580ab497079ba75b77ab212bb2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 21 Feb 2023 14:41:33 +0800 Subject: [PATCH 1005/2070] drm/amdkcl: wrap the code under macro HAVE_DRM_MODE_CONFIG_FB_BASE It's caused by 7c99616e3fe7f35fe25bf6f5797267da29b4751e "drm: Remove drm_mode_config::fb_base" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index d0d99d095f96e..c69c42be619ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -255,7 +255,9 @@ static int amdgpufb_create(struct drm_fb_helper *helper, drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); /* setup aperture base/size for vesafb takeover */ +#ifdef HAVE_DRM_MODE_CONFIG_FB_BASE info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; +#endif info->apertures->ranges[0].size = adev->gmc.aper_size; /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 index add5633e0f26f..4b809aec8cd50 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -12,7 +12,25 @@ AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ ]) ]) +dnl # +dnl # v6.1-rc1-103-g7c99616e3fe7 drm: Remove drm_mode_config::fb_base +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_base = 0; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_BASE, 1, + [drm_mode_config->fb_base is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED + AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE ]) From f952da18bfb67b69da29aac66810098578274d01 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 15:04:42 +0800 Subject: [PATCH 1006/2070] drm/amdkcl: kcl-cleanup HAVE_LINUX_DMA_FENCE_H cleanup the HAVE_LINUX_DMA_FENCE_H and refactor related code Change-Id: I72ea2ff319cb741ff236dad4b8c30e770291807c Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 6 +- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 4 - drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c | 149 ------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../gpu/drm/amd/dkms/m4/dma-fence-headers.m4 | 18 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 +- include/kcl/header/linux/dma-fence-array.h | 6 +- include/kcl/header/linux/dma-fence.h | 11 -- include/kcl/kcl_dma_fence.h | 4 +- include/kcl/kcl_dma_fence_chain.h | 4 - include/kcl/kcl_fence.h | 44 ------ include/kcl/kcl_fence_array.h | 93 ----------- 13 files changed, 12 insertions(+), 337 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 delete mode 100644 include/kcl/header/linux/dma-fence.h delete mode 100644 include/kcl/kcl_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 13174dc68bf06..106cd064fab41 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,9 +5,9 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_io.o kcl_seq_file.o\ - kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ - kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ + kcl_io.o kcl_seq_file.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ + kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 1969d6e0f289c..6b962278954e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -238,11 +238,7 @@ EXPORT_SYMBOL(_kcl_fence_enable_signaling); */ void amdkcl_fence_init(void) { -#if defined(HAVE_LINUX_DMA_FENCE_H) _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); -#else - _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); -#endif } #if !defined(HAVE_DMA_FENCE_DESCRIBE) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c deleted file mode 100644 index d42a986ecfe1d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * fence-array: aggregate fences to be waited together - * - * Copyright (C) 2016 Collabora Ltd - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * Authors: - * Gustavo Padovan - * Christian König - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) -static void fence_array_cb_func(struct fence *f, struct fence_cb *cb); - -static const char *fence_array_get_driver_name(struct fence *fence) -{ - return "fence_array"; -} - -static const char *fence_array_get_timeline_name(struct fence *fence) -{ - return "unbound"; -} - -static void fence_array_cb_func(struct fence *f, struct fence_cb *cb) -{ - struct fence_array_cb *array_cb = - container_of(cb, struct fence_array_cb, cb); - struct fence_array *array = array_cb->array; - - if (atomic_dec_and_test(&array->num_pending)) - fence_signal(&array->base); - fence_put(&array->base); -} - -static bool fence_array_enable_signaling(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - struct fence_array_cb *cb = (void *)(&array[1]); - unsigned i; - - for (i = 0; i < array->num_fences; ++i) { - cb[i].array = array; - /* - * As we may report that the fence is signaled before all - * callbacks are complete, we need to take an additional - * reference count on the array so that we do not free it too - * early. The core fence handling will only hold the reference - * until we signal the array as complete (but that is now - * insufficient). - */ - fence_get(&array->base); - if (fence_add_callback(array->fences[i], &cb[i].cb, - fence_array_cb_func)) { - fence_put(&array->base); - if (atomic_dec_and_test(&array->num_pending)) - return false; - } - } - - return true; -} - -static bool fence_array_signaled(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - - return atomic_read(&array->num_pending) <= 0; -} - -static void fence_array_release(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - unsigned i; - - for (i = 0; i < array->num_fences; ++i) - fence_put(array->fences[i]); - - kfree(array->fences); - fence_free(fence); -} - -const struct fence_ops fence_array_ops = { - .get_driver_name = fence_array_get_driver_name, - .get_timeline_name = fence_array_get_timeline_name, - .enable_signaling = fence_array_enable_signaling, - .signaled = fence_array_signaled, - .wait = _kcl_fence_default_wait, - .release = fence_array_release, -}; - -/** - * fence_array_create - Create a custom fence array - * @num_fences: [in] number of fences to add in the array - * @fences: [in] array containing the fences - * @context: [in] fence context to use - * @seqno: [in] sequence number to use - * @signal_on_any [in] signal on any fence in the array - * - * Allocate a fence_array object and initialize the base fence with fence_init(). - * In case of error it returns NULL. - * - * The caller should allocte the fences array with num_fences size - * and fill it with the fences it wants to add to the object. Ownership of this - * array is take and fence_put() is used on each fence on release. - * - * If @signal_on_any is true the fence array signals if any fence in the array - * signals, otherwise it signals when all fences in the array signal. - */ -struct fence_array *fence_array_create(int num_fences, struct fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) -{ - struct fence_array *array; - size_t size = sizeof(*array); - - /* Allocate the callback structures behind the array. */ - size += num_fences * sizeof(struct fence_array_cb); - array = kzalloc(size, GFP_KERNEL); - if (!array) - return NULL; - - spin_lock_init(&array->lock); - fence_init(&array->base, &fence_array_ops, &array->lock, - context, seqno); - - array->num_fences = num_fences; - atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); - array->fences = fences; - - return array; -} -EXPORT_SYMBOL(fence_array_create); - -#endif /* !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a14c4f882552..c3561c6ac1d69 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -898,9 +898,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_DMA_FENCE_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_MAP_OPS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 deleted file mode 100644 index 843491bfe3aef..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 +++ /dev/null @@ -1,18 +0,0 @@ -dnl # -dnl # commit f54d1867005c3323f5d8ad83eed823e84226c429 -dnl # dma-buf: Rename struct fence to dma_fence -dnl # -AC_DEFUN([AC_AMDGPU_DMA_FENCE_HEADERS], [ - AS_IF([test $HAVE_LINUX_DMA_FENCE_H], [ - AC_KERNEL_DO_BACKGROUND([ - ]) - ], [ - dnl # - dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 - dnl # dma-buf/fence: add fence_array fences v6 - dnl # - AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) - AC_KERNEL_DO_BACKGROUND([ - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f09e7488371ad..d50528622daab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,7 +33,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU - AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 379b6e4e9c766..2c9f72c524583 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -32,10 +32,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) dnl # - dnl # v4.9-rc2-299-gf54d1867005c - dnl # dma-buf: Rename struct fence to dma_fence + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 dnl # - AC_KERNEL_CHECK_HEADERS([linux/dma-fence.h]) + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) dnl # dnl # v5.3-rc1-449-g52791eeec1d9 diff --git a/include/kcl/header/linux/dma-fence-array.h b/include/kcl/header/linux/dma-fence-array.h index 49bb1fcd2a798..bc3d2e4bbaca2 100644 --- a/include/kcl/header/linux/dma-fence-array.h +++ b/include/kcl/header/linux/dma-fence-array.h @@ -2,10 +2,10 @@ #ifndef _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ #define _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ -#if defined(HAVE_LINUX_DMA_FENCE_H) +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) #include_next -#elif defined(HAVE_LINUX_FENCE_ARRAY_H) -#include +#else +#include_next #endif #endif diff --git a/include/kcl/header/linux/dma-fence.h b/include/kcl/header/linux/dma-fence.h deleted file mode 100644 index d4bb6177302a3..0000000000000 --- a/include/kcl/header/linux/dma-fence.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER__LINUX_DMA_FENCE_H_H_ -#define _KCL_HEADER__LINUX_DMA_FENCE_H_H_ - -#if defined(HAVE_LINUX_DMA_FENCE_H) -#include_next -#else -#include -#endif - -#endif diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index cbf594a40d4de..20a014352f967 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -14,9 +14,11 @@ #define AMDKCL_DMA_FENCE_H #ifndef HAVE_DMA_FENCE_IS_CONTAINER -#include #include +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#endif /** * dma_fence_is_chain - check if a fence is from the chain subclass * @fence: the fence to test diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index b7b66a3b93c90..97900481479c5 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -14,11 +14,7 @@ #endif #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) -#ifdef HAVE_LINUX_DMA_FENCE_H #include -#else -#include -#endif #include #include diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index e8adf7bef1c57..a4a94e8a03e54 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -15,36 +15,6 @@ #include #include #include -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#define dma_fence_cb fence_cb -#define dma_fence_ops fence_ops -#define dma_fence_array fence_array -#define dma_fence fence -#define dma_fence_init fence_init -#define dma_fence_context_alloc fence_context_alloc -#define DMA_FENCE_TRACE FENCE_TRACE -#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT -#define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT -#define DMA_FENCE_FLAG_USER_BITS FENCE_FLAG_USER_BITS -#define dma_fence_wait fence_wait -#define dma_fence_get fence_get -#define dma_fence_put fence_put -#define dma_fence_is_signaled fence_is_signaled -#define dma_fence_signal fence_signal -#define dma_fence_signal_locked fence_signal_locked -#define dma_fence_get_rcu fence_get_rcu -#define dma_fence_array_create fence_array_create -#define dma_fence_add_callback fence_add_callback -#define dma_fence_remove_callback fence_remove_callback -#define dma_fence_enable_sw_signaling fence_enable_sw_signaling -#define dma_fence_default_wait fence_default_wait -#define dma_fence_free fence_free -#define dma_fence_get_rcu_safe fence_get_rcu - -#define dma_fence_set_error fence_set_error -#endif #if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) @@ -81,20 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* commit v4.5-rc3-715-gb47bcb93bbf2 - * fall back to HAVE_LINUX_DMA_FENCE_H check directly - * as it's hard to detect the implementation in kernel - */ -#if !defined(HAVE_LINUX_DMA_FENCE_H) -static inline bool dma_fence_is_later(struct dma_fence *f1, struct dma_fence *f2) -{ - if (WARN_ON(f1->context != f2->context)) - return false; - - return (int)(f1->seqno - f2->seqno) > 0; -} -#endif - /* * commit v4.18-rc2-533-g418cc6ca0607 * dma-fence: Allow wait_any_timeout for all fences) diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h deleted file mode 100644 index 060edd1567fda..0000000000000 --- a/include/kcl/kcl_fence_array.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * this file is the copy of include/linux/fence-array.h, don't modify it - * - * fence-array: aggregates fence to be waited together - * - * Copyright (C) 2016 Collabora Ltd - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * Authors: - * Gustavo Padovan - * Christian König - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef AMDKCL_FENCE_ARRAY_H -#define AMDKCL_FENCE_ARRAY_H - -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#if !defined(HAVE_LINUX_FENCE_ARRAY_H) -#include - -/** - * struct fence_array_cb - callback helper for fence array - * @cb: fence callback structure for signaling - * @array: reference to the parent fence array object - */ -struct fence_array_cb { - struct fence_cb cb; - struct fence_array *array; -}; - -/** - * struct fence_array - fence to represent an array of fences - * @base: fence base class - * @lock: spinlock for fence handling - * @num_fences: number of fences in the array - * @num_pending: fences in the array still pending - * @fences: array of the fences - */ -struct fence_array { - struct fence base; - - spinlock_t lock; - unsigned num_fences; - atomic_t num_pending; - struct fence **fences; -}; - -extern const struct fence_ops fence_array_ops; - -/** - * to_fence_array - cast a fence to a fence_array - * @fence: fence to cast to a fence_array - * - * Returns NULL if the fence is not a fence_array, - * or the fence_array otherwise. - */ -static inline struct fence_array *to_fence_array(struct fence *fence) -{ - if (fence->ops != &fence_array_ops) - return NULL; - - return container_of(fence, struct fence_array, base); -} - -struct fence_array *fence_array_create(int num_fences, struct fence **fences, - u64 context, unsigned seqno, - bool signal_on_any); -/** - * dma_fence_is_array - check if a fence is from the array subclass - * @fence: the fence to test - * - * Return true if it is a dma_fence_array and false otherwise. - */ -static inline bool dma_fence_is_array(struct dma_fence *fence) -{ - return false; -} - -#endif -#endif - -#endif /* __LINUX_FENCE_ARRAY_H */ From 0ee5afa9befd0b9fe3ee7551ddb3988f253752f2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 9 Feb 2023 17:19:30 +0800 Subject: [PATCH 1007/2070] drm/amdkcl: Fix the dma_resv.seq checking bug Fix the dma_resv->seq checking bug Change-Id: I0ea3efe3d36d1e3996623f5f7fc5de16702516c9 Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 98 ++++++++++--------------- 1 file changed, 38 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 8cf888eb3a6b4..f65379d76636f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -1,78 +1,57 @@ dnl # -dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex -dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround dnl # -AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_resv *obj = NULL; - seqcount_ww_mutex_init(&obj->seq, &obj->lock); + struct dma_resv *resv = NULL; + resv->fences = NULL; ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, - [dma_resv->seq is seqcount_ww_mutex_t]) - AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, - [dma_resv->seq is available]) + dnl # this is the latest kernel + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1,[dma_resv->fences is available]) ], [ dnl # - dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates - dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv - dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex + dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key dnl # AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_LINUX_DMA_RESV_H #include - #else - #include - #endif ], [ - #ifdef HAVE_LINUX_DMA_RESV_H - struct dma_resv *resv = NULL; - #else - struct reservation_object *resv = NULL; - #endif - write_seqcount_begin(&resv->seq); + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, [dma_resv->seq is seqcount_ww_mutex_t]) ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, - [dma_resv->seq is available]) - ],[ - dnl # - dnl # dma_resv->seq is dropped since kernle 5.18.0 - dnl # So trigger the bug only for the kernel_version < 5.18.0 - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) - int this_is_bug; - this_is_bug = 0; - #else - this_is_not_bug(); - #endif - ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, - [bug for missing dma_resv->seq]) - ]) + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1,[dma_resv->seq is available]) + ],[ + dnl # + dnl # Trigger the bug for dma_resv->seq definition + dnl # + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, [Reporting dma_resv->seq bug]) ]) ]) - ]) -]) - -dnl # -dnl # v5.18-rc1-237-g047a1b877ed4 -dnl # dma-buf & drm/amdgpu: remove dma_resv workaround -dnl # -AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct dma_resv *resv = NULL; - resv->fences = NULL; - ], [ - AC_DEFINE(HAVE_DMA_RESV_FENCES, 1, - [dma_resv->fences is available]) ]) ]) ]) @@ -99,7 +78,6 @@ AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ ]) AC_DEFUN([AC_AMDGPU_DMA_RESV], [ - AC_AMDGPU_DMA_RESV_SEQ AC_AMDGPU_DMA_RESV_FENCES AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) From 15d5782c93463c9a7061f897ba9666f47e2701b7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 11:27:07 +0800 Subject: [PATCH 1008/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DEVICE_DRIVER_FEATURES Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +------------- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 19 ------------------- 4 files changed, 1 insertion(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6ab8cdeb5c590..5e9f825caeffa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2452,17 +2452,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; -#else - /* warn the user if they mix atomic and non-atomic capable GPUs */ - if ((amdgpu_kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) - DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); - /* support atomic early so the atomic debugfs stuff gets created */ - if (supports_atomic) - amdgpu_kms_driver.driver_features |= DRIVER_ATOMIC; -#endif kcl_pci_create_measure_file(pdev); kcl_pci_configure_extended_tags(pdev); @@ -3136,10 +3127,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { static struct drm_driver amdgpu_kms_driver = { .driver_features = - 0 -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES - | DRIVER_ATOMIC -#endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + DRIVER_ATOMIC | DRIVER_HAVE_IRQ #ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED | DRIVER_IRQ_SHARED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index e110383ec40e7..f01f385091083 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -77,11 +77,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; } -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES ddev->driver_features &= ~DRIVER_ATOMIC; -#else - ddev->driver->driver_features &= ~DRIVER_ATOMIC; -#endif adev->cg_flags = 0; adev->pg_flags = 0; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c3561c6ac1d69..93c5a5e414fc6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -289,12 +289,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* dev_device->driver_features is available */ -#define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 - -/* struct drm_device has fb_helper member */ -#define HAVE_DRM_DEVICE_FB_HELPER 1 - /* drm_device->filelist_mutex is available */ #define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 7ea0061caa47e..929e3edc5f603 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -1,21 +1,3 @@ -dnl # -dnl # commit v4.19-rc1-194-g18ace11f87e6 -dnl # drm: Introduce per-device driver_features -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_device *ddev = NULL; - ddev->driver_features = 0; - ],[ - AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, - [dev_device->driver_features is available]) - ]) - ]) -]) - dnl # dnl # commit v5.5-rc2-1419-g7e13ad896484 dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count @@ -35,6 +17,5 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ - AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) From e22d55db809c9cab1b6acb2443c2f400f86cc35b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 12:14:45 +0800 Subject: [PATCH 1009/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DEV_ENTER also remove macro HAVE_DRM_DEV_IS_UNPLUGGED Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 73 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 6 -- drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 | 19 ----- .../drm/amd/dkms/m4/drm-dev-is-unplugged.m4 | 21 ------ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 - include/kcl/kcl_drm_drv.h | 70 ------------------ 7 files changed, 1 insertion(+), 192 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 delete mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 106cd064fab41..fd8ef6b20a372 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o + kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c deleted file mode 100644 index 8014069a7c654..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org - * - * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Author Rickard E. (Rik) Faith - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef HAVE_DRM_DEV_ENTER -#include -#include - -DEFINE_STATIC_SRCU(drm_unplug_srcu); - -/** - * drm_dev_enter - Enter device critical section - * @dev: DRM device - * @idx: Pointer to index that will be passed to the matching drm_dev_exit() - * - * This function marks and protects the beginning of a section that should not - * be entered after the device has been unplugged. The section end is marked - * with drm_dev_exit(). Calls to this function can be nested. - * - * Returns: - * True if it is OK to enter the section, false otherwise. - */ -bool drm_dev_enter(struct drm_device *dev, int *idx) -{ - *idx = srcu_read_lock(&drm_unplug_srcu); - - if (atomic_read(&dev->unplugged)) { - srcu_read_unlock(&drm_unplug_srcu, *idx); - return false; - } - - return true; -} -EXPORT_SYMBOL(drm_dev_enter); - -/** - * drm_dev_exit - Exit device critical section - * @idx: index returned from drm_dev_enter() - * - * This function marks the end of a section that should not be entered after - * the device has been unplugged. - */ -void drm_dev_exit(int idx) -{ - srcu_read_unlock(&drm_unplug_srcu, idx); -} -EXPORT_SYMBOL(drm_dev_exit); - -#endif /* HAVE_DRM_DEV_ENTER */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 93c5a5e414fc6..637fe5d21ead5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -298,12 +298,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_enter() is available */ -#define HAVE_DRM_DEV_ENTER 1 - -/* drm_dev_is_unplugged() is available */ -#define HAVE_DRM_DEV_IS_UNPLUGGED 1 - /* drm_dev_put() is available */ #define HAVE_DRM_DEV_PUT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 deleted file mode 100644 index 4ac5579c0f5c2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 +++ /dev/null @@ -1,19 +0,0 @@ -dnl # -dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 -dnl # drm: Use srcu to protect drm_device.unplugged -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_ENTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - ], [ - drm_dev_enter(NULL, NULL); - ], [drm_dev_enter], [drivers/gpu/drm/drm_drv.c], [ - AC_DEFINE(HAVE_DRM_DEV_ENTER, 1, [drm_dev_enter() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 deleted file mode 100644 index 4a05d157649e4..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 -dnl # drm: Use srcu to protect drm_device.unplugged -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_IS_UNPLUGGED], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #endif - #ifdef HAVE_DRM_DRM_DRV_H - #include - #endif - ], [ - drm_dev_is_unplugged(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DEV_IS_UNPLUGGED, 1, - [drm_dev_is_unplugged() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d50528622daab..a96e8608cecb0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -124,8 +124,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA - AC_AMDGPU_DRM_DEV_ENTER - AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h deleted file mode 100644 index 0360a07613727..0000000000000 --- a/include/kcl/kcl_drm_drv.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * Copyright (c) 2009-2010, Code Aurora Forum. - * Copyright 2016 Intel Corp. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef __KCL_KCL_DRM_DRV_H__ -#define __KCL_KCL_DRM_DRV_H__ - -#include -#include - -#ifndef HAVE_DRM_DEV_ENTER -/* Copied from include/drm/drm_drv.h*/ - -bool drm_dev_enter(struct drm_device *dev, int *idx); -void drm_dev_exit(int idx); - -#ifndef HAVE_DRM_DEV_IS_UNPLUGGED -/** - * drm_dev_is_unplugged - is a DRM device unplugged - * @dev: DRM device - * - * This function can be called to check whether a hotpluggable is unplugged. - * Unplugging itself is singalled through drm_dev_unplug(). If a device is - * unplugged, these two functions guarantee that any store before calling - * drm_dev_unplug() is visible to callers of this function after it completes - * - * WARNING: This function fundamentally races against drm_dev_unplug(). It is - * recommended that drivers instead use the underlying drm_dev_enter() and - * drm_dev_exit() function pairs. - */ -static inline bool drm_dev_is_unplugged(struct drm_device *dev) -{ - int idx; - - if (drm_dev_enter(dev, &idx)) { - drm_dev_exit(idx); - return false; - } - - return true; -} -#endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ -#endif /* HAVE_DRM_DEV_ENTER */ - -#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY -extern bool drm_firmware_drivers_only(void); -#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ - -#endif From b5cde81566f6f09890d6761a6b74faf88e8d7cce Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 10:33:59 +0800 Subject: [PATCH 1010/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_PRINT_H Also removed related macro HAVE_DRM_PRINTER_PREFIX Change-Id: Iac8228a7ce9011fbb67423ea55d811e3e810717d Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 34 ---------------- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 --- drivers/gpu/drm/amd/dkms/m4/drm_print.m4 | 21 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/header/drm/drm_print.h | 2 - include/kcl/kcl_drm_print.h | 46 ---------------------- 7 files changed, 116 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 95e75be1d5ee8..68e4abe6470c6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -26,40 +26,6 @@ #include #include -#if !defined(HAVE_DRM_DRM_PRINT_H) -void drm_printf(struct drm_printer *p, const char *f, ...) -{ - struct va_format vaf; - va_list args; - - va_start(args, f); - vaf.fmt = f; - vaf.va = &args; - p->printfn(p, &vaf); - va_end(args); -} -EXPORT_SYMBOL(drm_printf); - -void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf) -{ - seq_printf(p->arg, "%pV", vaf); -} -EXPORT_SYMBOL(__drm_printfn_seq_file); -#endif - -#if !defined(HAVE_DRM_PRINTER_PREFIX) -void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) -{ -#ifndef HAVE_DRM_DRM_PRINT_H - printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", p->prefix, vaf); -#else - printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", "no prefix", vaf); -#endif -} -EXPORT_SYMBOL(__drm_printfn_debug); -#endif - - #if !defined(HAVE_DRM_ERR_MACRO) void kcl_drm_err(const char *format, ...) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 637fe5d21ead5..c5160240fc5a9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -515,9 +515,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PLANE_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PRINT_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 @@ -697,9 +694,6 @@ /* drm_prime_sg_to_dma_addr_array() is available */ #define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 -/* drm_printer->prefix is available */ -#define HAVE_DRM_PRINTER_PREFIX 1 - /* drm_print_bits() is available */ #define HAVE_DRM_PRINT_BITS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ccdccb0e48d30..5004222733f88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -9,12 +9,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) - dnl # - dnl # commit v4.9-rc2-477-gd8187177b0b1 - dnl # drm: add helper for printing to log or seq_file - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_print.h]) - dnl # dnl # commit v5.0-rc1-342-gfcd70cd36b9b dnl # drm: Split out drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 deleted file mode 100644 index 3c4a306d53cd3..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # v4.9-rc2-477-gd8187177b0b1 drm: add helper for printing to log or seq_file -dnl # -AC_DEFUN([AC_AMDGPU_DRM_PRINTER], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([test $HAVE_DRM_DRM_PRINT_H], [ - dnl # - dnl # v4.9-rc8-1738-gb5c3714fe878 drm/mm: Convert to drm_printer - dnl # v4.9-rc8-1737-g3d387d923c18 drm/printer: add debug printer - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_printer *p = NULL; - p->prefix = NULL; - ], [ - AC_DEFINE(HAVE_DRM_PRINTER_PREFIX, 1, [drm_printer->prefix is available]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a96e8608cecb0..b0099c0613588 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -58,7 +58,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT - AC_AMDGPU_DRM_PRINTER AC_AMDGPU_DRM_PRINT_BITS AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL diff --git a/include/kcl/header/drm/drm_print.h b/include/kcl/header/drm/drm_print.h index 0f1db6376a8a3..a6734c48c8eb5 100644 --- a/include/kcl/header/drm/drm_print.h +++ b/include/kcl/header/drm/drm_print.h @@ -2,9 +2,7 @@ #ifndef _KCL_HEADER_DRM_PRINT_H_H_ #define _KCL_HEADER_DRM_PRINT_H_H_ -#if defined(HAVE_DRM_DRM_PRINT_H) #include_next -#endif #include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a726abd73190d..71a5b6f419e46 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -29,52 +29,6 @@ #include #include -#if !defined(HAVE_DRM_DRM_PRINT_H) -/* Copied from d8187177b0b1 include/drm/drm_print.h */ -struct drm_printer { - void (*printfn)(struct drm_printer *p, struct va_format *vaf); - void *arg; - const char *prefix; -}; - -void drm_printf(struct drm_printer *p, const char *f, ...); -void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf); -static inline struct drm_printer drm_seq_file_printer(struct seq_file *f) -{ - struct drm_printer p = { - .printfn = __drm_printfn_seq_file, - .arg = f, - }; - return p; -} -#endif - -/* Copied from 3d387d923c18 include/drm/drm_print.h */ -#if !defined(HAVE_DRM_PRINTER_PREFIX) -extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); - -static inline struct drm_printer drm_debug_printer(const char *prefix) -{ - struct drm_printer p = { - .printfn = __drm_printfn_debug, -#ifndef HAVE_DRM_DRM_PRINT_H - .prefix = prefix -#endif - }; - return p; -} - -static inline -void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) -{ -#ifndef HAVE_DRM_DRM_PRINT_H - drm_mm_debug_table((struct drm_mm *)mm, p->prefix); -#else - drm_mm_debug_table((struct drm_mm *)mm, "no prefix"); -#endif -} -#endif - #ifndef _DRM_PRINTK #define _DRM_PRINTK(once, level, fmt, ...) \ do { \ From 7f4c2d1b42e1a5332adb421aa3fea4acd32b638d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 13 Feb 2023 13:03:04 +0800 Subject: [PATCH 1011/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 -- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 - .../kcl_amdgpu_drm_gem_framebuffer_helper.h | 30 -------------- .../backport/kcl_drm_gem_framebuffer_helper.c | 40 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 10 ----- 8 files changed, 6 insertions(+), 90 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h delete mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index c955c3272d25e..d0f25441e5c03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1205,7 +1205,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, struct drm_gem_object *obj) { int ret; - kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + rfb->base.obj[0] = obj; drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); @@ -1219,7 +1219,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; return ret; } @@ -1232,7 +1232,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, { int ret; - kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + rfb->base.obj[0] = obj; drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ @@ -1263,7 +1263,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index c69c42be619ef..09b60070309e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -304,7 +304,7 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb drm_gem_object_put(obj); #endif amdgpufb_destroy_pinned_object(obj); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 04e069038c84e..db30f16307ce4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -303,9 +303,6 @@ struct amdgpu_display_funcs { struct amdgpu_framebuffer { struct drm_framebuffer base; -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - struct drm_gem_object *obj; -#endif uint64_t tiling_flags; bool tmz_surface; diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index fa78abd428129..f5b5d3b9a2d33 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o + kcl_drm_gem.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 33955b477811e..3ab3ab68f5104 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -65,7 +65,6 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" -#include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h deleted file mode 100644 index bbd3326b824bf..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ -#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ - -#include -#include "amdgpu.h" - -static inline -void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) -{ -#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - if (fb) - fb->obj[index] = obj; -#else - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)index; /* for compile un-used warning */ - if (afb) - afb->obj = obj; -#endif -} - -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -/* Copied from include/drm/drm_gem_framebuffer_helper.h */ -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane); -void drm_gem_fb_destroy(struct drm_framebuffer *fb); -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle); -#endif - -#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c deleted file mode 100644 index 1f68cf8bbe2b3..0000000000000 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * drm gem framebuffer helper functions - * - * Copyright (C) 2017 Noralf Trønnes - */ - -#include - -/* Copied from drivers/gpu/drm/drm_gem_framebuffer_helper.c and modified for KCL */ -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane) -{ - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)plane; /* for compile un-used warning */ - if (afb) - return afb->obj; - else - return NULL; -} - -void drm_gem_fb_destroy(struct drm_framebuffer *fb) -{ - struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - - drm_gem_object_put(amdgpu_fb->obj); - - drm_framebuffer_cleanup(fb); - kfree(fb); -} - -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle) -{ - struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - - return drm_gem_handle_create(file, amdgpu_fb->obj, handle); -} -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c5160240fc5a9..917c3f82b136b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -490,16 +490,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_DRV_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_ENCODER_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FILE_H 1 - -/* Define to 1 if you have the header file. - */ -#define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 From dd7200e87bdce7a265eab62d797bf051815cc960 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:11:01 +0800 Subject: [PATCH 1012/2070] drm/amdkcl: kcl-cleanup HAVE_TTM_SG_TT_INIT Change-Id: Ib30a80618a524ae9f1b68ce8fdd7a73c87898204 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/ttm/ttm_tt.c | 5 +---- include/kcl/kcl_drm_prime.h | 12 ------------ 3 files changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 917c3f82b136b..f4d651bfa6d59 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1159,9 +1159,6 @@ /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 -/* ttm_sg_tt_init() is available */ -#define HAVE_TTM_SG_TT_INIT 1 - /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 1857075d429bb..19673c3c112b2 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -217,14 +217,11 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, ttm_tt_init_fields(ttm, bo, page_flags, caching, 0); -#ifndef HAVE_TTM_SG_TT_INIT - ret = ttm_dma_tt_alloc_page_directory(ttm); -#else if (page_flags & TTM_TT_FLAG_EXTERNAL) ret = ttm_sg_tt_alloc_page_directory(ttm); else ret = ttm_dma_tt_alloc_page_directory(ttm); -#endif + if (ret) { pr_err("Failed allocating page table\n"); return -ENOMEM; diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 2c5e972520576..c55e8d05c0318 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -12,19 +12,7 @@ static inline int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, int max_entries) { -#ifdef HAVE_TTM_SG_TT_INIT return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); -#else - /* - * the page array stands right next to dma address array, - * so get the page array pointer directly by max_entries offset - * refer to ttm_sg_tt_init() for initial array allocation and - * c67e62790f5c drm/prime: split array import functions v4 for - * the change to drm_prime_sg_to_page_addr_arrays() - */ - struct page **pages = (void*)((unsigned long)addrs - max_entries*sizeof(dma_addr_t)); - return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); -#endif } #endif /* HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY */ #endif From 69912e99edea3a1d991b6eb0b34c2cda0ea7a6d4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 16 Feb 2023 15:14:08 +0800 Subject: [PATCH 1013/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 30 +++---------------- .../backport/kcl_drm_dp_mst_helper_backport.h | 2 -- 3 files changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f4d651bfa6d59..393090f81ee2d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -355,9 +355,6 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* drm_dp_atomic_find_vcpi_slots() is available */ -#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 - /* drm_dp_atomic_release_time_slots() is available */ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index f19d5bf4ea976..c89bcdbf10edd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -4,7 +4,7 @@ dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) @@ -14,32 +14,10 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ #endif ], [ int retval; - retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); - ], [drm_dp_atomic_find_vcpi_slots], [drivers/gpu/drm/drm_dp_mst_topology.c], [ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, - [drm_dp_atomic_find_vcpi_slots() is available]) + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); ], [ - dnl # - dnl # commit dad1c2499a8f6d7ee01db8148f05ebba73cc41bd - dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots - dnl # - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif - ], [ - int retval; - retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, - [drm_dp_atomic_find_vcpi_slots() wants 5args]) - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, - [drm_dp_atomic_find_vcpi_slots() is available]) - ]) + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index edac58606beb9..97af03bd3e628 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -38,7 +38,6 @@ int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif -#if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, @@ -63,7 +62,6 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, } #define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ #if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) static inline From 9fc3c1ece8140185f8e25d74b1147231ff5fb939 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 20 Feb 2023 15:35:34 +0800 Subject: [PATCH 1014/2070] drm/amdkcl: Fix the "array-bound" warning info when compile conftest.c There is a bug in gcc12 which caused the warning info below: "array subscript 0 is outside array bounds of 'atomic_t[0]' [-Werror=array-bounds]" To fix this issue, we add "-Wno-error=array-bounds" to ingore this warning. The same problem in the kernel has been fixed by the following patch: f0be87c42cbd gcc-12: disable '-Warray-bounds' universally for now Change-Id: If810c289579311bb0aafd43d2045e965dd710052 Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b0099c0613588..3a32640e324f8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -383,7 +383,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From b814ee8ac05907685c3e0c9e40950c8fb177d369 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Mar 2023 17:30:47 +0800 Subject: [PATCH 1015/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To remove following compiling warning, wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS. /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c: In function ‘dm_helpers_dp_mst_send_payload_allocation’: /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c:460:13: warning: unused variable ‘ret’ [-Wunused-variable] 460 | int ret = 0; | ^~~ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index c12e86321a002..924dd1f66237d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -553,7 +553,9 @@ void dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) int ret = 0; +#endif aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; From 9db77704a3b925d536dc7768ccc28eb15c1a328c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 7 Mar 2023 09:36:24 +0800 Subject: [PATCH 1016/2070] drm/amdkcl: wrap code under macro RB_ROOT_CACHED Signed-off-by: Asher Song --- include/kcl/kcl_rbtree.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h index 6d3bf91f7b4f9..6a0f687a0801e 100644 --- a/include/kcl/kcl_rbtree.h +++ b/include/kcl/kcl_rbtree.h @@ -4,7 +4,7 @@ #include -#ifndef HAVE_RB_ROOT_CACHED +#ifndef RB_ROOT_CACHED /* * Leftmost-cached rbtrees. * From 4f883854ef9b4c46ee3248953c1e3bf47c0fd42f Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 10 Aug 2022 18:53:07 -0400 Subject: [PATCH 1017/2070] drm/amdkfd: Try to schedule bottom half on same core On systems that support SMT (hyperthreading) schedule the bottom half of the KFD interrupt handler on the same core. This makes it possible to reserve a core for interrupt handling and have the bottom half run on that same core. On systems without SMT, pick another core in the same NUMA node, as before. Use for_each_cpu_wrap instead of open-coding it. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 3ffd214b973ef..ad4b19a4c1a4d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_vi.h" From d949bc749763a849a950f159053bbf9fd9bec3f2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:10:18 +0800 Subject: [PATCH 1018/2070] drm/amdkcl: kcl-cleanup HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP Change-Id: I6e00c1b00b4640cbc0cf29649845d736a00e572c Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 72 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/config/config.h | 9 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/pcie-get-speed-width-cap.m4 | 12 ---- include/kcl/backport/kcl_pci_backport.h | 4 -- include/kcl/kcl_pci.h | 13 ---- 7 files changed, 113 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 96fc94dc7c244..c62f0a2f9d6e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -21,84 +21,12 @@ #include #include -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -/* - * pcie_get_speed_cap - query for the PCI device's link speed capability - * @dev: PCI device to query - * - * Query the PCI device speed capability. Return the maximum link speed - * supported by the device. - */ -enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) -{ - u32 lnkcap2, lnkcap; - - /* - * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link - * Speeds Vector in Link Capabilities 2 when supported, falling - * back to Max Link Speed in Link Capabilities otherwise. - */ - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); - if (lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - return PCI_SPEED_UNKNOWN; - } - - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) { - if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - } - - return PCI_SPEED_UNKNOWN; -} - -/** - * pcie_get_width_cap - query for the PCI device's link width capability - * @dev: PCI device to query - * - * Query the PCI device width capability. Return the maximum link width - * supported by the device. - */ -enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) -{ - u32 lnkcap; - - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) - return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; - - return PCIE_LNK_WIDTH_UNKNOWN; -} -#endif - enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_width_cap); -void amdkcl_pci_init(void) -{ -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) - _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); - _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); -#endif -} - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev) { diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 8304f79c8f18c..f2b0b8a5f736f 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -8,7 +8,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); -extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); @@ -21,7 +20,6 @@ int __init amdkcl_init(void) amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); - amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 393090f81ee2d..1f967dcac51f5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -972,15 +972,6 @@ /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 -/* pcie_bandwidth_available() is available */ -#define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 - -/* pci_enable_atomic_ops_to_root() exist */ -#define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 - -/* pcie_get_speed_cap() and pcie_get_width_cap() exist */ -#define HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3a32640e324f8..c432868860ca4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -19,7 +19,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER - AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 deleted file mode 100644 index 905b62bc15628..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 +++ /dev/null @@ -1,12 +0,0 @@ -dnl # -dnl # commit 576c7218a1546e0153480b208b125509cec71470 -dnl # PCI: Export pcie_get_speed_cap and pcie_get_width_cap -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pcie_get_speed_cap pcie_get_width_cap], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP, 1, - [pcie_get_speed_cap() and pcie_get_width_cap() exist]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 2cf66ef4aa69f..f75f4fbd7e7fa 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -6,10 +6,6 @@ #include #include -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -#define pcie_get_speed_cap _kcl_pcie_get_speed_cap -#endif - #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) #define AMDKCL_PCIE_BRIDGE_PM_USABLE #endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 3404986968bbd..11d939a6168e2 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -97,27 +97,14 @@ 0) #endif -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); -extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); -#endif - static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) { -#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) return pcie_get_speed_cap(dev); -#else - return _kcl_pcie_get_speed_cap(dev); -#endif } static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) { -#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) return pcie_get_width_cap(dev); -#else - return _kcl_pcie_get_width_cap(dev); -#endif } #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) From 5efa4055b89371a5f9541cf70bc2ba00c99589d2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 23 Feb 2023 11:02:14 +0800 Subject: [PATCH 1019/2070] drm/amdkcl:kcl-cleanup HAVE_DRM_GEM_MAP_ATTACH_2ARGS Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 8 +------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 2 -- drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 | 14 -------------- 4 files changed, 1 insertion(+), 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 85f34e7b3d7e3..b63b0c06474bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -149,9 +149,6 @@ __dma_resv_make_exclusive(struct dma_resv *obj) * 0 on success or a negative error code on failure. */ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, -#ifndef HAVE_DRM_GEM_MAP_ATTACH_2ARGS - struct device *target_dev, -#endif struct dma_buf_attachment *attach) { struct drm_gem_object *obj = dma_buf->priv; @@ -159,11 +156,8 @@ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); long r; -#ifdef HAVE_DRM_GEM_MAP_ATTACH_2ARGS r = drm_gem_map_attach(dma_buf, attach); -#else - r = drm_gem_map_attach(dma_buf, target_dev, attach); -#endif + if (r) return r; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1f967dcac51f5..a4878ef5a2d8d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -569,9 +569,6 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 -/* drm_gem_map_attach() wants 2 arguments */ -/* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ - /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index d4f139e428849..86159c3f96200 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -52,8 +52,6 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ ],[ AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, [dma_buf->dynamic_mapping is not available]) - - AC_AMDGPU_DRM_GEM_MAP_ATTACH ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 deleted file mode 100644 index 031d62f21740f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # commit v4.17-rc3-491-ga19741e5e5a9 -dnl # dma_buf: remove device parameter from attach callback v2 -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_MAP_ATTACH], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_gem_map_attach(NULL, NULL); - ], [drm_gem_map_attach], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_GEM_MAP_ATTACH_2ARGS, 1, - [drm_gem_map_attach() wants 2 arguments]) - ]) -]) From 66427177ed87b73446c94cb2dc50a5f4bb045912 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 24 Feb 2023 13:11:05 +0800 Subject: [PATCH 1020/2070] drm/amdkcl:kcl-cleanup CONFIG_DRM_AMD_DC_DSC_SUPPORT Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Reviewed-by: Folra Cui --- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 5 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ----- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ----- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ---- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ------- .../gpu/drm/amd/display/dc/core/dc_resource.c | 6 ---- .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 --- drivers/gpu/drm/amd/display/dc/dc.h | 4 --- drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 -- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 -- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 --- .../display/dc/dcn201/dcn201_link_encoder.c | 2 -- .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 -- .../display/dc/dio/dcn20/dcn20_link_encoder.c | 6 ---- .../display/dc/dio/dcn20/dcn20_link_encoder.h | 2 -- .../dc/dio/dcn20/dcn20_stream_encoder.c | 6 ---- .../dc/dio/dcn30/dcn30_dio_link_encoder.c | 2 -- .../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 4 --- .../dc/dio/dcn301/dcn301_dio_link_encoder.c | 2 -- .../dc/dio/dcn31/dcn31_dio_link_encoder.c | 6 ---- .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 6 ---- .../dc/dio/dcn32/dcn32_dio_link_encoder.c | 2 -- .../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 3 -- .../dc/dio/dcn321/dcn321_dio_link_encoder.c | 2 -- .../dc/dio/virtual/virtual_stream_encoder.c | 8 ----- .../amd/display/dc/dml/display_mode_enums.h | 2 -- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 2 -- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 -- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 2 -- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 -- .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 -- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 2 -- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ----- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn20/dcn20_init.c | 4 --- .../amd/display/dc/hwss/dcn21/dcn21_init.c | 2 -- .../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 -- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_init.c | 2 -- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 6 ---- .../amd/display/dc/hwss/dcn31/dcn31_init.c | 2 -- .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 -- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 -- .../gpu/drm/amd/display/dc/inc/core_types.h | 4 --- .../drm/amd/display/dc/inc/hw/link_encoder.h | 4 --- .../amd/display/dc/inc/hw/timing_generator.h | 2 -- .../gpu/drm/amd/display/dc/inc/link_service.h | 5 ++- .../gpu/drm/amd/display/dc/link/link_dpms.c | 12 ------- .../drm/amd/display/dc/link/link_validation.c | 7 ----- .../dc/link/protocols/link_dp_capability.c | 7 +---- .../dc/link/protocols/link_dp_capability.h | 2 -- .../display/dc/link/protocols/link_dp_phy.c | 2 -- .../dc/link/protocols/link_dp_training.c | 2 -- .../link/protocols/link_dp_training_8b_10b.c | 2 -- .../dc/link/protocols/link_dp_training_dpia.c | 2 -- .../link/protocols/link_edp_panel_control.c | 4 --- .../amd/display/dc/optc/dcn20/dcn20_optc.c | 9 ------ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 2 -- .../amd/display/dc/optc/dcn201/dcn201_optc.c | 2 -- .../amd/display/dc/optc/dcn30/dcn30_optc.c | 4 --- .../amd/display/dc/optc/dcn30/dcn30_optc.h | 2 -- .../amd/display/dc/optc/dcn31/dcn31_optc.c | 2 -- .../amd/display/dc/optc/dcn314/dcn314_optc.c | 2 -- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 -- .../dc/resource/dcn20/dcn20_resource.c | 31 ------------------- .../dc/resource/dcn20/dcn20_resource.h | 2 -- .../dc/resource/dcn201/dcn201_resource.c | 2 -- .../dc/resource/dcn21/dcn21_resource.c | 14 --------- .../dc/resource/dcn30/dcn30_resource.c | 22 ------------- .../dc/resource/dcn301/dcn301_resource.c | 14 --------- .../dc/resource/dcn302/dcn302_resource.c | 12 ------- .../dc/resource/dcn303/dcn303_resource.c | 10 ------ .../dc/resource/dcn31/dcn31_resource.c | 12 ------- .../dc/resource/dcn314/dcn314_resource.c | 10 ------ .../dc/resource/dcn315/dcn315_resource.c | 14 --------- .../dc/resource/dcn316/dcn316_resource.c | 14 --------- .../dc/resource/dcn32/dcn32_resource.c | 10 ------ .../resource/dcn32/dcn32_resource_helpers.c | 2 -- .../dc/resource/dcn321/dcn321_resource.c | 2 -- drivers/gpu/drm/amd/dkms/Makefile | 3 -- include/kcl/kcl_drm_dsc_helper.h | 3 -- 90 files changed, 4 insertions(+), 440 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c index f5546b4049608..8c799582dbbd7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -15,7 +15,6 @@ * device expects the PPS payload in big endian format for fields * that span more than 1 byte. */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include @@ -330,6 +329,4 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) return 0; } EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); -#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ - -#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb83c8038f419..74787dbe666bc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8499,7 +8499,6 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, @@ -8586,7 +8585,6 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, return 0; } #endif -#endif static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) { @@ -12549,11 +12547,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; -#endif trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -12890,7 +12886,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { @@ -12915,8 +12910,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } -#endif -#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index b45f2d6bd18ee..c3b74ce245b5b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1367,7 +1367,6 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static int dp_dsc_fec_support_show(struct seq_file *m, void *data) { struct drm_connector *connector = m->private; @@ -1423,7 +1422,6 @@ static int dp_dsc_fec_support_show(struct seq_file *m, void *data) return ret; } -#endif /* function: Trigger virtual HPD redetection on connector * @@ -1561,7 +1559,6 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, * 1 - means that DSC is currently enabled * 0 - means that DSC is disabled */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -2532,7 +2529,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, kfree(rd_buf); return result; } -#endif /* * function description: Read max_requested_bpc property from the connector @@ -3002,7 +2998,6 @@ DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, .read = dp_dsc_clock_en_read, @@ -3054,7 +3049,6 @@ static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { .read = dp_dsc_slice_bpg_offset_read, .llseek = default_llseek }; -#endif static const struct file_operations trigger_hotplug_debugfs_fops = { .owner = THIS_MODULE, @@ -3128,8 +3122,6 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, -#endif - {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, #ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 924dd1f66237d..7bd134c6e800b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -842,7 +842,6 @@ bool dm_helpers_execute_fused_io( return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, bool is_write_cmd, unsigned char cmd, @@ -1020,9 +1019,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( return ret; } -#endif -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, @@ -1115,7 +1112,6 @@ bool dm_helpers_dp_write_dsc_enable( return ret; } -#endif bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 7a46a7b7962a2..5368ca7e79602 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -268,7 +268,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; -#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -360,7 +359,6 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } #endif -#endif static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector) { @@ -510,7 +508,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) amdgpu_dm_update_freesync_caps( connector, aconnector->drm_edid); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) @@ -521,7 +518,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); -#endif #endif } } @@ -991,7 +987,6 @@ uint32_t dm_mst_get_pbn_divider(struct dc_link *link) return dfixed_const(pbn_div_x100) / 100; } -#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) #if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; @@ -2203,4 +2198,3 @@ enum dc_status dm_dp_mst_is_port_support_mode( #endif return DC_OK; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1db97b9cf6208..72ebbe56bf52a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -66,9 +66,7 @@ #include "dc_dmub_srv.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" -#endif #include "vm_helper.h" @@ -680,9 +678,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_end = crc_window->windowb_y_end; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; -#endif param.odm_mode = pipe->next_odm_pipe ? 1:0; /* Default to the union of both windows */ @@ -3022,10 +3018,8 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( if (stream_update->wb_update) su_flags->bits.wb_update = 1; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) su_flags->bits.dsc_changed = 1; -#endif if (stream_update->mst_bw_update) su_flags->bits.mst_bw = 1; @@ -3253,9 +3247,7 @@ static void copy_stream_update_to_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *update) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_context *dc_ctx = dc->ctx; -#endif if (update == NULL || stream == NULL) return; @@ -3360,7 +3352,6 @@ static void copy_stream_update_to_stream(struct dc *dc, update->wb_update->writeback_info[i]; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3386,7 +3377,6 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } -#endif if (update->scaler_sharpener_update) stream->scaler_sharpener_update = *update->scaler_sharpener_update; if (update->sharpening_required) @@ -3780,10 +3770,8 @@ static void commit_planes_do_stream_update(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) dc->link_srv->update_dsc_config(pipe_ctx); -#endif if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update->is_increase) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index f07119365ed0a..c9fbb64d706a2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -4090,11 +4090,7 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) if (dc->res_pool == NULL) return false; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT return dc->res_pool->res_cap->num_dsc > 0; -#else - return 0; -#endif } static bool planes_changed_for_existing_stream(struct dc_state *context, @@ -5015,10 +5011,8 @@ bool pipe_need_reprogram( false == pipe_ctx_old->stream->dpms_off) return true; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) return true; -#endif if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 83c0b98d9b600..191f6435e7c64 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -111,7 +111,6 @@ bool dc_stream_construct(struct dc_stream_state *stream, /* EDID CAP translation for HDMI 2.0 */ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); stream->timing.dsc_cfg.num_slices_h = 0; stream->timing.dsc_cfg.num_slices_v = 0; @@ -120,7 +119,6 @@ bool dc_stream_construct(struct dc_stream_state *stream, stream->timing.dsc_cfg.linebuf_depth = 9; stream->timing.dsc_cfg.version_minor = 2; stream->timing.dsc_cfg.ycbcr422_simple = 0; -#endif update_stream_signal(stream, dc_sink_data); @@ -866,7 +864,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream) @@ -877,7 +874,6 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, return DC_NO_DSC_RESOURCE; } } -#endif struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5fa2d2942899c..32fcbedd82d4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1019,7 +1019,6 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_dsc_power_gate; bool disable_optc_power_gate; bool disable_hpo_power_gate; @@ -1028,7 +1027,6 @@ struct dc_debug_options { bool disable_dio_power_gate; int dsc_min_slice_height_override; int dsc_bpp_increment_div; -#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -2636,7 +2634,6 @@ struct dc_container_id { }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps { // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'false' if they are sink's DSC caps @@ -2646,7 +2643,6 @@ struct dc_sink_dsc_caps { bool is_dsc_passthrough_supported; struct dsc_dec_dpcd_caps dsc_dec_caps; }; -#endif struct dc_sink_hblank_expansion_caps { // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index baf6e9d9eeeaf..86394203cee79 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -486,11 +486,9 @@ bool dc_stream_remove_writeback(struct dc *dc, struct dc_stream_state *stream, uint32_t dwb_pipe_inst); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); -#endif bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 4ca9934ce6ffa..d2e60480fb2be 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -550,9 +550,7 @@ enum dc_infoframe_type { DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_DP_INFOFRAME_TYPE_PPS = 0x10, -#endif }; struct dc_info_packet { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 9ef725ec2ea8c..d672231495ef5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -379,9 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); -#endif /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. @@ -394,7 +392,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode || psr_context->os_request_force_ffu; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && @@ -407,7 +404,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_2)))) copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; else -#endif copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 3628a949db90a..9459e8f283384 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -77,9 +77,7 @@ static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc) } static const struct link_encoder_funcs dcn201_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index bce7b78b254fa..36456c9971c84 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -298,9 +298,7 @@ static void dcn21_link_encoder_disable_output(struct link_encoder *enc, static const struct link_encoder_funcs dcn21_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index 2fccdb983b0aa..7d22618f90d2d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -173,10 +173,8 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { void enc2_fec_set_enable(struct link_encoder *enc, bool enable) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_LOG_DSC("%s FEC at link encoder inst %d", enable ? "Enabling" : "Disabling", enc->id.enum_id); -#endif REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); } @@ -197,7 +195,6 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -210,7 +207,6 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } -#endif static bool update_cfg_data( struct dcn10_link_encoder *enc10, @@ -360,9 +356,7 @@ void enc2_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn20_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h index 39a5f6882cf95..762c579fcb44d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h @@ -342,9 +342,7 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); bool enc2_fec_is_active(struct link_encoder *enc); void enc2_hw_init(struct link_encoder *enc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); -#endif void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index d4adc6630c135..c29c8f33d2167 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, @@ -365,7 +364,6 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif /* Set Dynamic Metadata-configuration. * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME @@ -461,10 +459,8 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) { bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !timing->dsc_cfg.ycbcr422_simple); -#endif return two_pix; } @@ -635,11 +631,9 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, .dp_set_dsc_config = enc2_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index 0915a1e660520..57b9ae5fca1dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -56,9 +56,7 @@ bool dcn30_link_encoder_validate_output_with_stream( } static const struct link_encoder_funcs dcn30_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index 106e963256c44..e93be7b6d9b03 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -295,7 +295,6 @@ void enc3_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC14_LINE, 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -402,7 +401,6 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( struct stream_encoder *enc, @@ -867,11 +865,9 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc3_read_state, .dp_set_dsc_config = enc3_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index ee3e776748ee6..47d84a2a48ce8 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -48,9 +48,7 @@ (enc10->link_regs->index) static const struct link_encoder_funcs dcn301_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, .setup = dcn10_link_encoder_setup, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 2c8e1e4eb00da..07d362ef0daf3 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -247,9 +247,7 @@ void enc31_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn31_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc31_hw_init, @@ -487,9 +485,7 @@ void dcn31_link_encoder_enable_dp_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); -#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); @@ -536,9 +532,7 @@ void dcn31_link_encoder_enable_dp_mst_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); -#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 10b307c5173a1..20fbddf074c50 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -384,7 +384,6 @@ void enc314_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -419,7 +418,6 @@ void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -468,14 +466,10 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .set_avmute = enc1_stream_encoder_set_avmute, .dig_connect_to_otg = enc1_dig_connect_to_otg, .dig_source_otg = enc1_dig_source_otg, - .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, - -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index a9bddb1206ff3..65d28cb07b046 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -204,9 +204,7 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, static const struct link_encoder_funcs dcn32_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 5982bc43b08b4..3523d1cdc1a35 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -346,7 +346,6 @@ void enc32_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -381,7 +380,6 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -460,7 +458,6 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc32_read_state, .dp_set_dsc_config = enc32_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index e87ba3c04b3d2..968f89295b64c 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -60,9 +60,7 @@ dm_write_reg(CTX, AUX_REG(reg_name), val) static const struct link_encoder_funcs dcn321_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c index e6bbc96c1d158..c5d2e9404d943 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c @@ -83,12 +83,10 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( struct stream_encoder *enc) {} -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_enc_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) {} -#endif static void virtual_dig_connect_to_otg( struct stream_encoder *enc, @@ -101,20 +99,16 @@ static void virtual_setup_stereo_sync( bool enable) {} -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_stream_encoder_set_dsc_pps_info_packet( struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) {} -#endif static const struct stream_encoder_funcs virtual_str_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_odm_combine = virtual_enc_dp_set_odm_combine, -#endif .dp_set_stream_attribute = virtual_stream_encoder_dp_set_stream_attribute, .hdmi_set_stream_attribute = @@ -141,9 +135,7 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .dig_connect_to_otg = virtual_dig_connect_to_otg, .setup_stereo_sync = virtual_setup_stereo_sync, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet, -#endif }; bool virtual_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index 8975cd1529fa3..d5831a34f5a19 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -174,9 +174,7 @@ enum dm_validation_status { DML_FAIL_DIO_SUPPORT, DML_FAIL_NOT_ENOUGH_DSC, DML_FAIL_DSC_CLK_REQUIRED, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DML_FAIL_DSC_VALIDATION_FAILURE, -#endif DML_FAIL_URGENT_LATENCY, DML_FAIL_REORDERING_BUFFER, DML_FAIL_DISPCLK_DPPCLK, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index e14e11ccf7d08..bf01d8a9e538b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "rc_calc_fpu.h" #include "qp_tables.h" @@ -258,4 +257,3 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h index 0b70eb9bcc6b9..d7cd8cc247583 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __RC_CALC_FPU_H__ #define __RC_CALC_FPU_H__ @@ -89,4 +88,3 @@ void _do_calc_rc_params(struct rc_params *rc, int minor_version); #endif -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 49ef90b1fe5bd..5b3584ad5b6b3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -22,7 +22,6 @@ * Author: AMD */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include #include "dc_hw_types.h" @@ -1458,4 +1457,3 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->slice_height_granularity = 1; options->force_dsc_when_not_needed = false; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index c9dab816865e4..8111e738f5d53 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include "reg_helper.h" @@ -779,4 +778,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index c61b13208a9e3..e32299982bbec 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -21,7 +21,6 @@ * Authors: AMD * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __DCN20_DSC_H__ #define __DCN20_DSC_H__ @@ -617,4 +616,3 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 1699a57ab7cb1..25ea69bd2e820 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -1,4 +1,3 @@ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2017 Advanced Micro Devices, Inc. @@ -68,4 +67,3 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) DC_FP_END(); #endif } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 13fc27926468f..6f5ad09ad1404 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -1,4 +1,3 @@ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2012-17 Advanced Micro Devices, Inc. * @@ -122,4 +121,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 7b181d4f959b2..759b453385c46 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -564,9 +564,7 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet( /* Load PPS into infoframe (SDP) registers */ pps_sdp.valid = true; pps_sdp.hb0 = 0; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; -#endif pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 7ccfcde03fa76..5243177c1faad 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -49,9 +49,7 @@ #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" -#endif #include "dio/dcn10/dcn10_dio.h" #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" @@ -682,7 +680,6 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); @@ -739,7 +736,6 @@ void dcn10_log_hw_state(struct dc *dc, } } DTN_INFO("\n"); -#endif DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index ea1f6a24af210..307e8f8060e6d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -32,9 +32,7 @@ #include "dcn20/dcn20_resource.h" #include "dcn20_hwseq.h" #include "dce/dce_hwseq.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn20/dcn20_optc.h" #include "abm.h" #include "clk_mgr.h" @@ -458,7 +456,6 @@ void dcn20_init_blank( hws->funcs.wait_for_blank_complete(opp); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -535,7 +532,6 @@ void dcn20_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif void dcn20_dpp_pg_control( struct dce_hwseq *hws, @@ -2602,7 +2598,6 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2614,12 +2609,10 @@ void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } -#endif } void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2631,7 +2624,6 @@ void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } -#endif } void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h index 1424a0f2c09d8..9d1ad3b29ca52 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h @@ -130,12 +130,10 @@ void dcn20_init_vm_ctx( void dcn20_set_flip_control_gsl( struct pipe_ctx *pipe_ctx, bool flip_immediate); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); -#endif void dcn20_fpga_init_hw(struct dc *dc); bool dcn20_wait_for_blank_complete( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index 8ad1455284fc9..ad253c586ea1a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -129,11 +129,7 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#else - .dsc_pg_control = NULL, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c index 46b06ea163ced..c7701a8b574aa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c @@ -132,9 +132,7 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index e091a7ccd42b6..5cbae0cdda962 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -139,9 +139,7 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 67090dca038c7..33cc48cd01962 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -136,9 +136,7 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c index 40fad52521647..0a6d58dd8f6da 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c @@ -156,7 +156,6 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; @@ -222,4 +221,3 @@ void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h index 6317b4a0f363e..1e5126a0e695d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h @@ -30,8 +30,6 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); -#endif #endif /* __DC_HWSS_DCN302_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c index 1602be017597a..637f9514d37b2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c @@ -37,7 +37,5 @@ void dcn302_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; -#endif } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index afdb0f665ec3b..a069b7117d071 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -276,7 +276,6 @@ void dcn31_init_hw(struct dc *dc) dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -339,7 +338,6 @@ void dcn31_dsc_pg_control( } } -#endif void dcn31_enable_power_gating_plane( @@ -363,10 +361,8 @@ void dcn31_enable_power_gating_plane( REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; -#endif /* DCS0/1/2/3/4/5 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); @@ -538,11 +534,9 @@ static void dcn31_reset_back_end_for_pipe( dc->hwseq->wa_state.skip_blank_stream = true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); -#endif pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index af7c65b76f8cd..e56b9a46aecfe 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -140,9 +140,7 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn31_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index f636f2009c512..3e239124c17d8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -222,7 +222,6 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -293,7 +292,6 @@ void dcn314_dsc_pg_control( } } -#endif void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { @@ -314,10 +312,8 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; -#endif /* DCS0/1/2/3/4 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 98ae42d954542..9900c87b4567f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -145,9 +145,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .dpp_pg_control = dcn314_dpp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn314_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index a7ecc8a82c196..ba2c06bd39505 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -67,7 +67,6 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -133,7 +132,6 @@ void dcn32_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, @@ -1519,7 +1517,6 @@ bool dcn32_dsc_pg_status( return pwr_status == 0; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable) @@ -1542,7 +1539,6 @@ void dcn32_update_dsc_pg(struct dc *dc, } } } -#endif void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index 644d141cd01e7..0303a59536737 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -107,11 +107,9 @@ bool dcn32_dsc_pg_status( struct dce_hwseq *hws, unsigned int dsc_inst); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable); -#endif void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index f1d777c9ce831..849dae18b7384 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -115,9 +115,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast, .update_phantom_vp_position = dcn32_update_phantom_vp_position, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .update_dsc_pg = dcn32_update_dsc_pg, -#endif .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index bdae9bfc82299..f6ae3209fab02 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -201,11 +201,9 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); -#endif void (*add_phantom_pipes)( struct dc *dc, @@ -268,9 +266,7 @@ struct resource_pool { unsigned int gsl_2:1; } gsl_groups; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dscs[MAX_PIPES]; -#endif unsigned int pipe_count; unsigned int underlay_pipe_index; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 5abc18564ad54..5abbf485d273e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -95,7 +95,6 @@ struct link_encoder { bool usbc_combo_phy; }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct link_enc_state { uint32_t dphy_fec_en; @@ -104,7 +103,6 @@ struct link_enc_state { uint32_t dp_link_training_complete; }; -#endif enum encoder_type_select { ENCODER_TYPE_DIG = 0, @@ -113,10 +111,8 @@ enum encoder_type_select { }; struct link_encoder_funcs { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); -#endif bool (*validate_output_with_stream)( struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 0ca7e3be1f8cd..2f70bb476c97b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -142,9 +142,7 @@ struct crc_params { enum crc_selection selection; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT uint8_t dsc_mode; -#endif uint8_t odm_mode; bool continuous_mode; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h index 57bb82e949427..540fbc174eec0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h @@ -165,7 +165,6 @@ struct link_service { bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable); bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx); - /*************************** DDC **************************************/ struct ddc_service *(*create_ddc_service)( struct ddc_service_init_data *ddc_init_data); @@ -228,9 +227,9 @@ struct link_service { const struct link_resource *link_res, struct link_training_settings *lt_settings); void (*dpcd_write_rx_power_ctrl)(struct dc_link *link, bool on); + - - /*************************** DP IRQ Handler ***************************/ + /*************************** DP IRQ Handler ***************************/ bool (*dp_parse_link_loss_status)( struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 4ffdaea679812..9e489a4a93b3d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -632,7 +632,6 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; @@ -645,7 +644,6 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); return result; } -#endif static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) { @@ -875,7 +873,6 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) { struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; @@ -899,7 +896,6 @@ bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) out: return result; } -#endif bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) { @@ -1724,9 +1720,7 @@ static void disable_link_dp(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_link_settings link_settings = link->cur_link_settings; -#endif if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->mst_stream_alloc_table.stream_count > 0) @@ -1743,13 +1737,11 @@ static void disable_link_dp(struct dc_link *link, if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, link_res, false); dp_set_fec_ready(link, link_res, false); } -#endif } static void disable_link(struct dc_link *link, @@ -2401,13 +2393,11 @@ void link_set_dpms_on( * will be automatically set at a later time when the video is enabled * (DP_VID_STREAM_EN = 1). */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) link_set_dsc_enable(pipe_ctx, true); } -#endif if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) dp_setup_replay(link, stream); @@ -2456,7 +2446,6 @@ void link_set_dpms_on( dc->hwss.enable_stream(pipe_ctx); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DPS PPS SDP (AKA "info frames") */ if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || @@ -2465,7 +2454,6 @@ void link_set_dpms_on( link_set_dsc_pps_packet(pipe_ctx, true, true); } } -#endif if (dc_is_dp_signal(pipe_ctx->stream->signal)) dp_set_hblank_reduction_on_rx(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index 937586151e78e..975894d1f0b5c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -144,14 +144,9 @@ static bool dp_active_dongle_validate_timing( return false; } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { -#else - if (dongle_caps->dfp_cap_ext.supported) { -#endif - if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; @@ -245,12 +240,10 @@ uint32_t dp_link_bandwidth_kbps( */ link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dp_should_enable_fec(link)) { total_data_bw_efficiency_x10000 /= 100; total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; } -#endif break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index a1333e2c3e789..460a4793b804d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -474,7 +474,6 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) return lttpr_max_link_rate; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) { enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; @@ -494,7 +493,6 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) return cable_max_link_rate; } -#endif static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) { @@ -839,7 +837,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -968,7 +966,6 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } return false; } -#endif static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) { @@ -2017,7 +2014,6 @@ static bool retrieve_link_cap(struct dc_link *link) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); @@ -2085,7 +2081,6 @@ static bool retrieve_link_cap(struct dc_link *link) } else link->wa_flags.dpia_forced_tbt3_mode = false; } -#endif if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 83c580791a62e..6e17f72a752f3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -81,12 +81,10 @@ bool link_decide_link_settings( bool edp_decide_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, enum dc_link_rate max_link_rate); -#endif enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c index 4ac00f9a2c183..49521ac4b0e85 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c @@ -135,7 +135,6 @@ void dp_set_drive_settings( dpcd_set_lane_settings(link, lt_settings, DPRX); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) { /* FEC has to be "set ready" before the link training. @@ -177,7 +176,6 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource return status; } -#endif void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 5bd7b68bc9314..2af51afef82ab 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -778,10 +778,8 @@ void override_training_settings( if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; -#endif /* Check DP tunnel LTTPR mode debug option. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index ee1a1c755332c..66d0fb1b9b9d2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -136,9 +136,7 @@ void decide_8b_10b_training_settings( lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); lt_settings->enhanced_framing = 1; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT lt_settings->should_set_fec_ready = true; -#endif lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index 04fdc70ae6da3..603537ffd1284 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -101,9 +101,7 @@ static enum link_training_result dpia_configure_link( struct link_training_settings *lt_settings) { enum dc_status status; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool fec_enable; -#endif DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", __func__, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 2fd602fbc2e8f..5b2c1a4911cf0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -376,14 +376,10 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link)); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!crtc_timing->flags.DSC) edp_decide_link_settings(link, &link_setting, req_bw); else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); -#else - dc_link_decide_edp_link_settings(link, &link_setting, req_bw); -#endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index d3d3fadce5dab..e7a90a437fffb 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -124,7 +124,6 @@ void optc2_set_gsl_source_select( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -146,7 +145,6 @@ void optc2_set_dsc_config(struct timing_generator *optc, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, dsc_slice_width); } -#endif /* Get DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format @@ -489,14 +487,9 @@ bool optc2_configure_crc(struct timing_generator *optc, { struct optc *optc1 = DCN10TG_FROM_TG(optc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT REG_SET_2(OTG_CRC_CNTL2, 0, OTG_CRC_DSC_MODE, params->dsc_mode, OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); -#else - REG_SET(OTG_CRC_CNTL2, 0, - OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); -#endif return optc1_configure_crc(optc, params); } @@ -555,9 +548,7 @@ static const struct timing_generator_funcs dcn20_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = optc2_set_dwb_source, .set_odm_bypass = optc2_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 09f16dc1c5048..928e110b95fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -98,12 +98,10 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc2_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); -#endif void optc2_get_dsc_status(struct timing_generator *optc, uint32_t *dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c index fcc5d6138e5a6..772a8bfb949c1 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c @@ -172,9 +172,7 @@ static const struct timing_generator_funcs dcn201_tg_funcs = { .clear_optc_underflow = optc1_clear_optc_underflow, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, -#endif .set_dwb_source = NULL, .get_optc_source = optc201_get_optc_source, .set_vtg_params = optc1_set_vtg_params, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index ddf112c87267d..ee4665aa49e9f 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -176,7 +176,6 @@ void optc3_set_vtotal_change_limit(struct timing_generator *optc, } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -192,7 +191,6 @@ void optc3_set_dsc_config(struct timing_generator *optc, optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); } -#endif void optc3_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) @@ -402,9 +400,7 @@ static const struct timing_generator_funcs dcn30_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index f3ca2df9a3a00..e2303f9eaf13b 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -348,12 +348,10 @@ void optc3_program_blank_color(struct timing_generator *optc, void optc3_set_vtotal_change_limit(struct timing_generator *optc, uint32_t limit); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc3_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); -#endif void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 23e66bc6c1ba0..c6417538090f2 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -489,9 +489,7 @@ static const struct timing_generator_funcs dcn31_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index d94b1edd6d87d..43ff957288b27 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -237,9 +237,7 @@ static const struct timing_generator_funcs dcn314_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .get_optc_source = optc2_get_optc_source, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 72b1d85ca0a2f..135624a810b5d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -344,9 +344,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc32_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 20da3ae307bec..2c91a9e0305f0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -618,7 +618,6 @@ static int map_transmitter_id_to_phy_instance( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -640,7 +639,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dccg_registers dccg_regs = { DCCG_REG_LIST_DCN2() @@ -664,9 +662,7 @@ static const struct resource_caps res_cap_nv10 = { .num_dwb = 1, .num_ddc = 6, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -704,9 +700,7 @@ static const struct resource_caps res_cap_nv14 = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, -#endif }; static const struct dc_debug_options debug_defaults_drv = { @@ -1063,7 +1057,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1084,7 +1077,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) kfree(container_of(*dsc, struct dcn20_dsc, base)); *dsc = NULL; } -#endif static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { @@ -1097,12 +1089,10 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1330,7 +1320,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1435,7 +1424,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, else return DC_OK; } -#endif enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1446,11 +1434,9 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, if (result == DC_OK) result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); -#endif if (result == DC_OK) result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); @@ -1463,9 +1449,7 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ { enum dc_status result = DC_OK; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); -#endif return result; } @@ -1504,9 +1488,7 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT next_odm_pipe->stream_res.dsc = NULL; -#endif if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; @@ -1533,15 +1515,12 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); ASSERT(next_odm_pipe->stream_res.dsc); if (next_odm_pipe->stream_res.dsc == NULL) return false; } -#endif - return true; } @@ -1564,9 +1543,7 @@ void dcn20_split_stream_for_mpc( secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT secondary_pipe->stream_res.dsc = NULL; -#endif if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -1657,7 +1634,6 @@ void dcn20_set_mcif_arb_params( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1693,7 +1669,6 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) } return true; } -#endif struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, @@ -1797,10 +1772,8 @@ void dcn20_merge_pipes_for_validate( odm_pipe->bottom_pipe = NULL; odm_pipe->prev_odm_pipe = NULL; odm_pipe->next_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (odm_pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); -#endif /* Clear plane_res and stream_res */ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); @@ -2244,9 +2217,7 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, @@ -2715,7 +2686,6 @@ static bool dcn20_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn20_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2724,7 +2694,6 @@ static bool dcn20_resource_construct( goto create_fail; } } -#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h index 072bfaa3185c8..e997d35a8b86e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h @@ -132,9 +132,7 @@ int dcn20_validate_apply_pipe_split_flags( void dcn20_release_dsc(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); -#endif void dcn20_split_stream_for_mpc( struct resource_context *res_ctx, const struct resource_pool *pool, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index a4b7e56dc6bdb..90d38631f63a0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1073,9 +1073,7 @@ static struct resource_funcs dcn201_res_pool_funcs = { .validate_bandwidth = dcn20_validate_bandwidth, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = NULL, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 834eddbb74c99..666b7be36a952 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -362,7 +362,6 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -384,7 +383,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif #define ipp_regs(id)\ [id] = {\ @@ -580,9 +578,7 @@ static const struct resource_caps res_cap_rn = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -668,12 +664,10 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -906,14 +900,12 @@ bool dcn21_fast_validate_bw(struct dc *dc, ASSERT(0); } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif *vlevel_out = vlevel; @@ -1094,7 +1086,6 @@ static void read_dce_straps( } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1109,7 +1100,6 @@ static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) { @@ -1378,9 +1368,7 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .validate_bandwidth = dcn21_validate_bandwidth, .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, @@ -1666,7 +1654,6 @@ static bool dcn21_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1675,7 +1662,6 @@ static bool dcn21_resource_construct( goto create_fail; } } -#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 10c4b75ebbc07..6cfdc37dab588 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -46,9 +46,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -513,7 +511,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN20(0), dsc_regsDCN20(1), @@ -530,7 +527,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -681,9 +677,7 @@ static const struct resource_caps res_cap_dcn3 = { .num_ddc = 6, .num_vmid = 16, .num_mpc_3dlut = 3, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1090,12 +1084,10 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1273,7 +1265,6 @@ static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn30_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1288,7 +1279,6 @@ static struct display_stream_compressor *dcn30_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1549,9 +1539,7 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT sec_pipe->stream_res.dsc = NULL; -#endif if (odm) { if (pri_pipe->next_odm_pipe) { ASSERT(pri_pipe->next_odm_pipe != sec_pipe); @@ -1573,14 +1561,12 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->stream_res.opp = pool->opps[pipe_idx]; else sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (sec_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) return false; } -#endif } else { if (pri_pipe->bottom_pipe) { ASSERT(pri_pipe->bottom_pipe != sec_pipe); @@ -1755,10 +1741,8 @@ noinline bool dcn30_internal_validate_bw( pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); -#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); repopulate_pipes = true; @@ -1877,13 +1861,11 @@ noinline bool dcn30_internal_validate_bw( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif if (repopulate_pipes) pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); @@ -2260,9 +2242,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2556,7 +2536,6 @@ static bool dcn30_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2565,7 +2544,6 @@ static bool dcn30_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn30_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 4dcd20ed09412..f0078eb134981 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -47,9 +47,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dce/dce_clock_source.h" @@ -491,7 +489,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -510,7 +507,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -652,9 +648,7 @@ static struct resource_caps res_cap_dcn301 = { .num_ddc = 4, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1061,12 +1055,10 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1233,7 +1225,6 @@ static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn301_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1248,7 +1239,6 @@ static struct display_stream_compressor *dcn301_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1404,9 +1394,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1667,7 +1655,6 @@ static bool dcn301_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1676,7 +1663,6 @@ static bool dcn301_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn301_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 3a2849b42e6a1..c0d4a1dc94f8a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -40,9 +40,7 @@ #include "dcn30/dcn30_optc.h" #include "dcn30/dcn30_resource.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn20/dcn20_resource.h" #include "dml/dcn30/dcn30_fpu.h" @@ -134,9 +132,7 @@ static const struct resource_caps res_cap_dcn302 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -665,7 +661,6 @@ static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -697,7 +692,6 @@ static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -1013,12 +1007,10 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } -#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1153,9 +1145,7 @@ static struct resource_funcs dcn302_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1444,7 +1434,6 @@ static bool dcn302_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn302_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1453,7 +1442,6 @@ static bool dcn302_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn302_dwbc_create(ctx, pool)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 1ad44c910ae9b..75e09c2c283e0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -129,9 +129,7 @@ static const struct resource_caps res_cap_dcn303 = { .num_ddc = 2, .num_vmid = 16, .num_mpc_3dlut = 1, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 2, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -627,7 +625,6 @@ static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -656,7 +653,6 @@ static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -955,12 +951,10 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } -#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1095,9 +1089,7 @@ static struct resource_funcs dcn303_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1374,7 +1366,6 @@ static bool dcn303_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn303_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1383,7 +1374,6 @@ static bool dcn303_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn303_dwbc_create(ctx, pool)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index a0d49405ab97a..8ad72557b16a4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -563,7 +563,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -582,7 +581,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -826,9 +824,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1389,12 +1385,10 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1569,7 +1563,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1584,7 +1577,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn31_destroy_resource_pool(struct resource_pool **pool) { @@ -1850,9 +1842,7 @@ static struct resource_funcs dcn31_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2154,7 +2144,6 @@ static bool dcn31_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2163,7 +2152,6 @@ static bool dcn31_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index ed52cddd3f37f..5f0fe6e5bd821 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -574,7 +574,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN314(0), dsc_regsDCN314(1), @@ -589,7 +588,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -1446,12 +1444,10 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1625,7 +1621,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn314_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1640,7 +1635,6 @@ static struct display_stream_compressor *dcn314_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn314_destroy_resource_pool(struct resource_pool **pool) { @@ -1778,9 +1772,7 @@ static struct resource_funcs dcn314_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2076,7 +2068,6 @@ static bool dcn314_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn314_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2085,7 +2076,6 @@ static bool dcn314_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index df48398b3e8a0..3ae787a377b18 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -49,9 +49,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -568,7 +566,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -587,7 +584,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -827,9 +823,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1392,12 +1386,10 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1572,7 +1564,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1587,7 +1578,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn315_destroy_resource_pool(struct resource_pool **pool) { @@ -1846,9 +1836,7 @@ static struct resource_funcs dcn315_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2105,7 +2093,6 @@ static bool dcn315_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2114,7 +2101,6 @@ static bool dcn315_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 2284a9e9de861..61bd6d373bb7d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -49,9 +49,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -560,7 +558,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -579,7 +576,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -823,9 +819,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1388,12 +1382,10 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1565,7 +1557,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1580,7 +1571,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn316_destroy_resource_pool(struct resource_pool **pool) { @@ -1723,9 +1713,7 @@ static struct resource_funcs dcn316_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -1973,7 +1961,6 @@ static bool dcn316_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1982,7 +1969,6 @@ static bool dcn316_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 036e197075b7d..a55078458ba54 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -438,7 +438,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { #define dsc_regsDCN20_init(id)\ DSC_REG_LIST_DCN20_RI(id) -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = { @@ -448,7 +447,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static struct dcn30_mpc_registers mpc_regs; @@ -1393,12 +1391,10 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1566,7 +1562,6 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1591,7 +1586,6 @@ static struct display_stream_compressor *dcn32_dsc_create( return &dsc->base; } -#endif static void dcn32_destroy_resource_pool(struct resource_pool **pool) { @@ -2108,9 +2102,7 @@ static struct resource_funcs dcn32_res_pool_funcs = { .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2458,7 +2450,6 @@ static bool dcn32_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSCs */ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn32_dsc_create(ctx, i); @@ -2468,7 +2459,6 @@ static bool dcn32_resource_construct( goto create_fail; } } -#endif /* DWB */ if (!dcn32_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index eb78191838c7c..f5a4e97c40ced 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -128,10 +128,8 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc, pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); -#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 188c3f24f110a..5a82662f20df5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -445,7 +445,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; - static struct dcn30_mpc_registers mpc_regs; #define dcn_mpc_regs_init()\ MPC_REG_LIST_DCN3_2_RI(0),\ @@ -1376,7 +1375,6 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } - if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); pool->base.mpc = NULL; diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a0e67352e5b38..c90d2e3182c23 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -204,9 +204,6 @@ ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN - -export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT endif endif diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h index 207bc76eb1195..0c61de575753d 100644 --- a/include/kcl/kcl_drm_dsc_helper.h +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -3,8 +3,6 @@ #ifndef _KCL_KCL_DRM_DSC_HELPER_H #define _KCL_KCL_DRM_DSC_HELPER_H -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - #include #include @@ -17,6 +15,5 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif -#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* _KCL_KCL_DRM_DSC_HELPER_H */ From a558de7265470108f6f3cf3d49e0d38de610c5b5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 11:58:45 +0800 Subject: [PATCH 1021/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_MM_INSERT_MODE This patch also removes macro HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 6 -- drivers/gpu/drm/ttm/backport/backport.h | 2 - include/kcl/backport/kcl_drm_mm_backport.h | 27 --------- include/kcl/kcl_drm_mm.h | 68 ---------------------- 5 files changed, 104 deletions(-) delete mode 100644 include/kcl/backport/kcl_drm_mm_backport.h delete mode 100644 include/kcl/kcl_drm_mm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3ab3ab68f5104..bf604b31f0fb5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -61,7 +61,6 @@ #include #include #include -#include #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a4878ef5a2d8d..6350533efdcd3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -620,12 +620,6 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 -/* whether drm_mm_insert_mode is available */ -#define HAVE_DRM_MM_INSERT_MODE 1 - -/* drm_mm_insert_node has three parameters */ -#define HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS 1 - /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index be45e938ed821..e6cab104d2b34 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h deleted file mode 100644 index 1a2614d47ab59..0000000000000 --- a/include/kcl/backport/kcl_drm_mm_backport.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef AMDKCL_DRM_MM_H -#define AMDKCL_DRM_MM_H - -/** - * interface change in mainline kernel 4.10 - * v4.10-rc5-1060-g4e64e5539d15 drm: Improve drm_mm search (and fix topdown allocation) - * with rbtrees - */ - -#include - -#ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS -static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, - struct drm_mm_node *node, - u64 size) -{ - return drm_mm_insert_node(mm, node, size, 0, DRM_MM_SEARCH_DEFAULT); -} -#define drm_mm_insert_node _kcl_drm_mm_insert_node -#endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ - -#ifndef HAVE_DRM_MM_INSERT_MODE -#define drm_mm_insert_node_in_range _kcl_drm_mm_insert_node_in_range -#endif - -#endif /* AMDKCL_DRM_MM_H */ diff --git a/include/kcl/kcl_drm_mm.h b/include/kcl/kcl_drm_mm.h deleted file mode 100644 index 5387e6c05bc65..0000000000000 --- a/include/kcl/kcl_drm_mm.h +++ /dev/null @@ -1,68 +0,0 @@ -/************************************************************************** - * - * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. - * Copyright 2016 Intel Corporation - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * - **************************************************************************/ -/* - * Authors: - * Thomas Hellstrom - */ -#ifndef _KCL_KCL_DRM_MM_H_H_ -#define _KCL_KCL_DRM_MM_H_H_ -#include - -#ifndef HAVE_DRM_MM_INSERT_MODE -/* Copied from 4e64e5539d15 include/drm/drm_mm.h */ -enum drm_mm_insert_mode { - DRM_MM_INSERT_BEST = 0, - DRM_MM_INSERT_LOW, - DRM_MM_INSERT_HIGH, - DRM_MM_INSERT_EVICT, -}; - -static inline -int _kcl_drm_mm_insert_node_in_range(struct drm_mm * const mm, - struct drm_mm_node * const node, - u64 size, u64 alignment, - unsigned long color, - u64 range_start, u64 range_end, - enum drm_mm_insert_mode mode) -{ - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; - - if (mode == DRM_MM_INSERT_HIGH) { - sflags = DRM_MM_SEARCH_BELOW; - aflags = DRM_MM_CREATE_TOP; - } - - return drm_mm_insert_node_in_range_generic(mm, node, size, - alignment, color, range_start, range_end, - sflags, aflags); -} -#endif /* HAVE_DRM_MM_INSERT_MODE */ - -#endif From 34b391f3c69b64176a59ec6c20cdc823a872e1de Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Jun 2023 17:17:10 +0800 Subject: [PATCH 1022/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_IS_420_XXX Signed-off-by: Leslie Shi Reviewed-by: Ma Jun Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 7 ------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 9 --------- .../gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 | 17 ----------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_modes.h | 7 ------- 6 files changed, 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c index e01b01bd4ae09..a7963c347e685 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -33,13 +33,6 @@ #include #include -#ifndef HAVE_DRM_MODE_IS_420_XXX -amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, - const struct drm_display_info *display, const struct drm_display_mode *mode) -amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, - const struct drm_display_info *display, const struct drm_display_mode *mode) -#endif - #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 74787dbe666bc..bccbea71bfcbd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6471,7 +6471,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, /* Assume 8 bpc by default if no bpc is specified. */ bpc = bpc ? bpc : 8; -#ifdef HAVE_DRM_MODE_IS_420_XXX if (is_y420) { bpc = 8; @@ -6483,7 +6482,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; } -#endif if (requested_bpc > 0) { /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6350533efdcd3..b0a6fe40fe4ab 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -629,15 +629,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_config->helper_private is available */ -#define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 - -/* drm_mode_get_hv_timing is available */ -#define HAVE_DRM_MODE_GET_HV_TIMING 1 - -/* drm_mode_is_420_xxx() is available */ -#define HAVE_DRM_MODE_IS_420_XXX 1 - /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INTT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 deleted file mode 100644 index 65c9ec9268e1b..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 2570fe2586254ff174c2ba5a20dabbde707dbb9b -dnl # drm: add helper functions for YCBCR420 handling -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MODE_IS_420_XXX], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_mode_is_420_only(NULL, NULL); - drm_mode_is_420_also(NULL, NULL); - ], [drm_mode_is_420_only drm_mode_is_420_also],[drivers/gpu/drm/drm_modes.c],[ - AC_DEFINE(HAVE_DRM_MODE_IS_420_XXX, 1, - [drm_mode_is_420_xxx() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c432868860ca4..8c3bbc1f785ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,7 +72,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER - AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index efd58502aad15..d3a387bad9988 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -29,13 +29,6 @@ #include -#ifndef HAVE_DRM_MODE_IS_420_XXX -bool drm_mode_is_420_only(const struct drm_display_info *display, - const struct drm_display_mode *mode); -bool drm_mode_is_420_also(const struct drm_display_info *display, - const struct drm_display_mode *mode); -#endif - #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); #endif From dc29b38b81ab36d328765d112492a04ee01de37a Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 1 Mar 2023 12:17:08 +0800 Subject: [PATCH 1023/2070] drm/amdkcl: check if fsleep() is available It's caused by b1121d678231324d281db891755aa547506457a9 "drm/amd/display: Reduce CPU busy-waiting for long delays" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/fsleep.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_delay.h | 18 ++++++++++++++++++ 5 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/fsleep.m4 create mode 100644 include/kcl/kcl_delay.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bf604b31f0fb5..952645eba7ad8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -99,4 +99,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b0a6fe40fe4ab..0433f059c9221 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -146,6 +146,9 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 +/* fsleep() is available */ +#define HAVE_FSLEEP 1 + /* drm_dp_mst_connector_early_unregister() is available */ #define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 new file mode 100644 index 0000000000000..782402a16e6a4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.7-rc2-1263-gc6af13d33475 +dnl # timer: add fsleep for flexible sleeping +dnl # +AC_DEFUN([AC_AMDGPU_FSLEEP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long usecs = 0; + fsleep(usecs); + ], [ + AC_DEFINE(HAVE_FSLEEP, 1, + [fsleep() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8c3bbc1f785ab..4bdf347062473 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -25,6 +25,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_FSLEEP AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT diff --git a/include/kcl/kcl_delay.h b/include/kcl/kcl_delay.h new file mode 100644 index 0000000000000..f5f2962c6bb6d --- /dev/null +++ b/include/kcl/kcl_delay.h @@ -0,0 +1,18 @@ +#ifndef AMDKCL_DELAY_H +#define AMDKCL_DELAY_H + +#ifndef HAVE_FSLEEP +static inline void _kcl_fsleep(unsigned long usecs) +{ + if (usecs <= 10) + udelay(usecs); + else if (usecs <= 20000) + usleep_range(usecs, 2 * usecs); + else + msleep(DIV_ROUND_UP(usecs, 1000)); +} + +#define fsleep _kcl_fsleep + +#endif +#endif From 037f1f0e00fad6b3bc6fc498f098e885e37cfbda Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 2 Mar 2023 13:15:42 +0800 Subject: [PATCH 1024/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 1d34dd584ae816e858b1177294262e80efe7d932 "drm/scheduler: rework entity flush, kill and fini" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 100 ++++++++++++++++++++++- 1 file changed, 97 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index e95e6f6abb273..66a24330c3372 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -176,6 +176,7 @@ EXPORT_SYMBOL(drm_sched_entity_error); static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, struct dma_fence_cb *cb); +#ifdef HAVE_STRUCT_XARRAY static void drm_sched_entity_kill_jobs_work(struct work_struct *wrk) { struct drm_sched_job *job = container_of(wrk, typeof(*job), work); @@ -267,7 +268,7 @@ static void drm_sched_entity_kill(struct drm_sched_entity *entity) } dma_fence_put(prev); } - +#endif /** * drm_sched_entity_flush - Flush a context entity * @@ -307,14 +308,75 @@ long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout) /* For a killed process disallow further enqueueing of jobs. */ last_user = cmpxchg(&entity->last_user, current->group_leader, NULL); +#ifdef HAVE_STRUCT_XARRAY if (last_user == current->group_leader && (current->flags & PF_EXITING) && (current->exit_code == SIGKILL)) drm_sched_entity_kill(entity); - +#else + if ((last_user == current->group_leader) && + (current->flags & PF_EXITING) && (current->exit_code == SIGKILL)) { + spin_lock(&entity->lock); + entity->stopped = true; + drm_sched_rq_remove_entity(entity->rq, entity); + spin_unlock(&entity->lock); + } +#endif return ret; } EXPORT_SYMBOL(drm_sched_entity_flush); +#ifndef HAVE_STRUCT_XARRAY +/* Signal the scheduler finished fence when the entity in question is killed. */ +static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, + struct dma_fence_cb *cb) +{ + struct drm_sched_job *job = container_of(cb, struct drm_sched_job, + finish_cb); + + dma_fence_put(f); + INIT_WORK(&job->work, drm_sched_entity_kill_jobs_work); + schedule_work(&job->work); +} + +static void drm_sched_entity_kill_jobs(struct drm_sched_entity *entity) +{ + struct drm_sched_job *job; + struct dma_fence *f; + int r; + + while ((job = drm_sched_entity_queue_pop(entity))) { + struct drm_sched_fence *s_fence = job->s_fence; + + /* Wait for all dependencies to avoid data corruptions */ + while ((f = job->sched->ops->dependency(job, entity))) { + dma_fence_wait(f, false); + dma_fence_put(f); + } + + drm_sched_fence_scheduled(s_fence, f); + dma_fence_set_error(&s_fence->finished, -ESRCH); + + /* + * When pipe is hanged by older entity, new entity might + * not even have chance to submit it's first job to HW + * and so entity->last_scheduled will remain NULL + */ + if (!entity->last_scheduled) { + drm_sched_entity_kill_jobs_cb(NULL, &job->finish_cb); + continue; + } + + dma_fence_get(entity->last_scheduled); + r = dma_fence_add_callback(entity->last_scheduled, + &job->finish_cb, + drm_sched_entity_kill_jobs_cb); + if (r == -ENOENT) + drm_sched_entity_kill_jobs_cb(NULL, &job->finish_cb); + else if (r) + DRM_ERROR("fence add callback failed (%d)\n", r); + } +} +#endif /** * drm_sched_entity_fini - Destroy a context entity * @@ -328,6 +390,36 @@ EXPORT_SYMBOL(drm_sched_entity_flush); */ void drm_sched_entity_fini(struct drm_sched_entity *entity) { +#ifndef HAVE_STRUCT_XARRAY + struct drm_gpu_scheduler *sched = NULL; + + if (entity->rq) { + sched = entity->rq->sched; + drm_sched_rq_remove_entity(entity->rq, entity); + } + + /* Consumption of existing IBs wasn't completed. Forcefully + * remove them here. + */ + if (spsc_queue_count(&entity->job_queue)) { + if (sched) { + /* + * Wait for thread to idle to make sure it isn't processing + * this entity. + */ + wait_for_completion(&entity->entity_idle); + + } + if (entity->dependency) { + dma_fence_remove_callback(entity->dependency, + &entity->cb); + dma_fence_put(entity->dependency); + entity->dependency = NULL; + } + + drm_sched_entity_kill_jobs(entity); + } +#else /* * If consumption of existing jobs wasn't completed forcefully remove * them. Also makes sure that the scheduler won't touch this entity any @@ -340,7 +432,7 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity) dma_fence_put(entity->dependency); entity->dependency = NULL; } - +#endif dma_fence_put(rcu_dereference_check(entity->last_scheduled, true)); RCU_INIT_POINTER(entity->last_scheduled, NULL); } @@ -439,6 +531,7 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity, return false; } +#ifdef HAVE_STRUCT_XARRAY static struct dma_fence * drm_sched_job_dependency(struct drm_sched_job *job, struct drm_sched_entity *entity) @@ -460,6 +553,7 @@ drm_sched_job_dependency(struct drm_sched_job *job, return NULL; } +#endif struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) { From 5412853a4de8c8fcafb166c19519dc500f58af84 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 2 Mar 2023 13:19:09 +0800 Subject: [PATCH 1025/2070] drm/amdkcl: rename dependency callback into prepare_job It's caused by a25fe9259b68c90033850033ad1b0f20b41e8980 "drm/scheduler: rename dependency callback into prepare_job" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 66a24330c3372..2682477c10a48 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -348,7 +348,7 @@ static void drm_sched_entity_kill_jobs(struct drm_sched_entity *entity) struct drm_sched_fence *s_fence = job->s_fence; /* Wait for all dependencies to avoid data corruptions */ - while ((f = job->sched->ops->dependency(job, entity))) { + while ((f = job->sched->ops->prepare_job(job, entity))) { dma_fence_wait(f, false); dma_fence_put(f); } @@ -570,7 +570,7 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) #ifdef HAVE_STRUCT_XARRAY drm_sched_job_dependency(sched_job, entity))) { #else - sched->ops->dependency(sched_job, entity))) { + sched->ops->prepare_job(sched_job, entity))) { #endif if (drm_sched_entity_add_dependency_cb(entity, sched_job)) return NULL; From 97f13e3c79defce0b1d4267210b7c7e20d2a40e5 Mon Sep 17 00:00:00 2001 From: Daniel Phillips Date: Sun, 5 Mar 2023 22:54:35 -0800 Subject: [PATCH 1026/2070] amdkfd: Fix memory availability double accounting of kfd pinned objects Pinned objects that are not kfd objects reduce the total vram available to kfd, so we subtract the total size of pinned objects from kdf vram availability. However this double counts objects pinned by kfd itself, because they are counted both as used and pinned. So track the total size of objects pinned by kfd and add it back to kfd availability to remove the double accounting. Signed-off-by: Daniel Phillips Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 2ef9ac31f31e8..2310603ad4696 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -109,6 +109,7 @@ struct amdgpu_kfd_dev { struct kfd_dev *dev; int64_t vram_used[MAX_XCP]; uint64_t vram_used_aligned[MAX_XCP]; + atomic64_t vram_pinned; bool init_complete; struct work_struct reset_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 9ba5e1349bd9f..f839c9f134286 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1611,6 +1611,11 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) pr_err("Error in Pinning BO to domain: %d\n", domain); amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); + + if (!ret && bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_add(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + out: amdgpu_bo_unreserve(bo); return ret; @@ -1633,6 +1638,11 @@ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) return; amdgpu_bo_unpin(bo); + + if (bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_sub(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + amdgpu_bo_unreserve(bo); } @@ -1754,6 +1764,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) - adev->kfd.vram_used_aligned[xcp_id] - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned) - reserved_for_pt - reserved_for_ras; From 58cb4f4d410918826fd6f7184340d31ca7891597 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 15 Mar 2023 14:20:22 +0800 Subject: [PATCH 1027/2070] drm/amdkcl: Rename DCN config to FP It's cauesd by 284c5833d58fd8c267d2d0858528e8a997183352 "drm/amd/display: Rename DCN config to FP" Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 +++--- drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7bd134c6e800b..7597e611da5d8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -422,7 +422,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->mst_output_port; -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); #endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 72ebbe56bf52a..f3bf90cd1abac 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1429,7 +1429,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ -#ifdef CONFIG_DRM_AMD_DC_DCN +#ifdef CONFIG_DRM_AMD_DC_FP if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 460a4793b804d..a81b42344e322 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -166,7 +166,7 @@ uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -251,7 +251,7 @@ static union dp_cable_id intersect_cable_id( return out; } -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -1249,7 +1249,7 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) if (link->dc->caps.dp_hdmi21_pcon_support) { link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 135624a810b5d..39cc0f88c9aad 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -307,7 +307,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, -#ifdef CONFIG_DRM_AMD_DC_DCN +#ifdef CONFIG_DRM_AMD_DC_FP .disable_phantom_crtc = optc32_disable_phantom_otg, #endif /* used by enable_timing_synchronization. Not need for FPGA */ diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index c90d2e3182c23..b4e3343fd05d5 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -202,8 +202,8 @@ endif # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_DCN=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN +export CONFIG_DRM_AMD_DC_FP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP endif endif From a74f55e2a2277f20f873745358f5a6aeb24e1e63 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 14 Mar 2023 20:45:51 +0800 Subject: [PATCH 1028/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by c602664a579de061dba08beb690f2718e4fb1b52 "drm/amd/display: Pass the right info to drm_dp_remove_payload" Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7597e611da5d8..c0fd540db9587 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -314,7 +314,7 @@ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, const struct dc_link *link) {} - +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void dm_helpers_construct_old_payload( struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_topology_state *mst_state, @@ -346,6 +346,7 @@ static void dm_helpers_construct_old_payload( old_payload->time_slots = allocated_time_slots; old_payload->pbn = allocated_time_slots * pbn_per_slot; } +#endif /* * Writes payload allocation table in immediate downstream device. From b3fa996ee7ca4064bd6c59c816c47c2eb7387899 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Mar 2023 10:45:23 +0800 Subject: [PATCH 1029/2070] drm/amdkcl: kcl-cleanup DEFINE_SRCU for legacy os Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 9 --------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 ------------- 2 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index ee7d72124e4c6..2434619cddc1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -26,11 +26,6 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" -#ifndef DEFINE_SRCU -void kfd_init_processes_srcu(void); -void kfd_cleanup_processes_srcu(void); -#endif - static int kfd_init(void) { int err; @@ -75,10 +70,6 @@ static int kfd_init(void) kfd_debugfs_init(); -#ifndef DEFINE_SRCU - kfd_init_processes_srcu(); -#endif - return 0; err_create_wq: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 7455ac0c6e616..3630accdc9c41 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -53,20 +53,7 @@ struct mm_struct; DEFINE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); DEFINE_MUTEX(kfd_processes_mutex); -#ifndef DEFINE_SRCU -struct srcu_struct kfd_processes_srcu; -void kfd_init_processes_srcu(void) -{ - init_srcu_struct(&kfd_processes_srcu); -} - -void kfd_cleanup_processes_srcu(void) -{ - cleanup_srcu_struct(&kfd_processes_srcu); -} -#else DEFINE_SRCU(kfd_processes_srcu); -#endif /* For process termination handling */ static struct workqueue_struct *kfd_process_wq; From e84192f35cfc51ba4db5bacf92ddccb587b42d32 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 10:08:24 +0800 Subject: [PATCH 1030/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_EDID_TO_ELD Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 6 -- .../gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 | 19 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_encoder.h | 57 ------------------- 4 files changed, 83 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 delete mode 100644 include/kcl/backport/kcl_drm_encoder.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0433f059c9221..d4b8579bf559a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -535,12 +535,6 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_edid_to_eld() are available */ -/* #undef HAVE_DRM_EDID_TO_ELD */ - -/* drm_encoder_find() wants file_priv */ -#define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 - /* drm_fbdev_generic_setup() is available */ #define HAVE_DRM_FBDEV_GENERIC_SETUP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 deleted file mode 100644 index f0efb113db67b..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 +++ /dev/null @@ -1,19 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-594-g79436a1c9bcc -dnl # drm/edid: make drm_edid_to_eld() static -dnl # -dnl # commit v3.1-rc6-139-g76adaa34db40 -dnl # drm: support routines for HDMI/DP ELD -dnl # -AC_DEFUN([AC_AMDGPU_DRM_EDID_TO_ELD], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_edid_to_eld(NULL, NULL); - ], [drm_edid_to_eld], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_EDID_TO_ELD, 1, - [drm_edid_to_eld() are available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4bdf347062473..d38179329f3a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -69,7 +69,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL - AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h deleted file mode 100644 index 0efc8f747defd..0000000000000 --- a/include/kcl/backport/kcl_drm_encoder.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006 Luc Verhaegen (quirks list) - * Copyright (c) 2007-2008 Intel Corporation - * Jesse Barnes - * Copyright 2010 Red Hat, Inc. - * - * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from - * FB layer. - * Copyright (C) 2006 Dennis Munsie - * For codes copied from drivers/gpu/drm/drm_edid.c - * - * Copyright (c) 2016 Intel Corporation - * For codes copied from include/drm/drm_encoder.h - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef KCL_BACKPORT_KCL_DRM_ENCODER_H -#define KCL_BACKPORT_KCL_DRM_ENCODER_H - -#include -#include - -/* Copied from drivers/gpu/drm/drm_edid.c and modified for KCL */ -#if defined(HAVE_DRM_EDID_TO_ELD) -static inline -int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) -{ - int ret; - - ret = drm_add_edid_modes(connector, edid); - - if (drm_edid_is_valid(edid)) - drm_edid_to_eld(connector, edid); - - return ret; -} -#define drm_add_edid_modes _kcl_drm_add_edid_modes -#endif - -#endif From 086ffb445cb26973338558ec275d2c27d06a6e5e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 13:30:18 +0800 Subject: [PATCH 1031/2070] drm/amdkcl: Remove the temp build directory Sometimes there are temp build directory left after execute the command "make -f dirvers/gpu/drm/amd/dkms/Makefile.config". So remove them all. Signed-off-by: Ma Jun Reviewd-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config index f6d23defbaae6..211fd393987e3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.config +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -15,7 +15,7 @@ config: force clean: force @( \ cd $(srctree)/$(dkmstree); \ - rm -f aclocal.m4 config.* configure config/*.in* \ + rm -rf aclocal.m4 config.* configure config/*.in* build_*\ ) .PHONY: all force From 21fdfe339cca540c22efa6f1df6ea400ac3bd038 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 13:41:41 +0800 Subject: [PATCH 1032/2070] drm/amdkcl: Fix the bug when check luminance_range Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d4b8579bf559a..1b850dd2f60aa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -344,7 +344,7 @@ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 /* display_info->luminance_range is available */ -/* #undef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE */ +#define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index d744dcc9b127a..0ae82ec0ca780 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -64,7 +64,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ #include ],[ struct drm_display_info *display_info = NULL; - display_info->luminance_range=NULL; + struct drm_luminance_range_info *luminance_range; + luminance_range = &display_info->luminance_range; ],[ AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, [display_info->luminance_range is available]) From 3c3a078674223f103b033581c57270539805d5ae Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 10:53:00 +0800 Subject: [PATCH 1033/2070] drm/amdkcl: Fix the return value of idr_init_base Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/idr.m4 | 3 +-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1b850dd2f60aa..8a5e5d56a3c67 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -750,6 +750,9 @@ /* i2c_new_client_device() is enabled */ #define HAVE_I2C_NEW_CLIENT_DEVICE 1 +/* idr_init_base() is available */ +#define HAVE_IDR_INIT_BASE 1 + /* idr_remove return void pointer */ #define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 @@ -1105,6 +1108,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* ide->idr_base is available */ +#define HAVE_STRUCT_IDE_IDR_BASE 1 + /* struct smca_bank is available */ /* #undef HAVE_STRUCT_SMCA_BANK */ diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 7816e84901c5a..1c678e3c401b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -27,8 +27,7 @@ AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - void *i; - i = idr_init_base(NULL, 0); + idr_init_base(NULL, 0); ], [ AC_DEFINE(HAVE_IDR_INIT_BASE, 1, [idr_init_base() is available]) From 165202cce92581a9dea830e213d4963f5d90ea71 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 10:13:24 +0800 Subject: [PATCH 1034/2070] drm/amdkcl: fix macro for amdgpu_acpi_should_gpu_reset() It's caused by ed199fb30b0178ed82311c4f0d5515b0718c9cc4 "drm/amdgpu: reposition the gpu reset checking for reuse" The amdgpu_acpi_should_gpu_reset() is moved, but the kcl macro haven't been include, so fix the kcl macro in new amdgpu_acpi_should_gpu_reset(). Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 37a4adb12b761..82e5782652c7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1440,7 +1440,11 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) return false; #if IS_ENABLED(CONFIG_SUSPEND) +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; +#else + return false; +#endif #else return true; #endif From feebbbf665f96cec7b8cda4ddb85d94de992983d Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 11:04:11 +0800 Subject: [PATCH 1035/2070] drm/amdkcl: open the macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP In dkms-6.0 the HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP has been support, so open the macro. Signed-off-by: bobzhou Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8a5e5d56a3c67..1f0b71ae5aa3e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -347,7 +347,7 @@ #define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ -/* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ +#define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 From 43620bd90519651615c6387e3b0c1347f3cc5e8a Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 14:41:20 +0800 Subject: [PATCH 1036/2070] drm/amdkcl: fake drm_warn macro It's caused by 2b7cb41b58aa950da4a61b21cfa9a62a49127edf "drm/amd/display/amdgpu_dm: Refactor register_backlight_device()" Signed-off-by: bobzhou Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 71a5b6f419e46..c71867326f13b 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -79,6 +79,11 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ +#ifndef drm_warn +#define drm_warn(drm, fmt, ...) \ + dev_warn((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) +#endif /* drm_warn */ + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From 4ccbcd914a5e9510a69be87316cd9368ed10679f Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 16:09:13 +0800 Subject: [PATCH 1037/2070] drm/amdkcl: Drop unnecessary FP guards [Why & How] drm-next branch code drop unnecessary FP guards, so clean up FP guards under kcl macro. Signed-off-by: bobzhou Reviewed-by: majun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ------ drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 -- 4 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index c0fd540db9587..a06053545e7e5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -423,9 +423,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->mst_output_port; -#if defined(CONFIG_DRM_AMD_DC_FP) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); -#endif if (enable) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f3bf90cd1abac..584cb550928c4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1429,12 +1429,10 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ -#ifdef CONFIG_DRM_AMD_DC_FP if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); } -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index a81b42344e322..937e390fa4ad1 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -166,7 +166,6 @@ uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } -#if defined(CONFIG_DRM_AMD_DC_FP) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -186,7 +185,6 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) return 0; } -#endif static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) { @@ -251,7 +249,6 @@ static union dp_cable_id intersect_cable_id( return out; } -#if defined(CONFIG_DRM_AMD_DC_FP) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -281,7 +278,6 @@ static uint32_t intersect_frl_link_bw_support( return supported_bw_in_kbps; } -#endif static enum clock_source_id get_clock_source_id(struct dc_link *link) { @@ -1249,7 +1245,6 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); -#if defined(CONFIG_DRM_AMD_DC_FP) if (link->dc->caps.dp_hdmi21_pcon_support) { link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = @@ -1261,7 +1256,6 @@ static void get_active_converter_info( if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; } -#endif if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 39cc0f88c9aad..3dcb0d0c931cf 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -307,9 +307,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, -#ifdef CONFIG_DRM_AMD_DC_FP .disable_phantom_crtc = optc32_disable_phantom_otg, -#endif /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = optc1_is_counter_moving, .get_position = optc1_get_position, From 139a195ae3570d1823a63a51a8ae6bba3bd6c400 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 21 Mar 2023 11:09:10 +0800 Subject: [PATCH 1038/2070] drm/amdkcl: modify the C standard to gnu99 for legacy gcc [Why & How] Upstream patches now uses gnu11/gnu99 as the default C standard version. However, gcc in legacy OS still uses gnu89, which will introduce a standard build gap leading to a DKMS build failure possibly. Add KBUILD_CFLAGS check to move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. Signed-off-by: bobzhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b4e3343fd05d5..ff21ca820d731 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -207,6 +207,16 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP endif endif +# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) +# Upstream patches now uses gnu11/gnu99 as the default C standard version. +# However, gcc in legacy OS still uses gnu89, which will introduce a standard +# build gap leading to a DKMS build failure possibly. So add below check to +# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. +ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) +KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) +$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +endif + include $(src)/amd/dkms/Makefile.drm_ttm_helper include $(src)/amd/dkms/Makefile.drm_buddy From c58e717c516112adf71b023125f0149f33470425 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 21 Mar 2023 11:37:33 -0600 Subject: [PATCH 1039/2070] drm/display: Add missing OLED Vesa brightnesses definitions Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira --- include/drm/display/drm_dp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index e4eebabab9759..42c58d772fa4f 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1038,6 +1038,8 @@ # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) +#define DP_EDP_OLED_VESA_BRIGHTNESS_ON 0x80 +# define DP_EDP_OLED_VESA_CAP (1 << 4) #define DP_EDP_GENERAL_CAP_2 0x703 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) From 5aadbc4f1d8bea9e72edf14a108803c5280be0d6 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 16:30:48 +0800 Subject: [PATCH 1040/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP v2 It's caused by c88ea46c1474c09939bf1546d5a44e8e42c23361 "drm/amd/display: Add height granularity limitation for dsc slice height calculation" v2: add support for struct dsc_options and reuse legacy data fill it. Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 5368ca7e79602..263688d7b0869 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1037,7 +1037,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p drm_connector = ¶ms[i].aconnector->base; dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); if (vars[i + k].dsc_enabled && dc_dsc_compute_config( From 15cbcb4bd6e53d188b1fa08b7d450b6e39962ae5 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 1 Apr 2023 12:01:56 +0800 Subject: [PATCH 1041/2070] drm/amdgpu: [hybrid] remove sync obj in the job It's caused by 1728baa7e4e60054bf13dd9b1212d133cbd53b3f "drm/amdgpu: use scheduler dependencies for CS" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a438b05e7f862..2423e818b4c78 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -668,7 +668,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } for (i = 0; i < p->gang_size; ++i) { - r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->jobs[i]->sync); + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->sync); if (r) return r; } From a0500519663f2096ae4e3fdab1f9ac9c1d7bc46f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 3 Apr 2023 16:07:11 +0800 Subject: [PATCH 1042/2070] drm/amdkcl: change included file from ttm_bo_api.h to ttm_bo.h It's caused by a3185f91d0579b61a0a0dce3df1c67d6e324ebc8 "drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 04b308171928f..3f3a70274a81c 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -4,8 +4,7 @@ #include #include -#include -#include +#include #include #include #include From f264c2d8c342c3f1cd5e865677bb796dce1ed4ea Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 14:44:21 +0800 Subject: [PATCH 1043/2070] drm/amdkcl: test whether apple_gmux.h is available and fake apple_gmux_detect() It's caused by 1e98231de4609b9e4597b52d0f29bb664e4938d2 "drm/amdgpu: register a vga_switcheroo client for MacBooks with apple-gmux" Signed-off-by: bobzhou Reviewed-by: Leslie Shi Reviewed-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 16 +++++--------- .../gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 | 16 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/apple-gmux.h | 9 ++++++++ include/kcl/kcl_apple-gmux.h | 21 +++++++++++++++++++ 7 files changed, 58 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 create mode 100644 include/kcl/header/linux/apple-gmux.h create mode 100644 include/kcl/kcl_apple-gmux.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 952645eba7ad8..4aec2ea045a87 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -100,4 +100,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1f0b71ae5aa3e..6a27a1c363e59 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -367,6 +367,9 @@ /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 + /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -816,17 +819,8 @@ /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ -/* kvcalloc() is available */ -#define HAVE_KVCALLOC 1 - -/* kvfree() is available */ -#define HAVE_KVFREE 1 - -/* kvmalloc_array() is available */ -#define HAVE_KVMALLOC_ARRAY 1 - -/* kv[mz]alloc() are available */ -#define HAVE_KVZALLOC_KVMALLOC 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APPLE_GMUX_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 new file mode 100644 index 0000000000000..defc80545265e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.1-2256-gbd100f492c7e +dnl # platform/x86: apple-gmux: Add apple_gmux_detect() helper +dnl # +AC_DEFUN([AC_AMDGPU_APPLE_GMUX_DETECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + apple_gmux_detect(NULL, NULL); + ],[ + AC_DEFINE(HAVE_APPLE_GMUX_DETECT, 1, + [apple_gmux_detect() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d38179329f3a8..ed0451315177c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -171,6 +171,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_APPLE_GMUX_DETECT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 2c9f72c524583..f99ed5020b2e7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,4 +114,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-mapping: split dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) + + dnl #v4.5-rc3-203-g2413306c2566 + dnl #apple-gmux: Add helper for presence detect + dnl + AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) ]) diff --git a/include/kcl/header/linux/apple-gmux.h b/include/kcl/header/linux/apple-gmux.h new file mode 100644 index 0000000000000..19c858a0be836 --- /dev/null +++ b/include/kcl/header/linux/apple-gmux.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_APPLE_GMUX_H_H +#define _KCL_HEADER_LINUX_APPLE_GMUX_H_H + +#ifdef HAVE_LINUX_APPLE_GMUX_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_apple-gmux.h b/include/kcl/kcl_apple-gmux.h new file mode 100644 index 0000000000000..27d96810046e7 --- /dev/null +++ b/include/kcl/kcl_apple-gmux.h @@ -0,0 +1,21 @@ +#ifndef AMDKCL_APPLE_GMUX_H +#define AMDKCL_APPLE_GMUX_H + +#include + +#ifndef HAVE_APPLE_GMUX_DETECT +#if IS_ENABLED(CONFIG_APPLE_GMUX) +static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) +{ + pr_warn_once("legacy kernel without apple_gmux_detect()\n"); + return false; +} +#else +static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) +{ + return false; +} +#endif +#endif + +#endif /* AMDKCL_APPLE_GMUX_H */ From 1a51478f748d8ab8e05941125c6ef5b155ef9722 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 16:52:08 +0800 Subject: [PATCH 1044/2070] drm/amdkcl: include linux/dma-resv.h in ttm_bo.h It's caused by a3185f91d0579b61a0a0dce3df1c67d6e324ebc8 "drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2" Signed-off-by: Asher Song --- include/drm/ttm/ttm_bo.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 8da654b4aac5c..5bc9cc38a7cb4 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -35,6 +35,7 @@ #include #include +#include #include "ttm_device.h" #ifndef HAVE_CONFIG_H From adfbabc7cb732ebff160ac76c54ca02e71621252 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 17:12:30 +0800 Subject: [PATCH 1045/2070] drm/amdkcl:Use amdkcl_ttm_resvp to check whether drm_gem_object->resv is available Signed-off-by: Asher Song --- drivers/gpu/drm/ttm/ttm_bo_util.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index cbc6afff927b8..b435093edcdde 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -604,7 +604,7 @@ static int ttm_bo_wait_free_node(struct ttm_buffer_object *bo, { long ret; - ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, 15 * HZ); if (ret == 0) return -EBUSY; @@ -786,7 +786,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) int ret; /* If already idle, no need for ghost object dance. */ - if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP)) { + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)) { if (!bo->ttm) { /* See comment below about clearing. */ ret = ttm_tt_create(bo, true); @@ -823,7 +823,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) ret = dma_resv_copy_fences(&amdkcl_ttm_resv(ghost), amdkcl_ttm_resvp(bo)); /* Last resort, wait for the BO to be idle when we are OOM */ if (ret) { - dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); } From 9ba9fb497c0d18e09d13fdd9008aced3aa5d7514 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 21:28:19 +0800 Subject: [PATCH 1046/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 4f91790b42ffba72d80434d901548979ab41dc7c "drm/amdgpu: use drm_sched_job_add_resv_dependencies for moves" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++ 5 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 2423e818b4c78..1e2223e14f9ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1420,11 +1420,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, fence = &p->jobs[i]->base.s_fence->scheduled; dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&leader->base, fence); if (r) { dma_fence_put(fence); return r; } +#endif } if (p->gang_size > 1) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 8858dd9ffb021..04afbbfd7bb1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -444,11 +444,13 @@ int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job) } dma_fence_get(f); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&job->base, f); if (r) { dma_fence_put(f); return r; } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 4ee3cc93612af..37ab3b0a6b8d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2832,11 +2832,15 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, adev->gart.bo); (*job)->vm_needs_flush = true; } +#ifndef HAVE_STRUCT_XARRAY + return 0; +#else if (!resv) return 0; return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, DMA_RESV_USAGE_BOOKKEEP); +#endif } #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 7ba95304eb7d0..9b8378c996aac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1171,11 +1171,13 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (r) goto err_free; } else { +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_resv_dependencies(&job->base, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; +#endif f = amdgpu_job_submit(job); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 00878c3524d6c..4a694075c2dc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -232,12 +232,14 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); + #ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&p->job->base, fence); if (r) { dma_fence_put(fence); dma_resv_iter_end(&cursor); return r; } +#endif } dma_resv_iter_end(&cursor); From fd64b8174a82b21a84a79427c15b2122cebe1aac Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 14 Apr 2023 15:10:32 +0800 Subject: [PATCH 1047/2070] drm/amdkcl: define macro VM_ACCESS_FLAGS It's caused by cc03817c0e8417419ede18a8e0749c5b9699b135 "amdgpu: use VM_ACCESS_FLAGS" Signed-off-by: Asher Song --- include/kcl/kcl_mm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index e0ccb3247704a..781ea2b6af9fe 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -75,4 +75,10 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) } #endif /* HAVE_VMA_LOOKUP */ +#ifndef VM_ACCESS_FLAGS +/* Copied from v5.6-12367-g6cb4d9a2870d mm/vma: introduce VM_ACCESS_FLAGS*/ +/* VMA basic access permission flags */ +#define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC) +#endif + #endif /* AMDKCL_MM_H */ From 5d203303157c16a5733b03728b42ed28d9eb7291 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 6 Apr 2023 18:17:24 +0800 Subject: [PATCH 1048/2070] drm/amdkcl: clean-up HAVE_IS_FIRMWARE_FRAMEBUFFER Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 55 -------------------------- include/kcl/kcl_drm_fb.h | 4 -- 3 files changed, 1 insertion(+), 60 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fd8ef6b20a372..cd69c6ce28ec0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ + kcl_drm_fb.o kcl_drm_print.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c deleted file mode 100644 index 006b8336abdca..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * linux/drivers/video/fbmem.c - * - * Copyright (C) 1994 Martin Schaller - * - * 2001 - Documented with DocBook - * - Brad Douglas - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include - -/* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ - !defined(HAVE_DRM_DRM_APERTURE_H) -int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -{ - struct apertures_struct *ap; - bool primary = false; - int err, idx, bar; - - for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - idx++; - } - - ap = alloc_apertures(idx); - if (!ap) - return -ENOMEM; - - for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - ap->ranges[idx].base = pci_resource_start(pdev, bar); - ap->ranges[idx].size = pci_resource_len(pdev, bar); - dev_dbg(&pdev->dev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, - (unsigned long)pci_resource_start(pdev, bar), - (unsigned long)pci_resource_end(pdev, bar)); - idx++; - } - -#ifdef CONFIG_X86 - primary = pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW; -#endif - err = remove_conflicting_framebuffers(ap, name, primary); - kfree(ap); - return err; -} -EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); -#endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index bdba6873f3689..2511c19b0f41a 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -60,8 +60,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif -#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER -extern bool is_firmware_framebuffer(struct apertures_struct *a); -#endif - #endif From ecb5162189d8a71f4c2a1bf6661cd0a5a28ad658 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 23 Feb 2023 11:06:01 +0800 Subject: [PATCH 1049/2070] drm/amdkcl:kcl-cleanup HAVE_DRM_FBDEV_GENERIC_SETUP Change-Id: I77e289c6ba211d528916193ed2b37ff9759368fb Signed-off-by: Ma Jun Reviewed-by: Leslie Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +--------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 8 +----- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 28 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../amd/dkms/m4/drm-fbdev-generic-setup.m4 | 16 ----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 4 --- 9 files changed, 3 insertions(+), 79 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index a3fbe1610da0f..7fea74ffe51d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -51,7 +51,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ - amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ + amdgpu_gem.o amdgpu_ring.o \ amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \ atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c3f36e92907f1..b366f4aa5c6d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4762,9 +4762,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - amdgpu_fbdev_init(adev); -#endif /* * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. * Otherwise the mgpu fan boost feature will be skipped due to the @@ -4935,9 +4932,6 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_device_sys_interface_fini(adev); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - amdgpu_fbdev_fini(adev); -#endif /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index d0f25441e5c03..e3b2714ac9c6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1797,7 +1797,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } -#ifdef AMDKCL_DRM_FBDEV_GENERIC static bool amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { @@ -1812,7 +1811,6 @@ amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; } -#endif int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { @@ -1852,16 +1850,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) continue; robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - /* don't unpin kernel fb objects */ - if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { - r = amdgpu_bo_reserve(robj, true); - if (r == 0) { - amdgpu_bo_unpin(robj); - amdgpu_bo_unreserve(robj); - } - } -#else + if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { @@ -1869,7 +1858,6 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) amdgpu_bo_unreserve(robj); } } -#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5fe0d8c16fc62..f352ca01658ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1364,7 +1364,6 @@ int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, return ret; } -#ifdef AMDKCL_DRM_FBDEV_GENERIC static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, @@ -1390,7 +1389,6 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, aligned &= ~pitch_mask; return aligned * cpp; } -#endif int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -1414,13 +1412,9 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, if (adev->mman.buffer_funcs_enabled) flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; -#ifdef AMDKCL_DRM_FBDEV_GENERIC args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); -#else - args->pitch = amdgpu_align_pitch(adev, args->width, - DIV_ROUND_UP(args->bpp, 8), 0); -#endif + args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index db30f16307ce4..de572e3a90ebc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -231,11 +231,6 @@ struct amdgpu_i2c_chan { struct mutex mutex; }; - -#ifndef AMDKCL_DRM_FBDEV_GENERIC -struct amdgpu_fbdev; -#endif - struct amdgpu_afmt { bool enabled; int offset; @@ -312,15 +307,6 @@ struct amdgpu_framebuffer { uint64_t address; }; -#ifndef AMDKCL_DRM_FBDEV_GENERIC -struct amdgpu_fbdev { - struct drm_fb_helper helper; - struct amdgpu_framebuffer rfb; - struct list_head fbdev_list; - struct amdgpu_device *adev; -}; -#endif - struct amdgpu_mode_info { struct atom_context *atom_context; struct card_info *atom_card_info; @@ -345,10 +331,6 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; -#ifndef AMDKCL_DRM_FBDEV_GENERIC - /* pointer to fbdev info structure */ - struct amdgpu_fbdev *rfbdev; -#endif /* firmware flags */ u32 firmware_flags; /* pointer to backlight encoder */ @@ -721,16 +703,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); -#ifndef AMDKCL_DRM_FBDEV_GENERIC -/* fbdev layer */ -int amdgpu_fbdev_init(struct amdgpu_device *adev); -void amdgpu_fbdev_fini(struct amdgpu_device *adev); -void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); -int amdgpu_fbdev_total_size(struct amdgpu_device *adev); -bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); - -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); -#endif /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6a27a1c363e59..b00466b2a27ee 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -538,9 +538,6 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_fbdev_generic_setup() is available */ -#define HAVE_DRM_FBDEV_GENERIC_SETUP 1 - /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 deleted file mode 100644 index cfd16b033ccbf..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v4.18-rc3-614-g9060d7f49376 -dnl # drm/fb-helper: Finish the generic fbdev emulation -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_fbdev_generic_setup(NULL, 0); - ], [drm_fbdev_generic_setup], [drivers/gpu/drm/drm_fb_helper.c],[ - AC_DEFINE(HAVE_DRM_FBDEV_GENERIC_SETUP, 1, - [drm_fbdev_generic_setup() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed0451315177c..7da352f9e719d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -124,7 +124,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT - AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index e14f228fc86fb..4b869a664735f 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,8 +25,4 @@ #include #include -#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) -#define AMDKCL_DRM_FBDEV_GENERIC -#endif - #endif From d8e6aab7bd6285d845060a5fa7df90eec0f2efbc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 3 Apr 2023 15:01:11 +0800 Subject: [PATCH 1050/2070] drm/amdkcl: remove unexpected comma Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ff21ca820d731..ab6ae33fa71b6 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -8,7 +8,7 @@ GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) KERNEL_MAJ=$(VERSION) KERNEL_PATCHLEVEL=$(PATCHLEVEL) KERNEL_SUBLEVEL=$(SUBLEVEL) -KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL), $(KERNEL_SUBLEVEL)) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) From b072e64bacb02d9850da7367e67454a27c451bc2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 3 Apr 2023 15:12:00 +0800 Subject: [PATCH 1051/2070] drm/amdkcl: use gcc-min-version macro to test gcc version This is caused by following commit: 88b61e3bff93 "Makefile.compiler: replace cc-ifversion with compiler-specific macros" Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ab6ae33fa71b6..a6b1568f0b0c8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,13 +12,6 @@ KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERN kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifeq ($(call cc-ifversion, -le, 0408, y), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif - ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") @@ -32,6 +25,17 @@ endif endif +ifndef gcc-min-version +export gcc-min-version=$(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifneq ($(call gcc-min-version, 40805), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + ifndef CONFIG_DRM $(error CONFIG_DRM disabled, exit...) endif From 3f2dfa69ee7564f5986daef10f969212f9f48956 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 4 Apr 2023 13:16:06 +0800 Subject: [PATCH 1052/2070] drm/amdkcl: Explicitly define gcc-min-version in separate file If we export gcc-min-version in dkms/Makefile, the function gcc-min-version cannot output correct value with gcc version 40805 in file display/dc/dml/Makefile for distro RHEL7.9. Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 ++ drivers/gpu/drm/amd/dkms/Makefile | 4 +--- drivers/gpu/drm/amd/dkms/Makefile.compiler | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.compiler diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 268b5fbdb48bd..875cfd1b5ddee 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -28,6 +28,8 @@ dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +include $(src)/../dkms/Makefile.compiler + ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a6b1568f0b0c8..0c7477083f0ec 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -25,9 +25,7 @@ endif endif -ifndef gcc-min-version -export gcc-min-version=$(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) -endif +include $(src)/amd/dkms/Makefile.compiler # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. ifneq ($(call gcc-min-version, 40805), y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.compiler b/drivers/gpu/drm/amd/dkms/Makefile.compiler new file mode 100644 index 0000000000000..9c546ebcbee5a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.compiler @@ -0,0 +1,3 @@ +ifndef gcc-min-version +gcc-min-version = $(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif From 4e33ba8f08970b5a78427af46ad7df28318a22f7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 21 Apr 2023 14:12:37 +0800 Subject: [PATCH 1053/2070] drm/amdkcl: kcl-cleanup remove amdgpu/amdgpu_fb.c file Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 409 ------------------------- 1 file changed, 409 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c deleted file mode 100644 index 09b60070309e1..0000000000000 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright © 2007 David Airlie - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * David Airlie - */ - -#ifndef AMDKCL_DRM_FBDEV_GENERIC - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "amdgpu.h" -#include "cikd.h" -#include "amdgpu_gem.h" - -#include "amdgpu_display.h" - -/* object hierarchy - - this contains a helper + a amdgpu fb - the helper contains a pointer to amdgpu framebuffer baseclass. -*/ - -static int -amdgpufb_open(struct fb_info *info, int user) -{ - struct drm_fb_helper *fb_helper = info->par; - int ret = pm_runtime_get_sync(fb_helper->dev->dev); - if (ret < 0 && ret != -EACCES) { - pm_runtime_mark_last_busy(fb_helper->dev->dev); - pm_runtime_put_autosuspend(fb_helper->dev->dev); - return ret; - } - return 0; -} - -static int -amdgpufb_release(struct fb_info *info, int user) -{ - struct drm_fb_helper *fb_helper = info->par; - - pm_runtime_mark_last_busy(fb_helper->dev->dev); - pm_runtime_put_autosuspend(fb_helper->dev->dev); - return 0; -} - -static const struct fb_ops amdgpufb_ops = { - .owner = THIS_MODULE, - DRM_FB_HELPER_DEFAULT_OPS, - .fb_open = amdgpufb_open, - .fb_release = amdgpufb_release, - .fb_fillrect = drm_fb_helper_cfb_fillrect, - .fb_copyarea = drm_fb_helper_cfb_copyarea, - .fb_imageblit = drm_fb_helper_cfb_imageblit, -}; - - -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) -{ - int aligned = width; - int pitch_mask = 0; - - switch (cpp) { - case 1: - pitch_mask = 255; - break; - case 2: - pitch_mask = 127; - break; - case 3: - case 4: - pitch_mask = 63; - break; - } - - aligned += pitch_mask; - aligned &= ~pitch_mask; - return aligned * cpp; -} - -static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) -{ - struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); - int ret; - - ret = amdgpu_bo_reserve(abo, true); - if (likely(ret == 0)) { - amdgpu_bo_kunmap(abo); - amdgpu_bo_unpin(abo); - amdgpu_bo_unreserve(abo); - } - drm_gem_object_put(gobj); -} - -static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, - struct drm_mode_fb_cmd2 *mode_cmd, - struct drm_gem_object **gobj_p) -{ - const struct drm_format_info *info; - struct amdgpu_device *adev = rfbdev->adev; - struct drm_gem_object *gobj = NULL; - struct amdgpu_bo *abo = NULL; - bool fb_tiled = false; /* useful for testing */ - u32 tiling_flags = 0, domain; - int ret; - int aligned_size, size; - int height = mode_cmd->height; - u32 cpp; - u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_VRAM_CLEARED; - - info = drm_get_format_info(adev_to_drm(adev), mode_cmd); - cpp = info->cpp[0]; - - /* need to align pitch with crtc limits */ - mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, - fb_tiled); - domain = amdgpu_display_supported_domains(adev, flags); - height = ALIGN(mode_cmd->height, 8); - size = mode_cmd->pitches[0] * height; - aligned_size = ALIGN(size, PAGE_SIZE); - ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, - ttm_bo_type_device, NULL, &gobj); - if (ret) { - pr_err("failed to allocate framebuffer (%d)\n", aligned_size); - return -ENOMEM; - } - abo = gem_to_amdgpu_bo(gobj); - - if (fb_tiled) - tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); - - ret = amdgpu_bo_reserve(abo, false); - if (unlikely(ret != 0)) - goto out_unref; - - if (tiling_flags) { - ret = amdgpu_bo_set_tiling_flags(abo, - tiling_flags); - if (ret) - dev_err(adev->dev, "FB failed to set tiling flags\n"); - } - - ret = amdgpu_bo_pin(abo, domain); - if (ret) { - amdgpu_bo_unreserve(abo); - goto out_unref; - } - - ret = amdgpu_ttm_alloc_gart(&abo->tbo); - if (ret) { - amdgpu_bo_unreserve(abo); - dev_err(adev->dev, "%p bind failed\n", abo); - goto out_unref; - } - - ret = amdgpu_bo_kmap(abo, NULL); - amdgpu_bo_unreserve(abo); - if (ret) { - goto out_unref; - } - - *gobj_p = gobj; - return 0; -out_unref: - amdgpufb_destroy_pinned_object(gobj); - *gobj_p = NULL; - return ret; -} - -static int amdgpufb_create(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) -{ - struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; - struct amdgpu_device *adev = rfbdev->adev; - struct fb_info *info; - struct drm_framebuffer *fb = NULL; - struct drm_mode_fb_cmd2 mode_cmd; - struct drm_gem_object *gobj = NULL; - struct amdgpu_bo *abo = NULL; - int ret; - - memset(&mode_cmd, 0, sizeof(mode_cmd)); - mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; - - if (sizes->surface_bpp == 24) - sizes->surface_bpp = 32; - - mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, - sizes->surface_depth); - - ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); - if (ret) { - DRM_ERROR("failed to create fbcon object %d\n", ret); - return ret; - } - - abo = gem_to_amdgpu_bo(gobj); - - /* okay we have an object now allocate the framebuffer */ - info = drm_fb_helper_alloc_fbi(helper); - if (IS_ERR(info)) { - ret = PTR_ERR(info); - goto out; - } - - ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, - &mode_cmd, gobj); - if (ret) { - DRM_ERROR("failed to initialize framebuffer %d\n", ret); - goto out; - } - - fb = &rfbdev->rfb.base; - - /* setup helper */ - rfbdev->helper.fb = fb; - - info->fbops = &amdgpufb_ops; - - info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); - info->fix.smem_len = amdgpu_bo_size(abo); - info->screen_base = amdgpu_bo_kptr(abo); - info->screen_size = amdgpu_bo_size(abo); - - drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); - - /* setup aperture base/size for vesafb takeover */ -#ifdef HAVE_DRM_MODE_CONFIG_FB_BASE - info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; -#endif - info->apertures->ranges[0].size = adev->gmc.aper_size; - - /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ - - if (info->screen_base == NULL) { - ret = -ENOSPC; - goto out; - } - - DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); - DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); - DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); - DRM_INFO("fb depth is %d\n", fb->format->depth); - DRM_INFO("pitch is %d\n", fb->pitches[0]); - - vga_switcheroo_client_fb_set(adev->pdev, info); - return 0; - -out: - if (abo) { - - } - if (fb && ret) { - drm_gem_object_put(gobj); - drm_framebuffer_unregister_private(fb); - drm_framebuffer_cleanup(fb); - kfree(fb); - } - return ret; -} - -static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) -{ - struct amdgpu_framebuffer *rfb = &rfbdev->rfb; - struct drm_gem_object *obj = NULL; - int i; - - drm_fb_helper_unregister_fbi(&rfbdev->helper); - obj = drm_gem_fb_get_obj(&rfb->base, 0); - - if (obj) { -#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED - for (i = 0; i < rfb->base.format->num_planes; i++) - drm_gem_object_put(obj); -#endif - amdgpufb_destroy_pinned_object(obj); - rfb->base.obj[0] = NULL; - drm_framebuffer_unregister_private(&rfb->base); - drm_framebuffer_cleanup(&rfb->base); - } - drm_fb_helper_fini(&rfbdev->helper); - - return 0; -} - -static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { - .fb_probe = amdgpufb_create, -}; - -int amdgpu_fbdev_init(struct amdgpu_device *adev) -{ - struct amdgpu_fbdev *rfbdev; - int bpp_sel = 32; - int ret; - - /* don't init fbdev on hw without DCE */ - if (!adev->mode_info.mode_config_initialized) - return 0; - - /* don't init fbdev if there are no connectors */ - if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) - return 0; - - /* select 8 bpp console on low vram cards */ - if (adev->gmc.real_vram_size <= (32*1024*1024)) - bpp_sel = 8; - - rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); - if (!rfbdev) - return -ENOMEM; - - rfbdev->adev = adev; - adev->mode_info.rfbdev = rfbdev; - - drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, - &amdgpu_fb_helper_funcs); - -#if defined(HAVE_DRM_FB_HELPER_INIT_2ARGS) - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); -#elif defined(HAVE_DRM_FB_HELPER_INIT_3ARGS) - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, - AMDGPUFB_CONN_LIMIT); -#else - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, - adev->mode_info.num_crtc, AMDGPUFB_CONN_LIMIT); -#endif - - if (ret) { - kfree(rfbdev); - return ret; - } - - /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) - drm_helper_disable_unused_functions(adev_to_drm(adev)); - - drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); - return 0; -} - -void amdgpu_fbdev_fini(struct amdgpu_device *adev) -{ - if (!adev->mode_info.rfbdev) - return; - - amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); - kfree(adev->mode_info.rfbdev); - adev->mode_info.rfbdev = NULL; -} - -void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) -{ - if (adev->mode_info.rfbdev) - drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, - state); -} - -int amdgpu_fbdev_total_size(struct amdgpu_device *adev) -{ - struct amdgpu_bo *robj; - int size = 0; - - if (!adev->mode_info.rfbdev) - return 0; - - robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0)); - size += amdgpu_bo_size(robj); - return size; -} - -bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) -{ - if (!adev->mode_info.rfbdev) - return false; - if (robj == gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0))) - return true; - return false; -} -#endif From 01244a521f836eb0241893582645aaf1a0d3250a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 7 Apr 2023 10:01:43 +0800 Subject: [PATCH 1054/2070] drm/amdkcl: Add missing macro definition in config.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b00466b2a27ee..dc590e5a84b6a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -514,11 +514,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_BUDDY_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_UTIL_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_VBLANK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ From 769f4e11dd2a6d6e0a5882c77a3b6b4e981032c6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 4 Apr 2023 10:04:12 +0800 Subject: [PATCH 1055/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_BUDDY_H Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ------ 2 files changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dc590e5a84b6a..50ec3abc0eb5a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -511,9 +511,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_BUDDY_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5004222733f88..a88e31ef833a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -81,12 +81,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) - dnl # - dnl # v5.19-rc1- c9cad937c0 - dnl # drm/amdgpu: add drm buddy support to amdgpu - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) - dnl # dnl # v6.1-rc2-542-g8ab59da26bc0 dnl # drm/fb-helper: Move generic fbdev emulation into separate source file From ee62766327bde554b95e388b08900be6deb21e22 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 28 Jun 2023 11:01:55 +0800 Subject: [PATCH 1056/2070] drm/amdkcl: Update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 97 +----------------------- 1 file changed, 2 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 50ec3abc0eb5a..80c53f2d9f8e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -174,51 +174,9 @@ drm_driver* */ #define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 -/* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are - available */ -#define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 - -/* drm_atomic_get_new_plane_state() is available */ -#define HAVE_DRM_ATOMIC_GET_NEW_PLANE_STATE 1 - /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 -/* drm_atomic_helper_check_plane_state() is available */ -#define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 - -/* drm_atomic_helper_shutdown() is available */ -#define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 - -/* drm_atomic_helper_wait_for_flip_done() is available */ -#define HAVE_DRM_ATOMIC_HELPER_WAIT_FOR_FLIP_DONE 1 - -/* {drm_atomic_helper_crtc_set_property, drm_atomic_helper_plane_set_property, - drm_atomic_helper_connector_set_property, drm_atomic_helper_connector_dpms} - is available */ -/* #undef HAVE_DRM_ATOMIC_HELPER_XXX_SET_PROPERTY */ - -/* drm_atomic_nonblocking_commit() is available */ -#define HAVE_DRM_ATOMIC_NONBLOCKING_COMMIT 1 - -/* drm_atomic_plane_disabling() wants drm_plane_state * arg */ -#define HAVE_DRM_ATOMIC_PLANE_DISABLING_DRM_PLANE_STATE 1 - -/* drm_atomic_private_obj_init() is available */ -#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 - -/* drm_atomic_private_obj_init() has p,p,p,p interface */ -#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P 1 - -/* whether struct drm_atomic_state have async_update */ -#define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 - -/* drm_atomic_state_put() is available */ -#define HAVE_DRM_ATOMIC_STATE_PUT 1 - -/* drm_color_lut_size() is available */ -#define HAVE_DRM_COLOR_LUT_SIZE 1 - /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 @@ -286,9 +244,6 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 -/* drm_crtc_init_with_planes() wants name */ -#define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 - /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 @@ -526,9 +481,6 @@ /* drm_gem_prime_export() with p,i arg is available */ #define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 -/* drm_drv_uses_atomic_modeset() is available */ -#define HAVE_DRM_DRV_USES_ATOMIC_MODESET 1 - /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 @@ -566,9 +518,6 @@ /* drm_gem_object_funcs.vmap hsa iosys_map arg */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 -/* drm_gem_object_lookup() wants 2 args */ -#define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 - /* drm_gem_object_put() is available */ #define HAVE_DRM_GEM_OBJECT_PUT 1 @@ -626,12 +575,6 @@ /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 -/* drm atomic nonblocking commit support is available */ -#define HAVE_DRM_NONBLOCKING_COMMIT_SUPPORT 1 - -/* drm_plane_helper_check_state is available */ -/* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ - /* drm_plane_helper_destroy() is available */ /* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ @@ -663,38 +606,11 @@ /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 -/* drm_syncobj_fence_get() is available */ -/* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ - -/* drm_syncobj_find_fence() is available */ -#define HAVE_DRM_SYNCOBJ_FIND_FENCE 1 - -/* whether drm_syncobj_find_fence() wants 3 args */ -/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_3ARGS */ - -/* whether drm_syncobj_find_fence() wants 4 args */ -/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_4ARGS */ - -/* whether drm_syncobj_find_fence() wants 5 args */ -#define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 -/* drm_universal_plane_init() wants 7 args */ -/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_7ARGS */ - -/* drm_universal_plane_init() wants 8 args */ -/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_8ARGS */ - -/* drm_universal_plane_init() wants 9 args */ -#define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 - -/* drm_vma_node_verify_access() 2nd argument is drm_file */ -#define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 - -/* Variable refresh rate(vrr) is supported */ -#define HAVE_DRM_VRR_SUPPORTED 1 +/* drm_vblank->time uses ktime_t type */ +#define HAVE_DRM_VBLANK_USE_KTIME_T 1 /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 @@ -933,9 +849,6 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 -/* num_u32_u32 is available */ -#define HAVE_MUL_U32_U32 1 - /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1038,12 +951,6 @@ /* struct drm_connector_state->self_refresh_aware is available */ #define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 -/* drm_connector->ycbcr_420_allowed is available */ -#define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 - -/* drm_crtc_funcs->enable_vblank() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 From 12f87c63846ccf38d695c0afcc54eb35c53cfb87 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Apr 2023 18:18:49 +0800 Subject: [PATCH 1057/2070] drm/amdkcl: fake drm_dp_atomic_release_time_slots() It's caused by df78f7f660cdd5974b68649a95dbb34da4d4dfa7 "drm/display/dp_mst: Call them time slots, not VCPI slots" Signed-off-by: Asher Song Reviewed-by: Perry Yuan Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi Reviewed-by: bobzhou --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 -- drivers/gpu/drm/amd/dkms/config/config.h | 11 +-- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 69 +++++++++++++------ .../backport/kcl_drm_dp_mst_helper_backport.h | 16 ++++- 4 files changed, 71 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 263688d7b0869..18b59e6a47cc2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -623,15 +623,11 @@ dm_dp_mst_detect(struct drm_connector *connector, static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { -#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); -#else - return 0; -#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 80c53f2d9f8e1..90f3ddc474c8c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -307,6 +307,12 @@ /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ + /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ @@ -314,10 +320,7 @@ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ /* drm_dp_atomic_release_time_slots() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ - -/* drm_dp_atomic_find_vcpi_slots() wants 5args */ -#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index c89bcdbf10edd..d50c35a4fd1bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -22,8 +22,55 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) + dnl # -dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # commit v5.19-rc6-1758-gdf78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ],[ + dnl # + dnl # commit v4.20-rc4-1031-geceae1472467 + dnl # drm/dp_mst: Start tracking per-port VCPI allocations + dnl # + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ],[ + int ret; + struct drm_dp_mst_port *port; + ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + ]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.19-rc6-1758-gdf78f7f660cd dnl # drm/display/dp_mst: Call them time slots, not VCPI slots dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ @@ -102,29 +149,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ ]) ]) -dnl # -dnl # commit v6.1-rc1~27-df78f7f660cd -dnl # drm/display/dp_mst: Call them time slots, not VCPI slots -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int ret; - ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); - ],[ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, - [drm_dp_atomic_release_time_slots() is available]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK - AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 97af03bd3e628..c6de78678e856 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -38,6 +38,8 @@ int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif + +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, @@ -63,7 +65,6 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) static inline int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_topology_mgr *mgr, @@ -73,6 +74,19 @@ int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, return drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn, pbn_div); } #define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots +#endif /* HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ + +#if !defined(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS) +#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT +static inline +int _kcl_drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port) +{ + return drm_dp_atomic_release_vcpi_slots(state, mgr, port); +} +#define drm_dp_atomic_release_time_slots _kcl_drm_dp_atomic_release_time_slots +#endif #endif #ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS From 7d97801602fd01fc131f55d2eeb45adaa26cc47e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 3 Apr 2023 13:46:08 +0800 Subject: [PATCH 1058/2070] drm/amdkcl: fake kcl copy of zone_device_page_init Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/zone_device_page_init.m4 | 12 ++++++++++++ include/kcl/kcl_mm.h | 4 ++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 9d7534002b7e1..d151a6db046cc 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -5,6 +5,7 @@ * Copyright (C) 1991, 1992 Linus Torvalds */ #include +#include #ifndef HAVE_MMPUT_ASYNC void (*_kcl_mmput_async)(struct mm_struct *mm); @@ -16,6 +17,19 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +/* copied from v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c and modified for kcl usage */ +void zone_device_page_init(struct page *page) +{ +/* v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount */ +#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) + get_page(page); +#endif + lock_page(page); +} +EXPORT_SYMBOL_GPL(zone_device_page_init); +#endif + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 90f3ddc474c8c..e489d6ba8509b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1078,6 +1078,9 @@ /* is_device_page is available */ /* #undef HAVE_ZONE_DEVICE_PUBLIC */ +/* zone_device_page_init() is available */ +#define HAVE_ZONE_DEVICE_PAGE_INIT 1 + /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7da352f9e719d..8674fabd80678 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -171,6 +171,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 new file mode 100644 index 0000000000000..d73aab950a652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c: take a pgmap reference on page allocation +dnl # v6.0-rc3-596-gef233450898f mm: free device private pages have zero refcount +dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 781ea2b6af9fe..89dd906d2659f 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,6 +26,10 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +void zone_device_page_init(struct page *page); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From ea5d3bfd4c37ab4832e8725e23a0e69fdb705f59 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 18 Feb 2023 16:19:33 +0800 Subject: [PATCH 1059/2070] drm/amdkcl: wrap code under macro HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by e43a06a5ef73e1329861ad3a70c490d3eb6e072b "drm/amdgpu: Add notifier lock for KFD userptrs" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 15 ++++-- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 47 ++++++++++++------- 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 2310603ad4696..53255cdebf282 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -72,7 +72,11 @@ struct kgd_mem { struct amdgpu_bo *bo; struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct amdgpu_hmm_range *range; +#else + struct page **user_pages; +#endif struct list_head attachments; /* protected by amdkfd_process_info.lock */ struct list_head validate_list; @@ -84,9 +88,6 @@ struct kgd_mem { uint32_t invalid; struct amdkfd_process_info *process_info; -#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED - struct page **user_pages; -#endif struct amdgpu_sync sync; @@ -208,8 +209,12 @@ int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem); +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); +#endif int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, uint32_t domain, struct dma_fence *fence); @@ -232,8 +237,12 @@ void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) } static inline +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) +#endif { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f839c9f134286..43cd1b6ad35fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2025,17 +2025,6 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( list_del_init(&mem->validate_list); mutex_unlock(&process_info->lock); -#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED - /* Free user pages if necessary */ - if (mem->user_pages) { - pr_debug("%s: Freeing user_pages array\n", __func__); - if (mem->user_pages[0]) - release_pages(mem->user_pages, - mem->bo->tbo.ttm->num_pages); - kvfree(mem->user_pages); - } -#endif - ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) return ret; @@ -2043,8 +2032,19 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Cleanup user pages and MMU notifiers */ if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { amdgpu_hmm_unregister(mem->bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(mem->range); mem->range = NULL; +#else + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, + mem->bo->tbo.ttm->num_pages); + kvfree(mem->user_pages); + } +#endif } amdgpu_amdkfd_remove_eviction_fence(mem->bo, @@ -2829,9 +2829,16 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, * restore, where we get updated page addresses. This function only * ensures that GPU access to the BO is stopped. */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) { + struct mm_struct *mm = mni->mm; +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, + struct mm_struct *mm) +{ +#endif struct amdkfd_process_info *process_info = mem->process_info; int r = 0; @@ -2842,12 +2849,14 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, return 0; mutex_lock(&process_info->notifier_lock); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mmu_interval_set_seq(mni, cur_seq); +#endif mem->invalid++; if (++process_info->evicted_bos == 1) { /* First eviction, stop the queues */ - r = kgd2kfd_quiesce_mm(mni->mm, + r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR); if (r && r != -ESRCH) @@ -3081,7 +3090,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) #else /* Copy pages array and validate the BO if we got user pages */ - if (mem->user_pages[0]) { + if (mem->user_pages && mem->user_pages[0]) { amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -3093,12 +3102,12 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } /* Validate succeeded, now the BO owns the pages, free - * our copy of the pointer array. Put this BO back on - * the userptr_valid_list. If we need to revalidate - * it, we need to start from scratch. + * our copy of the pointer array. */ - kvfree(mem->user_pages); - mem->user_pages = NULL; + if (mem->user_pages) { + kvfree(mem->user_pages); + mem->user_pages = NULL; + } #endif /* Update mapping. If the BO was not validated @@ -3147,6 +3156,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i list_for_each_entry_safe(mem, tmp_mem, &process_info->userptr_inval_list, validate_list) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool valid; /* keep mem without hmm range at userptr_inval_list */ @@ -3163,6 +3173,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i ret = -EAGAIN; continue; } +#endif if (mem->invalid) { WARN(1, "Valid BO is marked invalid"); From d774520a55c4c16e053d03c7f977b1ab7227d4ca Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 17 Apr 2023 16:30:57 +0800 Subject: [PATCH 1060/2070] drm/amdkcl: convert gfx.kiq to array type It's caused by 81a6a08325e46b446a249fca7f76b77937b3f77d "drm/amdgpu: convert gfx.kiq to array type (v3)" After modifying the struct amdgpu_gfx, some non-upstream code need to be updated. Signed-off-by: bobzhou Reviewed-by: Guchun Chen --- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 24 +++++++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++---- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 1dd189536c764..f58291c1fd40b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -27,32 +27,32 @@ void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); if (cntl) adev->gfx.spmfuncs->start(adev); else adev->gfx.spmfuncs->stop(adev); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); } void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->set_rdptr(adev, rptr); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); } int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; int r; if (!adev->gfx.rlc.funcs->update_spm_vmid) @@ -66,24 +66,24 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); /* set spm ring registers */ - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); return r; } void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; /* stop spm stream and interrupt */ - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->stop(adev); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index a49c510f660de..88d85a8e6089f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7798,7 +7798,7 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static void gfx_v10_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); @@ -7828,7 +7828,7 @@ static void gfx_v10_0_spm_start(struct amdgpu_device *adev) static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, @@ -7844,7 +7844,7 @@ static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); @@ -7853,7 +7853,7 @@ static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 25ec1ca8df8d6..1dbc8ddc31977 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5277,7 +5277,7 @@ static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, static void gfx_v8_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); @@ -5302,7 +5302,7 @@ static void gfx_v8_0_spm_start(struct amdgpu_device *adev) static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, @@ -5316,7 +5316,7 @@ static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); } @@ -5324,7 +5324,7 @@ static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b96cedea1030a..56a42deae1ae5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4803,7 +4803,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) static void gfx_v9_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); @@ -4827,7 +4827,7 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, @@ -4843,7 +4843,7 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); @@ -4851,7 +4851,7 @@ static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); From 76c017389754179f2dd9d63b6ae053c0c88d383c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 17 Apr 2023 15:13:41 +0800 Subject: [PATCH 1061/2070] drm/amdkcl: drop obsolete file symbols not needed anymore Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/symbols | 1 - drivers/gpu/drm/amd/dkms/pre-build.sh | 9 --------- 3 files changed, 1 insertion(+), 11 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/symbols diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index cd69c6ce28ec0..addade804e9ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -amdkcl-y += main.o symbols.o kcl_common.o +amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o diff --git a/drivers/gpu/drm/amd/amdkcl/symbols b/drivers/gpu/drm/amd/amdkcl/symbols deleted file mode 100644 index fe167314985be..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/symbols +++ /dev/null @@ -1 +0,0 @@ -SYMS="" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 07df3f07ea532..3d7f2084cae3e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -27,17 +27,8 @@ version_le () { [ "$KERNELVER_BASE" = "$oldest" ] } -source $KCL/symbols source $KCL/files -# lookup symbol address. obsolete. -echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c -for sym in $SYMS; do - awk -v sym=$sym '$3 == sym { - print "void *_kcl_" $3 " = (void *)0x" $1 ";" - }' /boot/System.map-$KERNELVER >>$KCL/symbols.c -done - sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ From d4dbf61b6a5dc4c79651577491f5009e3142a7a5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Apr 2023 10:27:09 +0800 Subject: [PATCH 1062/2070] drm/amdkcl: fix warning for kcl_apple-gmux.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add linux/pnp.h for build warning include/kcl/kcl_apple-gmux.h:8:45: warning: ‘struct pnp_dev’ declared inside parameter list will not be visible outside of this definition or declaration static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) ^~~~~~~ Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_apple-gmux.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_apple-gmux.h b/include/kcl/kcl_apple-gmux.h index 27d96810046e7..4e478cb3a1e87 100644 --- a/include/kcl/kcl_apple-gmux.h +++ b/include/kcl/kcl_apple-gmux.h @@ -2,6 +2,7 @@ #define AMDKCL_APPLE_GMUX_H #include +#include #ifndef HAVE_APPLE_GMUX_DETECT #if IS_ENABLED(CONFIG_APPLE_GMUX) From 400713e56c59e881a44f78ac004abe2358ce7e53 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 18 Apr 2023 15:06:01 +0800 Subject: [PATCH 1063/2070] drm/amdkcl: add fake macros for link_edp_panel_control.c It's caused by 200199ae9a64ad94e42ea995f9a9d4d362b3ff99 "drm/amd/display: Adding support for VESA SCR" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 9f921c3d9db24..532d8160eba9d 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -350,4 +350,18 @@ enum drm_dp_phy { #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ #endif +/* + * v6.1-4885-g200199ae9a64 + * drm/amd/display: Adding support for VESA SCR + */ +#ifndef DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE +#define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4) +#endif +#ifndef DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE +#define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7) +#endif +#ifndef DP_EDP_PANEL_TARGET_LUMINANCE_VALUE +#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 07ad805188814966476b40f485bf1e6b66e651d9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Apr 2023 10:47:22 +0800 Subject: [PATCH 1064/2070] drm/amdkcl: include string_helpers.h for str_yes_no() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dkms build on some distro system reports amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1708:47: error: implicit declaration of function ‘str_yes_no’; did you mean ‘strcspn’? [-Werror=implicit-function-declaration] these distro systems need linux/string_helpers.h, so include it. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_string_helpers.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h index ceac153f44bfd..e02c0059b3ade 100644 --- a/include/kcl/kcl_string_helpers.h +++ b/include/kcl/kcl_string_helpers.h @@ -2,7 +2,7 @@ #ifndef AMDKCL_STRING_HELPERS_H #define AMDKCL_STRING_HELPERS_H - +#include /* Copied from v5.17-rc2-224-gea4692c75e1c linux/string_helpers.h */ #ifndef HAVE_STR_YES_NO From 53a977f532551b02e4af844b4a8a9a99a18e2c86 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Apr 2023 15:37:15 +0800 Subject: [PATCH 1065/2070] drm/amdkcl: fake migrate_enable/disable() It's caused by 71c32def3700558ae3ecbb0e8aaea2378651b59c "drm/amd/display: Disable migration to ensure consistency of per-CPU variable" Signed-off-by: Bob Zhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 | 16 ++++++++++++++++ include/kcl/kcl_preempt.h | 11 +++++++++++ 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e489d6ba8509b..c2c755bad9e44 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -491,6 +491,12 @@ drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ +/* drm_fb_helper_alloc_info() is available */ +#define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 + +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8674fabd80678..34eae8ce68976 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -129,6 +129,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 new file mode 100644 index 0000000000000..5ffb95e258143 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.6-rc2-1-g66630058e56b +dnl # sched/rt: Provide migrate_disable/enable() inlines +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_DISABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + migrate_disable(); + ],[ + AC_DEFINE(HAVE_MIGRATE_DISABLE, 1, + [migrate_disable() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h index 1e59cbca1bf73..cc861beb098ae 100644 --- a/include/kcl/kcl_preempt.h +++ b/include/kcl/kcl_preempt.h @@ -53,4 +53,15 @@ (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET))) #endif +#ifndef HAVE_MIGRATE_DISABLE +static __always_inline void migrate_disable(void) +{ + preempt_disable(); +} +static __always_inline void migrate_enable(void) +{ + preempt_enable(); +} +#endif /* HAVE_MIGRATE_DISABLE */ + #endif /* AMDKCL_PREEMPT_H */ From 969ad654795dd60df9b47d8fc80eee3a94ef89d3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 16:25:06 +0800 Subject: [PATCH 1066/2070] drm/amdkcl: test whether drm_edid_override_connector_update() is available It's caused by 068553e14f869664ca66e63e5200b69db8ae8990 "drm/amd/display: assign edid_blob_ptr with edid from debugfs" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 | 32 ++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_edid.h | 20 +++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_edid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4aec2ea045a87..b41cfec4ea860 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -101,4 +101,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c2c755bad9e44..4f09f48780dc9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -542,6 +542,12 @@ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ + /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ /* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 index 02a5a8a2b5875..e2a939c448834 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -33,3 +33,35 @@ AC_DEFUN([AC_AMDGPU_DRM_EDID], [ ]) ]) ]) + +dnl # +dnl # v6.1-rc1-143-g019b93874834 +dnl # drm/edid: rename drm_add_override_edid_modes() to drm_edid_override_connector_update() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_edid_override_connector_update(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE, 1, + [drm_edid_override_connector_update() is available]) + ],[ + dnl # + dnl # v5.2-rc2-25-g48eaeb7664c7 + dnl # drm: add fallback override/firmware EDID modes workaround + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_add_override_edid_modes(NULL); + ],[ + AC_DEFINE(HAVE_DRM_ADD_OVERRIDE_EDID_MODES, 1, + [drm_add_override_edid_modes() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 34eae8ce68976..5afb4eb998871 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,6 +72,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/include/kcl/backport/kcl_drm_edid.h b/include/kcl/backport/kcl_drm_edid.h new file mode 100644 index 0000000000000..2076f6fe8b2b2 --- /dev/null +++ b/include/kcl/backport/kcl_drm_edid.h @@ -0,0 +1,20 @@ +#ifndef AMDKCL_BACKPORT_DRM_EDID_H +#define AMDKCL_BACKPORT_DRM_EDID_H + +#include + +#if !defined(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE) +#ifdef HAVE_DRM_ADD_OVERRIDE_EDID_MODES +static inline int _kcl_drm_edid_override_connector_update(struct drm_connector *connector) +{ + int ret; + + ret = drm_add_override_edid_modes(connector); + return ret; +} + +#define drm_edid_override_connector_update _kcl_drm_edid_override_connector_update +#endif +#endif + +#endif From 41426af253946433c619a2d068bf57308fca041d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 23 Apr 2023 10:56:25 +0800 Subject: [PATCH 1067/2070] drm/amdkcl: wrap code under macro HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by 529960ba2a622107c0115345f648de441048e244 "drm/amdkfd: Fix an issue at userptr buffer validation process." Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 43cd1b6ad35fa..dfc3800ae0718 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3012,7 +3012,9 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, goto unlock_out; } /* set mem valid if mem has hmm range associated */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (mem->range) +#endif mem->invalid = 0; } From a5b41ddb9c59e9cc61f6edfd9704bad61dc8ad6b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 23 Apr 2023 11:29:55 +0800 Subject: [PATCH 1068/2070] drm/amdkcl: test whether drm_connector->edid_override is available It's caused by 4596e8af5f3d520dcd2edf009aa785ad4cdc50e8 "drm/amd/display: implement force function in amdgpu_dm_connector_funcs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 7 +++++-- drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bccbea71bfcbd..594b6d2d7f67e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7867,6 +7867,7 @@ amdgpu_dm_connector_late_register(struct drm_connector *connector) return 0; } +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7903,6 +7904,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) &dc_em_sink->edid_caps); } } +#endif static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .reset = amdgpu_dm_connector_funcs_reset, @@ -7915,7 +7917,9 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .atomic_get_property = amdgpu_dm_connector_atomic_get_property, .late_register = amdgpu_dm_connector_late_register, .early_unregister = amdgpu_dm_connector_unregister, +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE .force = amdgpu_dm_connector_funcs_force +#endif }; static int get_modes(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4f09f48780dc9..f7467ed634abc 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -834,8 +834,11 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 -/* mem_encrypt_active() is available */ -#define HAVE_MEM_ENCRYPT_ACTIVE 1 +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + +/* struct migrate_vma has fault_page */ +#define HAVE_MIGRATE_VMA_FAULT_PAGE 1 /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 new file mode 100644 index 0000000000000..43fb1565aabc0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.1-rc1-146-g90b575f52c6a +dnl # drm/edid: detach debugfs EDID override from EDID property update +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector *connector = NULL; + connector->edid_override = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_EDID_OVERRIDE, 1, + [drm_connector->edid_override is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5afb4eb998871..76e0cff8c8654 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -80,6 +80,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS + AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From c5384abdb5a63b4d99fefc5439cc8935f1449ae2 Mon Sep 17 00:00:00 2001 From: tiancyin Date: Wed, 26 Apr 2023 11:45:08 +0800 Subject: [PATCH 1069/2070] drm/amdkcl: fix display dp mst malfunction It's caused by ffac9721939dca3f0ac7bfa90f3dc484b19c2706 "drm/display/dp_mst: Don't open code modeset checks for releasing time slots" Reviewed-by: Flora Cui Signed-off-by: tiancyin --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 18b59e6a47cc2..07ab7fb87c0c4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -626,7 +626,24 @@ static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; +#ifndef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS + struct drm_connector_state *new_conn_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_conn_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc_state *new_crtc_state; + + if (!old_conn_state->crtc) + return 0; + if (new_conn_state->crtc) { + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); + if (!new_crtc_state || + !drm_atomic_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->enable) + return 0; + } +#endif return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } #endif From 0476d4ce1e7c37b110f4c5e288e29405af983072 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Apr 2023 17:30:43 +0800 Subject: [PATCH 1070/2070] drm/amdkcl: fake macro DEFINE_DEBUGFS_ATTRIBUTE_SIGNED It's caused by 891d215cff04e230777a4b2b8611df31e7b822d2 "drm/amdgpu: add amdgpu_error_* debugfs file" Signed-off-by: Flora Cui Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 6 +- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c | 97 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_debugfs.h | 56 +++++++++++ 5 files changed, 159 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c create mode 100644 include/kcl/kcl_debugfs.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 83750ab4e81b5..e61371de6a75b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -681,6 +681,7 @@ static const struct file_operations amdgpu_debugfs_mqd_fops = { .llseek = default_llseek }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int amdgpu_debugfs_ring_error(void *data, u64 val) { struct amdgpu_ring *ring = data; @@ -691,7 +692,7 @@ static int amdgpu_debugfs_ring_error(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, amdgpu_debugfs_ring_error, "%lld\n"); - +#endif #endif void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, @@ -719,10 +720,11 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, ring->mqd_size); } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE sprintf(name, "amdgpu_error_%s", ring->name); debugfs_create_file(name, 0200, root, ring, &amdgpu_debugfs_error_fops); - +#endif #endif } diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index addade804e9ed..5563e79634c1c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,6 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o +amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c new file mode 100644 index 0000000000000..def9db4463a22 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * inode.c - part of debugfs, a tiny little debug file system + * + * Copyright (C) 2004,2019 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * Copyright (C) 2019 Linux Foundation + * + * debugfs is for people to use instead of /proc or /sys. + * See ./Documentation/core-api/kernel-api.rst for more details. + */ + +#include +#include +#include + +#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +/* Copied from fs/libfs.c */ +struct simple_attr { + int (*get)(void *, u64 *); + int (*set)(void *, u64); + char get_buf[24]; /* enough to store a u64 and "\n\0" */ + char set_buf[24]; + void *data; + const char *fmt; /* format for read operation */ + struct mutex mutex; /* protects access to these buffers */ +}; + +static ssize_t simple_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct simple_attr *attr; + unsigned long long val; + size_t size; + ssize_t ret; + + attr = file->private_data; + if (!attr->set) + return -EACCES; + + ret = mutex_lock_interruptible(&attr->mutex); + if (ret) + return ret; + + ret = -EFAULT; + size = min(sizeof(attr->set_buf) - 1, len); + if (copy_from_user(attr->set_buf, buf, size)) + goto out; + + attr->set_buf[size] = '\0'; + if (is_signed) + ret = kstrtoll(attr->set_buf, 0, &val); + else + ret = kstrtoull(attr->set_buf, 0, &val); + if (ret) + goto out; + ret = attr->set(attr->data, val); + if (ret == 0) + ret = len; /* on success, claim we got the whole input */ +out: + mutex_unlock(&attr->mutex); + return ret; +} + +ssize_t simple_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return simple_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(simple_attr_write_signed); + +/* Copied from fs/debugfs/file.c */ +#define F_DENTRY(filp) ((filp)->f_path.dentry) +static ssize_t debugfs_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct dentry *dentry = F_DENTRY(file); + ssize_t ret; + + ret = debugfs_file_get(dentry); + if (unlikely(ret)) + return ret; + if (is_signed) + ret = simple_attr_write_signed(file, buf, len, ppos); + else + ret = simple_attr_write(file, buf, len, ppos); + debugfs_file_put(dentry); + return ret; +} + +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return debugfs_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(debugfs_attr_write_signed); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b41cfec4ea860..3174602b972db 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -102,4 +102,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h new file mode 100644 index 0000000000000..ca6a8d391da78 --- /dev/null +++ b/include/kcl/kcl_debugfs.h @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * debugfs.h - a tiny little debug file system + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * + * debugfs is for people to use instead of /proc or /sys. + * See Documentation/filesystems/ for more details. + */ + +#ifndef KCL_DEBUGFS_H_ +#define KCL_DEBUGFS_H_ + +#include +#include +#include + +#include +#include + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) && !defined(DEFINE_DEBUGFS_ATTRIBUTE_SIGNED) +#define KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#define DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, __is_signed) \ +static int __fops ## _open(struct inode *inode, struct file *file) \ +{ \ + __simple_attr_check_format(__fmt, 0ull); \ + return simple_attr_open(inode, file, __get, __set, __fmt); \ +} \ +static const struct file_operations __fops = { \ + .owner = THIS_MODULE, \ + .open = __fops ## _open, \ + .release = simple_attr_release, \ + .read = debugfs_attr_read, \ + .write = (__is_signed) ? debugfs_attr_write_signed : debugfs_attr_write, \ + .llseek = no_llseek, \ +} + +#define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ + DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) + +#if defined(CONFIG_DEBUG_FS) +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos); +#else +static inline ssize_t debugfs_attr_write_signed(struct file *file, + const char __user *buf, + size_t len, loff_t *ppos) +{ + return -ENODEV; +} +#endif /* CONFIG_DEBUG_FS */ + +#endif /* DEFINE_DEBUGFS_ATTRIBUTE_SIGNED */ + +#endif From 833d4d6ef697570c1d867e1ef357aa3b8b0b2275 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 10 May 2023 17:39:34 +0800 Subject: [PATCH 1071/2070] Revert "drm/amdgpu: mark force completed fences with -ECANCELED" This reverts commit 44c41d7de74acbfec110ea28e400e051c1333f0d. This reverted patch causes a modprobe issue. (SWDEV-398339) Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 49fc459314a47..27c018d6c20e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -666,7 +666,6 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error) */ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) { - amdgpu_fence_driver_set_error(ring, -ECANCELED); amdgpu_fence_write(ring, ring->fence_drv.sync_seq); amdgpu_fence_process(ring); } From cf3e1bbd37379851b5618ce15260faf4364e3e1d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 20 Apr 2023 15:07:57 +0800 Subject: [PATCH 1072/2070] drm/amdkcl: fake kmalloc_size_roundup Signed-off-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 12 +++++ drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mm-kmalloc_size_roundup.m4 | 17 +++++++ include/kcl/kcl_slab.h | 4 ++ 7 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5563e79634c1c..870d13ea5d582 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o + kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index d151a6db046cc..637ecefbb9773 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -30,9 +30,21 @@ void zone_device_page_init(struct page *page) EXPORT_SYMBOL_GPL(zone_device_page_init); #endif +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB +extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +#endif +#endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif + +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB + _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); +#endif +#endif } diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c new file mode 100644 index 0000000000000..3de9dfff5d0df --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c @@ -0,0 +1,44 @@ +#include +#include +#include + +#if !defined(HAVE_KMALLOC_SIZE_ROUNDUP) +#ifdef CONFIG_SLOB +/* copy from mm/slob.c */ +size_t kmalloc_size_roundup(size_t size) +{ + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + + return ALIGN(size, ARCH_KMALLOC_MINALIGN); +} + +EXPORT_SYMBOL(kmalloc_size_roundup); +#else +/* copy from mm/slab_common.c and modified for KCL usage. */ +struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +size_t kmalloc_size_roundup(size_t size) +{ + struct kmem_cache *c; + + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + /* Above the smaller buckets, size is a multiple of page size. */ + if (size > KMALLOC_MAX_CACHE_SIZE) + return PAGE_SIZE << get_order(size); + + /* The flags don't matter since size_index is common to all. */ + c = _kcl_kmalloc_slab(size, GFP_KERNEL); + return c ? kmem_cache_size(c) : 0; +} +EXPORT_SYMBOL(kmalloc_size_roundup); +#endif +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f7467ed634abc..95d43bcf9e319 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -705,6 +705,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kmalloc_size_roundup is available */ +#define HAVE_KMALLOC_SIZE_ROUNDUP 1 + /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 76e0cff8c8654..bb75fa980c9d8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -174,6 +174,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 new file mode 100644 index 0000000000000..ab6586797229a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.0-rc2-7-g05a940656e1e +dnl # slab: Introduce kmalloc_size_roundup() +dnl # +AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_t a, b; + a = kmalloc_size_roundup(b); + ], [ + AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, + [kmalloc_size_roundup is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index e095f8a46088e..a23a565eab992 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -34,4 +34,8 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) } #endif +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +size_t kmalloc_size_roundup(size_t size); +#endif + #endif From 09d13b4db4586b37228dcef179209ba7ca5ed207 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 9 May 2023 17:16:23 -0400 Subject: [PATCH 1073/2070] Fix unsteady amdgpu dkms build against 5.x kernels Make rules robust against "Argument list too long" error. SWDEV-397841 Change-Id: Ib7e26359097e275801658c1a865831060b11bc51 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/dkms.conf | 2 ++ drivers/gpu/drm/amd/dkms/post-build.sh | 23 +++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 34 ++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100755 drivers/gpu/drm/amd/dkms/post-build.sh diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index bf06588ea6b9c..ec2c979254b55 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,6 +2,8 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" +POST_BUILD="amd/dkms/post-build.sh $kernelver" +POST_REMOVE="amd/dkms/post-build.sh $kernelver" # not all OS supports weak module updates NO_WEAK_MODULES="yes" diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh new file mode 100755 index 0000000000000..962903db89aca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +KERNELVER=$1 + +# +# Restore original kernel 5.x scripts/Makefile.build modified by post-add.sh +# +if [[ ${KERNELVER%%.*} -eq 5 ]]; then + moddir="/lib/modules/$KERNELVER" + mkfile="scripts/Makefile.build" + + if [[ -d "$moddir/source" ]]; then + mkfile="$moddir/source/$mkfile" + else + mkfile="$moddir/build/$mkfile" + fi + + mkfile=$(readlink -f $mkfile) + + if [[ -f "$mkfile~" ]]; then + mv -f $mkfile{~,} + fi +fi diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 3d7f2084cae3e..cdbac6500036c 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -55,6 +55,40 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done +#!/bin/bash + +KERNELVER=$1 + +# +# Kernel 5.x scripts/Makefile.build patch +# The patch makes rules robust against "Argument list too long" error +# +if [[ ${KERNELVER%%.*} -eq 5 ]]; then + moddir="/lib/modules/$KERNELVER" + mkfile="scripts/Makefile.build" + + if [[ -d "$moddir/source" ]]; then + mkfile="$moddir/source/$mkfile" + else + mkfile="$moddir/build/$mkfile" + fi + + mkfile=$(readlink -e $mkfile) + + if [[ "$?" -eq 0 ]] && [[ ! -f "$mkfile~" ]]; then + cp -a ${mkfile}{,~} + sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` + `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` + `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ + -e "s/^[[:space:]]\+cmd_link_multi-m =.*$/"` + `"cmd_link_multi-m = \\\\\n"` + `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` + `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` + `"\trm -f \$@.in/" \ + $mkfile + fi +fi + export KERNELVER (cd $SRC && ./configure) From 7fa2169c5253b90828d4700293a5a31978e46e55 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 17 May 2023 15:07:40 +0800 Subject: [PATCH 1074/2070] drm/amdkcl: modify AMDGPU_GFXHUB_0 to AMDGPU_GFXHUB(0) It's caused by 43ca920837c4ec57875b51272fe66421a4d24666 "drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)" Signed-off-by: Bob Zhou Reviewed-by: majun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index f58291c1fd40b..82c270b3a6946 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,7 +58,7 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB_0); + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); if (r) return r; @@ -85,7 +85,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From 027c1081f95bfa526267772bf5212480ab8f529b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 25 May 2023 16:26:31 +0800 Subject: [PATCH 1075/2070] drm/amdkcl: add mem_id_plus1 argument when invoke amdgpu_gem_object_create It's caused by 4a31ec3828d09618e496bbf16c15e05a2eeaf1ed drm/amdgpu: Add memory partition mem_id to amdgpu_bo Due to mem_id_plus1 is added as a parameter, modify the argument when invoke amdgpu_gem_object_create. Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f352ca01658ac..8d6d8beac461d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -667,6 +667,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_amdgpu_gem_dgma *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_gem_object *gobj; struct amdgpu_bo *abo; dma_addr_t *dma_addr; @@ -678,7 +679,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, - 0, NULL, &gobj); + 0, NULL, &gobj, fpriv->xcp_id + 1); if (r) return r; From 90adbe560e59112a0bd82181f6093627e935f49e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 13:38:44 +0800 Subject: [PATCH 1076/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE It's caused by 8764cee060df560171cf9ac266fa93366200e209 "drm/amdgpu: support partition drm devices" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 5e9f825caeffa..ef25c434576c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3211,8 +3211,11 @@ static struct drm_driver amdgpu_kms_driver = { const struct drm_driver amdgpu_partition_driver = { .driver_features = - DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .ioctls = amdgpu_ioctls_kms, From e18fa792819701e14795565eed4f9984e00fc2ca Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 13:50:38 +0800 Subject: [PATCH 1077/2070] drm/amdkcl: fake page_to_virt() It's caused by 5a3a28ac173e5dab4f4c3533693bd76596a5ae0e "drm/amdgpu: Allocate GART table in RAM for AMD APU" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_mm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 89dd906d2659f..e38dec08515b1 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -85,4 +85,8 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) #define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC) #endif +#ifndef page_to_virt +#define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) +#endif + #endif /* AMDKCL_MM_H */ From ad7b19cff8fcd3a1796c6657285f92ed24e4268c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 15:27:33 +0800 Subject: [PATCH 1078/2070] drm/amdkcl: use amdkcl_ttm_resv to get resv It's caused by 33403d2365e4710712ac8575dd83bd6df61186c0 "drm/amdgpu: Add memory partition mem_id to amdgpu_bo" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index dfc3800ae0718..ec2f366f12b95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -346,7 +346,7 @@ create_dmamap_sg_bo(struct amdgpu_device *adev, ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1, AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags, - ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0); + ttm_bo_type_sg, amdkcl_ttm_resvp(&mem->bo->tbo), &gem_obj, 0); amdgpu_bo_unreserve(mem->bo); From a5999d6430a02e7912e2aa0c45aa610cbce99cf5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 17:03:33 +0800 Subject: [PATCH 1079/2070] drm/amdkcl: fix non-upstream code for modifing kfd_dev to kfd_node It's caused by b0be1be09f5e15f00125940937bbab98c0dbc59d "drm/amdkfd: Introduce kfd_node struct (v5)" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 9 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index f9d9ec61bdc63..4cb64c36832dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2437,7 +2437,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, struct kgd_mem **kgd_mem) { uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); - struct kfd_dev *dev = pdd->dev; + struct kfd_node *dev = pdd->dev; struct kfd_bo *kfd_bo; int ret, idr_handle; uint64_t offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index ad4b19a4c1a4d..1c1b981164db0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -607,7 +607,7 @@ static int kfd_gws_init(struct kfd_node *node) && kfd->mec2_fw_version < 0x30) || (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) - kfd->gws_debug_workaround = true; + node->gws_debug_workaround = true; return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index cbd0d109ea883..3368779e354af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -174,7 +174,7 @@ void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) pr_debug("Process %d unmapping doorbell 0x%lx\n", process->pasid, vma->vm_start); - size = kfd_doorbell_process_slice(pdd->dev); + size = kfd_doorbell_process_slice(pdd->dev->kfd); zap_vma_ptes(vma, vma->vm_start, size); pdd->qpd.doorbell_mapped = 0; } @@ -201,7 +201,7 @@ int kfd_doorbell_remap(struct kfd_process_device *pdd) /* Calculate physical address of doorbell */ address = kfd_get_process_doorbells(pdd); vma = pdd->qpd.doorbell_vma; - size = kfd_doorbell_process_slice(pdd->dev); + size = kfd_doorbell_process_slice(pdd->dev->kfd); pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, vma->vm_start); @@ -251,7 +251,7 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", process->pasid, (unsigned long long) vma->vm_start, - address, vma->vm_flags, kfd_doorbell_process_slice(dev)); + address, vma->vm_flags, kfd_doorbell_process_slice(dev->kfd)); pdd = kfd_get_process_device_data(dev, process); if (WARN_ON_ONCE(!pdd)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 9cb5155809752..ab5769b0fe078 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -130,7 +130,7 @@ int kfd_ipc_init(void) return 0; } -static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, @@ -180,7 +180,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return r; } -int kfd_ipc_import_dmabuf(struct kfd_dev *dev, +int kfd_ipc_import_dmabuf(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, @@ -202,7 +202,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, return r; } -int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore) @@ -253,7 +253,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, return r; } -int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index be0bf2b388194..6e92cce265d9e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -28,7 +28,7 @@ #include /* avoid including kfd_priv.h */ -struct kfd_dev; +struct kfd_node; struct kfd_process; struct kfd_ipc_obj { @@ -39,15 +39,15 @@ struct kfd_ipc_obj { uint32_t flags; }; -int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore); -int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, +int kfd_ipc_import_dmabuf(struct kfd_node *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset); -int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 09cf783e460d3..50541b1dac44a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -140,7 +140,7 @@ struct amd_mem_context { uint64_t size; unsigned long offset; struct amdgpu_bo *bo; - struct kfd_dev *dev; + struct kfd_node *dev; struct sg_table *pages; struct device *dma_dev; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 3b45fd2697d7c..3bbe85b44f4b2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -409,7 +409,7 @@ struct kfd_ipc_obj; struct kfd_bo { void *mem; struct interval_tree_node it; - struct kfd_dev *dev; + struct kfd_node *dev; /* page-aligned VA address */ uint64_t cpuva; unsigned int mem_type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index b1fc5ace4015d..00da1cabcbd45 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -403,7 +403,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev int kfd_rlc_spm(struct kfd_process *p, void *data) { struct kfd_ioctl_spm_args *args = data; - struct kfd_dev *dev; + struct kfd_node *dev; struct kfd_process_device *pdd; dev = kfd_device_by_id(args->gpu_id); @@ -434,9 +434,10 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) return -EINVAL; } -void kgd2kfd_spm_interrupt(struct kfd_dev *dev) +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) { struct kfd_process_device *pdd; + struct kfd_node *dev = kfd->nodes[0]; uint16_t pasid = dev->spm_pasid; struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index cd0d2eb770526..3dcfe7bbd8505 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1281,7 +1281,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, return; /* checkout source dev has atomics support on root. */ - if (dev->gpu && (!dev->gpu->pci_atomic_requested || + if (dev->gpu && (!dev->gpu->kfd->pci_atomic_requested || dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; From 1e415688e1c0f25109caccde6dca55b67c903fef Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 17:21:50 +0800 Subject: [PATCH 1080/2070] drm/amdkcl: test whether acpi_dev_get_first_match_dev() is available It's caused by 69262b1d049af914e2adfd8faf4ea5a78c08d908 "drm/amdgpu: Add parsing of acpi xcc objects" Signed-off-by: Bob Zhou Acked-by: Leslie Shi drm/amdkcl: update range of HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV Clear up some HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV to enable mem_partitions feature. By return NULL, fake acpi_dev_get_first_match_dev bypass APU with old kernel. Signed-off-by: Bob Zhou Reviewed-by:Lijo Lazar --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- .../drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_acpi.h | 8 ++++++++ 4 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 95d43bcf9e319..9ba2d0a2f7cee 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -319,8 +319,8 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* drm_dp_atomic_release_time_slots() is available */ -#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 new file mode 100644 index 0000000000000..f83c2733ac2e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v5.1-rc3-1-g817b4d64da03 +dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_dev_get_first_match_dev], + [drivers/acpi/utils.c], [ + AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, + [acpi_dev_get_first_match_dev() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bb75fa980c9d8..d125a93fa0fc5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -91,6 +91,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h index d6f499640f0b8..4ad8d53bf3cec 100644 --- a/include/kcl/kcl_acpi.h +++ b/include/kcl/kcl_acpi.h @@ -23,4 +23,12 @@ #define ACPI_HANDLE(dev) DEVICE_ACPI_HANDLE(dev) #endif +#ifndef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV +static inline struct acpi_device * +acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) +{ + return NULL; +} +#endif + #endif /* AMDKCL_ACPI_H */ From 2f8bc3fa1216f79cdd9a312c594b65f01ba53692 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 30 May 2023 16:28:19 +0800 Subject: [PATCH 1081/2070] drm/amdkcl: amdxcp module add kcl support It's caused by 7dd353a7623ec9a10f9bfde53b19982f760995a2 "drm/amdxcp: add platform device driver for amdxcp" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdxcp/Makefile | 3 + drivers/gpu/drm/amd/amdxcp/backport/Makefile | 10 +++ .../gpu/drm/amd/amdxcp/backport/backport.h | 1 + .../backport/include/kcl/kcl_amdgpu_drm_drv.h | 42 +++++++++ .../gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c | 85 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms.conf | 4 + 7 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/Makefile create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/backport.h create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c diff --git a/drivers/gpu/drm/amd/amdxcp/Makefile b/drivers/gpu/drm/amd/amdxcp/Makefile index 870501a4bb8c0..5790475464f02 100644 --- a/drivers/gpu/drm/amd/amdxcp/Makefile +++ b/drivers/gpu/drm/amd/amdxcp/Makefile @@ -23,3 +23,6 @@ amdxcp-y := amdgpu_xcp_drv.o obj-$(CONFIG_DRM_AMDGPU) += amdxcp.o + +AMD_XCP_PATH := $(src) +include $(AMD_XCP_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/amd/amdxcp/backport/Makefile b/drivers/gpu/drm/amd/amdxcp/backport/Makefile new file mode 100644 index 0000000000000..4217ff962b225 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/Makefile @@ -0,0 +1,10 @@ +BACKPORT_OBJS := kcl_drm_drv.o + +amdxcp-y += $(addprefix ./backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(AMD_XCP_PATH)/ \ + -I$(AMD_XCP_PATH)/backport/include \ + -I$(AMD_XCP_PATH)/../dkms \ + -include config/config.h \ + -include backport/backport.h diff --git a/drivers/gpu/drm/amd/amdxcp/backport/backport.h b/drivers/gpu/drm/amd/amdxcp/backport/backport.h new file mode 100644 index 0000000000000..155f55d669456 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/backport.h @@ -0,0 +1 @@ +#include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..c331d7f60606b --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,42 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..4b2d043f4665a --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -0,0 +1,85 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +static void devm_drm_dev_init_release(void *data) +{ + drm_dev_put(data); + +#ifndef HAVE_DRM_DRM_MANAGED_H + if(data){ + struct drm_device *dev = data; + if(!kref_read(&dev->ref)) + kfree(dev->dev_private); + } +#endif +} +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +static int devm_drm_dev_init(struct device *parent, + struct drm_device *dev, + const struct drm_driver *driver) +{ + int ret; + + ret = drm_dev_init(dev, driver, parent); + if (ret) + return ret; + + return devm_add_action_or_reset(parent, + devm_drm_dev_init_release, dev); +} + +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + drm = container + offset; + ret = devm_drm_dev_init(parent, drm, driver); + if (ret) { + kfree(container); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#else + drm->dev_private = container; +#endif + return container; +} + +#endif diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0c7477083f0ec..39facc822b351 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -223,4 +223,4 @@ include $(src)/amd/dkms/Makefile.drm_ttm_helper include $(src)/amd/dkms/Makefile.drm_buddy -obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ +obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index ec2c979254b55..78cc07704d491 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -34,6 +34,10 @@ BUILT_MODULE_NAME[5]="amddrm_buddy" BUILT_MODULE_LOCATION[5]="." DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" +BUILT_MODULE_NAME[6]="amdxcp" +BUILT_MODULE_LOCATION[6]="amd/amdxcp" +DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" + MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ From fb8a5bbf1e18432d37104e73d9f949c7deb59b95 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 5 Jun 2023 13:51:23 +0800 Subject: [PATCH 1082/2070] drm/amdkcl: fake macro DECLARE_FLEX_ARRAY It's caused by 46ca366ec5b07937357d6c0aaecf706b3b762abd "drm/amdgpu/discovery: Replace fake flex-arrays with flexible-array members" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_stddef.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/kcl/kcl_stddef.h b/include/kcl/kcl_stddef.h index dc455e1423ab1..2656ab3239f48 100644 --- a/include/kcl/kcl_stddef.h +++ b/include/kcl/kcl_stddef.h @@ -13,4 +13,22 @@ #define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) #endif +#ifndef DECLARE_FLEX_ARRAY +/** + * DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union + * + * @TYPE: The type of each flexible array element + * @NAME: The name of the flexible array member + * + * In order to have a flexible array member in a union or alone in a + * struct, it needs to be wrapped in an anonymous struct with at least 1 + * named member, but that member can be empty. + */ +#define DECLARE_FLEX_ARRAY(TYPE, NAME) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[]; \ + } +#endif + #endif From 560741626757c423cc606b53534957950c5f7d19 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 7 Jun 2023 14:13:26 +0800 Subject: [PATCH 1083/2070] drm/amdkcl: check whether drm_gem_object->resv is available It's caused by c7cc29bdccb3ba26fe4de78df70c4c9c8a279af8 "drm/amdgpu: Add a low priority scheduler for VRAM clearing" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b467a3e276192..8ad49c0a28a83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -740,7 +740,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r = amdgpu_ttm_clear_buffer(bo, amdkcl_ttm_resvp(&bo->tbo), &fence); if (unlikely(r)) goto fail_unreserve; @@ -1363,13 +1363,13 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (r) goto out; - r = amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &bo->base._resv, + r = amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &amdkcl_ttm_resv(bo), &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; amdgpu_vram_mgr_set_cleared(bo->resource); - dma_resv_add_fence(&bo->base._resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(&amdkcl_ttm_resv(bo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); out: From f67e16732e11c1d0a104f7ea4ff6ca6cbfb3035f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 1 Aug 2023 17:10:04 +0800 Subject: [PATCH 1084/2070] drm/amdkcl: kcl-cleanup for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 31 ------------------- 2 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 594b6d2d7f67e..f71985dbec4f6 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12781,11 +12781,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } -#if !defined(for_each_new_crtc_in_state) - for_each_crtc_in_state(state, crtc, new_crtc_state, i) { -#else for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { -#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->mpo_requested) drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index f37529b88f778..0f8cbf63cc505 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -253,31 +253,6 @@ struct amdgpu_dm_backlight_caps { struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; -/** - * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic - * update in reverse order - * @__state: &struct drm_atomic_state pointer - * @plane: &struct drm_plane iteration cursor - * @old_plane_state: &struct drm_plane_state iteration cursor for the old state - * @new_plane_state: &struct drm_plane_state iteration cursor for the new state - * @__i: int iteration cursor, for macro-internal use - * - * This iterates over all planes in an atomic update in reverse order, - * tracking both old and new state. This is useful in places where the - * state delta needs to be considered, for example in atomic check functions. - */ -#if !defined(for_each_oldnew_plane_in_state_reverse) && \ - defined(for_each_oldnew_plane_in_state) -#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ - for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ - (__i) >= 0; \ - (__i)--) \ - for_each_if ((__state)->planes[__i].ptr && \ - ((plane) = (__state)->planes[__i].ptr, \ - (old_plane_state) = (__state)->planes[__i].old_state,\ - (new_plane_state) = (__state)->planes[__i].new_state, 1)) -#endif - /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations @@ -292,7 +267,6 @@ struct dal_allocation { u64 gpu_addr; }; - /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work @@ -1150,12 +1124,7 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, -#ifndef for_each_new_connector_in_state - struct drm_crtc *crtc, - bool from_state_var); -#else struct drm_crtc *crtc); -#endif int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); From 2fd77992a278f5b1387dd55461be42485f9766fa Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Jun 2023 18:46:51 +0800 Subject: [PATCH 1085/2070] drm/amdkcl: Optimize the interrupt the process function Fake the generic_handle_domain_irq function to optimize the irq process function Signed-off-by: Ma Jun Reviewed-by: Flora.Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ---- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c | 38 ++++++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_irqdesc.h | 11 +++++++ 5 files changed, 52 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c create mode 100644 include/kcl/kcl_irqdesc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index c5eb38ca11618..2167d7856f782 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -512,12 +512,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { -#ifdef HAVE_GENERIC_HANDLE_DOMAIN_IRQ generic_handle_domain_irq(adev->irq.domain, src_id); -#else - generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); -#endif - } else if (!adev->irq.client[client_id].sources) { dev_dbg(adev->dev, "Unregistered interrupt client_id: %d src_id: %d\n", diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 870d13ea5d582..33cbe6ba3bf43 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o + kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ + kcl_irqdesc.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c new file mode 100644 index 0000000000000..e53a60dbb71f0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar + * Copyright (C) 2005-2006, Thomas Gleixner, Russell King + * + * This file contains the interrupt descriptor management code. Detailed + * information is available in Documentation/core-api/genericirq.rst + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/** + * generic_handle_irq - Invoke the handler for a particular irq + * @irq: The irq number to handle + * + * Returns: 0 on success, or -EINVAL if conversion has failed + * + * This function must be called from an IRQ context with irq regs + * initialized. + */ +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq) +{ + int irq; + irq = irq_find_mapping(domain, hwirq); + + return generic_handle_irq(irq); +} +EXPORT_SYMBOL_GPL(kcl_generic_handle_domain_irq); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3174602b972db..daf3327ecaa48 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -103,4 +103,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_irqdesc.h b/include/kcl/kcl_irqdesc.h new file mode 100644 index 0000000000000..1e439ea146d7c --- /dev/null +++ b/include/kcl/kcl_irqdesc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMDKCL_IRQDESC_H +#define AMDKCL_IRQDESC_H + +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq); +#define generic_handle_domain_irq kcl_generic_handle_domain_irq +#endif /* HAVE_GENERIC_HANDLE_DOMAIN_IRQ */ + +#endif From 40124720923552b39fadb17c55e8ed4881d23340 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 29 May 2023 16:08:12 +0800 Subject: [PATCH 1086/2070] drm/amdkcl:drop redundant sched job cleanup It's caused by e9cc9cd75f2ce58751619436133cf44617268060 "drm/amdgpu: drop redundant sched job cleanup when cs is aborted" Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 1e2223e14f9ea..d55f3a905931a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1463,7 +1463,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { r = -ERESTARTSYS; - goto error_unlock; + amdgpu_mn_unlock(p->mn); + return r; } } #endif From 21a323368ce9fbaf0b2682d4739500c9024f490f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jun 2023 15:13:26 +0800 Subject: [PATCH 1087/2070] drm/amdkcl: fake macro PCI_CLASS_ACCELERATOR_PROCESSING It's caused by 186e61eda3749bf2ec669f73fa7c10bdf049a7ce "drm/amdgpu: add the accelerator PCIe class" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_pci_ids.h | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 include/kcl/kcl_pci_ids.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index daf3327ecaa48..2e14714c2a662 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -104,4 +104,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_pci_ids.h b/include/kcl/kcl_pci_ids.h new file mode 100644 index 0000000000000..e56bf58438f5b --- /dev/null +++ b/include/kcl/kcl_pci_ids.h @@ -0,0 +1,10 @@ +#ifndef AMDKCL_PCI_IDS_H +#define AMDKCL_PCI_IDS_H + +#include + +#ifndef PCI_CLASS_ACCELERATOR_PROCESSING +#define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200 +#endif + +#endif \ No newline at end of file From 91edc96755e4b12d1d46e3164e1375ecf239878b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jun 2023 13:39:20 +0800 Subject: [PATCH 1088/2070] drm/amdkcl: fake drm_mode_create_colorspace_property functions It's cauesd by a9fa9b21c98f7ebeb76897c1f9c6796508aed5a5 "drm/amd/display: Register Colorspace property for DP and HDMI" Signed-off-by: Bob Zhou --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 163 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 15 ++ ...rm_mode_create_hdmi_colorspace_property.m4 | 49 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 50 ++++++ 5 files changed, 278 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index a4a4e8d2e9acf..559b2610f2966 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -89,3 +89,166 @@ int _kcl_drm_connector_set_panel_orientation_with_quirk( } EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); #endif + +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +struct drm_property *prop = NULL; +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector) +{ + if(prop) + drm_object_attach_property(&connector->base, prop, DRM_MODE_COLORIMETRY_DEFAULT); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_connector_attach_colorspace_property); +#endif + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +/* copy from drivers/gpu/drm/drm_connector.c (v6.1-5788-gac3470b13f0d) */ +static const char * const colorspace_names[] = { + /* For Default case, driver will set the colorspace */ + [DRM_MODE_COLORIMETRY_DEFAULT] = "Default", + /* Standard Definition Colorimetry based on CEA 861 */ + [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = "SMPTE_170M_YCC", + [DRM_MODE_COLORIMETRY_BT709_YCC] = "BT709_YCC", + /* Standard Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_601] = "XVYCC_601", + /* High Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_709] = "XVYCC_709", + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */ + [DRM_MODE_COLORIMETRY_SYCC_601] = "SYCC_601", + /* Colorimetry based on IEC 61966-2-5 [33] */ + [DRM_MODE_COLORIMETRY_OPYCC_601] = "opYCC_601", + /* Colorimetry based on IEC 61966-2-5 */ + [DRM_MODE_COLORIMETRY_OPRGB] = "opRGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_CYCC] = "BT2020_CYCC", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_RGB] = "BT2020_RGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_YCC] = "BT2020_YCC", + /* Added as part of Additional Colorimetry Extension in 861.G */ + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65] = "DCI-P3_RGB_D65", + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER] = "DCI-P3_RGB_Theater", + [DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED] = "RGB_WIDE_FIXED", + /* Colorimetry based on scRGB (IEC 61966-2-2) */ + [DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT] = "RGB_WIDE_FLOAT", + [DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC", +}; + +static const u32 hdmi_colorspaces = + BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER); + +static const u32 dp_colorspaces = + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED) | + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT601_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); + +static int drm_mode_create_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + struct drm_device *dev = connector->dev; + u32 colorspaces = supported_colorspaces | BIT(DRM_MODE_COLORIMETRY_DEFAULT); + struct drm_prop_enum_list enum_list[DRM_MODE_COLORIMETRY_COUNT]; + int i, len; + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (connector->colorspace_property) +#else + if (prop) +#endif + return 0; + + + if (!supported_colorspaces) { + drm_err(dev, "No supported colorspaces provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + if ((supported_colorspaces & -BIT(DRM_MODE_COLORIMETRY_COUNT)) != 0) { + drm_err(dev, "Unknown colorspace provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + len = 0; + for (i = 0; i < DRM_MODE_COLORIMETRY_COUNT; i++) { + if ((colorspaces & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = colorspace_names[i]; + len++; + } +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + connector->colorspace_property = +#else + prop = +#endif + drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace", + enum_list, + len); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (!connector->colorspace_property) +#else + if (!prop) +#endif + return -ENOMEM; + + return 0; +} +#endif /* KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & hdmi_colorspaces; + else + colorspaces = hdmi_colorspaces; + + return drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); +#endif + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & dp_colorspaces; + else + colorspaces = dp_colorspaces; + + return drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9ba2d0a2f7cee..7f5a149600343 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -487,6 +487,21 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 new file mode 100644 index 0000000000000..7a8fe049ac51b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -0,0 +1,49 @@ +dnl # +dnl # commit v5.3-rc1-675-g8806cd3aa025 +dnl # drm: Rename HDMI colorspace property creation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + [drm_connector_attach_colorspace_property() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_hdmi_colorspace_property(NULL, 0); + ], [drm_mode_create_hdmi_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_hdmi_colorspace_property() has 2 args]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_dp_colorspace_property(NULL, 0); + ], [drm_mode_create_dp_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_dp_colorspace_property() has 2 args]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS], [ + AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d125a93fa0fc5..c241fca8b6963 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -89,6 +89,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ee8d72d7a4d72..9e95e282f458a 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -25,6 +25,7 @@ #include #include #include +#include /* * commit v4.9-rc4-949-g949f08862d66 @@ -108,6 +109,29 @@ int drm_connector_set_panel_orientation_with_quirk( } #endif +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector); +#define drm_connector_attach_colorspace_property _kcl_drm_connector_attach_colorspace_property +#endif /* HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +#define KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces); +#define drm_mode_create_hdmi_colorspace_property _kcl_drm_mode_create_hdmi_colorspace_property +#endif /* HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS */ + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +#define KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces); +#define drm_mode_create_dp_colorspace_property _kcl_drm_mode_create_dp_colorspace_property +#endif /* HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS */ + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +#define DRM_MODE_COLORIMETRY_COUNT 16 +#endif + #ifndef DRM_COLOR_FORMAT_YCBCR444 #define DRM_COLOR_FORMAT_YCBCR444 (1<<1) #endif @@ -120,4 +144,30 @@ int drm_connector_set_panel_orientation_with_quirk( #define DRM_COLOR_FORMAT_YCBCR420 (1<<3) #endif +/* For Default case, driver will set the colorspace */ +#ifndef DRM_MODE_COLORIMETRY_DEFAULT +/* For Default case, driver will set the colorspace */ +#define DRM_MODE_COLORIMETRY_DEFAULT 0 +/* CEA 861 Normal Colorimetry options */ +#define DRM_MODE_COLORIMETRY_NO_DATA 0 +#define DRM_MODE_COLORIMETRY_SMPTE_170M_YCC 1 +#define DRM_MODE_COLORIMETRY_BT709_YCC 2 +/* CEA 861 Extended Colorimetry Options */ +#define DRM_MODE_COLORIMETRY_XVYCC_601 3 +#define DRM_MODE_COLORIMETRY_XVYCC_709 4 +#define DRM_MODE_COLORIMETRY_SYCC_601 5 +#define DRM_MODE_COLORIMETRY_OPYCC_601 6 +#define DRM_MODE_COLORIMETRY_OPRGB 7 +#define DRM_MODE_COLORIMETRY_BT2020_CYCC 8 +#define DRM_MODE_COLORIMETRY_BT2020_RGB 9 +#define DRM_MODE_COLORIMETRY_BT2020_YCC 10 +/* Additional Colorimetry extension added as part of CTA 861.G */ +#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 11 +#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER 12 +/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */ +#define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED 13 +#define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT 14 +#define DRM_MODE_COLORIMETRY_BT601_YCC 15 +#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 70a99033dfe206a13c4f08bc7fb92622d2b2b88b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 Jun 2023 15:44:45 +0800 Subject: [PATCH 1089/2070] drm/amdkcl: fix non-upsteam code for amdgpu_vmid_alloc/free_reserved() It's caused by b43f292541814d06ee154d16cd0eae0d80a81ab6 "drm/amdgpu: add option params to enforce process isolation between graphics and compute" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 82c270b3a6946..0d1007d6f146b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,9 +58,12 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { + r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); if (r) return r; + vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; + } /* init spm vmid with 0x0 */ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); @@ -85,7 +88,10 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { + amdgpu_vmid_free_reserved(adev,AMDGPU_GFXHUB(0)); + vm->reserved_vmid[AMDGPU_GFXHUB(0)] = false; + } /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From 11e4e31756b9371b9ed5f22810a4adf1c0c5223a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Jun 2023 19:21:19 +0800 Subject: [PATCH 1090/2070] Revert "Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM" This reverts commit a56a0c9058b69133897ad4b54c1e76b2efc8fe5b. This patch causes a jira issue: SWDEV-405451 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 8ad49c0a28a83..e5e77df7903d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -153,7 +153,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); - else + else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) places[c].flags |= TTM_PL_FLAG_TOPDOWN; if (abo->tbo.type == ttm_bo_type_kernel && From 024394b2919d19e33921384b0ef0fa83ab3a7f25 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 19 Jun 2023 12:25:00 +0800 Subject: [PATCH 1091/2070] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 93ca881fcda746abc14b5c5794b456d4a9977977 "drm/amdgpu: Add vbios attribute only if supported" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 0ab3f4e9bfe8c..00de8677cf278 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1854,7 +1854,6 @@ const struct attribute_group amdgpu_vbios_version_attr_group = { .attrs = amdgpu_vbios_version_attrs, .is_visible = amdgpu_vbios_version_attrs_is_visible, }; -#endif int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) { @@ -1864,6 +1863,7 @@ int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) return 0; } +#endif /** * amdgpu_atombios_fini - free the driver info and callbacks for atombios diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 867bc5c5ce67d..ae32b280273aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -215,6 +215,8 @@ int amdgpu_atombios_get_data_table(struct amdgpu_device *adev, void amdgpu_atombios_fini(struct amdgpu_device *adev); int amdgpu_atombios_init(struct amdgpu_device *adev); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b366f4aa5c6d2..17b53b9fe6f82 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4312,11 +4312,12 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) { int r; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = amdgpu_atombios_sysfs_init(adev); if (r) drm_err(&adev->ddev, "registering atombios sysfs failed (%d).\n", r); - +#endif r = amdgpu_pm_sysfs_init(adev); if (r) dev_err(adev->dev, "registering pm sysfs failed (%d).\n", r); From eb10f8cb84a6dea0e636dafbdc87b95892ebf7ba Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 19 Jun 2023 13:25:52 +0800 Subject: [PATCH 1092/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE It's caused by 4d291ee797a2d278d1af143e9d94b4deaecb930e "drm/amd/display: Add MST Preferred Link Setting Entry" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index c3b74ce245b5b..7518f711161e4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -345,6 +345,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, return size; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) { bool is_end_device = false; @@ -491,7 +492,7 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, kfree(wr_buf); return size; } - +#endif /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * @@ -3094,12 +3095,13 @@ static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { .write = dp_dsc_passthrough_set, .llseek = default_llseek }; - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static const struct file_operations dp_mst_link_settings_debugfs_fops = { .owner = THIS_MODULE, .write = dp_mst_link_setting, .llseek = default_llseek }; +#endif static const struct { char *name; @@ -3129,7 +3131,9 @@ static const struct { #endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} +#endif }; static const struct { From 5b7ccb50d095c1f011f0a3a9645c3db49b90deaa Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 17 Apr 2023 18:52:54 -0400 Subject: [PATCH 1093/2070] drm/ttm: Update TTM memory limit for GFX9.4.3 APU This patch sets the TTM memory limit to be 3/4th of system memory for GFX 9.4.3 APU. This patch is only intended for DKMS branch. Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling --- drivers/gpu/drm/ttm/ttm_device.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 4c4e167955729..1c8f3049b2b38 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -80,6 +80,9 @@ static int ttm_global_init(void) { struct ttm_global *glob = &ttm_glob; unsigned long num_pages, num_dma32; +#if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); +#endif struct sysinfo si; int ret = 0; @@ -98,7 +101,17 @@ static int ttm_global_init(void) * system memory. */ num_pages = ((u64)si.totalram * si.mem_unit) >> PAGE_SHIFT; +#if IS_ENABLED(CONFIG_X86) + /* For GFX 9.4.3 APU, set mem limit to be 3/4th of + * system memory. + */ + if (c->x86 == 0x19 && c->x86_model == 0x90) + num_pages = (num_pages * 3) / 4; + else + num_pages /= 2; +#else num_pages /= 2; +#endif /* But for DMA32 we limit ourself to only use 2GiB maximum. */ num_dma32 = (u64)(si.totalram - si.totalhigh) * si.mem_unit From faf4465ad48f010f05ac3014b75e097eabe30f3f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 16 Jun 2023 10:48:18 +0800 Subject: [PATCH 1094/2070] drm/amdkcl: test whether drm_connector_state->colorspace is available It's caused by 95f27fa77de8dbc1e277af8dbb7d6f8640f650d1 "drm/amd/display: Send correct DP colorspace infopacket" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_connector_state.m4 | 21 +++++++++ 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f71985dbec4f6..f7973ef56b8d8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6530,6 +6530,7 @@ get_aspect_ratio(const struct drm_display_mode *mode_in) return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; } +#ifdef HAVE_DRM_CONNECTOR_STATE_COLORSPACE static enum dc_color_space get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, const struct drm_connector_state *connector_state) @@ -6588,6 +6589,51 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, return color_space; } +#else +static enum dc_color_space +get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, + const struct drm_connector_state *connector_state) +{ + enum dc_color_space color_space = COLOR_SPACE_SRGB; + + switch (dc_crtc_timing->pixel_encoding) { + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR444: + case PIXEL_ENCODING_YCBCR420: + { + /* + * 27030khz is the separation point between HDTV and SDTV + * according to HDMI spec, we use YCbCr709 and YCbCr601 + * respectively + */ + if (dc_crtc_timing->pix_clk_100hz > 270300) { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR709_LIMITED; + else + color_space = COLOR_SPACE_YCBCR709; + } else { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR601_LIMITED; + else + color_space = COLOR_SPACE_YCBCR601; + } + + } + break; + case PIXEL_ENCODING_RGB: + color_space = COLOR_SPACE_SRGB; + break; + + default: + WARN_ON(1); + break; + } + + return color_space; +} +#endif static enum display_content_type get_output_content_type(const struct drm_connector_state *connector_state) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7f5a149600343..df889760e5d24 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -496,6 +496,9 @@ /* drm_mode_create_dp_colorspace_property() has 2 args */ #define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c241fca8b6963..3745e9d5f5c17 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,6 +90,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 new file mode 100644 index 0000000000000..845426d6fe7bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v5.0-rc7-1020-gd2c6a405846c +dnl # drm: Add HDMI colorspace property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [drm_connector_state->colorspace is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE], [ + AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE +]) \ No newline at end of file From f45dfddff36f09c0394f4355d0c79c472c43f794 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 20 Jun 2023 14:42:14 +0800 Subject: [PATCH 1095/2070] drm/amdkcl: Optimize the vma init function Rename the vma init funciton and initialize the vma manager only if the vam space less than 16T Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- .../kcl/backport/kcl_drm_vma_manager_backport.h | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ef25c434576c4..250f082dd623a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2450,7 +2450,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); - kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); + /* Check and increase the vma range */ + kcl_drm_vma_offset_manager_adjust(ddev->vma_offset_manager); if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h index 9893688f6fac2..b7b16df2f6d2c 100644 --- a/include/kcl/backport/kcl_drm_vma_manager_backport.h +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -42,16 +42,25 @@ #define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFULL >> PAGE_SHIFT) * 4096) static inline void -kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +kcl_drm_vma_offset_manager_adjust(struct drm_vma_offset_manager *mgr) { - drm_vma_offset_manager_destroy(mgr); + u64 size; + + BUG_ON(!mgr); + + size = mgr->vm_addr_space_mm.head_node.hole_size; + if (size < DRM_FILE_PAGE_OFFSET_SIZE) + drm_vma_offset_manager_destroy(mgr); + else + return; + drm_vma_offset_manager_init(mgr, DRM_FILE_PAGE_OFFSET_START, DRM_FILE_PAGE_OFFSET_SIZE); } #else static inline void -kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +kcl_drm_vma_offset_manager_adjust(struct drm_vma_offset_manager *mgr) { } #endif From acd231250e961fb8bc73aa9bea09e49657cebcdb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 16:22:47 +0800 Subject: [PATCH 1096/2070] drm/amdkcl: fake suballoc* It's caused by 849ee8a2f0df7a4ed4d281e19d3c9824b8e60bc2 drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c | 461 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 + drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 17 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_suballoc.h | 10 + include/kcl/kcl_drm_suballoc.h | 113 +++++ 9 files changed, 610 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 create mode 100644 include/kcl/header/drm/drm_suballoc.h create mode 100644 include/kcl/kcl_drm_suballoc.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 33cbe6ba3bf43..e5ca4419fb44d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o + kcl_irqdesc.o kcl_drm_suballoc.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c new file mode 100644 index 0000000000000..8ad6e3d9b60eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2011 Red Hat Inc. + * Copyright 2023 Intel Corporation. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* Algorithm: + * + * We store the last allocated bo in "hole", we always try to allocate + * after the last allocated bo. Principle is that in a linear GPU ring + * progression was is after last is the oldest bo we allocated and thus + * the first one that should no longer be in use by the GPU. + * + * If it's not the case we skip over the bo after last to the closest + * done bo if such one exist. If none exist and we are not asked to + * block we report failure to allocate. + * + * If we are asked to block we wait on all the oldest fence of all + * rings. We just wait for any of those fence to complete. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +static void drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); + +/** + * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate + * @align: alignment for each suballocated chunk + * + * Prepares the suballocation manager for suballocations. + */ +void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + unsigned int i; + + BUILD_BUG_ON(!is_power_of_2(DRM_SUBALLOC_MAX_QUEUES)); + + if (!align) + align = 1; + + /* alignment must be a power of 2 */ + if (WARN_ON_ONCE(align & (align - 1))) + align = roundup_pow_of_two(align); + + init_waitqueue_head(&sa_manager->wq); + sa_manager->size = size; + sa_manager->align = align; + sa_manager->hole = &sa_manager->olist; + INIT_LIST_HEAD(&sa_manager->olist); + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + INIT_LIST_HEAD(&sa_manager->flist[i]); +} +EXPORT_SYMBOL(drm_suballoc_manager_init); + +/** + * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * + * Cleans up the suballocation manager after use. All fences added + * with drm_suballoc_free() must be signaled, or we cannot clean up + * the entire manager. + */ +void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (!sa_manager->size) + return; + + if (!list_empty(&sa_manager->olist)) { + sa_manager->hole = &sa_manager->olist; + drm_suballoc_try_free(sa_manager); + if (!list_empty(&sa_manager->olist)) + DRM_ERROR("sa_manager is not empty, clearing anyway\n"); + } + list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { + drm_suballoc_remove_locked(sa); + } + + sa_manager->size = 0; +} +EXPORT_SYMBOL(drm_suballoc_manager_fini); + +static void drm_suballoc_remove_locked(struct drm_suballoc *sa) +{ + struct drm_suballoc_manager *sa_manager = sa->manager; + + if (sa_manager->hole == &sa->olist) + sa_manager->hole = sa->olist.prev; + + list_del_init(&sa->olist); + list_del_init(&sa->flist); + dma_fence_put(sa->fence); + kfree(sa); +} + +static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (sa_manager->hole->next == &sa_manager->olist) + return; + + sa = list_entry(sa_manager->hole->next, struct drm_suballoc, olist); + list_for_each_entry_safe_from(sa, tmp, &sa_manager->olist, olist) { + if (!sa->fence || !dma_fence_is_signaled(sa->fence)) + return; + + drm_suballoc_remove_locked(sa); + } +} + +static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole != &sa_manager->olist) + return list_entry(hole, struct drm_suballoc, olist)->eoffset; + + return 0; +} + +static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole->next != &sa_manager->olist) + return list_entry(hole->next, struct drm_suballoc, olist)->soffset; + return sa_manager->size; +} + +static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, + struct drm_suballoc *sa, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + + soffset = drm_suballoc_hole_soffset(sa_manager); + eoffset = drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + if ((eoffset - soffset) >= (size + wasted)) { + soffset += wasted; + + sa->manager = sa_manager; + sa->soffset = soffset; + sa->eoffset = soffset + size; + list_add(&sa->olist, sa_manager->hole); + INIT_LIST_HEAD(&sa->flist); + sa_manager->hole = &sa->olist; + return true; + } + return false; +} + +static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + unsigned int i; + + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (!list_empty(&sa_manager->flist[i])) + return true; + + soffset = drm_suballoc_hole_soffset(sa_manager); + eoffset = drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + return ((eoffset - soffset) >= (size + wasted)); +} + +/** + * drm_suballoc_event() - Check if we can stop waiting + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to allocate + * @align: alignment we need to match + * + * Return: true if either there is a fence we can wait for or + * enough free memory to satisfy the allocation directly. + * false otherwise. + */ +static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + bool ret; + + spin_lock(&sa_manager->wq.lock); + ret = __drm_suballoc_event(sa_manager, size, align); + spin_unlock(&sa_manager->wq.lock); + return ret; +} + +static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, + struct dma_fence **fences, + unsigned int *tries) +{ + struct drm_suballoc *best_bo = NULL; + unsigned int i, best_idx; + size_t soffset, best, tmp; + + /* if hole points to the end of the buffer */ + if (sa_manager->hole->next == &sa_manager->olist) { + /* try again with its beginning */ + sa_manager->hole = &sa_manager->olist; + return true; + } + + soffset = drm_suballoc_hole_soffset(sa_manager); + /* to handle wrap around we add sa_manager->size */ + best = sa_manager->size * 2; + /* go over all fence list and try to find the closest sa + * of the current last + */ + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) { + struct drm_suballoc *sa; + + fences[i] = NULL; + + if (list_empty(&sa_manager->flist[i])) + continue; + + sa = list_first_entry(&sa_manager->flist[i], + struct drm_suballoc, flist); + + if (!dma_fence_is_signaled(sa->fence)) { + fences[i] = sa->fence; + continue; + } + + /* limit the number of tries each freelist gets */ + if (tries[i] > 2) + continue; + + tmp = sa->soffset; + if (tmp < soffset) { + /* wrap around, pretend it's after */ + tmp += sa_manager->size; + } + tmp -= soffset; + if (tmp < best) { + /* this sa bo is the closest one */ + best = tmp; + best_idx = i; + best_bo = sa; + } + } + + if (best_bo) { + ++tries[best_idx]; + sa_manager->hole = best_bo->olist.prev; + + /* + * We know that this one is signaled, + * so it's safe to remove it. + */ + drm_suballoc_remove_locked(best_bo); + return true; + } + return false; +} + +/** + * drm_suballoc_new() - Make a suballocation. + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate. + * @gfp: gfp flags used for memory allocation. Typically GFP_KERNEL but + * the argument is provided for suballocations from reclaim context or + * where the caller wants to avoid pipelining rather than wait for + * reclaim. + * @intr: Whether to perform waits interruptible. This should typically + * always be true, unless the caller needs to propagate a + * non-interruptible context from above layers. + * @align: Alignment. Must not exceed the default manager alignment. + * If @align is zero, then the manager alignment is used. + * + * Try to make a suballocation of size @size, which will be rounded + * up to the alignment specified in specified in drm_suballoc_manager_init(). + * + * Return: a new suballocated bo, or an ERR_PTR. + */ +struct drm_suballoc * +drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align) +{ + struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int tries[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int count; + int i, r; + struct drm_suballoc *sa; + + if (WARN_ON_ONCE(align > sa_manager->align)) + return ERR_PTR(-EINVAL); + if (WARN_ON_ONCE(size > sa_manager->size || !size)) + return ERR_PTR(-EINVAL); + + if (!align) + align = sa_manager->align; + + sa = kmalloc(sizeof(*sa), gfp); + if (!sa) + return ERR_PTR(-ENOMEM); + sa->manager = sa_manager; + sa->fence = NULL; + INIT_LIST_HEAD(&sa->olist); + INIT_LIST_HEAD(&sa->flist); + + spin_lock(&sa_manager->wq.lock); + do { + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + tries[i] = 0; + + do { + drm_suballoc_try_free(sa_manager); + + if (drm_suballoc_try_alloc(sa_manager, sa, + size, align)) { + spin_unlock(&sa_manager->wq.lock); + return sa; + } + + /* see if we can skip over some allocations */ + } while (drm_suballoc_next_hole(sa_manager, fences, tries)); + + for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (fences[i]) + fences[count++] = dma_fence_get(fences[i]); + + if (count) { + long t; + + spin_unlock(&sa_manager->wq.lock); + t = dma_fence_wait_any_timeout(fences, count, intr, + MAX_SCHEDULE_TIMEOUT, + NULL); + for (i = 0; i < count; ++i) + dma_fence_put(fences[i]); + + r = (t > 0) ? 0 : t; + spin_lock(&sa_manager->wq.lock); + } else if (intr) { + /* if we have nothing to wait for block */ + r = wait_event_interruptible_locked + (sa_manager->wq, + __drm_suballoc_event(sa_manager, size, align)); + } else { + spin_unlock(&sa_manager->wq.lock); + wait_event(sa_manager->wq, + drm_suballoc_event(sa_manager, size, align)); + r = 0; + spin_lock(&sa_manager->wq.lock); + } + } while (!r); + + spin_unlock(&sa_manager->wq.lock); + kfree(sa); + return ERR_PTR(r); +} +EXPORT_SYMBOL(drm_suballoc_new); + +/** + * drm_suballoc_free - Free a suballocation + * @suballoc: pointer to the suballocation + * @fence: fence that signals when suballocation is idle + * + * Free the suballocation. The suballocation can be re-used after @fence signals. + */ +void drm_suballoc_free(struct drm_suballoc *suballoc, + struct dma_fence *fence) +{ + struct drm_suballoc_manager *sa_manager; + + if (!suballoc) + return; + + sa_manager = suballoc->manager; + + spin_lock(&sa_manager->wq.lock); + if (fence && !dma_fence_is_signaled(fence)) { + u32 idx; + + suballoc->fence = dma_fence_get(fence); + idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); + list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); + } else { + drm_suballoc_remove_locked(suballoc); + } + wake_up_all_locked(&sa_manager->wq); + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(drm_suballoc_free); + +#ifdef CONFIG_DEBUG_FS +void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ + struct drm_suballoc *i; + + spin_lock(&sa_manager->wq.lock); + list_for_each_entry(i, &sa_manager->olist, olist) { + unsigned long long soffset = i->soffset; + unsigned long long eoffset = i->eoffset; + + if (&i->olist == sa_manager->hole) + drm_puts(p, ">"); + else + drm_puts(p, " "); + + drm_printf(p, "[0x%010llx 0x%010llx] size %8lld", + suballoc_base + soffset, suballoc_base + eoffset, + eoffset - soffset); + + if (i->fence) + drm_printf(p, " protected by 0x%016llx on context %llu", + (unsigned long long)i->fence->seqno, + (unsigned long long)i->fence->context); + + drm_puts(p, "\n"); + } + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(drm_suballoc_dump_debug_info); +#endif +MODULE_AUTHOR("Multiple"); +MODULE_DESCRIPTION("Range suballocator helper"); +MODULE_LICENSE("Dual MIT/GPL"); +#endif /*HAVE_DRM_SUBALLOC_MANAGER_INIT*/ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2e14714c2a662..4b5358ee17afd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -105,4 +105,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index b67bfda700d77..5abb5cf97824c 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -32,6 +32,7 @@ #include #include +#include #include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index a88e31ef833a7..642993ebcc9cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -87,4 +87,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + dnl # + dnl # v6.2-rc6-1265-g849ee8a2f0df + dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 new file mode 100644 index 0000000000000..bcb026ad2c36d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.2-rc6-1265-g849ee8a2f0df +dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_suballoc_manager_init(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_SUBALLOC_MANAGER_INIT, 1, + [Has function drm_suballoc_manager_init()]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3745e9d5f5c17..6bb506b471745 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -179,6 +179,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_APPLE_GMUX_DETECT AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT + AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/drm_suballoc.h b/include/kcl/header/drm/drm_suballoc.h new file mode 100644 index 0000000000000..3eca4a8774ac4 --- /dev/null +++ b/include/kcl/header/drm/drm_suballoc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_SUBALLOC_H_H_ +#define _KCL_HEADER_DRM_SUBALLOC_H_H_ + +#ifdef HAVE_DRM_DRM_SUBALLOC_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h new file mode 100644 index 0000000000000..46c61883e392f --- /dev/null +++ b/include/kcl/kcl_drm_suballoc.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2011 Red Hat Inc. + * Copyright © 2022 Intel Corporation + */ +#ifndef _KCL_DRM_SUBALLOC_H_ +#define _KCL_DRM_SUBALLOC_H_ + +#include + +#ifndef HAVE_DRM_DRM_SUBALLOC_H + +#include + +#include +#include + +#define DRM_SUBALLOC_MAX_QUEUES 32 +/** + * struct drm_suballoc_manager - fenced range allocations + * @wq: Wait queue for sleeping allocations on contention. + * @hole: Pointer to first hole node. + * @olist: List of allocated ranges. + * @flist: Array[fence context hash] of queues of fenced allocated ranges. + * @size: Size of the managed range. + * @align: Default alignment for the managed range. + */ +struct drm_suballoc_manager { + wait_queue_head_t wq; + struct list_head *hole; + struct list_head olist; + struct list_head flist[DRM_SUBALLOC_MAX_QUEUES]; + size_t size; + size_t align; +}; + +/** + * struct drm_suballoc - Sub-allocated range + * @olist: List link for list of allocated ranges. + * @flist: List linkk for the manager fenced allocated ranges queues. + * @manager: The drm_suballoc_manager. + * @soffset: Start offset. + * @eoffset: End offset + 1 so that @eoffset - @soffset = size. + * @dma_fence: The fence protecting the allocation. + */ +struct drm_suballoc { + struct list_head olist; + struct list_head flist; + struct drm_suballoc_manager *manager; + size_t soffset; + size_t eoffset; + struct dma_fence *fence; +}; + +void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align); + +void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); + +struct drm_suballoc * +drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align); + +void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); + +/** + * drm_suballoc_soffset - Range start. + * @sa: The struct drm_suballoc. + * + * Return: The start of the allocated range. + */ +static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) +{ + return sa->soffset; +} + +/** + * drm_suballoc_eoffset - Range end. + * @sa: The struct drm_suballoc. + * + * Return: The end of the allocated range + 1. + */ +static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) +{ + return sa->eoffset; +} + +/** + * drm_suballoc_size - Range size. + * @sa: The struct drm_suballoc. + * + * Return: The size of the allocated range. + */ +static inline size_t drm_suballoc_size(struct drm_suballoc *sa) +{ + return sa->eoffset - sa->soffset; +} + +#ifdef CONFIG_DEBUG_FS +void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base); +#else +static inline void +drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ } + +#endif +#endif /*HAVE_DRM_DRM_SUBALLOC_H*/ + +#endif /* _KCL_DRM_SUBALLOC_H_ */ From 83ec3a1a2987b05d243bbc31c734343511c7a3b9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 17:32:49 +0800 Subject: [PATCH 1097/2070] drm/amdkcl: drop include path include/kcl/header/uapi in dkms Makefile The file include/kcl/header/uapi has been clean up, so remove it from include path of dkms package. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 39facc822b351..a73a7f7227df2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -161,7 +161,6 @@ LINUXINCLUDE := \ -include $(src)/amd/dkms/config/config.h \ $(LINUX_SRCTREE_INCLUDE) \ -I$(src)/include/uapi \ - -I$(src)/include/kcl/header/uapi \ $(USER_INCLUDE) export CONFIG_HSA_AMD=y From 40b59625ea8eb1878d3fd92b4b67069395b9f759 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 18:14:23 +0800 Subject: [PATCH 1098/2070] drm/amdkcl: fake vm_flags_{set, clear} It's caused by v6.2-rc4-446-gbc292ab00f6c mm: introduce vma->vm_flags wrapper functions Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ .../amd/dkms/m4/mmap_assert_write_locked.m4 | 17 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 18 +++++++++++++++++ include/kcl/kcl_mm.h | 20 +++++++++++++++++++ 4 files changed, 57 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6bb506b471745..94183e717dbd6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -180,6 +180,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT + AC_AMDGPU_VM_FLAGS_SET + AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 new file mode 100644 index 0000000000000..f38fdf7f5d53c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.7-13157-g42fc541404f2 +dnl # mmap locking API: add mmap_assert_locked() and mmap_assert_write_locked() +dnl # +AC_DEFUN([AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmap_assert_write_locked(NULL); + ], [ + AC_DEFINE(HAVE_MMAP_ASSERT_WRITE_LOCKED, 1, + [mmap_assert_write_locked() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 index 1eb0129ff303c..74cd3b8edd7ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -14,3 +14,21 @@ AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ ]) ]) ]) + +dnl # +dnl # v6.2-rc4-446-gbc292ab00f6c +dnl # mm: introduce vma->vm_flags wrapper functions +dnl # +AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vm_flags_set(NULL, 0); + vm_flags_clear(NULL, 0); + ], [ + AC_DEFINE(HAVE_VM_FLAGS_SET, 1, + [vm_flags_{set, clear} is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index e38dec08515b1..2cb594bcf196f 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -89,4 +89,24 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) #define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) #endif +#ifndef HAVE_VM_FLAGS_SET +static inline void vm_flags_set(struct vm_area_struct *vma, + vm_flags_t flags) +{ +#ifdef HAVE_MMAP_ASSERT_WRITE_LOCKED + mmap_assert_write_locked(vma->vm_mm); +#endif + vma->vm_flags |= flags; +} + +static inline void vm_flags_clear(struct vm_area_struct *vma, + vm_flags_t flags) +{ +#ifdef HAVE_MMAP_ASSERT_WRITE_LOCKED + mmap_assert_write_locked(vma->vm_mm); +#endif + vma->vm_flags &= ~flags; +} +#endif + #endif /* AMDKCL_MM_H */ From 26fa8b296be87744d9251faabc21b254f914c4c7 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 12 Jun 2023 12:05:28 -0400 Subject: [PATCH 1099/2070] drm/amdkfd: remove old debugger Remove the old debugger to make way for the upstreamed debugger. Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +++++++++++ include/uapi/linux/kfd_ioctl.h | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 4cb64c36832dd..314d96a278e6c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1767,6 +1767,14 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated DBG API */ +static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, + struct kfd_process *p, void *data) +{ + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; +} + /* Place holder for deprecated CMA API */ static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, struct kfd_process *local_p, void *data) { @@ -3550,6 +3558,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 2eb3e7df52820..b8c0f996ee00e 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -254,7 +254,7 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff -struct kfd_ioctl_dbg_trap_args { +struct kfd_ioctl_dbg_trap_args_deprecated { __u64 exception_mask; /* to KFD */ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ @@ -1809,6 +1809,8 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) +#define AMDKFD_IOC_DBG_TRAP_DEPRECATED \ + AMDKFD_IOWR(0x82, struct kfd_ioctl_dbg_trap_args_deprecated) #define AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED \ AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_deprecated_args) From ed9beed5ff68fa9f3768e08fb312aa6692c8dba4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 18 Jul 2023 15:32:09 +0800 Subject: [PATCH 1100/2070] drm/amdkcl: test whether drm_dp_mst_hpd_irq_handle_event() is available It's caused by 55970ce5015265eb0985f518995aa8fc4b3fa384 "drm/dp_mst: Clear MSG_RDY flag before sending new message" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ .../m4/drm_dp_mst_hpd_irq_handle_event.m4 | 16 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 47 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 07ab7fb87c0c4..0676d3a54ea3c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -845,6 +845,7 @@ void dm_handle_mst_sideband_msg_ready_event( /* handle MST irq */ if (aconnector->mst_mgr.mst_state) +#ifdef HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, esi, ack, @@ -868,6 +869,29 @@ void dm_handle_mst_sideband_msg_ready_event( } drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); +#else + drm_dp_mst_hpd_irq( + &aconnector->mst_mgr, + esi, + &new_irq_handled); + + if (new_irq_handled) { + /* ACK at DPCD to notify down stream */ + const int ack_dpcd_bytes_to_write = + dpcd_bytes_to_read - 1; + + for (retry = 0; retry < 3; retry++) { + u8 wret; + + wret = drm_dp_dpcd_write( + &aconnector->dm_dp_aux.aux, + dpcd_addr + 1, + &esi[1], + ack_dpcd_bytes_to_write); + if (wret == ack_dpcd_bytes_to_write) + break; + } +#endif new_irq_handled = false; } else { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index df889760e5d24..2090d43c71eb8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -367,6 +367,12 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* drm_dp_mst_hpd_irq_handle_event() is available */ +#define HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT 1 + +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 new file mode 100644 index 0000000000000..a70fd97681104 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-4472-g55970ce50152 +dnl # drm/dp_mst: Clear MSG_RDY flag before sending new message +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_hpd_irq_handle_event(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT, 1, + [drm_dp_mst_hpd_irq_handle_event() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 94183e717dbd6..ccb25ec8cdb47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -136,6 +136,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD + AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG From ae5bde86b2a9df2a39b4a6dac1f4694fa6ab066b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 18 Jul 2023 16:55:33 +0800 Subject: [PATCH 1101/2070] drm/amdkcl: test whether drm_dp_mst_topology_cbs->poll_hpd_irq is available It's caused by ed8496801ab71fdfb9c9fdcbef058aa20a549ebd "drm/amd/display: Add polling method to handle MST reply packet" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 23 +++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 0676d3a54ea3c..2703866a69a09 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -905,10 +905,12 @@ void dm_handle_mst_sideband_msg_ready_event( DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) { dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#endif #ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, @@ -969,7 +971,9 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { #ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR .register_connector = dm_dp_mst_register_connector #endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, +#endif }; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2090d43c71eb8..eb6a0d1f48702 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -388,6 +388,9 @@ /* struct drm_dp_mst_topology_cbs has hotplug member */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ +/* struct drm_dp_mst_topology_cbs->poll_hpd_irq is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ 1 + /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 683d563cfc7bb..02dac4390e913 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -68,10 +68,33 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ ]) ]) +dnl # +dnl # commit v5.7-rc1-646-g471bdd0df0d5 +dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->poll_hpd_irq(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ, 1, + [struct drm_dp_mst_topology_cbs->poll_hpd_irq is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ ]) ]) From 0fce6ff978ef1184b38367e28e7311f4e8c51f7e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 21 Jul 2023 14:13:55 +0800 Subject: [PATCH 1102/2070] drm/amdkcl: check PIDTYPE_PID whether exits It's caused by 6883f81aac6f44e7df70a6af189b3689ff52cbfb pid: Implement PIDTYPE_TGID Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 ++++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pid_type.m4 | 17 +++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pid_type.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 8d6d8beac461d..39787e620297d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1461,7 +1461,12 @@ static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) */ rcu_read_lock(); pid = rcu_dereference(file->pid); - task = pid_task(pid, PIDTYPE_TGID); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PID); +#endif seq_printf(m, "pid %8d command %s:\n", pid_nr(pid), task ? task->comm : ""); rcu_read_unlock(); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ccb25ec8cdb47..91e27f969a474 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -183,6 +183,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_PID_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 new file mode 100644 index 0000000000000..da986da3833f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.18-rc1-6-g6883f81aac6f +dnl # pid: Implement PIDTYPE_TGID +dnl # +AC_DEFUN([AC_AMDGPU_PID_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum pid_type a; + a = PIDTYPE_TGID; + ], [ + AC_DEFINE(HAVE_PIDTYPE_TGID, 1, + [PIDTYPE is availablea]) + ]) + ]) +]) From ba2fcd155b48246606efcf0d44f6740b76d82cf2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Jul 2023 14:40:22 +0800 Subject: [PATCH 1103/2070] drm/amdkcl: Test struct dma_fence_ops whether has set_deadline It's caused by v6.3-rc2-1-gaec11c8d7cb3 dma-buf/dma-fence: Add deadline awareness Signed-off-by: Asher Song --- drivers/dma-buf/dma-resv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/sched_fence.c | 11 +++++++++- 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index bea3e9858aca5..2e78a095eaaf6 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -708,6 +708,7 @@ EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); * May be called without holding the dma_resv lock. Sets @deadline on * all fences filtered by @usage. */ +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, ktime_t deadline) { @@ -721,6 +722,7 @@ void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, dma_resv_iter_end(&cursor); } EXPORT_SYMBOL_GPL(dma_resv_set_deadline); +#endif /** * dma_resv_test_signaled - Test if a reservation object's fences have been diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 index c10c92dfb503e..5fd3aeec58e80 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -15,3 +15,24 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ ]) ]) ]) + + +dnl # +dnl # v6.3-rc2-1-gaec11c8d7cb3 +dnl # dma-buf/dma-fence: Add deadline awareness +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t deadline = 0; + struct dma_fence_ops *ops = NULL; + ops->set_deadline(NULL, deadline); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_SET_DEADLINE, 1, + [struct dma_fence_ops has callback set_deadline]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 91e27f969a474..c777c2da916ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -184,6 +184,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index acd4eaab1fd03..5cba4c3477a18 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -48,6 +48,7 @@ static void __exit drm_sched_fence_slab_fini(void) kmem_cache_destroy(sched_fence_slab); } +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE static void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, struct dma_fence *fence) { @@ -61,6 +62,7 @@ static void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, &s_fence->finished.flags)) dma_fence_set_deadline(fence, s_fence->deadline); } +#endif void drm_sched_fence_scheduled(struct drm_sched_fence *fence, struct dma_fence *parent) @@ -72,8 +74,11 @@ void drm_sched_fence_scheduled(struct drm_sched_fence *fence, * up. */ if (!IS_ERR_OR_NULL(parent)) +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE drm_sched_fence_set_parent(fence, parent); - +#else + fence->parent = dma_fence_get(parent); +#endif dma_fence_signal(&fence->scheduled); } @@ -149,6 +154,7 @@ static void drm_sched_fence_release_finished(struct dma_fence *f) dma_fence_put(&fence->scheduled); } +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, ktime_t deadline) { @@ -179,6 +185,7 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, if (parent) dma_fence_set_deadline(parent, deadline); } +#endif static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, @@ -194,7 +201,9 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, +#endif }; struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f) From d05458e57eccfe8ccbb1f5397dde7c2bb68cb316 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 26 Jul 2023 13:38:15 +0800 Subject: [PATCH 1104/2070] drm/amdkcl: use vm_flags function to set vm_flags It's caused by bc292ab00f6c7a661a8a605c714e8a148f629ef6 "mm: introduce vma->vm_flags wrapper functions" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c index 359099cb8af9e..84ffb99293e93 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -70,7 +70,7 @@ static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_s goto err_drm_gem_object_put; } - vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); } From 7c60923e76edda7a0674d54d040fde341faae4d6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 27 Jul 2023 01:05:14 +0800 Subject: [PATCH 1105/2070] drm/amdkfd: fix a build issue fix the following compile error: 2023-07-26T03:35:53.838Z] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.c:194:6: error: no previous prototype for 'kfd_doorbell_unmap_locked' [-Werror=missing-prototypes] [2023-07-26T03:35:53.838Z] void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) [2023-07-26T03:35:53.838Z] ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 3368779e354af..99e0d445ff2d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -156,7 +156,7 @@ static const struct vm_operations_struct kfd_doorbell_vm_ops = { .fault = kfd_doorbell_vm_fault, }; -void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +static void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) { struct kfd_process *process = pdd->process; struct vm_area_struct *vma; From b0d485b3b63999c51809cb9cf5c9610d9a2e086d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 28 Jul 2023 15:15:50 +0800 Subject: [PATCH 1106/2070] drm/amdkcl: change the test for HMM support in kernel Because mmu_notifier_range.vma field is removed in kernel 6.3 by commit 7d4a8be0c4b2b7ffb367 (mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export), We should change the test for HMM support. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 72147cbe68a28..72a1a8260873a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -49,6 +49,7 @@ dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h eve dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # 7d4a8be0c4b2 - mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export dnl # AC_DEFUN([AC_AMDGPU_HMM], [ AC_KERNEL_DO_BACKGROUND([ @@ -61,7 +62,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ struct mmu_notifier_range *mmu_range = NULL; range->notifier = NULL; - mmu_range->vma = NULL; + mmu_range->event = 0; #else #error CONFIG_HMM_MIRROR not enabled #endif From c789e5d5da85a4d33fba9760fd3a0e0a81ecbc89 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 1 Sep 2021 17:02:38 -0400 Subject: [PATCH 1107/2070] drm/amdkfd: set conditional trap_en on aldebaran To ensure performance benchmarks remain suitable for non-debugged processes on aldebaran, make the per-vmid SPI debug TRAP_EN bit conditional on the HSA_ENABLE_DEBUG ENV variable for running processes. For single process debug devices, TRAP_EN will always be on but by spec, the KFD should still report the ttmp setup status set by runtime through the ENV variable. The debugger can choose to ignore this status from its own device lookup. Note: some of the functions that refresh the runlist can be cleaned up now that the dispatch index save is no longer toggled in the initialization or updating of the MQD and there will be a follow on set of patches to do this since they are not functional critical at the moment. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index 8058ea91ecafd..fdaa7e72a62cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -772,7 +772,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, for (i = first_vmid; i < last_vmid; i++) { data = 0; soc15_grbm_select(adev, 0, 0, 0, i, 0); - data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); From 83fc446c6f267c71a8038597731b2524cb7023cd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jun 2023 10:21:20 +0800 Subject: [PATCH 1108/2070] drm/amkcl: fake drm_edid_encode_panel_id() It's caused by de1da2f7fe25828288af8ca287a21fb8f0172c3e "drm/amd/display: Add monitor specific edid quirk" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_edid.h | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 include/kcl/kcl_drm_edid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4b5358ee17afd..b4e8aa0270855 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -106,4 +106,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h new file mode 100644 index 0000000000000..dd472225c0477 --- /dev/null +++ b/include/kcl/kcl_drm_edid.h @@ -0,0 +1,14 @@ +#ifndef AMDKCL_DRM_EDID_H +#define AMDKCL_DRM_EDID_H + +#include + +#ifndef drm_edid_encode_panel_id +#define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ + ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ + (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ + (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ + ((product_id) & 0xffff)) +#endif /* drm_edid_encode_panel_id */ + +#endif From cff2867d4c1d431b9bd19754bcbf5eef6d8ecccb Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 28 Jun 2023 17:59:26 -0400 Subject: [PATCH 1109/2070] drm/amdkcl: Some tests fix Fix tests that produce invalid results. AC_KERNEL_TRY_COMPILE_SYMBOL macro requires all possible locations of .c files to search for exported symbols. If file locations either missing or invalid the tests always return 'false'. Change-Id: I717cdfb283c3e7fe81c397d9ef3702b9593e5662 Signed-off-by: Slava Grigorev --- .../gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 2 +- .../drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 5dc461c4db3df..fd42b70c0fd97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -16,7 +16,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; drm_dp_link_train_channel_eq_delay(aux, dpcd); - ], [drm_dp_link_train_channel_eq_delay],[drm/drm_dp_helper.c],[ + ], [drm_dp_link_train_channel_eq_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, [drm_dp_link_train_channel_eq_delay() has 2 args]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 4d0c1a7e21313..dbd7be4543404 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -16,7 +16,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; drm_dp_link_train_clock_recovery_delay(aux, dpcd); - ], [drm_dp_link_train_clock_recovery_delay],[drm/drm_dp_helper.c],[ + ], [drm_dp_link_train_clock_recovery_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, [drm_dp_link_train_clock_recovery_delay() has 2 args]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index 318f729096712..883dc5867886e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -15,7 +15,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); - ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, [drm_dp_mst_atomic_check() is available]) ]) From 3962ab0fa8931dba4aa1ee0b92a79d0a50e914e1 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 29 Jun 2023 12:37:25 -0400 Subject: [PATCH 1110/2070] drm/amdkcl: Add including of a missing header file This fixes the build against older kernels that don't have drm/display/drm_hdcp_helper.h in their source trees. Change-Id: I25338fac38453a8bc7ee8adac9381000d2b4424d Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov --- include/kcl/header/drm/display/drm_hdcp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kcl/header/drm/display/drm_hdcp_helper.h b/include/kcl/header/drm/display/drm_hdcp_helper.h index 047decb7fc695..8805018a9a244 100644 --- a/include/kcl/header/drm/display/drm_hdcp_helper.h +++ b/include/kcl/header/drm/display/drm_hdcp_helper.h @@ -4,6 +4,8 @@ #if defined(HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H) #include_next +#else +#include #endif #endif From 9a2e778b88d1996258a4a02e9a7778ac7baa1626 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 29 Jun 2023 14:45:41 +0800 Subject: [PATCH 1111/2070] drm/amdkcl: fix m4 issue and update config.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 76 ++++++------------- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 2 +- .../m4/drm-hdcp-update-content-protection.m4 | 5 +- 4 files changed, 27 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index eb6a0d1f48702..04b23437bad9e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -10,6 +10,9 @@ /* whether access_ok(x, x) is available */ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 + /* acpi_put_table() is available */ #define HAVE_ACPI_PUT_TABLE 1 @@ -183,6 +186,9 @@ /* drm_connector_attach_hdr_output_metadata_property() is available */ #define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -212,29 +218,17 @@ /* drm_connector_set_panel_orientation_with_quirk() is available */ #define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 -/* drm_connector_unreference() is available */ -/* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ - -/* drm_connector_xxx() drop _mode_ */ -#define HAVE_DRM_CONNECTOR_XXX_DROP_MODE 1 - -/* ddrm_atomic_stat has __drm_crtcs_state */ -/* #undef HAVE_DRM_CRTCS_STATE_MEMBER */ - -/* drm_crtc_accurate_vblank_count() is available */ -#define HAVE_DRM_CRTC_ACCURATE_VBLANK_COUNT 1 - -/* drm_crtc_enable_color_mgmt() is available */ -#define HAVE_DRM_CRTC_ENABLE_COLOR_MGMT 1 - -/* drm_crtc_from_index() is available */ -#define HAVE_DRM_CRTC_FROM_INDEX 1 +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 /* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg */ @@ -319,9 +313,6 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* acpi_dev_get_first_match_dev() is available */ -#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 - /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 @@ -424,6 +415,7 @@ /* drm_dp_update_payload_part1() function has start_slot argument */ #define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 +/* drm_driver->gem_prime_res_obj() is available */ /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ @@ -496,24 +488,15 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_connector_attach_colorspace_property() is available */ -#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 - -/* drm_mode_create_hdmi_colorspace_property() has 2 args */ -#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 - -/* drm_mode_create_dp_colorspace_property() has 2 args */ -#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 - -/* drm_connector_state->colorspace is available */ -#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 - /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ @@ -521,9 +504,6 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 -/* migrate_disable() is available */ -#define HAVE_MIGRATE_DISABLE 1 - /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -569,12 +549,6 @@ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 -/* drm_edid_override_connector_update() is available */ -#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 - -/* drm_add_override_edid_modes() is available */ -/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ - /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ /* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ @@ -831,14 +805,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PROCESSOR_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_MM_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_SIGNAL_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_TASK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_RBTREE_TYPES_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 @@ -864,8 +832,8 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 -/* drm_connector->edid_override is available */ -#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 /* struct migrate_vma has fault_page */ #define HAVE_MIGRATE_VMA_FAULT_PAGE 1 @@ -892,7 +860,7 @@ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 /* mm_access() is available */ -#define HAVE_MM_ACCESS 1 +/* #undef HAVE_MM_ACCESS */ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 @@ -1178,7 +1146,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.13.6" +#define PACKAGE_STRING "amdgpu-dkms 6.2.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1187,7 +1155,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.13.6" +#define PACKAGE_VERSION "6.2.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index f4df5913ba4e0..e584b1b4cfbe6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ #include ], [ cancel_work(NULL); - ], [ + ], [cancel_work], [], [ AC_DEFINE(HAVE_CANCEL_WORK, 1, [cancel_work() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 43fb1565aabc0..653c3e1e1ec98 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ],[ struct drm_connector *connector = NULL; connector->edid_override = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index f91f55f90ced8..e79473b4902ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,7 +5,8 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #include #include #else #include @@ -17,4 +18,4 @@ AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ [drm_hdcp_update_content_protection is available]) ]) ]) -]) +]) \ No newline at end of file From 53723c7af41e68d6c3ce68a1ed5d25b5ac5e0998 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 11 Jul 2023 12:14:26 -0400 Subject: [PATCH 1112/2070] drm/amdkcl: Add including of a missing header file This fixes the build against older kernels that don't have linux/iosys-map.h in their source trees. Change-Id: Ibffc262ec70c63220b92573119749fd6cccaba58 Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov --- include/kcl/header/linux/iosys-map.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/kcl/header/linux/iosys-map.h b/include/kcl/header/linux/iosys-map.h index a96b1547378c6..9ce52ad756e1d 100644 --- a/include/kcl/header/linux/iosys-map.h +++ b/include/kcl/header/linux/iosys-map.h @@ -3,7 +3,8 @@ #ifdef HAVE_LINUX_IOSYS_MAP_H #include_next +#else +#include #endif #endif - From d094b97bfed5b66edb5656c07f71a248aef8c501 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Jul 2023 14:26:32 +0800 Subject: [PATCH 1113/2070] drm/amdkcl: kcl-cleanup AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_connector.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 9e95e282f458a..c0e2b217ddcc5 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -27,14 +27,6 @@ #include #include -/* - * commit v4.9-rc4-949-g949f08862d66 - * drm: Make the connector .detect() callback optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) -#define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY -#endif - /** * drm_connector_for_each_possible_encoder - iterate connector's possible encoders * @connector: &struct drm_connector pointer From 7e77d0279397154159a6896026107cc7afdc7bec Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Jul 2023 10:21:55 +0800 Subject: [PATCH 1114/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP It's caused by 3f86b60691e60c57ad4ccc87a9b81e059c10af7e "drm/amd/display: only accept async flips for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f7973ef56b8d8..1ad643853c40c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10162,7 +10162,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * dm_crtc_helper_atomic_check() only accepts async flips with * fast updates. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc->state->async_flip && +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif (acrtc_state->update_type != UPDATE_TYPE_FAST || get_mem_type(old_plane_state->fb) != get_mem_type(fb))) drm_warn_once(state->dev, From aea0f0c4635dc10dc22b7b994a194102d7b1c1bd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jul 2023 11:59:54 +0800 Subject: [PATCH 1115/2070] drm/amdkcl: fake drm_warn_once() It's caused by 3f86b60691e60c57ad4ccc87a9b81e059c10af7e "drm/amd/display: only accept async flips for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c71867326f13b..15abde9faeb53 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -84,6 +84,11 @@ void kcl_drm_err(const char *format, ...); dev_warn((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) #endif /* drm_warn */ +#ifndef drm_warn_once +#define drm_warn_once(drm, fmt, ...) \ + dev_warn_once((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) +#endif /* drm_warn_once */ + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From d04af5ef4d52f1902edd71bfe04edfa2816de62f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 14 Jul 2023 10:53:22 +0800 Subject: [PATCH 1116/2070] drm/amdkcl: fake want_init_on_free() It's caused by 88181f344c9156ee111013c7e38187803b15612c "drm/ttm: Use init_on_free to delay release TTM BOs" Signed-off-by: Bob Zhou Change-Id: I56137fef24020b8ab3c341cff07b2d4b7d5db8b9 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 | 16 ++++++++++++++++ include/kcl/kcl_mm.h | 8 ++++++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 04b23437bad9e..60d876973cfbf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1085,6 +1085,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* want_init_on_free() is available */ +#define HAVE_WANT_INIT_ON_FREE 1 + /* ww_mutex_trylock() has context arg */ #define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c777c2da916ca..6564fa32a7189 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -177,6 +177,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_WANT_INIT_ON_FREE AC_AMDGPU_APPLE_GMUX_DETECT AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 new file mode 100644 index 0000000000000..8503b32aeee1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.2-5754-g6471384af2a6 +dnl # mm: security: introduce init_on_alloc=1 and init_on_free=1 boot options +dnl # +AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool r = want_init_on_free(); + ], [ + AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, + [want_init_on_free() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 2cb594bcf196f..fa9e3a7e7bd5b 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -109,4 +109,12 @@ static inline void vm_flags_clear(struct vm_area_struct *vma, } #endif +#ifndef HAVE_WANT_INIT_ON_FREE +static inline bool want_init_on_free(void) +{ + pr_warn_once("legacy kernel without want_init_on_free()\n"); + return false; +} +#endif + #endif /* AMDKCL_MM_H */ From d572529e3bb67a43ea94a33375dfa900d31dd430 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 17 Jul 2023 10:45:58 +0800 Subject: [PATCH 1117/2070] drm/amdkcl: fake macros DRM_FORMAT_ARG* It's caused by fb69732876d0ef8e6252fed2585a2acb4f75f121 "drm/amd/display: Expose more formats for overlay planes on DCN" Signed-off-by: Bob Zhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 959f64bb803a6..f28a041070a75 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -222,4 +222,10 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif +#ifndef DRM_FORMAT_ARGB16161616 +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From 555f4a03457a8cda988197dcdc85b854cd96b2af Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 20 Jul 2023 09:13:54 -0400 Subject: [PATCH 1118/2070] drm/amdkcl: Fix tests for exported symbols Fix tests that produce invalid results. AC_KERNEL_TRY_COMPILE_SYMBOL macro requires all possible locations of .c files to search for exported symbols. If file locations either missing or invalid the tests always return 'false'. Change-Id: I3ef01cece3da727bfdd912b616b486f9ee407bdb Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 | 7 +++++-- .../amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 | 2 +- .../drm-connector-attach-hdr-output-metadata-property.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 index 27001acd98f95..83a0b1e027b9b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -4,8 +4,11 @@ dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and dnl # early_acpi_os_unmap_memory() from Linux kernel AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_put_table], - [drivers/acpi/acpica/tbxface.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + acpi_put_table(NULL); + ], [acpi_put_table], [drivers/acpi/acpica/tbxface.c], [ AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, [acpi_put_table() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 index 7ae2c3fd78efd..211e6fdd63702 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ #include ], [ drm_connector_atomic_hdr_metadata_equal(NULL, NULL); - ], [drm_connector_atomic_hdr_metadata_equal], [drm/drm_connector.c], [ + ], [drm_connector_atomic_hdr_metadata_equal], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, [drm_connector_atomic_hdr_metadata_equal() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 index fccf8755fc7fe..7ea380c7d60eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ #include ], [ drm_connector_attach_hdr_output_metadata_property(NULL); - ], [drm_connector_attach_hdr_output_metadata_property], [drm/drm_connector.c], [ + ], [drm_connector_attach_hdr_output_metadata_property], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, [drm_connector_attach_hdr_output_metadata_property() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6564fa32a7189..0d6466d15598d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -498,7 +498,7 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ split(s, symbols, " ") } { for (i in symbols) { - s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\);" + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\)" if ($[0] ~ s) n++ } From 2a2f916d46f82831cde80bb450f0a9f4903c3afa Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Jul 2023 11:58:23 +0800 Subject: [PATCH 1119/2070] drm/amdkcl: apply amdkcl_ttm_resvp to dma_resv_trylock() It's caused by d769528e46493d56f9151fdecf25091b74c4eb49 "drm/amdgpu: add VISIBLE info in amdgpu_bo_print_info" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index e5e77df7903d4..b76457cb816c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1660,7 +1660,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) unsigned int pin_count; u64 size; - if (dma_resv_trylock(bo->tbo.base.resv)) { + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { if (!bo->tbo.resource) { placement = "NONE"; } else { @@ -1704,7 +1704,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) break; } } - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } else { placement = "UNKNOWN"; } From a92655405a646b04d9189c11d139a70516ae3cca Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Jul 2023 10:19:59 +0800 Subject: [PATCH 1120/2070] drm/amdkcl: fake _dynamic_func_call_no_desc() It's caused by 3f4e4c813a265803029c1c7e1a9915ceb0fc5da4 "drm/amdkfd: avoid svm dump when dynamic debug disabled" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_dynamic_debug.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_dynamic_debug.h b/include/kcl/kcl_dynamic_debug.h index 6c6f7296eba94..0d5ad3a9d2d52 100644 --- a/include/kcl/kcl_dynamic_debug.h +++ b/include/kcl/kcl_dynamic_debug.h @@ -3,6 +3,8 @@ #ifndef AMDKCL_DYNAMIC_DEBUG_H #define AMDKCL_DYNAMIC_DEBUG_H +#include + #ifndef DECLARE_DYNDBG_CLASSMAP enum class_map_type { DD_CLASS_TYPE_DISJOINT_BITS, @@ -61,4 +63,16 @@ struct ddebug_class_map { #endif +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) +#ifndef _dynamic_func_call_no_desc +#define __dynamic_func_call_no_desc(id, fmt, func, ...) do { \ + DEFINE_DYNAMIC_DEBUG_METADATA(id, fmt); \ + if (DYNAMIC_DEBUG_BRANCH(id)) \ + func(__VA_ARGS__); \ +} while (0) + +#define _dynamic_func_call_no_desc(fmt, func, ...) \ + __dynamic_func_call_no_desc(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__) +#endif /* _dynamic_func_call_no_desc */ +#endif /* CONFIG_DYNAMIC_DEBUG */ #endif /* AMDKCL_DYNAMIC_DEBUG_H */ From 646a572a84196e76590a8558369edc8c25b01791 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 14:31:36 +0800 Subject: [PATCH 1121/2070] drm/amdkcl: update KCL M4 find path for drm_dp_mst_helper.h The file path of drm_dp_mst_helper.h has been modify to 'drm/display/', some old KCL script path is invalid. So update new path and fix m4 test issue for drm_dp_mst_atomic_wait_for_dependencies. Fixes: 7607389cc536 ("drm/amdkcl: Check if drm_dp_mst_atomic_wait_for_dependencies() is available") Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++--- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 21 +++++++++++++++++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 60d876973cfbf..404f68719f952 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -308,10 +308,10 @@ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ /* drm_dp_mst_atomic_setup_commit() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ +#define HAVE_DRM_DP_ATOMIC_SETUP_COMMIT 1 /* drm_dp_mst_atomic_wait_for_dependencies() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ +#define HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES 1 /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 @@ -368,7 +368,7 @@ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ /* drm_dp_mst_root_conn_atomic_check() is available */ -/* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ +#define HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK 1 /* drm_dp_mst_port struct has full_pbn member */ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index d50c35a4fd1bc..96acc6bf42724 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -100,7 +100,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; ret = drm_dp_mst_atomic_setup_commit(NULL); @@ -120,10 +126,15 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ - int ret; - ret = drm_dp_mst_atomic_wait_for_dependencies(NULL); + drm_dp_mst_atomic_wait_for_dependencies(NULL); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, [drm_dp_mst_atomic_wait_for_dependencies() is available]) @@ -138,7 +149,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); From b0fd9541df56138de07e20bca323a9aa26b23ee7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 15:07:56 +0800 Subject: [PATCH 1122/2070] drm/amdkcl: test whether drm_gem_atomic_helper.h is available Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 8 +++++++- include/kcl/header/drm/drm_gem_atomic_helper.h | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 404f68719f952..0ef34d5c00f13 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -461,6 +461,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_IRQ_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 642993ebcc9cb..38a64fd0deb08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -55,7 +55,13 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/dp: Move public DisplayPort headers into dp/ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) - + + dnl # + dnl # v5.11-rc2-620-g6dd7b6ce43ac + dnl # drm: Add additional atomic helpers for shadow-buffered planes + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_atomic_helper.h]) + dnl # dnl # v5.18-rc2-594-gda68386d9edb dnl # drm: Rename dp/ to display/ diff --git a/include/kcl/header/drm/drm_gem_atomic_helper.h b/include/kcl/header/drm/drm_gem_atomic_helper.h index ba17f457edc4f..1eb467c2c3327 100644 --- a/include/kcl/header/drm/drm_gem_atomic_helper.h +++ b/include/kcl/header/drm/drm_gem_atomic_helper.h @@ -2,7 +2,7 @@ #ifndef _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ #define _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ -#if defined(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB) +#if defined(HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H) #include_next #endif From 72b1e97e97acaf8ecdb3e1d6842758e61618ae3b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 2 Aug 2023 10:33:07 +0800 Subject: [PATCH 1123/2070] drm/amdkcl: Fix typo in m4 file Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 index 6bf4a39e9679c..ed0b163902c11 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -17,7 +17,7 @@ AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ gem_obj->resv = &gem_obj->_resv; ], [ AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, - [ttm_buffer_object->base is available]) + [drm_gem_object->resv/_resv is available]) ]) ]) ]) From 155f6b580164cb74d7ba181aff3c968c08f5deab Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 17:34:58 +0800 Subject: [PATCH 1124/2070] drm/amdkcl: add kcl_header support for dkms m4 All of m4 script is using the same code block to verify if the header file is available, So add fake kcl header file and cleanup the verify for header files The M4 script will ben't blocked by the header file. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-device-pdev.m4 | 2 - .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 44 +------------------ .../gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 8 +--- .../drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 6 --- .../m4/drm-dp-cec-correlation-functions.m4 | 6 --- .../m4/drm-dp-link-train-channel-eq-delay.m4 | 8 +--- .../drm-dp-link-train-clock-recovery-delay.m4 | 6 --- .../m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 6 --- .../dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 12 ----- .../drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 6 --- .../dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 | 6 --- .../gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 24 ---------- .../dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 18 -------- .../drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 ----- .../dkms/m4/drm-dp-send-real-edid-checksum.m4 | 8 +--- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 9 ---- .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 4 -- .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 4 -- .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 3 -- .../m4/drm-hdcp-update-content-protection.m4 | 5 --- ...-up-update-payload-part1-start-slot-arg.m4 | 6 --- .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 6 --- .../dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 6 --- .../dkms/m4/drm_dsc_compute_rc_parameters.m4 | 6 +-- drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 | 4 -- .../amd/dkms/m4/drm_dsc_pps_payload_pack.m4 | 4 -- .../gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 | 4 -- .../drm/amd/dkms/m4/kernel_single_target.m4 | 3 ++ .../amd/dkms/tiny_wrapper/include/drm/drmP.h | 10 +++++ .../tiny_wrapper/include/drm/drm_aperture.h | 9 ++++ .../tiny_wrapper/include/drm/drm_dp_helper.h | 14 ++++++ .../include/drm/drm_dp_mst_helper.h | 14 ++++++ .../dkms/tiny_wrapper/include/drm/drm_dsc.h | 17 +++++++ .../dkms/tiny_wrapper/include/drm/drm_hdcp.h | 12 +++++ 38 files changed, 84 insertions(+), 252 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 index 25f5b1ca72eca..7bbbd70aab907 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -5,9 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ struct drm_device *pdd = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 96acc6bf42724..2e5156f632700 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); @@ -30,13 +24,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif + #include ],[ int ret; ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); @@ -49,13 +37,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ dnl # drm/dp_mst: Start tracking per-port VCPI allocations dnl # AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; struct drm_dp_mst_port *port; @@ -76,13 +58,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); @@ -100,13 +76,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_mst_atomic_setup_commit(NULL); @@ -126,13 +96,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ drm_dp_mst_atomic_wait_for_dependencies(NULL); ],[ @@ -149,13 +113,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index a20efecd2b022..cef22c56ee51c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index eabc0261dd0be..d168a591bcd23 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 3ba925a8e076f..3ded1ff2015a2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_cec_register_connector(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index fd42b70c0fd97..32db29f7c3936 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index dbd7be4543404..327cd21b0200c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 42d7b5595403a..1d4564270d065 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index 883dc5867886e..e56284f5a5a2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 0019f393b38f3..ad901210aeaba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ @@ -25,13 +19,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ dnl # drm/display/dp_mst: Move all payload info into the atomic state dnl # AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int vcpi; vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 7c01c0479075e..4198140ed6a0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 522d9e0e4b565..06d77b61ab828 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_dsc_aux_for_port(NULL); ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 index dc2ce8bd06835..e45e020edc7fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_port *mst_port = NULL; mst_port->full_pbn = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 index a1f26ca53e149..c66ffa1496233 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -5,13 +5,7 @@ dnl AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_port *dp_mst_port = NULL; dp_mst_port->passthrough_aux = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 02dac4390e913..4e54d919e6a3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,13 +4,7 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->hotplug(NULL); @@ -30,13 +24,7 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->register_connector(NULL); @@ -52,13 +40,7 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->destroy_connector(NULL, NULL); @@ -74,13 +56,7 @@ dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->poll_hpd_irq(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 961c150fe148e..3c491e182062e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_topology_mgr_resume(NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 44804d21ee9ff..8a11e44f294ed 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; mst_state->total_avail_slots = 0; @@ -30,13 +24,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; struct list_head payloads; @@ -56,13 +44,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; int pbn_div; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index cf4afe7538011..6de9a34aa627d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -15,13 +15,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_get_port_malloc(NULL); drm_dp_mst_put_port_malloc(NULL); @@ -36,13 +30,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index 27b63066be2dc..f09bb93dd8a35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index d10e0fcde3942..e480396741ffe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -9,10 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_SYNCOBJ_TIMELINE; @@ -28,10 +25,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_IRQ_SHARED; @@ -47,10 +41,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_PRIME; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 index 6631ba066edcf..0030f68fac152 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -15,12 +15,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ dnl # commit v5.9-rc5-1077-gd693def4fd1c dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRMP_H #include - #else #include - #endif ],[ struct drm_driver *drv = NULL; drv->gem_open_object = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 index cf63fed2c4727..226e89eebe85c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -5,12 +5,8 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #else #include - #endif ], [ struct drm_driver *drv = NULL; drv->gem_prime_res_obj(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 index bf7fcc83d14df..7eddabe7c8387 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -5,10 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ], [ drm_fb_helper_fill_info(NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index e79473b4902ab..55570026acaff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,12 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H - #include - #include - #else #include - #endif ], [ drm_hdcp_update_content_protection(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 7839b7b00baee..1b341003bb985 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_update_payload_part1(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 index 06cdbe40de8cf..c674432e635f2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif #include ], [ struct drm_dp_mst_topology_mgr *mst_mgr = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 66d1beb0b8a34..98d2982594b7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 index 57d179067d66b..a6f72c8fe6ba9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) - #include - #else - #include - #endif + #include ], [ drm_dsc_compute_rc_parameters(NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 index c5c3c2c4418bb..e10e43c6dfe6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) - #include - #else #include - #endif ], [ struct drm_dsc_config *conf = NULL; conf->simple_422 = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 index 624e489e45e3a..b85668160976c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) - #include - #else #include - #endif ], [ drm_dsc_pps_payload_pack(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 index 8c0d4b9e932ea..5bbcaa354dfde 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -5,9 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ drm_fb_helper_init(NULL, NULL); @@ -20,9 +18,7 @@ AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ dnl # drm: Rely on mode_config data for fb_helper initialization dnl # AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ drm_fb_helper_init(NULL, NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 7fd86cef1e099..91b36b22a7824 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -22,6 +22,9 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ xargs) + CFLAGS=$(echo $CFLAGS | \ + sed -e "s|nostdinc|nostdinc -I../tiny_wrapper/include|") + AC_SUBST(CC) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h new file mode 100644 index 0000000000000..c616e0e2c1798 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +struct vm_area_struct; +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h new file mode 100644 index 0000000000000..820228761e24b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..8a1cf0f4f9e33 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h new file mode 100644 index 0000000000000..dfc77f48cef83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include +#endif + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h new file mode 100644 index 0000000000000..309ffe3820d70 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include +#include +#else +#include_next +#endif + +#endif From 50b5f8472281325027f7d8418d1407aafaa1a72a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 1 Aug 2023 14:43:21 +0800 Subject: [PATCH 1125/2070] drm/amdkcl: fake totalram_pages() It's caused by 83c53bcd07ebbd0dd213049a5abd799dee842775 "drm/amd: Disable S/G for APUs when 64GB or more host memory" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm.h | 8 ++++++++ 5 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 637ecefbb9773..6357e5db55df3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -36,6 +36,11 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ +#ifndef HAVE_TOTALRAM_PAGES +unsigned long *_kcl_totalram_pages; +EXPORT_SYMBOL(_kcl_totalram_pages); +#endif /* HAVE_TOTALRAM_PAGES */ + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC @@ -47,4 +52,8 @@ void amdkcl_mm_init(void) _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); #endif #endif + +#ifndef HAVE_TOTALRAM_PAGES + _kcl_totalram_pages = (unsigned long *) amdkcl_fp_setup("totalram_pages", NULL); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0ef34d5c00f13..d28f52c2c9155 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1040,8 +1040,8 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 -/* interval_tree_insert have struct rb_root_cached */ -#define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 +/* totalram_pages() is available */ +#define HAVE_TOTALRAM_PAGES 1 /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0d6466d15598d..40818da042e74 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -159,6 +159,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE diff --git a/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 new file mode 100644 index 0000000000000..f57daa513df71 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.20-6506-gca79b0c211af +dnl # mm: convert totalram_pages and totalhigh_pages variables to atomic +dnl # +AC_DEFUN([AC_AMDGPU_TOTALRAM_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long ret; + ret = totalram_pages(); + ], [ + AC_DEFINE(HAVE_TOTALRAM_PAGES, 1, + [totalram_pages() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index fa9e3a7e7bd5b..767d6c3d41c66 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -117,4 +117,12 @@ static inline bool want_init_on_free(void) } #endif +#ifndef HAVE_TOTALRAM_PAGES +extern unsigned long *_kcl_totalram_pages; +static inline unsigned long totalram_pages(void) +{ + return *_kcl_totalram_pages; +} +#endif /* HAVE_TOTALRAM_PAGES */ + #endif /* AMDKCL_MM_H */ From b1b73438d970947124d91626c2889f9623d34128 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 3 Aug 2023 14:08:16 +0800 Subject: [PATCH 1126/2070] drm/amdkcl: fix 'totalram_pages' redeclared as different kind of symbol cleanup _kcl_totalram_pages symbol and replace totalram_pages to _totalram_pages Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 9 --------- include/kcl/kcl_mm.h | 8 +++++--- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 6357e5db55df3..637ecefbb9773 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -36,11 +36,6 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ -#ifndef HAVE_TOTALRAM_PAGES -unsigned long *_kcl_totalram_pages; -EXPORT_SYMBOL(_kcl_totalram_pages); -#endif /* HAVE_TOTALRAM_PAGES */ - void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC @@ -52,8 +47,4 @@ void amdkcl_mm_init(void) _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); #endif #endif - -#ifndef HAVE_TOTALRAM_PAGES - _kcl_totalram_pages = (unsigned long *) amdkcl_fp_setup("totalram_pages", NULL); -#endif } diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 767d6c3d41c66..994d6e41b429b 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -118,11 +119,12 @@ static inline bool want_init_on_free(void) #endif #ifndef HAVE_TOTALRAM_PAGES -extern unsigned long *_kcl_totalram_pages; -static inline unsigned long totalram_pages(void) +extern unsigned long totalram_pages; +static inline unsigned long _kcl_totalram_pages(void) { - return *_kcl_totalram_pages; + return totalram_pages; } +#define totalram_pages _kcl_totalram_pages #endif /* HAVE_TOTALRAM_PAGES */ #endif /* AMDKCL_MM_H */ From 9b09bf94220902273b3df85a61d289a0d22d26e6 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 2 Aug 2023 13:53:34 +0800 Subject: [PATCH 1127/2070] drm/amdkcl: Fix the compile warnnings in m4 files Fix the compile warnnings of "-Wunused-variable" and "-Wuninitialized" in m4 files Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- .../gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 7 +++++-- drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 9 ++++++--- drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 | 10 +++++----- drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 | 5 +++-- drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 | 3 ++- 10 files changed, 30 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 index ff2bf9c8949ad..7255ba02bca92 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -7,8 +7,11 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - void (*f)(struct pci_dev *pdev, u32 pasid); - amd_iommu_invalidate_ctx callback = f; + struct pci_dev *pdev = NULL; + u32 pasid = 0; + amd_iommu_invalidate_ctx callback = NULL; + + callback(pdev, pasid); ], [ AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, [amd_iommu_invalidate_ctx take arg type of pasid as u32]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 7867a6283d95f..1627d69677f9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -24,7 +24,8 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_fence_chain *chain = NULL; + struct dma_fence_chain *chain; + chain = NULL; ], [ AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, [struct dma_fence_chain is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 2e5156f632700..c0441f45a7861 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -40,11 +40,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ #include ],[ int ret; - struct drm_dp_mst_port *port; + struct drm_dp_mst_port *port = NULL; ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, - [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index e480396741ffe..5ca66e8289bc1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -12,7 +12,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_SYNCOBJ_TIMELINE; + int flag; + flag = DRIVER_SYNCOBJ_TIMELINE; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) @@ -28,7 +29,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_IRQ_SHARED; + int flag; + flag = DRIVER_IRQ_SHARED; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ drm_driver_feature DRIVER_IRQ_SHARED is available]) @@ -44,7 +46,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_PRIME; + int flag; + flag = DRIVER_PRIME; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ drm_driver_feature DRIVER_PRIME is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 index 95a45563d402e..54d06ba68400f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -7,11 +7,11 @@ AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct drm_format_info format = { - .format = DRM_FORMAT_XRGB16161616F, - .block_w = {0}, - .block_h = {0}, - }; + struct drm_format_info format; + + format.format = DRM_FORMAT_XRGB16161616F; + format.block_w[0] = 0; + format.block_h[0] = 0; ], [ AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, [drm_format_info.block_w and rm_format_info.block_h is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 index 786ce2c5590ac..53d34285e3b83 100644 --- a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -11,8 +11,9 @@ AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ #include #include ], [ - int v = MEMORY_DEVICE_COHERENT; - int w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + int v, w; + v = MEMORY_DEVICE_COHERENT; + w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; ], [ AC_DEFINE(HAVE_DEVICE_COHERENT, 1, [MEMORY_DEVICE_COHERENT is availablea]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 index ab6586797229a..108c7086638bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - size_t a, b; + size_t a, b = 0; a = kmalloc_size_roundup(b); ], [ AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 index 9ca6f08ae00e7..5aefabf94021b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - const char *str = str_yes_no(true); + const char *str; + str = str_yes_no(true); ], [ AC_DEFINE(HAVE_STR_YES_NO, 1, [str_yes_no() is defined]) diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 index 8503b32aeee1e..47463793e94b1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - bool r = want_init_on_free(); + bool r; + r = want_init_on_free(); ], [ AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, [want_init_on_free() is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 index e3018a1b798e0..9d87289b3bfc8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - int r = ww_mutex_trylock(NULL, NULL); + int r; + r = ww_mutex_trylock(NULL, NULL); ], [ AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, [ww_mutex_trylock() has context arg]) From eee9170cf501515fa4b13f16ce830b770576518b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 3 Aug 2023 11:08:58 +0800 Subject: [PATCH 1128/2070] drm/amdkcl: Optimize the code wrapped in the macro HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG [1] Fix the typo. [2] The fault function is not used here, so remove it. [3] Optimize the code wrapped in this macro. Only the vm_operations_struct->falut() function needs this macro Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ----- drivers/gpu/drm/amd/dkms/config/config.h | 5 +-- .../drm/amd/dkms/m4/vm_operations_struct.m4 | 5 ++- drivers/gpu/drm/ttm/ttm_bo_vm.c | 34 +------------------ include/drm/ttm/ttm_bo.h | 12 ++----- 5 files changed, 6 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 37ab3b0a6b8d2..34f25ad772783 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2855,11 +2855,7 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) #endif vm_fault_t ret; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_reserve(bo, vmf, vma); -#else ret = ttm_bo_vm_reserve(bo, vmf); -#endif if (ret) return ret; @@ -2867,12 +2863,8 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) if (ret) goto unlock; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_fault_reserved(vmf, vma, vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); -#else ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); -#endif if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d28f52c2c9155..55e3254002429 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1073,10 +1073,7 @@ /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 -/* vmf_insert_pfn_pud() is available */ -/* #undef HAVE_VMF_INSERT_PFN_PUD */ - -/* vm_fault->{address/vam} is available */ +/* vm_fault->{address/vma} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 /* vm_insert_pfn_prot() is available */ diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 index 9e01b9fb9f36b..111d006f1ac28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -7,14 +7,13 @@ AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf) = 0; struct vm_operations_struct *vm_ops = NULL; vm_ops->fault(NULL); ], [ AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, [vm_operations_struct->fault() wants 1 arg]) AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, - [vm_fault->{address/vam} is available]) + [vm_fault->{address/vma} is available]) ], [ dnl # dnl # commit v4.9-7746-g82b0f8c39a38 @@ -28,7 +27,7 @@ AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ ptest->vma = NULL; ], [ AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, - [vm_fault->{address/vam} is available]) + [vm_fault->{address/vma} is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 3497d1a566557..b205e25702a99 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -119,17 +119,10 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, * VM_FAULT_RETRY if blocking wait. * VM_FAULT_NOPAGE if blocking wait and retrying was not allowed. */ -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf, - struct vm_area_struct *vma) -{ -#else vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; -#endif /* * Work around locking order reversal in fault / nopfn * between mmap_lock and bo_reserve: Perform a trylock operation @@ -192,19 +185,11 @@ EXPORT_SYMBOL(ttm_bo_vm_reserve); * VM_FAULT_OOM on out-of-memory * VM_FAULT_RETRY if retryable wait */ -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, - struct vm_area_struct *vma, - pgprot_t prot, - pgoff_t num_prefault) -{ -#else vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; -#endif struct ttm_buffer_object *bo = vma->vm_private_data; unsigned long page_offset; unsigned long page_last; @@ -314,14 +299,9 @@ static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res) __free_page(dummy_page); } -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, struct vm_area_struct *vma, pgprot_t prot) -{ -#else vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) { struct vm_area_struct *vma = vmf->vma; -#endif struct ttm_buffer_object *bo = vma->vm_private_data; vm_fault_t ret = VM_FAULT_NOPAGE; unsigned long address; @@ -364,30 +344,18 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) pgprot_t prot; int idx; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_reserve(bo, vmf, vma); -#else ret = ttm_bo_vm_reserve(bo, vmf); -#endif if (ret) return ret; prot = vma->vm_page_prot; if (drm_dev_enter(bo->base.dev, &idx)) { - -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_fault_reserved(vmf, vma, prot, TTM_BO_VM_NUM_PREFAULT); -#else ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); -#endif drm_dev_exit(idx); } else { -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_dummy_page(vmf, vma, prot); -#else ret = ttm_bo_vm_dummy_page(vmf, prot); -#endif } + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 5bc9cc38a7cb4..42cd057829527 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -456,23 +456,15 @@ int ttm_bo_evict_first(struct ttm_device *bdev, int ttm_bo_access(struct ttm_buffer_object *bo, unsigned long offset, void *buf, int len, int write); -#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault); + +#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); #else -vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf, - struct vm_area_struct *vma); - -vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, - struct vm_area_struct *vma, - pgprot_t prot, - pgoff_t num_prefault); - vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf); #endif From ea6b75a96dd06ff582922ecfa7f837e32725bfcf Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 3 Aug 2023 13:10:47 +0800 Subject: [PATCH 1129/2070] drm/amdkcl: Modify compile CFLAGS for m4 files Removing "-Wno-error=uninitialized -Wno-error=unused-variable" to make these two kinds of warnning as error when compile m4 files. Signed-off-by: Ma Jun Reviewed-by: Bob Zhou Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 40818da042e74..056d5d2c4f315 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -397,7 +397,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From 65b162acab73c9f6e6e26e5bf22c8c2398b7667b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 8 Aug 2023 10:10:19 +0800 Subject: [PATCH 1130/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP It's caused by 6fb5589425ee17f732aaae462532d5034b096212 "drm/amd/display: ensure async flips are only accepted for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1ad643853c40c..32ff5c48d4753 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13081,7 +13081,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * Only allow async flips for fast updates that don't change * the FB pitch, the DCC state, rotation, mem_type, etc. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip && +#else + if ((new_crtc_state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif (lock_and_validation_needed || amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { drm_dbg_atomic(crtc->dev, From a57e6e1780e52657bdc76a1e8427959383af7833 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 11 Aug 2023 13:42:06 +0800 Subject: [PATCH 1131/2070] drm/amdkcl: Fix the uninitialized warning in m4 Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 index 406fa50e310c5..f989b29503c45 100644 --- a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ #include ], [ struct migrate_vma mig = {0}; - struct page *fault_page; + struct page *fault_page = NULL; mig.fault_page = fault_page; ], [ AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, From 282e2694c7ca49b9a13e60cd8a7e6821afc40e29 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Aug 2023 11:11:40 +0800 Subject: [PATCH 1132/2070] drm/amdkcl: fix file search path for m4 script Some file path has been modified, so update these file search path. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 2 +- .../gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index e584b1b4cfbe6..e7616748289ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ #include ], [ cancel_work(NULL); - ], [cancel_work], [], [ + ], [cancel_work], [kernel/workqueue.c], [ AC_DEFINE(HAVE_CANCEL_WORK, 1, [cancel_work() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1d4564270d065..c9127ca8d82c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); - ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, [drm_dp_mst_add_affected_dsc_crtcs() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 06d77b61ab828..6d83fb019062d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ #include ], [ drm_dp_mst_dsc_aux_for_port(NULL); - ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, [drm_dp_mst_dsc_aux_for_port() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index f09bb93dd8a35..44343cb753bbe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,10 +5,10 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + #include ], [ drm_dp_send_real_edid_checksum(NULL, 0); - ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c], [ AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, [drm_dp_send_real_edid_checksum() is available]) ]) From efdccf83b57c3d89d66e96dc7bf0c41b82833a46 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 15 Aug 2023 17:31:22 +0800 Subject: [PATCH 1133/2070] drm/amdkcl: Fix error in HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 check The original code can't detect the wrong param type. Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 index 7255ba02bca92..3ddbe27c03284 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -7,11 +7,10 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_dev *pdev = NULL; - u32 pasid = 0; - amd_iommu_invalidate_ctx callback = NULL; + void (*f)(struct pci_dev *pdev, u32 pasid) = NULL; + amd_iommu_invalidate_ctx callback; - callback(pdev, pasid); + callback = f; ], [ AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, [amd_iommu_invalidate_ctx take arg type of pasid as u32]) From 03a6df7b8e26d84f06f5e013741a3fb5caefb2d7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 16 Aug 2023 11:48:36 +0800 Subject: [PATCH 1134/2070] drm/amdkfd: Correct some spacing errors introduced in rebase process Signed-off-by: Asher Song Reviewd-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/Makefile | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 9b8dc9f53bb2c..66f584ea1c783 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -62,7 +62,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ - $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 314d96a278e6c..8b3b10d83ccf7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1769,17 +1769,17 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, /* Place holder for deprecated DBG API */ static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, - struct kfd_process *p, void *data) + struct kfd_process *p, void *data) { - dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); - return -EINVAL; + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; } /* Place holder for deprecated CMA API */ static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, - struct kfd_process *local_p, void *data) { - dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); - return -EINVAL; + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; } /* Handle requests for watching SMI events */ @@ -3558,8 +3558,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), - AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, - kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), From d443df6751ebbcefe349a03709059aad578580f6 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 23 Aug 2023 10:32:16 +0800 Subject: [PATCH 1135/2070] drm/amd/pm: workaround for the wrong ac power detection on smu 13.0.0 Workaround for the wrong ac power detection on smu 13.0.0. This is a temporary solution and will be dropped in the future. Signed-off-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +-- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 63a65ea802fd5..950cc8ec1ddc7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1002,8 +1002,7 @@ static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) { int ret = 0; - if (smu->dc_controlled_by_gpio && - smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) ret = smu_v13_0_allow_ih_interrupt(smu); return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 468d51f5f9187..8b5ef34173e00 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -3166,7 +3166,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, .get_power_limit = smu_v13_0_0_get_power_limit, .set_power_limit = smu_v13_0_0_set_power_limit, - .set_power_source = smu_v13_0_set_power_source, .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, .run_btc = smu_v13_0_run_btc, From 98b9ac9f35ae2a91832bd49c470cd810097d5246 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 16 Aug 2023 10:12:07 +0800 Subject: [PATCH 1136/2070] drm/amdkcl: drop the direct call for AC_KERNEL_CHECK_SYMBOL_EXPORT [why] To support distros systems, AC_KERNEL_CHECK_SYMBOL_EXPORT create symbol config entry by parsing Modules.symvers. But Modules.symvers is unavailable for intree build, so that the AC_KERNEL_CHECK_SYMBOL_EXPORT is invalid. [how] The AC_KERNEL_TRY_COMPILE_SYMBOL adds function signatures check base on AC_KERNEL_CHECK_SYMBOL_EXPORT. So modify all of AC_KERNEL_CHECK_SYMBOL_EXPORT to AC_KERNEL_TRY_COMPILE_SYMBOL and conduct function signatures check for all symbol config entries to support intree build. Signed-off-by: Bob Zhou Reviewed-by: Tim Huang --- .../dkms/m4/__drm_atomic_helper_crtc_reset.m4 | 8 ++- .../dkms/m4/acpi_dev_get_first_match_dev.m4 | 7 +- .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 7 +- .../gpu/drm/amd/dkms/m4/down-read-killable.m4 | 11 ++-- ...nector-set-panel-orientation-with-quirk.m4 | 9 ++- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 11 ++-- ...omic_helper_calc_timestamping_constants.m4 | 7 +- .../dkms/m4/drm_helper_force_disable_all.m4 | 6 +- ...rm_mode_create_hdmi_colorspace_property.m4 | 8 ++- drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 9 ++- drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 | 7 +- .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 8 ++- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 66 +++++++++---------- .../drm/amd/dkms/m4/i2c_new_client_device.m4 | 7 +- .../gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 | 6 +- .../drm/amd/dkms/m4/kallsyms-lookup-name.m4 | 8 ++- drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 6 +- .../gpu/drm/amd/dkms/m4/pci_pr3_present.m4 | 6 +- drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 | 7 +- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 10 +-- .../drm/amd/dkms/m4/synchronize-shrinkers.m4 | 11 ++-- drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 11 ++-- .../drm/amd/dkms/m4/zone_device_page_init.m4 | 9 ++- 23 files changed, 154 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 index 637a0bc453cd7..532031624b3a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -4,9 +4,11 @@ dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_s dnl # AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([__drm_atomic_helper_crtc_reset], - [drivers/gpu/drm/drm_atomic_state_helper.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + __drm_atomic_helper_crtc_reset(NULL, NULL); + ],[__drm_atomic_helper_crtc_reset], [drivers/gpu/drm/drm_atomic_state_helper.c],[ AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, [__drm_atomic_helper_crtc_reset() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 index f83c2733ac2e1..5668a2d728b89 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -4,8 +4,11 @@ dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper dnl # AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_dev_get_first_match_dev], - [drivers/acpi/utils.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + acpi_dev_get_first_match_dev(NULL, NULL, 0); + ],[acpi_dev_get_first_match_dev],[drivers/acpi/utils.c], [ AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, [acpi_dev_get_first_match_dev() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 index 67cbbec8cac3e..c42fcb583b362 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -12,8 +12,11 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, [amd_iommu_pc_get_max_banks() declared]) ], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_amd_iommu], - [drivers/iommu/amd/init.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + get_amd_iommu(0); + ],[get_amd_iommu],[drivers/iommu/amd/init.c], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, [amd_iommu_pc_get_max_banks() arg is unsigned int]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 index 6de71b3c0a40d..7a74bd4d25889 100644 --- a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -4,10 +4,13 @@ #dnl AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [down_read_killable], - [kernel/locking/rwsem.c], - [AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + int ret; + ret = down_read_killable(NULL); + ],[down_read_killable], [kernel/locking/rwsem.c],[ + AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, [down_read_killable() is available])] ) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 index 463767cb7e3a6..0ae5de382dec8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -3,9 +3,12 @@ dnl # commit v5.5-rc2-1360-g69654c632d80 dnl # drm/connector: Split out orientation quirk detection (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_set_panel_orientation_with_quirk], - [drivers/gpu/drm/drm_connector.c], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_panel_orientation_with_quirk(NULL, 0, 0, 0); + ],[drm_connector_set_panel_orientation_with_quirk], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, [drm_connector_set_panel_orientation_with_quirk() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index c4d2a03ec81c0..36c0a786c849f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -13,10 +13,13 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, [drm_gem_object_put() is available]) - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_object_put], - [drivers/gpu/drm/drm_gem.c], [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, - [drm_gem_object_put() is exported]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_object_put(NULL); + ],[drm_gem_object_put],[drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 index 79ab39b5802f3..7b6d31518fe3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -4,8 +4,11 @@ dnl # Extract drm_atomic_helper_calc_timestamping_constants() dnl # AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_atomic_helper_calc_timestamping_constants], - [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_atomic_helper_calc_timestamping_constants(NULL); + ],[drm_atomic_helper_calc_timestamping_constants], [drivers/gpu/drm/drm_atomic_helper.c], [ AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, [drm_atomic_helper_calc_timestamping_constants() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 index f52b3c10ccd43..69513e0cacc39 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -7,7 +7,11 @@ dnl # drm: Move the legacy kms disable_all helper to crtc helpers dnl # AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_helper_force_disable_all(NULL); + ],[drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, [drm_helper_force_disable_all() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 index 7a8fe049ac51b..ecc33db72dcbd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -4,8 +4,12 @@ dnl # drm: Rename HDMI colorspace property creation function dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ - AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_colorspace_property(NULL); + ],[drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, [drm_connector_attach_colorspace_property() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index 4a1160753c960..bae97886408be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -4,8 +4,13 @@ dnl # drm/prime: split array import functions v4 dnl # AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, [drm_prime_sg_to_dma_addr_array() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_prime_sg_to_dma_addr_array(NULL, NULL, 0); + ],[drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, + [drm_prime_sg_to_dma_addr_array() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 index 62209f24b90e0..fb7266321075c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -16,8 +16,11 @@ AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ ], [ dnl # v5.3-rc1-622-g2dc5d44ccc5e dnl # drm: add drm_print_bits - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_print_bits], - [drivers/gpu/drm/drm_print.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_print_bits(NULL, 0, NULL, 0, 0); + ],[drm_print_bits], [drivers/gpu/drm/drm_print.c], [ AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, [drm_print_bits() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 index 0ffcd218e5a99..7f8cf4e9ad0a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -3,9 +3,11 @@ dnl # v5.6-rc2-359-g63170ac6f2e8 dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() dnl # AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_simple_encoder_init], - [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, [drm_simple_encoder is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 index 8f70124da00f0..e2fe781b7d7dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -1,53 +1,47 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ AC_KERNEL_DO_BACKGROUND([ dnl # - dnl # v4.5-rc4-71-g1e9877902dc7 - dnl # mm/gup: Introduce get_user_pages_remote() + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code dnl # - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_user_pages_remote],[mm/gup.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ dnl # - dnl # v5.8-12463-g64019a2e467a - dnl # mm/gup: remove task_struct pointer for all gup code + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() dnl # - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, - [get_user_pages_remote() remove task_struct pointer]) - ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ],[ dnl # - dnl # commit v4.9-7744-g5b56d49fc31d - dnl # mm: add locked parameter to get_user_pages_remote() + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags dnl # - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, - [get_user_pages_remote() wants locked parameter]) - ], [ - dnl # - dnl # commit v4.8-14096-g9beae1ea8930 - dnl # mm: replace get_user_pages_remote() write/force parameters - dnl # with gup_flags - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, - [get_user_pages_remote() wants gup_flags parameter]) - ],[ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, - [get_user_pages_remote() is introduced with initial prototype]) - ]) + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) ]) ]) ]) ]) ]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 index cedd29e0fe70e..a4d3e37bfa38c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -4,8 +4,11 @@ dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dum dnl # AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([i2c_new_client_device], [drivers/i2c/i2c-core-base.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + i2c_new_client_device(NULL, NULL); + ],[i2c_new_client_device], [drivers/i2c/i2c-core-base.c],[ AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, [i2c_new_client_device() is enabled]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 index e44504998e830..29cc9b9271330 100644 --- a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -4,7 +4,11 @@ dnl # time: Introduce jiffies64_to_msecs() dnl # AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([jiffies64_to_msecs], [kernel/time/time.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + jiffies64_to_msecs(0); + ],[jiffies64_to_msecs], [kernel/time/time.c], [ AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 index 62e540f41a7df..4e123cddf2838 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -4,9 +4,11 @@ dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sam dnl # AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kallsyms_lookup_name], - [kernel/kallsyms.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + kallsyms_lookup_name(NULL); + ],[kallsyms_lookup_name],[kernel/kallsyms.c],[ AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, [kallsyms_lookup_name is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 index 2c8863597781f..bdfb1256a9ccb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -5,7 +5,11 @@ dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from th dnl # AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([mmput_async], [kernel/fork.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + mmput_async(NULL); + ],[mmput_async], [kernel/fork.c], [ AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 index 38e50b2c0766f..e0fbc073caf06 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -4,7 +4,11 @@ dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence dnl # AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pci_pr3_present], [drivers/pci/pci.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pci_pr3_present(NULL); + ],[pci_pr3_present], [drivers/pci/pci.c], [ AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 index 35651096f8e2a..a69d9f2264f6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -4,8 +4,11 @@ dnl # virtio-mem: Allow to specify an ACPI PXM as nid dnl # AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pxm_to_node], - [drivers/acpi/numa/srat.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pxm_to_node(0); + ],[pxm_to_node], [drivers/acpi/numa/srat.c], [ AC_DEFINE(HAVE_PXM_TO_NODE, 1, [pxm_to_node() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 8ad24bc40f5fb..6b53674fb88bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,12 +23,14 @@ dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c], [], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_atomic_helper_legacy_gamma_set(NULL, NULL, NULL, NULL, 0, NULL); + ], [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c],[],[ AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) - ]) + ]) ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 index 3abf21e7f2b67..3033e4be5a17c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -4,10 +4,13 @@ dnl # mm/vmscan: add sync_shrinkers function v3 dnl # AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([synchronize_shrinkers], - [mm/vmscan.c], [ - AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, - [synchronize_shrinkers() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + synchronize_shrinkers(); + ], [synchronize_shrinkers], [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 index c1dc1717cc324..7c355cae6ed01 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -4,13 +4,14 @@ dnl # sysfs: Add sysfs_emit and sysfs_emit_at dnl # to format sysfs output AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit sysfs_emit_at], - [fs/sysfs/file.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + sysfs_emit(NULL, NULL); + sysfs_emit_at(NULL, 0, NULL); + ],[sysfs_emit sysfs_emit_at],[fs/sysfs/file.c], [ AC_DEFINE(HAVE_SYSFS_EMIT, 1, [sysfs_emit() and sysfs_emit_at() are available]) ]) ]) ]) - - -) diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 index d73aab950a652..56eaeb4b6d888 100644 --- a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -5,8 +5,13 @@ dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page re dnl # AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([zone_device_page_init], [mm/memremap.c], [ - AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + zone_device_page_init(NULL); + ], [zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, + [zone_device_page_init() is available]) ]) ]) ]) From 38b554a0d42aa5669c581c1c42266418fe6172e5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Aug 2023 17:47:36 +0800 Subject: [PATCH 1137/2070] drm/amdkcl: fix m4 include for HAVE_SYNCHRONIZE_SHRINKERS To support difference version shrinkers.h in distro systems, including mmzone.h header file make m4 script detect success. Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 index 3033e4be5a17c..9429112a66d2b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include #include ], [ synchronize_shrinkers(); From 12266bb6dbc4a60662dabbcd715295172d822e10 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Aug 2023 17:59:02 +0800 Subject: [PATCH 1138/2070] drm/amdkcl: Include kcl_rbtree.h in the backport.h Include kcl_rbtree.h in the backport.h instead of gpu_scheduler.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/scheduler/backport/backport.h | 2 +- include/drm/gpu_scheduler.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 5c3a31abb6713..740dbe3af3b76 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -6,6 +6,6 @@ #include #include #include -#include +#include #endif diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index c2bdee34f631c..8dd05a0b7d1c5 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -29,7 +29,6 @@ #include #include #include -#include #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) From 661a853e6deacf83d377517440e10e721fc01106 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 28 Aug 2023 11:23:40 +0800 Subject: [PATCH 1139/2070] drm/amdkcl: update include sequence for kcl_rbtree.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit the kcl_amdgpu_drm_fb_helper.h should includes kcl_rbtree.h to avoid the below issue about struct lack. In file included from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu_ring.h:28:0, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu_ctx.h:29, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu.h:43, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h:36, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/backport/backport.h:69, from :0: /var/lib/dkms/amdgpu-pro/1.0/build/include/drm/gpu_scheduler.h:262:25: error: field ‘rb_tree_root’ has incomplete type struct rb_root_cached rb_tree_root; Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- .../gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 5abb5cf97824c..8c75bfc4e993b 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -33,6 +33,7 @@ #include #include #include +#include #include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE From f64bfea3684176d54168f603a7128aa1acb0edfd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 25 Aug 2023 11:29:55 +0800 Subject: [PATCH 1140/2070] drm/amdkcl: change the order of the judgment for mem_type To avoid the following Null pointer dereference error, change the order of the judgment for old_mem->mem_type Signed-off-by: Asher Song Acked-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 34f25ad772783..69880a3efa649 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -541,10 +541,6 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, abo = ttm_to_amdgpu_bo(bo); - if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || - old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) - return -EINVAL; - adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -553,6 +549,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, ttm_bo_move_null(bo, new_mem); return 0; } + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + if (old_mem->mem_type == TTM_PL_SYSTEM && (new_mem->mem_type == TTM_PL_TT || new_mem->mem_type == AMDGPU_PL_PREEMPT)) { From 4932664e0e21598e4992de0463d21a00a9dbd0ed Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Sep 2023 14:57:49 +0800 Subject: [PATCH 1141/2070] drm/amdkcl: fake drm_show_fdinfo It's caused v6.4-rc1-190-g3f09a0cd4ea3 drm: Add common fdinfo helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c | 68 +++++++++++++++++++ .../gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 | 37 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_file.h | 8 +++ 6 files changed, 117 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 create mode 100644 include/kcl/kcl_drm_file.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 250f082dd623a..b024977ba350b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3173,9 +3173,11 @@ static struct drm_driver amdgpu_kms_driver = { DRM_FBDEV_TTM_DRIVER_OPS, .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_DRIVER_SHOW_FDINFO #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif +#endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e5ca4419fb44d..ba35df4633674 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c new file mode 100644 index 0000000000000..7ddc32cafc5b7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c @@ -0,0 +1,68 @@ +/* + * \author Rickard E. (Rik) Faith + * \author Daryll Strauss + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#ifndef HAVE_DRM_SHOW_FDINFO +/** + * drm_show_fdinfo - helper for drm file fops + * @m: output stream + * @f: the device file instance + * + * Helper to implement fdinfo, for userspace to query usage stats, etc, of a + * process using the GPU. See also &drm_driver.show_fdinfo. + * + * For text output format description please see Documentation/gpu/drm-usage-stats.rst + */ +void drm_show_fdinfo(struct seq_file *m, struct file *f) +{ + struct drm_file *file = f->private_data; + struct drm_device *dev = file->minor->dev; + struct drm_printer p = drm_seq_file_printer(m); + + drm_printf(&p, "drm-driver:\t%s\n", dev->driver->name); + + if (dev_is_pci(dev->dev)) { + struct pci_dev *pdev = to_pci_dev(dev->dev); + + drm_printf(&p, "drm-pdev:\t%04x:%02x:%02x.%d\n", + pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + } +} +EXPORT_SYMBOL(drm_show_fdinfo); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 new file mode 100644 index 0000000000000..a144bfa3967d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_show_fdinfo(NULL, NULL); + ],[drm_show_fdinfo], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_SHOW_FDINFO, 1, [drm_show_fdinfo() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_driver *drm_driver = NULL; + + drm_driver->show_fdinfo(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_SHOW_FDINFO, 1, + [drm_driver->show_fdinfo() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_SHOW_FDINFO], [ + AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO + AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 056d5d2c4f315..bb1b196336981 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -187,6 +187,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE + AC_AMDGPU_DRM_SHOW_FDINFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_file.h b/include/kcl/kcl_drm_file.h new file mode 100644 index 0000000000000..d23292e37dc25 --- /dev/null +++ b/include/kcl/kcl_drm_file.h @@ -0,0 +1,8 @@ +#ifndef __AMDKCL_KCL_DRM_DRV_H__ +#define __AMDKCL_KCL_DRM_DRV_H__ +#include + +#ifndef HAVE_DRM_SHOW_FDINFO +void drm_show_fdinfo(struct seq_file *m, struct file *f); +#endif +#endif From db59af5956318b95617a0719d205b30ce58113aa Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Sep 2023 17:38:41 +0800 Subject: [PATCH 1142/2070] drm/amdkcl: fake local64_try_cmpxchg It's caused by 8fc4fddaf9a184eea7da21290236a1764e608a01 locking/generic: Wire up local{,64}_try_cmpxchg() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/dkms/m4/atomic-long-try-cmpxchg.m4 | 37 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/kcl_local64.h | 33 +++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 create mode 100644 include/kcl/kcl_local64.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b4e8aa0270855..a38b7a020b57b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -107,4 +107,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 new file mode 100644 index 0000000000000..5d20db398bf97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v5.13-rc1-138-g67d1b0de258a locking/atomic: add arch_atomic_long*() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + long r = 0; + t = atomic_long_try_cmpxchg(NULL, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG, 1, + [atomic_long_try_cmpxchg() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.3-rc1-6-g8fc4fddaf9a1 +dnl # locking/generic: Wire up local{,64}_try_cmpxchg() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + s64 r = 0; + local_t *l = NULL; + t = local_try_cmpxchg(l, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_LOCAL_TRY_CMPXCHG, 1, + [local_try_cmpchg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bb1b196336981..7cfefe20e1955 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -188,6 +188,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PID_TYPE AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO + AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG + AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_local64.h b/include/kcl/kcl_local64.h new file mode 100644 index 0000000000000..0b374fef81d85 --- /dev/null +++ b/include/kcl/kcl_local64.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_ASM_GENERIC_LOCAL64_H +#define AMDKCL_ASM_GENERIC_LOCAL64_H + +#include +#include +#include + +/* + * A signed long type for operations which are atomic for a single CPU. + * Usually used in combination with per-cpu variables. + * + * This is the default implementation, which uses atomic64_t. Which is + * rather pointless. The whole point behind local64_t is that some processors + * can perform atomic adds and subtracts in a manner which is atomic wrt IRQs + * running on this CPU. local64_t allows exploitation of such capabilities. + */ + +/* Implement in terms of atomics. */ + +#if !defined HAVE_LINUX_LOCAL_TRY_CMPXCHG && defined HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG +#define local_try_cmpxchg(l, po, n) atomic_long_try_cmpxchg((&(l)->a), (po), (n)) +#if BITS_PER_LONG == 64 + +static inline bool local64_try_cmpxchg(local64_t *l, s64 *old, s64 new) +{ + return local_try_cmpxchg(&l->a, (long *)old, new); +} +#else +#define local64_try_cmpxchg(l, po, n) atomic64_try_cmpxchg((&(l)->a), (po), (n)) +#endif +#endif +#endif From 61865b39cce5ed848c1c56ce7a796d23718e29bf Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 14:54:33 +0800 Subject: [PATCH 1143/2070] drm/amdkcl: test whether atomoic_long_try_cmpxchg() exist It's caused by v6.5-rc2-955-g9e761bff03e1 drm/amdgpu: Use local64_try_cmpxchg in amdgpu_perf_read Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c index 6e91ea1de5aaf..1017a30d3687d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -275,9 +275,13 @@ static void amdgpu_perf_read(struct perf_event *event) if ((!pe->adev->df.funcs) || (!pe->adev->df.funcs->pmc_get_count)) return; - +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG prev = local64_read(&hwc->prev_count); +#endif do { +#ifndef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG + prev = local64_read(&hwc->prev_count); +#endif switch (hwc->config_base) { case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF: case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI: @@ -288,8 +292,11 @@ static void amdgpu_perf_read(struct perf_event *event) count = 0; break; } +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG } while (!local64_try_cmpxchg(&hwc->prev_count, &prev, count)); - +#else + } while (local64_cmpxchg(&hwc->prev_count, prev, count) != prev); +#endif local64_add(count - prev, &event->count); } From 346ee09a41de3da973b3db4b271799976801dab0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 17:04:21 +0800 Subject: [PATCH 1144/2070] drm/amdkcl: test create_class's argument quantity It's caused by v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/create_class.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/class.h | 10 ++++++++++ include/kcl/kcl_class.h | 17 +++++++++++++++++ 6 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/create_class.m4 create mode 100644 include/kcl/header/linux/class.h create mode 100644 include/kcl/kcl_class.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a38b7a020b57b..a5a27b4857acc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -108,4 +108,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/create_class.m4 b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 new file mode 100644 index 0000000000000..bb9bd7bd2d13d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_DEVICE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct class* class = NULL; + class = class_create(NULL); + ], [ + AC_DEFINE(HAVE_ONE_ARGUMENT_OF_CLASS_CREATE, 1, + [class_create has one argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7cfefe20e1955..d9fc3d1fbd968 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -190,6 +190,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SHOW_FDINFO AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG + AC_AMDGPU_LINUX_DEVICE_CLASS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index f99ed5020b2e7..557b1a1589e6d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -119,4 +119,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #apple-gmux: Add helper for presence detect dnl AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) + + dnl #v5.5-rc2-6-ga8ae608529ab + dnl #device.h: move 'struct class' stuff out to device/class.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) ]) diff --git a/include/kcl/header/linux/class.h b/include/kcl/header/linux/class.h new file mode 100644 index 0000000000000..595b34ca30dbe --- /dev/null +++ b/include/kcl/header/linux/class.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CLASS_H_H_ +#define _KCL_HEADER_LINUX_CLASS_H_H_ + +#ifdef HAVE_LINUX_DEVICE_CLASS_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_class.h b/include/kcl/kcl_class.h new file mode 100644 index 0000000000000..fbce818309960 --- /dev/null +++ b/include/kcl/kcl_class.h @@ -0,0 +1,17 @@ +#ifndef __AMDKCL_CLASS_H__ +#define __AMDKCL_CLASS_H__ + +#ifdef HAVE_LINUX_DEVICE_CLASS_H +#include +#endif +#include +static inline struct class* kcl_class_create(struct module *owner, const char* name) +{ +#ifdef HAVE_ONE_ARGUMENT_OF_CLASS_CREATE + return class_create(name); +#else + return class_create(owner, name); +#endif +} +#endif + From 99942927fd536218ddc5f267a48e1d29b7882965 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 17:39:12 +0800 Subject: [PATCH 1145/2070] drm/amdkcl: update dkms support for hmm using new drm_exec object It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 85 ++++++++++++--------- 2 files changed, 49 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index ad81170f068da..ffbe106d1fbdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -24,6 +24,7 @@ #define __AMDGPU_BO_LIST_H__ #include +#include struct hmm_range; @@ -43,6 +44,7 @@ struct amdgpu_bo_list_entry { bool user_invalidated; #else int user_invalidated; + struct ttm_validate_buffer tv; #endif }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index d55f3a905931a..f7f164704b07b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -956,21 +956,56 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct mm_struct *usermm; + usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); + if (usermm && usermm != current->mm) { + r = -EPERM; + goto out_free_user_pages; + } + if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && + e->user_invalidated) { + amdgpu_bo_placement_from_domain(e->bo, + AMDGPU_GEM_DOMAIN_CPU); + r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, + &ctx); + if (r) + goto out_free_user_pages; + amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, + e->range); + } + } #else while (1) { struct list_head need_pages; + drm_exec_until_all_locked(&p->exec) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; - r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, - &duplicates); - if (unlikely(r != 0)) { - if (r != -ERESTARTSYS) - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); - goto error_free_pages; - } + amdgpu_bo_list_for_each_entry(e, p->bo_list) { + /* One fence for TTM and one for each CS job */ + r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + + e->bo_va = amdgpu_vm_bo_find(vm, e->bo); + } + if (p->uf_bo) { + r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + } + } INIT_LIST_HEAD(&need_pages); amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + struct amdgpu_bo *bo = e->bo; if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, &e->user_invalidated) && e->user_pages) { @@ -997,7 +1032,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, break; /* Unreserve everything again. */ - ttm_eu_backoff_reservation(&p->ticket, &p->validated); + drm_exec_fini(&p->exec); /* We tried too many times, just abort */ if (!--tries) { @@ -1027,35 +1062,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } } - - /* And try again. */ - list_splice(&need_pages, &p->validated); } #endif - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct mm_struct *usermm; - - usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); - if (usermm && usermm != current->mm) { - r = -EPERM; - goto out_free_user_pages; - } - - if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && - e->user_invalidated) { - amdgpu_bo_placement_from_domain(e->bo, - AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, - &ctx); - if (r) - goto out_free_user_pages; - - amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, - e->range); - } - } - amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, &p->bytes_moved_vis_threshold); p->bytes_moved = 0; @@ -1092,8 +1101,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, return 0; -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED out_free_user_pages: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { amdgpu_hmm_range_free(e->range); e->range = NULL; @@ -1479,13 +1488,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (p->jobs[i] == leader) continue; - dma_resv_add_fence(gobj->resv, + dma_resv_add_fence(amdkcl_gem_resvp(gobj), &p->jobs[i]->base.s_fence->finished, DMA_RESV_USAGE_READ); } /* The gang leader as remembered as writer */ - dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE); + dma_resv_add_fence(amdkcl_gem_resvp(gobj), p->fence, DMA_RESV_USAGE_WRITE); } seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx], From 0960a26f357af0b3e88579da1c8a5e4d9ae19dc7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Sep 2023 17:12:58 +0800 Subject: [PATCH 1146/2070] drm/amdkcl: fake macro static_assert() It's caused by ff6320eb2b5616b4843588b066652837e6972666 "drm/amdgpu: add UMSCH 4.0 api definition" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_build_bug.h | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 include/kcl/kcl_build_bug.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a5a27b4857acc..dca3f2bd5f4c3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -109,4 +109,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_build_bug.h b/include/kcl/kcl_build_bug.h new file mode 100644 index 0000000000000..eb39ce95a8d7d --- /dev/null +++ b/include/kcl/kcl_build_bug.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LINUX_BUILD_BUG_H +#define AMDKCL_LINUX_BUILD_BUG_H + +#ifndef static_assert +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg) +#endif + +#endif /* AMDKCL_LINUX_BUILD_BUG_H */ \ No newline at end of file From f1f85cd309e240a1bbf7e808b5a815faed476105 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 15:43:50 +0800 Subject: [PATCH 1147/2070] drm/amdkcl: Test whether get_user_{pages/pages_remote}() wants {6/4} args It's caused by v6.4-rc4-55-gca5e863233e8 mm/gup: remove vmas parameter from get_user_pages_remote() v6.4-rc4-53-g54d020692b34 mm/gup: remove unused vmas parameter from get_user_pages() Signed-off-by: Asher Song --- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 17 +++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 19 ++++++++++++++++--- include/kcl/backport/kcl_mm_backport.h | 4 ++++ 3 files changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 index e2fe781b7d7dc..d538ceb02d6b2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -37,8 +37,21 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, [get_user_pages_remote() wants gup_flags parameter]) ],[ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, - [get_user_pages_remote() is introduced with initial prototype]) + dnl # + dnl # commit v6.4-rc4-55-gca5e863233e8 + dnl # mm/gup: remove vmas parameter from get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS, 1, + [get_user_pages_remote() remove argument vmas]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 index 7f9931fdf453f..8042f69a0228e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -24,7 +24,20 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ ], [get_user_pages], [mm/gup.c], [ AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, [get_user_pages() wants 6 args]) - ]) - ]) - ]) + ],[ + dnl # + dnl # commit v6.4-rc4-53-g54d020692b34 + dnl # mm/gup: remove unused vmas parameter from get_user_pages() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOVE_VMAS, 1, + [get_user_pages() remove vmas argument]) + ]) + ]) + ]) + ]) ]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 48312d64e5869..27c77cd60bbea 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -31,6 +31,8 @@ long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, #elif defined(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED) return get_user_pages_remote(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS) + return get_user_pages_remote(mm, start, nr_pages, gup_flags, pages, locked); #else return get_user_pages(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); @@ -46,6 +48,8 @@ long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, #if defined(HAVE_GET_USER_PAGES_6ARGS) return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOVE_VMAS) + return get_user_pages(start, nr_pages, gup_flags, pages); #else return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); From 2605ebe012464b22ac3eb0d28e1367594fe42eff Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 16:20:08 +0800 Subject: [PATCH 1148/2070] drm/amdkcl: Test struct drm_driver whether has member gem_prime_mmap It's caused by v6.4-rc2-425-g0adec22702d4 drm: Remove struct drm_driver.gem_prime_mmap Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b024977ba350b..7d00f796e51f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3203,7 +3203,9 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_vunmap = amdgpu_gem_prime_vunmap, #endif +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, @@ -3230,6 +3232,9 @@ const struct drm_driver amdgpu_partition_driver = { .release = &amdgpu_driver_release_kms, .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP + .gem_prime_mmap = drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 index 226e89eebe85c..80cba3a5a1459 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -16,3 +16,23 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ ]) ]) ]) +dnl # +dnl # commit 4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +dnl # commit v6.4-rc2-425-g0adec22702d4 +dnl # drm: Remove struct drm_driver.gem_prime_mmap +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_mmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_MMAP, 1, + [drm_driver->gem_prime_mmap() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d9fc3d1fbd968..7237adce01dd0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -191,6 +191,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 9830349fe59af0a4a6bd89d732198a3c3181ca39 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 27 Sep 2023 17:01:59 +0800 Subject: [PATCH 1149/2070] drm/amdkcl: assign to .prime_handle_to_fd and .prime_fd_to_handle of amdgpu_kms_driver It's caused by v6.4-rc7-1904-g71a7974ac701 drm/prime: Unexport helpers for fd/handle conversion Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7d00f796e51f9..3c3d1f4583df5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3179,6 +3179,11 @@ static struct drm_driver amdgpu_kms_driver = { #endif #endif +#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#endif + #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, #endif @@ -3231,6 +3236,10 @@ const struct drm_driver amdgpu_partition_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#endif .gem_prime_import = amdgpu_gem_prime_import, #ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index bae97886408be..5d14a0d6b877a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -14,3 +14,23 @@ AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ ]) ]) ]) + +dnl # +dnl # commit v3.3-9296-g3248877ea179 +dnl # drm: base prime/dma-buf support (v5) +dnl # +dnl # commit v6.4-rc7-1904-g71a7974ac701 +dnl # drm/prime: Unexport helpers for fd/handle conversion +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_fd(NULL, NULL, 0, 0, NULL); + ],[drm_gem_prime_handle_to_fd], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_FD, 1, + [drm_gem_prime_handle_to_fd() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7237adce01dd0..1d1e5b8d754bf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -192,6 +192,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From b8e96d48a11f74d049302b93ec2e746678b32cfb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Sep 2023 15:39:25 +0800 Subject: [PATCH 1150/2070] drm/amdkcl: Fix unsteady amdgpu dkms build against 4.x kernels The error "Argument list too long" occur on rhel8.*, So extend the previous workaround to fix the error. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/post-build.sh | 4 ++-- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh index 962903db89aca..59ccb1bf481e6 100755 --- a/drivers/gpu/drm/amd/dkms/post-build.sh +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -3,9 +3,9 @@ KERNELVER=$1 # -# Restore original kernel 5.x scripts/Makefile.build modified by post-add.sh +# Restore original kernel 5.x and Kernel 4.x scripts/Makefile.build modified by post-add.sh # -if [[ ${KERNELVER%%.*} -eq 5 ]]; then +if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then moddir="/lib/modules/$KERNELVER" mkfile="scripts/Makefile.build" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index cdbac6500036c..1eba510fa6eb1 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -60,10 +60,10 @@ done KERNELVER=$1 # -# Kernel 5.x scripts/Makefile.build patch +# Kernel 5.x and Kernel 4.x scripts/Makefile.build patch # The patch makes rules robust against "Argument list too long" error # -if [[ ${KERNELVER%%.*} -eq 5 ]]; then +if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then moddir="/lib/modules/$KERNELVER" mkfile="scripts/Makefile.build" @@ -80,7 +80,7 @@ if [[ ${KERNELVER%%.*} -eq 5 ]]; then sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ - -e "s/^[[:space:]]\+cmd_link_multi-m =.*$/"` + -e "s/^[[:space:]]*cmd_link_multi-m = \$(LD).*$/"` `"cmd_link_multi-m = \\\\\n"` `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` From f16e1acfd62a9f0ac1b2524d7fc1bdd8890730f7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 6 Sep 2023 11:15:25 +0800 Subject: [PATCH 1151/2070] drm/amdkcl: fix the missing build_bug.h and update config.h It's caused by ff6320eb2b5616b4843588b066652837e6972666 "drm/amdgpu: add UMSCH 4.0 api definition" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 ++++++- include/kcl/header/linux/build_bug.h | 9 +++++++++ include/kcl/kcl_build_bug.h | 2 ++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/linux/build_bug.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 55e3254002429..eb76847e912b2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -754,6 +754,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BUILD_BUG_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 557b1a1589e6d..a9a77d3a9cdf4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,7 +114,7 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-mapping: split dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) - + dnl #v4.5-rc3-203-g2413306c2566 dnl #apple-gmux: Add helper for presence detect dnl @@ -124,4 +124,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #device.h: move 'struct class' stuff out to device/class.h dnl AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) + + dnl #v4.12-10499-gbc6245e5efd7 + dnl #bug: split BUILD_BUG stuff out into + dnl + AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) ]) diff --git a/include/kcl/header/linux/build_bug.h b/include/kcl/header/linux/build_bug.h new file mode 100644 index 0000000000000..d97f9812224e1 --- /dev/null +++ b/include/kcl/header/linux/build_bug.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_BUG_BUILD_H_H +#define _KCL_HEADER_LINUX_BUG_BUILD_H_H + +#ifdef HAVE_LINUX_BUILD_BUG_H +#include_next +#endif + +#endif \ No newline at end of file diff --git a/include/kcl/kcl_build_bug.h b/include/kcl/kcl_build_bug.h index eb39ce95a8d7d..7abac2512a33d 100644 --- a/include/kcl/kcl_build_bug.h +++ b/include/kcl/kcl_build_bug.h @@ -2,6 +2,8 @@ #ifndef AMDKCL_LINUX_BUILD_BUG_H #define AMDKCL_LINUX_BUILD_BUG_H +#include + #ifndef static_assert #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) From 21f177c047196dccad41348b25877a810642b9e0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Sep 2023 12:30:39 +0800 Subject: [PATCH 1152/2070] drm/amdkcl: kcl cleanup macro PCI_IRQ_MSI It's caused by df9155c8fe089418a999d7c0d188897cb694645c "drm/amd: Fix the flag setting code for interrupt request" The macro is included for fixing build for centos7.4 3.10.0-693.el7.x86_64. The latest system is rhel7.9 with kernel 3.10, so clean up the KCL macro. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 2167d7856f782..3bd40fd9c49a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -371,11 +371,7 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev) free_irq(adev->irq.irq, adev_to_drm(adev)); adev->irq.installed = false; if (adev->irq.msi_enabled) -#ifdef PCI_IRQ_MSI pci_free_irq_vectors(adev->pdev); -#else - pci_disable_msi(adev->pdev); -#endif } amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); From 2b1449ffe2cf6b9dea8ce1c3086c96a64c788dac Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 11 Sep 2023 14:50:39 +0800 Subject: [PATCH 1153/2070] drm/amdkcl: fake drm_dp_read_dpcd_caps() It's caused by 58b80b00d4e27a08ea10a281b7e79a4553b70557 "drm/amd/display: Adjust the MST resume flow" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c | 118 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 | 16 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_drm_dp_helper_backport.h | 10 ++ 6 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ba35df4633674..edce7b2389ef2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_dp_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c new file mode 100644 index 0000000000000..c27581210a3d6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c @@ -0,0 +1,118 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include +#include + +#ifndef HAVE_DRM_DP_READ_DPCD_CAPS +static int _kcl_drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + /* + * Prior to DP1.3 the bit represented by + * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. + * If it is set DP_DPCD_REV at 0000h could be at a value less than + * the true capability of the panel. The only way to check is to + * then compare 0000h and 2200h. + */ + if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) + return 0; + + ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, + sizeof(dpcd_ext)); + if (ret < 0) + return ret; + if (ret != sizeof(dpcd_ext)) + return -EIO; + + if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { + drm_dbg_kms( + drm_dev, + "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", + aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); + return 0; + } + + if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) + return 0; + + drm_dbg_kms(drm_dev, "%s: Base DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); + + return 0; +} + +/** + * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if + * available + * @aux: DisplayPort AUX channel + * @dpcd: Buffer to store the resulting DPCD in + * + * Attempts to read the base DPCD caps for @aux. Additionally, this function + * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if + * present. + * + * Returns: %0 if the DPCD was read successfully, negative error code + * otherwise. + */ +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + + ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); + if (ret < 0) + return ret; + if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) + return -EIO; + + ret = _kcl_drm_dp_read_extended_dpcd_caps(aux, dpcd); + if (ret < 0) + return ret; + + drm_dbg_kms(drm_dev, "%s: DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + return ret; +} +EXPORT_SYMBOL(_kcl_drm_dp_read_dpcd_caps); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index eb76847e912b2..9e5b8f3b0b350 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -406,6 +406,9 @@ /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 +/* drm_dp_read_dpcd_caps() is available */ +#define HAVE_DRM_DP_READ_DPCD_CAPS 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 new file mode 100644 index 0000000000000..dbd64ba5dbbe8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.9-rc1-294-gb9936121d95b +dnl # drm/i915/dp: Extract drm_dp_read_dpcd_caps() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_read_dpcd_caps(NULL, NULL); + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, + [drm_dp_read_dpcd_caps() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1d1e5b8d754bf..3740a55fb204e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -164,6 +164,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DP_READ_DPCD_CAPS AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 4c541b78127d7..61b4a14bb0151 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -17,4 +17,14 @@ #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) #define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector #endif + +#if !defined(HAVE_DRM_DP_READ_DPCD_CAPS) +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]); +static inline int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return _kcl_drm_dp_read_dpcd_caps(aux, dpcd); +} +#endif #endif From 82a07bcc081ed422aa35e8bf77ddf935fdd82f9c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 14 Sep 2023 15:39:05 +0800 Subject: [PATCH 1154/2070] drm/amdkcl: fake drm_dp_add_payload_part{1,2}() It's caused by 7c5343f2a75336d865edea2d15f5f0234eaf8054 "drm/mst: Refactor the flow for payload allocation/removement" The function drm_dp_remove_payload() has been splited to two subfuctions, so add kcl macro bypass the new feature. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-remove-payload-part.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index a06053545e7e5..d1474ad1aa11a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -404,8 +404,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); target_payload = &old_payload; - +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); +#else + drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); +#endif } /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9e5b8f3b0b350..bd5149df5223f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -409,6 +409,9 @@ /* drm_dp_read_dpcd_caps() is available */ #define HAVE_DRM_DP_READ_DPCD_CAPS 1 +/* drm_dp_remove_payload_part{1,2}() is available */ +#define HAVE_DRM_DP_REMOVE_RAYLOAD_PART 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 new file mode 100644 index 0000000000000..10468731e64f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.3-5135-g7c5343f2a753 +dnl # "drm/mst: Refactor the flow for payload allocation/removement" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_remove_payload_part1(NULL, NULL, NULL); + ], [drm_dp_remove_payload_part1],[drivers/gpu/drm/display/drm_dp_mst_topology.c],[ + AC_DEFINE(HAVE_DRM_DP_REMOVE_RAYLOAD_PART, 1, + [drm_dp_remove_payload_part{1,2}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3740a55fb204e..837a05f2424b6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -165,6 +165,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DP_READ_DPCD_CAPS + AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB From 46277699851285588db21cccedd7492482d701c1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Sep 2023 15:24:23 +0800 Subject: [PATCH 1155/2070] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 402742b54302cbf0faf126cdf2c7c01265ffb586 "drm/amdgpu: add amdgpu mca debug sysfs support" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 3ca03b5e0f913..91d4819cd7f12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -613,8 +613,10 @@ static const struct file_operations mca_ue_dump_debug_fops = { .release = single_release, }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); #endif +#endif void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) { @@ -622,7 +624,9 @@ void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root if (!root) return; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); +#endif debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); #endif From 95b3fe19921468e956950c0939cc90954fbd230a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Sep 2023 13:39:35 +0800 Subject: [PATCH 1156/2070] drm/amdkcl: fix function return in HAVE_DMA_FENCE_CHAIN_ALLOC To support rhel9.3, add function return verify in M4 HAVE_DMA_FENCE_CHAIN_ALLOC Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 1627d69677f9e..f35b2f8d404ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - dma_fence_chain_alloc(); + struct dma_fence_chain *chain = NULL; + chain = dma_fence_chain_alloc(); ], [ AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, [dma_fence_chain_alloc() is available]) From 54f943832fe7d13f311f396b97729c9ade28706e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 25 Sep 2023 12:48:51 +0800 Subject: [PATCH 1157/2070] drm/amdkcl: fake drm_dbg_dp() It's caused by ec1e3bdbb037d7d4397cb8c14db801cc3b839860 "drm/amd/display: switch DC over to the new DRM logging macros" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 15abde9faeb53..c1aa05a71ff23 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -137,6 +137,11 @@ void kcl_drm_err(const char *format, ...); drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_dp) +#define drm_dbg_dp(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 2260ffbc1586476e6cc18d4e74c8e75e3248ff6c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 25 Sep 2023 12:50:14 +0800 Subject: [PATCH 1158/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_AUX_DRM_DEV and HAVE_KTIME_IS_UNION It's caused by ec1e3bdbb037d7d4397cb8c14db801cc3b839860 "drm/amd/display: switch DC over to the new DRM logging macros" the old macro DC_LOG_DC has been modified, so update DC_LOG_DC to DRM_DEBUG_KMS. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 23 ++++++++++++++----- 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 32ff5c48d4753..4e9bcda07c71d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -584,8 +584,8 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; -#ifndef HAVE_KTIME_IS_UNION struct drm_device *drm_dev; +#ifndef HAVE_KTIME_IS_UNION struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; #endif @@ -596,8 +596,8 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); -#ifndef HAVE_KTIME_IS_UNION drm_dev = acrtc->base.dev; +#ifndef HAVE_KTIME_IS_UNION vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index d1474ad1aa11a..3fe186cf8a549 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -907,8 +907,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, // read rc data drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); } - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "success = %d\n", success); +#else + DRM_DEBUG_KMS("%s: success = %d\n", __func__, success); +#endif return success; @@ -920,9 +923,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) { unsigned char data[16] = {0}; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Start\n"); - +#else + DRM_DEBUG_KMS("Start %s\n", __func__); +#endif // Step 2 data[0] = 'P'; data[1] = 'R'; @@ -978,8 +983,11 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) // Step 6 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) return; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Done\n"); +#else + DRM_DEBUG_KMS("Done %s\n", __func__); +#endif } /* MST Dock */ @@ -991,9 +999,12 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( bool enable) { uint8_t ret = 0; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); +#else + DRM_DEBUG_KMS("MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); +#endif if (enable) { /* When DSC is enabled on previous boot and reboot with the hub, @@ -1093,7 +1104,7 @@ bool dm_helpers_dp_write_dsc_enable( } #else ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); - DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); + DRM_DEBUG_KMS("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); #endif } From dcb526d5e7392a89cc4b311022a7cb4db8782564 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:03:46 +0800 Subject: [PATCH 1159/2070] drm/amdkcl: keep drm DPCD declarations for KCL It's caused by f53df85fbe6576ea111f11333ae3fbcd9d9220f3 "drm/amd/display: Remove unused DPCD declarations" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_dp.h | 67 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 include/kcl/kcl_drm_dp.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index dca3f2bd5f4c3..94842a545d3fc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -110,4 +110,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h new file mode 100644 index 0000000000000..1f277a16b5874 --- /dev/null +++ b/include/kcl/kcl_drm_dp.h @@ -0,0 +1,67 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_H +#define _KCL_DRM_DP_H + +#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS +#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 +#endif +#ifndef DP_FEC_CAPABILITY_1 +#define DP_FEC_CAPABILITY_1 0x091 +#endif + +#ifndef DP_DSC_CONFIGURATION +#define DP_DSC_CONFIGURATION 0x161 +#endif +#ifndef DP_PHY_SQUARE_PATTERN +#define DP_PHY_SQUARE_PATTERN 0x249 +#endif + +#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 +#endif +#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK +#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 +#endif +#ifndef DP_DSC_DECODER_COUNT_MASK +#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +#endif +#ifndef DP_DSC_DECODER_COUNT_SHIFT +#define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 +#endif +#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION +#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) +#endif + +#endif \ No newline at end of file From b2242d9c0687408956cc09b2b0321c3bdfed3fce Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:12:29 +0800 Subject: [PATCH 1160/2070] drm/amdkcl: test whether drm_connector_helper_funcs->prepare_writeback_job is available It's caused by 457ca82075a522bc5655d0abe363761d05ab2609 "drm/amd/display: Initialize writeback connector" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_connector_helper_funcs.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bd5149df5223f..ee6b2c374135b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -203,6 +203,9 @@ arg */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* drm_connector_helper_funcs->prepare_writeback_job is available */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB 1 + /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 new file mode 100644 index 0000000000000..fe75c0300c099 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc1-14-g9d2230dc1351 +dnl # drm: writeback: Add job prepare and cleanup operations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_helper_funcs *funcs; + funcs->prepare_writeback_job = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, + [drm_connector_helper_funcs->prepare_writeback_job is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 837a05f2424b6..75520ab7082d2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL From 9e12914cb1c19d1ac3fc75b445503bc1ad80e85f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:13:50 +0800 Subject: [PATCH 1161/2070] drm/amdkcl: test whether drm_writeback_connector_init() has 7 args It's caused by 457ca82075a522bc5655d0abe363761d05ab2609 "drm/amd/display: Initialize writeback connector" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++ .../dkms/m4/drm_writeback_connector_init.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_writeback.h | 31 +++++++++++++++++++ 5 files changed, 55 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 create mode 100644 include/kcl/kcl_drm_writeback.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 94842a545d3fc..2eb9d8cab56db 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -111,4 +111,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ee6b2c374135b..3a328ed1da076 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -640,6 +640,12 @@ /* drm_vblank->time uses ktime_t type */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 +/* struct drm_vma_offset_node has readonly field */ +/* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ + +/* drm_writeback_connector_init() has 7 args */ +#define HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS 1 + /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 new file mode 100644 index 0000000000000..7f2c208c36f96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.18-rc2-67-g57b8280a0a41 +dnl # drm: allow passing possible_crtcs to drm_writeback_connector_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_writeback_connector_init(NULL, NULL, NULL, NULL, NULL, 0, 0); + ],[drm_writeback_connector_init], [drivers/gpu/drm/drm_writeback.c],[ + AC_DEFINE(HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS, 1, + [drm_writeback_connector_init() has 7 args]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 75520ab7082d2..0fde15c2610bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT diff --git a/include/kcl/kcl_drm_writeback.h b/include/kcl/kcl_drm_writeback.h new file mode 100644 index 0000000000000..14b6d63f4b4b3 --- /dev/null +++ b/include/kcl/kcl_drm_writeback.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. + * Author: Brian Starkey + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + */ +#ifndef AMDKCL_DRM_WRITEBACK_H +#define AMDKCL_DRM_WRITEBACK_H + +#include + +#ifndef HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS +static inline int _kcl_drm_writeback_connector_init(struct drm_device *dev, + struct drm_writeback_connector *wb_connector, + const struct drm_connector_funcs *con_funcs, + const struct drm_encoder_helper_funcs *enc_helper_funcs, + const u32 *formats, int n_formats, + u32 possible_crtcs) +{ + wb_connector->encoder.possible_crtcs = possible_crtcs; + + return drm_writeback_connector_init(dev, wb_connector, con_funcs, enc_helper_funcs, formats, n_formats); +} +#define drm_writeback_connector_init _kcl_drm_writeback_connector_init +#endif + +#endif \ No newline at end of file From 8a311e27ecf33e34447e507a78e47f9247c3fbf2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:29:36 +0800 Subject: [PATCH 1162/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by ed5694767b668f36d80b2c986af8703ed9c51a5f "drm/amdgpu: add cached GPU fault structure to vm struct" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d722067b1412b..2f0000d101bb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3203,6 +3203,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ +#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3249,6 +3250,7 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, } xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); } +#endif /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 3e65e9a72750f..d672b3727e57b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -679,11 +679,14 @@ static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) mutex_unlock(&vm->eviction_lock); } +#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, uint32_t status, unsigned int vmhub); +#endif + void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 2568eeaae9454..2879e00ef3f55 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -135,9 +135,10 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); +#endif } if (!printk_ratelimit()) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 6349e239a3673..65600c411f7ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -132,9 +132,10 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); +#endif } if (printk_ratelimit()) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index b2e87d3aa2038..8cbf0202f36ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1275,10 +1275,10 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); - +#endif if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 086bf24f5db8f..278b4e6cdcd93 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1458,10 +1458,10 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); - +#endif if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); From d59477fa4ee8c8c712b4c92f6af8a691e77de5b7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:32:52 +0800 Subject: [PATCH 1163/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 2b332c97042ed499b7f04d2648736848c8f007a4 "drm/amdgpu: add new INFO ioctl query for the last GPU page fault" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 457d742e3d35a..42e54df22d984 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1406,6 +1406,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } +#ifdef HAVE_STRUCT_XARRAY case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1426,6 +1427,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } +#endif + case AMDGPU_INFO_UQ_FW_AREAS: { struct drm_amdgpu_info_uq_metadata meta_info = {}; From 89a15e24266cef4b24edd9c05dc8796b8853f1a1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:39:02 +0800 Subject: [PATCH 1164/2070] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 442a478469621f459834b27d5ac1c392bacd9c25 "drm/amdgpu: Add sysfs attribute to get board info" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 17b53b9fe6f82..92a5a80f70f45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -331,7 +331,7 @@ void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev) * - "unknown" - Not known * */ - +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static ssize_t amdgpu_device_get_board_info(struct device *dev, struct device_attribute *attr, char *buf) @@ -383,6 +383,7 @@ static const struct attribute_group amdgpu_board_attrs_group = { .attrs = amdgpu_board_attrs, .is_visible = amdgpu_board_attrs_is_visible }; +#endif /** * DOC: uma/carveout_options @@ -4333,10 +4334,12 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) if (r) dev_err(adev->dev, "Could not create amdgpu device attr\n"); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); if (r) dev_err(adev->dev, "Could not create amdgpu board attributes\n"); +#endif amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); From c926d4a5919c32732c541f3a64f00bf07958a7f1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 12 Oct 2023 11:01:39 +0800 Subject: [PATCH 1165/2070] drm/amdkcl: add return statements for KCL It's caused by 0da86105f4b82253e4521281aa377bd1a2c989b1 "drm/amdgpu: Drop unnecessary return statements" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 2bd00a0b27b3c..e7b65e7fc55c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -232,6 +232,8 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode /* Try registering an ACPI video backlight device instead. */ #ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#else + return; #endif } From 546243a029ffb9e1596a0b73ada67e07517be102 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 24 Oct 2023 14:03:17 +0800 Subject: [PATCH 1166/2070] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3a328ed1da076..07131e2456eb6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -253,12 +253,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_put() is available */ -#define HAVE_DRM_DEV_PUT 1 - -/* drm_dev_unplug() is available */ -#define HAVE_DRM_DEV_UNPLUG 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_H 1 @@ -418,9 +412,6 @@ /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 -/* drm_dp_start_crc() is available */ -#define HAVE_DRM_DP_START_CRC 1 - /* drm_dp_update_payload_part1() function has start_slot argument */ #define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 @@ -558,6 +549,9 @@ /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 +/* drm_gem_prime_handle_to_fd() is available */ +/* #undef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD */ + /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -655,9 +649,6 @@ /* fs_reclaim_acquire() is available */ #define HAVE_FS_RECLAIM_ACQUIRE 1 -/* drm_driver->gem_free_object_unlocked() is available */ -/* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ - /* generic_handle_domain_irq() is available */ #define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 @@ -946,12 +937,6 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 -/* drm_driver->set_busid is available */ -/* #undef HAVE_SET_BUSID_IN_STRUCT_DRM_DRIVER */ - -/* whether si_mem_available() is available */ -#define HAVE_SI_MEM_AVAILABLE 1 - /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ @@ -1024,9 +1009,6 @@ /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ -/* drm_pending_vblank_event->sequence is available */ -#define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 - /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 From 2dfce2a069b46ef2219f9e4de661634bb5722318 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 24 Oct 2023 16:42:09 +0800 Subject: [PATCH 1167/2070] drm/amdgpu: add missing null check for tbo.resource It's caused by 2e6dcc672567d7ffe913fac226ad1f4bd139e88e "drm/ttm: stop allocating dummy resources during BO creation" The latest ttm beable to handle the move without a resource, so some tbo.resource is null when bo release. Then add null pointer chec when adding AMDGPU_PL_DGMA support. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 39787e620297d..c5c67593327d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -175,10 +175,10 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } - if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) atomic64_sub(amdgpu_bo_size(aobj), &adev->direct_gma.vram_usage); - else if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + else if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) atomic64_sub(amdgpu_bo_size(aobj), &adev->direct_gma.gart_usage); From 298061b7d10590d5b1756a9accd83d3f4e968e4d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Oct 2023 14:44:27 +0800 Subject: [PATCH 1168/2070] drm/amdkcl: align M4 format Update some M4 to align the format. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- .../drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 | 16 +++++++++------- .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 16 +++++++++------- .../gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 18 ++++++++++-------- 3 files changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 index 5854aa864fd2e..cae3e54d7c7f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -3,12 +3,14 @@ dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e dnl # drm: allow limiting the scatter list size. dnl # AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_prime_pages_to_sg(NULL, NULL, 0); - ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, - [drm_prime_pages_to_sg() wants 3 arguments]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 index 7f8cf4e9ad0a1..837e690cc9c32 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -3,12 +3,14 @@ dnl # v5.6-rc2-359-g63170ac6f2e8 dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() dnl # AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_simple_encoder_init(NULL, NULL, 0); - ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ - AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, - [drm_simple_encoder is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 index ac2a78006ea2e..e3d33a862d7fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -3,13 +3,15 @@ dnl # dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again dnl # AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - enum mce_notifier_prios pri; - pri = MCE_PRIO_UC; - ], [ - AC_DEFINE(HAVE_MCE_PRIO_UC, 1, - [enum MCE_PRIO_UC is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) ]) ]) From 4db31d79b16b17780ebf83f8bb8c3c9a25d29472 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Oct 2023 14:45:50 +0800 Subject: [PATCH 1169/2070] drm/amdkcl: update prepare_writeback_job to limit param The latest HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB hasn't been defined, so update M4 to fix the issue and limit params. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 index fe75c0300c099..11f356754b2c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -7,8 +7,8 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - struct drm_connector_helper_funcs *funcs; - funcs->prepare_writeback_job = NULL; + struct drm_connector_helper_funcs *funcs = NULL; + funcs->prepare_writeback_job((struct drm_writeback_connector *)NULL, (struct drm_writeback_job *)NULL); ],[ AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, [drm_connector_helper_funcs->prepare_writeback_job is available]) From 968c6877d036b910a8dabf90dfc1df69c1176c2f Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Oct 2023 12:47:03 -0400 Subject: [PATCH 1170/2070] Shorten path to DKMS module build directory Make the build robust against too long argument error Change-Id: Ifb3f146f55d645bb1809f79751902690f937b096 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 8 +++--- drivers/gpu/drm/amd/dkms/post-build.sh | 23 ++------------- drivers/gpu/drm/amd/dkms/pre-build.sh | 39 ++++---------------------- 3 files changed, 11 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 78cc07704d491..6067de790980c 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,9 +1,9 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -PRE_BUILD="amd/dkms/pre-build.sh $kernelver" -POST_BUILD="amd/dkms/post-build.sh $kernelver" -POST_REMOVE="amd/dkms/post-build.sh $kernelver" +module_build_dir="$(mktemp -ut amd.XXXXXXXX)" +PRE_BUILD="amd/dkms/pre-build.sh $kernelver $dkms_tree $module $module_version $module_build_dir" +POST_BUILD="amd/dkms/post-build.sh $module_build_dir" # not all OS supports weak module updates NO_WEAK_MODULES="yes" @@ -41,4 +41,4 @@ DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ - M=$dkms_tree/$module/$module_version/build" + M=$module_build_dir" diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh index 59ccb1bf481e6..0c600db277937 100755 --- a/drivers/gpu/drm/amd/dkms/post-build.sh +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -1,23 +1,4 @@ #!/bin/bash -KERNELVER=$1 - -# -# Restore original kernel 5.x and Kernel 4.x scripts/Makefile.build modified by post-add.sh -# -if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then - moddir="/lib/modules/$KERNELVER" - mkfile="scripts/Makefile.build" - - if [[ -d "$moddir/source" ]]; then - mkfile="$moddir/source/$mkfile" - else - mkfile="$moddir/build/$mkfile" - fi - - mkfile=$(readlink -f $mkfile) - - if [[ -f "$mkfile~" ]]; then - mv -f $mkfile{~,} - fi -fi +MODULE_BUILD_DIR=$1 +rm -rf $MODULE_BUILD_DIR diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 1eba510fa6eb1..ca64bd8c9fc66 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -5,6 +5,10 @@ INC="include" SRC="amd/dkms" KERNELVER=$1 +DKMS_TREE=$2 +MODULE=$3 +MODULE_VERSION=$4 +MODULE_BUILD_DIR=$5 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -55,41 +59,8 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done -#!/bin/bash - -KERNELVER=$1 - -# -# Kernel 5.x and Kernel 4.x scripts/Makefile.build patch -# The patch makes rules robust against "Argument list too long" error -# -if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then - moddir="/lib/modules/$KERNELVER" - mkfile="scripts/Makefile.build" - - if [[ -d "$moddir/source" ]]; then - mkfile="$moddir/source/$mkfile" - else - mkfile="$moddir/build/$mkfile" - fi - - mkfile=$(readlink -e $mkfile) - - if [[ "$?" -eq 0 ]] && [[ ! -f "$mkfile~" ]]; then - cp -a ${mkfile}{,~} - sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` - `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` - `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ - -e "s/^[[:space:]]*cmd_link_multi-m = \$(LD).*$/"` - `"cmd_link_multi-m = \\\\\n"` - `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` - `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` - `"\trm -f \$@.in/" \ - $mkfile - fi -fi - export KERNELVER +ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From 0bf80706d17cc4a6acb46df49d7423f8641a273b Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 30 Oct 2023 22:20:57 -0400 Subject: [PATCH 1171/2070] Fix dkms driver build on Oracle Linux 8.x Change-Id: I953c377749fb2d7cec6dbb4b1bbf8211454cc19d Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/Makefile | 1 + drivers/gpu/drm/amd/dkms/dkms.conf | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a73a7f7227df2..0e41d5633a6f9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -179,6 +179,7 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -Wno-error ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 6067de790980c..1006d000952ed 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -38,7 +38,7 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ +MAKE[0]=". $module_build_dir/.env && make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$module_build_dir" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ca64bd8c9fc66..796020ae1570f 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -61,6 +61,18 @@ done export KERNELVER ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR + +# Enable gcc-toolset for kernels that are built with non-default compiler +if [[ -d /opt/rh ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + if strings /boot/vmlinuz-$KERNELVER | grep -q "$($f --version | head -1)"; then + . ${f%/*}/../../../enable + break + fi + done +fi +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From 370a2155bb0170b33beee741bd9ca2bb13255bd8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 2 Nov 2023 11:18:00 +0800 Subject: [PATCH 1172/2070] drm/amdkcl: fake dev_is_removable() repalce pci_is_thunderbolt_attached() It's caused by 99abe09a40d2c87d849a2cb1930c2792fc5e3396 "drm/amdgpu: don't use pci_is_thunderbolt_attached()" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_device.h | 9 +++++++++ 4 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 07131e2456eb6..e600bece2fd2a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -86,11 +86,8 @@ /* MEMORY_DEVICE_COHERENT is availablea */ #define HAVE_DEVICE_COHERENT 1 -/* devm_memremap_pages() wants struct dev_pagemap */ -#define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 - -/* devm_memremap_pages() wants p,p,p,p interface */ -/* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ +/* dev_is_removable() is available */ +#define HAVE_DEV_IS_REMOVABLE 1 /* dev_pagemap->owner is available */ #define HAVE_DEV_PAGEMAP_OWNER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 new file mode 100644 index 0000000000000..14ddb4989bbac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.13-rc2-70-g70f400d4d957 +dnl # driver core: Move the "removable" attribute from USB to core +dnl # +AC_DEFUN([AC_AMDGPU_DEV_IS_REMOVABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool res = 0; + res = dev_is_removable(NULL); + ], [ + AC_DEFINE(HAVE_DEV_IS_REMOVABLE, 1, + [dev_is_removable() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0fde15c2610bb..7f3e361387c96 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -131,6 +131,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DEV_IS_REMOVABLE AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index b2e3a9d24811b..4c5c92015651d 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -45,4 +45,13 @@ do { \ #define dev_err_ratelimited(dev, fmt, ...) \ dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__) #endif + +#ifndef HAVE_DEV_IS_REMOVABLE +static inline bool _kcl_dev_is_removable(struct device *dev) +{ + return false; +} +#define dev_is_removable _kcl_dev_is_removable +#endif + #endif /* AMDKCL_DEVICE_H */ From 4e84ffc27af10cf5fc48ac4055fd6edf26062702 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Nov 2023 15:38:40 +0800 Subject: [PATCH 1173/2070] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 0c0e51e78d7697be597eefb1e2dcbec3c3bf801d "drm/amdgpu: Attach eviction fence on alloc" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index ec2f366f12b95..1a61d8a2d4786 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -454,11 +454,11 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, if (ret) goto unreserve_out; - ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (ret) goto unreserve_out; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_BOOKKEEP); unreserve_out: From a4bd29daf00f3114d4cda2383d20c9087a7b5d36 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 3 Nov 2023 19:43:26 -0400 Subject: [PATCH 1174/2070] Fix dkms parrallel build 'dkms' has a bug and can't substitute 'make' command if it is not the first word in the command line. So, we restore -j option that used to be in dkms.conf before it was integrated into dkms. Change-Id: I39653f4bace4832bb110e3debcee89c51b106bf0 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 1006d000952ed..ceef7d15a7c26 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -38,7 +38,17 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -MAKE[0]=". $module_build_dir/.env && make TTM_NAME=${BUILT_MODULE_NAME[1]} \ +num_cpu_cores() +{ + if [ -x /usr/bin/nproc ]; then + nproc + else + echo "1" + fi +} + +MAKE[0]=". $module_build_dir/.env && make -j$(num_cpu_cores) KERNELRELEASE=$kernelver \ + TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$module_build_dir" From 7236e6f7f05e7f721b0a8a023f554172de5f2679 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Nov 2023 16:34:53 -0500 Subject: [PATCH 1175/2070] drm/amdkcl: fix DRM_DP_READ_DPCD_CAPS test Add another location to search for drm_dp_read_dpcd_caps exported symbol to cover older kernels. Change-Id: I216e6ffcb1f66947974acd0d4ef1b9477826852c Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 index dbd64ba5dbbe8..8306568c2e0ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -8,9 +8,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ #include ], [ drm_dp_read_dpcd_caps(NULL, NULL); - ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c], [ + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c drivers/gpu/drm/drm_dp_helper.c], [ AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, [drm_dp_read_dpcd_caps() is available]) ]) ]) -]) \ No newline at end of file +]) From d51fd59d13f339f960438078e6b1bf9d647b563a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Nov 2023 19:06:19 +0800 Subject: [PATCH 1176/2070] Revert "drm/amdgpu: fix AGP init order" The reverted patch cause a page fault error on navi32 when modprobe. Temporarily revert it. This reverts commit 00ee8d37fae64ce4e6d01bf83707e7e39d6a6398. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 -- 7 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b76457cb816c1..a472583cff495 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1093,6 +1093,9 @@ static const char * const amdgpu_vram_names[] = { */ int amdgpu_bo_init(struct amdgpu_device *adev) { + /* set the default AGP aperture state */ + amdgpu_gmc_set_agp_default(adev, &adev->gmc); + /* On A+A platform, VRAM can be mapped as WB */ if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { /* reserve PAT memory space to WC for VRAM */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 2879e00ef3f55..26485790cc03a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -658,7 +658,6 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 65600c411f7ef..b2312bc8de9d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -657,7 +657,6 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); if (!amdgpu_sriov_vf(adev) && diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 886bf77309a54..b4d597772f0b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -211,7 +211,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 8cbf0202f36ee..5b26005c497ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -242,7 +242,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 278b4e6cdcd93..357f5f3020200 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -417,7 +417,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e35ed0cc2ec62..5475507f0e07e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1636,8 +1636,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, { u64 base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); - /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; if (amdgpu_gmc_is_pdb0_enabled(adev)) { From 88d909ade1cf0360f5ce03a673fd1eb094407916 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 14 Nov 2023 13:36:34 +0800 Subject: [PATCH 1177/2070] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by f8340195642eae0367646d59fbc046a380ccce9e "drm/amd/display: add a debugfs interface for the DMUB trace mask" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7518f711161e4..d3dbd3911ad21 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3276,6 +3276,7 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val) return 0; } +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) /* check if kernel disallow eDP enter psr state * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr * 0: allow edp enter psr; 1: disallow @@ -3401,7 +3402,7 @@ static int dmub_trace_mask_show(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, dmub_trace_mask_set, "0x%llx\n"); - +#endif /* * Set dmcub trace event IRQ enable or disable. * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en From 354761102bc8cef5e34b9fad04cf6df26826d8e1 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 9 Nov 2023 13:08:13 +0530 Subject: [PATCH 1178/2070] drm/amdgpu: Skip execution of pending reset jobs cancel_work is not backported to all custom kernels. Add a workaround to skip execution of already queued recovery jobs, if the device is already reset. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 16 ++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 92a5a80f70f45..75858db0f1ed0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6202,6 +6202,8 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + amdgpu_reset_domain_clear_pending(adev->reset_domain); + #if defined(CONFIG_DEBUG_FS) if (!amdgpu_sriov_vf(adev)) cancel_work(&adev->reset_work); @@ -6237,6 +6239,9 @@ static void amdgpu_device_recovery_prepare(struct amdgpu_device *adev, { struct amdgpu_device *tmp_adev = NULL; + if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) + return 0; + /* * Build list of devices to reset. * In case we are in XGMI hive mode, resort the device list diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 28c4ad62f50e2..4c50530e7c327 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -271,6 +271,14 @@ void amdgpu_reset_destroy_reset_domain(struct kref *ref) kvfree(reset_domain); } +static void amdgpu_reset_domain_cancel_all_work(struct work_struct *work) +{ + struct amdgpu_reset_domain *reset_domain = + container_of(work, struct amdgpu_reset_domain, clear); + + reset_domain->drain = false; +} + struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, char *wq_name) { @@ -293,6 +301,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d } + INIT_WORK(&reset_domain->clear, amdgpu_reset_domain_cancel_all_work); atomic_set(&reset_domain->in_gpu_reset, 0); atomic_set(&reset_domain->reset_res, 0); init_rwsem(&reset_domain->sem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 07b4d37f1db69..fbf5e95dbd16e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -99,6 +99,8 @@ struct amdgpu_reset_domain { struct rw_semaphore sem; atomic_t in_gpu_reset; atomic_t reset_res; + struct work_struct clear; + bool drain; }; int amdgpu_reset_init(struct amdgpu_device *adev); @@ -137,6 +139,20 @@ static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *doma return queue_work(domain->wq, work); } +static inline void amdgpu_reset_domain_clear_pending(struct amdgpu_reset_domain *domain) +{ + domain->drain = true; + /* queue one more work to the domain queue. Till this work is finished, + * domain is in drain mode. + */ + queue_work(domain->wq, &domain->clear); +} + +static inline bool amdgpu_reset_domain_in_drain_mode(struct amdgpu_reset_domain *domain) +{ + return domain->drain; +} + static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain) { lockdep_assert_held(&domain->sem); From 3c69c1a0e34a4750e70ae882698e0baf3911392a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 23 Nov 2023 12:18:21 +0800 Subject: [PATCH 1179/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by 1b6d631dea0b57f564722f78c144ee621691d5be "drm/amd/display: adjust flow for deallocation mst payload" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Ma Jun Reviewed-by: Slava Abramov --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 3fe186cf8a549..0ac66c8fc0a15 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -555,9 +555,7 @@ void dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; -#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) int ret = 0; -#endif aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; @@ -596,9 +594,13 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; - struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_topology_mgr *mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *new_payload, old_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; @@ -608,15 +610,26 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); +#endif +#else + mst_port = aconnector->mst_output_port; + if (!mst_mgr->mst_state) + return; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); +#endif } void dm_dtn_log_begin(struct dc_context *ctx, From d217b765bbca636123bd55c19b6d0d6d6eae6bb1 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 24 Nov 2023 16:17:56 -0500 Subject: [PATCH 1180/2070] drm/amdkcl: compare only gcc version Compare only CONFIG_GCC_VERSION kernel build option with gcc version. "gcc --version" line embedded into the kernel binary could be different. For example the kernel 5.15 in Oracle 8 contains this version string: gcc (GCC) 11.2.1 20220127 (Red Hat 11.2.1-9.1.0.6) but gcc-toolset-11 prints gcc (GCC) 11.2.1 20220127 (Red Hat 11.2.1-9.2.0.1) Regardless the gcc versions are identical the compiler vendor portion is different. To avoid mismatching we compare only actual gcc version. SWDEV-427914 Change-Id: I7903db72f01b3880d9ce8514c6a841f573c241cd Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 796020ae1570f..5f922ec16986c 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -65,7 +65,11 @@ ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR # Enable gcc-toolset for kernels that are built with non-default compiler if [[ -d /opt/rh ]]; then for f in $(find /opt/rh -type f -a -name gcc); do - if strings /boot/vmlinuz-$KERNELVER | grep -q "$($f --version | head -1)"; then + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then . ${f%/*}/../../../enable break fi From 5f74c8a3e8887598d9759c101283dba690c84b7e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 30 Nov 2023 18:09:19 +0800 Subject: [PATCH 1181/2070] drm/amdkcl: fake dma_fence_timestamp Signed-off-by: Asher Song --- .../drm/amd/dkms/m4/dma-fence-timestamp.m4 | 17 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 21 +++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 new file mode 100644 index 0000000000000..8054979dd1b6a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.6-rc1-33-gb83ce9cb4a46 +dnl # dma-buf: add dma_fence_timestamp helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t time; + time = dma_fence_timestamp(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_TIMESTAMP, 1, [dma_fence_TIMESTAMP() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7f3e361387c96..f93e9a1054467 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -198,6 +198,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD + AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index 20a014352f967..ae63b65466e00 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -45,4 +45,25 @@ static inline bool dma_fence_is_container(struct dma_fence *fence) #endif /* HAVE_DMA_FENCE_IS_CONTAINER */ +#ifndef HAVE_DMA_FENCE_TIMESTAMP +/** + * dma_fence_timestamp - helper to get the completion timestamp of a fence + * @fence: fence to get the timestamp from. + * + * After a fence is signaled the timestamp is updated with the signaling time, + * but setting the timestamp can race with tasks waiting for the signaling. This + * helper busy waits for the correct timestamp to appear. + */ +static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) +{ + if (WARN_ON(!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) + return ktime_get(); + + while (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags)) + cpu_relax(); + + return fence->timestamp; +} +#endif + #endif From b7a22e45aec79554805ffbebfc4a29b0fe3439e3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 17:21:54 +0800 Subject: [PATCH 1182/2070] drm/amdkcl: test macro __counted_by whether is defined It's caused by v6.5-rc2-17-gc8248faf3ca2 Compiler Attributes: counted_by: Adjust name and identifier expansion Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 6 +++++- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++++ drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 6 +++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index ffbe106d1fbdc..f7fb857cc1fa7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -60,8 +60,12 @@ struct amdgpu_bo_list { /* Protect access during command submission. */ struct mutex bo_list_mutex; - +#ifdef __counted_by struct amdgpu_bo_list_entry entries[] __counted_by(num_entries); +#else + struct amdgpu_bo_list_entry entries[]; +#endif + }; int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 3dd6f009e1c62..9599c8247517d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -845,7 +845,11 @@ struct ip_hw_instance { u8 harvest; int num_base_addresses; +#ifdef __counted_by u32 base_addr[] __counted_by(num_base_addresses); +#else + u32 base_addr[]; +#endif }; struct ip_hw_id { diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h index 42adc2a3dcbc1..ec6cec793c25c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h @@ -192,7 +192,11 @@ struct smu10_clock_voltage_dependency_record { struct smu10_voltage_dependency_table { uint32_t count; - struct smu10_clock_voltage_dependency_record entries[] __counted_by(count); + struct smu10_clock_voltage_dependency_record entries[] +#ifdef __counted_by + __counted_by(count) +#endif + ; }; struct smu10_clock_voltage_information { From 2fb5fd9420edea45699b24c2c7bf121fb71cdad1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 20:03:38 +0800 Subject: [PATCH 1183/2070] drm/amdkcl:test whether shrinker_register exists It's caused by v6.6-rc4-53-gc42d50aefd17 mm: shrinker: add infrastructure for dynamically allocating shrinker Signed-off-by: Asher Song Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- .../gpu/drm/amd/dkms/m4/register_shrinker.m4 | 22 +++++++++++++++ drivers/gpu/drm/ttm/ttm_pool.c | 28 +++++++++++++++++-- include/kcl/kcl_shrinker.h | 2 ++ 4 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f93e9a1054467..23d4da7352e5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -173,7 +173,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 - AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 index 903f100bf18bd..98c49b53ddc6f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -17,3 +17,25 @@ AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ ]) ]) ]) + +dnl # +dnl # commit: v6.6-rc4-53-gc42d50aefd17 +dnl # mm: shrinker: add infrastructure for dynamically allocating shrinker +dnl # +AC_DEFUN([AC_AMDGPU_SHRINKER_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shrinker_register(NULL); + ], [shrinker_register], [mm/shrinker.c], [ + AC_DEFINE(HAVE_SHRINKER_REGISTER, 1, + [shrinker_register() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_SHRINKER], [ + AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER_REGISTER +]) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index cdad09312a59b..a4fa19994162e 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -129,7 +129,12 @@ static struct ttm_pool_type global_dma32_uncached[NR_PAGE_ORDERS]; static spinlock_t shrinker_lock; static struct list_head shrinker_list; -static struct shrinker *mm_shrinker; +static struct shrinker +#ifdef HAVE_SHRINKER_REGISTER +*mm_shrinker; +#else +mm_shrinker; +#endif static DECLARE_RWSEM(pool_shrink_rwsem); /* Allocate pages of size 1 << order with the given gfp_flags */ @@ -1293,9 +1298,17 @@ static int ttm_pool_debugfs_shrink_show(struct seq_file *m, void *data) unsigned long count; fs_reclaim_acquire(GFP_KERNEL); + +#ifdef HAVE_SHRINKER_REGISTER count = ttm_pool_shrinker_count(mm_shrinker, &sc); seq_printf(m, "%lu/%lu\n", count, ttm_pool_shrinker_scan(mm_shrinker, &sc)); +#else + count = ttm_pool_shrinker_count(&mm_shrinker, &sc); + seq_printf(m, "%lu/%lu\n", count, + ttm_pool_shrinker_scan(&mm_shrinker, &sc)); +#endif + fs_reclaim_release(GFP_KERNEL); return 0; @@ -1343,6 +1356,7 @@ int ttm_pool_mgr_init(unsigned long num_pages) #endif #endif +#ifdef HAVE_SHRINKER_REGISTER mm_shrinker = shrinker_alloc(0, "drm-ttm_pool"); if (!mm_shrinker) return -ENOMEM; @@ -1353,8 +1367,14 @@ int ttm_pool_mgr_init(unsigned long num_pages) mm_shrinker->seeks = 1; shrinker_register(mm_shrinker); - return 0; +#else + mm_shrinker.count_objects = ttm_pool_shrinker_count; + mm_shrinker.scan_objects = ttm_pool_shrinker_scan; + mm_shrinker.seeks = 1; + + return kcl_register_shrinker(&mm_shrinker, "drm-ttm_pool"); +#endif } /** @@ -1374,6 +1394,10 @@ void ttm_pool_mgr_fini(void) ttm_pool_type_fini(&global_dma32_uncached[i]); } +#ifdef HAVE_SHRINKER_REGISTER shrinker_free(mm_shrinker); +#else + unregister_shrinker(&mm_shrinker); +#endif WARN_ON(!list_empty(&shrinker_list)); } diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index c237de4b867cf..ca93cd0197f9f 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -7,6 +7,7 @@ extern void synchronize_shrinkers(void); #endif +#ifndef HAVE_SHRINKER_REGISTER static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker, const char *fmt, ...) { @@ -16,5 +17,6 @@ static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker return register_shrinker(shrinker); #endif } +#endif #endif From 02a9af5a4a24189a5fc85c7e4dc1f7c0a470752c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 6 Dec 2023 13:29:14 +0800 Subject: [PATCH 1184/2070] drm/amdkcl: fake pci_get_base_class It's caused by v6.6-rc1-1-gd427da2323b0 PCI: Add pci_get_base_class() helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 57 +++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 | 22 +++++++++ include/kcl/kcl_pci.h | 10 ++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index c62f0a2f9d6e9..742ba33ab1884 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -249,3 +249,60 @@ u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); #endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ #endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ + +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_GET_BASE_CLASS +static inline const struct pci_device_id * +pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) +{ + if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && + (id->device == PCI_ANY_ID || id->device == dev->device) && + (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && + (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && + !((id->class ^ dev->class) & id->class_mask)) + return id; + return NULL; +} + +static int match_pci_dev_by_id(struct device *dev, const void *data) +{ + struct pci_dev *pdev = to_pci_dev(dev); + const struct pci_device_id *id = data; + + if (pci_match_one_device(id, pdev)) + return 1; + return 0; +} + +static struct pci_dev *pci_get_dev_by_id(const struct pci_device_id *id, + struct pci_dev *from) +{ + struct device *dev; + struct device *dev_start = NULL; + struct pci_dev *pdev = NULL; + + if (from) + dev_start = &from->dev; + dev = bus_find_device(&pci_bus_type, dev_start, (void *)id, + match_pci_dev_by_id); + if (dev) + pdev = to_pci_dev(dev); + pci_dev_put(from); + return pdev; +} + +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from) +{ + struct pci_device_id id = { + .vendor = PCI_ANY_ID, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .class_mask = 0xFF0000, + .class = class << 16, + }; + + return pci_get_dev_by_id(&id, from); +} +EXPORT_SYMBOL(pci_get_base_class); +#endif /*HAVE_PCI_GET_BASE_CLASS*/ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 23d4da7352e5a..131718b7eea03 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -20,7 +20,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS - AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_ZONE_MANAGED_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 index 29c0928f6bd40..0138c0b995d3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -14,3 +14,25 @@ AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ ]) ]) ]) + +dnl # +dnl # commit: v6.6-rc1-1-gd427da2323b0 +dnl # PCI: Add pci_get_base_class() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_GET_BASE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pci_get_base_class(0, NULL); + ], [pci_get_base_class], [drivers/pci/search.c], [ + AC_DEFINE(HAVE_PCI_GET_BASE_CLASS, 1, + [pci_get_base_class() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_PCI], [ + AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_GET_BASE_CLASS +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 11d939a6168e2..0fd605cf81fef 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -194,4 +194,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ +/* Copied from include/linux/pci.h */ +#ifndef HAVE_PCI_GET_BASE_CLASS +#ifdef CONFIG_PCI +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); +#else /*CONFIG_PCI*/ +static inline struct pci_dev *pci_get_base_class(unsigned int class, + struct pci_dev *from) +{ return NULL; } +#endif /*CONFIG_PCI*/ +#endif /*HAVE_PCI_GET_BASE_CLASS*/ #endif /* AMDKCL_PCI_H */ From 8409c69c0a43f1b5bbbbf137ebbcbe2a9e5e497b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 21:26:06 +0800 Subject: [PATCH 1185/2070] drm/amdkcl:fake vma_is_init_{heap, stack} It's caused by v6.5-rc4-265-g11250fd12eb8 mm: factor out VMA stack and heap checks Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 19 +++++++++++++++ include/kcl/kcl_mm.h | 28 +++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 131718b7eea03..81eb88ccd2fbc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP + AC_AMDGPU_VMA_IS_INITIAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 index 74cd3b8edd7ce..537ee8180393a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -32,3 +32,22 @@ AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ ]) ]) ]) + +dnl # +dnl # v6.5-rc4-265-g11250fd12eb8 +dnl # mm: factor out VMA stack and heap checks +dnl # +AC_DEFUN([AC_AMDGPU_VMA_IS_INITIAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_is_initial_heap(NULL); + vma_is_initial_stack(NULL); + ], [ + AC_DEFINE(HAVE_VMA_IS_INITIAL_HEAP, 1, + [vma_is_initial_{heap, stack} is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 994d6e41b429b..848e47a2c3d39 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -127,4 +127,32 @@ static inline unsigned long _kcl_totalram_pages(void) #define totalram_pages _kcl_totalram_pages #endif /* HAVE_TOTALRAM_PAGES */ +/*copy from include/linux/mm.h */ +#ifndef HAVE_VMA_IS_INITIAL_HEAP +/* + * Indicate if the VMA is a heap for the given task; for + * /proc/PID/maps that is the heap of the main task. + */ +static inline bool vma_is_initial_heap(const struct vm_area_struct *vma) +{ + return vma->vm_start <= vma->vm_mm->brk && + vma->vm_end >= vma->vm_mm->start_brk; +} + +/* + * Indicate if the VMA is a stack for the given task; for + * /proc/PID/maps that is the stack of the main task. + */ +static inline bool vma_is_initial_stack(const struct vm_area_struct *vma) +{ + /* + * We make no effort to guess what a given thread considers to be + * its "stack". It's not even well-defined for programs written + * languages like Go. + */ + return vma->vm_start <= vma->vm_mm->start_stack && + vma->vm_end >= vma->vm_mm->start_stack; +} +#endif + #endif /* AMDKCL_MM_H */ From d24e0cd2ef68779d3052660112e7c7b717f6e89b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 21:26:57 +0800 Subject: [PATCH 1186/2070] drm/amdkcl: test struct x86 whether has member topo Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/processor.m4 | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/processor.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3dcfe7bbd8505..45436e45276ac 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2425,7 +2425,11 @@ static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask) if (first_cpu_of_numa_node >= nr_cpu_ids) return -1; #ifdef CONFIG_X86_64 +#ifdef HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT return cpu_data(first_cpu_of_numa_node).topo.apicid; +#else + return cpu_data(first_cpu_of_numa_node).apicid; +#endif #else return first_cpu_of_numa_node; #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 81eb88ccd2fbc..26212b3dc93d8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -200,6 +200,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_AMDGPU_VMA_IS_INITIAL + AC_AMDGPU_CPUINFO_X86 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/processor.m4 b/drivers/gpu/drm/amd/dkms/m4/processor.m4 new file mode 100644 index 0000000000000..66dececcd8989 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/processor.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.6-rc1-4-gb9655e702dc5 +dnl # x86/cpu: Encapsulate topology information in cpuinfo_x86 +dnl # +AC_DEFUN([AC_AMDGPU_CPUINFO_X86], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct cpuinfo_x86* cpuinfo = NULL; + struct cpuinfo_topology topo; + topo = cpuinfo -> topo; + ],[ + AC_DEFINE(HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT, 1, + [ cpuinfo_x86.topo is available]) + ]) + ]) +]) From 24e979c5c8bb2f5deb97abe05205d3b7d1905b17 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 6 Dec 2023 17:53:42 +0800 Subject: [PATCH 1187/2070] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 32 ++++++++++++++++-------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e600bece2fd2a..9ee764aefff45 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -32,6 +32,12 @@ /* *FLAGS_.o support to take the path relative to $(obj) */ #define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 +/* hmm support is enabled */ +#define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 + +/* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ +/* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ + /* amd_iommu_pc_get_max_banks() declared */ #define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 @@ -77,6 +83,9 @@ /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 +/* cpuinfo_x86.topo is available */ +#define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 + /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 @@ -119,11 +128,8 @@ /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 -/* dma_fence_set_error() is available */ -#define HAVE_DMA_FENCE_SET_ERROR 1 - -/* dma_map_resource() is enabled */ -#define HAVE_DMA_MAP_RESOURCE 1 +/* dma_fence_TIMESTAMP() is available */ +#define HAVE_DMA_FENCE_TIMESTAMP 1 /* dma_map_sgtable() is enabled */ #define HAVE_DMA_MAP_SGTABLE 1 @@ -886,8 +892,8 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 -/* pci_is_thunderbolt_attached() is available */ -#define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 +/* pci_get_base_class() is available */ +#define HAVE_PCI_GET_BASE_CLASS 1 /* pci_pr3_present() is available */ #define HAVE_PCI_PR3_PRESENT 1 @@ -917,7 +923,7 @@ #define HAVE_PXM_TO_NODE 1 /* whether register_shrinker(x, x) is available */ -#define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 +/* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ /* remove_conflicting_pci_framebuffers() is available */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ @@ -934,6 +940,9 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 +/* shrinker_register() is available */ +#define HAVE_SHRINKER_REGISTER 1 + /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ @@ -1032,7 +1041,7 @@ #define HAVE_STR_YES_NO 1 /* synchronize_shrinkers() is available */ -#define HAVE_SYNCHRONIZE_SHRINKERS 1 +/* #undef HAVE_SYNCHRONIZE_SHRINKERS */ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 @@ -1052,6 +1061,9 @@ /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ +/* vma_is_initial_{heap, stack} is available */ +#define HAVE_VMA_IS_INITIAL_HEAP 1 + /* vma_lookup() is available */ #define HAVE_VMA_LOOKUP 1 @@ -1122,7 +1134,7 @@ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 /* __kthread_should_park() is available */ -#define HAVE___KTHREAD_SHOULD_PARK 1 +/* #undef HAVE___KTHREAD_SHOULD_PARK */ /* __print_array is available */ #define HAVE___PRINT_ARRAY 1 From a426b7e186d9e664096534482219bfdc870bbd3b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 7 Dec 2023 17:25:32 +0800 Subject: [PATCH 1188/2070] drm/amdkcl: fake dma_fence_is_later_or_same It's caused by v6.7-rc1-17-g95ba893c9f4f dma-buf: fix check in dma_resv_add_fence Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index bbc3eb8117f9c..0523264d08807 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -28,3 +28,19 @@ AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ ]) ]) ]) + +dnl # +dnl # v6.7-rc1-17-g95ba893c9f4f +dnl # dma-buf: fix check in dma_resv_add_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_later_or_same(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_LATER_OR_SAME, 1, [dma_fence_is_later_or_same() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 26212b3dc93d8..ccd288dc2c914 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -201,6 +201,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_AMDGPU_VMA_IS_INITIAL AC_AMDGPU_CPUINFO_X86 + AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index ae63b65466e00..a24278c214244 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -66,4 +66,12 @@ static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) } #endif +/* copy from include/linux/dma-fence.h*/ +#ifndef HAVE_DMA_FENCE_IS_LATER_OR_SAME +static inline bool dma_fence_is_later_or_same(struct dma_fence *f1, + struct dma_fence *f2) +{ + return f1 == f2 || dma_fence_is_later(f1, f2); +} +#endif /*HAVE_DMA_FENCE_IS_LATER_OR_SAME*/ #endif From f567aa948be732652abeba8ce779f11334414a09 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 5 Dec 2023 15:23:43 +0800 Subject: [PATCH 1189/2070] drm/amdkcl: tset whether list_cmp_func is const param It's caused by 93de84df60bc71c5f0d95de84a71eb119b51afe1 "drm/amdgpu: optimize the printing order of error data" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/list-sort.m4 | 18 ++++++++++++++++++ 4 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-sort.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a1b40c9b51aa1..2c5d80d04c2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -5407,7 +5407,11 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void) return err_node; } +#ifdef HAVE_LIST_CMP_FUNC_IS_CONST_PARAM static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) +#else +static int ras_err_info_cmp(void *priv, struct list_head *a, struct list_head *b) +#endif { struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9ee764aefff45..834a96917d020 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -829,8 +829,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_XARRAY_H 1 -/* list_bulk_move_tail() is available */ -#define HAVE_LIST_BULK_MOVE_TAIL 1 +/* list_cmp_func() is const param */ +#define HAVE_LIST_CMP_FUNC_IS_CONST_PARAM 1 /* list_is_first() is available */ #define HAVE_LIST_IS_FIRST 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ccd288dc2c914..a24f94100f0f2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -191,6 +191,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG diff --git a/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 new file mode 100644 index 0000000000000..aa7b739d04961 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc6-9-g4f0f586bf0c8 +dnl # treewide: Change list_sort to use const pointers +dnl # +AC_DEFUN([AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_cmp_func_t cmp = NULL; + struct list_head a, b; + cmp(NULL, &a, &b); + ], [ + AC_DEFINE(HAVE_LIST_CMP_FUNC_IS_CONST_PARAM, 1, + [list_cmp_func() is const param]) + ]) + ]) +]) \ No newline at end of file From 9fff3eabbfea48f5059e77e602a1cfb81ab463db Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 21 Nov 2023 16:47:57 +0800 Subject: [PATCH 1190/2070] drm/amdkcl: fix issue of missing mca-debug-mode debugfs node v1: fix issue of missing mca-debug-mode debugfs node. v2: using helper macro DEFINE_SIMPLE_ATTRIBUTE to simple code Fixes: 96e2072e93c0 ("drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE") Signed-off-by: Yang Wang Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 91d4819cd7f12..78a89601e4e5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -615,6 +615,8 @@ static const struct file_operations mca_ue_dump_debug_fops = { #ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); #endif #endif @@ -624,9 +626,7 @@ void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root if (!root) return; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); -#endif debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); #endif From 848acd1ba4c048775799f58243673e4dddf6ffd9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 4 Dec 2023 15:54:47 +0800 Subject: [PATCH 1191/2070] drm/amdkcl: reduce argunemts of kgd2kfd_resume To aliagn with kgd2kfd_resume prototype, reduce arguments of dummy kgd2kfd_resume. Signed-off-by: Asher Song Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 53255cdebf282..7701f3616faa7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -545,7 +545,7 @@ static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) { return 0; } From 1daa3cb39774eea17a617339b99d7122bde1d943 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 13:46:52 +0800 Subject: [PATCH 1192/2070] drm/amdkcl: update config.h It's caused by 9a893b4afa61a72b3a81dd334c210fdb4ca93154 Revert "drm/prime: Unexport helpers for fd/handle conversion" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 834a96917d020..49bf3dad7237a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -553,7 +553,7 @@ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 /* drm_gem_prime_handle_to_fd() is available */ -/* #undef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 From 00613aae74fb9fb9e4f36971b4fef64d156c348a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 11:13:44 +0800 Subject: [PATCH 1193/2070] drm/amdkcl: fake drm_client_register() It's caused by 6a56a446d0dfd620c451772f742c20dafa9fe83b "drm/amdkfd: Export DMABufs from KFD using GEM handles" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_client_register.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_client.h | 14 ++++++++++++++ 5 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 create mode 100644 include/kcl/kcl_drm_client.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2eb9d8cab56db..e2777f4894a71 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -112,4 +112,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 49bf3dad7237a..ae3bf61f5d415 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -183,6 +183,9 @@ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 +/* drm_client_register() is available */ +#define HAVE_DRM_CLIENT_REGISTER 1 + /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 new file mode 100644 index 0000000000000..ef060260bee20 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.1-rc2-1103-ge33898a20744 +dnl # drm/client: Rename drm_client_add() to drm_client_register() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_client_register(NULL); + ],[ + AC_DEFINE(HAVE_DRM_CLIENT_REGISTER, 1, + [drm_client_register() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a24f94100f0f2..c64b92a38bf38 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -197,6 +197,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP diff --git a/include/kcl/kcl_drm_client.h b/include/kcl/kcl_drm_client.h new file mode 100644 index 0000000000000..0857e2fc2cd65 --- /dev/null +++ b/include/kcl/kcl_drm_client.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_CLIENT_H +#define KCL_KCL_DRM_CLIENT_H + +#include + +#ifndef HAVE_DRM_CLIENT_REGISTER +static inline void drm_client_register(struct drm_client_dev *client) +{ + drm_client_add(client); +} +#endif /* HAVE_DRM_CLIENT_REGISTER */ + +#endif From 5445fa6e016d401d83464a9e9c50ab17640e0042 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Dec 2023 10:57:13 +0800 Subject: [PATCH 1194/2070] drm/amdkcl: fake drm_dbg_driver() It's casued by eb826a227c7d72fecb1b40d49d1d6ec611fa4219 "drm/amd/display: add plane shaper LUT support" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c1aa05a71ff23..e2855aa2a299d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -142,6 +142,11 @@ void kcl_drm_err(const char *format, ...); drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_driver) +#define drm_dbg_driver(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From b3bc72d1db570713080ec313671910bf2c3567f9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 18:54:39 +0800 Subject: [PATCH 1195/2070] drm/amdkcl: check whether acpi_amd_wbrf.h exist It's caused by v6.7-rc1-2-g58e82a62669d platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c | 319 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 + include/kcl/header/linux/acpi_amd_wbrf.h | 9 + include/kcl/kcl_acpi_amd_wbrf.h | 94 ++++++ 6 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c create mode 100644 include/kcl/header/linux/acpi_amd_wbrf.h create mode 100644 include/kcl/kcl_acpi_amd_wbrf.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index edce7b2389ef2..4150605156bba 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -20,7 +20,7 @@ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o - +amdkcl-$(CONFIG_AMD_WBRF) += kcl_wbrf.o CFLAGS_kcl_fence.o := -I$(src) ccflags-y += \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c new file mode 100644 index 0000000000000..3299b4e78c7a7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c @@ -0,0 +1,319 @@ +//SPDX-License-Identifier: GPL-2.0 +/* + * Wifi Frequency Band Manage Interface + * Copyright (C) 2023 Advanced Micro Devices + */ + +#include +#include + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +/* + * Functions bit vector for WBRF method + * + * Bit 0: WBRF supported. + * Bit 1: Function 1 (Add / Remove frequency) is supported. + * Bit 2: Function 2 (Get frequency list) is supported. + */ +#define WBRF_ENABLED 0x0 +#define WBRF_RECORD 0x1 +#define WBRF_RETRIEVE 0x2 + +#define WBRF_REVISION 0x1 + +/* + * The data structure used for WBRF_RETRIEVE is not naturally aligned. + * And unfortunately the design has been settled down. + */ +struct amd_wbrf_ranges_out { + u32 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +} __packed; + +static const guid_t wifi_acpi_dsm_guid = + GUID_INIT(0x7b7656cf, 0xdc3d, 0x4c1c, + 0x83, 0xe9, 0x66, 0xe7, 0x21, 0xde, 0x30, 0x70); + +/* + * Used to notify consumer (amdgpu driver currently) about + * the wifi frequency is change. + */ +static BLOCKING_NOTIFIER_HEAD(wbrf_chain_head); + +static int wbrf_record(struct acpi_device *adev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + union acpi_object argv4; + union acpi_object *tmp; + union acpi_object *obj; + u32 num_of_ranges = 0; + u32 num_of_elements; + u32 arg_idx = 0; + int ret; + u32 i; + + if (!in) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (in->band_list[i].start && in->band_list[i].end) + num_of_ranges++; + } + + /* + * The num_of_ranges value in the "in" object supplied by + * the caller is required to be equal to the number of + * entries in the band_list array in there. + */ + if (num_of_ranges != in->num_of_ranges) + return -EINVAL; + + /* + * Every input frequency band comes with two end points(start/end) + * and each is accounted as an element. Meanwhile the range count + * and action type are accounted as an element each. + * So, the total element count = 2 * num_of_ranges + 1 + 1. + */ + num_of_elements = 2 * num_of_ranges + 2; + + tmp = kcalloc(num_of_elements, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + argv4.package.type = ACPI_TYPE_PACKAGE; + argv4.package.count = num_of_elements; + argv4.package.elements = tmp; + + /* save the number of ranges*/ + tmp[0].integer.type = ACPI_TYPE_INTEGER; + tmp[0].integer.value = num_of_ranges; + + /* save the action(WBRF_RECORD_ADD/REMOVE/RETRIEVE) */ + tmp[1].integer.type = ACPI_TYPE_INTEGER; + tmp[1].integer.value = action; + + arg_idx = 2; + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (!in->band_list[i].start || !in->band_list[i].end) + continue; + + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].start; + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].end; + } + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RECORD, &argv4); + + if (!obj) + return -EINVAL; + + if (obj->type != ACPI_TYPE_INTEGER) { + ret = -EINVAL; + goto out; + } + + ret = obj->integer.value; + if (ret) + ret = -EINVAL; + +out: + ACPI_FREE(obj); + kfree(tmp); + + return ret; +} + +/** + * acpi_amd_wbrf_add_remove - add or remove the frequency band the device is using + * + * @dev: device pointer + * @action: remove or add the frequency band into bios + * @in: input structure containing the frequency band the device is using + * + * Broadcast to other consumers the frequency band the device starts + * to use. Underneath the surface the information is cached into an + * internal buffer first. Then a notification is sent to all those + * registered consumers. So then they can retrieve that buffer to + * know the latest active frequency bands. Consumers that haven't + * yet been registered can retrieve the information from the cache + * when they register. + * + * Return: + * 0 for success add/remove wifi frequency band. + * Returns a negative error code for failure. + */ +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + struct acpi_device *adev; + int ret; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + ret = wbrf_record(adev, action, in); + if (ret) + return ret; + + blocking_notifier_call_chain(&wbrf_chain_head, WBRF_CHANGED, NULL); + + return 0; +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_add_remove); + +/** + * acpi_amd_wbrf_supported_producer - determine if the WBRF can be enabled + * for the device as a producer + * + * @dev: device pointer + * + * Check if the platform equipped with necessary implementations to + * support WBRF for the device as a producer. + * + * Return: + * true if WBRF is supported, otherwise returns false + */ +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RECORD)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_producer); + +/** + * acpi_amd_wbrf_supported_consumer - determine if the WBRF can be enabled + * for the device as a consumer + * + * @dev: device pointer + * + * Determine if the platform equipped with necessary implementations to + * support WBRF for the device as a consumer. + * + * Return: + * true if WBRF is supported, otherwise returns false. + */ +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RETRIEVE)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_consumer); + +/** + * amd_wbrf_retrieve_freq_band - retrieve current active frequency bands + * + * @dev: device pointer + * @out: output structure containing all the active frequency bands + * + * Retrieve the current active frequency bands which were broadcasted + * by other producers. The consumer who calls this API should take + * proper actions if any of the frequency band may cause RFI with its + * own frequency band used. + * + * Return: + * 0 for getting wifi freq band successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + struct amd_wbrf_ranges_out acpi_out = {0}; + struct acpi_device *adev; + union acpi_object *obj; + union acpi_object param; + int ret = 0; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + param.type = ACPI_TYPE_STRING; + param.string.length = 0; + param.string.pointer = NULL; + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RETRIEVE, ¶m); + if (!obj) + return -EINVAL; + + /* + * The return buffer is with variable length and the format below: + * number_of_entries(1 DWORD): Number of entries + * start_freq of 1st entry(1 QWORD): Start frequency of the 1st entry + * end_freq of 1st entry(1 QWORD): End frequency of the 1st entry + * ... + * ... + * start_freq of the last entry(1 QWORD) + * end_freq of the last entry(1 QWORD) + * + * Thus the buffer length is determined by the number of entries. + * - For zero entry scenario, the buffer length will be 4 bytes. + * - For one entry scenario, the buffer length will be 20 bytes. + */ + if (obj->buffer.length > sizeof(acpi_out) || obj->buffer.length < 4) { + dev_err(dev, "Wrong sized WBRT information"); + ret = -EINVAL; + goto out; + } + memcpy(&acpi_out, obj->buffer.pointer, obj->buffer.length); + + out->num_of_ranges = acpi_out.num_of_ranges; + memcpy(out->band_list, acpi_out.band_list, sizeof(acpi_out.band_list)); + +out: + ACPI_FREE(obj); + return ret; +} +EXPORT_SYMBOL_GPL(amd_wbrf_retrieve_freq_band); + +/** + * amd_wbrf_register_notifier - register for notifications of frequency + * band update + * + * @nb: driver notifier block + * + * The consumer should register itself via this API so that it can get + * notified on the frequency band updates from other producers. + * + * Return: + * 0 for registering a consumer driver successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_register_notifier); + +/** + * amd_wbrf_unregister_notifier - unregister for notifications of + * frequency band update + * + * @nb: driver notifier block + * + * The consumer should call this API when it is longer interested with + * the frequency band updates from other producers. Usually, this should + * be performed during driver cleanup. + * + * Return: + * 0 for unregistering a consumer driver. + * Returns a negative error code for failure. + */ +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_unregister_notifier); +#endif /*HAVE_LINUX_ACPI_AMD_WBRF_H*/ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e2777f4894a71..1788dc63f626f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -113,4 +113,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index a9a77d3a9cdf4..88fa953aa980a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -129,4 +129,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #bug: split BUILD_BUG stuff out into dnl AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) + + dnl #v6.7-rc1-2-g58e82a62669d + dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature + dnl + AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) ]) diff --git a/include/kcl/header/linux/acpi_amd_wbrf.h b/include/kcl/header/linux/acpi_amd_wbrf.h new file mode 100644 index 0000000000000..ecf5be29494d4 --- /dev/null +++ b/include/kcl/header/linux/acpi_amd_wbrf.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___ACPI_AMD_WBRF_H___H_ +#define _KCL_HEADER___ACPI_AMD_WBRF_H___H_ + +#ifdef HAVE_LINUX_ACPI_AMD_WBRF_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_acpi_amd_wbrf.h b/include/kcl/kcl_acpi_amd_wbrf.h new file mode 100644 index 0000000000000..b8178e740f171 --- /dev/null +++ b/include/kcl/kcl_acpi_amd_wbrf.h @@ -0,0 +1,94 @@ +/*Copy from include/linux/acpi_amd_wbrf.h*/ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Wifi Band Exclusion Interface (AMD ACPI Implementation) + * Copyright (C) 2023 Advanced Micro Devices + */ + +#ifndef _KCL_ACPI_AMD_WBRF_H +#define _KCL_ACPI_AMD_WBRF_H + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +#include +#include + +/* The maximum number of frequency band ranges */ +#define MAX_NUM_OF_WBRF_RANGES 11 + +/* Record actions */ +#define WBRF_RECORD_ADD 0x0 +#define WBRF_RECORD_REMOVE 0x1 + +/** + * struct freq_band_range - Wifi frequency band range definition + * @start: start frequency point (in Hz) + * @end: end frequency point (in Hz) + */ +struct freq_band_range { + u64 start; + u64 end; +}; + +/** + * struct wbrf_ranges_in_out - wbrf ranges info + * @num_of_ranges: total number of band ranges in this struct + * @band_list: array of Wifi band ranges + */ +struct wbrf_ranges_in_out { + u64 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +}; + +/** + * enum wbrf_notifier_actions - wbrf notifier actions index + * @WBRF_CHANGED: there was some frequency band updates. The consumers + * should retrieve the latest active frequency bands. + */ +enum wbrf_notifier_actions { + WBRF_CHANGED, +}; + +#if IS_ENABLED(CONFIG_AMD_WBRF) +bool acpi_amd_wbrf_supported_producer(struct device *dev); +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in); +bool acpi_amd_wbrf_supported_consumer(struct device *dev); +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out); +int amd_wbrf_register_notifier(struct notifier_block *nb); +int amd_wbrf_unregister_notifier(struct notifier_block *nb); +#else +static inline +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + return false; +} + +static inline +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + return -ENODEV; +} + +static inline +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + return false; +} +static inline +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + return -ENODEV; +} +static inline +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} +static inline +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} +#endif /* CONFIG_AMD_WBRF */ + +#endif /* HAVE_LINUX_ACPI_AMD_WBRF */ +#endif /* _KCL_ACPI_AMD_WBRF_H */ From c877d30d7c0cda9abd97dba64081f764fd576015 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Dec 2023 17:15:52 +0800 Subject: [PATCH 1196/2070] drm/amdkcl: check whether drm/drm_eld.h exist It's caused by v6.6-rc2-771-g8eb80946ab0c drm/edid: split out drm_eld.h from drm_edid.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_eld.h | 9 +++++++++ 2 files changed, 15 insertions(+) create mode 100644 include/kcl/header/drm/drm_eld.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 38a64fd0deb08..e95a330d6472b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -98,4 +98,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) + + dnl # + dnl # v6.6-rc2-771-g8eb80946ab0c + dnl # drm/edid: split out drm_eld.h from drm_edid.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) ]) diff --git a/include/kcl/header/drm/drm_eld.h b/include/kcl/header/drm/drm_eld.h new file mode 100644 index 0000000000000..e531edccae0d7 --- /dev/null +++ b/include/kcl/header/drm/drm_eld.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_ELD_H_ +#define _KCL_HEADER_DRM_ELD_H_H_ + +#ifdef HAVE_DRM_DRM_ELD_H +#include_next +#endif + +#endif From fe9cbf9f2f9a1a84c2c914e32d9e21519730bd1f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Dec 2023 14:19:22 +0800 Subject: [PATCH 1197/2070] drm/amdkcl: test drm_dp_calc_pbn_mode whether has two argument It's caused by v6.6-rc2-668-g7707dd602259 drm/dp_mst: Fix fractional DSC bpp handling Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 7 +++++-- include/kcl/backport/kcl_drm_dp_mst_helper_backport.h | 11 ++++++++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4e9bcda07c71d..2ce23ea5dad43 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8524,7 +8524,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, max_bpc); bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; clock = adjusted_mode->clock; - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } dm_new_connector_state->vcpi_slots = diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index d168a591bcd23..7261c98f40b18 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -1,7 +1,10 @@ dnl # -dnl # commit 9a7c0da823fd4e65098bd466a996503cc8309c0e +dnl # commit v5.5-rc2-902-gdc48529fb14e dnl # drm/dp_mst: Add PBN calculation for DSC modes dnl # +dnl #v6.6-rc2-668-g7707dd602259 +dnl #drm/dp_mst: Fix fractional DSC bpp handling +dnl AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ @@ -10,7 +13,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, - [drm_dp_calc_pbn_mode() wants 3args]) + [drm_dp_calc_pbn_mode() wants 3 args]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index c6de78678e856..9791910ed58b0 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -25,15 +25,20 @@ #include /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ -#if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) +#ifndef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS static inline int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { +#ifndef HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H if (dsc) return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), 8 * 54 * 1000 * 1000); - - return drm_dp_calc_pbn_mode(clock, bpp); +#endif + return drm_dp_calc_pbn_mode(clock, bpp +#ifdef HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H + << 4 +#endif + ); } #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif From e6167964a84976a02f2b28ea9a5039c158243b5e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Dec 2023 16:14:20 +0800 Subject: [PATCH 1198/2070] drm/amdkcl: test struct drm_dp_mst_topology_state whether has union member pbn_div It's caused by v6.6-rc2-733-g191dc43935d1 drm/dp_mst: Store the MST PBN divider value in fixed point format Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 12 ++++++++---- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 19 +++++++++++++++---- 4 files changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2ce23ea5dad43..38b65ab60976b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8473,7 +8473,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) struct drm_dp_mst_topology_state *mst_state; #endif enum dc_color_depth color_depth; @@ -8506,12 +8506,15 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#else + mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#endif #endif if (!state->duplicated) { @@ -12943,7 +12946,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) if (!mgr->mst_state ) continue; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0ac66c8fc0a15..b3e8ec55e8e52 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -322,7 +322,12 @@ static void dm_helpers_construct_old_payload( struct drm_dp_mst_atomic_payload *old_payload) { struct drm_dp_mst_atomic_payload *pos; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + int pbn_per_slot = mst_state->pbn_div; +#endif + u8 next_payload_vc_start = mgr->next_start_slot; u8 payload_vc_start = new_payload->vc_start_slot; u8 allocated_time_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 2703866a69a09..905314fa1cef1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1167,7 +1167,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) int pbn_per_timeslot; #endif int link_timeslots_used; @@ -1175,7 +1175,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); #endif @@ -1210,8 +1210,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, for (i = 0; i < count; i++) link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION dfixed_trunc(mst_state->pbn_div) +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div #else pbn_per_timeslot #endif @@ -1219,8 +1221,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div; #else pbn_per_timeslot; #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 8a11e44f294ed..8cf95a2c43af3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -44,14 +44,25 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ], [ struct drm_dp_mst_topology_state * mst_state = NULL; - int pbn_div; - pbn_div = mst_state->pbn_div; + mst_state->pbn_div = 0; ], [ - AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV, 1, + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT, 1, [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + fixed20_12 pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION, 1, + [struct drm_dp_mst_topology_state has union member pbn_div]) ]) ]) ]) From 1bc7cb3e62b9c28193a478094c14314e7951cdbc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Dec 2023 10:50:30 +0800 Subject: [PATCH 1199/2070] drm/amdkcl: fake drm_WARN_ON It's caused by a78422e9dff366b3a46ae44caf6ec8ded9c9fc2f drm/sched: implement dynamic job-flow control Signed-off-by: Asher Song --- drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/kcl_drm_print.h | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 740dbe3af3b76..97113f7b2c0db 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -7,5 +7,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index e2855aa2a299d..888592871d7ca 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -54,6 +54,19 @@ dev_name((drm)->dev), ## arg) #endif +#ifndef drm_WARN +#define drm_WARN(drm, condition, format, arg...) \ + WARN(condition, "%s %s: " format, \ + dev_driver_string((drm)->dev), \ + dev_name((drm)->dev), ## arg) +#endif + +#ifndef drm_WARN_ON +#define drm_WARN_ON(drm, x) \ + drm_WARN((drm), (x), "%s", \ + "drm_WARN_ON(" __stringify(x) ")") +#endif + #ifndef DRM_NOTE #define DRM_NOTE(fmt, ...) \ _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) From 86226941c779f46aba466910e4e623a3774f27e0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 25 Mar 2024 17:15:20 +0800 Subject: [PATCH 1200/2070] drm/amdkcl: fake queue_work_node It's caused by v6.7-rc1-196-gb0a7ce53d494 drm/ttm: Schedule delayed_delete worker closer Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_workqueue_backport.h | 10 +++++++++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index e7616748289ce..17faee9d17a88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -15,3 +15,25 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ ]) ]) ]) + +dnl # +dnl # commit id:v5.0-rc2-28-g8204e0c1113d +dnl # workqueue: Provide queue_work_node to queue work near a given NUMA node +dnl # +AC_DEFUN([AC_AMDGPU_QUEUE_WORK_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + queue_work_node(0,NULL, NULL); + ], [queue_work_node], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_QUEUE_WORK_NODE, 1, + [queue_work_node() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_WORKQUEUE], [ + AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_QUEUE_WORK_NODE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c64b92a38bf38..bf9144ab0dea5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -159,7 +159,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC - AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO AC_AMDGPU_TOTALRAM_PAGES @@ -204,6 +203,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMA_IS_INITIAL AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME + AC_AMDGPU_WORKQUEUE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index e6cab104d2b34..032baf13deb03 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h index ac9ffbddd468c..db95877443f53 100644 --- a/include/kcl/backport/kcl_workqueue_backport.h +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -10,4 +10,14 @@ extern bool kcl_cancel_work(struct work_struct *work); #define cancel_work kcl_cancel_work #endif +/* Copied from kernel/workqueue.c and modified for KCL */ +#ifndef HAVE_QUEUE_WORK_NODE +static inline +bool _kcl_queue_work_node(int node, struct workqueue_struct *wq, + struct work_struct *work) +{ + return queue_work(wq, work); +} +#define queue_work_node _kcl_queue_work_node +#endif #endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From fc4f5dcfe438d667ac2764db824814ee8dce50c2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 14:19:16 +0800 Subject: [PATCH 1201/2070] drm/amdkcl: test linux/units.h whether exists It's caused by v6.7-rc5-897-g18df969b44a0 drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/units.h | 10 ++++++++++ include/kcl/kcl_units.h | 12 ++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 include/kcl/header/linux/units.h create mode 100644 include/kcl/kcl_units.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1788dc63f626f..b41ecbd50909c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -114,4 +114,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 88fa953aa980a..4df530c27442c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -134,4 +134,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature dnl AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) + + dnl #v5.5-5479-g23331e489361 + dnl #include/linux/units.h: add helpers for kelvin to/from Celsius conversion + dnl + AC_KERNEL_CHECK_HEADERS([linux/units.h]) ]) diff --git a/include/kcl/header/linux/units.h b/include/kcl/header/linux/units.h new file mode 100644 index 0000000000000..228273e685fc1 --- /dev/null +++ b/include/kcl/header/linux/units.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_LINUX_UNITS_H_H +#define _KCL_HEADER_LINUX_UNITS_H_H + +#ifdef HAVE_LINUX_UNITS_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_units.h b/include/kcl/kcl_units.h new file mode 100644 index 0000000000000..21d9f45fb1c5e --- /dev/null +++ b/include/kcl/kcl_units.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_LINUX_UNITS_H +#define KCL_KCL_LINUX_UNITS_H + +#include + +#ifndef HZ_PER_MHZ +#define HZ_PER_MHZ 1000000UL +#endif + +#endif + From 58e5d8ec5d97575c0654cb7f0a0ba727892ce98b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 16:16:43 +0800 Subject: [PATCH 1202/2070] drm/amdkcl: test whether drm_gem_object->resv whether exist It's caused by v6.7-rc3-500-gdfc03588cf8c drm/amd/display: Initialize writeback connector Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index d9527c05fc878..3ca85a9ebd38e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -106,7 +106,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); goto error_unlock; From 8520f4073ff3e04eafa971e21b058f666a6509b8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 16:35:19 +0800 Subject: [PATCH 1203/2070] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB It's caused by v6.7-rc3-500-gdfc03588cf8c drm/amd/display: Initialize writeback connector Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index 3ca85a9ebd38e..fab8b363e6477 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -80,6 +80,7 @@ static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector) return drm_add_modes_noedid(connector, 3840, 2160); } +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, struct drm_writeback_job *job) { @@ -164,6 +165,7 @@ static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector, amdgpu_bo_unreserve(rbo); amdgpu_bo_unref(&rbo); } +#endif static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = { .atomic_check = amdgpu_dm_wb_encoder_atomic_check, @@ -179,8 +181,10 @@ static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = { static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = { .get_modes = amdgpu_dm_wb_connector_get_modes, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB .prepare_writeback_job = amdgpu_dm_wb_prepare_job, .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job, +#endif }; int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm, From af6984dfe786a566d1a114c8be5ba19410a9835b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 20:02:46 +0800 Subject: [PATCH 1204/2070] drm/amdgpu: [hybrid] remove DRM_UNLOCKED flag This is caused by v6.7-rc3-559-g2798ffcc1d6a drm: Remove locking for legacy ioctls and DRM_UNLOCKED Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3c3d1f4583df5..4445461e51980 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3123,7 +3123,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) }; static struct drm_driver amdgpu_kms_driver = { From 3bbdbf27c429bd4890222e3c8052ac252fe60b5e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 28 Dec 2023 18:13:37 +0800 Subject: [PATCH 1205/2070] drm/amdkcl: add clang support Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bf9144ab0dea5..554caef0a4b0c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -411,10 +411,16 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ kbuild_src_flag='' kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' kbuild_workaround_flag='' + kbuild_cc='' + if test -s ${LINUX_OBJ}/.config; then + if grep -q 'CONFIG_CC_IS_CLANG=y' "${LINUX_OBJ}/.config"; then + kbuild_cc='CC=clang' + fi + fi test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From e8b218352dec8229d76af840dc0bf26fa8aef17c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 4 Jan 2024 19:44:03 +0800 Subject: [PATCH 1206/2070] drm/amdkcl: initialize the variables in m4. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 index 326a3fc8e64c4..4527ccd0a9659 100644 --- a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - pgprot_t prot; + pgprot_t prot = {0}; kmap_local_page_prot(NULL, prot); ], [ AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 index d1f869507e4dd..192bb1767dda5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ #include #include ],[ - pgprot_t prot; + pgprot_t prot = {0}; vmf_insert_pfn_prot(NULL, 0, 0, prot); ],[ AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, @@ -23,7 +23,7 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ #include #include ],[ - pgprot_t prot; + pgprot_t prot = {0}; vm_insert_pfn_prot(NULL, 0, 0, prot); ],[ AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, From 7b2cefc67897c3eeff0ba65f2036734914dbfeb1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 9 Jan 2024 13:32:34 +0800 Subject: [PATCH 1207/2070] drm/amdkcl: test whether dma_buf_is_dynamic() is available It's caused by 79e7fdec71f255c9961fae19619532bb4493742a "drm/amdgpu: Auto-validate DMABuf imports in compute VMs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma-buf.h | 18 ++++++++++++++++++ 5 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 create mode 100644 include/kcl/kcl_dma-buf.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b41ecbd50909c..ff1003cceb382 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -115,4 +115,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ae3bf61f5d415..5270fd76d84fc 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -107,6 +107,9 @@ /* dev_pm_set_driver_flags() is available */ #define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 +/* dma_buf_is_dynamic() is available */ +#define HAVE_DMA_BUF_IS_DYNAMIC 1 + /* dma_buf->dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 new file mode 100644 index 0000000000000..0b5844f8c43dc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.4-rc4-863-g15fd552d186c +dnl # dma-buf: change DMA-buf locking convention v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_IS_DYNAMIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_is_dynamic(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_IS_DYNAMIC, 1, + [dma_buf_is_dynamic() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 554caef0a4b0c..4e4d7e79e8bb7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -196,6 +196,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/include/kcl/kcl_dma-buf.h b/include/kcl/kcl_dma-buf.h new file mode 100644 index 0000000000000..fe7094bc3071e --- /dev/null +++ b/include/kcl/kcl_dma-buf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer to dma-buf-mapped memory, plus helpers. + * Copied from include/kcl/dma-buf.h + */ +#ifndef _KCL_KCL__DMA_BUF_H__H__ +#define _KCL_KCL__DMA_BUF_H__H__ + +#include + +#ifndef HAVE_DMA_BUF_IS_DYNAMIC +static inline bool dma_buf_is_dynamic(struct dma_buf *dmabuf) +{ + return false; +} +#endif + +#endif \ No newline at end of file From fe11cadd08d928f80a3fc3dfe1a990d9267b8d29 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 9 Jan 2024 11:36:56 +0800 Subject: [PATCH 1208/2070] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 79e7fdec71f255c9961fae19619532bb4493742a "drm/amdgpu: Auto-validate DMABuf imports in compute VMs" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 2f0000d101bb2..daa36bcfcfa66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -636,7 +636,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, spin_unlock(&vm->status_lock); bo = bo_base->bo; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); r = validate(param, bo); if (r) From f790aa26888bdbae257cd06f9548eacffb22c789 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 10 Jan 2024 14:01:23 +0800 Subject: [PATCH 1209/2070] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 455b15748da59235d86edd764c0fcc35b71d6b69 "drm/amdgpu: add ACA bank dump debugfs support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index 9b31804491500..e9c981e7d348d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -968,7 +968,11 @@ static const struct file_operations aca_ue_dump_debug_fops = { .release = single_release, }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); +#endif #endif void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) From e1b4d31ffe40ae8e2107dc50b16d2e0c32c35dce Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 17 Jan 2024 14:07:56 +0800 Subject: [PATCH 1210/2070] drm/amdgpu: Synchronize after mapping into a compute VM Compute VMs use user mode queues for command submission. They cannot use a CS ioctl to synchronize with pending PTE updates and flush TLBs. Do this synchronization in amdgpu_gem_va_ioctl for compute VMs. Signed-off-by: Felix Kuehling Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c5c67593327d8..ea67f1e3d3579 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -879,11 +879,12 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, */ static struct dma_fence * amdgpu_gem_va_update_vm(struct amdgpu_device *adev, - struct amdgpu_vm *vm, + struct amdgpu_fpriv *fpriv, struct amdgpu_bo_va *bo_va, uint32_t operation) { struct dma_fence *fence; + struct amdgpu_vm *vm = &fpriv->vm; int r = 0; /* Always start from the VM's existing last update fence. */ @@ -916,6 +917,23 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, if (r) goto error; + if (vm->is_compute_context) { + if (bo_va->last_pt_update) + r = dma_fence_wait(bo_va->last_pt_update, true); + if (!r && vm->last_update) + r = dma_fence_wait(vm->last_update, true); + if (!r) { + uint32_t xcc_mask = (!adev->xcp_mgr || + fpriv->xcp_id == ~0) ? 1 : + adev->xcp_mgr->xcp[fpriv->xcp_id] + .ip[AMDGPU_XCP_GFX].inst_mask; + + r = amdgpu_vm_flush_compute_tlb(adev, vm, + TLB_FLUSH_LEGACY, + xcc_mask); + } + } + /* * Decide which fence best represents the last update: * @@ -1119,7 +1137,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, * fence can then be exported to the user-visible VM timeline. */ if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) { - fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, + fence = amdgpu_gem_va_update_vm(adev, fpriv, bo_va, args->operation); if (timeline_syncobj && fence) { From e43790b5c8c5e2efccae4e35dca5d0e86d578cb3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 Jan 2024 11:40:44 +0800 Subject: [PATCH 1211/2070] drm/amdgpu: update update_spm_vmid() param for non-upstream code It's caused by 3a260e1feaa636b3d718055a3259228fbd1d6bb4 "drm/amd/amdgpu: Update RLC_SPM_MC_CNT by ring wreg in guest" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 0d1007d6f146b..037e9aea2b691 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -66,7 +66,7 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * } /* init spm vmid with 0x0 */ - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0); /* set spm ring registers */ spin_lock(&adev->gfx.kiq[0].ring_lock); @@ -95,7 +95,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); } void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) From 4d2eace5fc29efa709d15429db2532d153af131f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 6 Feb 2024 19:14:59 +0800 Subject: [PATCH 1212/2070] drm/amdkcl: export drm_gem_prime_handle_to_fd and drm_gem_prime_fd_to_handle On rhel9.4 which using kernel 6.4, drm_gem_prime_handle_to_fd and drm_gem_prime_fd_to_handle are unexported, so export it. It's caused by v6.4-rc7-1904-g71a7974ac701 drm/prime: Unexport helpers for fd/handle conversion eec9e451b drm/amdkfd: Export DMABufs from KFD using GEM handles Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ----- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c | 28 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ include/kcl/backport/kcl_drm_prime.h | 13 ++++++++++ 5 files changed, 44 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4445461e51980..192dd75682243 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3178,12 +3178,8 @@ static struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif #endif - -#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -#endif - #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, #endif @@ -3236,10 +3232,8 @@ const struct drm_driver amdgpu_partition_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, -#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -#endif .gem_prime_import = amdgpu_gem_prime_import, #ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4150605156bba..4ded83c6f80b8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_dp_helper.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_dp_helper.o kcl_drm_prime.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c new file mode 100644 index 0000000000000..36ca9dec40c2b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * driver/drm/drm_prime.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int (*_kcl_drm_gem_prime_handle_to_fd)(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +EXPORT_SYMBOL(_kcl_drm_gem_prime_handle_to_fd); + +int (*_kcl_drm_gem_prime_fd_to_handle)(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +EXPORT_SYMBOL(_kcl_drm_gem_prime_fd_to_handle); +#endif + +void amdkcl_prime_init(void) +{ +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + _kcl_drm_gem_prime_handle_to_fd = amdkcl_fp_setup("drm_gem_prime_handle_to_fd", NULL); + _kcl_drm_gem_prime_fd_to_handle = amdkcl_fp_setup("drm_gem_prime_fd_to_handle", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index f2b0b8a5f736f..487bacf96db43 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -11,6 +11,7 @@ extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); +extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { @@ -23,6 +24,7 @@ int __init amdkcl_init(void) amdkcl_suspend_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); + amdkcl_prime_init(); return 0; } diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h index 33187c1891d71..de796e551b712 100644 --- a/include/kcl/backport/kcl_drm_prime.h +++ b/include/kcl/backport/kcl_drm_prime.h @@ -50,4 +50,17 @@ struct sg_table *_kcl_drm_prime_pages_to_sg(struct drm_device *dev, #define drm_prime_pages_to_sg _kcl_drm_prime_pages_to_sg #endif +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int _kcl_drm_gem_prime_handle_to_fd(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +#define drm_gem_prime_handle_to_fd _kcl_drm_gem_prime_handle_to_fd + +int _kcl_drm_gem_prime_fd_to_handle(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +#define drm_gem_prime_fd_to_handle _kcl_drm_gem_prime_fd_to_handle +#endif + #endif From d638e37d3e7535407820f6c0804f9e08539a0e3d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 26 Feb 2024 21:24:54 +0800 Subject: [PATCH 1213/2070] drm/amdkcl: Check MAX_ORDER whether defined It's caused by 5e0a760b44417f7cadd79de2204d6247109558a0 mm, treewide: rename MAX_ORDER to MAX_PAGE_ORDER On kernel 6.8, macro MAX_ORDER is renamed to MAX_PAGE_ORDER. Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_mmzone.h | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 include/kcl/kcl_mmzone.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ff1003cceb382..c1affbb7aaf88 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 032baf13deb03..f9e3e75824090 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_mmzone.h b/include/kcl/kcl_mmzone.h new file mode 100644 index 0000000000000..7cd5ea05d5af8 --- /dev/null +++ b/include/kcl/kcl_mmzone.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_MMZONE_H +#define _KCL_MMZONE_H + +#include + +#ifndef __ASSEMBLY__ +#ifndef __GENERATING_BOUNDS_H + +#ifndef MAX_PAGE_ORDER +#define MAX_PAGE_ORDER MAX_ORDER +#endif + +#ifndef NR_PAGE_ORDERS +#define NR_PAGE_ORDERS (MAX_PAGE_ORDER + 1) +#endif + +#endif +#endif + +#endif From 3b868222b2daf3617470b33b3c926b9046e3112e Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 11:16:56 -0400 Subject: [PATCH 1214/2070] drm/amdkfd/kfd_ioctl: add pc sampling support Add pc sampling support in kfd_ioctl. The user mode code which uses this new kfd_ioctl is linked to https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface with master branch. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- include/uapi/linux/kfd_ioctl.h | 61 +++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index b8c0f996ee00e..063ff133ae0a5 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1676,6 +1676,62 @@ struct kfd_ioctl_dbg_trap_args { }; }; +/** + * kfd_ioctl_pc_sample_op - PC Sampling ioctl operations + * + * @KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: Query device PC Sampling capabilities + * @KFD_IOCTL_PCS_OP_CREATE: Register this process with a per-device PC sampler instance + * @KFD_IOCTL_PCS_OP_DESTROY: Unregister from a previously registered PC sampler instance + * @KFD_IOCTL_PCS_OP_START: Process begins taking samples from a previously registered PC sampler instance + * @KFD_IOCTL_PCS_OP_STOP: Process stops taking samples from a previously registered PC sampler instance + */ +enum kfd_ioctl_pc_sample_op { + KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES, + KFD_IOCTL_PCS_OP_CREATE, + KFD_IOCTL_PCS_OP_DESTROY, + KFD_IOCTL_PCS_OP_START, + KFD_IOCTL_PCS_OP_STOP, +}; + +/* Values have to be a power of 2*/ +#define KFD_IOCTL_PCS_FLAG_POWER_OF_2 0x00000001 + +enum kfd_ioctl_pc_sample_method { + KFD_IOCTL_PCS_METHOD_HOSTTRAP = 1, + KFD_IOCTL_PCS_METHOD_STOCHASTIC, +}; + +enum kfd_ioctl_pc_sample_type { + KFD_IOCTL_PCS_TYPE_TIME_US, + KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES, + KFD_IOCTL_PCS_TYPE_INSTRUCTIONS +}; + +struct kfd_pc_sample_info { + __u64 interval; /* [IN] if PCS_TYPE_INTERVAL_US: sample interval in us + * if PCS_TYPE_CLOCK_CYCLES: sample interval in graphics core clk cycles + * if PCS_TYPE_INSTRUCTIONS: sample interval in instructions issued by + * graphics compute units + */ + __u64 interval_min; /* [OUT] */ + __u64 interval_max; /* [OUT] */ + __u64 flags; /* [OUT] indicate potential restrictions e.g FLAG_POWER_OF_2 */ + __u32 method; /* [IN/OUT] kfd_ioctl_pc_sample_method */ + __u32 type; /* [IN/OUT] kfd_ioctl_pc_sample_type */ +}; + +#define KFD_IOCTL_PCS_QUERY_TYPE_FULL (1 << 0) /* If not set, return current */ + +struct kfd_ioctl_pc_sample_args { + __u64 sample_info_ptr; /* array of kfd_pc_sample_info */ + __u32 num_sample_info; + __u32 op; /* kfd_ioctl_pc_sample_op */ + __u32 gpu_id; + __u32 trace_id; + __u32 flags; /* kfd_ioctl_pcs_query flags */ + __u32 reserved; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1818,7 +1874,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) +#define AMDKFD_IOC_PC_SAMPLE \ + AMDKFD_IOWR(0x85, struct kfd_ioctl_pc_sample_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x85 +#define AMDKFD_COMMAND_END_2 0x86 #endif From c9e21fb5f7daeacd31f9eee1f5561c2fc6b2cb9d Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 12:09:14 -0400 Subject: [PATCH 1215/2070] drm/amdkfd: add pc sampling support Add pc sampling functions in amdkfd. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 46 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 78 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h | 34 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 13 ++++ 5 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 66f584ea1c783..f03e99f6f3443 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -65,7 +65,8 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ - $(AMDKFD_PATH)/kfd_debug.o + $(AMDKFD_PATH)/kfd_debug.o \ + $(AMDKFD_PATH)/kfd_pc_sampling.o ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 8b3b10d83ccf7..b1edcafc4e78f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -41,6 +41,7 @@ #include "kfd_svm.h" #include "kfd_ipc.h" #include "kfd_trace.h" +#include "kfd_pc_sampling.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" @@ -1876,6 +1877,39 @@ static int kfd_ioctl_rlc_spm(struct file *filep, return kfd_rlc_spm(p, data); } +static int kfd_ioctl_pc_sample(struct file *filep, + struct kfd_process *p, void __user *data) +{ + struct kfd_ioctl_pc_sample_args *args = data; + struct kfd_process_device *pdd; + int ret = 0; + + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { + pr_err("PC Sampling does not support sched_policy %i", sched_policy); + return -EINVAL; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + + if (!pdd) { + pr_debug("could not find gpu id 0x%x.", args->gpu_id); + ret = -EINVAL; + } else if (args->op == KFD_IOCTL_PCS_OP_START) { + pdd = kfd_bind_process_to_device(pdd->dev, p); + if (IS_ERR(pdd)) { + pr_debug("failed to bind process %p with gpu id 0x%x", p, args->gpu_id); + ret = -ESRCH; + } + } + + if (!ret) + ret = kfd_pc_sample(pdd, args); + mutex_unlock(&p->mutex); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3566,6 +3600,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, kfd_ioctl_cross_memory_copy_deprecated, 0), + + /* TODO: KFD_IOC_FLAG_PERFMON is not required for host-trap, disable first */ + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PC_SAMPLE, + kfd_ioctl_pc_sample, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) @@ -3640,6 +3678,14 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) } } + /* PC Sampling Monitor */ + if (unlikely(ioctl->flags & KFD_IOC_FLAG_PERFMON)) { + if (!capable(CAP_PERFMON) && !capable(CAP_SYS_ADMIN)) { + retcode = -EACCES; + goto err_i1; + } + } + if (cmd & (IOC_IN | IOC_OUT)) { if (asize <= sizeof(stack_kdata)) { kdata = stack_kdata; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c new file mode 100644 index 0000000000000..a7e78ff42d079 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "kfd_pc_sampling.h" + +static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + return -EINVAL; +} + +static int kfd_pc_sample_start(struct kfd_process_device *pdd) +{ + return -EINVAL; +} + +static int kfd_pc_sample_stop(struct kfd_process_device *pdd) +{ + return -EINVAL; + +} + +static int kfd_pc_sample_create(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + return -EINVAL; +} + +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) +{ + return -EINVAL; + +} + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args) +{ + switch (args->op) { + case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: + return kfd_pc_sample_query_cap(pdd, args); + + case KFD_IOCTL_PCS_OP_CREATE: + return kfd_pc_sample_create(pdd, args); + + case KFD_IOCTL_PCS_OP_DESTROY: + return kfd_pc_sample_destroy(pdd, args->trace_id); + + case KFD_IOCTL_PCS_OP_START: + return kfd_pc_sample_start(pdd); + + case KFD_IOCTL_PCS_OP_STOP: + return kfd_pc_sample_stop(pdd); + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h new file mode 100644 index 0000000000000..4eeded4ea5b6c --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_PC_SAMPLING_H_ +#define KFD_PC_SAMPLING_H_ + +#include "amdgpu.h" +#include "kfd_priv.h" + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args); + +#endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 3bbe85b44f4b2..31f9d6d4dfc1d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -156,6 +156,19 @@ enum kfd_ioctl_flags { * we also allow ioctls with SYS_ADMIN capability. */ KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), + + /* + * @KFD_IOC_FLAG_PERFMON: + * Performance monitoring feature, GPU performance monitoring can allow users + * to gather some information about other processes. PC sampling can allow + * users to infer information about wavefronts from other processes that are + * running on the same CUs, such as which execution units they are using. As + * such, this type of performance monitoring should be protected and only + * available to users with sufficient capabilities: either CAP_PERFMON, or, + * for backwards compatibility, CAP_SYS_ADMIN. + */ + + KFD_IOC_FLAG_PERFMON = BIT(1), }; /* * Kernel module parameter to specify maximum number of supported queues per From 5a5d5ff4cdf42ef0715f9757efdbce96d19b037d Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 12:24:13 -0400 Subject: [PATCH 1216/2070] drm/amdkfd: enable pc sampling query Enable pc sampling to query system capability. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 65 +++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index a7e78ff42d079..e9277c9beec73 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -25,10 +25,73 @@ #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +struct supported_pc_sample_info { + uint32_t ip_version; + const struct kfd_pc_sample_info *sample_info; +}; + +const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { + 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; + +struct supported_pc_sample_info supported_formats[] = { + { IP_VERSION(9, 4, 1), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, +}; + static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { - return -EINVAL; + uint64_t sample_offset; + int num_method = 0; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) + num_method++; + + if (!num_method) { + pr_debug("PC Sampling not supported on GC_HWIP:0x%x.", + pdd->dev->adev->ip_versions[GC_HWIP][0]); + return -EOPNOTSUPP; + } + + ret = 0; + mutex_lock(&pdd->dev->pcs_data.mutex); + if (user_args->flags != KFD_IOCTL_PCS_QUERY_TYPE_FULL && + pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + /* If we already have a session, restrict returned list to current method */ + user_args->num_sample_info = 1; + + if (user_args->sample_info_ptr) + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : 0; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + + if (!user_args->sample_info_ptr || user_args->num_sample_info < num_method) { + user_args->num_sample_info = num_method; + pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); + return -ENOSPC; + } + + sample_offset = user_args->sample_info_ptr; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) { + ret = copy_to_user((void __user *) sample_offset, + supported_formats[i].sample_info, sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info to user."); + return -EFAULT; + } + sample_offset += sizeof(struct kfd_pc_sample_info); + } + } + + return 0; } static int kfd_pc_sample_start(struct kfd_process_device *pdd) From d62d95fe719b8d33eade2095587749d555926454 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 16:26:26 -0400 Subject: [PATCH 1217/2070] drm/amdkfd: add pc sampling mutex Add pc sampling mutex per node, and do init/destroy in node init. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 1c1b981164db0..c8089a0e30c3b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -618,6 +618,16 @@ static void kfd_smi_init(struct kfd_node *dev) spin_lock_init(&dev->smi_lock); } +static void kfd_pc_sampling_init(struct kfd_node *dev) +{ + mutex_init(&dev->pcs_data.mutex); +} + +static void kfd_pc_sampling_exit(struct kfd_node *dev) +{ + mutex_destroy(&dev->pcs_data.mutex); +} + static int kfd_init_node(struct kfd_node *node) { int err = -1; @@ -648,6 +658,7 @@ static int kfd_init_node(struct kfd_node *node) } kfd_smi_init(node); + kfd_pc_sampling_init(node); return 0; @@ -686,6 +697,7 @@ static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) kfd_topology_remove_device(knode); if (knode->gws) amdgpu_amdkfd_free_gws(knode->adev, knode->gws); + kfd_pc_sampling_exit(knode); kfree(knode); kfd->nodes[i] = NULL; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 31f9d6d4dfc1d..deed97e1621d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -293,6 +293,11 @@ struct kfd_vmid_info { struct kfd_dev; +/* Per device PC Sampling data */ +struct kfd_dev_pc_sampling { + struct mutex mutex; +}; + struct kfd_node { unsigned int node_id; struct amdgpu_device *adev; /* Duplicated here along with keeping @@ -348,6 +353,8 @@ struct kfd_node { /* Track per device allocated watch points */ uint32_t alloc_watch_ids; spinlock_t watch_points_lock; + + struct kfd_dev_pc_sampling pcs_data; }; struct kfd_dev { From 90cbacdb0ee141a62df9a60a9070553cff45dd7f Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 14:43:49 -0400 Subject: [PATCH 1218/2070] drm/amdkfd: enable pc sampling create Enable pc sampling create. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 59 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 10 ++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e9277c9beec73..9267de0bbdac3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -108,7 +108,64 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd) static int kfd_pc_sample_create(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { - return -EINVAL; + struct kfd_pc_sample_info *supported_format = NULL; + struct kfd_pc_sample_info user_info; + int ret; + int i; + + if (user_args->num_sample_info != 1) + return -EINVAL; + + ret = copy_from_user(&user_info, (void __user *) user_args->sample_info_ptr, + sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info from user\n"); + return -EFAULT; + } + + if (user_info.flags & KFD_IOCTL_PCS_FLAG_POWER_OF_2 && + user_info.interval & (user_info.interval - 1)) { + pr_debug("Sampling interval's power is unmatched!"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version + && user_info.method == supported_formats[i].sample_info->method + && user_info.type == supported_formats[i].sample_info->type + && user_info.interval <= supported_formats[i].sample_info->interval_max + && user_info.interval >= supported_formats[i].sample_info->interval_min) { + supported_format = + (struct kfd_pc_sample_info *)supported_formats[i].sample_info; + break; + } + } + + if (!supported_format) { + pr_debug("Sampling format is not supported!"); + return -EOPNOTSUPP; + } + + mutex_lock(&pdd->dev->pcs_data.mutex); + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + + /* TODO: add trace_id return */ + + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + + pdd->dev->pcs_data.hosttrap_entry.base.use_count++; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + return 0; } static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index deed97e1621d0..a2f7129ef37cc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -293,9 +293,19 @@ struct kfd_vmid_info { struct kfd_dev; +struct kfd_dev_pc_sampling_data { + uint32_t use_count; /* Num of PC sampling sessions */ + struct kfd_pc_sample_info pc_sample_info; +}; + +struct kfd_dev_pcs_hosttrap { + struct kfd_dev_pc_sampling_data base; +}; + /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; + struct kfd_dev_pcs_hosttrap hosttrap_entry; }; struct kfd_node { From 2eb6af117b1f83edb9c558cbea8cb8880ebe9b6e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 8 Aug 2023 16:13:46 -0400 Subject: [PATCH 1219/2070] drm/amdkfd: add trace_id return Add trace_id return for new pc sampling creation per device, Use IDR to quickly locate pc_sampling_entry for reference. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index c8089a0e30c3b..1be49ac37220e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -621,10 +621,12 @@ static void kfd_smi_init(struct kfd_node *dev) static void kfd_pc_sampling_init(struct kfd_node *dev) { mutex_init(&dev->pcs_data.mutex); + idr_init_base(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, 1); } static void kfd_pc_sampling_exit(struct kfd_node *dev) { + idr_destroy(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr); mutex_destroy(&dev->pcs_data.mutex); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 9267de0bbdac3..a607fc1489587 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -110,6 +110,7 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, { struct kfd_pc_sample_info *supported_format = NULL; struct kfd_pc_sample_info user_info; + struct pc_sampling_entry *pcs_entry; int ret; int i; @@ -157,7 +158,19 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return ret ? -EFAULT : -EEXIST; } - /* TODO: add trace_id return */ + pcs_entry = kzalloc(sizeof(*pcs_entry), GFP_KERNEL); + if (!pcs_entry) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + return -ENOMEM; + } + + i = idr_alloc_cyclic(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + pcs_entry, 1, 0, GFP_KERNEL); + if (i < 0) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + kfree(pcs_entry); + return i; + } if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; @@ -165,6 +178,11 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, pdd->dev->pcs_data.hosttrap_entry.base.use_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); + pcs_entry->pdd = pdd; + user_args->trace_id = (uint32_t)i; + + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a2f7129ef37cc..fa8825868ddd5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -295,6 +295,7 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ + struct idr pc_sampling_idr; struct kfd_pc_sample_info pc_sample_info; }; @@ -827,6 +828,11 @@ enum kfd_pdd_bound { */ #define SDMA_ACTIVITY_DIVISOR 100 +struct pc_sampling_entry { + bool enabled; + struct kfd_process_device *pdd; +}; + /* Data that is per-process-per device. */ struct kfd_process_device { /* The device that owns this data. */ From 8113b53b91dd78ddf21b04eef58d755d666bf175 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 8 Aug 2023 16:28:47 -0400 Subject: [PATCH 1220/2070] drm/amdkfd: check pcs_entry valid Check pcs_entry valid for pc sampling ioctl. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 33 ++++++++++++++++++-- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index a607fc1489587..72c66d4bd24f9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -195,6 +195,24 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args) { + struct pc_sampling_entry *pcs_entry; + + if (args->op != KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES && + args->op != KFD_IOCTL_PCS_OP_CREATE) { + + mutex_lock(&pdd->dev->pcs_data.mutex); + pcs_entry = idr_find(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + args->trace_id); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + /* pcs_entry is only for this pc sampling process, + * which has kfd_process->mutex protected here. + */ + if (!pcs_entry || + pcs_entry->pdd != pdd) + return -EINVAL; + } + switch (args->op) { case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: return kfd_pc_sample_query_cap(pdd, args); @@ -203,13 +221,22 @@ int kfd_pc_sample(struct kfd_process_device *pdd, return kfd_pc_sample_create(pdd, args); case KFD_IOCTL_PCS_OP_DESTROY: - return kfd_pc_sample_destroy(pdd, args->trace_id); + if (pcs_entry->enabled) + return -EBUSY; + else + return kfd_pc_sample_destroy(pdd, args->trace_id); case KFD_IOCTL_PCS_OP_START: - return kfd_pc_sample_start(pdd); + if (pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_start(pdd); case KFD_IOCTL_PCS_OP_STOP: - return kfd_pc_sample_stop(pdd); + if (!pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_stop(pdd); } return -EINVAL; From 4cba45a0fefd949797453bf07f5af8f1cbab62fb Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:50:00 -0400 Subject: [PATCH 1221/2070] drm/amdkfd: enable pc sampling destroy Enable pc sampling destroy. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 72c66d4bd24f9..b46caa52fbe83 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -186,10 +186,24 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return 0; } -static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", + pcs_entry, trace_id, pdd->dev->id); + + mutex_lock(&pdd->dev->pcs_data.mutex); + pdd->dev->pcs_data.hosttrap_entry.base.use_count--; + idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfree(pcs_entry); + + return 0; } int kfd_pc_sample(struct kfd_process_device *pdd, @@ -224,7 +238,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (pcs_entry->enabled) return -EBUSY; else - return kfd_pc_sample_destroy(pdd, args->trace_id); + return kfd_pc_sample_destroy(pdd, args->trace_id, pcs_entry); case KFD_IOCTL_PCS_OP_START: if (pcs_entry->enabled) From 8f70aeed4329f7146f5374a0d318ccada029b722 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:11:56 -0400 Subject: [PATCH 1222/2070] drm/amdkfd: add interface to trigger pc sampling trap Add interface to trigger pc sampling trap. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index ed07155666ab6..32f92e0ac3588 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -31,6 +31,8 @@ #include #include #include +#include + #include "amdgpu_irq.h" #include "amdgpu_gfx.h" @@ -338,6 +340,12 @@ struct kfd2kgd_calls { uint32_t inst, unsigned int utimeout); uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev, int engine, int queue); + uint32_t (*trigger_pc_sample_trap)(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From 28702fff67d349c45974e322da2dc3ec0bbb5ef1 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 12:41:03 -0400 Subject: [PATCH 1223/2070] drm/amdkfd: trigger pc sampling trap for gfx v9 Implement trigger pc sampling trap for gfx v9. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 36 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 8 +++++ 2 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 088d09cc7a724..a01917aa8b75d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1225,8 +1225,44 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, int engine, int queue) +{ + return 0; +} +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) { + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_simd */ + value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= max_wave_slot; + if (!(*target_wave_slot)) { + (*target_simd)++; + *target_simd %= max_simd; + } + } else { + pr_debug("PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 704452ca62f8e..892c91a1c1b63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -114,3 +114,11 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, unsigned int utimeout); uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, int engine, int queue); +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); From 8342933469805bb2d65a6df1b2eab6ef549f0e4d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 4 Mar 2025 21:49:25 +0800 Subject: [PATCH 1224/2070] Revert "drm/amdkfd: Clear MODE.VSKIP in gfx9 trap handler" This reverts commit 1241b64d4be8f9cc013711df9847436ef1599b24. --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2851 ++++++++--------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 4 +- 2 files changed, 1424 insertions(+), 1431 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 54fa76f374c90..b14e9b28d1225 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,7 +274,7 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820259, + 0xbf820001, 0xbf820258, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -390,142 +390,98 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840063, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84005f, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840063, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84005f, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -544,138 +500,181 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850051, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbf8200c7, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001e, - 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf840019, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, - 0xbefe00c1, 0xbeff00c1, - 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbf8200c7, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001e, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf840019, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, + 0x8078ff78, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1303,7 +1302,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202d5, + 0xbf820001, 0xbf8202d4, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1420,37 +1419,99 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1469,50 +1530,31 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -1532,259 +1574,215 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbefc0080, 0xbf11017c, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, - 0xd2890000, 0x00000900, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200e3, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200e3, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbefc0080, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202e0, + 0xbf820001, 0xbf8202df, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1831,169 +1829,106 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, - 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, 0xb8f02985, 0x80708170, 0x8e708a70, 0x8e708170, 0xb8fa1605, 0x807a817a, 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bba, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bfa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2013,31 +1948,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2056,51 +2010,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2140,139 +2074,202 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, + 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3154,7 +3151,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202dc, + 0xbf820001, 0xbf8202db, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -3225,143 +3222,80 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000074, 0xbf8cc07f, 0xbef4007e, 0x8675ff7f, 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, 0xb8f02985, 0x80708170, 0x8e708a70, 0x8e708170, 0xb8fa1605, 0x807a817a, 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bba, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bfa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3381,31 +3315,50 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3424,51 +3377,31 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3508,139 +3441,202 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, + 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { @@ -4103,7 +4099,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202ca, + 0xbf820001, 0xbf8202c9, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -4218,99 +4214,133 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb5306, 0x867bc17b, - 0xbf840052, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84004e, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb5306, + 0x867bc17b, 0xbf840052, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84004e, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85001d, 0x24040682, + 0xd86c0000, 0x00000002, + 0xbf8cc07f, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000100, + 0xd0c9006a, 0x0000f702, + 0xbf87ffe5, 0xbf820016, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbefe016a, + 0xbf87fff6, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85001d, - 0x24040682, 0xd86c0000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -4320,32 +4350,61 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000100, 0xd0c9006a, - 0x0000f702, 0xbf87ffe5, - 0xbf820016, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbefe016a, 0xbf87fff6, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4384,206 +4443,142 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200f4, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf840025, 0xbefe00c1, - 0xbeff00c1, 0xb8ef5306, - 0x866fc16f, 0xbf840020, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0xe0510200, 0x781d0000, - 0xe0510300, 0x781d0000, - 0xe0510400, 0x781d0000, - 0x807cff7c, 0x00000500, - 0x8078ff78, 0x00000500, - 0xbf0a6f7c, 0xbf85fff0, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200f4, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf840025, 0xbefe00c1, 0xbeff00c1, + 0xb8ef5306, 0x866fc16f, + 0xbf840020, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0xe0510200, + 0x781d0000, 0xe0510300, + 0x781d0000, 0xe0510400, + 0x781d0000, 0x807cff7c, + 0x00000500, 0x8078ff78, + 0x00000500, 0xbf0a6f7c, + 0xbf85fff0, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 6869e07a2fff2..0eabb7a8cab94 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -447,9 +447,7 @@ L_SAVE: s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) - // Clear VSKIP state now that MODE.VSKIP has been saved. - // If user shader set it then vector instructions would be skipped. - s_setvskip 0,0 + /* the first wave in the threadgroup */ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit From 3ba2f649cc4498e590c03bda75eabbd070ea23c4 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Aug 2023 14:46:44 -0400 Subject: [PATCH 1225/2070] drm/amdkfd/gfx9: enable host trap Enable host trap. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 63 +++++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 24 ++++--- 2 files changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index b14e9b28d1225..791ece748b9b7 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,14 +274,14 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820258, + 0xbf820001, 0xbf82025e, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -294,7 +294,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -303,13 +303,16 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1302,14 +1305,14 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202d4, + 0xbf820001, 0xbf8202da, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -1322,7 +1325,7 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1331,13 +1334,16 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1782,14 +1788,14 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202df, + 0xbf820001, 0xbf8202e5, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -1802,7 +1808,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1811,13 +1817,16 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 0eabb7a8cab94..ada7df7e6f21b 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -121,6 +121,10 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 +var TMA_HOST_TRAP_EN_SHIFT = 1 +var TMA_HOST_TRAP_EN_SIZE = 1 +var TMA_HOST_TRAP_EN_BFE = (TMA_HOST_TRAP_EN_SHIFT | (TMA_HOST_TRAP_EN_SIZE << 16)) + var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 @@ -305,17 +309,21 @@ L_FETCH_2ND_TRAP: s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag - s_waitcnt lgkmcnt(0) - s_lshl_b32 ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp2 - + s_load_dword ttmp4, [ttmp14, ttmp15], 0x10 glc:1 // enable flags from 1st level TMA s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA - s_waitcnt lgkmcnt(0) s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - + s_and_b32 ttmp5, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK // host trap request + s_cbranch_scc0 L_NOT_HT + s_bfe_u32 ttmp5, ttmp4, TMA_HOST_TRAP_EN_BFE // extract host_trap_en to ttmp5[0] + s_cbranch_scc0 L_EXIT_TRAP // HT requested, but host traps not enabled + s_branch L_GOTO_2ND_TRAP +L_NOT_HT: + s_and_b32 ttmp4, ttmp4, 0x1 // debug_enable bit left over + s_lshl_b32 ttmp4, ttmp4, TTMP_DEBUG_TRAP_ENABLED_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp4 +L_GOTO_2ND_TRAP: s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler From 7185cb9a80c38bda5e5ac3d3a47ca1d34b784cd9 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 27 Sep 2023 11:01:18 -0400 Subject: [PATCH 1226/2070] drm/amdgpu: use trapID 4 for host trap Since TRAPSTS.HOST_TRAP won't work pre-gfx943, so use TTMP1 (bit 24: HT) and (bit 16-23: trapID) to identify the host trap. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 + .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2103 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 5 + 3 files changed, 1063 insertions(+), 1047 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index a01917aa8b75d..7e059eb963d54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1248,6 +1248,8 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); /* select *target_wave_slot */ value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 791ece748b9b7..30bc5b3437703 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,155 +274,263 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf82025e, + 0xbf820001, 0xbf820263, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2a05, - 0x807a817a, 0x8e7a8a7a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2a05, 0x807a817a, + 0x8e7a8a7a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840063, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84005f, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, 0x80708170, 0x8e708a70, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -460,224 +568,119 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbf8200c7, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001e, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840063, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84005f, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, + 0xb8ef4306, 0x866fc16f, + 0xbf840019, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbf8200c7, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001e, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf840019, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, + 0xbef600ff, 0x01000000, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, + 0x80786e78, 0xbef60084, 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1305,219 +1308,265 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202da, + 0xbf820001, 0xbf8202df, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2a05, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2a05, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1536,471 +1585,368 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200e3, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200e3, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202e5, + 0xbf820001, 0xbf8202ea, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2019,31 +1965,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2063,51 +2028,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2146,139 +2091,203 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index ada7df7e6f21b..972bacf767ed3 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -261,6 +261,11 @@ L_NOT_HALTED: SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP + // Check TTMP1 bits 24 (HT) and 23:16(trapID): HT == 1 & trapID == 4 + s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) + s_cmp_eq_u32 ttmp2, 0x1040000 + s_cbranch_scc1 L_FETCH_2ND_TRAP + // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. // Maskable exceptions only cause the wave to enter the trap handler if // their respective bit in mode.excp_en is set. From e9e7bab7ce14613110fc84294bc1874b0f19a20b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 27 Sep 2023 10:56:13 -0400 Subject: [PATCH 1227/2070] drm/amdgpu: add sq host trap status check Before fire a new host trap, check the host trap status. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 36 +++++++++++++++++++ .../amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 5 +++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 7e059eb963d54..d45923bfde87f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1229,6 +1229,36 @@ uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return 0; } +static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_hosttrap_status = RREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS); + + if (sq_hosttrap_status & SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK) { + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS, + SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK); + sq_hosttrap_status = 0x0; + continue; + } + if (sq_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_hosttrap_status; +} + uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t max_wave_slot, @@ -1240,6 +1270,12 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, { if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_aldebaran_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index 12d451e5475b7..5b17d90664524 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -462,6 +462,8 @@ #define mmSQ_IND_DATA_BASE_IDX 0 #define mmSQ_CMD 0x037b #define mmSQ_CMD_BASE_IDX 0 +#define mmSQ_HOSTTRAP_STATUS 0x0376 +#define mmSQ_HOSTTRAP_STATUS_BASE_IDX 0 #define mmSQ_TIME_HI 0x037c #define mmSQ_TIME_HI_BASE_IDX 0 #define mmSQ_TIME_LO 0x037d diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 2dfa0e5b1aa3e..3e0210c2bf369 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -2616,6 +2616,11 @@ //SQ_CMD_TIMESTAMP #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_HOSTTRAP_STATUS +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L //SQ_IND_INDEX #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 From dbc5e4e9fc4f04e1e0b07eaa62733c9cfdfb7df3 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Aug 2023 11:58:46 -0400 Subject: [PATCH 1228/2070] drm/amdkfd: trigger pc sampling trap for arcturus Implement trigger pc sampling trap for arcturus. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 1105a09e55dc1..01b0a33a17042 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -389,6 +389,18 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev, return 0; } + +static uint32_t kgd_arcturus_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 10, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -420,5 +432,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap }; From d51a6a9397e28a3caf067fa358b62dc19ea2c34b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:15:57 -0400 Subject: [PATCH 1229/2070] drm/amdkfd: trigger pc sampling trap for aldebaran Implement trigger pc sampling trap for aldebaran. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index c55bc29a2c77c..af2f201eb32f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -164,6 +164,17 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch( return watch_address_cntl; } +static uint32_t kgd_aldebaran_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -194,5 +205,6 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap }; From 0e473092574d82f837e7bd9090bc0d7848df94b6 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 27 Jul 2023 20:20:20 -0400 Subject: [PATCH 1230/2070] drm/amdkfd: use bit operation set debug trap 1st level TMA's 2nd byte which used for trap type setting, to use bit operation to change selected bit only. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 3630accdc9c41..6ab4357226901 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1578,13 +1578,23 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported) return true; } +/* bit offset in 1st-level TMA's 2nd byte which used for KFD_TRAP_TYPE_BIT */ +enum KFD_TRAP_TYPE_BIT { + KFD_TRAP_TYPE_DEBUG = 0, /* bit 0 for debug trap */ + KFD_TRAP_TYPE_HOST, + KFD_TRAP_TYPE_STOCHASTIC, +}; + void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled) { if (qpd->cwsr_kaddr) { - uint64_t *tma = - (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); - tma[2] = enabled; + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); + else + clear_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); } } From 62ac2fd89d45d15bbcce8ca49d451863eeeb359e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:58:57 -0400 Subject: [PATCH 1231/2070] drm/amdkfd: add setting trap pc sampling flag Add setting trap pc sampling flag. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index fa8825868ddd5..3a8fbb590ee3e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1331,6 +1331,8 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, uint64_t tma_addr); void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled); +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled); /* CWSR initialization */ int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 6ab4357226901..9f091b3519996 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1598,6 +1598,19 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, } } +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled) +{ + if (qpd->cwsr_kaddr) { + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(method, &tma[2]); + else + clear_bit(method, &tma[2]); + } +} + /* * On return the kfd_process is fully operational and will be freed when the * mm is released From 66e09b5718ac800e6c735fb5e45fca2dd1d17c39 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 17:10:08 -0400 Subject: [PATCH 1232/2070] drm/amdkfd: enable pc sampling stop Enable pc sampling stop. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 19 ++++++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index b46caa52fbe83..8796c6c28172e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -99,10 +99,23 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd) return -EINVAL; } -static int kfd_pc_sample_stop(struct kfd_process_device *pdd) +static int kfd_pc_sample_stop(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + bool pc_sampling_stop = false; + + pcs_entry->enabled = false; + mutex_lock(&pdd->dev->pcs_data.mutex); + pdd->dev->pcs_data.hosttrap_entry.base.active_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_stop = true; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + + return 0; } static int kfd_pc_sample_create(struct kfd_process_device *pdd, @@ -250,7 +263,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (!pcs_entry->enabled) return -EALREADY; else - return kfd_pc_sample_stop(pdd); + return kfd_pc_sample_stop(pdd, pcs_entry); } return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 3a8fbb590ee3e..6c1f387bbfdc2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -295,6 +295,9 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ + uint32_t active_count; /* Num of active sessions */ + uint32_t target_simd; /* target simd for trap */ + uint32_t target_wave_slot; /* target wave slot for trap */ struct idr pc_sampling_idr; struct kfd_pc_sample_info pc_sample_info; }; From cc6841bda4a46e92c468ed3c26828172ee8730b8 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 13:07:28 -0400 Subject: [PATCH 1233/2070] drm/amdkfd: add queue remapping Add queue remapping to ensure that any waves executing the PC sampling part of the trap handler are done before kfd_pc_sample_stop returns, and that no new waves enter that part of the trap handler afterwards. This avoids race conditions that could lead to use-after-free. Unmapping and remapping the queues either waits for the waves to drain, or preempts them with CWSR, which itself executes a trap and waits for previous traps to finish. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12 ++++++++++++ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 +++ 3 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 452139c3e7afd..4538b4a7623b4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3638,6 +3638,17 @@ int debug_refresh_runlist(struct device_queue_manager *dqm) return debug_map_and_unlock(dqm); } +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param, + uint32_t grace_period) +{ + dqm_lock(dqm); + if (!dqm->dev->kfd->shared_resources.enable_mes) + execute_queues_cpsch(dqm, filter, filter_param, grace_period); + dqm_unlock(dqm); +} + bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, int doorbell_off, u32 *queue_format) @@ -3662,6 +3673,7 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, dqm_unlock(dqm); return r; } + #if defined(CONFIG_DEBUG_FS) static void seq_reg_dump(struct seq_file *m, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index a0cd2ac24253f..0b902433cb888 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -332,6 +332,11 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, int doorbell_off, u32 *queue_format); +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param, + uint32_t grace_period); + static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { return (pdd->lds_base >> 16) & 0xFF; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 8796c6c28172e..5d78fb38620dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -24,6 +24,7 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +#include "kfd_device_queue_manager.h" struct supported_pc_sample_info { uint32_t ip_version; @@ -114,6 +115,8 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + remap_queue(pdd->dev->dqm, + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); return 0; } From 60bbb096ab2dca42a35e550c8e21b3dd44626398 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 17:03:13 -0400 Subject: [PATCH 1234/2070] drm/amdkfd: enable pc sampling start Enable pc sampling start. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 5d78fb38620dd..e3512c6dec5e2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -95,9 +95,23 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, return 0; } -static int kfd_pc_sample_start(struct kfd_process_device *pdd) +static int kfd_pc_sample_start(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + bool pc_sampling_start = false; + + pcs_entry->enabled = true; + mutex_lock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, true); + + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + return 0; } static int kfd_pc_sample_stop(struct kfd_process_device *pdd, @@ -260,7 +274,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (pcs_entry->enabled) return -EALREADY; else - return kfd_pc_sample_start(pdd); + return kfd_pc_sample_start(pdd, pcs_entry); case KFD_IOCTL_PCS_OP_STOP: if (!pcs_entry->enabled) From a6aae63e560c846644c1e3e13c4abc24f3673f5a Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 18:42:49 -0400 Subject: [PATCH 1235/2070] drm/amdkfd: add pc sampling thread to trigger trap Add a kthread to trigger pc sampling trap. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 103 ++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e3512c6dec5e2..fc991dd893b18 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -39,6 +39,92 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, }; +static int kfd_pc_sample_thread(void *param) +{ + struct amdgpu_device *adev; + struct kfd_node *node = param; + uint32_t timeout = 0; + ktime_t next_trap_time; + bool need_wait; + + mutex_lock(&node->pcs_data.mutex); + if (node->pcs_data.hosttrap_entry.base.active_count && + node->pcs_data.hosttrap_entry.base.pc_sample_info.interval && + node->kfd2kgd->trigger_pc_sample_trap) { + switch (node->pcs_data.hosttrap_entry.base.pc_sample_info.type) { + case KFD_IOCTL_PCS_TYPE_TIME_US: + timeout = (uint32_t)node->pcs_data.hosttrap_entry.base.pc_sample_info.interval; + break; + default: + pr_debug("PC Sampling type %d not supported.", + node->pcs_data.hosttrap_entry.base.pc_sample_info.type); + } + } + mutex_unlock(&node->pcs_data.mutex); + if (!timeout) + return -EINVAL; + + adev = node->adev; + need_wait = false; + allow_signal(SIGKILL); + while (!kthread_should_stop() && + !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + if (!need_wait) { + uint32_t inst; + + next_trap_time = ktime_add_us(ktime_get_raw(), timeout); + + for_each_inst(inst, node->xcc_mask) { + node->kfd2kgd->trigger_pc_sample_trap(adev, node->vm_info.last_vmid_kfd, + &node->pcs_data.hosttrap_entry.base.target_simd, + &node->pcs_data.hosttrap_entry.base.target_wave_slot, + node->pcs_data.hosttrap_entry.base.pc_sample_info.method, + inst); + } + pr_debug_ratelimited("triggered a host trap."); + need_wait = true; + } else { + ktime_t wait_time; + s64 wait_ns, wait_us; + + wait_time = ktime_sub(next_trap_time, ktime_get_raw()); + wait_ns = ktime_to_ns(wait_time); + wait_us = ktime_to_us(wait_time); + if (wait_ns >= 10000) + usleep_range(wait_us - 10, wait_us); + else if (wait_ns > 0) + schedule(); + else + need_wait = false; + } + } + + node->pcs_data.hosttrap_entry.base.target_simd = 0; + node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; + node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + + return 0; +} + +static int kfd_pc_sample_thread_start(struct kfd_node *node) +{ + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "pcs_%d", node->adev->ddev.render->index); + node->pcs_data.hosttrap_entry.base.pc_sample_thread = + kthread_run(kfd_pc_sample_thread, node, thread_name); + + if (IS_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + ret = PTR_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread); + node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + pr_debug("Failed to create pc sample thread for %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { @@ -99,6 +185,7 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, struct pc_sampling_entry *pcs_entry) { bool pc_sampling_start = false; + int ret = 0; pcs_entry->enabled = true; mutex_lock(&pdd->dev->pcs_data.mutex); @@ -108,10 +195,21 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); - return 0; + while (pc_sampling_start) { + /* true means pc_sample_thread stop is in progress */ + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + usleep_range(1000, 2000); + } else { + ret = kfd_pc_sample_thread_start(pdd->dev); + break; + } + } + + return ret; } static int kfd_pc_sample_stop(struct kfd_process_device *pdd, @@ -132,6 +230,9 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, remap_queue(pdd->dev->dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); + if (pc_sampling_stop) + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6c1f387bbfdc2..773480e072cb9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -299,6 +299,7 @@ struct kfd_dev_pc_sampling_data { uint32_t target_simd; /* target simd for trap */ uint32_t target_wave_slot; /* target wave slot for trap */ struct idr pc_sampling_idr; + struct task_struct *pc_sample_thread; struct kfd_pc_sample_info pc_sample_info; }; From 7153e8840134e8ae8b6a14c79a348a06e78a0da2 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 18:48:43 -0400 Subject: [PATCH 1236/2070] drm/amdkfd: add pc sampling release when process release Add pc sampling release when process release, it will force to stop all activate sessions with this process. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 25 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index fc991dd893b18..94bd601129c1f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -337,6 +337,31 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ return 0; } +void kfd_pc_sample_release(struct kfd_process_device *pdd) +{ + struct pc_sampling_entry *pcs_entry; + struct idr *idp; + uint32_t id; + + /* force to release all PC sampling task for this process */ + idp = &pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr; + do { + pcs_entry = NULL; + mutex_lock(&pdd->dev->pcs_data.mutex); + idr_for_each_entry(idp, pcs_entry, id) { + if (pcs_entry->pdd != pdd) + continue; + break; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + if (pcs_entry) { + if (pcs_entry->enabled) + kfd_pc_sample_stop(pdd, pcs_entry); + kfd_pc_sample_destroy(pdd, id, pcs_entry); + } + } while (pcs_entry); +} + int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h index 4eeded4ea5b6c..6175563ca9bea 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -30,5 +30,6 @@ int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args); +void kfd_pc_sample_release(struct kfd_process_device *pdd); #endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 9f091b3519996..c29dfbb69e94e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -45,6 +45,7 @@ struct mm_struct; #include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" +#include "kfd_pc_sampling.h" /* * List of struct kfd_process (field kfd_process). @@ -1109,6 +1110,9 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + + kfd_pc_sample_release(pdd); + kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); From 6dfd88372d23b9856b676eda826258d6c1863b6f Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 14 Dec 2023 18:45:49 +0000 Subject: [PATCH 1237/2070] drm/amdkfd: Set debug trap bit when enabling PC Sampling We need the SPI_GDBG_PER_VMID_CNTL.TRAP_EN bit to be set during PC Sampling so that the TTMP registers are valid inside the sampling data. runtime_info.ttmp_setup will be cleared when the user application does the AMDKFD_IOC_RUNTIME_ENABLE ioctl without KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK flag on exit. It is also not valid to have the debugger attached to a process while PC sampling is enabled so adding some checks to prevent this. Co-developed-by: James Zhu Signed-off-by: David Yat Sin Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 28 ++++++-------------- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 26 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 13 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ 5 files changed, 52 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b1edcafc4e78f..0e01b354a766c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3074,26 +3074,9 @@ static int runtime_enable(struct kfd_process *p, uint64_t r_debug, p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; p->runtime_info.r_debug = r_debug; - p->runtime_info.ttmp_setup = enable_ttmp_setup; - if (p->runtime_info.ttmp_setup) { - for (i = 0; i < p->n_pdds; i++) { - struct kfd_process_device *pdd = p->pdds[i]; - - if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { - amdgpu_gfx_off_ctrl(pdd->dev->adev, false); - pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - true, - pdd->dev->vm_info.last_vmid_kfd); - } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { - pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - false, - 0); - } - } - } + if (enable_ttmp_setup) + kfd_dbg_enable_ttmp_setup(p); retry: if (p->debug_trap_enabled) { @@ -3262,7 +3245,7 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v /* Check if target is still PTRACED. */ rcu_read_lock(); if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE - && ptrace_parent(target->lead_thread) != current) { + && ptrace_parent(target->lead_thread) != current) { pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); r = -EPERM; } @@ -3272,6 +3255,11 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; mutex_lock(&target->mutex); + if (!!target->pc_sampling_ref) { + pr_debug("Cannot enable debug trap on PID:%d because PC Sampling active\n", args->pid); + r = -EBUSY; + goto unlock_out; + } if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 0f7aa51b629eb..3563a4ee506a7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -1175,3 +1175,29 @@ void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, mutex_unlock(&target->event_mutex); } + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p) +{ + int i; + + if (p->runtime_info.ttmp_setup) + return; + + p->runtime_info.ttmp_setup = true; + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + + if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { + amdgpu_gfx_off_ctrl(pdd->dev->adev, false); + pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + true, + pdd->dev->vm_info.last_vmid_kfd); + } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { + pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + false, + 0); + } + } +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h index fbb751821c692..f8996f5431329 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h @@ -92,6 +92,9 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, uint64_t exception_set_mask); + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p); + /* * If GFX off is enabled, chips that do not support RLC restore for the debug * registers will disable GFX off temporarily for the entire debug session. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 94bd601129c1f..fc5333603613b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -24,6 +24,7 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +#include "kfd_debug.h" #include "kfd_device_queue_manager.h" struct supported_pc_sample_info { @@ -312,6 +313,14 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, pcs_entry->pdd = pdd; user_args->trace_id = (uint32_t)i; + /* + * Set SPI_GDBG_PER_VMID_CNTL.TRAP_EN so that TTMP registers are valid in the sampling data + * p->runtime_info.ttmp_setup will be cleared when user application calls runtime_disable + * on exit. + */ + kfd_dbg_enable_ttmp_setup(pdd->process); + pdd->process->pc_sampling_ref++; + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); return 0; @@ -323,6 +332,7 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, trace_id, pdd->dev->id); + pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); pdd->dev->pcs_data.hosttrap_entry.base.use_count--; idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); @@ -381,6 +391,9 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (!pcs_entry || pcs_entry->pdd != pdd) return -EINVAL; + } else if (pdd->process->debug_trap_enabled) { + pr_debug("Cannot have PC Sampling and debug trap simultaneously"); + return -EBUSY; } switch (args->op) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 773480e072cb9..ccc76920016ac 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1126,6 +1126,8 @@ struct kfd_process { /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */ struct ida id_table; + /* Indicates process' PC Sampling ref cnt*/ + uint32_t pc_sampling_ref; }; #define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */ From 24fea2ef8032afdc4f8b22085d592367c96bc122 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 16:05:46 +0800 Subject: [PATCH 1238/2070] drm/amdkcl: fake macros DRM_EDID_RANGE_OFFSET_{MIN/MAX}_{VFREQ/HFREQ} It's caused by 5f3e0476a2e2efe4595b4579e74a6028400abbfd "drm/amd/display: handle range offsets in VRR ranges" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_edid.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index dd472225c0477..b121281e6f45a 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -11,4 +11,11 @@ ((product_id) & 0xffff)) #endif /* drm_edid_encode_panel_id */ +#ifndef DRM_EDID_RANGE_OFFSET_MIN_VFREQ +#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ +#endif + #endif From 06a0ecc5c87f64717c347fb7c0946ba76e074bf1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 10:37:18 +0800 Subject: [PATCH 1239/2070] drm/amdkcl: modify kcl code under macro HAVE_STRUCT_XARRAY some kcl code under macro HAVE_STRUCT_XARRAY could be implemented by spin_lock_irqsave, so improve these code. Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 7 files changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 42e54df22d984..7897bdf25d4c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1406,7 +1406,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } -#ifdef HAVE_STRUCT_XARRAY + case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1418,16 +1418,23 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); +#endif gpuvm_fault.addr = vm->fault_info.addr; gpuvm_fault.status = vm->fault_info.status; gpuvm_fault.vmhub = vm->fault_info.vmhub; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } -#endif case AMDGPU_INFO_UQ_FW_AREAS: { struct drm_amdgpu_info_uq_metadata meta_info = {}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index daa36bcfcfa66..dd59e09f7b235 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3203,7 +3203,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ -#ifdef HAVE_STRUCT_XARRAY + void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3213,9 +3213,14 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); - vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif + /* Don't update the fault cache if status is 0. In the multiple * fault case, subsequent faults will return a 0 status which is * useless for userspace and replaces the useful fault status, so @@ -3248,9 +3253,12 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, WARN_ONCE(1, "Invalid vmhub %u\n", vmhub); } } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); -} +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); #endif +} /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index d672b3727e57b..27aed3df07dde 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -679,13 +679,11 @@ static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) mutex_unlock(&vm->eviction_lock); } -#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, uint32_t status, unsigned int vmhub); -#endif void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 26485790cc03a..12d2f181b5344 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -135,10 +135,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); -#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); -#endif } if (!printk_ratelimit()) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index b2312bc8de9d6..9a2a15692c5e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -132,10 +132,8 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); -#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); -#endif } if (printk_ratelimit()) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 5b26005c497ac..18c9839f4a500 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1274,10 +1274,10 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; -#ifdef HAVE_STRUCT_XARRAY + amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); -#endif + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 357f5f3020200..98baad2cfbc50 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1457,10 +1457,10 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; -#ifdef HAVE_STRUCT_XARRAY + amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); -#endif + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); From 8cf5c022e4b481c28d3d3834d030593daaf918fc Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Mar 2024 10:02:45 +0800 Subject: [PATCH 1240/2070] drm/amdkcl: fake macro CAP_PERFMON It's caused by 68592cff2583a71a6af1810a687bc5f86aaafea3 "drm/amdkfd: add pc sampling support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_capability.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h index 2cc984db5ac19..52448ad625f96 100644 --- a/include/kcl/kcl_capability.h +++ b/include/kcl/kcl_capability.h @@ -28,4 +28,8 @@ #define CAP_CHECKPOINT_RESTORE CAP_SYS_ADMIN #endif +#ifndef CAP_PERFMON +#define CAP_PERFMON 38 +#endif + #endif From 574ceb094e0470b1d9e380cfdb1e1ffb6b2da3c1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Mar 2024 15:57:48 +0800 Subject: [PATCH 1241/2070] drm/amdkcl: modify struct kfd_class to non-const For some old kernel, the device_create and class_register APIs use the non-const param, so when define the struct kfd_class to const that causes unpredictable issue. v6.3-rc1-21-g2bd5c63978b7 "driver core: device: make device_create*() take a const struct class *" v6.3-rc5-105-g43a7206b0963 "driver core: class: make class_register() take a const *" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 0e01b354a766c..e2dd54b928c76 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -66,7 +66,7 @@ static const struct file_operations kfd_fops = { static int kfd_char_dev_major = -1; struct device *kfd_device; -static const struct class kfd_class = { +static struct class kfd_class = { .name = kfd_dev_name, }; From 61723cccfa4ca7b450e231797ea030d09f0613bf Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 11 Mar 2024 13:09:34 +0800 Subject: [PATCH 1242/2070] drm/amdkcl: fake macro DRM_EDID_FEATURE_CONTINUOUS_FREQ It's caused by db3e4f1cbb842e29999fa2dbc5cec4341aade464 "drm/amd/display: Use freesync when `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_edid.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index b121281e6f45a..0e5b0fab8f8e3 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -18,4 +18,8 @@ #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ #endif +#ifndef DRM_EDID_FEATURE_CONTINUOUS_FREQ +#define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ +#endif + #endif From 9e539ecc629c4ceb5dd6705bc536aa0f6cad875b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Mar 2024 10:18:09 +0800 Subject: [PATCH 1243/2070] drm/amdkcl: fake macros PCI_ERROR_RESPONSE It's caused by bedb8766222115ae69345fe158eb3cd8027da3f7 "drm/amdgpu: Do a basic health check before reset" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 0fd605cf81fef..a015093db3889 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -97,6 +97,12 @@ 0) #endif +#ifndef PCI_ERROR_RESPONSE +#define PCI_ERROR_RESPONSE (~0ULL) +#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) +#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) +#endif + static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) { return pcie_get_speed_cap(dev); From 85479337fc1db3b194c423d84bdc21d5ac85ab37 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 16:44:07 +0800 Subject: [PATCH 1244/2070] drm/amdkcl: check dgb_printer whether defined Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_print.h | 12 ++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 0250d30115d15..38c1584359f8b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -15,3 +15,21 @@ AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ ]) ]) ]) + +dnl # +dnl # commit v6.8-rc3-242-g9fd6f61a297e +dnl # drm/print: add drm_dbg_printer() for drm device specific printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_dbg_printer(NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DBG_PRINTER, + 1, + [drm_dbg_printer() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4e4d7e79e8bb7..d3c754404c7fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -205,6 +205,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE + AC_AMDGPU_DRM_DBG_PRINTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_print.h b/include/kcl/backport/kcl_drm_print.h index 379308c2563d4..5dc86123ce523 100644 --- a/include/kcl/backport/kcl_drm_print.h +++ b/include/kcl/backport/kcl_drm_print.h @@ -48,4 +48,16 @@ void _kcl_drm_print_bits(struct drm_printer *p, unsigned long value, #define drm_print_bits _kcl_drm_print_bits #endif + +#ifndef HAVE_DRM_DBG_PRINTER +static inline +struct drm_printer _kcl_drm_dbg_printer(struct drm_device *drm, + enum drm_debug_category category, + const char *prefix) +{ + return drm_debug_printer(prefix); +} +#define drm_dbg_printer _kcl_drm_dbg_printer +#endif + #endif From 47a2f10194d8533f13c527a43279e236da918a39 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 17:09:33 +0800 Subject: [PATCH 1245/2070] drm/amdkcl: check drm_gem_object_is_shared_for_memory_stats whether exits It's caused by v6.8-rc3-288-gba1a58d5b907 drm/amdgpu: add shared fdinfo stats Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_gem.h | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index 36c0a786c849f..8f42e769f8845 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -24,3 +24,19 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ ]) ]) ]) + +dnl # +dnl # v6.8-rc3-286-gb31f5eba32ae drm: add drm_gem_object_is_shared_for_memory_stats() helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_gem_object_is_shared_for_memory_stats(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS, 1, + [drm_gem_object_is_shared_for_memory_stats() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3c754404c7fb..6cf37cc61c610 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -206,6 +206,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE AC_AMDGPU_DRM_DBG_PRINTER + AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index cded9b424aa89..73518a8a22f8b 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -57,4 +57,12 @@ drm_gem_object_get(struct drm_gem_object *obj) } #endif /* HAVE_DRM_GEM_OBJECT_PUT */ +/* copy from include/drm/drm_gem.h */ +#ifndef HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS +static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_object *obj) +{ + return (obj->handle_count > 1) || obj->dma_buf; +} +#endif /* HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS */ + #endif From e965bfd76a256da1eac0b349e3f9c2244fe89ddd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 18:11:20 +0800 Subject: [PATCH 1246/2070] drm/amdkcl: check enum drm_debug_category whether exits It's caused by v6.8-rc3-249-ge154c4fc7bf2 drm: remove drm_debug_printer in favor of drm_dbg_printer Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 6 ++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 38c1584359f8b..88be95171ea7b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -33,3 +33,22 @@ AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ ]) ]) ]) + +dnl # +dnl # commit v5.4-rc4-974-g876905b8fe59 +dnl # drm/print: convert debug category macros into an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_CATEGORY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + enum drm_debug_category category; + category = DRM_UT_CORE; + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_CATEGORY, + 1, + [enum drm_debug_category is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6cf37cc61c610..c40791d364e42 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -207,6 +207,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_WORKQUEUE AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS + AC_AMDGPU_DRM_DEBUG_CATEGORY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 888592871d7ca..4c7dd20cd01f8 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -179,4 +179,10 @@ void drm_print_bits(struct drm_printer *p, unsigned long value, const char * const bits[], unsigned int nbits); #endif +#ifndef HAVE_DRM_DEBUG_CATEGORY +enum drm_debug_category { + KCL_DRM_DEBUG_CATEGORY +}; +#endif + #endif From 5347ac8461957702dcc05c350b8745a3600ac217 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 25 Mar 2024 15:38:11 +0800 Subject: [PATCH 1247/2070] drm/amdkcl: test drm_info whether exists Signed-off-by: Asher Song --- include/kcl/kcl_drm_print.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 4c7dd20cd01f8..0546bd944b72c 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -185,4 +185,20 @@ enum drm_debug_category { }; #endif +#ifndef drm_info +/* + * struct drm_device based logging + * + * Prefer drm_device based logging over device or prink based logging. + */ + +/* Helper for struct drm_device based logging. */ +#define __drm_printk(drm, level, type, fmt, ...) \ + dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__) + + +#define drm_info(drm, fmt, ...) \ + __drm_printk((drm), info,, fmt, ##__VA_ARGS__) +#endif + #endif From 18cce25b2d09af42866ebfe931eeffb4d59b5d60 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 10:29:57 +0800 Subject: [PATCH 1248/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 0e70df0c1c78cfbaa632efc9e06ad1b62912026d "drm/amdgpu: change vm->task_info handling" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index dd59e09f7b235..31ef9fc91bc09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2505,9 +2505,15 @@ amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid) struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); vm = xa_load(&adev->vm_manager.pasids, pasid); xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return vm; } From 84b0aa576b5244cc31071f5bd8f4a3932a541f68 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 1 Apr 2024 11:42:00 +0800 Subject: [PATCH 1249/2070] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 87 +++++------------------- 1 file changed, 16 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5270fd76d84fc..473f5119fc5c1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -77,9 +77,6 @@ /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 -/* whether CHUNK_ID_SYNOBJ_IN_OUT is defined */ -#define HAVE_CHUNK_ID_SYNOBJ_IN_OUT 1 - /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 @@ -201,9 +198,6 @@ /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 -/* struct drm_connector_funcs has register members */ -#define HAVE_DRM_CONNECTOR_FUNCS_REGISTER 1 - /* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 @@ -250,6 +244,12 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 +/* drm_dbg_printer() is available */ +#define HAVE_DRM_DBG_PRINTER 1 + +/* enum drm_debug_category is available */ +#define HAVE_DRM_DEBUG_CATEGORY 1 + /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 @@ -394,9 +394,6 @@ /* struct drm_dp_mst_topology_mgr.base is available */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 -/* drm_dp_mst_topology_mgr_init() wants drm_device arg */ -#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 - /* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ @@ -437,15 +434,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_APERTURE_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_AUDIO_COMPONENT_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_AUTH_H 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ @@ -476,9 +464,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PLANE_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 @@ -516,6 +501,9 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 +/* drm_exec() has 3 arguments */ +#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -525,12 +513,6 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ -/* whether drm_fb_helper_lastclose() is available */ -#define HAVE_DRM_FB_HELPER_LASTCLOSE 1 - -/* drm_fb_helper_set_suspend_unlocked() is available */ -#define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 - /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 @@ -546,6 +528,9 @@ /* drm_gem_object_funcs.vmap hsa iosys_map arg */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 +/* drm_gem_object_is_shared_for_memory_stats() is available */ +#define HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS 1 + /* drm_gem_object_put() is available */ #define HAVE_DRM_GEM_OBJECT_PUT 1 @@ -607,20 +592,7 @@ #define HAVE_DRM_NEED_SWIOTLB 1 /* drm_plane_helper_destroy() is available */ -/* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ - -/* drm_plane_mask is available */ -#define HAVE_DRM_PLANE_MASK 1 - -/* drm_plane_create_alpha_property, drm_plane_create_blend_mode_property are - available */ -#define HAVE_DRM_PLANE_PROPERTY_ALPHA_BLEND_MODE 1 - -/* drm_plane_create_color_properties is available */ -#define HAVE_DRM_PLANE_PROPERTY_COLOR_ENCODING_RANGE 1 - -/* drm_plane_create_rotation_property is available */ -#define HAVE_DRM_PLANE_PROPERTY_ROTATION 1 +#define HAVE_DRM_PLANE_HELPER_DESTROY 1 /* drm_prime_pages_to_sg() wants 3 arguments */ #define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 @@ -640,9 +612,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 -/* drm_vblank->time uses ktime_t type */ -#define HAVE_DRM_VBLANK_USE_KTIME_T 1 - /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ @@ -811,12 +780,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_NOSPEC_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_OVERFLOW_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 @@ -826,9 +789,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PROCESSOR_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_RBTREE_TYPES_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 @@ -880,9 +840,6 @@ /* mmu_notifier_synchronize() is available */ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 -/* mm_access() is available */ -/* #undef HAVE_MM_ACCESS */ - /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 @@ -928,6 +885,9 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* rb_add_cached is available */ +#define HAVE_RB_ADD_CACHED 1 + /* whether register_shrinker(x, x) is available */ /* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ @@ -1025,12 +985,6 @@ arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 -/* drm_plane_helper_funcs->prepare_fb() wants const p arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ - -/* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 - /* ide->idr_base is available */ #define HAVE_STRUCT_IDE_IDR_BASE 1 @@ -1064,9 +1018,6 @@ /* vga_remove_vgacon() is available */ #define HAVE_VGA_REMOVE_VGACON 1 -/* vga_switcheroo_set_dynamic_switch() exist */ -/* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ - /* vma_is_initial_{heap, stack} is available */ #define HAVE_VMA_IS_INITIAL_HEAP 1 @@ -1079,12 +1030,6 @@ /* vmf_insert_mixed_prot() is available */ #define HAVE_VMF_INSERT_MIXED_PROT 1 -/* vmf_insert_pfn_{pmd,pud}() wants 3 args */ -/* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ - -/* vmf_insert_pfn_{pmd,pud}_prot() is available */ -#define HAVE_VMF_INSERT_PFN_PMD_PROT 1 - /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 From 3642d345dcb08cfb88c38e6a5903cd2dac257bcb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Mar 2024 15:19:12 +0800 Subject: [PATCH 1250/2070] drm/amdkcl: Fix mst hotplug issue It's caused by bd4e5321fb2237d50a1dcce5602fb3da40a4c506 "drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS" 02e1db74d7ba5b2607421fedce5fc002d4299459 "drm/amd/display: adjust flow for deallocation mst payload" For some old kernel, the asdn code need be keep. So wrap these code under HAVE_DRM_DP_REMOVE_RAYLOAD_PART to fix it. Signed-off-by: Wayne Lin Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 3 + .../gpu/drm/amd/display/dc/link/link_dpms.c | 83 +++++++++++++++++++ 3 files changed, 105 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 38b65ab60976b..498afb1014bc0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2095,6 +2095,25 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ adev->dm.dc->debug.ignore_cable_id = true; +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + /* TODO: There is a new drm mst change where the freedom of + * vc_next_start_slot update is revoked/moved into drm, instead of in + * driver. This forces us to make sure to get vc_next_start_slot updated + * in drm function each time without considering if mst_state is active + * or not. Otherwise, next time hotplug will give wrong start_slot + * number. We are implementing a temporary solution to even notify drm + * mst deallocation when link is no longer of MST type when uncommitting + * the stream so we will have more time to work on a proper solution. + * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we + * should notify drm to do a complete "reset" of its states and stop + * calling further drm mst functions when link is no longer of an MST + * type. This could happen when we unplug an MST hubs/displays. When + * uncommit stream comes later after unplug, we should just reset + * hardware states only. + */ + adev->dm.dc->debug.temp_mst_deallocation_sequence = true; +#endif //HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (adev->dm.dc->caps.dp_hdmi21_pcon_support) drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 32fcbedd82d4f..1df45ffe6eb1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1151,6 +1151,9 @@ struct dc_debug_options { unsigned int min_prefetch_in_strobe_ns; bool disable_unbounded_requesting; bool dig_fifo_off_in_blank; + #ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + bool temp_mst_deallocation_sequence; + #endif bool override_dispclk_programming; bool otg_crc_db; bool disallow_dispclk_dppclk_ds; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 9e489a4a93b3d..e14c89eae6d89 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -1215,6 +1215,85 @@ static void print_mst_streams(struct dc_link *link) } } +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART +static enum dc_status deallocate_mst_payload_with_temp_drm_wa( + struct pipe_ctx *pipe_ctx) +{ + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; + struct dc_dp_mst_stream_allocation_table proposed_table = {0}; + struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); + int i; + bool mst_mode = (link->type == dc_connection_mst_branch); + /* adjust for drm changes*/ + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + const struct dc_link_settings empty_link_settings = {0}; + DC_LOGGER_INIT(link->ctx->logger); + + if (link_hwss->ext.set_throttled_vcp_size) + link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); + if (link_hwss->ext.set_hblank_min_symbol_width) + link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, + &empty_link_settings, + avg_time_slots_per_mtp); + + if (dm_helpers_dp_mst_write_payload_allocation_table( + stream->ctx, + stream, + &proposed_table, + false)) + update_mst_stream_alloc_table( + link, + pipe_ctx->stream_res.stream_enc, + pipe_ctx->stream_res.hpo_dp_stream_enc, + &proposed_table); + else + DC_LOG_WARNING("Failed to update" + "MST allocation table for" + "pipe idx:%d\n", + pipe_ctx->pipe_idx); + + DC_LOG_MST("%s" + "stream_count: %d: ", + __func__, + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { + DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].hpo_dp_stream_enc: %p " + "stream[%d].vcp_id: %d " + "stream[%d].slot_count: %d\n", + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, + i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id, + i, + link->mst_stream_alloc_table.stream_allocations[i].slot_count); + } + + if (link_hwss->ext.update_stream_allocation_table == NULL || + link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { + DC_LOG_DEBUG("Unknown encoding format\n"); + return DC_ERROR_UNEXPECTED; + } + + link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, + &link->mst_stream_alloc_table); + + if (mst_mode) { + dm_helpers_dp_mst_poll_for_allocation_change_trigger( + stream->ctx, + stream); + } + + dm_helpers_dp_mst_update_mst_mgr_for_deallocation(stream->ctx, stream); + + return DC_OK; +} +#endif + static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -1226,6 +1305,10 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) const struct dc_link_settings empty_link_settings = {0}; DC_LOGGER_INIT(link->ctx->logger); +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (link->dc->debug.temp_mst_deallocation_sequence) + return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); +#endif /* deallocate_mst_payload is called before disable link. When mode or * disable/enable monitor, new stream is created which is not in link * stream[] yet. For this, payload is not allocated yet, so de-alloc From 3c401ad85c1b9027b90a26d631753c31e9e85156 Mon Sep 17 00:00:00 2001 From: Lancelot SIX Date: Tue, 12 Mar 2024 11:46:34 +0000 Subject: [PATCH 1251/2070] drm/amdkfd: handle masking host traps in cwsr_trap_handler This patch ensures that the 1st level trap handler for gfx9 (cwsr_trap_handler_gfx9.asm) can correctly handle the case where a non-driver-maskable exception and a host trap (driver maskable) are received simultaneously. It also fixes an issue with the current trap handler which uses ttmp4 temporally, overwriting information needed by the debugger. Tested on gfx90a and gfx942. Co-developed-by: Joseph Greathouse Signed-off-by: Lancelot SIX Signed-off-by: Joseph Greathouse Tested-by: Vladimir Indic Reviewed-by: Laurent Morichetti --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 906 +++++++++--------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 100 +- 2 files changed, 529 insertions(+), 477 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 30bc5b3437703..98061af544db2 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,47 +274,49 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820263, + 0xbf820001, 0xbf820267, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -680,7 +682,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1308,47 +1310,49 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202df, + 0xbf820001, 0xbf8202e3, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -1790,51 +1794,53 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ea, + 0xbf820001, 0xbf8202ee, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -2287,7 +2293,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3169,25 +3175,27 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202db, + 0xbf820001, 0xbf8202ea, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0xbf840008, 0xbf0d986d, + 0xbf85001f, 0x866eff7b, + 0x00000400, 0xbf850061, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, - 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850046, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -3196,187 +3204,130 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031cfd, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b79, - 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0xbf8cc07f, 0x8e739773, + 0x8979ff79, 0x01800000, + 0x87797379, 0xbf0d986d, + 0xbf840009, 0xbf0d9879, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef91898, 0xbeed189d, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b79, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3395,31 +3346,50 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3439,51 +3409,31 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3522,139 +3472,203 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 972bacf767ed3..8014b010654cf 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -100,6 +100,7 @@ var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 +var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT = 22 var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 @@ -121,20 +122,25 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 -var TMA_HOST_TRAP_EN_SHIFT = 1 -var TMA_HOST_TRAP_EN_SIZE = 1 -var TMA_HOST_TRAP_EN_BFE = (TMA_HOST_TRAP_EN_SHIFT | (TMA_HOST_TRAP_EN_SIZE << 16)) - var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 +var TTMP_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP_HOST_TRAP_ENABLED_MASK = 0x1000000 +var TTMP_FEATURES_ENABLED_FLAGS_SHIFT = TTMP_DEBUG_TRAP_ENABLED_SHIFT +var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK /* Save */ var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 var S_SAVE_PC_HI_HT_MASK = 0x01000000 +var S_SAVE_PC_HI_HT_SHIFT = 24 +var S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP = 29 // Only used by the 1st level trap handler to remember if + // we saw a trap type that the driver could not mask, so that + // we can still go to the 2nd-level handler if we driver-mask another + // simultaneous trap. var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 @@ -160,9 +166,15 @@ var s_save_m0 = ttmp5 var s_save_ttmps_lo = s_save_tmp //no conflict var s_save_ttmps_hi = s_save_trapsts //no conflict #if ASIC_FAMILY >= CHIP_GC_9_4_3 -var s_save_ib_sts = ttmp13 +var s_save_ib_sts = ttmp13 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request + // so bits 22:0 are available for stashing next variable's backup. +var s_tma_flags = ttmp7 // free #else -var s_save_ib_sts = ttmp11 +var s_save_ib_sts = ttmp11 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request, bit 6 is no-scratch, bits 5-0 are wave-in-wg + // so bits 22:7 are available for stashing next variable's backup +var s_tma_flags = ttmp13 // free #endif /* Restore */ @@ -231,8 +243,8 @@ L_SKIP_RESTORE: L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK - s_cbranch_scc1 L_FETCH_2ND_TRAP + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE L_CHECK_SAVE: s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save @@ -250,22 +262,16 @@ L_NOT_HALTED: // Any concurrent SAVECTX will be handled upon re-entry once halted. // Check non-maskable exceptions. memory_violation, illegal_instruction - // and debugger (host trap, wave start/end, trap after instruction) - // exceptions always cause the wave to enter the trap handler. + // and debugger (wave start/end, trap after instruction) exceptions always + // cause the wave to enter the trap handler. s_and_b32 ttmp2, s_save_trapsts, \ SQ_WAVE_TRAPSTS_MEM_VIOL_MASK | \ SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK | \ - SQ_WAVE_TRAPSTS_HOST_TRAP_MASK | \ SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK | \ SQ_WAVE_TRAPSTS_WAVE_END_MASK | \ SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP - // Check TTMP1 bits 24 (HT) and 23:16(trapID): HT == 1 & trapID == 4 - s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) - s_cmp_eq_u32 ttmp2, 0x1040000 - s_cbranch_scc1 L_FETCH_2ND_TRAP - // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. // Maskable exceptions only cause the wave to enter the trap handler if // their respective bit in mode.excp_en is set. @@ -283,9 +289,15 @@ L_NOT_ADDR_WATCH: s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_TRAP_ID: - // Check trap_id != 0 + // Check trap_id != 0. If this is a host trap (ttmp1.HT == 1), trap_id is + // non 0, but we defer that part of the check until later as this exception + // is driver maskable. We need to make sure that all non-driver-maskable + // exceptions are accounted for before checking for driver-maskable ones. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_SKIP_CHECK_TRAP_ID s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP +L_SKIP_CHECK_TRAP_ID: if SINGLE_STEP_MISSED_WORKAROUND // Prioritize single step exception over context save. @@ -295,16 +307,22 @@ if SINGLE_STEP_MISSED_WORKAROUND s_cbranch_scc1 L_FETCH_2ND_TRAP end + // Check TTMP1 bits 24 (HT) == 1 + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP +L_FETCH_2ND_TRAP_DRIVER_MASKABLE: // Preserve and clear scalar XNACK state before issuing scalar reads. save_and_clear_ib_sts(ttmp14) // Read second-level TBA/TMA from first-level TMA and jump if available. - // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) - // ttmp12 holds SQ_WAVE_STATUS + // ttmp[2:5] and s_tma_flags can be used (others hold SPI-initialized debug + // data) ttmp12 holds SQ_WAVE_STATUS s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 @@ -313,22 +331,42 @@ L_FETCH_2ND_TRAP: s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - - s_load_dword ttmp4, [ttmp14, ttmp15], 0x10 glc:1 // enable flags from 1st level TMA + s_load_dword s_tma_flags, [ttmp14, ttmp15], 0x10 glc:1 //Load the debug enables and host trap enabled flags s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - s_and_b32 ttmp5, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK // host trap request - s_cbranch_scc0 L_NOT_HT - s_bfe_u32 ttmp5, ttmp4, TMA_HOST_TRAP_EN_BFE // extract host_trap_en to ttmp5[0] - s_cbranch_scc0 L_EXIT_TRAP // HT requested, but host traps not enabled - s_branch L_GOTO_2ND_TRAP -L_NOT_HT: - s_and_b32 ttmp4, ttmp4, 0x1 // debug_enable bit left over - s_lshl_b32 ttmp4, ttmp4, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp4 + + // Put debug enable bit and host trap bit into SAVE_IB_STS register, bits + // 23 and 24, respectively. + s_lshl_b32 s_tma_flags, s_tma_flags, TTMP_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_FEATURES_ENABLED_FLAGS_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, s_tma_flags + + // If not a host trap, then driver cannot mask this. Go to the 2nd-level + // trap handler now. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc0 L_GOTO_2ND_TRAP + + // If driver said host traps are OK, go to the 2nd-level handler now. + s_bitcmp1_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_cbranch_scc1 L_GOTO_2ND_TRAP + + // The driver said host traps are masked, zero out host trap and trapID. + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0x0 + + // If there was another trap besides this masked host trap, go handle it in + // 2nd-level handler. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP // zero this out + s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler + L_GOTO_2ND_TRAP: + // Reset bits used temporarily by 1st level trap handler so they do not + // leak to the 2nd level trap handler. + s_bitset0_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler From a493dec39a07a125cff3554f8e802c102095042e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 20 Mar 2024 12:14:20 +0800 Subject: [PATCH 1252/2070] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 0af3db3ac5b50b67ca88dda58de9b6c4637a8b9c "drm/amdgpu: implement TLB flush fence" Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 31ef9fc91bc09..0d8cd624e5571 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1077,7 +1077,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, amdgpu_vm_tlb_fence_create(params->adev, vm, fence); /* Makes sure no PD/PT is freed before the flush */ - dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), *fence, DMA_RESV_USAGE_BOOKKEEP); } } From 21cd6c7b488fc70112f600e186ab3983b93670b6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 29 Mar 2024 11:22:23 +0800 Subject: [PATCH 1253/2070] drm/amdkcl: fake macro function DIV64_U64_ROUND_UP It's caused by 1f0f4865388bd1d19701d1d65552535dd890e566 "drm/amd/display: Add timing pixel encoding for mst mode validation" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_math64.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_math64.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c1affbb7aaf88..5d6d8f4422c3f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -117,4 +117,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_math64.h b/include/kcl/kcl_math64.h new file mode 100644 index 0000000000000..f1d04dee6b8c5 --- /dev/null +++ b/include/kcl/kcl_math64.h @@ -0,0 +1,11 @@ +#ifndef AMDKCL_MATH64_H +#define AMDKCL_MATH64_H + +#include + +#ifndef DIV64_U64_ROUND_UP +#define DIV64_U64_ROUND_UP(ll, d) \ + ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) +#endif + +#endif \ No newline at end of file From a73c3ad72709c5bdf9225bdf9b016e1a284cdb5f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 29 Mar 2024 11:29:47 +0800 Subject: [PATCH 1254/2070] drm/amdkcl: wrap code out of macro HAVE_DRM_DP_MST_ATOMIC_CHECK It's caused by 1f0f4865388bd1d19701d1d65552535dd890e566 "drm/amd/display: Add timing pixel encoding for mst mode validation" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 905314fa1cef1..634de9a42314f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1041,6 +1041,7 @@ struct dsc_mst_fairness_params { uint32_t bpp_overwrite; struct amdgpu_dm_connector *aconnector; }; +#endif #if defined(CONFIG_DRM_AMD_DC_FP) static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) @@ -1065,6 +1066,7 @@ static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, int count, From 428e0dd069ff29c6d3160a5960b83514907aceb1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Apr 2024 17:53:57 +0800 Subject: [PATCH 1255/2070] drm/amdkcl: fake display legacy macros It's caused by fd4faa19ceb32ed720c818570e5a01d0da456396 "drm/amd/display: Drop legacy code" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- include/kcl/kcl_drm_dp.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 1f277a16b5874..25c848be0df94 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -22,6 +22,8 @@ #ifndef _KCL_DRM_DP_H #define _KCL_DRM_DP_H +#include + #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 #endif @@ -64,4 +66,14 @@ #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) #endif +#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 +#endif + #endif \ No newline at end of file From 5b5d7bd9f1e6f46a385b138918c05583a527b51e Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Mon, 1 Apr 2024 13:30:38 +0000 Subject: [PATCH 1256/2070] drm/amdkfd: return success when no buffer provided For PC Sampling, when user application queries current device capabilities and does not provide buffer, this is used to query the size of buffer needed. Return success instead of error. Return the number of valid samples to the user in case the user provided a larger buffer than needed. Signed-off-by: David Yat Sin Acked-by: Felix Kuehling Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index fc5333603613b..4572ac447ee4b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -133,6 +133,7 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, int num_method = 0; int ret; int i; + const uint32_t user_num_sample_info = user_args->num_sample_info; for (i = 0; i < ARRAY_SIZE(supported_formats); i++) if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) @@ -160,8 +161,15 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, } mutex_unlock(&pdd->dev->pcs_data.mutex); - if (!user_args->sample_info_ptr || user_args->num_sample_info < num_method) { - user_args->num_sample_info = num_method; + user_args->num_sample_info = num_method; + + if (!user_args->sample_info_ptr || !user_num_sample_info) { + /* + * User application is querying the size of buffer needed. Application will + * allocate required buffer size and send a second query. + */ + return 0; + } else if (user_num_sample_info < num_method) { pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); return -ENOSPC; } From 649482e8529e898fed269b01d2b60b036db20844 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 22 Apr 2024 10:53:24 +0800 Subject: [PATCH 1257/2070] drm/amdkcl: fake macro AMD_FMT_MOD_TILE_VER_GFX12 and AMD_FMT_MOD_TILE_GFX12_64K_2D It's caused by 2de480179f2a5cbb54e970ba1312f3aac246f33a "drm/amd/display: Add gfx12 modifiers" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index f28a041070a75..9b1a99ec6d52b 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -100,6 +100,11 @@ #define AMD_FMT_MOD_TILE_VER_GFX11 4 #endif +#ifndef AMD_FMT_MOD_TILE_VER_GFX12 +#define AMD_FMT_MOD_TILE_VER_GFX12 5 +#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 +#endif + #ifndef AMD_FMT_MOD_TILE_GFX11_256K_R_X #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 #endif From 77c332b9bc4fa9ae5f4a6878bee479ec989f2b65 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 14:34:46 +0800 Subject: [PATCH 1258/2070] drm/amdkcl: fix __devm_drm_dev_alloc in amdxcp/backport Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- .../gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c | 33 ++----------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c index 4b2d043f4665a..cc1da02e06e84 100644 --- a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -30,33 +30,7 @@ #include #ifdef AMDKCL_DEVM_DRM_DEV_ALLOC -static void devm_drm_dev_init_release(void *data) -{ - drm_dev_put(data); - -#ifndef HAVE_DRM_DRM_MANAGED_H - if(data){ - struct drm_device *dev = data; - if(!kref_read(&dev->ref)) - kfree(dev->dev_private); - } -#endif -} /* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ -static int devm_drm_dev_init(struct device *parent, - struct drm_device *dev, - const struct drm_driver *driver) -{ - int ret; - - ret = drm_dev_init(dev, driver, parent); - if (ret) - return ret; - - return devm_add_action_or_reset(parent, - devm_drm_dev_init_release, dev); -} - void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, size_t size, size_t offset) { @@ -69,16 +43,15 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, return ERR_PTR(-ENOMEM); drm = container + offset; - ret = devm_drm_dev_init(parent, drm, driver); + ret = drm_dev_init(drm, driver, parent); if (ret) { - kfree(container); + drm_dev_put(drm); return ERR_PTR(ret); } #ifdef HAVE_DRM_DRM_MANAGED_H drmm_add_final_kfree(drm, container); -#else - drm->dev_private = container; #endif + drm->dev_private = container; return container; } From fad1dfa142b68f2039f21f909a9d283a5916abc2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 14:48:35 +0800 Subject: [PATCH 1259/2070] drm/amdkcl: seperate check for DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED as they're introduced in another commit 45cf0e91df8c("drm: Add DisplayPort colorspace property creation function") Signed-off-by: Flora Cui Reviewed-by: Jun Ma --- include/kcl/kcl_drm_connector.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index c0e2b217ddcc5..c0a969519be7f 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -156,10 +156,14 @@ int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, /* Additional Colorimetry extension added as part of CTA 861.G */ #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 11 #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER 12 +#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ + +/* v5.3-rc1-676-g45cf0e91df8c */ +#ifndef DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED /* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */ #define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED 13 #define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT 14 #define DRM_MODE_COLORIMETRY_BT601_YCC 15 -#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ +#endif #endif /* AMDKCL_DRM_CONNECTOR_H */ From c030b5e7e1d7aa530abbeb776c69192fe5dad1a0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 15:07:10 +0800 Subject: [PATCH 1260/2070] drm/amdkcl: rename kcl copy drm_mode_create_colorspace_property to avoid conflict with the drm counterpart Signed-off-by: Flora Cui Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index 559b2610f2966..7616f113d4afb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -164,7 +164,7 @@ static const u32 dp_colorspaces = BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); -static int drm_mode_create_colorspace_property(struct drm_connector *connector, +static int _kcl_drm_mode_create_colorspace_property(struct drm_connector *connector, u32 supported_colorspaces) { struct drm_device *dev = connector->dev; @@ -232,7 +232,7 @@ int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connecto else colorspaces = hdmi_colorspaces; - return drm_mode_create_colorspace_property(connector, colorspaces); + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); } EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); #endif @@ -248,7 +248,7 @@ int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, else colorspaces = dp_colorspaces; - return drm_mode_create_colorspace_property(connector, colorspaces); + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); } EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); #endif \ No newline at end of file From b0526d6cc5830cd60e1426824311e8dad5dbaf7b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 26 Apr 2024 13:57:08 +0800 Subject: [PATCH 1261/2070] drm/amdkcl: Support fdinfo interface for older drm version Fake a drm_show_fdinfo for old kernel version which should print gpu memory stat. Signed-off-by: Philip Yang Signed-off-by: Asher Song Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/backport/Makefile | 2 +- .../gpu/drm/amd/backport/include}/kcl/kcl_drm_file.h | 4 ++-- drivers/gpu/drm/amd/{amdkcl => backport}/kcl_drm_file.c | 4 +++- 4 files changed, 7 insertions(+), 5 deletions(-) rename {include => drivers/gpu/drm/amd/backport/include}/kcl/kcl_drm_file.h (60%) rename drivers/gpu/drm/amd/{amdkcl => backport}/kcl_drm_file.c (97%) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4ded83c6f80b8..6fe8eec72cb21 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_dp_helper.o kcl_drm_prime.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index f5b5d3b9a2d33..8bc3adedebc57 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o + kcl_drm_gem.o kcl_drm_file.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h similarity index 60% rename from include/kcl/kcl_drm_file.h rename to drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index d23292e37dc25..a067b59578b6c 100644 --- a/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -1,5 +1,5 @@ -#ifndef __AMDKCL_KCL_DRM_DRV_H__ -#define __AMDKCL_KCL_DRM_DRV_H__ +#ifndef __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ #include #ifndef HAVE_DRM_SHOW_FDINFO diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c similarity index 97% rename from drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c rename to drivers/gpu/drm/amd/backport/kcl_drm_file.c index 7ddc32cafc5b7..5bc74f05d555e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -37,6 +37,7 @@ #include #include #include +#include "amdgpu_fdinfo.h" #ifndef HAVE_DRM_SHOW_FDINFO /** * drm_show_fdinfo - helper for drm file fops @@ -63,6 +64,7 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) pci_domain_nr(pdev->bus), pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); } + + amdgpu_show_fdinfo(&p, file); } -EXPORT_SYMBOL(drm_show_fdinfo); #endif From 886c78eae16d450fec6bbc5e0719e29caabd54e7 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Mon, 6 May 2024 14:40:21 +0800 Subject: [PATCH 1262/2070] drm/amd/pm: fix the uninitialized scalar variable warning Fix warning for using uninitialized values sclk_mask, mclk_mask and soc_mask. v2:Set default variable to UMD PSTATE(Tim Huang) Signed-off-by: Jesse Zhang Acked-by: Yang Wang Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 31e21ff8859a5..a55830cbf4f46 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -824,10 +824,20 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); + /* = 0: min_freq + * = 1: UMD_PSTATE_CLK + * >= 2: max_freq + */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, + soft_max_level == 0 ? min_freq : + soft_max_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, + soft_min_level == 0 ? min_freq : + soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; break; @@ -839,10 +849,21 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); + /* mclk levels are in reverse order + * = 0: max_freq + * = 1: UMD_PSTATE_CLK + * >= 2: min_freq + */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, + soft_max_level >= 2 ? min_freq : + soft_max_level == 1 ? RENOIR_UMD_PSTATE_FCLK : max_freq, + NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, + soft_min_level >= 2 ? min_freq : + soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; break; From f30e2a65b5313b10dcaedf67e5a46d23d7a2289c Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Tue, 7 May 2024 13:17:32 +0800 Subject: [PATCH 1263/2070] drm/amd/pm: revert "drm/amd/pm: fix the uninitialized scalar variable warning" Revert commit 576bffd10d01 ("drm/amd/pm: fix the uninitialized scalar variable warning") and will update new patch. Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++---------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index a55830cbf4f46..31e21ff8859a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -824,20 +824,10 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - /* = 0: min_freq - * = 1: UMD_PSTATE_CLK - * >= 2: max_freq - */ - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, - soft_max_level == 0 ? min_freq : - soft_max_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, - soft_min_level == 0 ? min_freq : - soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); if (ret) return ret; break; @@ -849,21 +839,10 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - /* mclk levels are in reverse order - * = 0: max_freq - * = 1: UMD_PSTATE_CLK - * >= 2: min_freq - */ - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, - soft_max_level >= 2 ? min_freq : - soft_max_level == 1 ? RENOIR_UMD_PSTATE_FCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, - soft_min_level >= 2 ? min_freq : - soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); if (ret) return ret; break; From 9c13d8ad472c59da6eb8104ee4d8960ca41ab5fa Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 5 Apr 2024 17:59:53 -0400 Subject: [PATCH 1264/2070] drm/amdgpu: Skip dma map resource for null RDMA device To test RDMA using dummy driver on the system without NIC/RDMA device, the get/put dma pages pass in null device pointer, skip the dma map/unmap resource and sg table to avoid null pointer access. Signed-off-by: Philip Yang Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 33 +++++++++++--------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 2ad7009578190..997c8f8a19d7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -721,12 +721,15 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, unsigned long size = min(cursor.size, AMDGPU_MAX_SG_SEGMENT_SIZE); dma_addr_t addr; - addr = dma_map_resource(dev, phys, size, dir, - DMA_ATTR_SKIP_CPU_SYNC); - r = dma_mapping_error(dev, addr); - if (r) - goto error_unmap; - + if (dev) { + addr = dma_map_resource(dev, phys, size, dir, + DMA_ATTR_SKIP_CPU_SYNC); + r = dma_mapping_error(dev, addr); + if (r) + goto error_unmap; + } else { + addr = phys; + } sg_set_page(sg, NULL, size, 0); sg_dma_address(sg) = addr; sg_dma_len(sg) = size; @@ -740,10 +743,10 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, for_each_sgtable_sg((*sgt), sg, i) { if (!sg->length) continue; - - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); } sg_free_table(*sgt); @@ -768,10 +771,12 @@ void amdgpu_vram_mgr_free_sgt(struct device *dev, struct scatterlist *sg; int i; - for_each_sgtable_sg(sgt, sg, i) - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) { + for_each_sgtable_sg(sgt, sg, i) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); + } sg_free_table(sgt); kfree(sgt); } From f5a11b6b11b345a59194f51b614cdd61ca2bc8fc Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 5 Apr 2024 18:54:51 -0400 Subject: [PATCH 1265/2070] drm/amdkfd: Allow peer direct dma map with null RDMA device To test KFD peer direct RDMA functions on system without NIC/RDMA device. Add dynamic debug message to dump sg table segments address and size, to help debug contiguous VRAM peer direct RDMA. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++++---- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 13 ++++++++++--- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1a61d8a2d4786..097ca3c5a6663 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2624,9 +2624,11 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, cur_page++; } - ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); - if (ret) - goto out_of_range; + if (dma_dev) { + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + } *ret_sg = sg; return 0; @@ -2650,7 +2652,8 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, } /* Unmap system memory */ - dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (dma_dev) + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); sg_free_table(sgt); kfree(sgt); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 50541b1dac44a..637a6ceaffefe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -281,7 +281,9 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, struct device *dma_device, int dmasync, int *nmap) { struct sg_table *sg_table_tmp; + struct scatterlist *sg; int ret; + int i; /* * NOTE/TODO: @@ -308,7 +310,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, pr_debug("Client context: 0x%p, sg_head: 0x%p\n", client_context, sg_head); - if (!mem_context || !mem_context->bo || !mem_context->dev) { + if (!mem_context || !mem_context->bo) { pr_warn("Invalid client context"); return -EINVAL; } @@ -328,6 +330,11 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, return ret; } + pr_debug("size 0x%llx nents %d\n", mem_context->size, sg_table_tmp->nents); + for_each_sgtable_sg(sg_table_tmp, sg, i) + pr_debug("segment_%d dma_address 0x%llx length 0x%x dma_length 0x%x\n", + i, sg->dma_address, sg->length, sg->dma_length); + /* Maintain a copy of the handle to sg_table */ mem_context->pages = sg_table_tmp; mem_context->dma_dev = dma_device; @@ -335,7 +342,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, /* Copy information about previosly allocated sg_table */ *sg_head = *mem_context->pages; - /* Return number of pages */ + /* Return number of sg table segments */ *nmap = mem_context->pages->nents; return ret; @@ -350,7 +357,7 @@ static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, pr_debug("Client context: 0x%p, sg_table: 0x%p\n", client_context, sg_head); - if (!mem_context || !mem_context->bo || !mem_context->dma_dev) { + if (!mem_context || !mem_context->bo) { pr_warn("Invalid client context"); return -EINVAL; } From 61964385ff05ac7eb8cb947f2cfb5eaaca30cf43 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 15 May 2024 11:02:55 +0800 Subject: [PATCH 1266/2070] drm/amdkcl: wrap code under macro HAVE_HDR_SINK_METADATA It's caused by e559239eabe628d65d3fbe184890f73477fca0f9 "drm/amd/display: Don't register panel_power_savings on OLED panels" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 498afb1014bc0..7850c180c0c14 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7775,6 +7775,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) return false; +#ifdef HAVE_HDR_SINK_METADATA /* check for OLED panels */ if (amdgpu_dm_connector->bl_idx >= 0) { struct drm_device *drm = amdgpu_dm_connector->base.dev; @@ -7785,6 +7786,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (caps->aux_support) return false; } +#endif return true; } From 91223f8adb58de562a99f2257a96f09a02795a17 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 9 May 2024 15:52:44 -0400 Subject: [PATCH 1267/2070] drm/amdkfd: clear soft lockup issue with host trap When user sets an interval less than what driver can handle, soft lockup arises. To clear this soft lockup with adding a schedule before trigger a new host trap. [ 2896.405488] watchdog: BUG: soft lockup - CPU#22 stuck for 26s! [pcs_130:38057] [ 2896.405676] Supported: No, Unsupported modules are loaded [ 2896.405678] CPU: 22 PID: 38057 Comm: pcs_130 Kdump: loaded Tainted: G OE X N 5.14.21-150500.55.59-default #1 SLE15-SP5 3a8569df5696e57cdcb648c7e890af33bdc23f85 [ 2896.405683] Hardware name: Dell Inc. PowerEdge R7525/0590KW, BIOS 2.6.6 01/13/2022 [ 2896.405684] RIP: 0010:amdgpu_device_rreg.part.42+0x57/0x1d0 [amdgpu] [ 2896.405978] Code: 6f 4c 9c 00 4c 8b 83 b8 08 00 00 4d 01 e0 85 c9 74 15 65 48 8b 04 25 00 1c 02 00 3b 88 b8 09 00 00 0f 85 52 01 00 00 41 8b 28 <8b> 05 43 4c 9c 00 85 c0 74 56 65 48 8b 14 25 00 1c 02 00 39 82 b8 [ 2896.405981] RSP: 0018:ffffb7a6ecc33e30 EFLAGS: 00000246 [ 2896.405984] RAX: ffff949389f18000 RBX: ffff94d3d1100000 RCX: 00000000000094a9 [ 2896.405985] RDX: 0000000000000000 RSI: 0000000000002376 RDI: ffff94d3d1100000 [ 2896.405987] RBP: 0000000000000000 R08: ffffb7a6e2b88dd8 R09: ffff94d30e3b1f14 [ 2896.405989] R10: ffffb7a6c0427d88 R11: ffffb7a6ecc33c80 R12: 0000000000008dd8 [ 2896.405990] R13: 0000000000002376 R14: ffff94d30e3b1f14 R15: ffff94d3d1100000 [ 2896.405992] FS: 0000000000000000(0000) GS:ffff9512ff580000(0000) knlGS:0000000000000000 [ 2896.405994] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2896.405996] CR2: 00007f5b2b732000 CR3: 0000006a1ee10003 CR4: 0000000000770ee0 [ 2896.405998] PKRU: 55555554 [ 2896.405999] Call Trace: [ 2896.406004] [ 2896.406007] kgd_gfx_v9_trigger_pc_sample_trap+0x1d6/0x4f0 [amdgpu 75bb93fc913928fc00917a1c71d5c2dca258175d] Signed-off-by: James Zhu Tested-by: Vladimir Indic Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 4572ac447ee4b..2a9a7a9bb6e6d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -91,12 +91,13 @@ static int kfd_pc_sample_thread(void *param) wait_time = ktime_sub(next_trap_time, ktime_get_raw()); wait_ns = ktime_to_ns(wait_time); wait_us = ktime_to_us(wait_time); - if (wait_ns >= 10000) + if (wait_ns >= 10000) { usleep_range(wait_us - 10, wait_us); - else if (wait_ns > 0) + } else { schedule(); - else - need_wait = false; + if (wait_ns <= 0) + need_wait = false; + } } } From 5cdcb112f87ea181c40287f82ac9a1d77ddd6ee4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 22 Aug 2024 15:45:53 +0800 Subject: [PATCH 1268/2070] drm/amdkfd: [WA] disable SQ core clock gate When host trap pc sampling is activted. Since Command bus from SPI/SQG to SQ may have some conflict with SQ internal clock gating, when we have many host trap command it will trigger qcm fence timeout. Signed-off-by: James Zhu Tested-by: Vladimir Indic Reviewed-by: Vladimir Indic Signed-off-by: Asher Song --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 3 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 3 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 16 ++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 11 +++++++++-- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 +++ 6 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index af2f201eb32f9..31314ed5bb0b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -206,5 +206,6 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, - .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap + .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 01b0a33a17042..c9a4ef391f0d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -433,5 +433,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, - .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index d45923bfde87f..07f26968a598a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1259,6 +1259,22 @@ static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, return sq_hosttrap_status; } +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) +{ + uint32_t clk_cntl; + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + + RREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL); + clk_cntl = REG_SET_FIELD(clk_cntl, CGTT_SQ_CLK_CTRL, CORE_OVERRIDE, value); + WREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL, clk_cntl); + + mutex_unlock(&adev->grbm_idx_mutex); +} + uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t max_wave_slot, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 892c91a1c1b63..675054356eca6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -122,3 +122,6 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t *target_wave_slot, enum kfd_ioctl_pc_sample_method method, uint32_t inst); +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 2a9a7a9bb6e6d..72042277cc2b8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -47,6 +47,7 @@ static int kfd_pc_sample_thread(void *param) uint32_t timeout = 0; ktime_t next_trap_time; bool need_wait; + uint32_t inst; mutex_lock(&node->pcs_data.mutex); if (node->pcs_data.hosttrap_entry.base.active_count && @@ -68,11 +69,14 @@ static int kfd_pc_sample_thread(void *param) adev = node->adev; need_wait = false; allow_signal(SIGKILL); + + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 1, inst); + while (!kthread_should_stop() && !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { if (!need_wait) { - uint32_t inst; - next_trap_time = ktime_add_us(ktime_get_raw(), timeout); for_each_inst(inst, node->xcc_mask) { @@ -100,6 +104,9 @@ static int kfd_pc_sample_thread(void *param) } } } + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 0, inst); node->pcs_data.hosttrap_entry.base.target_simd = 0; node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 32f92e0ac3588..26f5a542877cc 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -346,6 +346,9 @@ struct kfd2kgd_calls { uint32_t *target_wave_slot, enum kfd_ioctl_pc_sample_method method, uint32_t inst); + void (*override_core_cg)(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From 2c202a482745ac6d6231f0fe5080cbbae6fe3386 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 16 May 2024 14:00:18 +0800 Subject: [PATCH 1269/2070] drm/amdkcl: kcl-cleanup HAVE_SMCA_UMC_V2 is_smca_umc_v2 function never occurs in upstream kernel, macro HAVE_SMCA_UMC_V2 is undefined all the time, which cause MCE notifications is not handled on MI200 A+A platform. So we drop macro HAVE_SMCA_UMC_V2. On the other hand, on Centos 7.9, SMCA_UMC_V2 is not defined in arch/x86/include/asm/mce.h, we don't care umc_v2 error notification on centos 7.9. Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++-------- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- .../gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- .../gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 17 +++++++++++++++++ 5 files changed, 22 insertions(+), 24 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 2c5d80d04c2fc..241e6c945696e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -46,10 +46,8 @@ #ifdef CONFIG_X86_MCE_AMD #include -#ifdef HAVE_SMCA_UMC_V2 static bool notifier_registered; #endif -#endif static const char *RAS_FS_NAME = "ras"; const char *ras_error_string[] = { @@ -151,7 +149,6 @@ static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev); static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev); #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); static void amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev); @@ -161,7 +158,6 @@ struct mce_notifier_adev_list { }; static struct mce_notifier_adev_list mce_adev_list; #endif -#endif void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { @@ -3906,11 +3902,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); amdgpu_ras_ecc_log_init(&con->umc_ecc_log); #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); -#endif #endif return 0; @@ -4911,7 +4905,6 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) } #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 static struct amdgpu_device *find_adev(uint32_t node_id) { int i; @@ -4947,8 +4940,10 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ +#ifdef HAVE_SMCA_UMC_V2 if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) +#endif return NOTIFY_DONE; /* @@ -5034,7 +5029,6 @@ static void amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev) } } #endif -#endif struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 473f5119fc5c1..8e5f69acb2704 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -915,8 +915,8 @@ /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 -/* is_smca_umc_v2() is available */ -/* #undef HAVE_SMCA_UMC_V2 */ +/* enum SMCA_UMC_V2 is available */ +#define HAVE_SMCA_UMC_V2 1 /* strscpy() is available */ #define HAVE_STRSCPY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 deleted file mode 100644 index 28eda1decdae2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # -dnl # is_smca_umc_v2() -dnl # -AC_DEFUN([AC_AMDGPU_CHECK_SMCA_UMC_V2], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([is_smca_umc_v2], - [arch/x86/kernel/cpu/mce/amd.c], [ - AC_DEFINE(HAVE_SMCA_UMC_V2, 1, - [is_smca_umc_v2() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c40791d364e42..02069e04b0da9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,7 +109,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION - AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_STRUCT_XARRAY @@ -208,6 +207,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY + AC_AMDGPU_SMCA_UMC_V2 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 index e3d33a862d7fb..de3f546345a28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -15,3 +15,20 @@ AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ ]) ]) ]) +dnl # +dnl # v5.13-rc3-1-g94a311ce248e +dnl # x86/MCE/AMD, EDAC/mce_amd: Add new SMCA bank types +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum smca_bank_types bank_type; + bank_type = SMCA_UMC_V2; + ], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [enum SMCA_UMC_V2 is available]) + ]) + ]) +]) From 6a1f63193b57a6ee2ac059f54c8ea981fad45d85 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 17 May 2024 11:52:59 +0800 Subject: [PATCH 1270/2070] drm/amdkcl: fake smca_get_bank_type When redefining HAVE_SMCA_UMC_V2, the fake function smca_get_bank_type is called by amdgpu_bad_page_notifier. However origin fake function can not be referenced when making intree build as it defined in amdkcl modules. So we make a macro for the fake function in backport/kcl_mce.h Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 37 +++++------------------- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_mce.h | 13 +++++++++ include/kcl/kcl_mce.h | 26 +++++++++++++---- 5 files changed, 42 insertions(+), 37 deletions(-) create mode 100644 include/kcl/backport/kcl_mce.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 241e6c945696e..8c0b39062b67a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4941,7 +4941,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * process the error, else bail out. */ #ifdef HAVE_SMCA_UMC_V2 - if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && + if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) #endif return NOTIFY_DONE; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c index bd90d447713f5..e2cd6191d7171 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -7,24 +7,11 @@ * * All MC4_MISCi registers are shared between cores on a node. */ - - #ifdef CONFIG_X86_MCE_AMD #include -#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(cpu, bank); -} -#elif defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - -/* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ -#elif defined(HAVE_STRUCT_SMCA_BANK) +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) && !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +#if defined(HAVE_STRUCT_SMCA_BANK) enum smca_bank_types smca_get_bank_type(unsigned int bank) { struct smca_bank *b; @@ -38,24 +25,14 @@ enum smca_bank_types smca_get_bank_type(unsigned int bank) return b->hwid->bank_type; } -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - #else int smca_get_bank_type(unsigned int bank) { - pr_warn_once("smca_get_bank_type is not supported\n"); - return 0; + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; } - -int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - -#endif -EXPORT_SYMBOL_GPL(kcl_smca_get_bank_type); +#endif +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif #endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5d6d8f4422c3f..3b095f9d533bc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -118,4 +118,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_mce.h b/include/kcl/backport/kcl_mce.h new file mode 100644 index 0000000000000..08c69209a1a49 --- /dev/null +++ b/include/kcl/backport/kcl_mce.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_MCE_H +#define _KCL_BACKPORT_KCL_MCE_H + +#include + +#ifdef CONFIG_X86_MCE_AMD +#ifndef HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS +#define smca_get_bank_type _kcl_smca_get_bank_type +#endif /* HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS */ +#endif /* CONFIG_X86_MCE_AMD */ + +#endif /* _KCL_BACKPORT_KCL_MCE_H */ diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index fd6098c99a240..223c2bd03bb87 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,15 +11,29 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) || defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); -#else -int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); -#endif - #ifndef HAVE_MCE_PRIO_UC #define MCE_PRIO_UC MCE_PRIO_SRAO #endif +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) +#if defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types smca_get_bank_type(unsigned int bank); +#endif +static inline +enum smca_bank_types _kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} +#else +int smca_get_bank_type(unsigned int bank); +static inline +int _kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} +#endif +#endif + #endif /* CONFIG_X86_MCE_AMD */ #endif From d75b3295fd8575b1860a9f361111b4a959979fa2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 22 May 2024 21:00:34 +0800 Subject: [PATCH 1271/2070] drm/amdkcl:test topology_num_cores_per_package whether exist It's caused by v6.8-rc4-71-g89b0f15f408f x86/cpu/topology: Get rid of cpuinfo::x86_max_cores Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 new file mode 100644 index 0000000000000..ec603c4bd1a9b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v6.8-rc4-70-gfd43b8ae76e9 +dnl # x86/cpu/topology: Provide __num_[cores|threads]_per_package +dnl # +AC_DEFUN([AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int a = 0; + a = topology_num_cores_per_package(); + ], [ + AC_DEFINE(HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE, 1, + [topology_num_cores_per_package is availablea]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 02069e04b0da9..8b6252e70b95a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -208,6 +208,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY AC_AMDGPU_SMCA_UMC_V2 + AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 08179840697e1..f4d4918e54b78 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -457,7 +457,11 @@ static int vangogh_init_smc_tables(struct smu_context *smu) #ifdef CONFIG_X86 /* AMD x86 APU only */ +#ifdef HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE smu->cpu_core_num = topology_num_cores_per_package(); +#else + smu->cpu_core_num = boot_cpu_data.x86_max_cores; +#endif #else smu->cpu_core_num = 4; #endif From 77b2029f7f173e8266d753950bdd74f72f365e25 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 13:59:58 +0800 Subject: [PATCH 1272/2070] drm/amdkcl: fake linux/pgtable.h header It's caused by v6.8-rc6-1469-g2c6f6831876a drm/ttm: make ttm_caching.h self-contained Signed-off-by: Asher Song --- include/kcl/header/linux/pgtable.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 include/kcl/header/linux/pgtable.h diff --git a/include/kcl/header/linux/pgtable.h b/include/kcl/header/linux/pgtable.h new file mode 100644 index 0000000000000..27198a089c730 --- /dev/null +++ b/include/kcl/header/linux/pgtable.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PGTABLE_H_H_ +#define _KCL_HEADER_LINUX_PGTABLE_H_H_ + +#ifdef HAVE_LINUX_PGTABLE_H +#include_next +#else +#include +#endif + +#endif From 632e5fd023e656e5a96500f2a255843c6df039a7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 14:41:31 +0800 Subject: [PATCH 1273/2070] drm/amdkcl: fake drm_info_once It's caused by v6.9-rc1-50-g27906e5d7824 drm/ttm: Print the memory decryption status just once Signed-off-by: Asher Song --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 0546bd944b72c..0506b7a41f121 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -201,4 +201,10 @@ enum drm_debug_category { __drm_printk((drm), info,, fmt, ##__VA_ARGS__) #endif +#ifndef drm_info_once +/* copied from include/drm/drm_print.h */ +#define drm_info_once(drm, fmt, ...) \ + __drm_printk((drm), info, _once, fmt, ##__VA_ARGS__) +#endif + #endif From 39a7765e88a7ba74edb4b38d21481d1fecccfa06 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 14:58:19 +0800 Subject: [PATCH 1274/2070] drm/amdkcl: Test whether drm_gem_object->resv is available It's caused by v6.8-rc6-1519-g5a95f39d9b21 drm/ttm: warn when resv objs are mixed in a bulk_move v6.4-rc2-1582-ge2ad8e2df432 drm/amdgpu: make sure BOs are locked in amdgpu_vm_get_memory Signed-off-by: Asher Song --- drivers/gpu/drm/ttm/ttm_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 666907102cbb4..e267683099718 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -233,7 +233,7 @@ static void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk, pos->first = res; pos->last = res; } else { - WARN_ON(pos->first->bo->base.resv != res->bo->base.resv); + WARN_ON(amdkcl_ttm_resvp(pos->first->bo) != amdkcl_ttm_resvp(res->bo)); ttm_lru_bulk_move_pos_tail(pos, res); } } From 8d0dad27264fe64250c9e89eab6b68adac8450ae Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 29 May 2024 17:39:47 +0800 Subject: [PATCH 1275/2070] drm/amdkcl: remove macro HAVE_AMD_IOMMU_PC_SUPPORTED Due IOMMUv2 support have been removed, this macro is not required. c99a2e7ae291e5b19b60443eb drm/amdkfd: drop IOMMUv2 support Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 18 ------------------ drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 ------ 2 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 45436e45276ac..667bbb7814911 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -115,9 +115,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; struct kfd_iolink_properties *p2plink; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; -#endif list_del(&dev->list); @@ -149,14 +147,12 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(p2plink); } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); list_del(&perf->list); kfree(perf); } -#endif kfree(dev); } @@ -193,9 +189,7 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); INIT_LIST_HEAD(&dev->p2p_link_props); -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED INIT_LIST_HEAD(&dev->perf_props); -#endif list_add_tail(&dev->list, device_list); @@ -389,7 +383,6 @@ static const struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /****** Sysfs of Performance Counters ******/ struct kfd_perf_attr { @@ -423,7 +416,6 @@ static struct kfd_perf_attr perf_attr_iommu[] = { KFD_PERF_DESC(counter_ids, 0), }; /****************************************/ -#endif static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) @@ -593,9 +585,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; -#endif if (dev->kobj_p2plink) { list_for_each_entry(p2plink, &dev->p2p_link_props, list) @@ -661,7 +651,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED if (dev->kobj_perf) { list_for_each_entry(perf, &dev->perf_props, list) { kfree(perf->attr_group); @@ -671,7 +660,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) kobject_put(dev->kobj_perf); dev->kobj_perf = NULL; } -#endif if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); @@ -690,11 +678,9 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; uint32_t num_attrs; struct attribute **attrs; -#endif int ret; uint32_t i; @@ -731,11 +717,9 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_p2plink) return -ENOMEM; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; -#endif /* * Creating sysfs files for node properties @@ -854,7 +838,6 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -880,7 +863,6 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; } -#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index a5e07857299e1..129b447fcf84d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -135,14 +135,12 @@ struct kfd_iolink_properties { struct attribute attr; }; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties { struct list_head list; char block_name[16]; uint32_t max_concurrent; struct attribute_group *attr_group; }; -#endif struct kfd_topology_device { struct list_head list; @@ -153,18 +151,14 @@ struct kfd_topology_device { struct list_head cache_props; struct list_head io_link_props; struct list_head p2p_link_props; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct list_head perf_props; -#endif struct kfd_node *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; struct kobject *kobj_p2plink; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kobject *kobj_perf; -#endif struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; From 290e006e53f1307a81e03161ab94cc49375e2352 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 May 2024 15:18:01 +0800 Subject: [PATCH 1276/2070] drm/amdgpu: fix the used uninitialized issue The vailable clk_cntl is used uninitialized, so initialize it to fix intree build issue. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 07f26968a598a..ad08db2887687 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1263,7 +1263,7 @@ void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, uint32_t value, uint32_t inst) { - uint32_t clk_cntl; + uint32_t clk_cntl = 0; mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); From 50ae5e65a41dca3ac482d140e396a18fcebd7d3c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 20 May 2024 10:57:42 +0800 Subject: [PATCH 1277/2070] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 7535d371a27cc788d8f41394a22e3fd492ee5d2c "drm/amd/pm: Add support for DPM policies" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 938361ecae055..4b8d05d157d7c 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -4774,6 +4774,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) dev_info(adev->dev, "overdrive feature is not supported\n"); } +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) != -EOPNOTSUPP) { ret = devm_device_add_group(adev->dev, @@ -4781,6 +4782,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) if (ret) goto err_out1; } +#endif if (amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) { ret = devm_device_add_group(adev->dev, From 95063f6a821c6154bac2cd331633e69ccd1f2dc3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 27 May 2024 10:54:39 +0800 Subject: [PATCH 1278/2070] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY It's caused by e3a473ed04f7f1b061860437876a269073dc302d "drm/amd/display: Enable colorspace property for MST connectors" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 634de9a42314f..ef66d7be2e916 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -755,10 +755,12 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, &connector->base, dev->mode_config.tile_property, 0); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY connector->colorspace_property = master->base.colorspace_property; if (connector->colorspace_property) drm_connector_attach_colorspace_property(connector); - +#endif drm_connector_set_path_property(connector, pathprop); if (!retrieve_branch_specific_data(aconnector)) From 4da4fc4707b26c20dc02daaa852376156675313c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 27 May 2024 10:56:52 +0800 Subject: [PATCH 1279/2070] drm/amdkcl: fake macro fuction __counted_by() It's caused by d4fa69b7bd8a7c950a0b838ca0c1feef2bb03d84 "drm/amdgpu: silence UBSAN warning" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_compiler_attributes.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h index 34d035352059c..e844e68139479 100644 --- a/include/kcl/kcl_compiler_attributes.h +++ b/include/kcl/kcl_compiler_attributes.h @@ -10,4 +10,16 @@ #define fallthrough do {} while (0) /* fallthrough */ #endif +#ifndef __has_attribute +#define __has_attribute(x) 0 +#endif + +#ifndef __counted_by +#if __has_attribute(__counted_by__) +# define __counted_by(member) __attribute__((__counted_by__(member))) +#else +# define __counted_by(member) +#endif +#endif + #endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ From 299d68424de7dc09517a79a3500c8beb1d377b64 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 28 May 2024 14:45:06 +0800 Subject: [PATCH 1280/2070] drm/amd/display: add judge condition to fix intree build issue Due to dkms backport includes ASSERT macro, so add judge condition to avoid redefined macro. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c index e17b5ceba4471..3bb835b5585ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c @@ -4,7 +4,9 @@ #include "lib_float_math.h" +#ifndef ASSERT #define ASSERT(condition) +#endif #define isNaN(number) ((number) != (number)) From 786d6c8f22b433460f15be44f5f62c6233f6b9cb Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Thu, 30 May 2024 14:07:15 -0700 Subject: [PATCH 1281/2070] drm/amdkfd: Fix various crash, hang and corruption issues for KFD SPM support 1. Need to convert drm_priv to amdgpu_vm when calling amdgpu_amdkfd_rlc_spm_*() functions. 2. Per RLC spec, ring_wptr = 0 and ring_rptr = 0 point to mmRLC_SPM_PERFMON_RING_BASE+0x20, change code accordingly. Signed-off-by: Bing Ma Reviewed-by: Harish Kasiviwanathan --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 00da1cabcbd45..6480e9c49f608 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -39,7 +39,6 @@ struct kfd_spm_cntr { struct mutex spm_worker_mutex; u64 gpu_addr; u32 ring_size; - u32 ring_mask; u32 ring_rptr; u32 size_copied; u32 has_data_loss; @@ -63,7 +62,8 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) return -EFAULT; user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); - ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr); + // From RLC spec, ring_rptr = 0 points to spm->cpu_addr+0x20 + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); if (user_address == NULL) return -EFAULT; @@ -101,7 +101,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) int ret = 0; u32 ring_wptr; - ring_wptr = READ_ONCE(spm->cpu_addr[0]) & spm->ring_mask; + ring_wptr = READ_ONCE(spm->cpu_addr[0]); /* keep SPM ring buffer running */ if (!spm->has_user_buf || spm->is_user_buf_filled) { @@ -118,13 +118,6 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (spm->ring_rptr == ring_wptr) goto exit; - if ((spm->ring_rptr >= 0) && (spm->ring_rptr < 0x20)) { - /* - * First 8DW, only use for WritePtr, it is not Counter data - */ - spm->ring_rptr = 0x20; - } - if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -139,7 +132,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->ring_rptr = ring_wptr; goto exit; } - spm->ring_rptr = 0x20; + spm->ring_rptr = 0; size_to_copy = ring_wptr - spm->ring_rptr; if (!ret) ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -192,12 +185,10 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device mutex_unlock(&pdd->spm_mutex); return -ENOMEM; } - mutex_unlock(&pdd->spm_mutex); /* git spm ring buffer 4M */ pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); - pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4 - 0xff; - pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; + pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4; pdd->spm_cntr->has_user_buf = false; ret = amdgpu_amdkfd_alloc_gtt_mem(adev, @@ -208,7 +199,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, pdd->drm_priv, + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -233,12 +224,11 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: - mutex_lock(&pdd->spm_mutex); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; - mutex_unlock(&pdd->spm_mutex); out: + mutex_unlock(&pdd->spm_mutex); return ret; } @@ -259,7 +249,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(adev, pdd->drm_priv); + amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From 81e0952e5da1bbce5d8f09585460edf0020b0c22 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:39:28 +0800 Subject: [PATCH 1282/2070] drm/amdkcl: Test drm_atomic_plane_enabling() is available It's caused by 1d0c9ded451944ef616149be5fe4a7d9a9d428da "drm/amd/display: Introduce overlay cursor mode" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 16 ++++++++++++++++ 4 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8e5f69acb2704..e775d523ec883 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -183,6 +183,9 @@ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 +/* drm_atomic_plane_enabling() is available */ +#define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 + /* drm_client_register() is available */ #define HAVE_DRM_CLIENT_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 new file mode 100644 index 0000000000000..5fe466630d8dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc6-1230-g169b9182f192 +dnl # drm/atomic-helper: Add atomic_enable plane-helper callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_atomic_plane_enabling(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_ATOMIC_PLANE_ENABLING, 1, + [drm_atomic_plane_enabling() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8b6252e70b95a..82e14d50b95ae 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -78,6 +78,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 7bedeace08ad0..3af6d075cbe99 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -58,4 +58,20 @@ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); #endif +#ifndef HAVE_DRM_ATOMIC_PLANE_ENABLING +static inline bool drm_atomic_plane_enabling(struct drm_plane_state *old_plane_state, + struct drm_plane_state *new_plane_state) +{ + /* + * When enabling a plane, CRTC and FB should always be set together. + * Anything else should be considered a bug in the atomic core, so we + * gently warn about it. + */ + WARN_ON((!new_plane_state->crtc && new_plane_state->fb) || + (new_plane_state->crtc && !new_plane_state->fb)); + + return !old_plane_state->crtc && new_plane_state->crtc; +} +#endif + #endif From 00035834089e7329759cf6761e3a1f40ed2f7b03 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 17 Jun 2024 14:41:40 -0400 Subject: [PATCH 1283/2070] drm/amdkfd: remove gfx(9, 4, 1) pc sampling support Since it is not stable on stress test. Signed-off-by: James Zhu Reviewed-by: Felix Kuehling Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 72042277cc2b8..de91e4e53df6a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -36,7 +36,6 @@ const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; struct supported_pc_sample_info supported_formats[] = { - { IP_VERSION(9, 4, 1), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, }; From 5b0eb61df366001c1a4122be4fb09ced25472431 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 17 Jun 2024 15:12:30 -0400 Subject: [PATCH 1284/2070] drm/amdkfd: use version field to pass back pc sampling revision temporarily not for upstream. -v2: fix typo -v3: rename kfd_ioctl_pc_sample_args "reserved" to "version" Signed-off-by: James Zhu Reviewed-by: Felix Kuehling Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 11 +++++++++++ include/uapi/linux/kfd_ioctl.h | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index de91e4e53df6a..435ebba8c0de7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -27,6 +27,14 @@ #include "kfd_debug.h" #include "kfd_device_queue_manager.h" +/* + * PC Sampling revision change log + * + * 0.1 - Initial revision + */ +#define KFD_IOCTL_PCS_MAJOR_VERSION 0 +#define KFD_IOCTL_PCS_MINOR_VERSION 1 + struct supported_pc_sample_info { uint32_t ip_version; const struct kfd_pc_sample_info *sample_info; @@ -142,6 +150,9 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, int i; const uint32_t user_num_sample_info = user_args->num_sample_info; + /* use version field to pass back pc sampling revision temporarily, not for upstream */ + user_args->version = KFD_IOCTL_PCS_MAJOR_VERSION << 16 | KFD_IOCTL_PCS_MINOR_VERSION; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) num_method++; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 063ff133ae0a5..7b03f3ffaac6b 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1729,7 +1729,7 @@ struct kfd_ioctl_pc_sample_args { __u32 gpu_id; __u32 trace_id; __u32 flags; /* kfd_ioctl_pcs_query flags */ - __u32 reserved; + __u32 version; }; #define AMDKFD_IOCTL_BASE 'K' From c2c0d534ce4378637d9507b0671ae36f4835d420 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:28:41 +0800 Subject: [PATCH 1285/2070] drm/amdkcl: fake macros DP_LINK_BW_{10/13_5/20} It's caused by 13ba1f22181d90f4d62f9103351581b94d2442b2 "drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_dp.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 25c848be0df94..7f3607f89c6a4 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -76,4 +76,12 @@ #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 #endif +/* v5.9-rc5-1031-g7d56927efac7 * + * drm/dp: add a number of DP 2.0 DPCD definitions */ +#ifndef DP_LINK_BW_10 +#define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ +#define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ +#define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ +#endif + #endif \ No newline at end of file From 035ebea2c9e12fd53db7ae5f3adff57c74ca0099 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Jun 2024 16:46:37 +0800 Subject: [PATCH 1286/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS It's caused by 583ed0fe6bff86af2ce28a451f31cfa0c36013d1 "drm/amd/display: Introduce overlay cursor mode" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index e8245edd980f1..f08196f97f995 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1311,8 +1311,12 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, return -EINVAL; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS new_plane_state = drm_atomic_get_new_plane_state(state, plane); new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + new_crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); /* Reject overlay cursors for now*/ if (!flip && dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) From 60ebd4bedf1c0a26fb1d4cc39d8b6d52f52124a8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Jul 2024 16:28:43 +0800 Subject: [PATCH 1287/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by f12e6db4a019bcb24dc99a909534dec35bcdd408 "drm/amd/display: Fix refresh rate range for some panel" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7850c180c0c14..15a7d6767daf1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13274,6 +13274,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, return ret; } +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE static void parse_edid_displayid_vrr(struct drm_connector *connector, const struct edid *edid) { @@ -13316,6 +13317,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, j++; } } +#endif static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) @@ -13454,10 +13456,12 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE /* Some eDP panels only have the refresh rate range info in DisplayID */ if ((connector->display_info.monitor_range.min_vfreq == 0 || connector->display_info.monitor_range.max_vfreq == 0)) parse_edid_displayid_vrr(connector, edid); +#endif if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || sink->sink_signal == SIGNAL_TYPE_EDP)) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index f08196f97f995..a72279afb4357 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -169,12 +169,10 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 *size += 1; } -#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); } -#endif static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) { From 77a34793f4d7aba44759cdaa97cddd875be99ec7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Jul 2024 16:27:27 +0800 Subject: [PATCH 1288/2070] drm/amdkcl: fake macro AMD_FMT_MOD_TILE_GFX12_* It's caused by 2146fa1d796c804c337ea2fee8f2628bda4eb2ab "drm/amdgpu/display: add all gfx12 modifiers" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_fourcc.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 9b1a99ec6d52b..cc36737aafae0 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -233,4 +233,13 @@ #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #endif +#ifndef AMD_FMT_MOD_TILE_GFX12_256B_2D +#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 +#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 +#endif + +#ifndef AMD_FMT_MOD_TILE_GFX12_256K_2D +#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From 282f9e0da6d2949382153b7f1aef764891d2fe80 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Jun 2024 11:00:46 +0530 Subject: [PATCH 1289/2070] drm/amd/pm: Add phase detect control support Add support to tune phase detect parameters. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/include/kgd_pp_interface.h | 9 ++++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 53 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 36 +++++++++++++ 3 files changed, 98 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index bdf8e6ff556cf..7f7136be4a5c0 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -312,6 +312,15 @@ enum pp_policy_soc_pstate { #define PP_POLICY_MAX_LEVELS 5 +enum pp_pm_phase_det_param_id { + PP_PM_PHASE_DET_LO_FREQ = 0, + PP_PM_PHASE_DET_HI_FREQ = 1, + PP_PM_PHASE_DET_THRESH = 2, + PP_PM_PHASE_DET_ALPHA = 3, + PP_PM_PHASE_DET_HYST = 4, + PP_PM_PHASE_DET_ALL = 5, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 18ece5c714c5e..f9ff832e4be2d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4164,3 +4164,56 @@ int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return 0; } + +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->set) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->set(smu, id, val); +} + +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get) + return -EOPNOTSUPP; + + return pd_ctl->ops->get(smu, id, val); +} + +int smu_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->enable) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->enable(smu, enable); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index a6303d093c50e..82fff27561bc3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -438,6 +438,34 @@ struct smu_dpm_policy_ctxt { unsigned long policy_mask; }; +struct smu_phase_det_params { + uint32_t freq_hi; + uint32_t freq_lo; + uint32_t thresh; + uint32_t hyst; + uint32_t alpha; +}; + +struct smu_phase_det_ops { + int (*set)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t val); + int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t *val); + int (*enable)(struct smu_context *smu, bool enable); +}; + +enum phase_det_state { + SMU_PHASE_DET_OFF = 0, + SMU_PHASE_DET_ON = 1, + SMU_PHASE_DET_DISABLED = -1, +}; + +struct smu_phase_det_ctl { + struct smu_phase_det_params params; + struct smu_phase_det_ops *ops; + enum phase_det_state status; +}; + struct smu_dpm_context { uint32_t dpm_context_size; void *dpm_context; @@ -449,6 +477,7 @@ struct smu_dpm_context { struct smu_power_state *dpm_current_power_state; struct mclock_latency_table *mclk_latency_table; struct smu_dpm_policy_ctxt *dpm_policies; + struct smu_phase_det_ctl *pd_ctl; }; struct smu_temp_context { @@ -1995,8 +2024,15 @@ ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle); +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val); +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val); +int smu_phase_det_enable(struct smu_context *smu, bool enable); + int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, uint32_t param, uint32_t *readarg); + #endif void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); From 16399bd282b66b8e205344016253a6876865dd62 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Jun 2024 16:35:36 +0530 Subject: [PATCH 1290/2070] drm/amd/pm: Add debugfs controls for phase detect Add debugfs nodes for enabling/disabling and tuning parameters used in phase detect. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 8 ++ drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 + drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 96 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + 5 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b4749..930c99e212fc2 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -2111,6 +2111,14 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, return ret; } +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev) +{ + if (!is_support_sw_smu(adev)) + return; + + amdgpu_smu_phase_det_debugfs_init(adev); +} + const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) { void *pp_handle = adev->powerplay.pp_handle; diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 4b8d05d157d7c..474624ed42ad3 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -5107,5 +5107,6 @@ void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) adev->pm.smu_prv_buffer_size); amdgpu_dpm_stb_debug_fs_init(adev); + amdgpu_dpm_phase_det_debugfs_init(adev); #endif } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index aa3f427819a09..6a73df27088e4 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -608,6 +608,7 @@ ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf); int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev); +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev); bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index f9ff832e4be2d..7144cdd5af9a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4217,3 +4217,99 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable) return pd_ctl->ops->enable(smu, enable); } + +#if defined(CONFIG_DEBUG_FS) + +static int smu_phase_det_debugfs_status(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + + *val = pd_ctl->status; + + return 0; +} + +static int smu_phase_det_debugfs_enable(void *data, u64 val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct amdgpu_device *adev = smu->adev; + + if (amdgpu_in_reset(adev) || adev->in_suspend) + return -EPERM; + + return smu_phase_det_enable(smu, !!val); +} + +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") + +DEBUGFS_PHASE_DET_FOPS(LO_FREQ); +DEBUGFS_PHASE_DET_FOPS(HI_FREQ); +DEBUGFS_PHASE_DET_FOPS(THRESH); +DEBUGFS_PHASE_DET_FOPS(ALPHA); +DEBUGFS_PHASE_DET_FOPS(HYST); + +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); + +#define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ + debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) + +#define AMDGPU_SMU_PHASE_DET "smu_phase_detect" +#endif + +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + + struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + struct dentry *dir; + + pd_ctl = dpm_ctxt->pd_ctl; + + if (!smu || !pd_ctl) + return; + + dir = debugfs_create_dir(AMDGPU_SMU_PHASE_DET, + adev_to_drm(adev)->primary->debugfs_root); + + debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); + DEBUGFS_CREATE_PHASE_DET_ATTR(alpha, ALPHA); + DEBUGFS_CREATE_PHASE_DET_ATTR(hyst, HYST); + +#endif +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 82fff27561bc3..e4ab6ded9aac5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -2029,6 +2029,7 @@ int smu_set_phase_det_param(struct smu_context *smu, int smu_get_phase_det_param(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t *val); int smu_phase_det_enable(struct smu_context *smu, bool enable); +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, uint32_t param, uint32_t *readarg); From e54423c8725ccc20f2d5165ac5994dd1ed0e158b Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 26 Jun 2024 13:15:32 +0530 Subject: [PATCH 1291/2070] drm/amd/pm: Add phase detect support to SMUv13.0.6 Add support for enabling phase detect and tuning params for SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 6 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 6 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 162 ++++++++++++++++-- 4 files changed, 161 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index 63a088ef71693..3cb2ce259e9ad 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -93,6 +93,12 @@ #define PPSMC_MSG_SelectPLPDMode 0x40 #define PPSMC_MSG_RmaDueToBadPageThreshold 0x43 #define PPSMC_MSG_SetThrottlingPolicy 0x44 +#define PPSMC_MSG_SetPhsDetWRbwThreshold 0x45 +#define PPSMC_MSG_SetPhsDetWRbwFreqHigh 0x46 +#define PPSMC_MSG_SetPhsDetWRbwFreqLow 0x47 +#define PPSMC_MSG_SetPhsDetWRbwHystDown 0x48 +#define PPSMC_MSG_SetPhsDetWRbwAlpha 0x49 +#define PPSMC_MSG_SetPhsDetOnOff 0x4A #define PPSMC_MSG_ResetSDMA 0x4D #define PPSMC_MSG_GetStaticMetricsTable 0x59 #define PPSMC_MSG_ResetVCN 0x5B diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 584c4cfd0c16f..e7d2569b76a06 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -276,6 +276,12 @@ __SMU_DUMMY_MAP(SetThrottlingPolicy), \ __SMU_DUMMY_MAP(MALLPowerController), \ __SMU_DUMMY_MAP(MALLPowerState), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwThreshold), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwFreqHigh), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwFreqLow), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwHystDown), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwAlpha), \ + __SMU_DUMMY_MAP(SetPhsDetOnOff), \ __SMU_DUMMY_MAP(ResetSDMA), \ __SMU_DUMMY_MAP(ResetVCN), \ __SMU_DUMMY_MAP(GetStaticMetricsTable), \ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 950cc8ec1ddc7..330f1e615b1bf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -531,6 +531,7 @@ int smu_v13_0_fini_smc_tables(struct smu_context *smu) smu_table->watermarks_table = NULL; smu_table->metrics_time = 0; + kfree(smu_dpm->pd_ctl); kfree(smu_dpm->dpm_policies); kfree(smu_dpm->dpm_context); kfree(smu_dpm->golden_dpm_context); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 07592e285cf56..156b85cb64990 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -179,6 +179,12 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), + MSG_MAP(SetPhsDetWRbwThreshold, PPSMC_MSG_SetPhsDetWRbwThreshold, 0), + MSG_MAP(SetPhsDetWRbwFreqHigh, PPSMC_MSG_SetPhsDetWRbwFreqHigh, 0), + MSG_MAP(SetPhsDetWRbwFreqLow, PPSMC_MSG_SetPhsDetWRbwFreqLow, 0), + MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), + MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), + MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), }; // clang-format on @@ -684,6 +690,112 @@ static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level) return ret; } +static int smu_v13_0_6_phase_det_set(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + uint32_t *param; + int r, msg_id; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqLow; + param = &pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqHigh; + param = &pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + msg_id = SMU_MSG_SetPhsDetWRbwThreshold; + param = &pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + msg_id = SMU_MSG_SetPhsDetWRbwAlpha; + param = &pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + msg_id = SMU_MSG_SetPhsDetWRbwHystDown; + param = &pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + r = smu_cmn_send_smc_msg_with_param(smu, msg_id, val, NULL); + if (!r) + *param = val; + + return r; +} + +static int smu_v13_0_6_phase_det_get(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t *val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl || !val) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + *val = pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + *val = pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + *val = pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + *val = pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + *val = pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + int r; + + pd_ctl = smu_dpm->pd_ctl; + r = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPhsDetOnOff, enable, + NULL); + + if (!r) { + pd_ctl->status = enable ? SMU_PHASE_DET_ON : SMU_PHASE_DET_OFF; + } else { + dev_warn(smu->adev->dev, "Phase detect %s failed", + enable ? "enable" : "disable"); + pd_ctl->status = SMU_PHASE_DET_DISABLED; + } + + return r; +} + +static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { + .set = smu_v13_0_6_phase_det_set, + .get = smu_v13_0_6_phase_det_get, + .enable = smu_v13_0_6_phase_det_enable, +}; + static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -702,6 +814,17 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } + smu_dpm->pd_ctl = kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, sizeof(struct smu_phase_det_params)); + if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -1086,6 +1209,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; struct smu_table_context *smu_table = &smu->smu_table; struct smu_dpm_table *dpm_table = NULL; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; uint32_t gfxclkmin, gfxclkmax, levels; @@ -1118,6 +1242,12 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } + if (smu_dpm->pd_ctl && !(smu->adev->flags & AMD_IS_APU) && + (smu->smc_fw_version < 0x00556E00)) { + kfree(smu_dpm->pd_ctl); + smu_dpm->pd_ctl = NULL; + } + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; @@ -3146,6 +3276,23 @@ static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu) return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET)); } +static int smu_v13_0_6_post_init(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + bool enable; + + pd_ctl = smu_dpm->pd_ctl; + + if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) + return 0; + + enable = (pd_ctl->status == SMU_PHASE_DET_ON) ? true : false; + smu_v13_0_6_phase_det_enable(smu, enable); + + return 0; +} + static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) { int ret = 0; @@ -3177,20 +3324,6 @@ static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_ty return ret; } -static int smu_v13_0_6_post_init(struct smu_context *smu) -{ - if (smu_v13_0_6_is_link_reset_supported(smu)) - smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET); - - if (smu_v13_0_6_reset_sdma_is_supported(smu)) - smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); - - if (smu_v13_0_6_reset_vcn_is_supported(smu)) - smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET); - - return 0; -} - static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) { struct smu_context *smu = adev->powerplay.pp_handle; @@ -3891,6 +4024,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num, .send_rma_reason = smu_v13_0_6_send_rma_reason, .reset_sdma = smu_v13_0_6_reset_sdma, + .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, .post_init = smu_v13_0_6_post_init, .ras_send_msg = smu_v13_0_6_ras_send_msg, From 18bfd4c58ef1987c803acab6c9179bc33f1206a9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 8 Jul 2024 16:14:55 +0800 Subject: [PATCH 1292/2070] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 4134c8ebf636e6d2d5b43c1a246b21d833bf9651 "drm/amd/pm: Add debugfs controls for phase detect" Signed-off-by: Bob Zhou Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 7144cdd5af9a5..6b5fd80ee9df2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4244,6 +4244,7 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) return smu_phase_det_enable(smu, !!val); } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE #define DEBUGFS_PHASE_DET_FOPS(param) \ static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ { \ @@ -4270,6 +4271,34 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ smu_phase_det_fops_##param##_get, \ smu_phase_det_fops_##param##_set, "%llu\n") +#else +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") +#endif DEBUGFS_PHASE_DET_FOPS(LO_FREQ); DEBUGFS_PHASE_DET_FOPS(HI_FREQ); @@ -4277,8 +4306,13 @@ DEBUGFS_PHASE_DET_FOPS(THRESH); DEBUGFS_PHASE_DET_FOPS(ALPHA); DEBUGFS_PHASE_DET_FOPS(HYST); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); +#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) From dd41380e8eb2ed669c4d47f9fdfe231d348e04a6 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Jul 2024 17:45:27 +0530 Subject: [PATCH 1293/2070] drm/amd/pm: Restrict phase detect to SMUv13.0.6 Phase detect controls are only available for SMUv13.0.6 dGPUs. Create control object only on those. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Hawking Zhang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 156b85cb64990..bc420e60b6f83 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -814,17 +814,22 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } - smu_dpm->pd_ctl = kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); - if (!smu_dpm->pd_ctl) { - kfree(smu_dpm->dpm_policies); - kfree(smu_dpm->dpm_context); - return -ENOMEM; - } - smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; - smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; - /* Init to 0xFF to indicate that present values are unknown */ - memset(&smu_dpm->pd_ctl->params, 0xFF, sizeof(struct smu_phase_det_params)); + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) && + !(smu->adev->flags & AMD_IS_APU)) { + smu_dpm->pd_ctl = + kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, + sizeof(struct smu_phase_det_params)); + } if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -1242,8 +1247,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } - if (smu_dpm->pd_ctl && !(smu->adev->flags & AMD_IS_APU) && - (smu->smc_fw_version < 0x00556E00)) { + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556E00)) { kfree(smu_dpm->pd_ctl); smu_dpm->pd_ctl = NULL; } From 337ccec0a31f9abd9a89d0414a91d96f2be1a94a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Jul 2024 15:42:08 +0800 Subject: [PATCH 1294/2070] drm/amdkcl: cleanup dma-resv stuff Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 7 ++++--- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 +++++------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6fe8eec72cb21..5bbea8dc4d3d3 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,7 @@ amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o -amdkcl-y += dma-buf/dma-resv.o +amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_seq_file.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index dc92c2d10f23d..f2a2cdcbf3165 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -32,6 +32,10 @@ /* * Authors: Thomas Hellstrom */ + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + #include #include #include @@ -41,9 +45,6 @@ #include #include -/* Copied from drivers/dma-buf/dma-resv.c */ -#ifndef HAVE_DMA_RESV_FENCES - /** * DOC: Reservation Object Overview * diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 5f922ec16986c..ec0c41cd4411e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -34,10 +34,12 @@ version_le () { source $KCL/files sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ - -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h \ - -e '/struct dma_resv_iter {/, /}/d' $INC/linux/dma-resv.h \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h # add amd prefix to exported symbols @@ -86,7 +88,3 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi - -if ! grep -q 'define HAVE_DMA_RESV_FENCES' $SRC/config/config.h; then - sed -i 's|dma-buf/dma-resv.o|kcl_dma-resv.o|' amd/amdkcl/Makefile -fi From 7d48a8f6758abf85cf8ff760743c3f07d0d046d5 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 1 Mar 2024 11:25:34 -0500 Subject: [PATCH 1295/2070] drm/amdkfd: add Host Trap Sampling support on gfx943 Add Host Trap Sampling support on gfx943. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index 89a45a9218f3f..b9d226aa7b133 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,17 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -555,5 +566,7 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; From 70f2eacd4189cc81182a38ed4f383602eaa7821e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:21:23 -0400 Subject: [PATCH 1296/2070] drm/amdkfd: enable Host Trap PC sampling for gfx943 Enable Host Trap PC sampling for gfx943. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 435ebba8c0de7..c829676d631a6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -31,9 +31,10 @@ * PC Sampling revision change log * * 0.1 - Initial revision + * 0.2 - Support gfx9_4_3 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 2 struct supported_pc_sample_info { uint32_t ip_version; @@ -45,6 +46,7 @@ const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From a31d557c7304012400dcc9c62a1417b36f2e6021 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 30 Jul 2024 16:25:47 +0800 Subject: [PATCH 1297/2070] drm/amdkcl: fake drm_edid_{alloc/free/raw/valid}() It's caused by 1dc166feb7e808f16ec2289bf1da3adb7018248a "drm/amdgpu: convert bios_hardcoded_edid to drm_edid" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 95 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 9 ++ drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 | 57 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_edid.h | 34 +++++++ 6 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5bbea8dc4d3d3..b113c725c0e7e 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_drm_print.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c new file mode 100644 index 0000000000000..c5272121a0ab4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include + +#ifndef HAVE_DRM_EDID_MALLOC +static const struct drm_edid *__kcl_drm_edid_alloc(const void *edid, size_t size) +{ + struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); + if (drm_edid) { + drm_edid->edid = edid; + drm_edid->size = size; + } + + return drm_edid; +} + +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size) +{ + const struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + edid = kmemdup(edid, size, GFP_KERNEL); + if (!edid) + return NULL; + + drm_edid = __kcl_drm_edid_alloc(edid, size); + if (!drm_edid) + kfree(edid); + + return drm_edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_alloc); + +void _kcl_drm_edid_free(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return; + + kfree(drm_edid->edid); + kfree(drm_edid); +} +EXPORT_SYMBOL(_kcl_drm_edid_free); +#endif + +#ifndef HAVE_DRM_EDID_RAW +static int edid_extension_block_count(const struct edid *edid) +{ + return edid->extensions; +} + +static int edid_block_count(const struct edid *edid) +{ + return edid_extension_block_count(edid) + 1; +} + +static int edid_size_by_blocks(int num_blocks) +{ + return num_blocks * EDID_LENGTH; +} + +static int edid_size(const struct edid *edid) +{ + return edid_size_by_blocks(edid_block_count(edid)); +} + +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid) +{ + if (!drm_edid || !drm_edid->size) + return NULL; + + /* + * Do not return pointers where relying on EDID extension count would + * lead to buffer overflow. + */ + if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) + return NULL; + + return drm_edid->edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_raw); +#endif + diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e775d523ec883..6de7b509d62e0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -494,6 +494,9 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_alloc() is available */ +#define HAVE_DRM_EDID_MALLOC 1 + /* drm_edid_override_connector_update() is available */ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 @@ -504,6 +507,12 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 +/* drm_edid_raw() is available */ +#define HAVE_DRM_EDID_RAW 1 + +/* drm_edid_valid() is available */ +#define HAVE_DRM_EDID_VALID 1 + /* drm_exec() has 3 arguments */ #define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 new file mode 100644 index 0000000000000..86301a9a861f4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.18-rc5-1218-g6537f79a2aae +dnl # drm/edid: add new interfaces around struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_MALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_alloc(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_EDID_MALLOC, 1, + [drm_edid_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v5.19-rc2-380-g3d1ab66e043f +dnl # drm/edid: add drm_edid_raw() to access the raw EDID data +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_RAW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_raw(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_RAW, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1-145-g6c9b3db70aad +dnl # drm/edid: add function for checking drm_edid validity +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_VALID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_valid(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_VALID, 1, + [drm_edid_valid() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_EDID], [ + AC_AMDGPU_DRM_EDID_MALLOC + AC_AMDGPU_DRM_EDID_RAW + AC_AMDGPU_DRM_EDID_VALID +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 82e14d50b95ae..d6b81ea66fbce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -173,6 +173,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_SHRINKER + AC_AMDGPU_STRUCT_DRM_EDID AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 0e5b0fab8f8e3..05afadb754485 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -22,4 +22,38 @@ #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ #endif + +/* commit v5.18-rc5-1046-ge4ccf9a777d3 + drm/edid: add struct drm_edid container */ +#if !defined(HAVE_DRM_EDID_MALLOC) || !defined(HAVE_DRM_EDID_RAW) || !defined(HAVE_DRM_EDID_VALID) +struct drm_edid { + /* Size allocated for edid */ + size_t size; + const struct edid *edid; +}; +#endif + +#ifndef HAVE_DRM_EDID_MALLOC +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size); +void _kcl_drm_edid_free(const struct drm_edid *drm_edid); +#define drm_edid_alloc _kcl_drm_edid_alloc +#define drm_edid_free _kcl_drm_edid_free +#endif + +#ifndef HAVE_DRM_EDID_RAW +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid); +#define drm_edid_raw _kcl_drm_edid_raw +#endif + +#ifndef HAVE_DRM_EDID_VALID +static inline bool _kcl_drm_edid_valid(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return false; + + return drm_edid_is_valid(drm_edid->edid); +} +#define drm_edid_valid _kcl_drm_edid_valid +#endif + #endif From a83495638b53a5125b8f3c241a6f4136b5d84090 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 15 Jul 2024 15:46:30 +0530 Subject: [PATCH 1298/2070] drm/amd/pm: Add phase detect residency support Add support to get phase detect residency through debugfs Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 + 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 6b5fd80ee9df2..5e3ce937bd4e5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4218,8 +4218,40 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable) return pd_ctl->ops->enable(smu, enable); } +static int smu_phase_det_get_residency(struct smu_context *smu, uint32_t *res) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get_residency) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->get_residency(smu, res); +} + #if defined(CONFIG_DEBUG_FS) +static int smu_phase_det_debugfs_get_residency(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + uint32_t res; + int r; + + r = smu_phase_det_get_residency(smu, &res); + if (r) + return r; + *val = res; + + return 0; +} + static int smu_phase_det_debugfs_status(void *data, u64 *val) { struct smu_context *smu = (struct smu_context *)data; @@ -4314,6 +4346,9 @@ DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); #endif +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); + #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) @@ -4339,6 +4374,10 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + if (pd_ctl->ops->get_residency) + debugfs_create_file("residency", 0444, dir, smu, + &smu_phase_det_fops_res); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index e4ab6ded9aac5..c22de58dc0ec7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -452,6 +452,7 @@ struct smu_phase_det_ops { int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t *val); int (*enable)(struct smu_context *smu, bool enable); + int (*get_residency)(struct smu_context *smu, uint32_t *res); }; enum phase_det_state { @@ -464,6 +465,7 @@ struct smu_phase_det_ctl { struct smu_phase_det_params params; struct smu_phase_det_ops *ops; enum phase_det_state status; + uint32_t residency; }; struct smu_dpm_context { From 2186cdf34c7e079d9003f527dfc85eb8231d4618 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 15 Jul 2024 16:46:08 +0530 Subject: [PATCH 1299/2070] drm/amd/pm: Add SMUv13.0.6 phase detect residency Add support to get phase detect residency information on SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 1 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 1 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 24 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index 3cb2ce259e9ad..8a87ff43cbb2d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -99,6 +99,7 @@ #define PPSMC_MSG_SetPhsDetWRbwHystDown 0x48 #define PPSMC_MSG_SetPhsDetWRbwAlpha 0x49 #define PPSMC_MSG_SetPhsDetOnOff 0x4A +#define PPSMC_MSG_GetPhsDetResidency 0x4B #define PPSMC_MSG_ResetSDMA 0x4D #define PPSMC_MSG_GetStaticMetricsTable 0x59 #define PPSMC_MSG_ResetVCN 0x5B diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index e7d2569b76a06..a4e283a3a1c9b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -282,6 +282,7 @@ __SMU_DUMMY_MAP(SetPhsDetWRbwHystDown), \ __SMU_DUMMY_MAP(SetPhsDetWRbwAlpha), \ __SMU_DUMMY_MAP(SetPhsDetOnOff), \ + __SMU_DUMMY_MAP(GetPhsDetResidency), \ __SMU_DUMMY_MAP(ResetSDMA), \ __SMU_DUMMY_MAP(ResetVCN), \ __SMU_DUMMY_MAP(GetStaticMetricsTable), \ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index bc420e60b6f83..6f95abcc8ea44 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -185,6 +185,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), + MSG_MAP(GetPhsDetResidency, PPSMC_MSG_GetPhsDetResidency, 0), }; // clang-format on @@ -790,10 +791,30 @@ static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) return r; } +static int smu_v13_0_6_phase_det_get_residency(struct smu_context *smu, + uint32_t *res) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + + if (!res) + return -EINVAL; + + if (pd_ctl->status != SMU_PHASE_DET_ON) { + *res = 0; + return 0; + } + + return smu_cmn_send_smc_msg(smu, SMU_MSG_GetPhsDetResidency, res); +} + static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { .set = smu_v13_0_6_phase_det_set, .get = smu_v13_0_6_phase_det_get, .enable = smu_v13_0_6_phase_det_enable, + .get_residency = smu_v13_0_6_phase_det_get_residency, }; static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) @@ -1252,6 +1273,9 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) smu_dpm->pd_ctl = NULL; } + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556F78)) + smu_dpm->pd_ctl->ops->get_residency = NULL; + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; From d8d8402009c29049d5f3d61cf7b1d1b9829df73c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 8 Aug 2024 17:08:05 +0800 Subject: [PATCH 1300/2070] drm/amdkcl: add oot build support Signed-off-by: Flora Cui Signed-off-by: Bob Zhou Reviewed-by: Horatio Zhang --- drivers/gpu/drm/amd/dkms/oot/Makefile.oot | 41 ++++++++ drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 96 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/oot/pre-build.sh | 91 ++++++++++++++++++ 3 files changed, 228 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/oot/Makefile.oot create mode 100644 drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec create mode 100644 drivers/gpu/drm/amd/dkms/oot/pre-build.sh diff --git a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot new file mode 100644 index 0000000000000..5c8c78df4e932 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot @@ -0,0 +1,41 @@ +ifneq ($(KERNELRELEASE),) +include $(src)/amd/dkms/Makefile +else +KERNELVER := $(shell uname -r) +kernel_build_dir := /lib/modules/$(KERNELVER)/build +PACKAGE_NAME := $(shell sed -n '/PACKAGE_NAME/s|.*=||p' amd/dkms/dkms.conf) +PACKAGE_VERSION := $(shell sed -n '/PACKAGE_VERSION/s|.*=||p' amd/dkms/dkms.conf) +module_src_dir := $(CURDIR) +module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) +module_build_flags := +num_cpu_cores := $(shell nproc) +Q := @ + +ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) +$(error "invalid kernel obj dir, is kernel-devel installed?") +endif + +.PHONY: modules pre-build + +include $(kernel_build_dir)/include/config/auto.conf + +ifneq ($(CONFIG_CC_IS_CLANG),) +module_build_flags += CC=clang +endif +ifneq ($(CONFIG_LD_IS_LLD),) +module_build_flags += LD=ld.lld +endif + +modules:pre-build + $(Q)make -j$(num_cpu_cores) KERNELRELEASE=$(KERNELVER) \ + TTM_NAME=amdttm \ + SCHED_NAME=amd-sched \ + -C $(kernel_build_dir) \ + M=$(module_build_dir) $(module_build_flags) + $(Q)unlink $(module_build_dir) + +pre-build: + $(Q)cp -f amd/dkms/oot/pre-build.sh amd/dkms + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(PACKAGE_NAME) $(PACKAGE_VERSION) $(module_build_dir) + +endif diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec new file mode 100644 index 0000000000000..dd92860353f46 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -0,0 +1,96 @@ +%global pkg amdgpu +%global kernel kernel version +%define pkg_version 6.8.7 +%define osdb_version 1798298 +%define anolis_release 1 + +%global debug_package %{nil} + +Name: kmod-%{pkg} +Version: %(echo %{kernel} | sed -E 's/-/~/g; s/\.(an|al)[0-9]+$//g') +Release: %{pkg_version}_%{osdb_version}~%{anolis_release}%{?dist} +Summary: The amdgpu Linux kernel driver + +License: GPLv2 and Redistributable, no modification permitted +URL: http://www.amd.com/ +Source0: kmod-%{pkg}-%{pkg_version}.tar.gz + +BuildRequires: gcc +BuildRequires: make +Requires: kernel >= %{kernel} + +%description +The AMD display driver kernel module in DKMS format for AMD graphics S/W + +%prep +%autosetup -n kmod-%{pkg}-%{pkg_version} -p1 + +%build +pushd src +%{__make} -f amd/dkms/oot/Makefile.oot KERNELVER=%(uname -r) +popd + +%install +mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko + +# Make .ko objects temporarily executable for automatic stripping +find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ + +# Generate depmod.conf +%{__install} -d %{buildroot}/%{_sysconfdir}/depmod.d/ +for kmod in $(find %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra -type f -name \*.ko -printf "%%P\n" | sort) +do + echo "override $(basename $kmod .ko) * weak-updates/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf + echo "override $(basename $kmod .ko) * extra/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf +done + +%clean +%{__rm} -rf %{buildroot} + +%post +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +%preun +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" >> /var/run/rpm-%{pkg}-modules.list + +%postun +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{pkg}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{pkg}-modules.list + +%files +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko +%defattr(644,root,root,755) +%license licenses +%config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf + +%changelog +* Thu Jul 18 2024 Bob Zhou - 6.8.7-1798298 +- diff --git a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh new file mode 100644 index 0000000000000..7cb58df401aa8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh @@ -0,0 +1,91 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +DKMS_TREE=$2 +MODULE=$3 +MODULE_VERSION=$4 +MODULE_BUILD_DIR=$5 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +source $KCL/files + +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h + +# add amd prefix to exported symbols +for file in $FILES; do + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h +done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile +done + +export KERNELVER +ln -s $DKMS_TREE $MODULE_BUILD_DIR + +# Enable gcc-toolset for kernels that are built with non-default compiler +# perform this check only when permissions allow +if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done +fi +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + +(cd $SRC && ./configure) + +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file + done +fi From 6925a8d5907806d47cb56e707799cba02198a552 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Aug 2024 18:43:59 +0800 Subject: [PATCH 1301/2070] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by 7368b413ed6e5a98516b8018e8e47850f32cd1d3 "drm/amd/pm: Add phase detect residency support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 5e3ce937bd4e5..23fdf43218190 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4346,8 +4346,13 @@ DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); #endif +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); +#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) From 4582616e219b6a650cdf00d85f87ae3e22b75350 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Aug 2024 18:56:27 +0800 Subject: [PATCH 1302/2070] drm/amdkcl: update kbps_to_peak_pbn param for non-upstream code It's caused by 4b6564cb120c9872ba6b2c108e634586acebc792 "drm/amd/display: Fix MST BW calculation Regression" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ef66d7be2e916..45d2c37851878 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2220,11 +2220,13 @@ enum dc_status dm_dp_mst_is_port_support_mode( */ int pbn_div, slot_num, max_slot_num; enum dc_link_encoding_format link_encoding; + uint16_t fec_overhead_multiplier_x1000 = + get_fec_overhead_multiplier(stream->link); uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( &stream->timing, dc_link_get_highest_encoding_format(stream->link)); - pbn = kbps_to_peak_pbn(stream_kbps); + pbn = kbps_to_peak_pbn(stream_kbps, fec_overhead_multiplier_x1000); pbn_div = dm_mst_get_pbn_divider(stream->link); slot_num = DIV_ROUND_UP(pbn, pbn_div); From 737ab0f27d69a53232c6eea67c4fcb58f82127cd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 18 Aug 2024 13:48:05 +0800 Subject: [PATCH 1303/2070] drm/amdkcl: fake drm/drm_fbdev_ttm.h header It's caused by v6.9-rc6-1436-gaae4682e5d66 drm/fbdev-generic: Convert to fbdev-ttm v6.1-rc2-542-g8ab59da26bc0 drm/fb-helper: Move generic fbdev emulation into separate source file Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 +++++++ include/kcl/backport/kcl_drm_fbdev_ttm.h | 16 ++++++++++++++++ include/kcl/header/drm/drm_fbdev_generic.h | 9 +++++++++ include/kcl/header/drm/drm_fbdev_ttm.h | 11 +++++++++++ 5 files changed, 44 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_fbdev_ttm.h create mode 100644 include/kcl/header/drm/drm_fbdev_generic.h create mode 100644 include/kcl/header/drm/drm_fbdev_ttm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3b095f9d533bc..271ab15e0112d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -119,4 +119,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index e95a330d6472b..e66cb05345fe6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -104,4 +104,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/edid: split out drm_eld.h from drm_edid.h dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) + + dnl # + dnl # v6.9-rc6-1436-gaae4682e5d66 + dnl # drm/fbdev-generic: Convert to fbdev-ttm + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_ttm.h]) + ]) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h new file mode 100644 index 0000000000000..03ddc7699ddb1 --- /dev/null +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -0,0 +1,16 @@ +#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H_ +#define __KCL_BACKPORT_KCL_DRM_DRV_H__ + +#include +#include + +#ifndef HAVE_DRM_DRM_FBDEV_TTM_H +static inline +void _kcl_drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp) +{ + return drm_fbdev_generic_setup(dev, preferred_bpp); +} +#define drm_fbdev_ttm_setup _kcl_drm_fbdev_ttm_setup +#endif + +#endif diff --git a/include/kcl/header/drm/drm_fbdev_generic.h b/include/kcl/header/drm/drm_fbdev_generic.h new file mode 100644 index 0000000000000..13b6f65c37f01 --- /dev/null +++ b/include/kcl/header/drm/drm_fbdev_generic.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_FBDEV_GENERIC_H_H_ +#define _KCL_HEADER_DRM_DRM_FBDEV_GENERIC_H_H_ + +#ifdef HAVE_DRM_DRM_FBDEV_GENERIC_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_fbdev_ttm.h b/include/kcl/header/drm/drm_fbdev_ttm.h new file mode 100644 index 0000000000000..dbf67afb91594 --- /dev/null +++ b/include/kcl/header/drm/drm_fbdev_ttm.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_FBDEV_TTM_H_H_ +#define _KCL_HEADER_DRM_DRM_FBDEV_TTM_H_H_ + +#ifdef HAVE_DRM_DRM_FBDEV_TTM_H +#include_next +#else +#include +#endif + +#endif From 64ca13bf64d7a88eec44b332ccdd23f1b6b818c1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 16:21:31 +0800 Subject: [PATCH 1304/2070] drm/amdkcl: fake drm_crtc_vblank_crtc It's caused by v6.9-rc2-247-gd12e36494dc2 drm/vblank: Introduce drm_crtc_vblank_crtc() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c | 43 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 | 16 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_vblank.h | 36 +++++++++++++++++ 6 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 create mode 100644 include/kcl/kcl_drm_vblank.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index b113c725c0e7e..8239c1478a928 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ + kcl_drm_vblank.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c new file mode 100644 index 0000000000000..f8d4ab7de31e3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c @@ -0,0 +1,43 @@ +/* + * drm_irq.c IRQ and vblank support + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/*copy from drivers/gpu/drm/drm_vblank.c */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +static struct drm_vblank_crtc * +drm_vblank_crtc(struct drm_device *dev, unsigned int pipe) +{ + return &dev->vblank[pipe]; +} + +struct drm_vblank_crtc * +drm_crtc_vblank_crtc(struct drm_crtc *crtc) +{ + return drm_vblank_crtc(crtc->dev, drm_crtc_index(crtc)); +} +EXPORT_SYMBOL(drm_crtc_vblank_crtc); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 271ab15e0112d..cb67c65490397 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -120,4 +120,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 new file mode 100644 index 0000000000000..d2f9038b46063 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc2-247-gd12e36494dc2 +dnl # drm/vblank: Introduce drm_crtc_vblank_crtc() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_VBLANK_CRTC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_crtc_vblank_crtc(NULL); + ],[ + AC_DEFINE(HAVE_CRTC_DRM_VBLANK_CRTC, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d6b81ea66fbce..c64efa25ddbb1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -211,6 +211,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_CATEGORY AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE + AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_vblank.h b/include/kcl/kcl_drm_vblank.h new file mode 100644 index 0000000000000..4a74049654c92 --- /dev/null +++ b/include/kcl/kcl_drm_vblank.h @@ -0,0 +1,36 @@ +/* + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_DRM_VBLANK_H +#define _KCL_KCL_DRM_VBLANK_H + +#include +#include +#include + +/*copy from include/drm/drm_vblank.h */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +struct drm_vblank_crtc *drm_crtc_vblank_crtc(struct drm_crtc *crtc); +#endif + +#endif /*_KCL_KCL_DRM_VBLANK_H */ From 1b389f5007b0d488fcec9dd7ca583b872cc619ae Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 21 Aug 2024 18:02:16 +0800 Subject: [PATCH 1305/2070] drm/amdkcl: modify the makefile for dml It's caused by v6.9-9706-g6cbd1d6d36c5 arch: add ARCH_HAS_KERNEL_FPU_SUPPORT`` Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 35 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dml/Makefile | 38 ++++++++++++++++++- .../gpu/drm/amd/display/dc/dml2_0/Makefile | 38 +++++++++++++++++++ 3 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index e46f8ce41d871..dab8eb705cafa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -26,7 +26,20 @@ #include "dc_trace.h" +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT #include +#else +#if defined(CONFIG_X86) +#include +#elif defined(CONFIG_PPC64) +#include +#include +#elif defined(CONFIG_ARM64) +#include +#elif defined(CONFIG_LOONGARCH) +#include +#endif +#endif /** * DOC: DC FPU manipulation overview @@ -79,8 +92,19 @@ void dc_fpu_begin(const char *function_name, const int line) preempt_disable(); depth = __this_cpu_inc_return(fpu_recursion_depth); if (depth == 1) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT BUG_ON(!kernel_fpu_available()); kernel_fpu_begin(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) + kernel_fpu_begin(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + enable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_begin(); +#endif +#endif } TRACE_DCN_FPU(true, function_name, line, depth); @@ -102,7 +126,18 @@ void dc_fpu_end(const char *function_name, const int line) depth = __this_cpu_dec_return(fpu_recursion_depth); if (depth == 0) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + kernel_fpu_end(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) kernel_fpu_end(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + disable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_end(); +#endif +#endif } else { WARN_ON_ONCE(depth < 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 875cfd1b5ddee..2690778645354 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -24,12 +24,48 @@ # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. - +# +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml_ccflags := $(dml_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml_ccflags := -mfpu=64 +dml_rcflags := -msoft-float +endif include $(src)/../dkms/Makefile.compiler +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml_ccflags += -mpreferred-stack-boundary=4 +else +dml_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile index 30cfc0848792e..66b4afa57742d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile @@ -24,8 +24,46 @@ # # Makefile for dml2. +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml2_ccflags := $(CC_FLAGS_FPU) dml2_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml2_ccflags := $(dml2_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml2_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml2_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml2_ccflags := -mfpu=64 +dml2_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml2_ccflags += -mpreferred-stack-boundary=4 +else +dml2_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) From f8587b50d68b4be303303917e42f6817bf6ca0fd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 11:10:38 +0800 Subject: [PATCH 1306/2070] drm/amdkcl: include correct header when macro HAVE_ASM_FPU_API_H isn't defined Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index dab8eb705cafa..35066ae9acbce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -30,7 +30,11 @@ #include #else #if defined(CONFIG_X86) +#if defined(HAVE_ASM_FPU_API_H) #include +#else +#include +#endif #elif defined(CONFIG_PPC64) #include #include From d63f42c4c60eab0b7e75704cac001264c5fcf0b9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 17:02:07 +0800 Subject: [PATCH 1307/2070] drm/amdkcl: check PCI_IRQ_INTX whether exist It's caused by v6.7-rc1-1-g58ff9c5acb4a PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX v6.9-rc1-32-g0e1fdd222f0 PCI: Remove PCI_IRQ_LEGACY Signed-off-by: Asher Song --- include/kcl/kcl_pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index a015093db3889..c40f95b9507c1 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -210,4 +210,10 @@ static inline struct pci_dev *pci_get_base_class(unsigned int class, { return NULL; } #endif /*CONFIG_PCI*/ #endif /*HAVE_PCI_GET_BASE_CLASS*/ + +/* Copied from include/linux/pci.h */ +#ifndef PCI_IRQ_INTX +#define PCI_IRQ_INTX PCI_IRQ_LEGACY +#endif + #endif /* AMDKCL_PCI_H */ From 97b3c5e5bbae9e7e2c49bf50b4a7878a30fdeba4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Dec 2023 13:54:33 +0800 Subject: [PATCH 1308/2070] drm/amdkcl: test whether struct drm_color_ctm_3x4 is available It's caused by 2d4457c2d03ed0e2fcf4206a10c0bdfcab4fd03f "drm/amd/display: Add 3x4 CTM support for plane CTM" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_color_ctm_3x4.m4 | 20 +++++++++++++++++++ include/kcl/kcl_drm_modes.h | 11 ++++++++++ 3 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c64efa25ddbb1..cbf15346d47cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_DRM_CLIENT_REGISTER + AC_AMDGPU_DRM_COLOR_CTM_3X4 AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 new file mode 100644 index 0000000000000..cef143831f813 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.5-2548-g2d4457c2d03e +dnl # drm/amd/display: Add 3x4 CTM support for plane CTM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_CTM_3X4], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_color_ctm_3x4 *ctm = NULL; + ctm->matrix[0] = 0; + ],[ + AC_DEFINE(HAVE_DRM_COLOR_CTM_3X4, 1, + [struct drm_color_ctm_3x4 is available]) + ]) + ]) +]) + + + diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index d3a387bad9988..37be6de3ff49f 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -29,6 +29,17 @@ #include +#ifndef HAVE_DRM_COLOR_CTM_3X4 +/* FIXME wrong namespace! */ +struct drm_color_ctm_3x4 { + /* + * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude + * (not two's complement!) format. + */ + __u64 matrix[12]; +}; +#endif + #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); #endif From eb4ddd5a344f5587ac261d4a7218c2bb0ea4b74c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Aug 2024 09:35:42 +0800 Subject: [PATCH 1309/2070] drm/amdkcl: check drm_dp_add_payload_part2 whether requires three argunments It's caused by v6.9-rc6-1554-g8a0a7b98d4b6 drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 commit v5.19-rc6-1771-g4d07b0bc4034 drm/display/dp_mst: Move all payload info into the atomic state Signed-off-by: Asher Song --- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 13 ++++++++++++ 3 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 8cf95a2c43af3..1755debc25f59 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -67,3 +67,23 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ ]) ]) +dnl # +dnl # commit v6.9-rc6-1554-g8a0a7b98d4b6 +dnl # drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int a = 0; + a = drm_dp_add_payload_part2(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS, 1, + [drm_dp_add_payload_part2 has three arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cbf15346d47cf..9afdefda490fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC + AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 9791910ed58b0..a84cd2ac22cc2 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -104,4 +104,17 @@ _kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_mst_topology_mgr_resume _kcl_drm_dp_mst_topology_mgr_resume #endif +#ifdef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS +static inline int +_kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_atomic_payload *payload) +{ + struct drm_dp_mst_topology_state *mst_state; + + mst_state = to_drm_dp_mst_topology_state(mgr->base.state); + return drm_dp_add_payload_part2(mgr, mst_state->base.state, payload); +} +#define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 +#endif + #endif From 4b79d6bdb2151cecf7daa7398794ab0da26ce99f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Aug 2024 14:15:33 +0800 Subject: [PATCH 1310/2070] drm/amdkcl: test follow_pfn() is available It's caused by cb10c28ac82c9b7a5e9b3b1dc7157036c20c36dd "mm: remove follow_pfn" Signed-off-by: Bob Zhou Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/kcl_memory.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 6 ++++++ 6 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/kcl_memory.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 8bc3adedebc57..2d01094326e2c 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o kcl_drm_file.o + kcl_drm_gem.o kcl_drm_file.o kcl_memory.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/kcl_memory.c b/drivers/gpu/drm/amd/backport/kcl_memory.c new file mode 100644 index 0000000000000..153710b6883de --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_memory.c @@ -0,0 +1,20 @@ +#include + +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn) +{ + int ret = -EINVAL; + spinlock_t *ptl; + pte_t *ptep; + + ret = follow_pte(vma, address, &ptep, &ptl); + if (ret) + return ret; + *pfn = pte_pfn(ptep_get(ptep)); + pte_unmap_unlock(ptep, ptl); + return 0; +} + +EXPORT_SYMBOL(_kcl_follow_pfn); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6de7b509d62e0..0b15cd5a1c091 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -618,6 +618,12 @@ /* drm_print_bits() has 4 args */ #define HAVE_DRM_PRINT_BITS_4ARGS 1 +/* drm_show_fdinfo() is available */ +#define HAVE_DRM_SHOW_FDINFO 1 + +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 new file mode 100644 index 0000000000000..ea2c47c00ab90 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.9-rc4-152-gcb10c28ac82c +dnl # mm: remove follow_pfn +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfn(NULL, 0, NULL); + ],[follow_pfn], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFN, 1, + [follow_pfn() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9afdefda490fb..1c260c85d1ee6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -191,6 +191,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 848e47a2c3d39..a009a7159cc4a 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -155,4 +155,10 @@ static inline bool vma_is_initial_stack(const struct vm_area_struct *vma) } #endif +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn); +#define follow_pfn _kcl_follow_pfn +#endif + #endif /* AMDKCL_MM_H */ From 02a547528955a4bff8e3285e311b78e3595fc7e1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 30 Aug 2024 08:58:00 +0800 Subject: [PATCH 1311/2070] drm/amdgpu: fix a call trace when unload amdgpu driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In some APUs, the bo type of GART page table is ttm_bo_type_sg. Those type BOs is released by bo->delayed_delete which is added in ttm_device->wq, not released immediately. To make sure all the ttm_resource is released before ttm_resource_manager is finilized, drain the workqueue in ttm_device. v2: move drain_workqueue to amdgpu_ttm.c Fixes:d99fbd9aab62 ("drm/ttm: Always take the bo delayed cleanup path for imported bos") Suggested-by: Christian König Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 69880a3efa649..36b5ca860842a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2703,6 +2703,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + drain_workqueue(adev->mman.bdev.wq); amdgpu_direct_gma_fini(adev); if (!adev->gmc.is_app_apu) amdgpu_vram_mgr_fini(adev); From 1df4ea3c0fc56ceaf1b8272dc8f344f558e6570a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Sep 2024 14:25:24 +0800 Subject: [PATCH 1312/2070] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 5efa478729c8f2c8eb3c05034a37ad72654307af "drm/amdgpu: re-work VM syncing" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 0d8cd624e5571..1890739954f18 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1332,7 +1332,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ - r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_EXPLICIT, vm); if (r) goto error_free; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index b435093edcdde..b8c4d1200eabd 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -844,13 +844,13 @@ static bool ttm_lru_walk_trylock(struct ttm_bo_lru_cursor *curs, curs->needs_unlock = false; - if (dma_resv_trylock(bo->base.resv)) { + if (dma_resv_trylock(amdkcl_ttm_resvp(bo))) { curs->needs_unlock = true; return true; } - if (bo->base.resv == ctx->resv && ctx->allow_res_evict) { - dma_resv_assert_held(bo->base.resv); + if (amdkcl_ttm_resvp(bo) == ctx->resv && ctx->allow_res_evict) { + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); return true; } @@ -864,9 +864,9 @@ static int ttm_lru_walk_ticketlock(struct ttm_bo_lru_cursor *curs, int ret; if (arg->ctx->interruptible) - ret = dma_resv_lock_interruptible(bo->base.resv, arg->ticket); + ret = dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), arg->ticket); else - ret = dma_resv_lock(bo->base.resv, arg->ticket); + ret = dma_resv_lock(amdkcl_ttm_resvp(bo), arg->ticket); if (!ret) { curs->needs_unlock = true; From df7541c64e56429610610b1595ee660b0ba7cecd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Sep 2024 14:27:41 +0800 Subject: [PATCH 1313/2070] drm/amdkcl: test import_guid() is available It's caused by ea612cbee8cea66d71922f446cdd3223636e1df2 "drm/amd/display: switch to guid_gen() to generate valid GUIDs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/import_guid.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_uuid.h | 19 +++++++++++++++++++ 5 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/import_guid.m4 create mode 100644 include/kcl/kcl_uuid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cb67c65490397..1f45d3ecf8a3b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -121,4 +121,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0b15cd5a1c091..a08eb1f9aea69 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -687,6 +687,9 @@ /* idr_remove return void pointer */ #define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 +/* import_guid() is available */ +#define HAVE_IMPORT_GUID 1 + /* in_compat_syscall is defined */ #define HAVE_IN_COMPAT_SYSCALL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 new file mode 100644 index 0000000000000..c96b4703e6cf9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_IMPORT_GUID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + import_guid(NULL, NULL); + ],[ + AC_DEFINE(HAVE_IMPORT_GUID, 1, + [import_guid() is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1c260c85d1ee6..f547680f0a8a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -192,6 +192,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN + AC_AMDGPU_IMPORT_GUID AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/include/kcl/kcl_uuid.h b/include/kcl/kcl_uuid.h new file mode 100644 index 0000000000000..be6580926dabc --- /dev/null +++ b/include/kcl/kcl_uuid.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_UUID_H +#define KCL_KCL_UUID_H + +#include + +#ifndef HAVE_IMPORT_GUID +static inline void import_guid(guid_t *dst, const __u8 *src) +{ + memcpy(dst, src, sizeof(guid_t)); +} + +static inline void export_guid(__u8 *dst, const guid_t *src) +{ + memcpy(dst, src, sizeof(guid_t)); +} +#endif + +#endif \ No newline at end of file From cee5170364c60108907c200a150fbd37ff1b5494 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 5 Sep 2024 17:17:04 +0800 Subject: [PATCH 1314/2070] drm/amdkcl: test struct drm_dp_mst_branch has guid_t It's caused by ea612cbee8cea66d71922f446cdd3223636e1df2 "drm/amd/display: switch to guid_gen() to generate valid GUIDs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_dp_mst_branch.m4 | 21 +++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 15a7d6767daf1..f346bb131be2b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2856,7 +2856,11 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) } } +#ifdef HAVE_DRM_DP_MST_BRANCH_GUID_T guid_copy(&mgr->mst_primary->guid, &guid); +#else + memcpy(mgr->mst_primary->guid, &guid, 16); +#endif out_fail: mutex_unlock(&mgr->lock); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a08eb1f9aea69..acfe1a47ff59b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -358,6 +358,9 @@ /* drm_dp_mst_atomic_enable_dsc() wants 5args */ /* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ +/* the guid of struct drm_dp_mst_branch is guid_t */ +#define HAVE_DRM_DP_MST_BRANCH_GUID_T 1 + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f547680f0a8a8..7daf02055c2fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -193,6 +193,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_IMPORT_GUID + AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 new file mode 100644 index 0000000000000..753914f3cc392 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_dp_mst_branch mst_primary; + const guid_t guid; + guid_copy(&mst_primary.guid, &guid); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_BRANCH_GUID_T, 1, + [the guid of struct drm_dp_mst_branch is guid_t]) + ]) + ]) +]) + + + From b3915435bab71796b74c69f13ad8e7591c723554 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 6 Sep 2024 16:17:17 +0800 Subject: [PATCH 1315/2070] drm/amdkcl: test drm_vblank_crtc_config is available It's caused by 786628e0bf493cabcaa1c7a5ef5c27e2fa530c18 "drm/amd/display: use new vblank enable policy for DCN35+" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_vblank_crtc_config .m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f346bb131be2b..5ec16bc08cf04 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9413,6 +9413,7 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, * backend index - some even map to more than one. * So we have to go through the CRTC to find the right IRQ. */ +#ifdef HAVE_DRM_VBLANK_CRTC_CONFIG int irq_type = amdgpu_display_crtc_idx_to_irq_type( adev, acrtc->crtc_id); @@ -9501,6 +9502,12 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, drm_crtc_vblank_off(&acrtc->base); } +#else + if (acrtc_state) + drm_crtc_vblank_on(&acrtc->base); + else + drm_crtc_vblank_off(&acrtc->base); +#endif } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index acfe1a47ff59b..0ab67024ed818 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -633,6 +633,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 +/* drm_vblank_crtc_config is available */ +/* #undef HAVE_DRM_VBLANK_CRTC_CONFIG */ + /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 new file mode 100644 index 0000000000000..90ef0ba2c3cc5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc_config config; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_CONFIG, 1, + [drm_vblank_crtc_config is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7daf02055c2fb..a5808af057bc2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,6 +90,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_MODE_CONFIG + AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS From 64a65d23626e2015c6e62093c914944732027a6b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 18:37:18 +0800 Subject: [PATCH 1316/2070] drm/amdkcl: wrap code out of HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT is for validate_dsc_caps_on_connector. It should not be guarding retrieve_downstream_port_device. Signed-off-by: Kent Russell --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 45d2c37851878..397627d6d0169 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -339,6 +339,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto return true; } #endif +#endif static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) { @@ -358,7 +359,6 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } -#endif static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector) { @@ -514,11 +514,10 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) memset(&aconnector->dc_sink->dsc_caps, 0, sizeof(aconnector->dc_sink->dsc_caps)); #endif - +#endif if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); -#endif } } From 6059fb62de1f6b56a21283b97f32634b57101d73 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 19 Sep 2024 15:38:15 +0800 Subject: [PATCH 1317/2070] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 71372e402994d29b6d456b714e6e8608c8112e91 "drm/amdgpu: add amdgpu_jpeg_sched_mask debugfs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index 63ee6ba6a9316..56128f6930a4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -402,9 +402,15 @@ static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, amdgpu_debugfs_jpeg_sched_mask_get, amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, + amdgpu_debugfs_jpeg_sched_mask_get, + amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#endif #endif From dac681eae7796979938a597aa6a9ebb44aad1287 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 23 Sep 2024 13:22:28 +0800 Subject: [PATCH 1318/2070] drm/amdkcl: test drm_gem_prime_handle_to_dmabuf() is available It's caused by eeab2428df5a886d40c08f9847ea4d2c2fbce7e0 "drm/amdgpu: fix a race in kfd_mem_export_dmabuf()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 097ca3c5a6663..dcf09f30330be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -821,12 +822,25 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) if (!mem->dmabuf) { struct amdgpu_device *bo_adev; struct dma_buf *dmabuf; +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF + int r, fd; + bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file, + mem->gem_handle, + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DRM_RDWR : 0, &fd); + if (r) + return r; + dmabuf = dma_buf_get(fd); + close_fd(fd); +#else bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file, mem->gem_handle, mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0); +#endif if (IS_ERR(dmabuf)) return PTR_ERR(dmabuf); mem->dmabuf = dmabuf; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0ab67024ed818..d701875535c14 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -558,6 +558,9 @@ /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 +/* drm_gem_prime_handle_to_dmabuf() is available */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF 1 + /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 new file mode 100644 index 0000000000000..cfdf6da657222 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3140-ge9b641807e5e +dnl # drm: new helper: drm_gem_prime_handle_to_dmabuf() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_dmabuf(NULL, NULL, 0, 0); + ],[drm_gem_prime_handle_to_dmabuf],[drivers/gpu/drm/drm_prime.c],[ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF, 1, + [drm_gem_prime_handle_to_dmabuf() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a5808af057bc2..49774d5d32405 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -191,6 +191,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_IMPORT_GUID From 6d0689107c3314ec57f929332b3dfb77f3767577 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 10:46:49 -0700 Subject: [PATCH 1319/2070] drm/amdkfd: [SPM] Fix a crash issue when running SPM on latest kernel driver Root cause: Parameter type for amdgpu_amdkfd_free_gtt_mem() has changed. Fix: Change SPM code to match this change. Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 6480e9c49f608..a9354d43bba3b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -62,7 +62,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) return -EFAULT; user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); - // From RLC spec, ring_rptr = 0 points to spm->cpu_addr+0x20 + /* From RLC spec, ring_rptr = 0 points to spm->cpu_addr + 0x20 */ ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); if (user_address == NULL) @@ -221,7 +221,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: kfree(pdd->spm_cntr); @@ -250,7 +250,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device wake_up_all(&pdd->spm_cntr->spm_buf_wq); amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); - amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); kfree(pdd->spm_cntr); From 7ef52faffe25c337a816a7e25238924755706389 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 11:13:12 -0700 Subject: [PATCH 1320/2070] drm/amdgpu: [SPM] Remove 'SPM Start' logic from gfx_v9_0_spm_start() We should start SPM only after all SPM configurations are done, otherwise we might see garbage data or other undefined behaviors. Because user mode module (profiler) is responsible for SPM configurations, we will let user mode module to start SPM. Signed-off-by: Bing Ma Acked-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 56a42deae1ae5..c8ae6ca3de4a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4816,11 +4816,6 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); - data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, - STRM_PERFMON_STATE_START_COUNTING); - gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); - gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } From 48712feced362e01a62b84b3cc8f0235cef45862 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Tue, 24 Sep 2024 16:58:03 -0700 Subject: [PATCH 1321/2070] drm/amd: [SPM] Reset SPM ringbuffer 'rptr' When SPM is reset When SPM is reset, RLC automatically resets wptr to 0. We need to manually reset rptr to match this. Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index c8ae6ca3de4a6..c9664f3573aab 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4816,6 +4816,12 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } @@ -4834,6 +4840,12 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) CP_PERFMON_STATE_DISABLE_AND_RESET); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); } static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index a9354d43bba3b..0827e2d4163c0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -371,6 +371,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); } else { /* If SPM was already started, there may already @@ -382,6 +386,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev amdgpu_amdkfd_rlc_spm_cntl(adev, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); } From a7f92dd826bcee97a4fc0f658aebb35da9d2b245 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 15:29:40 -0700 Subject: [PATCH 1322/2070] drm/amdkfd: [SPM] Remove 'rptr = wptr' when 'is_user_buf_filled == true'. We cannot set rptr = wptr here, because wptr is always set at segment boundary and profiler uses this knowledge to parse SPM counters. But rptr is not always set at segment boundary, and if we force 'rptr = wptr', we might leave an incomplete segment to user mode profiler and profiler won't be able to parse the counter properly. Signed-off-by: Bing Ma Acked-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 0827e2d4163c0..9b829adfc8ed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -103,9 +103,12 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) ring_wptr = READ_ONCE(spm->cpu_addr[0]); - /* keep SPM ring buffer running */ + /* SPM might stall if we cannot copy data out of SPM ringbuffer. + * spm->has_data_loss is only a hint here since stall is only a + * possibility and data loss might not happen. But it is a useful + * hint for user mode profiler to take extra actions. + */ if (!spm->has_user_buf || spm->is_user_buf_filled) { - spm->ring_rptr = ring_wptr; spm->has_data_loss = true; /* set flag due to there is no flag setup * when read ring buffer timeout. From a4afd10826f24ce1acc2c2b3f0364c507e2d1c14 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 15:33:02 -0700 Subject: [PATCH 1323/2070] drm/amdkfd: [SPM] Merge spm_copy_data_to_usr() and spm_set_dest_info() into one function spm_update_dest_info() The gap between the two functions will trigger unnecessary data loss condition in kfd_spm_read_ring_buffer(). Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 45 +++++++++++++--------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 9b829adfc8ed9..45a81dd764eab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -264,26 +264,24 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device return 0; } -static void spm_copy_data_to_usr(struct kfd_ioctl_spm_args *user_spm_data, - struct kfd_process_device *pdd) -{ - mutex_lock(&pdd->spm_cntr->spm_worker_mutex); - user_spm_data->bytes_copied = pdd->spm_cntr->size_copied; - user_spm_data->has_data_loss = pdd->spm_cntr->has_data_loss; - pdd->spm_cntr->has_user_buf = false; - mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); -} - -static void spm_set_dest_info(struct kfd_process_device *pdd, +static void spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { + struct kfd_spm_cntr *spm = pdd->spm_cntr; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); - pdd->spm_cntr->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; - pdd->spm_cntr->ubuf.ubufsize = user_spm_data->buf_size; - pdd->spm_cntr->has_data_loss = false; - pdd->spm_cntr->size_copied = 0; - pdd->spm_cntr->is_user_buf_filled = false; - pdd->spm_cntr->has_user_buf = true; + if (spm->has_user_buf) { + user_spm_data->bytes_copied = spm->size_copied; + user_spm_data->has_data_loss = spm->has_data_loss; + spm->has_user_buf = false; + } + if (user_spm_data->dest_buf) { + spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + spm->ubuf.ubufsize = user_spm_data->buf_size; + spm->has_data_loss = false; + spm->size_copied = 0; + spm->is_user_buf_filled = false; + spm->has_user_buf = true; + } mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } @@ -360,16 +358,15 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev flush_work(&pdd->spm_work); } - if (spm->has_user_buf) { - /* get info about filled space in previous output buffer */ - spm_copy_data_to_usr(user_spm_data, pdd); + if (spm->has_user_buf || user_spm_data->dest_buf) { + /* Get info about filled space in previous output buffer. + * Setup new dest buf if provided. + */ + spm_update_dest_info(pdd, user_spm_data); } if (user_spm_data->dest_buf) { - /* setup new dest buf, start streaming if necessary */ - spm_set_dest_info(pdd, user_spm_data); - - /* Start SPM */ + /* Start SPM if necessary*/ if (spm->is_spm_started == false) { amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From ac86a27fa356472d0685452cd26f6f19525657ea Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 23 Sep 2024 10:15:39 -0400 Subject: [PATCH 1324/2070] drm/amdkfd: release spm when process destroy If process is killed, process destroy will be called. Signed-off-by: James Zhu Tested-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index ccc76920016ac..0a3ea6d9e0c52 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1699,6 +1699,7 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, bool kfd_is_locked(struct kfd_dev *kfd); void kfd_spm_init_process_device(struct kfd_process_device *pdd); +int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); int kfd_rlc_spm(struct kfd_process *p, void __user *data); /* PeerDirect support */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index c29dfbb69e94e..dbb44e52f395b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1112,6 +1112,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->dev->id, p->lead_thread->pid); kfd_pc_sample_release(pdd); + kfd_release_spm(pdd, pdd->dev->adev); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 45a81dd764eab..9a27949e00f59 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -235,7 +235,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; From 8a2b49780bc703ab3eb83eaedabb3b9758bab67f Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 23 Sep 2024 11:05:44 -0400 Subject: [PATCH 1325/2070] drm/amdkfd: workaround for spm overflow reserve space to avoid page fault and data loss. Signed-off-by: James Zhu Reviewed-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 40 ++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 0a3ea6d9e0c52..4b9dd30008f1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -889,6 +889,8 @@ struct kfd_process_device { struct mutex spm_mutex; struct work_struct spm_work; spinlock_t spm_irq_lock; + /* reserve space to fix spm overflow */ + u32 spm_overflow_reserved; /* Eviction activity tracking */ uint64_t last_evict_timestamp; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 9a27949e00f59..d6a03240f36af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -50,6 +50,21 @@ struct kfd_spm_cntr { bool is_spm_started; }; +/* used to detect SPM overflow */ +#define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD + +static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) +{ + uint64_t *overflow_ptr, *overflow_end_ptr; + + overflow_ptr = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + + pdd->spm_cntr->ring_size + 0x20); + overflow_end_ptr = overflow_ptr + (size >> 3); + /* SPM data filling is 0x20 alignment */ + for ( ; overflow_ptr < overflow_end_ptr; overflow_ptr += 4) + *overflow_ptr = SPM_OVERFLOW_MAGIC; +} + static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) { struct kfd_spm_cntr *spm = pdd->spm_cntr; @@ -97,6 +112,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) { struct kfd_spm_cntr *spm = pdd->spm_cntr; + u32 overflow_size = 0; u32 size_to_copy; int ret = 0; u32 ring_wptr; @@ -125,6 +141,19 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); } else { + uint64_t *ring_start, *ring_end; + + ring_start = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + 0x20); + ring_end = ring_start + (pdd->spm_cntr->ring_size >> 3); + for ( ; overflow_size < pdd->spm_overflow_reserved; overflow_size += 0x20) { + uint64_t *overflow_ptr = ring_end + (overflow_size >> 3); + + if (*overflow_ptr == SPM_OVERFLOW_MAGIC) + break; + } + /* move overflow counters into ring buffer to avoid data loss */ + memcpy(ring_start, ring_end, overflow_size); + size_to_copy = spm->ring_size - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -143,6 +172,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } exit: + kfd_spm_preset(pdd, overflow_size); amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); return ret; } @@ -168,6 +198,10 @@ static void kfd_spm_work(struct work_struct *work) void kfd_spm_init_process_device(struct kfd_process_device *pdd) { + /* pre-gfx11 spm has a hardware bug to cause overflow */ + if (pdd->dev->adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 1)) + pdd->spm_overflow_reserved = 0x400; + mutex_init(&pdd->spm_mutex); pdd->spm_cntr = NULL; } @@ -202,7 +236,9 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), + /* reserve space to fix spm overflow */ + pdd->spm_cntr->ring_size -= pdd->spm_overflow_reserved; + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -221,6 +257,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device spin_lock_init(&pdd->spm_irq_lock); + kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + goto out; acquire_spm_failure: From ebdda4f874a063a9444728d7a5aa91f14df7ddf4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 29 Sep 2024 11:50:28 +0800 Subject: [PATCH 1326/2070] drm/amdkcl: wrap code under HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE It's caused by c7de57033d9b55b4bdc89dfeae6f57ba45401032 "drm/amdgpu: Add sysfs nodes to get xcp details" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 73250ab45f202..93bb07302b466 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -744,7 +744,9 @@ static const char *nps_desc[] = { [AMDGPU_NPS8_PARTITION_MODE] = "NPS8", }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); +#endif #define to_xcp_attr(x) \ container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr) @@ -771,7 +773,11 @@ static const struct sysfs_ops xcp_cfg_res_sysfs_ops = { static const struct kobj_type xcp_cfg_res_sysfs_ktype = { .sysfs_ops = &xcp_cfg_res_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = xcp_cfg_res_sysfs_groups, +#else + .default_attrs = xcp_cfg_res_sysfs_attrs, +#endif }; const char *xcp_res_names[] = { From ea305446f2ec4ef69b70f174b3a0378a1ee36268 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 29 Sep 2024 11:52:03 +0800 Subject: [PATCH 1327/2070] drm/amdkcl: test if macro __ATTR_RW_MODE is available It's caused by c7de57033d9b55b4bdc89dfeae6f57ba45401032 "drm/amdgpu: Add sysfs nodes to get xcp details" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 93bb07302b466..663aa67803f7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -878,7 +878,11 @@ static ssize_t xcp_config_store(struct kobject *kobj, } static struct kobj_attribute xcp_cfg_sysfs_mode = +#ifdef __ATTR_RW_MODE __ATTR_RW_MODE(xcp_config, 0644); +#else + __ATTR(xcp_config, 0644, xcp_config_show, xcp_config_store); +#endif static void xcp_cfg_sysfs_release(struct kobject *kobj) { From 33bdcb4fd74feb9a5475978f127dd9dcaf0a7c38 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Oct 2024 10:54:32 +0800 Subject: [PATCH 1328/2070] drm/amdkcl: rename TAINT_CPU_OUT_OF_SPEC to TAINT_UNSAFE_SMP It's caused by fe6db14d2f114fce6a607d1b09f9d0a5d2b1a609 "drm/amd: Taint the kernel when enabling overdrive" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_kernel.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index d055fad138c19..47e8853f7e144 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -29,4 +29,9 @@ #define __GFP_KSWAPD_RECLAIM ((__force gfp_t)___GFP_KSWAPD_RECLAIM) /* kswapd can wake */ #endif /* ___GFP_KSWAPD_RECLAIM */ +/* v5.13-335-gf39650de687e ("kernel.h: split out panic and oops helpers") */ +#ifndef TAINT_CPU_OUT_OF_SPEC +#define TAINT_CPU_OUT_OF_SPEC TAINT_UNSAFE_SMP +#endif + #endif /* AMDKCL_KERNEL_H */ From f3e4bdc174a016ca449daad917c0deab2f15fbcb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Oct 2024 11:08:17 +0800 Subject: [PATCH 1329/2070] drm/amdkcl: test whether pm_runtime_resume_and_get() is available It's caused by 718922a1d2231f11f73c7f0f12c351cbdaf1e808 "drm/amd/pm: use pm_runtime_resume_and_get" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 10 +++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_runtime_resume_and_get.m4 | 16 +++++++++++ include/kcl/kcl_pm_runtime.h | 27 +++++++++++++++++++ 5 files changed, 53 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 create mode 100644 include/kcl/kcl_pm_runtime.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1f45d3ecf8a3b..bafa11f20512c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -122,4 +122,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d701875535c14..90ded8cd71552 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -906,8 +906,14 @@ /* vm_insert_mixed() wants pfn_t arg */ /* #undef HAVE_PFN_T_VM_INSERT_MIXED */ -/* pm_genpd_remove_device() wants 2 arguments */ -/* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ +/* PIDTYPE is availablea */ +#define HAVE_PIDTYPE_TGID 1 + +/* pm_runtime_resume_and_get() is available */ +#define HAVE_PM_RUNTIME_RESUME_AND_GET 1 + +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 /* pm_suspend_via_firmware() is available */ #define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 49774d5d32405..1cc47c8203d55 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,6 +218,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC + AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 new file mode 100644 index 0000000000000..738b08a40004b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.10-rc3-244-gdd8088d5a896 +dnl # PM: runtime: Add pm_runtime_resume_and_get to deal with usage counter +dnl # +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_runtime_resume_and_get(NULL); + ],[ + AC_DEFINE(HAVE_PM_RUNTIME_RESUME_AND_GET, 1, + [pm_runtime_resume_and_get() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pm_runtime.h b/include/kcl/kcl_pm_runtime.h new file mode 100644 index 0000000000000..77513261a62b1 --- /dev/null +++ b/include/kcl/kcl_pm_runtime.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * pm.h - Power management interface + * + * Copyright (C) 2000 Andrew Henroid + */ +#ifndef KCL_KCL_PM_RUNTIME_H +#define KCL_KCL_PM_RUNTIME_H + +#include + +#ifndef HAVE_PM_RUNTIME_RESUME_AND_GET +static inline int pm_runtime_resume_and_get(struct device *dev) +{ + int ret; + + ret = __pm_runtime_resume(dev, RPM_GET_PUT); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + return 0; +} +#endif + +#endif From 2b145ffd5c6948be1aa001593e4972900de00dbe Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Oct 2024 16:45:18 +0800 Subject: [PATCH 1330/2070] drm/amdkcl: test whether pm_runtime_get_if_active() is available It's caused by e13590646ddac10c9a433c1d9d2d3ad8cbdad738 "drm/amd/pm: use pm_runtime_get_if_active for debugfs getters" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_runtime_get_if_active.m4 | 25 +++++++++++++++++++ include/kcl/kcl_pm_runtime.h | 18 ++++++++++++- 4 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 90ded8cd71552..b8dc3a858e01d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -909,6 +909,12 @@ /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 +/* pm_runtime_get_if_active() has one parameters */ +#define HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS 1 + +/* pm_runtime_get_if_active() has two parameters */ +/* #undef HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ + /* pm_runtime_resume_and_get() is available */ #define HAVE_PM_RUNTIME_RESUME_AND_GET 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1cc47c8203d55..c9875af26988f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -219,6 +219,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET + AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 new file mode 100644 index 0000000000000..9615da53282ad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 @@ -0,0 +1,25 @@ +dnl # +dnl # commit v5.6-rc4-1-gc111566bea7c +dnl # PM: runtime: Add pm_runtime_get_if_active() +dnl # +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pm_runtime_get_if_active(NULL); + ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS, 1, + [pm_runtime_get_if_active() has one parameters]) + ],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pm_runtime_get_if_active(NULL, 0); + ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS, 1, + [pm_runtime_get_if_active() has two parameters]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pm_runtime.h b/include/kcl/kcl_pm_runtime.h index 77513261a62b1..54df71e7b5b24 100644 --- a/include/kcl/kcl_pm_runtime.h +++ b/include/kcl/kcl_pm_runtime.h @@ -24,4 +24,20 @@ static inline int pm_runtime_resume_and_get(struct device *dev) } #endif -#endif +#ifdef CONFIG_PM +#if defined(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS) +static inline int _kcl_pm_runtime_get_if_active(struct device *dev) +{ + return pm_runtime_get_if_active(dev, true); +} +#define pm_runtime_get_if_active _kcl_pm_runtime_get_if_active +#elif !defined(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS) +static inline int _kcl_pm_runtime_get_if_active(struct device *dev) +{ + return pm_runtime_get_if_in_use(dev); +} +#define pm_runtime_get_if_active _kcl_pm_runtime_get_if_active +#endif /* HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ +#endif /* CONFIG_PM */ + +#endif /* KCL_KCL_PM_RUNTIME_H */ \ No newline at end of file From b5c79339d5f4d0b311f9084f9f5cd363504e549b Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 15 Oct 2024 11:10:37 +0800 Subject: [PATCH 1331/2070] drm/amdkcl: Accounting pdd vram_usage for svm on non-upstream code It's caused by 9bc846f3ad947d195921926f225fe088f0acd9ec "drm/amdkfd: Accounting pdd vram_usage for svm" The pdd->vram_usage change from uint64_t type to atomic64_t type Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e2dd54b928c76..0a7e0cc02d885 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2555,7 +2555,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, bo_bucket->restored_offset = offset; if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) /* Update the VRAM usage count */ - WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + atomic64_add(bo_bucket->size, &pdd->vram_usage); return 0; } From 2275eb1ee45ed4992e5707f42f0a57ff4664b4b0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 24 Oct 2024 10:23:11 +0800 Subject: [PATCH 1332/2070] drm/amdkcl: test whether drm_dp_mst_edid_read is available It's caused by 7f082eb3011c4f1146436bbf9c550b7adbcf42ec "drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 135 +++++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8 ++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 22 +++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 45 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 | 16 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 7 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5ec16bc08cf04..fd35e83e5b7dd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3919,7 +3919,11 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); amdgpu_dm_update_freesync_caps(connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid); +#else + aconnector->edid); +#endif } else { amdgpu_dm_update_freesync_caps(connector, NULL); if (!aconnector->dc_sink) { @@ -3972,12 +3976,17 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); if (sink->dc_edid.length == 0) { +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif hdmi_cec_unset_edid(aconnector); if (aconnector->dc_link->aux_mode) { drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); @@ -3987,6 +3996,15 @@ void amdgpu_dm_update_connector_after_detect( if (aconnector->dc_link->aux_mode) drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, connector->display_info.source_physical_address); +#else + aconnector->edid = + (struct edid *)sink->dc_edid.raw_edid; + + hdmi_cec_set_edid(aconnector); + if (aconnector->dc_link->aux_mode) + drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, + aconnector->edid); +#endif } if (!aconnector->timing_requested) { @@ -3997,7 +4015,11 @@ void amdgpu_dm_update_connector_after_detect( "failed to create aconnector->requested_timing\n"); } +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); +#else + amdgpu_dm_update_freesync_caps(connector, aconnector->edid); +#endif update_connector_ext_caps(aconnector); } else { hdmi_cec_unset_edid(aconnector); @@ -4006,8 +4028,12 @@ void amdgpu_dm_update_connector_after_detect( aconnector->num_modes = 0; dc_sink_release(aconnector->dc_sink); aconnector->dc_sink = NULL; +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(aconnector->drm_edid); aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif kfree(aconnector->timing_requested); aconnector->timing_requested = NULL; /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ @@ -7944,6 +7970,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dc_link *dc_link = aconnector->dc_link; struct dc_sink *dc_em_sink = aconnector->dc_em_sink; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; struct i2c_adapter *ddc; struct drm_device *dev = connector->dev; @@ -7956,15 +7983,39 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { +#else + struct edid *edid; + struct i2c_adapter *ddc; + + if (dc_link && dc_link->aux_mode) + ddc = &aconnector->dm_dp_aux.aux.ddc; + else + ddc = &aconnector->i2c->base; + + /* + * Note: drm_get_edid gets edid in the following order: + * 1) override EDID if set via edid_override debugfs, + * 2) firmware EDID if set via edid_firmware module parameter + * 3) regular DDC read. + */ + edid = drm_get_edid(connector, ddc); + if (!edid) { +#endif drm_err(dev, "No EDID found on connector: %s.\n", connector->name); return; } +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid; +#else + aconnector->edid = edid; +#endif /* Update emulated (virtual) sink's EDID */ if (dc_em_sink && dc_link) { +#ifdef HAVE_DRM_DP_MST_EDID_READ // FIXME: Get rid of drm_edid_raw() const struct edid *edid = drm_edid_raw(drm_edid); +#endif memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); memmove(dc_em_sink->dc_edid.raw_edid, edid, @@ -8006,6 +8057,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_VIRTUAL }; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; const struct edid *edid; struct i2c_adapter *ddc; @@ -8018,16 +8070,42 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { +#else + struct dc_link *dc_link = aconnector->dc_link; + struct edid *edid; + struct i2c_adapter *ddc; + + if (dc_link->aux_mode) + ddc = &aconnector->dm_dp_aux.aux.ddc; + else + ddc = &aconnector->i2c->base; + + /* + * Note: drm_get_edid gets edid in the following order: + * 1) override EDID if set via edid_override debugfs, + * 2) firmware EDID if set via edid_firmware module parameter + * 3) regular DDC read. + */ + edid = drm_get_edid(connector, ddc); + if (!edid) { +#endif drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name); return; } +#ifdef HAVE_DRM_DP_MST_EDID_READ if (connector->display_info.is_hdmi) init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; aconnector->drm_edid = drm_edid; edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#else + if (drm_detect_hdmi_monitor(edid)) + init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; + + aconnector->edid = edid; +#endif aconnector->dc_em_sink = dc_link_add_remote_sink( aconnector->dc_link, (uint8_t *)edid, @@ -8848,17 +8926,28 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector) } static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (drm_edid) { +#else + if (edid) { +#endif /* empty probed_modes */ INIT_LIST_HEAD(&connector->probed_modes); amdgpu_dm_connector->num_modes = +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_add_modes(connector); - +#else + drm_add_edid_modes(connector, edid); +#endif /* sorting the probed modes before calling function * amdgpu_dm_get_native_mode() since EDID can have * more than one preferred mode. The modes that are @@ -8874,7 +8963,11 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, * drm_edid_connector_add_modes() and need to be * restored here. */ +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_update_freesync_caps(connector, drm_edid); +#else + amdgpu_dm_update_freesync_caps(connector, edid); +#endif } else { amdgpu_dm_connector->num_modes = 0; } @@ -8974,12 +9067,20 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) } static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!(amdgpu_freesync_vid_mode && drm_edid)) +#else + if (!(amdgpu_freesync_vid_mode && edid)) +#endif return; if (!amdgpu_dm_connector->dc_sink || !amdgpu_dm_connector->dc_link) @@ -9003,13 +9104,21 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) to_amdgpu_dm_connector(connector); struct dc_link *dc_link = amdgpu_dm_connector->dc_link; struct drm_encoder *encoder; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; +#else + struct edid *edid = amdgpu_dm_connector->edid; +#endif struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap; const struct dc *dc = dc_link->dc; encoder = amdgpu_dm_connector_to_encoder(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid) { +#else + if (!edid) { +#endif amdgpu_dm_connector->num_modes = drm_add_modes_noedid(connector, 640, 480); if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) @@ -9027,10 +9136,18 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) connector, common_modes[i].w, common_modes[i].h); } } else { +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); +#else + amdgpu_dm_connector_ddc_get_modes(connector, edid); +#endif if (encoder) amdgpu_dm_connector_add_common_modes(encoder, connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); +#else + amdgpu_dm_connector_add_freesync_modes(connector, edid); +#endif } amdgpu_dm_fbc_init(connector); @@ -13426,7 +13543,11 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, * FreeSync parameters. */ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { int i = 0; struct amdgpu_dm_connector *amdgpu_dm_connector = @@ -13435,7 +13556,9 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct dc_sink *sink; struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid; +#endif bool freesync_capable = false; enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; @@ -13448,9 +13571,13 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->dc_sink : amdgpu_dm_connector->dc_em_sink; +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update(connector, drm_edid); if (!drm_edid || !sink) { +#else + if (!edid || !sink) { +#endif dm_con_state = to_dm_connector_state(connector->state); amdgpu_dm_connector->min_vfreq = 0; @@ -13465,7 +13592,9 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) goto update; +#ifdef HAVE_DRM_DP_MST_EDID_READ edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif #ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE /* Some eDP panels only have the refresh rate range info in DisplayID */ @@ -13493,7 +13622,11 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; } +#ifdef HAVE_DRM_DP_MST_EDID_READ } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#else + } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#endif i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (i >= 0 && vsdb_info.freesync_supported) { amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 0f8cbf63cc505..29f6b2f3d8d10 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -774,7 +774,11 @@ struct amdgpu_dm_connector { /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; +#else + struct edid *edid; +#endif /* shared with amdgpu */ struct amdgpu_hpd hpd; @@ -1067,7 +1071,11 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid); +#else + struct edid *edid); +#endif void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index b3e8ec55e8e52..02ecacfe9b2f9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1166,6 +1166,7 @@ bool dm_helpers_is_dp_sink_present(struct dc_link *link) return dp_sink_present; } +#ifdef HAVE_DRM_DP_MST_EDID_READ static int dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len) { @@ -1226,6 +1227,7 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector) return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector); } +#endif void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps) { @@ -1244,7 +1246,9 @@ enum dc_edid_status dm_helpers_read_local_edid( struct i2c_adapter *ddc; int retry = 25; enum dc_edid_status edid_status = EDID_NO_RESPONSE; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; +#endif const struct edid *edid; if (link->aux_mode) @@ -1259,28 +1263,42 @@ enum dc_edid_status dm_helpers_read_local_edid( * do check sum and retry to make sure read correct edid. */ do { +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid = dm_helpers_read_acpi_edid(aconnector); if (drm_edid) drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name); else drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); +#else + edid = drm_get_edid(&aconnector->base, ddc); +#endif #ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid && connector->edid_corrupt) { +#else + if (!edid && connector->edid_corrupt) { +#endif connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } #endif +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid) +#else + if (!edid) +#endif continue; +#ifdef HAVE_DRM_DP_MST_EDID_READ edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif if (!edid || edid->extensions >= sizeof(sink->dc_edid.raw_edid) / EDID_LENGTH) return EDID_BAD_INPUT; @@ -1289,7 +1307,11 @@ enum dc_edid_status dm_helpers_read_local_edid( memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); /* We don't need the original edid anymore */ +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(drm_edid); +#else + kfree(edid); +#endif edid_status = dm_helpers_parse_edid_caps( link, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 397627d6d0169..870700f436229 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -173,7 +173,11 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) } #endif +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(aconnector->drm_edid); +#else + kfree(aconnector->edid); +#endif drm_connector_cleanup(connector); #if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) @@ -206,9 +210,15 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) static inline void amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector) { +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif aconnector->dsc_aux = NULL; +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX aconnector->mst_output_port->passthrough_aux = NULL; +#endif aconnector->mst_local_bw = 0; aconnector->vc_full_pbn = 0; } @@ -396,6 +406,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!aconnector) return drm_add_edid_modes(connector, NULL); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!aconnector->drm_edid) { const struct drm_edid *drm_edid; @@ -404,12 +415,25 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) aconnector->mst_output_port); if (!drm_edid) { +#else + if (!aconnector->edid) { + struct edid *edid; + edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); + + if (!edid) { +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, false); +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update( &aconnector->base, NULL); +#else + drm_connector_update_edid_property( + &aconnector->base, + NULL); +#endif DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); if (!aconnector->dc_sink) { @@ -441,7 +465,11 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) return ret; } +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid; +#else + aconnector->edid = edid; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, true); } @@ -456,13 +484,20 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) struct dc_sink_init_data init_params = { .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid; edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif dc_sink = dc_link_add_remote_sink( aconnector->dc_link, +#ifdef HAVE_DRM_DP_MST_EDID_READ (uint8_t *)edid, (edid->extensions + 1) * EDID_LENGTH, +#else + (uint8_t *)aconnector->edid, + (aconnector->edid->extensions + 1) * EDID_LENGTH, +#endif &init_params); if (!dc_sink) { @@ -506,7 +541,11 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( +#ifdef HAVE_DRM_DP_MST_EDID_READ connector, aconnector->drm_edid); +#else + connector, aconnector->edid); +#endif #if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) @@ -521,10 +560,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) } } +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update(&aconnector->base, aconnector->drm_edid); ret = drm_edid_connector_add_modes(connector); +#else + drm_connector_update_edid_property( + &aconnector->base, aconnector->edid); + ret = drm_add_edid_modes(connector, aconnector->edid); +#endif return ret; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b8dc3a858e01d..66e65d8e820b0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -367,6 +367,9 @@ /* drm_dp_mst_dsc_aux_for_port() is available */ #define HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT 1 +/* drm_dp_mst_edid_read() is available */ +#define HAVE_DRM_DP_MST_EDID_READ 1 + /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 new file mode 100644 index 0000000000000..6d733484238af --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.4-rc2-497-gc1c9042b2003 +dnl # drm/display/dp_mst: convert to struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_EDID_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_edid_read(NULL, NULL, NULL); + ], [drm_dp_mst_edid_read], [drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_EDID_READ, 1, + [drm_dp_mst_edid_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c9875af26988f..cbc0f5ec44dc7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS + AC_AMDGPU_DRM_DP_MST_EDID_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 24c2a403fa48d3c4b8072b5d33036087e713ef87 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 21 Oct 2024 16:05:17 +0800 Subject: [PATCH 1333/2070] drm/amdkcl: test whether usleep_range_state() is available It's caused by 4ba1ee36b0f95cb5a2f639e7d7ba959f75496db3 "drm/amd/display: Add a Precise Delay Routine" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/usleep_range_state.m4 | 17 +++++++++++++++++ include/kcl/kcl_delay.h | 18 ++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 66e65d8e820b0..0b0f6bf071fa1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1057,6 +1057,9 @@ /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 +/* usleep_range_stat() is available */ +#define HAVE_USLEEP_RANGE_STATE 1 + /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cbc0f5ec44dc7..1b8d06edb6f46 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,6 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_FSLEEP + AC_AMDGPU_USLEEP_RANGE_STATE AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT diff --git a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 new file mode 100644 index 0000000000000..7540052fefc59 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.16-rc4-168-ge4779015fd5d +dnl # timers: implement usleep_idle_range() +dnl # +AC_DEFUN([AC_AMDGPU_USLEEP_RANGE_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); + ], [usleep_range_state], [kernel/time/timer.c], [ + AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, + [usleep_range_state() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_delay.h b/include/kcl/kcl_delay.h index f5f2962c6bb6d..a7e76948be28c 100644 --- a/include/kcl/kcl_delay.h +++ b/include/kcl/kcl_delay.h @@ -1,6 +1,10 @@ #ifndef AMDKCL_DELAY_H #define AMDKCL_DELAY_H +#include +#include +#include + #ifndef HAVE_FSLEEP static inline void _kcl_fsleep(unsigned long usecs) { @@ -15,4 +19,18 @@ static inline void _kcl_fsleep(unsigned long usecs) #define fsleep _kcl_fsleep #endif + +#ifndef HAVE_USLEEP_RANGE_STATE +static inline void _kcl_usleep_range_state(unsigned long min, unsigned long max, + unsigned int state) +{ + if (state != TASK_UNINTERRUPTIBLE) + pr_warn_once("legacy kernel without usleep_range_state()\n"); + + usleep_range(min, max); +} + +#define usleep_range_state _kcl_usleep_range_state +#endif + #endif From 82e7db49e34c48e9a3f354159cd58f840e2e2ddd Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 15 Oct 2024 13:53:05 +0800 Subject: [PATCH 1334/2070] drm/amdkcl: test whether drm_dp_cec_attach() is available It's caused by 73497e063c6dc0d6d9224175475ada8b67a60907 "drm/amd/display: switch to setting physical address directly" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ++++++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fd35e83e5b7dd..2b641a2749ab4 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3986,24 +3986,21 @@ void amdgpu_dm_update_connector_after_detect( drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { -#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; - +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); drm_edid_connector_update(connector, aconnector->drm_edid); +#else + aconnector->edid = edid; +#endif hdmi_cec_set_edid(aconnector); if (aconnector->dc_link->aux_mode) +#ifdef HAVE_DRM_DP_CEC_ATTACH drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, connector->display_info.source_physical_address); #else - aconnector->edid = - (struct edid *)sink->dc_edid.raw_edid; - - hdmi_cec_set_edid(aconnector); - if (aconnector->dc_link->aux_mode) - drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, - aconnector->edid); + drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, edid); #endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0b0f6bf071fa1..8ab2c2a7f1bc7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -331,6 +331,9 @@ /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 +/* drm_dp_cec_attach() is available */ +#define HAVE_DRM_DP_CEC_ATTACH 1 + /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 new file mode 100644 index 0000000000000..b17bff9ecd850 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.5-rc2-872-g113cdddcded6 +dnl # drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_ATTACH], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_cec_attach(NULL, 0); + ], [drm_dp_cec_attach], [drivers/gpu/drm/display/drm_dp_cec.c], [ + AC_DEFINE(HAVE_DRM_DP_CEC_ATTACH, 1, + [drm_dp_cec_attach() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1b8d06edb6f46..10f453f5ba3b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -223,6 +223,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_DRM_DP_MST_EDID_READ + AC_AMDGPU_DRM_DP_CEC_ATTACH AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 5278be1e9223d0618e9b97aa2a45021730562094 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 28 Oct 2024 17:21:46 +0800 Subject: [PATCH 1335/2070] drm/amdkcl: update initrd for oot build Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec index dd92860353f46..5f00c10afe2db 100644 --- a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -60,6 +60,7 @@ if [ -x "/usr/sbin/weak-modules" ]; then printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules fi +dracut -f --kver %{kernel}.%{_arch} %preun echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" >> /var/run/rpm-%{pkg}-modules.list @@ -78,6 +79,7 @@ if [ -x "/usr/sbin/weak-modules" ]; then printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules fi rm /var/run/rpm-%{pkg}-modules.list +dracut -f --kver %{kernel}.%{_arch} %files /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko From 2707d1f7fd57b83b8e67350f884006be9d272785 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 28 Oct 2024 14:29:00 +0800 Subject: [PATCH 1336/2070] drm/amdkcl: fix miss code under HAVE_DRM_DP_MST_EDID_READ It's caused by 457fdc01f440a3ac2c32d9784fd015f112da7692 "drm/amd/display: always call connector_update when parsing freesync_caps" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2b641a2749ab4..bb72d19f759a6 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13573,6 +13573,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!drm_edid || !sink) { #else + drm_connector_update_edid_property(connector, edid); + if (!edid || !sink) { #endif dm_con_state = to_dm_connector_state(connector->state); From 6fec385fd7bc7aa2ccc27c5d22829df3b887dda8 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 30 Oct 2024 17:16:15 +0800 Subject: [PATCH 1337/2070] drm/amdkcl: fix missing header file It's caused by following commit 14c2c55eca4b07a2cbe7fd62562f8cf9c327c1cd "drm/amdgpu: correct the S3 abort check condition" This commit fixes a compilation issue caused by linux/suspend.h that isn't included in some c files in older kernel versions. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_suspend.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index 37a3cab923aa5..a5299f997479f 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -2,6 +2,8 @@ #ifndef AMDKCL_SUSPEND_H #define AMDKCL_SUSPEND_H +#include + #ifndef HAVE_KSYS_SYNC_HELPER #ifdef CONFIG_PM_SLEEP extern void _kcl_ksys_sync_helper(void); From 956ddc065f39d0ad9f7f347331b67624ae7349c5 Mon Sep 17 00:00:00 2001 From: Cruz Zhao Date: Thu, 31 Oct 2024 12:33:05 +0800 Subject: [PATCH 1338/2070] drm/amdkfd: fix the incorrect exception handling logic in function amd_acquire() In function amd_acquire(), kfd_get_process() is call to get process. When judge whether we get an exception pointer, we shouldn't judge whether it's a null pointer, because kfd_get_process will return ERR_PTR(-EINVAL) instead of null pointer if error. Because of this wrong logic, the kernel will panic then once kfd_get_process() returns ERR_PTR(-EINVAL). So, the correct logic should be: if (IS_ERR(p)) { Fixes: commit 779b4d05a1c9("drm/amdkfd: Add RDMA and PeerDirect support") Signed-off-by: Cruz Zhao Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 637a6ceaffefe..ed93247d83caa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -178,7 +178,7 @@ static int amd_acquire(unsigned long addr, size_t size, p = peer_mem_private_data; } else { p = kfd_get_process(current); - if (!p) { + if (IS_ERR(p)) { pr_debug("Not a KFD process\n"); return 0; } From 36ad448ebcb59d067ba1df1c80b607d63a17fec4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 19:32:12 +0800 Subject: [PATCH 1339/2070] drm/amdkcl: check whether .fop_flags is in file_operation It's caused by v6.9-rc1-17-g210a03c9d51a fs: claw back a few FMODE_* bits Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 | 21 +++++++++++++++++++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 192dd75682243..29434782f9a89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3082,7 +3082,9 @@ static const struct file_operations amdgpu_driver_kms_fops = { #ifdef CONFIG_PROC_FS .show_fdinfo = drm_show_fdinfo, #endif +#ifdef HAVE_FILE_OPERATION_FOP_FLAGS .fop_flags = FOP_UNSIGNED_OFFSET, +#endif }; int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 10f453f5ba3b0..fb67d0e9af5aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -224,6 +224,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_DRM_DP_MST_EDID_READ AC_AMDGPU_DRM_DP_CEC_ATTACH + AC_AMDGPU_STRUCT_FILE_OPERATION AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 new file mode 100644 index 0000000000000..07011778633f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.9-rc1-17-g210a03c9d51a +dnl # fs: claw back a few FMODE_* bits +dnl # +AC_DEFUN([AC_AMDGPU_FILE_OPERATION_FOP_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct file_operations file_operation; + file_operation.fop_flags = 0; + ],[ + AC_DEFINE(HAVE_FILE_OPERATION_FOP_FLAGS, 1, + [file_operation->fop_flags is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_FILE_OPERATION], [ + AC_AMDGPU_FILE_OPERATION_FOP_FLAGS +]) From 94c789a1119e600882c7cb52e1bd6b3f27aad237 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 19:51:59 +0800 Subject: [PATCH 1340/2070] drm/amdkcl: fake linux/unasigned.h It's caused by v6.12-rc1-3-g5f60d5f6bbc1 move asm/unaligned.h to linux/unaligned.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 +++++ include/kcl/header/linux/unaligned.h | 12 ++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/kcl/header/linux/unaligned.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index e66cb05345fe6..3e79dfb6f8ea8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -111,4 +111,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_ttm.h]) + dnl # + dnl # v6.12-rc1-3-g5f60d5f6bbc1 + dnl # move asm/unaligned.h to linux/unaligned.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/unaligned.h]) ]) diff --git a/include/kcl/header/linux/unaligned.h b/include/kcl/header/linux/unaligned.h new file mode 100644 index 0000000000000..e64489be09fe2 --- /dev/null +++ b/include/kcl/header/linux/unaligned.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_UNALIGNED_H +#define _KCL_HEADER_LINUX_UNALIGNED_H + +#ifdef HAVE_LINUX_UNALIGNED_H +#include_next +#else +#include +#endif + +#endif + From 182c8123b3455ce4c69c9ff4ab66173ffa6782d1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 20:05:26 +0800 Subject: [PATCH 1341/2070] drm/amdkcl: define macro BACKLIGHT_POWER_ON It's caused by v6.10-rc1-7-ga1cacb8a8e70 backlight: Add BACKLIGHT_POWER_ constants for power states Signed-off-by: Asher Song --- include/kcl/kcl_backlight.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_backlight.h b/include/kcl/kcl_backlight.h index 1d06b61502c3c..bc2696815393d 100644 --- a/include/kcl/kcl_backlight.h +++ b/include/kcl/kcl_backlight.h @@ -13,4 +13,11 @@ int backlight_device_set_brightness(struct backlight_device *bd, unsigned long brightness); #endif /* HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS */ + +#ifndef BACKLIGHT_POWER_ON +#define BACKLIGHT_POWER_ON (0) +#define BACKLIGHT_POWER_OFF (4) +#define BACKLIGHT_POWER_REDUCED (1) // deprecated; don't use in new code +#endif + #endif From 7f670a4a4e47dc84af8e754e3383fec3373b8a9c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 20:41:52 +0800 Subject: [PATCH 1342/2070] drm/amdkcl: define macro fd_file It's caused by v6.11-rc1-1-g1da91ea87aef introduce fd_file(), convert all accessors to it. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_file.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_file.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bafa11f20512c..265a065628672 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -123,4 +123,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_file.h b/include/kcl/kcl_file.h new file mode 100644 index 0000000000000..2b81dc3f31644 --- /dev/null +++ b/include/kcl/kcl_file.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LINUX_FILE_H +#define AMDKCL_LINUX_FILE_H + +#include + +#ifndef fd_file +#define fd_file(f) ((f).file) +#endif + +#endif From be8f540906409dc482b8d9fd58faacb53ed67c3d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 12 Nov 2024 11:50:21 +0800 Subject: [PATCH 1343/2070] drm/amdkcl: check macro MAX whether exists in linux/minmax.h It's caused by v6.11-rc1-1-g1a251f52cfdc minmax: make generic MIN() and MAX() macros available everywhere Signed-off-by: Asher Song --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 6fd50c2fd20e0..91f24aede8560 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -880,7 +880,11 @@ static const char *smu_get_feature_name(struct smu_context *smu, size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, char *buf) { +#ifdef MAX int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; +#else + int8_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; +#endif struct smu_feature_bits feature_mask; uint32_t features[2]; int i, feature_index; From 5a401b443a253e13615aae457c94a699748c1b90 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Nov 2024 14:46:43 +0800 Subject: [PATCH 1344/2070] drm/amdkcl: test follow_pfnmap_start whether exist It's caused by v6.11-rc6-389-g6da8e9634bb7 mm: new follow_pfnmap API Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_memory.c | 15 ++++++++++++++- drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 | 20 +++++++++++++++++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_memory.c b/drivers/gpu/drm/amd/backport/kcl_memory.c index 153710b6883de..2ade0fbdbc8e1 100644 --- a/drivers/gpu/drm/amd/backport/kcl_memory.c +++ b/drivers/gpu/drm/amd/backport/kcl_memory.c @@ -5,14 +5,27 @@ int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, unsigned long *pfn) { int ret = -EINVAL; +#ifdef HAVE_FOLLOW_PFNMAP_START + struct follow_pfnmap_args args = { + .vma = vma, + .address = address, + }; + ret = follow_pfnmap_start(&args); + + if (ret) + return ret; + *pfn = args.pfn; + follow_pfnmap_end(&args); +#else spinlock_t *ptl; pte_t *ptep; - ret = follow_pte(vma, address, &ptep, &ptl); + if (ret) return ret; *pfn = pte_pfn(ptep_get(ptep)); pte_unmap_unlock(ptep, ptl); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 index ea2c47c00ab90..e702269ad9e9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 @@ -13,4 +13,22 @@ AC_DEFUN([AC_AMDGPU_FOLLOW_PFN], [ [follow_pfn() is available]) ]) ]) -]) \ No newline at end of file +]) + +dnl # +dnl # v6.11-rc6-389-g6da8e9634bb7 +dnl # mm: new follow_pfnmap API +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFNMAP_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfnmap_start(NULL); + ],[follow_pfnmap_start], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFNMAP_START, 1, + [follow_pfnmap_start() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fb67d0e9af5aa..279e1d253076a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -225,6 +225,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_EDID_READ AC_AMDGPU_DRM_DP_CEC_ATTACH AC_AMDGPU_STRUCT_FILE_OPERATION + AC_AMDGPU_FOLLOW_PFNMAP_START AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2d3fe3e5aea614bee70daa89f976ecfa9e184eed Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 11:29:58 +0800 Subject: [PATCH 1345/2070] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by following commit: b8521b1a8e7d0b "drm/amdgpu: add amdgpu_gfx_sched_mask and amdgpu_compute_sched_mask debugfs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index cab3196a87fb1..4c91cffee0431 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2553,9 +2553,15 @@ static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, amdgpu_debugfs_gfx_sched_mask_get, amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, + amdgpu_debugfs_gfx_sched_mask_get, + amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); +#endif #endif @@ -2624,9 +2630,15 @@ static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, amdgpu_debugfs_compute_sched_mask_get, amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, + amdgpu_debugfs_compute_sched_mask_get, + amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); +#endif #endif From 1fe5a72a9f8cdb6e4064223144e148280970a08e Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 12:03:51 +0800 Subject: [PATCH 1346/2070] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by following commit:9733f1d9355c3 "drm/amdgpu: add amdgpu_sdma_sched_mask debugfs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 321310ba2c08e..546a0c8f8c648 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -434,9 +434,15 @@ static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, amdgpu_debugfs_sdma_sched_mask_get, amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, + amdgpu_debugfs_sdma_sched_mask_get, + amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); +#endif #endif From 352c5bf96236356c27b3cf50471ef2eafda2f6f7 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 15:19:59 +0800 Subject: [PATCH 1347/2070] drm/amdkcl: test whether str_read_write() is is available It's caused by following commit: 8a65a9cb5c "drm/amdgpu: use string choice helpers" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 | 18 ++++++++++++++++++ include/kcl/kcl_string_helpers.h | 8 ++++++++ 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8ab2c2a7f1bc7..0c0094f0110c4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1045,6 +1045,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* str_read_write() is defined */ +#define HAVE_STR_READ_WRITE 1 + /* str_yes_no() is defined */ #define HAVE_STR_YES_NO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 279e1d253076a..f48a537ed7a4a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -163,6 +163,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_STR_READ_WRITE AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG diff --git a/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 b/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 new file mode 100644 index 0000000000000..df1463125da0d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 1f5d7ea73c4b630dbb2c90818cb9fc0be54d2fe3 +dnl # lib/string_helpers: Add str_read_write() helper +dnl # v6.0-rc1-122-g1f5d7ea73c4b +dnl # +AC_DEFUN([AC_AMDGPU_STR_READ_WRITE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str; + str = str_read_write(true); + ], [ + AC_DEFINE(HAVE_STR_READ_WRITE, 1, + [str_read_write() is defined]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h index e02c0059b3ade..7d65d60fc2200 100644 --- a/include/kcl/kcl_string_helpers.h +++ b/include/kcl/kcl_string_helpers.h @@ -27,4 +27,12 @@ static inline const char *str_enabled_disabled(bool v) } #endif /* HAVE_STR_YES_NO */ + +#ifndef HAVE_STR_READ_WRITE +static inline const char *str_read_write(bool v) +{ + return v ? "read" : "write"; +} +#endif + #endif From 406f732f1d92d901834ba45e5495d0a39a07e3de Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 14:39:55 +0800 Subject: [PATCH 1348/2070] drm/amdkcl: kcl-cleanup HAVE_RESERVATION_OBJECT_STAGED Change-Id: I7e226cc12719abd32970d33c08eaa965db50190b Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 153 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 22 --- include/kcl/kcl_dma-resv.h | 9 -- include/kcl/reservation.h | 17 --- 5 files changed, 4 insertions(+), 200 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index bad215a62e54d..e1b018386c601 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -37,155 +37,4 @@ void amdkcl_reservation_init(void) { amdkcl_fp_setup("reservation_ww_class", NULL); -} - -#if defined(HAVE_RESERVATION_OBJECT_STAGED) -/* - * Copied from v4.19-rc6-1514-g27836b641c1b^:drivers/dma-buf/reservation.c - * and modified for KCL - */ -static void -reservation_object_add_shared_inplace(struct reservation_object *obj, - struct reservation_object_list *fobj, - struct dma_fence *fence) -{ - struct dma_fence *signaled = NULL; - u32 i, signaled_idx; - - dma_fence_get(fence); - - preempt_disable(); - write_seqcount_begin(&obj->seq); - - for (i = 0; i < fobj->shared_count; ++i) { - struct dma_fence *old_fence; - - old_fence = rcu_dereference_protected(fobj->shared[i], - dma_resv_held(obj)); - - if (old_fence->context == fence->context) { - /* memory barrier is added by write_seqcount_begin */ - RCU_INIT_POINTER(fobj->shared[i], fence); - write_seqcount_end(&obj->seq); - preempt_enable(); - - dma_fence_put(old_fence); - return; - } - - if (!signaled && dma_fence_is_signaled(old_fence)) { - signaled = old_fence; - signaled_idx = i; - } - } - - /* - * memory barrier is added by write_seqcount_begin, - * fobj->shared_count is protected by this lock too - */ - if (signaled) { - RCU_INIT_POINTER(fobj->shared[signaled_idx], fence); - } else { - BUG_ON(fobj->shared_count >= fobj->shared_max); - RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); - fobj->shared_count++; - } - - write_seqcount_end(&obj->seq); - preempt_enable(); - - dma_fence_put(signaled); -} - -static void -reservation_object_add_shared_replace(struct reservation_object *obj, - struct reservation_object_list *old, - struct reservation_object_list *fobj, - struct dma_fence *fence) -{ - unsigned i, j, k; - - dma_fence_get(fence); - - if (!old) { - RCU_INIT_POINTER(fobj->shared[0], fence); - fobj->shared_count = 1; - goto done; - } - - /* - * no need to bump fence refcounts, rcu_read access - * requires the use of kref_get_unless_zero, and the - * references from the old struct are carried over to - * the new. - */ - for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) { - struct dma_fence *check; - - check = rcu_dereference_protected(old->shared[i], - dma_resv_held(obj)); - - if (check->context == fence->context || - dma_fence_is_signaled(check)) - RCU_INIT_POINTER(fobj->shared[--k], check); - else - RCU_INIT_POINTER(fobj->shared[j++], check); - } - fobj->shared_count = j; - RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); - fobj->shared_count++; - -done: - preempt_disable(); - write_seqcount_begin(&obj->seq); - /* - * RCU_INIT_POINTER can be used here, - * seqcount provides the necessary barriers - */ - RCU_INIT_POINTER(obj->fence, fobj); - write_seqcount_end(&obj->seq); - preempt_enable(); - - if (!old) - return; - - /* Drop the references to the signaled fences */ - for (i = k; i < fobj->shared_max; ++i) { - struct dma_fence *f; - - f = rcu_dereference_protected(fobj->shared[i], - dma_resv_held(obj)); - dma_fence_put(f); - } - kfree_rcu(old, rcu); -} - -void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) -{ - struct dma_resv_list *old, *fobj = obj->staged; - - old = dma_resv_shared_list(obj); - obj->staged = NULL; - - if (!fobj) - reservation_object_add_shared_inplace(obj, old, fence); - else - reservation_object_add_shared_replace(obj, old, fobj, fence); -} -EXPORT_SYMBOL(_kcl_dma_resv_add_shared_fence); - -int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) -{ - int ret; - - ret = dma_resv_copy_fences(dst, src); - if (ret) - return ret; - - kfree(dst->staged); - dst->staged = NULL; - - return ret; -} -EXPORT_SYMBOL(_kcl_dma_resv_copy_fences); -#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0c0094f0110c4..9ffcb8e32038a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -948,6 +948,9 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ +/* request_firmware_direct() is available */ +#define HAVE_REQUEST_FIRMWARE_DIRECT 1 + /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index f65379d76636f..baeb0ee766979 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -56,28 +56,6 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ ]) ]) - -dnl # -dnl # v4.19-rc6-1514-g27836b641c1b -dnl # dma-buf: remove shared fence staging in reservation object -dnl # -AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([test x$HAVE_LINUX_DMA_RESV_H = x ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct reservation_object *resv = NULL; - resv->staged = NULL; - ], [ - AC_DEFINE(HAVE_RESERVATION_OBJECT_STAGED, 1, - [reservation_object->staged is available]) - ]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_FENCES - AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index a6b8ab359aa0d..4c2b2576374ed 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -187,15 +187,6 @@ struct dma_resv { struct dma_fence __rcu *fence_excl; struct dma_resv_list __rcu *fence; }; -#elif defined(HAVE_RESERVATION_OBJECT_STAGED) -struct dma_resv { - struct ww_mutex lock; - seqcount_t seq; - - struct dma_fence __rcu *fence_excl; - struct dma_resv_list __rcu *fence; - struct dma_resv_list *staged; -}; #else struct dma_resv { struct ww_mutex lock; diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h index fbd036fdd650d..8dcc5e3c18479 100644 --- a/include/kcl/reservation.h +++ b/include/kcl/reservation.h @@ -4,23 +4,6 @@ #ifndef HAVE_LINUX_DMA_RESV_H #include - -#if defined(HAVE_RESERVATION_OBJECT_STAGED) -static inline void -_kcl_reservation_object_fini(struct reservation_object *obj) -{ - dma_resv_fini(obj); - kfree(obj->staged); -} -#define amddma_resv_fini _kcl_reservation_object_fini - -void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence); -#define amddma_resv_add_shared_fence _kcl_dma_resv_add_shared_fence - -int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src); -#define amddma_resv_copy_fences _kcl_dma_resv_copy_fences - -#endif /* HAVE_RESERVATION_OBJECT_STAGED */ #endif /* HAVE_LINUX_DMA_RESV_H */ #endif From 61c1da32648b7a4aebabebae1ec7f65d491b742b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2024 14:36:23 +0800 Subject: [PATCH 1349/2070] drm/amdkcl: move reservation_ww_class check to compile-time Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 40 -------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/Makefile | 4 ++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 10 +++++ 5 files changed, 15 insertions(+), 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_reservation.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8239c1478a928..efe970c8e4c62 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ - kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ + kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c deleted file mode 100644 index e1b018386c601..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) - * - * Based on bo.c which bears the following copyright notice, - * but is dual licensed: - * - * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ -/* - * Authors: Thomas Hellstrom - */ -#include - -void amdkcl_reservation_init(void) -{ - amdkcl_fp_setup("reservation_ww_class", NULL); -} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 487bacf96db43..0cb299f8b9489 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -5,7 +5,6 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); -extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); @@ -18,7 +17,6 @@ int __init amdkcl_init(void) amdkcl_symbol_init(); amdkcl_dev_cgroup_init(); amdkcl_fence_init(); - amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0e41d5633a6f9..6153df061bcd8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -52,6 +52,10 @@ ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) $(error dma_resv->seq is missing. exit...) endif +ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) +$(error reservation_ww_class is missing. exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index baeb0ee766979..8f83620935f38 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -56,6 +56,16 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ ]) ]) +AC_DEFUN([AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([reservation_ww_class],[drivers/dma-buf/dma-resv.c], + [],[ + AC_DEFINE(HAVE_RESERVATION_WW_CLASS_BUG, 1, [Reporting reservation_ww_class missing]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_FENCES + AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS ]) From 0bd1af003e7479f4243f96e6a6fcd4703339a18b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2024 14:40:44 +0800 Subject: [PATCH 1350/2070] drm/amdkcl: use kprobe for address resolution of unexported functions Replaces the usage of kallsyms_lookup_name with kprobe to obtain the addresses of kernel functions that are not exported. Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_common.c | 41 ++++++++++++------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- 2 files changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c index 5867b4d1a6c38..3d11e965887ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -5,7 +5,26 @@ #include #include -unsigned long (*_kcl_kallsyms_lookup_name)(const char *name); +static unsigned long _kcl_kallsyms_lookup_name(const char *name) +{ + unsigned long addr = 0; +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = name; + r = register_kprobe(&kp); + if (!r) { + addr = (unsigned long)kp.addr; + unregister_kprobe(&kp); + } +#else + addr = kallsyms_lookup_name(name); +#endif + + return addr; +} void *amdkcl_fp_setup(const char *symbol, void *dummy) { @@ -27,23 +46,3 @@ void *amdkcl_fp_setup(const char *symbol, void *dummy) return fp; } -void amdkcl_symbol_init(void) -{ -#ifndef HAVE_KALLSYMS_LOOKUP_NAME - struct kprobe kp; - int r; - - memset(&kp, 0, sizeof(kp)); - kp.symbol_name = "kallsyms_lookup_name"; - r = register_kprobe(&kp); - if (!r) { - _kcl_kallsyms_lookup_name = (void *)kp.addr; - unregister_kprobe(&kp); - } else { - pr_err("fail to get kallsyms_lookup_name, abort...\n"); - BUG(); - } -#else - _kcl_kallsyms_lookup_name = kallsyms_lookup_name; -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 0cb299f8b9489..7b33f819a874f 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -2,7 +2,6 @@ #include #include -extern void amdkcl_symbol_init(void); extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); @@ -14,7 +13,6 @@ extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { - amdkcl_symbol_init(); amdkcl_dev_cgroup_init(); amdkcl_fence_init(); amdkcl_io_init(); From bb833a9be2493a7cfa8f2be0a99b45e9ce3560a2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Nov 2024 14:43:26 +0800 Subject: [PATCH 1351/2070] drm/amdkcl: wrap code under macro AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT when AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT isn't defined, _kcl_fence_default_wait_cb isn't used. So avoid call the amdkcl_fp_setup. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 6b962278954e6..e79e331222d00 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -50,9 +50,9 @@ struct default_wait_cb { struct task_struct *task; }; +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT signed long _kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) { @@ -238,7 +238,9 @@ EXPORT_SYMBOL(_kcl_fence_enable_signaling); */ void amdkcl_fence_init(void) { +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); +#endif } #if !defined(HAVE_DMA_FENCE_DESCRIBE) From 5ff44586355fde528fd76aa4b909c98f232eb021 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 4 Nov 2024 16:20:39 +0800 Subject: [PATCH 1352/2070] drm/amdkcl: fake the Macro definition drm_WARN_ON_ONCE It's caused by following commit a2529f67e20 "drm/amdgpu: Use drm_print_memory_stats helper from fdinfo" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 0506b7a41f121..a4e435d18106e 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -54,6 +54,12 @@ dev_name((drm)->dev), ## arg) #endif +#ifndef drm_WARN_ON_ONCE +#define drm_WARN_ON_ONCE(drm, x) \ + drm_WARN_ONCE((drm), (x), "%s", \ + "drm_WARN_ON_ONCE(" __stringify(x) ")") +#endif + #ifndef drm_WARN #define drm_WARN(drm, condition, format, arg...) \ WARN(condition, "%s %s: " format, \ From b4718394f464e9b56d2dc981e2384c5d640c0c9e Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 4 Nov 2024 13:41:58 +0800 Subject: [PATCH 1353/2070] drm/amdkcl: test whether drm_print_memory_stats() is available It's caused by following commit a2529f67e20 "drm/amdgpu: Use drm_print_memory_stats helper from fdinfo" Signed-off-by: chengjya Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/backport/include/kcl/kcl_drm_file.h | 22 +++++++++++- drivers/gpu/drm/amd/backport/kcl_drm_file.c | 35 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_memoty_status.m4 | 23 ++++++++++++ include/kcl/kcl_drm_gem.h | 8 +++++ 7 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 265a065628672..da6ed263f834c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -64,6 +64,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index a067b59578b6c..91ea254aa7434 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -1,8 +1,28 @@ #ifndef __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ #define __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ -#include +#include +#include +#include +#include #ifndef HAVE_DRM_SHOW_FDINFO void drm_show_fdinfo(struct seq_file *m, struct file *f); #endif + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +struct drm_memory_stats { + u64 shared; + u64 private; + u64 resident; + u64 purgeable; + u64 active; +}; + +void _kcl_drm_print_memory_stats(struct drm_printer *p, + const struct drm_memory_stats *stats, + enum drm_gem_object_status supported_status, + const char *region); +#define drm_print_memory_stats _kcl_drm_print_memory_stats; +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index 5bc74f05d555e..a6d0cea48cecf 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -67,4 +67,39 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) amdgpu_show_fdinfo(&p, file); } + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +static void print_size(struct drm_printer *p, const char *stat, + const char *region, u64 sz) +{ + const char *units[] = {"", " KiB", " MiB"}; + unsigned u; + + for (u = 0; u < ARRAY_SIZE(units) - 1; u++) { + if (sz == 0 || !IS_ALIGNED(sz, SZ_1K)) + break; + sz = div_u64(sz, SZ_1K); + } + + drm_printf(p, "drm-%s-%s:\t%llu%s\n", stat, region, sz, units[u]); +} + +void _kcl_drm_print_memory_stats(struct drm_printer *p, + const struct drm_memory_stats *stats, + enum drm_gem_object_status supported_status, + const char *region) +{ + print_size(p, "total", region, stats->private + stats->shared); + print_size(p, "shared", region, stats->shared); + print_size(p, "active", region, stats->active); + + if (supported_status & DRM_GEM_OBJECT_RESIDENT) + print_size(p, "resident", region, stats->resident); + + if (supported_status & DRM_GEM_OBJECT_PURGEABLE) + print_size(p, "purgeable", region, stats->purgeable); +} +EXPORT_SYMBOL(_kcl_drm_print_memory_stats); +#endif + #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9ffcb8e32038a..d9e241e5a4879 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -630,6 +630,9 @@ /* drm_print_bits() has 4 args */ #define HAVE_DRM_PRINT_BITS_4ARGS 1 +/* drm_print_memory_stats() is available */ +#define HAVE_DRM_PRINT_MEMORY_STATS 1 + /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f48a537ed7a4a..62e7752247885 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -227,6 +227,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_ATTACH AC_AMDGPU_STRUCT_FILE_OPERATION AC_AMDGPU_FOLLOW_PFNMAP_START + AC_AMDGPU_DRM_FILE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 new file mode 100644 index 0000000000000..3e25ff65320cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v6.4-rc1-193-g686b21b5f6ca +dnl # drm: Add fdinfo memory stats +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + enum drm_gem_object_status res = 0; + res |= DRM_GEM_OBJECT_RESIDENT; + drm_print_memory_stats(NULL, NULL, res, NULL); + ],[drm_print_memory_stats], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_PRINT_MEMORY_STATS, 1, + [drm_print_memory_stats() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_FILE], [ + AC_AMDGPU_DRM_PRINT_MEMORY_STATS +]) diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index 73518a8a22f8b..cea563821fa86 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,6 +35,14 @@ #define __KCL_KCL_DRM_GEM_H__ #include + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +enum drm_gem_object_status { + DRM_GEM_OBJECT_RESIDENT = BIT(0), + DRM_GEM_OBJECT_PURGEABLE = BIT(1), +}; +#endif + #if defined(HAVE_DRM_GEM_OBJECT_PUT) #if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) static inline void From 0c1aee0890ab715f3d1a90bf5bca7e6ad648bf1d Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 6 Nov 2024 17:35:23 +0800 Subject: [PATCH 1354/2070] drm/amdkcl: test wether drm_dp_mst_topology_queue_probe() is available It's caused by following commit 7f6d4ea8399ad "drm/amd/display: Don't write DP_MSTM_CTRL after LT" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../drm/amd/amdkcl/kcl_drm_dp_mst_topology.c | 71 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../m4/drm_dp_mst_topology_queue_probe.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 5 ++ 6 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index efe970c8e4c62..b17ff92f2265a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c new file mode 100644 index 0000000000000..d6b4e9d0f77be --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c @@ -0,0 +1,71 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include + +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +static void _kcl_drm_dp_mst_queue_probe_work(struct drm_dp_mst_topology_mgr *mgr) +{ + queue_work(system_long_wq, &mgr->work); +} + +static void +_kcl_drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) +{ + struct drm_dp_mst_port *port; + + /* The link address will need to be re-sent on resume */ + mstb->link_address_sent = false; + + list_for_each_entry(port, &mstb->ports, next) + if (port->mstb) + _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb); +} + +/** + * drm_dp_mst_topology_queue_probe - Queue a topology probe + * @mgr: manager to probe + * + * Queue a work to probe the MST topology. Driver's should call this only to + * sync the topology's HW->SW state after the MST link's parameters have + * changed in a way the state could've become out-of-sync. This is the case + * for instance when the link rate between the source and first downstream + * branch device has switched between UHBR and non-UHBR rates. Except of those + * cases - for instance when a sink gets plugged/unplugged to a port - the SW + * state will get updated automatically via MST UP message notifications. + */ +void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) +{ + mutex_lock(&mgr->lock); + + if (drm_WARN_ON(mgr->dev, !mgr->mst_state || !mgr->mst_primary)) + goto out_unlock; + + _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(mgr->mst_primary); + _kcl_drm_dp_mst_queue_probe_work(mgr); + +out_unlock: + mutex_unlock(&mgr->lock); +} +EXPORT_SYMBOL(_kcl_drm_dp_mst_topology_queue_probe); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d9e241e5a4879..79c359a6bf60e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -412,6 +412,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* drm_dp_mst_topology_queue_probe() is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE 1 + /* struct drm_dp_mst_topology_state has member payloads */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 new file mode 100644 index 0000000000000..1aace85d3c0f1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3523-gb1c1c23eae66 +dnl # drm/dp_mst: Add a helper to queue a topology probe +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_topology_queue_probe(NULL); + ], [drm_dp_mst_topology_queue_probe], [drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE, 1, + [drm_dp_mst_topology_queue_probe() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 62e7752247885..b96922a703460 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -228,6 +228,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_FILE_OPERATION AC_AMDGPU_FOLLOW_PFNMAP_START AC_AMDGPU_DRM_FILE + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index a84cd2ac22cc2..a6e237c081029 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -117,4 +117,9 @@ _kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 #endif +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); +#define drm_dp_mst_topology_queue_probe _kcl_drm_dp_mst_topology_queue_probe +#endif + #endif From fc3a0a71dd47fa35f12c8e97b8a3d3cfc9f81554 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 8 Nov 2024 16:36:24 +0800 Subject: [PATCH 1355/2070] drm/amdkcl: wrap code under HAVE_DRM_GEM_OBJECT_RESV It's caused by following commit:fefc81edfd0ca40ef283 "drm/amdgpu: fix check in gmc_v9_0_get_vm_pte()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_resource.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 5475507f0e07e..aa95cb4818ee1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1088,7 +1088,7 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, bool snoop = false; bool is_local; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); switch (gc_ip_version) { case IP_VERSION(9, 4, 1): diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index b185c3a2626bd..b061563479b19 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1274,7 +1274,7 @@ int ttm_bo_populate(struct ttm_buffer_object *bo, bool swapped; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (!tt) return 0; diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index e267683099718..52a38b7f4f2fd 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -268,7 +268,7 @@ static bool ttm_resource_is_swapped(struct ttm_resource *res, struct ttm_buffer_ if (bo->resource != res || !bo->ttm) return false; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); return ttm_tt_is_swapped(bo->ttm); } From c81bd619112e6553d9adb63bb1a7d8302eb19871 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Nov 2024 19:57:31 +0800 Subject: [PATCH 1356/2070] drm/amdkcl: define macro FOP_UNSIGNED_OFFSET It's caused by v6.11-rc4-29-g641bb4394f40 fs: move FMODE_UNSIGNED_OFFSET to fop_flags Signed-off-by: Asher Song --- include/kcl/kcl_fs.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index 4a4c208d833e0..e05a4edacabda 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -19,4 +19,11 @@ static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, #define compat_ptr_ioctl NULL #endif /* CONFIG_COMPAT */ #endif /* HAVE_COMPAT_PTR_IOCTL */ + +#ifdef HAVE_FILE_OPERATION_FOP_FLAGS +#ifndef FOP_UNSIGNED_OFFSET +#define FOP_UNSIGNED_OFFSET ((__force fop_flags_t)(1 << 5)) +#endif +#endif + #endif From 413edb1811ccde4e04d6867a400055c7bc82e3ad Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 18 Nov 2024 14:45:44 +0800 Subject: [PATCH 1357/2070] drm/amdkcl: test whether drm_client_setup exists It's caused by v6.11-rc7-1514-gd07fdf922592 drm: Add client-agnostic setup helper v6.12-rc6-1222-gb86711c6d6e2 drm/client: Move public client header to clients/ subdirectory Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 15 ++++++++++- drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 25 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 12 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/header/drm/clients/drm_client_setup.h | 11 ++++++++ 5 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-client.m4 create mode 100644 include/kcl/header/drm/clients/drm_client_setup.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 29434782f9a89..516b6bf82e3e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2506,11 +2506,20 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* select 8 bpp console on low vram cards */ if (adev->gmc.real_vram_size <= (32*1024*1024)) +#if HAVE_DRM_CLIENT_SETUP format = drm_format_info(DRM_FORMAT_C8); +#else + drm_fbdev_ttm_setup(adev_to_drm(adev), 8); +#endif else +#if HAVE_DRM_CLIENT_SETUP format = NULL; - +#else + drm_fbdev_ttm_setup(adev_to_drm(adev), 32); +#endif +#if HAVE_DRM_CLIENT_SETUP drm_client_setup(adev_to_drm(adev), format); +#endif } ret = amdgpu_debugfs_init(adev); @@ -3172,7 +3181,9 @@ static struct drm_driver amdgpu_kms_driver = { .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, +#ifdef DRM_FBDEV_TTM_DRIVER_OPS DRM_FBDEV_TTM_DRIVER_OPS, +#endif .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, #ifdef HAVE_DRM_DRIVER_SHOW_FDINFO @@ -3230,7 +3241,9 @@ const struct drm_driver amdgpu_partition_driver = { .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, +#ifdef DRM_FBDEV_TTM_DRIVER_OPS DRM_FBDEV_TTM_DRIVER_OPS, +#endif .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 new file mode 100644 index 0000000000000..689086c18718e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -0,0 +1,25 @@ +dnl # +dnl # commit v6.11-rc7-1514-gd07fdf922592 +dnl # drm: Add client-agnostic setup helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_CLIENT_SETUP_H + #include + #endif + #ifdef HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H + #include + #endif + ], [ + drm_client_setup(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_CLIENT_SETUP, 1, + [drm_client_setup() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CLIENT], [ + AC_AMDGPU_DRM_CLIENT_SETUP +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 3e79dfb6f8ea8..1ec4bd7b9aabd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -116,4 +116,16 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # move asm/unaligned.h to linux/unaligned.h dnl # AC_KERNEL_CHECK_HEADERS([linux/unaligned.h]) + + dnl # + dnl # v6.11-rc7-1514-gd07fdf922592 + dnl # drm: Add client-agnostic setup helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_client_setup.h]) + + dnl # + dnl # v6.12-rc6-1222-gb86711c6d6e2 + dnl # drm/client: Move public client header to clients/ subdirectory + dnl # + AC_KERNEL_CHECK_HEADERS([drm/clients/drm_client_setup.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b96922a703460..0c86ea767eb2f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -229,6 +229,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FOLLOW_PFNMAP_START AC_AMDGPU_DRM_FILE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE + AC_AMDGPU_DRM_CLIENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/clients/drm_client_setup.h b/include/kcl/header/drm/clients/drm_client_setup.h new file mode 100644 index 0000000000000..58e21f2498f49 --- /dev/null +++ b/include/kcl/header/drm/clients/drm_client_setup.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_CLIENT_SETUP_H +#define _KCL_HEADER_DRM_DRM_CLIENT_SETUP_H + +#if defined(HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H) +#include_next +#elif defined(HAVE_DRM_DRM_CLIENT_SETUP_H) +#include +#endif + +#endif From 9eff12b1f2cda4ef58d2d1dccfe3978ff6a9501a Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 11 Nov 2024 16:04:24 +0800 Subject: [PATCH 1358/2070] drm/amdkcl: test whether drm_dp_mst_edid_read is available It's caused by 7f082eb3011c4f1146436bbf9c550b7adbcf42ec "drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 ++ .../drm/amd/dkms/m4/drm_syncobj_add_point.m4 | 16 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_syncobj.h | 19 +++++ 7 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 create mode 100644 include/kcl/kcl_drm_syncobj.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index b17ff92f2265a..a6d429412554b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o kcl_drm_dp_mst_topology.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c new file mode 100644 index 0000000000000..20393f00b0a47 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include +#include + +#ifndef HAVE_DRM_SYNCOBJ_ADD_POINT +struct syncobj_wait_entry { + struct list_head node; + struct task_struct *task; + struct dma_fence *fence; + struct dma_fence_cb fence_cb; + u64 point; +}; + +static void _kcl_syncobj_wait_syncobj_func(struct drm_syncobj *syncobj, + struct syncobj_wait_entry *wait) +{ + struct dma_fence *fence; + + /* This happens inside the syncobj lock */ + fence = rcu_dereference_protected(syncobj->fence, + lockdep_is_held(&syncobj->lock)); + dma_fence_get(fence); + if (!fence || dma_fence_chain_find_seqno(&fence, wait->point)) { + dma_fence_put(fence); + return; + } else if (!fence) { + wait->fence = dma_fence_get_stub(); + } else { + wait->fence = fence; + } + + wake_up_process(wait->task); + list_del_init(&wait->node); +} + +void _kcl_drm_syncobj_add_point(struct drm_syncobj *syncobj, + struct dma_fence_chain *chain, + struct dma_fence *fence, + uint64_t point) +{ + struct syncobj_wait_entry *wait_cur, *wait_tmp; + struct dma_fence *prev; + + dma_fence_get(fence); + + spin_lock(&syncobj->lock); + + prev = drm_syncobj_fence_get(syncobj); + /* You are adding an unorder point to timeline, which could cause payload returned from query_ioctl is 0! */ + if (prev && prev->seqno >= point) + DRM_DEBUG("You are adding an unorder point to timeline!\n"); + dma_fence_chain_init(chain, prev, fence, point); + rcu_assign_pointer(syncobj->fence, &chain->base); + + list_for_each_entry_safe(wait_cur, wait_tmp, &syncobj->cb_list, node) + _kcl_syncobj_wait_syncobj_func(syncobj, wait_cur); + + spin_unlock(&syncobj->lock); + + /* Walk the chain once to trigger garbage collection */ + dma_fence_chain_for_each(fence, prev); + dma_fence_put(prev); +} +EXPORT_SYMBOL(_kcl_drm_syncobj_add_point); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index da6ed263f834c..7db22c4883ecb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -125,4 +125,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 79c359a6bf60e..491b7832280ff 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -645,6 +645,12 @@ /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 +/* Has function drm_suballoc_manager_init() */ +#define HAVE_DRM_SUBALLOC_MANAGER_INIT 1 + +/* drm_syncobj_add_point() is available */ +#define HAVE_DRM_SYNCOBJ_ADD_POINT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 new file mode 100644 index 0000000000000..af363349cc643 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.0-1332-g44f8a1396e83 +dnl # drm/syncobj: add new drm_syncobj_add_point interface v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_syncobj_add_point(NULL, NULL, NULL, 0); + ],[drm_syncobj_add_point], [drivers/gpu/drm/drm_syncobj.c], [ + AC_DEFINE(HAVE_DRM_SYNCOBJ_ADD_POINT, 1, + [drm_syncobj_add_point() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0c86ea767eb2f..43a589a83fd32 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -230,7 +230,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE AC_AMDGPU_DRM_CLIENT - + AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/include/kcl/kcl_drm_syncobj.h b/include/kcl/kcl_drm_syncobj.h new file mode 100644 index 0000000000000..9323b1a4f5387 --- /dev/null +++ b/include/kcl/kcl_drm_syncobj.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef AMDKCL_DRM_SYNCOBJ_H +#define AMDKCL_DRM_SYNCOBJ_H + +#include +#include +#include + +#ifndef HAVE_DRM_SYNCOBJ_ADD_POINT +void _kcl_drm_syncobj_add_point(struct drm_syncobj *syncobj, + struct dma_fence_chain *chain, + struct dma_fence *fence, + uint64_t point); + +#define drm_syncobj_add_point _kcl_drm_syncobj_add_point +#endif + +#endif From b083e3fb719066b44bdc07b3129e9f837b1fd2c0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 11 Nov 2024 14:53:41 +0800 Subject: [PATCH 1359/2070] drm/amdkcl: fix the missing dam-fence-unwrap.h It's caused by following commit:d6c9f947 "drm/amdgpu: Add wait IOCTL timeline syncobj support" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/dma-fence-unwrap.h | 9 +++++++++ 3 files changed, 17 insertions(+) create mode 100644 include/kcl/header/linux/dma-fence-unwrap.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 491b7832280ff..148515957f25f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -807,6 +807,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_UNWRAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_MAP_OPS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 4df530c27442c..e3f0b8cd28802 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -139,4 +139,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #include/linux/units.h: add helpers for kelvin to/from Celsius conversion dnl AC_KERNEL_CHECK_HEADERS([linux/units.h]) + + dnl #v5.17-rc6-1496-g64a8f92fd783 + dnl #dma-buf: add dma_fence_unwrap v2 + dnl + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-unwrap.h]) ]) diff --git a/include/kcl/header/linux/dma-fence-unwrap.h b/include/kcl/header/linux/dma-fence-unwrap.h new file mode 100644 index 0000000000000..4564e22d18fb8 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-unwrap.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_UNWRAP_H_H +#define _KCL_HEADER__LINUX_DMA_FENCE_UNWRAP_H_H + +#ifdef HAVE_LINUX_DMA_FENCE_UNWRAP_H +#include_next +#endif + +#endif \ No newline at end of file From fb7cbb079f409b93c1048d117a505291660b17e6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 25 Mar 2025 11:50:35 +0800 Subject: [PATCH 1360/2070] drm/amdkcl: fake drm_client_dev_{resume/suspend} It's caused by v6.12-rc2-587-gbf17766f1083 drm/client: Move suspend/resume into DRM client callbacks Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_client_event.c | 16 ++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_client_event.h | 9 ++++++++ include/kcl/kcl_drm_client_event.h | 12 +++++++++++ 7 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c create mode 100644 include/kcl/header/drm/drm_client_event.h create mode 100644 include/kcl/kcl_drm_client_event.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a6d429412554b..4a37a7ba6e08e 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c new file mode 100644 index 0000000000000..f49f9e059e17b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c @@ -0,0 +1,16 @@ +#include + +#ifndef HAVE_DRM_CLIENT_DEV_RESUME +void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock) +{ + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, holds_console_lock); +} +EXPORT_SYMBOL(drm_client_dev_resume); + +void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock) +{ + bool suspend = !holds_console_lock; + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, suspend); +} +EXPORT_SYMBOL(drm_client_dev_suspend); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7db22c4883ecb..8691cd4c83e35 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -126,4 +126,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 index 689086c18718e..2c58adc325572 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -20,6 +20,27 @@ AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ ]) ]) +dnl # +dnl # commit v6.12-rc2-587-gbf17766f1083 +dnl # drm/client: Move suspend/resume into DRM client callbacks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_DEV_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_client_dev_resume(NULL, false); + ], [ + AC_DEFINE(HAVE_DRM_CLIENT_DEV_RESUME, 1, + [drm_client_dev_resume() is available]) + ]) + ]) +]) + + + AC_DEFUN([AC_AMDGPU_DRM_CLIENT], [ AC_AMDGPU_DRM_CLIENT_SETUP + AC_AMDGPU_DRM_CLIENT_DEV_RESUME ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 1ec4bd7b9aabd..4b96e46ae974b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -128,4 +128,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/client: Move public client header to clients/ subdirectory dnl # AC_KERNEL_CHECK_HEADERS([drm/clients/drm_client_setup.h]) + + dnl # + dnl # v6.12-rc2-586-gdf7e8b522a60 + dnl # drm/client: Move client event handlers to drm_client_event.c + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_client_event.h]) ]) diff --git a/include/kcl/header/drm/drm_client_event.h b/include/kcl/header/drm/drm_client_event.h new file mode 100644 index 0000000000000..84269dac95e6a --- /dev/null +++ b/include/kcl/header/drm/drm_client_event.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_CLIENT_EVENT_H +#define _KCL_HEADER_DRM_DRM_CLIENT_EVENT_H + +#ifdef HAVE_DRM_DRM_CLIENT_EVENT_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_client_event.h b/include/kcl/kcl_drm_client_event.h new file mode 100644 index 0000000000000..52f3342a5e573 --- /dev/null +++ b/include/kcl/kcl_drm_client_event.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_CLIENT_EVENT_H +#define KCL_KCL_DRM_CLIENT_EVENT_H + +#include + +#ifndef HAVE_DRM_CLIENT_DEV_RESUME +void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock); +void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock); +#endif + +#endif From cb880e02fd54670a73ec8f3e23f10c1348918b6c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Nov 2024 12:58:09 +0800 Subject: [PATCH 1361/2070] drm/amdkcl: fake aperture_remove_conflicting_pci_devices It's caused by 5.19-rc2-317-g7283f862bd99 drm: Implement DRM aperture helpers under video/ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + ...ure-remove-conflicting-pci-framebuffers.m4 | 22 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++++ include/kcl/backport/kcl_linux_aperture.h | 25 +++++++++++++++++++ include/kcl/header/linux/aperture.h | 10 ++++++++ 7 files changed, 65 insertions(+), 2 deletions(-) create mode 100644 include/kcl/backport/kcl_linux_aperture.h create mode 100644 include/kcl/header/linux/aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index 91f2508079ff1..a5c85881e336b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_DRM_APERTURE_H +#if !defined(HAVE_DRM_DRM_APERTURE_H) && !defined(HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES) #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8691cd4c83e35..7f724d30266fe 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -127,4 +127,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 index 50cfd872b53b3..0f644628eb68c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -16,3 +16,25 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ ]) ]) ]) + +dnl # +dnl # v5.19-rc2-317-g7283f862bd99 +dnl # drm: Implement DRM aperture helpers under video/ +dnl # +AC_DEFUN([AC_AMDGPU_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + aperture_remove_conflicting_pci_devices(NULL, NULL); + ], [ + AC_DEFINE(HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES, 1, + [aperture_remove_conflicting_pci_device() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 43a589a83fd32..a327d6e26540f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -144,7 +144,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG - AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_DRM_APERTURE AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index e3f0b8cd28802..661896d6ee4c2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -144,4 +144,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #dma-buf: add dma_fence_unwrap v2 dnl AC_KERNEL_CHECK_HEADERS([linux/dma-fence-unwrap.h]) + + dnl #5.19-rc2-317-g7283f862bd99 + dnl #drm: Implement DRM aperture helpers under video/ + dnl + AC_KERNEL_CHECK_HEADERS([linux/aperture.h]) ]) diff --git a/include/kcl/backport/kcl_linux_aperture.h b/include/kcl/backport/kcl_linux_aperture.h new file mode 100644 index 0000000000000..3aca24db4e3d2 --- /dev/null +++ b/include/kcl/backport/kcl_linux_aperture.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef _KCL_BACKPORT_KCL_LINUX_APERTURE_H_ +#define _KCL_BACKPORT_KCL_LINUX_APERTURE_H_ + +#include + +struct pci_dev; + +#ifndef HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES +#include +static inline int _kcl_aperture_remove_conflicting_pci_devices(struct pci_dev *pdev, const char *name) +{ +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + char *nonconst_name = (char *)name; + struct drm_driver *drm_driver = container_of(&nonconst_name, struct drm_driver, name); + return drm_aperture_remove_conflicting_pci_framebuffers(pdev, drm_driver); +#else + return drm_aperture_remove_conflicting_pci_framebuffers(pdev, name); +#endif +} +#define aperture_remove_conflicting_pci_devices _kcl_aperture_remove_conflicting_pci_devices +#endif + +#endif /* _KCL_BACKPORT_KCL_LINUX_APERTURE_H_ */ diff --git a/include/kcl/header/linux/aperture.h b/include/kcl/header/linux/aperture.h new file mode 100644 index 0000000000000..358ef946ab28e --- /dev/null +++ b/include/kcl/header/linux/aperture.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_APERTURE_H +#define _KCL_HEADER_LINUX_APERTURE_H + +#ifdef HAVE_LINUX_APERTURE_H +#include_next +#endif + +#endif + From 460a7e690b00326f10879788b3f9381777b02113 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 30 Oct 2024 17:33:56 -0400 Subject: [PATCH 1362/2070] drm/amdkfd: fix hw stall issue When register RLC_SPM_PERFMON_CNTL/PERFMON_RING_MODE is set to 0x11,SPM HW fires warning interrupt when rptr reaches RLC_SPM_SEGMENT_THRESHOLD, and stalls when rptr reaches the end of ring buffer. But the HW bug causes that both stall and interrupt arise when rptr reaches RLC_SPM_SEGMENT_THRESHOLD, and this means unexpecetd data loss with early SPM HW stall arise when interrupt received. this fix uses polling mode instead to avoid expected SPM HW early stall. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 86 +++++++++++++++++++++++++- 5 files changed, 87 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 88d85a8e6089f..48f28eac78306 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7865,7 +7865,7 @@ static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0x1); gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 1dbc8ddc31977..9796777113a50 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5336,7 +5336,7 @@ static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, mmRLC_SPM_PERFMON_RING_SIZE, size); gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, - mmRLC_SPM_SEGMENT_THRESHOLD, 0xff); + mmRLC_SPM_SEGMENT_THRESHOLD, 0x1); gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index c9664f3573aab..b6bcefc251519 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4870,7 +4870,7 @@ static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gp gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0x1); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4b9dd30008f1c..d928793811f0f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -355,6 +355,7 @@ struct kfd_node { /*spm process id */ unsigned int spm_pasid; + struct task_struct *spm_monitor_thread; /* Maximum process number mapped to HW scheduler */ unsigned int max_proc_per_quantum; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index d6a03240f36af..46d05c834ce76 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -48,11 +48,79 @@ struct kfd_spm_cntr { bool has_user_buf; bool is_user_buf_filled; bool is_spm_started; + u32 warned_ring_rptr; }; /* used to detect SPM overflow */ #define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD +static int kfd_spm_monitor_thread(void *param) +{ + struct kfd_process_device *pdd = param; + struct kfd_node *node = pdd->dev; + + allow_signal(SIGKILL); + while (!kthread_should_stop() && + !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { + struct kfd_spm_cntr *spm = pdd->spm_cntr; + bool need_schedule = false; + + usleep_range(1, 11); + + if (!mutex_trylock(&pdd->spm_cntr->spm_worker_mutex)) + continue; + + if (spm->is_spm_started) { + u32 warned_ring_rptr; + u32 ring_size; + u32 ring_rptr; + u32 ring_wptr; + + ring_size = spm->ring_size; + ring_rptr = spm->ring_rptr; + warned_ring_rptr = spm->warned_ring_rptr; + ring_wptr = READ_ONCE(spm->cpu_addr[0]); + + if (need_schedule || (ring_rptr != warned_ring_rptr && + (ring_size + ring_wptr - ring_rptr) % ring_size > + (ring_size >> 1))) { + spm->warned_ring_rptr = ring_rptr; + if (!need_schedule) { + dev_dbg(node->adev->dev, + "SPM soft interrupt rptr:0x%08x--wptr:0x%08x", + ring_rptr, ring_wptr); + need_schedule = true; + } + } + } + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + if (need_schedule) + schedule_work(&pdd->spm_work); + } + node->spm_monitor_thread = NULL; + return 0; +} + +static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) +{ + struct kfd_node *node = pdd->dev; + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "spm_%d", node->adev->ddev.render->index); + node->spm_monitor_thread = + kthread_run(kfd_spm_monitor_thread, pdd, thread_name); + + if (IS_ERR(node->spm_monitor_thread)) { + ret = PTR_ERR(node->spm_monitor_thread); + node->spm_monitor_thread = NULL; + dev_dbg(node->adev->dev, "Failed to create spm monitor thread %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) { uint64_t *overflow_ptr, *overflow_end_ptr; @@ -137,6 +205,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (spm->ring_rptr == ring_wptr) goto exit; + spm->warned_ring_rptr = spm->ring_rptr; if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -258,6 +327,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device spin_lock_init(&pdd->spm_irq_lock); kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + pdd->spm_cntr->warned_ring_rptr = ~0; + pdd->dev->spm_monitor_thread = NULL; goto out; @@ -283,6 +354,9 @@ int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) return -EINVAL; } + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); pdd->spm_cntr->is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -413,7 +487,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev * Adjust rptr accordingly */ spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (!pdd->dev->spm_monitor_thread) + kfd_spm_monitor_thread_start(pdd); } else { /* If SPM was already started, there may already * be data in the ring-buffer that needs to be read. @@ -428,7 +505,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev * Adjust rptr accordingly */ spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); } mutex_unlock(&pdd->spm_mutex); @@ -480,7 +560,7 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) unsigned long flags; if (!p) { - pr_debug("kfd_spm_interrupt p = %p\n", p); + dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); return; /* Presumably process exited. */ } @@ -489,11 +569,11 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) return; spin_lock_irqsave(&pdd->spm_irq_lock, flags); - if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) - schedule_work(&pdd->spm_work); + pdd->spm_cntr->has_data_loss = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + dev_dbg(dev->adev->dev, "SPM ring buffer stall."); kfd_unref_process(p); } From d1d6600b3958056939839715ae859b39e2d5a6d4 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 30 Oct 2024 17:37:04 -0400 Subject: [PATCH 1363/2070] drm/amdkfd: adding spm ring buffer overflow message to provide user space more information. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 46d05c834ce76..cdf38ad27100e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -220,6 +220,9 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (*overflow_ptr == SPM_OVERFLOW_MAGIC) break; } + if (overflow_size) + dev_dbg(pdd->dev->adev->dev, + "SPM ring buffer overflow size 0x%x", overflow_size); /* move overflow counters into ring buffer to avoid data loss */ memcpy(ring_start, ring_end, overflow_size); From 897cf13740d62de2cccbb9408e024bd0cb8ae7a5 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 9 Oct 2024 16:48:43 -0400 Subject: [PATCH 1364/2070] drm/amdkfd: add spm buffer header to send data back to user. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- include/uapi/linux/kfd_ioctl.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 7b03f3ffaac6b..f3b0590c91f61 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -621,9 +621,8 @@ enum kfd_ioctl_spm_op { * @buf_size[in]: size of the destination buffer * @timeout[in/out]: [in]: timeout in milliseconds, [out]: amount of time left * `in the timeout window - * @bytes_copied[out]: amount of data that was copied to the previous dest_buf - * @has_data_loss: boolean indicating whether data was lost - * (e.g. due to a ring-buffer overflow) + * @bytes_copied[out]: total amount of data that was copied to the previous dest_buf + * @has_data_loss: total count for sub-block which has data loss * * This ioctl performs different functions depending on the @op parameter. * @@ -673,6 +672,21 @@ struct kfd_ioctl_spm_args { __u32 has_data_loss; }; +/** + * kfd_ioctl_spm_buffer_header - SPM Buffer header for kfd_ioctl_spm_args->dest_buf + * + * @version [out]: spm versiom + * @bytes_copied [out]: amount of data for each sub-block + * @has_data_loss: [out]: boolean indicating whether data was lost for each sub-block + * (e.g. due to a ring-buffer overflow) + */ +struct kfd_ioctl_spm_buffer_header { + __u32 version; /* 0-23: minor 24-31: major */ + __u32 bytes_copied; + __u32 has_data_loss; + __u32 reserved[5]; +}; + /* * SVM event tracing via SMI system management interface * From 11d1f6645db15c8591fc090c29be32937fcf5205 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 10 Oct 2024 15:42:16 -0400 Subject: [PATCH 1365/2070] drm/amdkfd: implement spm buffer header on existing ASIC. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 61 ++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index cdf38ad27100e..504f3f16eeedb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -29,6 +29,15 @@ #include // for use_mm() #include +/* + * SPM revision change log + * + * 0.1 - Initial revision + * 0.2 - add kfd_ioctl_spm_buffer_header + */ +#define KFD_IOCTL_SPM_MAJOR_VERSION 0 +#define KFD_IOCTL_SPM_MINOR_VERSION 2 + struct user_buf { uint64_t __user *user_addr; u32 ubufsize; @@ -379,25 +388,52 @@ int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) return 0; } -static void spm_update_dest_info(struct kfd_process_device *pdd, +static int spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { struct kfd_spm_cntr *spm = pdd->spm_cntr; + int ret = 0; + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); if (spm->has_user_buf) { - user_spm_data->bytes_copied = spm->size_copied; - user_spm_data->has_data_loss = spm->has_data_loss; + struct kfd_ioctl_spm_buffer_header spm_header; + uint64_t __user *user_address; + + user_spm_data->bytes_copied += spm->size_copied; + user_spm_data->has_data_loss += spm->has_data_loss; + + memset(&spm_header, 0, sizeof(spm_header)); + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr - sizeof(spm_header)); + spm_header.version = KFD_IOCTL_SPM_MAJOR_VERSION << 24 | + KFD_IOCTL_SPM_MINOR_VERSION; + spm_header.bytes_copied = spm->size_copied; + spm_header.has_data_loss = spm->has_data_loss; spm->has_user_buf = false; + + ret = copy_to_user(user_address, &spm_header, sizeof(spm_header)); + if (ret) { + ret = -EFAULT; + goto out; + } } if (user_spm_data->dest_buf) { + user_spm_data->bytes_copied = 0; + user_spm_data->has_data_loss = 0; + spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; spm->ubuf.ubufsize = user_spm_data->buf_size; + /* reserve space for kfd_ioctl_spm_buffer_header */ + spm->ubuf.user_addr = (uint64_t *)((uint64_t)spm->ubuf.user_addr + + sizeof(struct kfd_ioctl_spm_buffer_header)); + spm->ubuf.ubufsize -= sizeof(struct kfd_ioctl_spm_buffer_header); spm->has_data_loss = false; spm->size_copied = 0; spm->is_user_buf_filled = false; spm->has_user_buf = true; } +out: mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + return ret; } static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, @@ -441,6 +477,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev struct kfd_ioctl_spm_args *user_spm_data; struct kfd_spm_cntr *spm; unsigned long flags; + u32 ubufsize; int ret = 0; user_spm_data = (struct kfd_ioctl_spm_args *) data; @@ -449,8 +486,14 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev spm = pdd->spm_cntr; if (spm == NULL) { - mutex_unlock(&pdd->spm_mutex); - return -EINVAL; + ret = -EINVAL; + goto out; + } + + ubufsize = user_spm_data->buf_size; + if (ubufsize <= sizeof(struct kfd_ioctl_spm_buffer_header)) { + ret = -EINVAL; + goto out; } if (user_spm_data->timeout && spm->has_user_buf && @@ -464,8 +507,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev ret = 0; } else if (ret) { /* handle other errors normally, including -ERESTARTSYS */ - mutex_unlock(&pdd->spm_mutex); - return ret; + goto out; } } else if (!user_spm_data->timeout && spm->has_user_buf) { /* Copy (partial) data to user buffer */ @@ -477,7 +519,9 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* Get info about filled space in previous output buffer. * Setup new dest buf if provided. */ - spm_update_dest_info(pdd, user_spm_data); + ret = spm_update_dest_info(pdd, user_spm_data); + if (ret) + goto out; } if (user_spm_data->dest_buf) { @@ -514,6 +558,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev kthread_stop(pdd->dev->spm_monitor_thread); } +out: mutex_unlock(&pdd->spm_mutex); return ret; From a9ece63d6f468e80f5415d9bcce1c2fd884bca7e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 10 Oct 2024 17:53:04 -0400 Subject: [PATCH 1366/2070] drm/amdkfd: refactor kfd spm for later adding multiple xcc support Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 192 +++++++++++++++-------- 3 files changed, 132 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index d928793811f0f..36f113a7ea30d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1702,7 +1702,7 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, bool kfd_is_locked(struct kfd_dev *kfd); void kfd_spm_init_process_device(struct kfd_process_device *pdd); -int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +void kfd_spm_release_process_device(struct kfd_process_device *pdd); int kfd_rlc_spm(struct kfd_process *p, void __user *data); /* PeerDirect support */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index dbb44e52f395b..b4b93e72f2be7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1112,7 +1112,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->dev->id, p->lead_thread->pid); kfd_pc_sample_release(pdd); - kfd_release_spm(pdd, pdd->dev->adev); + kfd_spm_release_process_device(pdd); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 504f3f16eeedb..da935d318e426 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -43,9 +43,8 @@ struct user_buf { u32 ubufsize; }; -struct kfd_spm_cntr { +struct kfd_spm_base { struct user_buf ubuf; - struct mutex spm_worker_mutex; u64 gpu_addr; u32 ring_size; u32 ring_rptr; @@ -53,16 +52,26 @@ struct kfd_spm_cntr { u32 has_data_loss; u32 *cpu_addr; void *spm_obj; - wait_queue_head_t spm_buf_wq; bool has_user_buf; bool is_user_buf_filled; bool is_spm_started; u32 warned_ring_rptr; }; +struct kfd_spm_cntr { + struct kfd_spm_base spm; + struct mutex spm_worker_mutex; + wait_queue_head_t spm_buf_wq; + u32 have_users_buf_cnt; + bool are_users_buf_filled; +}; + /* used to detect SPM overflow */ #define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); + static int kfd_spm_monitor_thread(void *param) { struct kfd_process_device *pdd = param; @@ -71,7 +80,7 @@ static int kfd_spm_monitor_thread(void *param) allow_signal(SIGKILL); while (!kthread_should_stop() && !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); bool need_schedule = false; usleep_range(1, 11); @@ -132,10 +141,11 @@ static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); uint64_t *overflow_ptr, *overflow_end_ptr; - overflow_ptr = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr - + pdd->spm_cntr->ring_size + 0x20); + overflow_ptr = (uint64_t *)((uint64_t)spm->cpu_addr + + spm->ring_size + 0x20); overflow_end_ptr = overflow_ptr + (size >> 3); /* SPM data filling is 0x20 alignment */ for ( ; overflow_ptr < overflow_end_ptr; overflow_ptr += 4) @@ -144,7 +154,7 @@ static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); uint64_t __user *user_address; uint64_t *ring_buf; u32 user_buf_space_left; @@ -179,7 +189,8 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) spm->size_copied = spm->ubuf.ubufsize; spm->ring_rptr += user_buf_space_left; - WRITE_ONCE(spm->is_user_buf_filled, true); + spm->is_user_buf_filled = true; + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); wake_up(&pdd->spm_cntr->spm_buf_wq); } @@ -188,7 +199,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); u32 overflow_size = 0; u32 size_to_copy; int ret = 0; @@ -208,6 +219,8 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) */ if (!spm->is_user_buf_filled) spm->is_user_buf_filled = true; + dev_dbg(pdd->dev->adev->dev, "[SPM] [%d|%d] rptr:0x%x--wptr:0x%x", + spm->has_user_buf, spm->is_user_buf_filled, spm->ring_rptr, ring_wptr); goto exit; } @@ -221,8 +234,8 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } else { uint64_t *ring_start, *ring_end; - ring_start = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + 0x20); - ring_end = ring_start + (pdd->spm_cntr->ring_size >> 3); + ring_start = (uint64_t *)((uint64_t)spm->cpu_addr + 0x20); + ring_end = ring_start + (spm->ring_size >> 3); for ( ; overflow_size < pdd->spm_overflow_reserved; overflow_size += 0x20) { uint64_t *overflow_ptr = ring_end + (overflow_size >> 3); @@ -268,7 +281,9 @@ static void kfd_spm_work(struct work_struct *work) kthread_use_mm(mm); { /* attach mm */ mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, false); kfd_spm_read_ring_buffer(pdd); + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } /* detach mm */ kthread_unuse_mm(mm); @@ -287,67 +302,90 @@ void kfd_spm_init_process_device(struct kfd_process_device *pdd) pdd->spm_cntr = NULL; } -static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +void kfd_spm_release_process_device(struct kfd_process_device *pdd) { - int ret = 0; + struct amdgpu_device *adev = pdd->dev->adev; - mutex_lock(&pdd->spm_mutex); - - if (pdd->spm_cntr) { - mutex_unlock(&pdd->spm_mutex); - return -EINVAL; - } + kfd_release_spm(pdd, adev); + mutex_destroy(&pdd->spm_mutex); +} - pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); - if (!pdd->spm_cntr) { - mutex_unlock(&pdd->spm_mutex); - return -ENOMEM; - } +static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + int ret = 0; - /* git spm ring buffer 4M */ - pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); - pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4; - pdd->spm_cntr->has_user_buf = false; + /* allocate 4M spm ring buffer */ + spm->ring_size = order_base_2(4 * 1024 * 1024/4); + spm->ring_size = (1 << spm->ring_size) * 4; ret = amdgpu_amdkfd_alloc_gtt_mem(adev, - pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, - &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, + spm->ring_size, &spm->spm_obj, + &spm->gpu_addr, (void *)&spm->cpu_addr, false, false); if (ret) - goto alloc_gtt_mem_failure; + goto out; /* reserve space to fix spm overflow */ - pdd->spm_cntr->ring_size -= pdd->spm_overflow_reserved; + spm->ring_size -= pdd->spm_overflow_reserved; ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), - pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); + spm->gpu_addr, spm->ring_size); /* * By definition, the last 8 DWs of the buffer are not part of the rings * and are instead part of the Meta data area. */ - pdd->spm_cntr->ring_size -= 0x20; + spm->ring_size -= 0x20; + if (ret) + goto rlc_spm_acquire_failure; + + kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + spm->warned_ring_rptr = ~0; + goto out; + +rlc_spm_acquire_failure: + amdgpu_amdkfd_free_gtt_mem(adev, &spm->spm_obj); + memset(spm, 0, sizeof(*spm)); +out: + return ret; +} + +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + int ret = 0; + + mutex_lock(&pdd->spm_mutex); + + if (pdd->spm_cntr) { + ret = -EBUSY; + goto out; + } + + pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); + if (!pdd->spm_cntr) { + ret = -ENOMEM; + goto out; + } + + ret = _kfd_acquire_spm(pdd, adev); if (ret) goto acquire_spm_failure; + pdd->spm_cntr->have_users_buf_cnt = 0; mutex_init(&pdd->spm_cntr->spm_worker_mutex); init_waitqueue_head(&pdd->spm_cntr->spm_buf_wq); INIT_WORK(&pdd->spm_work, kfd_spm_work); spin_lock_init(&pdd->spm_irq_lock); - - kfd_spm_preset(pdd, pdd->spm_overflow_reserved); - pdd->spm_cntr->warned_ring_rptr = ~0; pdd->dev->spm_monitor_thread = NULL; goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); - -alloc_gtt_mem_failure: + _kfd_release_spm(pdd, adev); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; @@ -356,42 +394,61 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + unsigned long flags; + + if (!spm->ring_size) + return; + amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); + amdgpu_amdkfd_free_gtt_mem(adev, &(spm->spm_obj)); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + memset(spm, 0, sizeof(*spm)); + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + +} + +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; + int ret = 0; mutex_lock(&pdd->spm_mutex); if (!pdd->spm_cntr) { - mutex_unlock(&pdd->spm_mutex); - return -EINVAL; + ret = -EINVAL; + goto out; } if (pdd->dev->spm_monitor_thread) kthread_stop(pdd->dev->spm_monitor_thread); spin_lock_irqsave(&pdd->spm_irq_lock, flags); - pdd->spm_cntr->is_spm_started = false; + pdd->spm_cntr->spm.is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0); flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); - amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); + _kfd_release_spm(pdd, adev); spin_lock_irqsave(&pdd->spm_irq_lock, flags); + mutex_destroy(&(pdd->spm_cntr->spm_worker_mutex)); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); +out: mutex_unlock(&pdd->spm_mutex); - return 0; + return ret; } static int spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); int ret = 0; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); @@ -409,6 +466,7 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, spm_header.bytes_copied = spm->size_copied; spm_header.has_data_loss = spm->has_data_loss; spm->has_user_buf = false; + pdd->spm_cntr->have_users_buf_cnt--; ret = copy_to_user(user_address, &spm_header, sizeof(spm_header)); if (ret) { @@ -430,13 +488,15 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, spm->size_copied = 0; spm->is_user_buf_filled = false; spm->has_user_buf = true; + pdd->spm_cntr->are_users_buf_filled = false; + pdd->spm_cntr->have_users_buf_cnt++; } out: mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); return ret; } -static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, +static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm_cntr, struct kfd_ioctl_spm_args *user_spm_data) { int ret = 0; @@ -444,8 +504,8 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, long timeout = msecs_to_jiffies(user_spm_data->timeout); long start_jiffies = jiffies; - ret = wait_event_interruptible_timeout(spm->spm_buf_wq, - (READ_ONCE(spm->is_user_buf_filled) == true), + ret = wait_event_interruptible_timeout(spm_cntr->spm_buf_wq, + (READ_ONCE(spm_cntr->are_users_buf_filled) == true), timeout); switch (ret) { @@ -475,17 +535,19 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { struct kfd_ioctl_spm_args *user_spm_data; - struct kfd_spm_cntr *spm; + struct kfd_spm_cntr *spm_cntr; + struct kfd_spm_base *spm; + bool need_schedule = false; unsigned long flags; u32 ubufsize; int ret = 0; user_spm_data = (struct kfd_ioctl_spm_args *) data; + dev_dbg(pdd->dev->adev->dev, "SPM start to set new destination buffer."); mutex_lock(&pdd->spm_mutex); - spm = pdd->spm_cntr; - - if (spm == NULL) { + spm_cntr = pdd->spm_cntr; + if (spm_cntr == NULL) { ret = -EINVAL; goto out; } @@ -496,9 +558,11 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev goto out; } - if (user_spm_data->timeout && spm->has_user_buf && - !READ_ONCE(spm->is_user_buf_filled)) { - ret = spm_wait_for_fill_awake(spm, user_spm_data); + if (user_spm_data->timeout && spm_cntr->have_users_buf_cnt && + !READ_ONCE(spm_cntr->are_users_buf_filled)) { + dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", + user_spm_data->timeout); + ret = spm_wait_for_fill_awake(spm_cntr, user_spm_data); if (ret == -ETIME) { /* Copy (partial) data to user buffer after a timeout */ schedule_work(&pdd->spm_work); @@ -509,12 +573,13 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* handle other errors normally, including -ERESTARTSYS */ goto out; } - } else if (!user_spm_data->timeout && spm->has_user_buf) { + } else if (!user_spm_data->timeout && spm_cntr->have_users_buf_cnt) { /* Copy (partial) data to user buffer */ schedule_work(&pdd->spm_work); flush_work(&pdd->spm_work); } + spm = &(spm_cntr->spm); if (spm->has_user_buf || user_spm_data->dest_buf) { /* Get info about filled space in previous output buffer. * Setup new dest buf if provided. @@ -542,7 +607,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* If SPM was already started, there may already * be data in the ring-buffer that needs to be read. */ - schedule_work(&pdd->spm_work); + need_schedule = true; } } else { amdgpu_amdkfd_rlc_spm_cntl(adev, 0); @@ -560,7 +625,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev out: mutex_unlock(&pdd->spm_mutex); + if (need_schedule) + schedule_work(&pdd->spm_work); + dev_dbg(pdd->dev->adev->dev, "SPM finish to set new destination buffer, ret = %d.", ret); return ret; } @@ -617,8 +685,8 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) return; spin_lock_irqsave(&pdd->spm_irq_lock, flags); - if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) - pdd->spm_cntr->has_data_loss = true; + if (pdd->spm_cntr && pdd->spm_cntr->spm.is_spm_started) + pdd->spm_cntr->spm.has_data_loss = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); dev_dbg(dev->adev->dev, "SPM ring buffer stall."); From fb9f40c95f07de5e9bcca93a97c3133b501a39ca Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 11 Oct 2024 21:11:21 -0400 Subject: [PATCH 1367/2070] drm/amdkfd: add general multiple xcc support on current kfd SPM. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 216 ++++++++++++++++----------- 1 file changed, 126 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index da935d318e426..87adcaa415738 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -34,9 +34,10 @@ * * 0.1 - Initial revision * 0.2 - add kfd_ioctl_spm_buffer_header + * 0.3 - add multiple XCC support */ #define KFD_IOCTL_SPM_MAJOR_VERSION 0 -#define KFD_IOCTL_SPM_MINOR_VERSION 2 +#define KFD_IOCTL_SPM_MINOR_VERSION 3 struct user_buf { uint64_t __user *user_addr; @@ -59,7 +60,8 @@ struct kfd_spm_base { }; struct kfd_spm_cntr { - struct kfd_spm_base spm; + struct kfd_spm_base spm[MAX_XCP]; + int spm_use_cnt; struct mutex spm_worker_mutex; wait_queue_head_t spm_buf_wq; u32 have_users_buf_cnt; @@ -70,7 +72,7 @@ struct kfd_spm_cntr { #define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); -static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev); static int kfd_spm_monitor_thread(void *param) { @@ -80,20 +82,24 @@ static int kfd_spm_monitor_thread(void *param) allow_signal(SIGKILL); while (!kthread_should_stop() && !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); bool need_schedule = false; + u32 inst; usleep_range(1, 11); if (!mutex_trylock(&pdd->spm_cntr->spm_worker_mutex)) continue; - if (spm->is_spm_started) { + for_each_inst(inst, node->xcc_mask) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); u32 warned_ring_rptr; u32 ring_size; u32 ring_rptr; u32 ring_wptr; + if (!spm->is_spm_started) + continue; + ring_size = spm->ring_size; ring_rptr = spm->ring_rptr; warned_ring_rptr = spm->warned_ring_rptr; @@ -105,8 +111,8 @@ static int kfd_spm_monitor_thread(void *param) spm->warned_ring_rptr = ring_rptr; if (!need_schedule) { dev_dbg(node->adev->dev, - "SPM soft interrupt rptr:0x%08x--wptr:0x%08x", - ring_rptr, ring_wptr); + "[SPM#%d] soft interrupt rptr:0x%08x--wptr:0x%08x", + inst, ring_rptr, ring_wptr); need_schedule = true; } } @@ -139,9 +145,8 @@ static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) return ret; } -static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) +static void kfd_spm_preset(struct kfd_spm_base *spm, u32 size) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); uint64_t *overflow_ptr, *overflow_end_ptr; overflow_ptr = (uint64_t *)((uint64_t)spm->cpu_addr @@ -152,9 +157,9 @@ static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) *overflow_ptr = SPM_OVERFLOW_MAGIC; } -static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) +static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy, int inst) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); uint64_t __user *user_address; uint64_t *ring_buf; u32 user_buf_space_left; @@ -190,16 +195,14 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) spm->size_copied = spm->ubuf.ubufsize; spm->ring_rptr += user_buf_space_left; spm->is_user_buf_filled = true; - WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); - wake_up(&pdd->spm_cntr->spm_buf_wq); } return ret; } -static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) +static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd, int inst) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); u32 overflow_size = 0; u32 size_to_copy; int ret = 0; @@ -219,7 +222,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) */ if (!spm->is_user_buf_filled) spm->is_user_buf_filled = true; - dev_dbg(pdd->dev->adev->dev, "[SPM] [%d|%d] rptr:0x%x--wptr:0x%x", + dev_dbg(pdd->dev->adev->dev, "[SPM#%d] [%d|%d] rptr:0x%x--wptr:0x%x", inst, spm->has_user_buf, spm->is_user_buf_filled, spm->ring_rptr, ring_wptr); goto exit; } @@ -230,7 +233,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->warned_ring_rptr = spm->ring_rptr; if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; - ret = kfd_spm_data_copy(pdd, size_to_copy); + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); } else { uint64_t *ring_start, *ring_end; @@ -249,7 +252,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) memcpy(ring_start, ring_end, overflow_size); size_to_copy = spm->ring_size - spm->ring_rptr; - ret = kfd_spm_data_copy(pdd, size_to_copy); + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); /* correct counter start point */ if (spm->ring_size == spm->ring_rptr) { @@ -261,13 +264,13 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->ring_rptr = 0; size_to_copy = ring_wptr - spm->ring_rptr; if (!ret) - ret = kfd_spm_data_copy(pdd, size_to_copy); + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); } } exit: - kfd_spm_preset(pdd, overflow_size); - amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); + kfd_spm_preset(spm, overflow_size); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, inst, spm->ring_rptr); return ret; } @@ -280,10 +283,21 @@ static void kfd_spm_work(struct work_struct *work) if (mm) { kthread_use_mm(mm); { /* attach mm */ + int inst; + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, false); - kfd_spm_read_ring_buffer(pdd); + for_each_inst(inst, pdd->dev->xcc_mask) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + kfd_spm_read_ring_buffer(pdd, inst); + if (spm->is_user_buf_filled) + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); + } + if (READ_ONCE(pdd->spm_cntr->are_users_buf_filled)) { + pr_debug("SPM wake up buffer work queue."); + wake_up(&pdd->spm_cntr->spm_buf_wq); + } mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } /* detach mm */ kthread_unuse_mm(mm); @@ -310,9 +324,9 @@ void kfd_spm_release_process_device(struct kfd_process_device *pdd) mutex_destroy(&pdd->spm_mutex); } -static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +static int _kfd_acquire_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); int ret = 0; /* allocate 4M spm ring buffer */ @@ -329,7 +343,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device /* reserve space to fix spm overflow */ spm->ring_size -= pdd->spm_overflow_reserved; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, inst, drm_priv_to_vm(pdd->drm_priv), spm->gpu_addr, spm->ring_size); /* @@ -341,7 +355,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto rlc_spm_acquire_failure; - kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + kfd_spm_preset(spm, pdd->spm_overflow_reserved); spm->warned_ring_rptr = ~0; goto out; @@ -355,6 +369,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { int ret = 0; + int inst; mutex_lock(&pdd->spm_mutex); @@ -369,9 +384,12 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; } - ret = _kfd_acquire_spm(pdd, adev); - if (ret) - goto acquire_spm_failure; + for_each_inst(inst, pdd->dev->xcc_mask) { + ret = _kfd_acquire_spm(pdd, inst, adev); + if (ret) + goto acquire_spm_failure; + pdd->spm_cntr->spm_use_cnt++; + } pdd->spm_cntr->have_users_buf_cnt = 0; mutex_init(&pdd->spm_cntr->spm_worker_mutex); @@ -385,7 +403,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; acquire_spm_failure: - _kfd_release_spm(pdd, adev); + for_each_inst(inst, pdd->dev->xcc_mask) + _kfd_release_spm(pdd, inst, adev); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; @@ -394,25 +413,27 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); unsigned long flags; if (!spm->ring_size) return; - amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); + amdgpu_amdkfd_rlc_spm_release(adev, inst, drm_priv_to_vm(pdd->drm_priv)); amdgpu_amdkfd_free_gtt_mem(adev, &(spm->spm_obj)); spin_lock_irqsave(&pdd->spm_irq_lock, flags); memset(spm, 0, sizeof(*spm)); spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + --pdd->spm_cntr->spm_use_cnt; } static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; + int inst; int ret = 0; mutex_lock(&pdd->spm_mutex); @@ -424,15 +445,17 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device if (pdd->dev->spm_monitor_thread) kthread_stop(pdd->dev->spm_monitor_thread); - spin_lock_irqsave(&pdd->spm_irq_lock, flags); - pdd->spm_cntr->spm.is_spm_started = false; - spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - - amdgpu_amdkfd_rlc_spm_cntl(adev, 0); + for_each_inst(inst, pdd->dev->xcc_mask) { + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + pdd->spm_cntr->spm[inst].is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 0); + } flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - _kfd_release_spm(pdd, adev); + for_each_inst(inst, pdd->dev->xcc_mask) + _kfd_release_spm(pdd, inst, adev); spin_lock_irqsave(&pdd->spm_irq_lock, flags); mutex_destroy(&(pdd->spm_cntr->spm_worker_mutex)); @@ -446,9 +469,9 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device } static int spm_update_dest_info(struct kfd_process_device *pdd, - struct kfd_ioctl_spm_args *user_spm_data) + int inst, struct kfd_ioctl_spm_args *user_spm_data) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); int ret = 0; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); @@ -534,15 +557,13 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm_cntr, static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { - struct kfd_ioctl_spm_args *user_spm_data; + struct kfd_ioctl_spm_args user_spm_data, *user_spm_ptr; struct kfd_spm_cntr *spm_cntr; - struct kfd_spm_base *spm; bool need_schedule = false; unsigned long flags; u32 ubufsize; int ret = 0; - - user_spm_data = (struct kfd_ioctl_spm_args *) data; + int inst; dev_dbg(pdd->dev->adev->dev, "SPM start to set new destination buffer."); mutex_lock(&pdd->spm_mutex); @@ -552,17 +573,22 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev goto out; } - ubufsize = user_spm_data->buf_size; + user_spm_ptr = (struct kfd_ioctl_spm_args *) data; + ubufsize = user_spm_ptr->buf_size / spm_cntr->spm_use_cnt; + ubufsize = rounddown(ubufsize, 32); + if (ubufsize <= sizeof(struct kfd_ioctl_spm_buffer_header)) { ret = -EINVAL; goto out; } - if (user_spm_data->timeout && spm_cntr->have_users_buf_cnt && + memcpy(&user_spm_data, user_spm_ptr, sizeof(user_spm_data)); + user_spm_data.buf_size = ubufsize; + if (user_spm_data.timeout && spm_cntr->have_users_buf_cnt && !READ_ONCE(spm_cntr->are_users_buf_filled)) { dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", - user_spm_data->timeout); - ret = spm_wait_for_fill_awake(spm_cntr, user_spm_data); + user_spm_data.timeout); + ret = spm_wait_for_fill_awake(spm_cntr, &user_spm_data); if (ret == -ETIME) { /* Copy (partial) data to user buffer after a timeout */ schedule_work(&pdd->spm_work); @@ -573,54 +599,58 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* handle other errors normally, including -ERESTARTSYS */ goto out; } - } else if (!user_spm_data->timeout && spm_cntr->have_users_buf_cnt) { + } else if (!user_spm_data.timeout && spm_cntr->have_users_buf_cnt) { /* Copy (partial) data to user buffer */ schedule_work(&pdd->spm_work); flush_work(&pdd->spm_work); } - spm = &(spm_cntr->spm); - if (spm->has_user_buf || user_spm_data->dest_buf) { - /* Get info about filled space in previous output buffer. - * Setup new dest buf if provided. - */ - ret = spm_update_dest_info(pdd, user_spm_data); - if (ret) - goto out; - } + for_each_inst(inst, pdd->dev->xcc_mask) { + struct kfd_spm_base *spm = &(spm_cntr->spm[inst]); - if (user_spm_data->dest_buf) { - /* Start SPM if necessary*/ - if (spm->is_spm_started == false) { - amdgpu_amdkfd_rlc_spm_cntl(adev, 1); + if (spm->has_user_buf || user_spm_data.dest_buf) { + /* Get info about filled space in previous output buffer. + * Setup new dest buf if provided. + */ + ret = spm_update_dest_info(pdd, inst, &user_spm_data); + if (ret) + goto out; + } + + if (user_spm_data.dest_buf) { + /* Start SPM if necessary*/ + if (spm->is_spm_started == false) { + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 1); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = true; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and + * wptr will become 0, adjust rptr accordingly. + */ + spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (!pdd->dev->spm_monitor_thread) + kfd_spm_monitor_thread_start(pdd); + } else { + /* If SPM was already started, there may already + * be data in the ring-buffer that needs to be read. + */ + need_schedule = true; + } + user_spm_data.dest_buf += ubufsize; + } else { + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); - spm->is_spm_started = true; + spm->is_spm_started = false; /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. * Adjust rptr accordingly */ spm->ring_rptr = 0; spm->warned_ring_rptr = ~0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - if (!pdd->dev->spm_monitor_thread) - kfd_spm_monitor_thread_start(pdd); - } else { - /* If SPM was already started, there may already - * be data in the ring-buffer that needs to be read. - */ - need_schedule = true; + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); } - } else { - amdgpu_amdkfd_rlc_spm_cntl(adev, 0); - spin_lock_irqsave(&pdd->spm_irq_lock, flags); - spm->is_spm_started = false; - /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. - * Adjust rptr accordingly - */ - spm->ring_rptr = 0; - spm->warned_ring_rptr = ~0; - spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - if (pdd->dev->spm_monitor_thread) - kthread_stop(pdd->dev->spm_monitor_thread); } out: @@ -669,12 +699,18 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) { struct kfd_process_device *pdd; - struct kfd_node *dev = kfd->nodes[0]; - uint16_t pasid = dev->spm_pasid; - - struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + struct kfd_node *dev; + uint8_t xcp_id; + uint16_t pasid; + struct kfd_process *p; unsigned long flags; + xcp_id = kfd->adev->xcp_mgr ? + fls(amdgpu_xcp_get_partition(kfd->adev->xcp_mgr, AMDGPU_XCP_GFX, xcc_id)) - 1 : 0; + dev = kfd->nodes[xcp_id]; + pasid = dev->spm_pasid; + p = kfd_lookup_process_by_pasid(pasid); + if (!p) { dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); return; /* Presumably process exited. */ @@ -685,11 +721,11 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) return; spin_lock_irqsave(&pdd->spm_irq_lock, flags); - if (pdd->spm_cntr && pdd->spm_cntr->spm.is_spm_started) - pdd->spm_cntr->spm.has_data_loss = true; + if (pdd->spm_cntr && pdd->spm_cntr->spm[xcc_id].is_spm_started) + pdd->spm_cntr->spm[xcc_id].has_data_loss = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - dev_dbg(dev->adev->dev, "SPM ring buffer stall."); + dev_dbg(pdd->dev->adev->dev, "[SPM#%d:%d] ring buffer stall.", xcp_id, xcc_id); kfd_unref_process(p); } From 0390c1f594ddab9545213765988015a6094a8e34 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Oct 2024 00:08:27 -0400 Subject: [PATCH 1368/2070] drm/amdkfd: add multiple xcc support on gfx_v9_4_3. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 194 ++++++++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 3 +- 2 files changed, 185 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index ad4d442e7345e..7e6a01f457d75 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -169,6 +169,8 @@ static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); +static void gfx_v9_4_3_update_spm_vmid_internal(struct amdgpu_device *adev, + int xcc_id, unsigned int vmid); static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); @@ -1066,6 +1068,13 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) num_xcc = NUM_XCC(adev->gfx.xcc_mask); + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -1454,10 +1463,14 @@ static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) { - /* init spm vmid with 0xf */ - if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); + int i, num_xcc; + + if (amdgpu_sriov_vf(adev)) + return 0; + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); return 0; } @@ -1632,14 +1645,15 @@ static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) { int r; + gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { - gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); /* legacy rlc firmware loading */ r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); if (r) return r; - gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); } + gfx_v9_4_3_update_spm_vmid_internal(adev, xcc_id, 0xf); + gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); /* disable CG */ @@ -1667,28 +1681,38 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, - int inst, struct amdgpu_ring *ring, unsigned int vmid) +static void gfx_v9_4_3_update_spm_vmid_internal(struct amdgpu_device *adev, + int xcc_id, unsigned int vmid) { u32 reg, pre_data, data; - reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) pre_data = RREG32_NO_KIQ(reg); else - pre_data = RREG32(reg); + pre_data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; if (pre_data != data) { if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { - WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); } else - WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); } } +static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) +{ + amdgpu_gfx_off_ctrl(adev, false); + + gfx_v9_4_3_update_spm_vmid_internal(adev, xcc_id, vmid); + + amdgpu_gfx_off_ctrl(adev, true); +} + static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, @@ -2376,6 +2400,7 @@ static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) int i, num_xcc; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -2510,12 +2535,112 @@ static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v9_4_3_spm_start(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), 0); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_INT_CNTL), 1); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); + data |= RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); +} + +static void gfx_v9_4_3_spm_stop(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); + data &= (~RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), 0); +} + +static void gfx_v9_4_3_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_4_3_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + regRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + regRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), + regRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), + regRLC_SPM_SEGMENT_THRESHOLD), 0x1); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_4_3_spm_funcs = { + .start = &gfx_v9_4_3_spm_start, + .stop = &gfx_v9_4_3_spm_stop, + .set_rdptr = &gfx_v9_4_3_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_4_3_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_4_3_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_4_3_spm_funcs; +} + static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_4_3_set_spm_funcs(adev); gfx_v9_4_3_set_kiq_pm4_funcs(adev); gfx_v9_4_3_set_ring_funcs(adev); gfx_v9_4_3_set_irq_funcs(adev); @@ -2537,6 +2662,10 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -3395,6 +3524,41 @@ static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } +static int gfx_v9_4_3_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + } + return 0; +} + +static int gfx_v9_4_3_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int xcc_id; + + xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); + + amdgpu_amdkfd_rlc_spm_interrupt(adev, xcc_id); + return 0; +} + static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { @@ -4822,11 +4986,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { .process = gfx_v9_4_3_priv_inst_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_4_3_spm_irq_funcs = { + .set = gfx_v9_4_3_spm_set_interrupt_state, + .process = gfx_v9_4_3_spm_irq, +}; + static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_4_3_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 87adcaa415738..4291325d9e164 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -35,9 +35,10 @@ * 0.1 - Initial revision * 0.2 - add kfd_ioctl_spm_buffer_header * 0.3 - add multiple XCC support + * 0.4 - add gfx_v9_4_3 SPM support */ #define KFD_IOCTL_SPM_MAJOR_VERSION 0 -#define KFD_IOCTL_SPM_MINOR_VERSION 3 +#define KFD_IOCTL_SPM_MINOR_VERSION 4 struct user_buf { uint64_t __user *user_addr; From b565b43062eb4ef7dac8d732b0b28a27a19e5f88 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 2 Oct 2024 09:49:37 -0400 Subject: [PATCH 1369/2070] drm/amdgpu: change xcp_id to xcc_id psp fw implementation needs xcc_mask as input actually. Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Reviewed-by: Feifei Xu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 ++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +- drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 2 +- 5 files changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index fb2be29c61be9..1b41c01e01525 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -913,7 +913,7 @@ bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) } /* Config CGTT_SQ_CLK_CTRL */ -int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) { int r; @@ -921,7 +921,7 @@ int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, if (!adev->kfd.init_complete) return 0; - r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, + r = psp_config_sq_perfmon(&adev->psp, xcc_id, core_override_enable, reg_override_enable, perfmon_override_enable); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 7701f3616faa7..03234bc217e6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -285,7 +285,7 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, u32 inst); int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); -int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a7c7b378c696c..d24078970cb36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4041,7 +4041,7 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) } int psp_config_sq_perfmon(struct psp_context *psp, - uint32_t xcp_id, bool core_override_enable, + uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) { int ret; @@ -4049,11 +4049,6 @@ int psp_config_sq_perfmon(struct psp_context *psp, if (amdgpu_sriov_vf(psp->adev)) return 0; - if (xcp_id > MAX_XCP) { - dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); - return -EINVAL; - } - if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); @@ -4062,15 +4057,15 @@ int psp_config_sq_perfmon(struct psp_context *psp, struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; - cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); + cmd->cmd.config_sq_perfmon.gfx_xcc_mask = BIT_MASK(xcc_id); cmd->cmd.config_sq_perfmon.core_override = core_override_enable; cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); if (ret) - dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", - xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); + dev_warn(psp->adev->dev, "PSP failed to config sq: xcc%d core%d reg%d perfmon%d\n", + xcc_id, core_override_enable, reg_override_enable, perfmon_override_enable); release_psp_cmd_buf(psp); return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 79a49cba8d406..c6e311077b58e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -623,7 +623,7 @@ int is_psp_fw_valid(struct psp_bin_desc bin); int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); bool amdgpu_psp_get_ras_capability(struct psp_context *psp); -int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, +int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index e8f768638fd59..c52ba7c94bf4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -361,7 +361,7 @@ struct psp_gfx_cmd_sriov_spatial_part { /*Structure for sq performance monitoring/profiling enable/disable*/ struct psp_gfx_cmd_config_sq_perfmon { - uint32_t gfx_xcp_mask; + uint32_t gfx_xcc_mask; uint8_t core_override; uint8_t reg_override; uint8_t perfmon_override; From 06d22b310dfc52a9c903ae429acbf9332d2c10ae Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 2 Oct 2024 10:08:39 -0400 Subject: [PATCH 1370/2070] drm/amdkfd: fix sq hang on gfx_v9_4_3 when running pc sampling host trap. -v2: use GET_INST and dev_dbg Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Tested-by: Vladimir Indic --- .../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 21 ++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 ++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index b9d226aa7b133..334ede86a48bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,25 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) +{ + uint32_t sq_clk_ctrl; + + /* disable/enable SQ core override */ + amdgpu_amdkfd_config_sq_perfmon(adev, GET_INST(GC, inst), value, 0, 0); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + sq_clk_ctrl = RREG32_SOC15(GC, GET_INST(GC, inst), regCGTT_SQ_CLK_CTRL); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + dev_dbg(adev->dev, "sq clock control on instance [%d]: 0x%x\n", + GET_INST(GC, inst), sq_clk_ctrl); +} + static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t *target_simd, @@ -568,5 +587,5 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, - .override_core_cg = kgd_gfx_v9_override_core_cg + .override_core_cg = kgd_gfx_v9_4_3_override_core_cg }; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index c829676d631a6..603e557c986b4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -32,9 +32,10 @@ * * 0.1 - Initial revision * 0.2 - Support gfx9_4_3 Host Trap PC sampling + * 0.3 - Fix gfx9_4_3 SQ hang issue */ #define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 2 +#define KFD_IOCTL_PCS_MINOR_VERSION 3 struct supported_pc_sample_info { uint32_t ip_version; From 44dd9105de0d5a97e7c76ec7aefb788df3b8b2d3 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 15 Nov 2024 13:17:41 -0500 Subject: [PATCH 1371/2070] drm/amdgpu: Use SG helper for peer-direct sgtable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use SG helper functions to generate sgtable for peer-direct interface. This also improves performance since contiguous ranges are squashed into single scatterlist entry Suggested-by: Christian König Signed-off-by: Harish Kasiviswanathan Reviewed-by: Christian König --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 51 +++++-------------- 1 file changed, 13 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index dcf09f30330be..fa4bcc347c8bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2555,13 +2555,11 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct sg_table **ret_sg) { struct sg_table *sg = NULL; - struct scatterlist *s; struct page **pages; uint64_t offset_in_page; unsigned int page_size; unsigned int cur_page; - unsigned int chunks; - unsigned int idx; + size_t max_segment = 0; int ret; /* Determine access does not cross memory boundary */ @@ -2591,52 +2589,29 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, /* Handle BO (type: ttm_bo_type_device) that is used to surface * memory resources from GPU's GART aperture. The allocation flag * of BO falls in GTT domain i.e. the physical backing memory is - * part of system memory. Construction of SG Table proceeds - * as follows: - * - * Allocate memory for SG Table - * Determine number of Scatterlist node in table - * Logic uses one Scatterlist node per PAGE_SIZE - * Allocate memory for Scatterlist nodes - * Initialize Scatterlist nodes to zero length - * Walk down system memory pointed by BO while - * Updating Scatterlist nodes with system memory info + * part of system memory */ sg = kmalloc(sizeof(*sg), GFP_KERNEL); - if (!sg) { - ret = -ENOMEM; - goto out; - } + if (!sg) + return -ENOMEM; page_size = PAGE_SIZE; offset_in_page = offset & (page_size - 1); - chunks = (size + offset_in_page + page_size - 1) - / page_size; - - ret = sg_alloc_table(sg, chunks, GFP_KERNEL); - if (unlikely(ret)) - goto out; - - for_each_sgtable_sg(sg, s, idx) - s->length = 0; pages = bo->tbo.ttm->pages; cur_page = offset / page_size; - for_each_sg(sg->sgl, s, sg->orig_nents, idx) { - uint64_t chunk_size, length; - - chunk_size = page_size - offset_in_page; - length = min(size, chunk_size); - sg_set_page(s, pages[cur_page], length, offset_in_page); - s->dma_address = page_to_phys(pages[cur_page]); - s->dma_length = length; + max_segment = dma_max_mapping_size(dma_dev); + if (!max_segment) + max_segment = UINT_MAX; - size -= length; - offset_in_page = 0; - cur_page++; - } + ret = sg_alloc_table_from_pages_segment(sg, &pages[cur_page], + bo->tbo.ttm->num_pages - cur_page, + offset_in_page, size, max_segment, + GFP_KERNEL); + if (ret) + goto out; if (dma_dev) { ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); From 225e0217fca66431238877a9698810f5c07f09a7 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 20 Nov 2024 13:57:58 +0800 Subject: [PATCH 1372/2070] drm/amdkcl:test whether sg_alloc_table_from_pages_segment() is available It's caused by follow commit:166ea4a47bdfec1a789c98a6a5bab70274d58502 "drm/amdgpu: Use SG helper for peer-direct sgtable" Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c | 19 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../m4/sg_alloc_table_from_pages_segment.m4 | 17 +++++++++++++++++ include/kcl/kcl_scatterlist.h | 15 +++++++++++++++ 7 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 create mode 100644 include/kcl/kcl_scatterlist.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4a37a7ba6e08e..6eaf2f73a5832 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ + kcl_scatterlist.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c new file mode 100644 index 0000000000000..44a6951e306e8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2007 Jens Axboe + * + * Scatterlist handling helpers. + */ +#include + +#ifndef HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT +int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **pages, + unsigned int n_pages, unsigned int offset, + unsigned long size, unsigned int max_segment, + gfp_t gfp_mask) +{ + return PTR_ERR_OR_ZERO(__sg_alloc_table_from_pages(sgt, pages, n_pages, + offset, size, max_segment, gfp_mask)); +} +EXPORT_SYMBOL(_kcl_sg_alloc_table_from_pages_segment); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7f724d30266fe..0ae42dc928c8b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -128,4 +128,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 148515957f25f..ff4aac44cc9da 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -981,6 +981,9 @@ /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 +/* whether sg_alloc_table_from_pages_segment() is available */ +#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 + /* enum SMCA_UMC_V2 is available */ #define HAVE_SMCA_UMC_V2 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a327d6e26540f..c262a1f637da3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -231,6 +231,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE AC_AMDGPU_DRM_CLIENT AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT + AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 new file mode 100644 index 0000000000000..e2c706d06e921 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 90e7a6de62781c27d6a111fccfb19b807f9b6887 +dnl # v5.14-rc6-1-g90e7a6de6278 +dnl # lib/scatterlist: Provide a dedicated function to support table append +dnl # +AC_DEFUN([AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + sg_alloc_table_from_pages_segment(NULL,NULL,0,0,0,0,GFP_KERNEL); + ], [sg_alloc_table_from_pages_segment],[lib/scatterlist.c], [ + AC_DEFINE(HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT, 1, + [sg_alloc_table_from_pages_segment() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_scatterlist.h b/include/kcl/kcl_scatterlist.h new file mode 100644 index 0000000000000..d73af56137c72 --- /dev/null +++ b/include/kcl/kcl_scatterlist.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_LINUX_SCATTERLIST_H +#define _KCL_LINUX_SCATTERLIST_H + +#include + +#ifndef HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT +int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **pages, + unsigned int n_pages, unsigned int offset, + unsigned long size, + unsigned int max_segment, gfp_t gfp_mask); +#define sg_alloc_table_from_pages_segment _kcl_sg_alloc_table_from_pages_segment +#endif + +#endif /* _LINUX_SCATTERLIST_H */ From dea7a1fe554358ae2cd0bd4fa21c33af9fb7c466 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 26 Nov 2024 10:20:56 +0800 Subject: [PATCH 1373/2070] drm/amdkcl: use the amdkcl_ttm_resvp to get resv It's caused by the commit:9d3d50f "drm/amdgpu: add gfx eviction fence helpers" commit:64b20409 "drm/amdgpu: resume gfx userqueues" v6.14-rc4-390-gf3bcfd04a52f drm/ttm: Add a macro to perform LRU iteration v6.14-rc1-243-gcb0de06d1b0a drm/amdgpu: remove all KFD fences from the BO on release Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c | 4 ++-- drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index fa4bcc347c8bf..106339c29e117 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -399,7 +399,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, */ void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) { - struct dma_resv *resv = &bo->tbo.base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(&bo->tbo); struct dma_fence *fence, *stub; struct dma_resv_iter cursor; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index 23d7d0b0d6252..aed29e3c0c4d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -198,7 +198,7 @@ int amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr, struct amdgpu_bo *bo) { struct amdgpu_eviction_fence *ev_fence; - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); int ret; if (!resv) @@ -224,7 +224,7 @@ void amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, { struct dma_fence *stub = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, evf_mgr->ev_fence_ctx, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), evf_mgr->ev_fence_ctx, stub, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(stub); } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index b8c4d1200eabd..567b3f12f23e2 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -945,7 +945,7 @@ static void ttm_bo_lru_cursor_cleanup_bo(struct ttm_bo_lru_cursor *curs) if (bo) { if (curs->needs_unlock) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); curs->bo = NULL; } @@ -1169,7 +1169,7 @@ bool ttm_bo_shrink_suitable(struct ttm_buffer_object *bo, struct ttm_operation_c { return bo->ttm && ttm_tt_is_populated(bo->ttm) && !bo->pin_count && (!ctx->no_wait_gpu || - dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP)); + dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)); } EXPORT_SYMBOL(ttm_bo_shrink_suitable); From 9d298db7050563d09faed2e6e2cc176daa052307 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 26 Nov 2024 12:13:49 +0800 Subject: [PATCH 1374/2070] drm/amdkcl: Add 'static' to function to avoid Intree build compilation failure In the process of the Intree build, when the GCC compiler is invoked with the -Werror=missing-prototypes flag, the compilation was failing due to kgd_gfx_v9_4_3_override_core_cg() lacking a prior prototype declaration. Add 'static' ensures that during Intree build, the compilation can proceed smoothly without being halted by the missing prototype error. Signed-off-by: chengjya Reviewed-by: Bob Zhou Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index 334ede86a48bc..c1c184babcaf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,7 +520,7 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } -void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, +static void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, uint32_t value, uint32_t inst) { From 84891f60352407b941a92f59749d7eb99ae57fdc Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 27 Nov 2024 10:06:00 +0800 Subject: [PATCH 1375/2070] drm/amdkcl: Move _kcl_drm_dp_mst_topology_queue_probe() declaration to proper header file Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../drm/amd/amdkcl/kcl_drm_dp_mst_topology.c | 4 +-- drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 5 --- include/kcl/kcl_drm_dp_mst_helper.h | 32 +++++++++++++++++++ 4 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 include/kcl/kcl_drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c index d6b4e9d0f77be..8b3f68cacab77 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c @@ -20,7 +20,7 @@ * OF THIS SOFTWARE. */ -#include +#include #include #ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE @@ -54,7 +54,7 @@ _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) * cases - for instance when a sink gets plugged/unplugged to a port - the SW * state will get updated automatically via MST UP message notifications. */ -void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0ae42dc928c8b..569a4a0212690 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -129,4 +129,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index a6e237c081029..a84cd2ac22cc2 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -117,9 +117,4 @@ _kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 #endif -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE -void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); -#define drm_dp_mst_topology_queue_probe _kcl_drm_dp_mst_topology_queue_probe -#endif - #endif diff --git a/include/kcl/kcl_drm_dp_mst_helper.h b/include/kcl/kcl_drm_dp_mst_helper.h new file mode 100644 index 0000000000000..69bb114300b58 --- /dev/null +++ b/include/kcl/kcl_drm_dp_mst_helper.h @@ -0,0 +1,32 @@ +/* + * Copyright © 2014 Red Hat. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_MST_HELPER_H_ +#define _KCL_DRM_DP_MST_HELPER_H_ + +#include + +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); +#define drm_dp_mst_topology_queue_probe _kcl_drm_dp_mst_topology_queue_probe +#endif + +#endif From 47909678ae12eeda7a1dde78176a3ee3c453e205 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 28 Nov 2024 16:39:40 +0800 Subject: [PATCH 1376/2070] drm/amdkcl: wrap slab.h under HAVE_DMA_FENCE_CHAIN_ALLOC The dma_fence_chain_alloc includes kmalloc() and kfree(). the slab.h need the same mecro judge condition, so fix it. Signed-off-by: Bob Zhou Reviewed-by: chengjya --- include/kcl/kcl_dma_fence_chain.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index 97900481479c5..57324eeca102e 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -13,10 +13,13 @@ #include #endif +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) || !defined(HAVE_DMA_FENCE_CHAIN_ALLOC) +#include +#endif + #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #include #include -#include /** * struct dma_fence_chain - fence to represent an node of a fence chain From 22160d22d57a502ebd91b30c0e0bbd3c0f4e2782 Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 28 Nov 2024 17:32:37 +0800 Subject: [PATCH 1377/2070] drm/amdkcl: test __sg_alloc_table_from_pages() has 9 args It's caused by follow commit:166ea4a47bdfec1a789c98a6a5bab70274d58502 "drm/amdgpu: Use SG helper for peer-direct sgtable" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c | 8 +++++++- drivers/gpu/drm/amd/dkms/config/config.h | 16 ++-------------- .../dkms/m4/sg_alloc_table_from_pages_segment.m4 | 14 ++++++++++++++ 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c index 44a6951e306e8..bfa5ed0e16feb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c @@ -12,8 +12,14 @@ int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **p unsigned long size, unsigned int max_segment, gfp_t gfp_mask) { +#ifdef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS return PTR_ERR_OR_ZERO(__sg_alloc_table_from_pages(sgt, pages, n_pages, - offset, size, max_segment, gfp_mask)); + offset, size, max_segment, + NULL, 0, gfp_mask)); +#else + return __sg_alloc_table_from_pages(sgt, pages, n_pages, offset, size, + max_segment, gfp_mask); +#endif } EXPORT_SYMBOL(_kcl_sg_alloc_table_from_pages_segment); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ff4aac44cc9da..7054b236e719d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1162,20 +1162,8 @@ /* __kthread_should_park() is available */ /* #undef HAVE___KTHREAD_SHOULD_PARK */ -/* __print_array is available */ -#define HAVE___PRINT_ARRAY 1 - -/* kobj_type->default_groups is available */ -#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 - -/* close_fd() is available */ -#define HAVE_KERNEL_CLOSE_FD 1 - -/* ksys_close() is available */ -#define HAVE_KSYS_CLOSE_FD 1 - -/* pm_suspend_target_state is available */ -#define HAVE_PM_SUSPEND_TARGET_STATE 1 +/* __sg_alloc_table_from_pages() has 9 args */ +/* #undef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS */ /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 index e2c706d06e921..474a1baed1064 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 @@ -12,6 +12,20 @@ AC_DEFUN([AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT], [ ], [sg_alloc_table_from_pages_segment],[lib/scatterlist.c], [ AC_DEFINE(HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT, 1, [sg_alloc_table_from_pages_segment() is available]) + ],[ + dnl # + dnl # commit 07da1223ec939982497db3caccd6215b55acc35c + dnl # v5.9-rc8-3-g07da1223ec93 + dnl # lib/scatterlist: Add support in dynamic allocation of SG table from pages + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + __sg_alloc_table_from_pages(NULL,NULL,0,0,0,0,NULL,0,GFP_KERNEL); + ], [__sg_alloc_table_from_pages],[lib/scatterlist.c], [ + AC_DEFINE(HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS, 1, + [__sg_alloc_table_from_pages() has 9 args]) + ]) ]) ]) ]) From ddff21444685cd946a7a1fcdbdb6477f0ba6746e Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 3 Dec 2024 10:18:23 +0800 Subject: [PATCH 1378/2070] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by following commit: d1dfdec7 "drm/amdgpu: Add amdgpu_vcn_sched_mask debugfs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 75ae9b429420e..c3f00b9285c21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1436,10 +1436,15 @@ static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) *val = mask; return 0; } - +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, amdgpu_debugfs_vcn_sched_mask_get, amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, + amdgpu_debugfs_vcn_sched_mask_get, + amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); +#endif #endif void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) From e11c25dfc97a2d84f23f1dca047f79cc9d4ff966 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 3 Dec 2024 16:40:22 +0800 Subject: [PATCH 1379/2070] drm/amdkcl: relax unused-variable error for conftest Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c262a1f637da3..2822a1501a0d7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -448,7 +448,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 91b36b22a7824..f8f51b0d19c7a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -13,6 +13,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") + CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-.*-variable|error=unused-.*-variable)( |$)//g') CPPFLAGS=$(echo $CFLAGS | \ cut -d ';' -f 1 | \ From 7d1e06ec4af0ee1d335525099eaca8d5d76a5f4b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 4 Dec 2024 10:01:54 -0500 Subject: [PATCH 1380/2070] drm/kfd: copy back total spm data to user space copy back total spm data to user space. Signed-off-by: James Zhu Reviewed-by: Bing Ma Tested-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 4291325d9e164..c7dc812b5a483 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -470,7 +470,8 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device } static int spm_update_dest_info(struct kfd_process_device *pdd, - int inst, struct kfd_ioctl_spm_args *user_spm_data) + int inst, struct kfd_ioctl_spm_args *user_spm_data, + struct kfd_ioctl_spm_args *user_spm_ptr) { struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); int ret = 0; @@ -480,8 +481,8 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_buffer_header spm_header; uint64_t __user *user_address; - user_spm_data->bytes_copied += spm->size_copied; - user_spm_data->has_data_loss += spm->has_data_loss; + user_spm_ptr->bytes_copied += spm->size_copied; + user_spm_ptr->has_data_loss += spm->has_data_loss; memset(&spm_header, 0, sizeof(spm_header)); user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr - sizeof(spm_header)); @@ -499,9 +500,6 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, } } if (user_spm_data->dest_buf) { - user_spm_data->bytes_copied = 0; - user_spm_data->has_data_loss = 0; - spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; spm->ubuf.ubufsize = user_spm_data->buf_size; /* reserve space for kfd_ioctl_spm_buffer_header */ @@ -585,6 +583,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev memcpy(&user_spm_data, user_spm_ptr, sizeof(user_spm_data)); user_spm_data.buf_size = ubufsize; + if (user_spm_data.timeout && spm_cntr->have_users_buf_cnt && !READ_ONCE(spm_cntr->are_users_buf_filled)) { dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", @@ -606,6 +605,8 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev flush_work(&pdd->spm_work); } + user_spm_ptr->bytes_copied = 0; + user_spm_ptr->has_data_loss = 0; for_each_inst(inst, pdd->dev->xcc_mask) { struct kfd_spm_base *spm = &(spm_cntr->spm[inst]); @@ -613,7 +614,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* Get info about filled space in previous output buffer. * Setup new dest buf if provided. */ - ret = spm_update_dest_info(pdd, inst, &user_spm_data); + ret = spm_update_dest_info(pdd, inst, &user_spm_data, user_spm_ptr); if (ret) goto out; } From 80b5cbe19c5f08619cf6269159e04ca89cf5a886 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 17 Dec 2024 16:02:26 +0800 Subject: [PATCH 1381/2070] drm/amdkcl: fake the drm/drm_panic.h header It's caused by the following commits: 89e8d6fa("drm/amdgpu: add generic display panic helper code") Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_panic.h | 9 +++++++++ 3 files changed, 18 insertions(+) create mode 100644 include/kcl/header/drm/drm_panic.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7054b236e719d..7f359c62160cb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -479,6 +479,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PANIC_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 4b96e46ae974b..bca9e1778fa23 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -105,6 +105,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) + dnl # + dnl # v6.9-rc2-212-ge2a1cda3e0c7 + dnl # drm/panic: Add drm panic locking + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_panic.h]) + dnl # dnl # v6.9-rc6-1436-gaae4682e5d66 dnl # drm/fbdev-generic: Convert to fbdev-ttm diff --git a/include/kcl/header/drm/drm_panic.h b/include/kcl/header/drm/drm_panic.h new file mode 100644 index 0000000000000..c64b615518416 --- /dev/null +++ b/include/kcl/header/drm/drm_panic.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PANIC_H_H_ +#define _KCL_HEADER_DRM_PANIC_H_H_ + +#ifdef HAVE_DRM_DRM_PANIC_H +#include_next +#endif + +#endif From 17b9dad6bda1561355050a0179eae9f1ff5ba302 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 13 Dec 2024 11:25:39 +0800 Subject: [PATCH 1382/2070] drm/amdkcl: test struct drm_plane_helper_funcs->get_scanout_buffer() is available It's caused by the following commits: 89e8d6fa("drm/amdgpu: add generic display panic helper code") 3feb9568("drm/amd/display: add DC drm_panic support") 7d862fb7("drm/amd/display: add non-DC drm_panic support") Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 23 ++++++++++++++++++- 8 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index e3b2714ac9c6e..10d1921c13382 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1912,6 +1912,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) */ static struct amdgpu_bo *panic_abo; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* Use the indirect MMIO to write each pixel to the GPU VRAM, * This is a simplified version of amdgpu_device_mm_access() */ @@ -1991,3 +1992,4 @@ int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, return 0; } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 49a29bf47a379..85a7ebbc469ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -52,8 +52,10 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier); int amdgpu_display_suspend_helper(struct amdgpu_device *adev); int amdgpu_display_resume_helper(struct amdgpu_device *adev); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb); +#endif #define ABM_SYSFS_CONTROL -1 #define ABM_LEVEL_OFF 0 diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6ad793264dd0b..b46e82877aa05 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2678,6 +2678,7 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v10_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2703,6 +2704,7 @@ static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_fu .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v10_0_panic_flush, }; +#endif static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2751,7 +2753,9 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 5a1fe581e02d2..831e6cb450663 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2645,6 +2645,7 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v6_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2670,6 +2671,7 @@ static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_fun .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v6_0_panic_flush, }; +#endif static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2698,7 +2700,9 @@ static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 34e5b3e0ffff6..8d68edc0b3934 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2604,6 +2604,7 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v8_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2628,6 +2629,7 @@ static const struct drm_plane_helper_funcs dce_v8_0_drm_primary_plane_helper_fun .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v8_0_panic_flush, }; +#endif static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2656,7 +2658,9 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v8_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a72279afb4357..abd25f9abd468 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1473,6 +1473,7 @@ static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, amdgpu_dm_plane_handle_cursor_update(plane, old_state); } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane->state); @@ -1486,6 +1487,7 @@ static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane) dc_plane_force_dcc_and_tiling_disable(dc_plane_state, fb->modifier ? true : false); } +#endif static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, @@ -1501,8 +1503,10 @@ static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = { .atomic_check = amdgpu_dm_plane_atomic_check, .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = amdgpu_dm_plane_panic_flush, +#endif }; static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7f359c62160cb..a34778ac6765a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1057,6 +1057,9 @@ arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 +/* struct drm_plane_helper_funcs->get_scanout_buffer is available */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER 1 + /* ide->idr_base is available */ #define HAVE_STRUCT_IDE_IDR_BASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index c5e0918674904..fce9bda9696c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -14,5 +14,26 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_ ]) ]) -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS],[AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS +dnl # +dnl # v6.9-rc2-213-gbf9fb17c6672 +dnl # drm/panic: Add a drm panic handler +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_plane_helper_funcs *ptr = NULL; + ptr->get_scanout_buffer(NULL, NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER, 1, + [struct drm_plane_helper_funcs->get_scanout_buffer is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER ]) From c51852b80e2b56d827723a80f277c65452057bb2 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 20 Dec 2024 12:03:51 +0800 Subject: [PATCH 1383/2070] drm/amdkcl: fix build error by adding missing arguments It's caused by the following commit: 907c32e5 "drm/amdkfd: fixed page fault when enable MES shader debugger" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 3563a4ee506a7..fe778b210673f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -363,7 +363,7 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en) &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (r) { dev_err(adev->dev, "failed to allocate process context bo\n"); From 60541ecba3556ae78c2ee010661e1b1a08669523 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 20 Dec 2024 15:04:08 +0800 Subject: [PATCH 1384/2070] drm/amdkcl: Test if kfifo_out_linear is available Backport this upstream patch and the functions needed to add kfifo_out_linear support for Redhat kernel. This is used in the following patch. commit 4edd7e96a1f1 ("kfifo: add kfifo_out_linear{,_ptr}()") Author: Jiri Slaby (SUSE) Date: Fri Apr 5 08:08:14 2024 +0200 Signed-off-by: Philip Yang Signed-off-by: Flora Cui Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c | 53 ++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 | 18 ++++ include/kcl/kcl_kfifo.h | 96 +++++++++++++++++++ 7 files changed, 176 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 create mode 100644 include/kcl/kcl_kfifo.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6eaf2f73a5832..62baea5001d4a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o + kcl_scatterlist.o kcl_kfifo.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c new file mode 100644 index 0000000000000..fad3a2306bdad --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#ifndef HAVE_KFIFO_OUT_LINEAR + +#define __KFIFO_PEEK(data, out, mask) \ + ((data)[(out) & (mask)]) +/* + * __kfifo_peek_n internal helper function for determinate the length of + * the next record in the fifo + */ +static unsigned int __kfifo_peek_n(struct __kfifo *fifo, size_t recsize) +{ + unsigned int l; + unsigned int mask = fifo->mask; + unsigned char *data = fifo->data; + + l = __KFIFO_PEEK(data, fifo->out, mask); + + if (--recsize) + l |= __KFIFO_PEEK(data, fifo->out + 1, mask) << 8; + + return l; +} + +unsigned int __kfifo_out_linear(struct __kfifo *fifo, + unsigned int *tail, unsigned int n) +{ + unsigned int size = fifo->mask + 1; + unsigned int off = fifo->out & fifo->mask; + + if (tail) + *tail = off; + + return min3(n, fifo->in - fifo->out, size - off); +} +EXPORT_SYMBOL(__kfifo_out_linear); + +unsigned int __kfifo_out_linear_r(struct __kfifo *fifo, + unsigned int *tail, unsigned int n, size_t recsize) +{ + if (fifo->in == fifo->out) + return 0; + + if (tail) + *tail = fifo->out + recsize; + + return min(n, __kfifo_peek_n(fifo, recsize)); +} +EXPORT_SYMBOL(__kfifo_out_linear_r); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 569a4a0212690..e70437bc74ea7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -129,5 +129,6 @@ #include #include #include +#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a34778ac6765a..0bae0e1fbf50d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -744,6 +744,12 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kfifo_out_linear() available */ +#define HAVE_KFIFO_OUT_LINEAR 1 + +/* kfifo_put() have non pointer parameter */ +#define HAVE_KFIFO_PUT_NON_POINTER 1 + /* kmalloc_size_roundup is available */ #define HAVE_KMALLOC_SIZE_ROUNDUP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2822a1501a0d7..d0dbf43547819 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -205,6 +205,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_DMA_BUF_IS_DYNAMIC + AC_AMDGPU_KFIFO_OUT_LINEAR AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_COLOR_CTM_3X4 AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP diff --git a/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 b/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 new file mode 100644 index 0000000000000..ad65e8605f268 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v6.9-rc3-3-g4edd7e96a1f1 +dnl # kfifo: add kfifo_out_linear{,_ptr}() +dnl # +AC_DEFUN([AC_AMDGPU_KFIFO_OUT_LINEAR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + static DEFINE_KFIFO(fifo, int, 2); + unsigned int ret = kfifo_out_linear(&fifo, 0, 0); + ],[ + AC_DEFINE(HAVE_KFIFO_OUT_LINEAR, 1, + [kfifo_out_linear() available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_kfifo.h b/include/kcl/kcl_kfifo.h new file mode 100644 index 0000000000000..3be41b4d98708 --- /dev/null +++ b/include/kcl/kcl_kfifo.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_KFIFO_H +#define KCL_LINUX_KFIFO_H + +#ifndef HAVE_KFIFO_OUT_LINEAR + +#include + +/** + * commit 4edd7e96a1f159f43bd1cb82616f81eaddd54262 + * Author: Jiri Slaby (SUSE) + * Date: Fri Apr 5 08:08:14 2024 +0200 + * + * kfifo: add kfifo_out_linear{,_ptr}() + */ + +/** + * kfifo_out_linear - gets a tail of/offset to available data + * @fifo: address of the fifo to be used + * @tail: pointer to an unsigned int to store the value of tail + * @n: max. number of elements to point at + * + * This macro obtains the offset (tail) to the available data in the fifo + * buffer and returns the + * numbers of elements available. It returns the available count till the end + * of data or till the end of the buffer. So that it can be used for linear + * data processing (like memcpy() of (@fifo->data + @tail) with count + * returned). + * + * Note that with only one concurrent reader and one concurrent + * writer, you don't need extra locking to use these macro. + */ +#define kfifo_out_linear(fifo, tail, n) \ +__kfifo_uint_must_check_helper( \ +({ \ + typeof((fifo) + 1) __tmp = (fifo); \ + unsigned int *__tail = (tail); \ + unsigned long __n = (n); \ + const size_t __recsize = sizeof(*__tmp->rectype); \ + struct __kfifo *__kfifo = &__tmp->kfifo; \ + (__recsize) ? \ + __kfifo_out_linear_r(__kfifo, __tail, __n, __recsize) : \ + __kfifo_out_linear(__kfifo, __tail, __n); \ +}) \ +) + +/** + * kfifo_out_linear_ptr - gets a pointer to the available data + * @fifo: address of the fifo to be used + * @ptr: pointer to data to store the pointer to tail + * @n: max. number of elements to point at + * + * Similarly to kfifo_out_linear(), this macro obtains the pointer to the + * available data in the fifo buffer and returns the numbers of elements + * available. It returns the available count till the end of available data or + * till the end of the buffer. So that it can be used for linear data + * processing (like memcpy() of @ptr with count returned). + * + * Note that with only one concurrent reader and one concurrent + * writer, you don't need extra locking to use these macro. + */ +#define kfifo_out_linear_ptr(fifo, ptr, n) \ +__kfifo_uint_must_check_helper( \ +({ \ + typeof((fifo) + 1) ___tmp = (fifo); \ + unsigned int ___tail; \ + unsigned int ___n = kfifo_out_linear(___tmp, &___tail, (n)); \ + *(ptr) = ___tmp->kfifo.data + ___tail * kfifo_esize(___tmp); \ + ___n; \ +}) \ +) + +extern unsigned int __kfifo_out_linear(struct __kfifo *fifo, + unsigned int *tail, unsigned int n); + +extern unsigned int __kfifo_out_linear_r(struct __kfifo *fifo, + unsigned int *tail, unsigned int n, size_t recsize); + +/** + * kfifo_skip_count - skip output data + * @fifo: address of the fifo to be used + * @count: count of data to skip + */ +#define kfifo_skip_count(fifo, count) do { \ + typeof((fifo) + 1) __tmp = (fifo); \ + const size_t __recsize = sizeof(*__tmp->rectype); \ + struct __kfifo *__kfifo = &__tmp->kfifo; \ + if (__recsize) \ + __kfifo_skip_r(__kfifo, __recsize); \ + else \ + __kfifo->out += (count); \ +} while (0) + +#endif +#endif From f86731f9b070a91b00721b72547a14283b1f5bf8 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Mon, 23 Dec 2024 09:21:03 -0500 Subject: [PATCH 1385/2070] amdgpu: validate pointer before accessing its field Validate adev pointer before access its field in amdgpu_gem_object_free(), to avoid invalid memory access. Signed-off-by: Jiang Liu Signed-off-by: Kent Russell Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index ea67f1e3d3579..1a951f7c7ccaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -166,7 +166,7 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) #endif { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); - struct amdgpu_device *adev = amdgpu_ttm_adev(aobj->tbo.bdev); + struct amdgpu_device *adev; if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { if (!amdgpu_bo_reserve(aobj, false)) { @@ -175,6 +175,7 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } + adev = amdgpu_ttm_adev(aobj->tbo.bdev); if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) atomic64_sub(amdgpu_bo_size(aobj), &adev->direct_gma.vram_usage); From 7266e3fdca1b97be3c9f48ceda6132c1fff7438a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 17 Dec 2024 19:48:01 +0800 Subject: [PATCH 1386/2070] drm/amdkcl: unify dkms & oot make cmd Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/Kbuild | 230 ++++++++++++++++ drivers/gpu/drm/amd/dkms/Makefile | 246 ++---------------- drivers/gpu/drm/amd/dkms/dkms.conf | 19 +- drivers/gpu/drm/amd/dkms/oot/Makefile.oot | 41 --- drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 2 +- drivers/gpu/drm/amd/dkms/oot/pre-build.sh | 91 ------- drivers/gpu/drm/amd/dkms/pre-build.sh | 11 +- 7 files changed, 266 insertions(+), 374 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Kbuild delete mode 100644 drivers/gpu/drm/amd/dkms/oot/Makefile.oot delete mode 100644 drivers/gpu/drm/amd/dkms/oot/pre-build.sh diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild new file mode 100644 index 0000000000000..6153df061bcd8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -0,0 +1,230 @@ +ifeq ($(CC), gcc) +GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) +GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) +# CONFIG_GCC_VERSION returns x.xx.xx as the version format +GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) + +KERNEL_MAJ=$(VERSION) +KERNEL_PATCHLEVEL=$(PATCHLEVEL) +KERNEL_SUBLEVEL=$(SUBLEVEL) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) + +kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +ifdef CONFIG_CC_IS_GCC +ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) +$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") +$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") +endif +else +export CONFIG_CC_IS_GCC=y +export CONFIG_GCC_VERSION=$(GCCSTR) +$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") +endif + +endif + +include $(src)/amd/dkms/Makefile.compiler + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifneq ($(call gcc-min-version, 40805), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) +$(error dma_resv->seq is missing. exit...) +endif + +ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) +$(error reservation_ww_class is missing. exit...) +endif + +DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) +DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) +ifeq ($(DRM_VER),) +DRM_VER = $(VERSION) +DRM_PATCH = $(PATCHLEVEL) +endif + +subdir-ccflags-y += \ + -DDRM_VER=$(DRM_VER) \ + -DDRM_PATCH=$(DRM_PATCH) \ + -DDRM_SUB="0" + +define get_rhel_version +printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) +endef +RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) +RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) + +ifneq (,$(RHEL_MAJOR)) +OS_NAME = "rhel" +OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" +else ifneq (,$(wildcard /etc/os-release)) +OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" +# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL +ifeq ("centos",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("rhel",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("linuxmint",$(OS_NAME)) +OS_NAME="ubuntu" +endif +OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +else +OS_NAME = "unknown" +OS_VERSION = "0.0" +endif + +OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) + +ifeq ("ubuntu",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_UBUNTU +else ifeq ("rhel",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_RHEL +else ifeq ("steamos",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_STEAMOS +else ifeq ("sled",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("sles",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("amzn",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_AMZ +else ifeq ("debian",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_DEBIAN +else +subdir-ccflags-y += -DOS_NAME_UNKNOWN +endif + +subdir-ccflags-y += \ + -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ + -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) + +ifeq ($(OS_NAME),"opensuse-leap") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sled") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sles") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"ubuntu") +OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) +subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) +OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" +ifeq ($(OS_OEM),"oem") +subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM +endif +subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"rhel") +subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) + +ifeq ($(RHEL_MAJOR),7) +subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ + -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h +else ifeq ($(RHEL_MAJOR),8) +subdir-ccflags-y += -DOS_NAME_RHEL_8_X +endif +endif + +export OS_NAME OS_VERSION + +_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) +LINUX_SRCTREE_INCLUDE := \ + $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) + +LINUXINCLUDE := \ + -I$(src)/include \ + -I$(src)/include/kcl/header \ + -include $(src)/include/kcl/kcl_version.h \ + -include $(src)/include/rename_symbol.h \ + -include $(src)/amd/dkms/config/config.h \ + $(LINUX_SRCTREE_INCLUDE) \ + -I$(src)/include/uapi \ + $(USER_INCLUDE) + +export CONFIG_HSA_AMD=y +export CONFIG_DRM_TTM=m +export CONFIG_DRM_TTM_DMA_PAGE_POOL=y +export CONFIG_DRM_AMDGPU=m +export CONFIG_DRM_SCHED=m +export CONFIG_DRM_AMDGPU_CIK=y +export CONFIG_DRM_AMDGPU_SI=y +export CONFIG_DRM_AMDGPU_USERPTR=y +export CONFIG_DRM_AMD_DC=y + +subdir-ccflags-y += -DCONFIG_HSA_AMD +subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -Wno-error + +ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) +ifdef CONFIG_DEVICE_PRIVATE +export CONFIG_HSA_AMD_SVM=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +endif +endif + +export CONFIG_DRM_AMD_DC_HDCP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP + +ifeq (y,$(CONFIG_PCI_P2PDMA)) + ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) + export CONFIG_HSA_AMD_P2P=y + subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P + endif +endif + +# Trying to enable DCN2/3 with core2 optimizations will result in +# older versions of GCC hanging during building/installing. Check +# if the compiler is using core2 optimizations and only build DCN2/3 +# if core2 isn't in the compiler flags +ifndef CONFIG_ARM64 +ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) +export CONFIG_DRM_AMD_DC_FP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP +endif +endif + +# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) +# Upstream patches now uses gnu11/gnu99 as the default C standard version. +# However, gcc in legacy OS still uses gnu89, which will introduce a standard +# build gap leading to a DKMS build failure possibly. So add below check to +# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. +ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) +KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) +$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +endif + +include $(src)/amd/dkms/Makefile.drm_ttm_helper + +include $(src)/amd/dkms/Makefile.drm_buddy + +obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6153df061bcd8..59d814c49e8e3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,230 +1,40 @@ -ifeq ($(CC), gcc) -GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) -GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) -GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) -# CONFIG_GCC_VERSION returns x.xx.xx as the version format -GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) - -KERNEL_MAJ=$(VERSION) -KERNEL_PATCHLEVEL=$(PATCHLEVEL) -KERNEL_SUBLEVEL=$(SUBLEVEL) -KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) - -kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) - -ifdef CONFIG_CC_IS_GCC -ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) -$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") -$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") -endif -else -export CONFIG_CC_IS_GCC=y -export CONFIG_GCC_VERSION=$(GCCSTR) -$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") -endif - -endif - -include $(src)/amd/dkms/Makefile.compiler - -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifneq ($(call gcc-min-version, 40805), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif - -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - -ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) -$(error reservation_ww_class is missing. exit...) -endif - -DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) -DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) -ifeq ($(DRM_VER),) -DRM_VER = $(VERSION) -DRM_PATCH = $(PATCHLEVEL) -endif - -subdir-ccflags-y += \ - -DDRM_VER=$(DRM_VER) \ - -DDRM_PATCH=$(DRM_PATCH) \ - -DDRM_SUB="0" - -define get_rhel_version -printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) -endef -RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) -RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) - -ifneq (,$(RHEL_MAJOR)) -OS_NAME = "rhel" -OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" -else ifneq (,$(wildcard /etc/os-release)) -OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" -# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL -ifeq ("centos",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("rhel",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("linuxmint",$(OS_NAME)) -OS_NAME="ubuntu" -endif -OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +ifneq ($(KERNELRELEASE),) +include $(src)/amd/dkms/Kbuild else -OS_NAME = "unknown" -OS_VERSION = "0.0" -endif - -OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) - -ifeq ("ubuntu",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_UBUNTU -else ifeq ("rhel",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_RHEL -else ifeq ("steamos",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_STEAMOS -else ifeq ("sled",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("sles",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("amzn",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_AMZ -else ifeq ("debian",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_DEBIAN -else -subdir-ccflags-y += -DOS_NAME_UNKNOWN -endif - -subdir-ccflags-y += \ - -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ - -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) - -ifeq ($(OS_NAME),"opensuse-leap") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sled") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sles") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"ubuntu") -OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) -subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) -OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" -ifeq ($(OS_OEM),"oem") -subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM -endif -subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) -endif +KERNELVER := $(shell uname -r) +kernel_build_dir := /lib/modules/$(KERNELVER)/build +module_src_dir := $(CURDIR) +module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) +module_build_flags := +num_cpu_cores := $(shell which nproc > /dev/null && nproc || echo "1") +Q := @ -ifeq ($(OS_NAME),"rhel") -subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) - -ifeq ($(RHEL_MAJOR),7) -subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ - -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h -else ifeq ($(RHEL_MAJOR),8) -subdir-ccflags-y += -DOS_NAME_RHEL_8_X -endif +ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) +$(error "invalid kernel obj dir, is kernel-devel installed?") endif -export OS_NAME OS_VERSION - -_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) -LINUX_SRCTREE_INCLUDE := \ - $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) -USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) - -LINUXINCLUDE := \ - -I$(src)/include \ - -I$(src)/include/kcl/header \ - -include $(src)/include/kcl/kcl_version.h \ - -include $(src)/include/rename_symbol.h \ - -include $(src)/amd/dkms/config/config.h \ - $(LINUX_SRCTREE_INCLUDE) \ - -I$(src)/include/uapi \ - $(USER_INCLUDE) - -export CONFIG_HSA_AMD=y -export CONFIG_DRM_TTM=m -export CONFIG_DRM_TTM_DMA_PAGE_POOL=y -export CONFIG_DRM_AMDGPU=m -export CONFIG_DRM_SCHED=m -export CONFIG_DRM_AMDGPU_CIK=y -export CONFIG_DRM_AMDGPU_SI=y -export CONFIG_DRM_AMDGPU_USERPTR=y -export CONFIG_DRM_AMD_DC=y +.PHONY: modules pre-build clean -subdir-ccflags-y += -DCONFIG_HSA_AMD -subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC -subdir-ccflags-y += -Wno-error +include $(kernel_build_dir)/include/config/auto.conf -ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) -ifdef CONFIG_DEVICE_PRIVATE -export CONFIG_HSA_AMD_SVM=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +ifneq ($(CONFIG_CC_IS_CLANG),) +module_build_flags += CC=clang endif +ifneq ($(CONFIG_LD_IS_LLD),) +module_build_flags += LD=ld.lld endif -export CONFIG_DRM_AMD_DC_HDCP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +modules:pre-build + $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ + TTM_NAME=amdttm \ + SCHED_NAME=amd-sched \ + -C $(kernel_build_dir) \ + M=$(module_build_dir) $(module_build_flags) + $(Q)amd/dkms/post-build.sh $(module_build_dir) -ifeq (y,$(CONFIG_PCI_P2PDMA)) - ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) - export CONFIG_HSA_AMD_P2P=y - subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P - endif -endif - -# Trying to enable DCN2/3 with core2 optimizations will result in -# older versions of GCC hanging during building/installing. Check -# if the compiler is using core2 optimizations and only build DCN2/3 -# if core2 isn't in the compiler flags -ifndef CONFIG_ARM64 -ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_FP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP -endif -endif +pre-build: + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) -# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) -# Upstream patches now uses gnu11/gnu99 as the default C standard version. -# However, gcc in legacy OS still uses gnu89, which will introduce a standard -# build gap leading to a DKMS build failure possibly. So add below check to -# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. -ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) -KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) -$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +clean: + $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean endif - -include $(src)/amd/dkms/Makefile.drm_ttm_helper - -include $(src)/amd/dkms/Makefile.drm_buddy - -obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index ceef7d15a7c26..7d262536848b6 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,9 +1,6 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -module_build_dir="$(mktemp -ut amd.XXXXXXXX)" -PRE_BUILD="amd/dkms/pre-build.sh $kernelver $dkms_tree $module $module_version $module_build_dir" -POST_BUILD="amd/dkms/post-build.sh $module_build_dir" # not all OS supports weak module updates NO_WEAK_MODULES="yes" @@ -38,17 +35,5 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -num_cpu_cores() -{ - if [ -x /usr/bin/nproc ]; then - nproc - else - echo "1" - fi -} - -MAKE[0]=". $module_build_dir/.env && make -j$(num_cpu_cores) KERNELRELEASE=$kernelver \ - TTM_NAME=${BUILT_MODULE_NAME[1]} \ - SCHED_NAME=${BUILT_MODULE_NAME[3]} \ - -C $kernel_source_dir \ - M=$module_build_dir" +MAKE[0]="'make' KERNELVER=$kernelver" + diff --git a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot deleted file mode 100644 index 5c8c78df4e932..0000000000000 --- a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot +++ /dev/null @@ -1,41 +0,0 @@ -ifneq ($(KERNELRELEASE),) -include $(src)/amd/dkms/Makefile -else -KERNELVER := $(shell uname -r) -kernel_build_dir := /lib/modules/$(KERNELVER)/build -PACKAGE_NAME := $(shell sed -n '/PACKAGE_NAME/s|.*=||p' amd/dkms/dkms.conf) -PACKAGE_VERSION := $(shell sed -n '/PACKAGE_VERSION/s|.*=||p' amd/dkms/dkms.conf) -module_src_dir := $(CURDIR) -module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) -module_build_flags := -num_cpu_cores := $(shell nproc) -Q := @ - -ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) -$(error "invalid kernel obj dir, is kernel-devel installed?") -endif - -.PHONY: modules pre-build - -include $(kernel_build_dir)/include/config/auto.conf - -ifneq ($(CONFIG_CC_IS_CLANG),) -module_build_flags += CC=clang -endif -ifneq ($(CONFIG_LD_IS_LLD),) -module_build_flags += LD=ld.lld -endif - -modules:pre-build - $(Q)make -j$(num_cpu_cores) KERNELRELEASE=$(KERNELVER) \ - TTM_NAME=amdttm \ - SCHED_NAME=amd-sched \ - -C $(kernel_build_dir) \ - M=$(module_build_dir) $(module_build_flags) - $(Q)unlink $(module_build_dir) - -pre-build: - $(Q)cp -f amd/dkms/oot/pre-build.sh amd/dkms - $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(PACKAGE_NAME) $(PACKAGE_VERSION) $(module_build_dir) - -endif diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec index 5f00c10afe2db..79795b24bb7c8 100644 --- a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -27,7 +27,7 @@ The AMD display driver kernel module in DKMS format for AMD graphics S/W %build pushd src -%{__make} -f amd/dkms/oot/Makefile.oot KERNELVER=%(uname -r) +%{__make} KERNELVER=%(uname -r) popd %install diff --git a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh deleted file mode 100644 index 7cb58df401aa8..0000000000000 --- a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh +++ /dev/null @@ -1,91 +0,0 @@ -#!/bin/bash - -KCL="amd/amdkcl" -INC="include" -SRC="amd/dkms" - -KERNELVER=$1 -DKMS_TREE=$2 -MODULE=$3 -MODULE_VERSION=$4 -MODULE_BUILD_DIR=$5 -KERNELVER_BASE=${KERNELVER%%-*} - -version_lt () { - newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) - [ "$KERNELVER_BASE" != "$newest" ] -} - -version_ge () { - newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) - [ "$KERNELVER_BASE" = "$newest" ] -} - -version_gt () { - oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) - [ "$KERNELVER_BASE" != "$oldest" ] -} - -version_le () { - oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) - [ "$KERNELVER_BASE" = "$oldest" ] -} - -source $KCL/files - -sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ - -e '/dma_resv_lockdep/,/subsys_initcall/d' \ - -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ - -e '$a\#endif' $KCL/dma-buf/dma-resv.c -sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' \ - -e '/struct dma_resv_iter {/, /}/d' \ - -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h - -# add amd prefix to exported symbols -for file in $FILES; do - awk -F'[()]' '/EXPORT_SYMBOL/ { - print "#define "$2" amd"$2" //"$0 - }' $file | sort -u >>$INC/rename_symbol.h -done - -# rename CONFIG_xxx to CONFIG_xxx_AMDKCL -# otherwise kernel config would override dkms package config -AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') -TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) -SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) -for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do - for file in $(grep -rl $config ./); do - sed -i "s/\<$config\>/&_AMDKCL/" $file - done - sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile -done - -export KERNELVER -ln -s $DKMS_TREE $MODULE_BUILD_DIR - -# Enable gcc-toolset for kernels that are built with non-default compiler -# perform this check only when permissions allow -if [[ -d /opt/rh && `id -u` -eq 0 ]]; then - for f in $(find /opt/rh -type f -a -name gcc); do - [[ -f /boot/config-$KERNELVER ]] || continue - config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) - IFS='.' read -ra ver <<<$($f -dumpfullversion) - gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) - if [[ "$config_gcc_version" = "$gcc_version" ]]; then - . ${f%/*}/../../../enable - break - fi - done -fi -echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env - -(cd $SRC && ./configure) - -# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o -# for kernel version < 5.3 -if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then - for file in $(grep -rl 'CFLAGS_' amd/display/); do - sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file - done -fi diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ec0c41cd4411e..7f3e5f9323673 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,9 +6,7 @@ SRC="amd/dkms" KERNELVER=$1 DKMS_TREE=$2 -MODULE=$3 -MODULE_VERSION=$4 -MODULE_BUILD_DIR=$5 +MODULE_BUILD_DIR=$3 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -58,14 +56,15 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do for file in $(grep -rl $config ./); do sed -i "s/\<$config\>/&_AMDKCL/" $file done - sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild done export KERNELVER -ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR +ln -s $DKMS_TREE $MODULE_BUILD_DIR # Enable gcc-toolset for kernels that are built with non-default compiler -if [[ -d /opt/rh ]]; then +# perform this check only when permissions allow +if [[ -d /opt/rh && `id -u` -eq 0 ]]; then for f in $(find /opt/rh -type f -a -name gcc); do [[ -f /boot/config-$KERNELVER ]] || continue config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) From 2d3a64fbf1c20b5da53459b1dddfce9752683450 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 23 Dec 2024 11:01:06 +0800 Subject: [PATCH 1387/2070] drm/amdkcl: fake perfmon_capable() if not define macro CAP_PERFMON It's caused by the following commit:b58289f0 "Add kfd_ioctl_profiler to contain profiler kernel driver changes" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_capability.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h index 52448ad625f96..7373bcf3ac8f4 100644 --- a/include/kcl/kcl_capability.h +++ b/include/kcl/kcl_capability.h @@ -30,6 +30,11 @@ #ifndef CAP_PERFMON #define CAP_PERFMON 38 + +static inline bool perfmon_capable(void) +{ + return capable(CAP_PERFMON) || capable(CAP_SYS_ADMIN); +} #endif #endif From 730eaceeac706b5c67898b9b3f5e579351a301d0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 3 Dec 2024 13:55:07 +0800 Subject: [PATCH 1388/2070] drm/amdkcl: redefine KCL_DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 12 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--- drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 26 ------------- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 ------------------- include/kcl/kcl_debugfs.h | 22 ++++++++++- 11 files changed, 22 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index e9c981e7d348d..9b31804491500 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -968,11 +968,7 @@ static const struct file_operations aca_ue_dump_debug_fops = { .release = single_release, }; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); -#endif #endif void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 51d370d6e46d5..6d67492cd88c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1799,14 +1799,12 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib); DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark, "%lld\n"); -#endif static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, struct dma_fence **fences) @@ -2020,13 +2018,11 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) return ret; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, amdgpu_debugfs_ib_preempt, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, amdgpu_debugfs_sclk_set, "%llu\n"); -#endif int amdgpu_debugfs_init(struct amdgpu_device *adev) { @@ -2037,7 +2033,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) if (!debugfs_initialized()) return 0; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_x32("amdgpu_smu_debug", 0600, root, &adev->pm.smu_debug_mask); @@ -2056,7 +2051,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) "unable to create amdgpu_set_sclk debugsfs file\n"); return PTR_ERR(ent); } -#endif /* Register debugfs entries for amdgpu_ttm */ amdgpu_ttm_debugfs_init(adev); @@ -2113,14 +2107,12 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) amdgpu_fw_attestation_debugfs_init(adev); amdgpu_psp_debugfs_init(adev); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_evict_vram", 0400, root, adev, &amdgpu_evict_vram_fops); debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev, &amdgpu_evict_gtt_fops); debugfs_create_file("amdgpu_benchmark", 0200, root, adev, &amdgpu_benchmark_fops); -#endif debugfs_create_file("amdgpu_test_ib", 0400, root, adev, &amdgpu_debugfs_test_ib_fops); debugfs_create_file("amdgpu_vm_info", 0444, root, adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 4c91cffee0431..cab3196a87fb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2553,15 +2553,9 @@ static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, amdgpu_debugfs_gfx_sched_mask_get, amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, - amdgpu_debugfs_gfx_sched_mask_get, - amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); -#endif #endif @@ -2630,15 +2624,9 @@ static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, amdgpu_debugfs_compute_sched_mask_get, amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, - amdgpu_debugfs_compute_sched_mask_get, - amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); -#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 78a89601e4e5e..3ca03b5e0f913 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -613,11 +613,7 @@ static const struct file_operations mca_ue_dump_debug_fops = { .release = single_release, }; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); -#endif #endif void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index e61371de6a75b..5de786551aaac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -681,7 +681,6 @@ static const struct file_operations amdgpu_debugfs_mqd_fops = { .llseek = default_llseek }; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int amdgpu_debugfs_ring_error(void *data, u64 val) { struct amdgpu_ring *ring = data; @@ -693,7 +692,6 @@ static int amdgpu_debugfs_ring_error(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, amdgpu_debugfs_ring_error, "%lld\n"); #endif -#endif void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) @@ -720,12 +718,10 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, ring->mqd_size); } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE sprintf(name, "amdgpu_error_%s", ring->name); debugfs_create_file(name, 0200, root, ring, &amdgpu_debugfs_error_fops); #endif -#endif } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 546a0c8f8c648..321310ba2c08e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -434,15 +434,9 @@ static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, amdgpu_debugfs_sdma_sched_mask_get, amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, - amdgpu_debugfs_sdma_sched_mask_get, - amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); -#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index c3f00b9285c21..75ae9b429420e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1436,15 +1436,10 @@ static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) *val = mask; return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE + DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, amdgpu_debugfs_vcn_sched_mask_get, amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, - amdgpu_debugfs_vcn_sched_mask_get, - amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); -#endif #endif void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c index def9db4463a22..919f869e81857 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c @@ -14,7 +14,7 @@ #include #include -#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_XSIGNED /* Copied from fs/libfs.c */ struct simple_attr { int (*get)(void *, u64 *); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index d3dbd3911ad21..1d57076153c17 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -576,7 +576,6 @@ static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, return result; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int dp_lttpr_status_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -611,7 +610,6 @@ static int dp_lttpr_status_show(struct seq_file *m, void *unused) seq_puts(m, "\n"); return 0; } -#endif static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) @@ -2984,9 +2982,7 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); -#endif DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); @@ -3109,9 +3105,7 @@ static const struct { } dp_debugfs_entries[] = { {"link_settings", &dp_link_settings_debugfs_fops}, {"phy_settings", &dp_phy_settings_debugfs_fop}, -#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"lttpr_status", &dp_lttpr_status_fops}, -#endif {"test_pattern", &dp_phy_test_pattern_fops}, {"hdcp_sink_capability", &hdcp_sink_capability_fops}, {"sdp_message", &sdp_message_fops}, @@ -3168,10 +3162,8 @@ static int force_yuv420_output_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, force_yuv420_output_set, "%llu\n"); -#endif /* * Read Replay state @@ -3434,7 +3426,6 @@ static int dmcub_trace_event_state_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, dmcub_trace_event_state_set, "%llu\n"); @@ -3452,7 +3443,6 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); -#endif DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, ips_residency_cntl_set, "%llu\n"); @@ -3465,9 +3455,7 @@ static const struct { char *name; const struct file_operations *fops; } connector_debugfs_entries[] = { -#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"force_yuv420_output", &force_yuv420_output_fops}, -#endif {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, {"internal_display", &internal_display_fops}, {"odm_combine_segments", &odm_combine_segments_fops} @@ -3639,7 +3627,6 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) } } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); @@ -3661,7 +3648,6 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); } -#endif for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { debugfs_create_file(connector_debugfs_entries[i].name, @@ -4027,7 +4013,6 @@ static int mst_topo_show(struct seq_file *m, void *unused) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Sets trigger hpd for MST topologies. * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. @@ -4101,7 +4086,6 @@ static int trigger_hpd_mst_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, trigger_hpd_mst_set, "%llu\n"); -#endif /* * Sets the force_timing_sync debug option from the given string. @@ -4132,13 +4116,9 @@ static int force_timing_sync_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, force_timing_sync_set, "%llu\n"); -#endif - -#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Disables all HPD and HPD RX interrupt handling in the * driver when set to 1. Default is 0. @@ -4168,7 +4148,6 @@ static int disable_hpd_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); -#endif /* * Prints hardware capabilities. These are used for IGT testing. @@ -4278,11 +4257,9 @@ static int visual_confirm_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(mst_topo); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); - /* * Sets the DC skip_detection_link_training debug option from the given string. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training @@ -4315,7 +4292,6 @@ static int skip_detection_link_training_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, skip_detection_link_training_get, skip_detection_link_training_set, "%llu\n"); -#endif /* * Dumps the DCC_EN bit for each pipe. @@ -4403,7 +4379,6 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, &dp_set_mst_en_for_sst_ops); debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, @@ -4448,5 +4423,4 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev, &ips_residency_fops); } -#endif } diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 23fdf43218190..00d8a273b46dd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4276,7 +4276,6 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) return smu_phase_det_enable(smu, !!val); } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE #define DEBUGFS_PHASE_DET_FOPS(param) \ static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ { \ @@ -4303,34 +4302,6 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ smu_phase_det_fops_##param##_get, \ smu_phase_det_fops_##param##_set, "%llu\n") -#else -#define DEBUGFS_PHASE_DET_FOPS(param) \ - static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ - { \ - struct smu_context *smu = (struct smu_context *)data; \ - int r; \ - u32 v; \ - \ - r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ - *val = v; \ - return r; \ - } \ - \ - static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ - { \ - struct smu_context *smu = (struct smu_context *)data; \ - struct amdgpu_device *adev = smu->adev; \ - \ - if (amdgpu_in_reset(adev) || adev->in_suspend) \ - return -EPERM; \ - \ - return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ - (u32)val); \ - } \ - DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_##param, \ - smu_phase_det_fops_##param##_get, \ - smu_phase_det_fops_##param##_set, "%llu\n") -#endif DEBUGFS_PHASE_DET_FOPS(LO_FREQ); DEBUGFS_PHASE_DET_FOPS(HI_FREQ); @@ -4338,21 +4309,11 @@ DEBUGFS_PHASE_DET_FOPS(THRESH); DEBUGFS_PHASE_DET_FOPS(ALPHA); DEBUGFS_PHASE_DET_FOPS(HYST); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, - smu_phase_det_debugfs_enable, "%llu\n"); -#endif -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_res, - smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); -#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h index ca6a8d391da78..75a68ada50ccc 100644 --- a/include/kcl/kcl_debugfs.h +++ b/include/kcl/kcl_debugfs.h @@ -19,8 +19,10 @@ #include #include -#if defined(DEFINE_DEBUGFS_ATTRIBUTE) && !defined(DEFINE_DEBUGFS_ATTRIBUTE_SIGNED) -#define KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#if !defined(DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED) + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE +#define KCL_FAKE_DEBUGFS_ATTRIBUTE_XSIGNED #define DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, __is_signed) \ static int __fops ## _open(struct inode *inode, struct file *file) \ { \ @@ -36,6 +38,10 @@ static const struct file_operations __fops = { \ .llseek = no_llseek, \ } +#undef DEFINE_DEBUGFS_ATTRIBUTE +#define DEFINE_DEBUGFS_ATTRIBUTE(__fops, __get, __set, __fmt) \ + DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false) + #define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) @@ -51,6 +57,18 @@ static inline ssize_t debugfs_attr_write_signed(struct file *file, } #endif /* CONFIG_DEBUG_FS */ +#else +#define DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SIMPLE_ATTRIBUTE +#define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED DEFINE_SIMPLE_ATTRIBUTE +static inline struct dentry *debugfs_create_file_unsafe(const char *name, + umode_t mode, struct dentry *parent, + void *data, + const struct file_operations *fops) +{ + return ERR_PTR(-ENODEV); +} +#endif /* DEFINE_DEBUGFS_ATTRIBUTE */ + #endif /* DEFINE_DEBUGFS_ATTRIBUTE_SIGNED */ #endif From 158d18f48f7f21cd29ae5d8f43a4d0f12c8d70a1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Dec 2024 15:25:04 +0800 Subject: [PATCH 1389/2070] drm/amdkcl: split previous sanity check to Makefile Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 12 ------------ drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 6153df061bcd8..5af98db3e5580 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -34,18 +34,6 @@ $(error "The GCC is too old for this kernel, please update the GCC to higher tha endif endif -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 59d814c49e8e3..332b2796f0ff1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -17,6 +17,18 @@ endif include $(kernel_build_dir)/include/config/auto.conf +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU_AMDKCL)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + ifneq ($(CONFIG_CC_IS_CLANG),) module_build_flags += CC=clang endif From a2426b5a1d4333e60ce629d9274f7651b58a14f6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Dec 2024 15:25:58 +0800 Subject: [PATCH 1390/2070] drm/amdkcl: Set modules as default target Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 332b2796f0ff1..46c5694210b41 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -14,6 +14,7 @@ $(error "invalid kernel obj dir, is kernel-devel installed?") endif .PHONY: modules pre-build clean +modules: include $(kernel_build_dir)/include/config/auto.conf From c02b4b19ecf05221f9ad6960cfda66093435804a Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 30 Dec 2024 11:13:46 +0800 Subject: [PATCH 1391/2070] drm/amdkcl: Remove redundant DEFINE_DEBUGFS_ATTRIBUTE macro define The legacy definition of DEFINE_DEBUGFS_ATTRIBUTE is semantically equivalent to DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false), so remove unnecessary redefinitions. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_debugfs.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h index 75a68ada50ccc..f9444191d7cec 100644 --- a/include/kcl/kcl_debugfs.h +++ b/include/kcl/kcl_debugfs.h @@ -38,10 +38,6 @@ static const struct file_operations __fops = { \ .llseek = no_llseek, \ } -#undef DEFINE_DEBUGFS_ATTRIBUTE -#define DEFINE_DEBUGFS_ATTRIBUTE(__fops, __get, __set, __fmt) \ - DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false) - #define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) From 1747aa4848fbe21186553ff4d4de3e648d7d793c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 30 Dec 2024 10:59:59 +0800 Subject: [PATCH 1392/2070] drm/amdkcl: split kcl config sanity check to Makefile Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 8 -------- drivers/gpu/drm/amd/dkms/Makefile | 11 +++++++++-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 5af98db3e5580..0821ba268d9a4 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -36,14 +36,6 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - -ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) -$(error reservation_ww_class is missing. exit...) -endif - DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 46c5694210b41..abb5fa4da4920 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -13,7 +13,7 @@ ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) $(error "invalid kernel obj dir, is kernel-devel installed?") endif -.PHONY: modules pre-build clean +.PHONY: modules sanity-check pre-build clean modules: include $(kernel_build_dir)/include/config/auto.conf @@ -37,7 +37,10 @@ ifneq ($(CONFIG_LD_IS_LLD),) module_build_flags += LD=ld.lld endif -modules:pre-build +config-file ?= amd/dkms/config/config.h +KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") + +modules: sanity-check $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ TTM_NAME=amdttm \ SCHED_NAME=amd-sched \ @@ -45,6 +48,10 @@ modules:pre-build M=$(module_build_dir) $(module_build_flags) $(Q)amd/dkms/post-build.sh $(module_build_dir) +sanity-check: pre-build $(config-file) + $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) + $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) + pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) From 1a8b2b365a99001430c634fa79a9c944b3769798 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Jan 2025 13:28:14 +0800 Subject: [PATCH 1393/2070] drm/amdkcl: update header macro to avoid repeat The macro is repeated by kcl/backport/kcl_drm_drv.h, so modify the header macro. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/backport/kcl_drm_fbdev_ttm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h index 03ddc7699ddb1..5d504414c4478 100644 --- a/include/kcl/backport/kcl_drm_fbdev_ttm.h +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -1,5 +1,5 @@ -#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H_ -#define __KCL_BACKPORT_KCL_DRM_DRV_H__ +#ifndef __KCL_BACKPORT_KCL_DRM_FBDEV_TTM_H__ +#define __KCL_BACKPORT_KCL_DRM_FBDEV_TTM_H__ #include #include From a5dad9b613385387794f8f8507362fba17125c9e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Jan 2025 13:39:00 +0800 Subject: [PATCH 1394/2070] drm/amdkcl: initiate return result for non-upsteam In special case, uninitialized result will cause error, so fix it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 037e9aea2b691..b1105f1f15f17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -52,16 +52,16 @@ void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - int r; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + int r = 0; if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); - if (r) - return r; + if (r) + return r; vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; } From 6afeeba40ced43712aeac3c6ea4a76d1aba67a6b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 17 Dec 2024 16:04:14 -0500 Subject: [PATCH 1395/2070] drm/kfd: use support format check flag kfd_pc_sample_info flag is for OUT only, so user input format flag should not be used to check condition. -v2: fix typo Signed-off-by: James Zhu Reviewed-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 603e557c986b4..80a185ba10b60 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -285,12 +285,6 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return -EFAULT; } - if (user_info.flags & KFD_IOCTL_PCS_FLAG_POWER_OF_2 && - user_info.interval & (user_info.interval - 1)) { - pr_debug("Sampling interval's power is unmatched!"); - return -EINVAL; - } - for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version && user_info.method == supported_formats[i].sample_info->method @@ -308,6 +302,12 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return -EOPNOTSUPP; } + if (supported_format->flags == KFD_IOCTL_PCS_FLAG_POWER_OF_2 && + user_info.interval & (user_info.interval - 1)) { + pr_debug("Sampling interval's power is unmatched!"); + return -EINVAL; + } + mutex_lock(&pdd->dev->pcs_data.mutex); if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, From 568e9fc496edcba35e3e23bd7c8355c1a8363643 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 09:34:59 -0400 Subject: [PATCH 1396/2070] drm/amdkfd: refactor for adding stochastic PC sampling Share sampling_idr to support both Host Trap and Stochastic PC sampling running simultaneously. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Acked-by: Shweta Khatri --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +-- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 32 ++++++++++---------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++--- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 1be49ac37220e..0ac215d723a0b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -621,12 +621,12 @@ static void kfd_smi_init(struct kfd_node *dev) static void kfd_pc_sampling_init(struct kfd_node *dev) { mutex_init(&dev->pcs_data.mutex); - idr_init_base(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, 1); + idr_init_base(&dev->pcs_data.sampling_idr, 1); } static void kfd_pc_sampling_exit(struct kfd_node *dev) { - idr_destroy(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr); + idr_destroy(&dev->pcs_data.sampling_idr); mutex_destroy(&dev->pcs_data.mutex); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 80a185ba10b60..7a78592fe450a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -85,14 +85,14 @@ static int kfd_pc_sample_thread(void *param) node->kfd2kgd->override_core_cg(adev, 1, inst); while (!kthread_should_stop() && - !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + !signal_pending(node->pcs_data.hosttrap_entry.pc_sample_thread)) { if (!need_wait) { next_trap_time = ktime_add_us(ktime_get_raw(), timeout); for_each_inst(inst, node->xcc_mask) { node->kfd2kgd->trigger_pc_sample_trap(adev, node->vm_info.last_vmid_kfd, - &node->pcs_data.hosttrap_entry.base.target_simd, - &node->pcs_data.hosttrap_entry.base.target_wave_slot, + &node->pcs_data.hosttrap_entry.target_simd, + &node->pcs_data.hosttrap_entry.target_wave_slot, node->pcs_data.hosttrap_entry.base.pc_sample_info.method, inst); } @@ -118,9 +118,9 @@ static int kfd_pc_sample_thread(void *param) for_each_inst(inst, node->xcc_mask) node->kfd2kgd->override_core_cg(adev, 0, inst); - node->pcs_data.hosttrap_entry.base.target_simd = 0; - node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; - node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + node->pcs_data.hosttrap_entry.target_simd = 0; + node->pcs_data.hosttrap_entry.target_wave_slot = 0; + node->pcs_data.hosttrap_entry.pc_sample_thread = NULL; return 0; } @@ -131,12 +131,12 @@ static int kfd_pc_sample_thread_start(struct kfd_node *node) int ret = 0; snprintf(thread_name, 16, "pcs_%d", node->adev->ddev.render->index); - node->pcs_data.hosttrap_entry.base.pc_sample_thread = + node->pcs_data.hosttrap_entry.pc_sample_thread = kthread_run(kfd_pc_sample_thread, node, thread_name); - if (IS_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { - ret = PTR_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread); - node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + if (IS_ERR(node->pcs_data.hosttrap_entry.pc_sample_thread)) { + ret = PTR_ERR(node->pcs_data.hosttrap_entry.pc_sample_thread); + node->pcs_data.hosttrap_entry.pc_sample_thread = NULL; pr_debug("Failed to create pc sample thread for %s with ret = %d.", thread_name, ret); } @@ -231,7 +231,7 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, while (pc_sampling_start) { /* true means pc_sample_thread stop is in progress */ - if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { usleep_range(1000, 2000); } else { ret = kfd_pc_sample_thread_start(pdd->dev); @@ -261,7 +261,7 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); if (pc_sampling_stop) - kthread_stop(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread); + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); return 0; } @@ -325,7 +325,7 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return -ENOMEM; } - i = idr_alloc_cyclic(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + i = idr_alloc_cyclic(&pdd->dev->pcs_data.sampling_idr, pcs_entry, 1, 0, GFP_KERNEL); if (i < 0) { mutex_unlock(&pdd->dev->pcs_data.mutex); @@ -364,7 +364,7 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); pdd->dev->pcs_data.hosttrap_entry.base.use_count--; - idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); + idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, @@ -383,7 +383,7 @@ void kfd_pc_sample_release(struct kfd_process_device *pdd) uint32_t id; /* force to release all PC sampling task for this process */ - idp = &pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr; + idp = &pdd->dev->pcs_data.sampling_idr; do { pcs_entry = NULL; mutex_lock(&pdd->dev->pcs_data.mutex); @@ -410,7 +410,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, args->op != KFD_IOCTL_PCS_OP_CREATE) { mutex_lock(&pdd->dev->pcs_data.mutex); - pcs_entry = idr_find(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + pcs_entry = idr_find(&pdd->dev->pcs_data.sampling_idr, args->trace_id); mutex_unlock(&pdd->dev->pcs_data.mutex); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 36f113a7ea30d..234e51310bcce 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -296,20 +296,20 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ uint32_t active_count; /* Num of active sessions */ - uint32_t target_simd; /* target simd for trap */ - uint32_t target_wave_slot; /* target wave slot for trap */ - struct idr pc_sampling_idr; - struct task_struct *pc_sample_thread; struct kfd_pc_sample_info pc_sample_info; }; struct kfd_dev_pcs_hosttrap { struct kfd_dev_pc_sampling_data base; + uint32_t target_simd; /* target simd for trap */ + uint32_t target_wave_slot; /* target wave slot for trap */ + struct task_struct *pc_sample_thread; }; /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; + struct idr sampling_idr; struct kfd_dev_pcs_hosttrap hosttrap_entry; }; From f334e561d76dec74ab6258bbec148bf569728b67 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 09:49:45 -0400 Subject: [PATCH 1397/2070] drm/amdkfd: add interface setup_stoch_sampling To support gfx943 stochastic PC sampling. -v3: use compute_vmid_bitmap instead of hardcode -v7: move interval conversion into soc specified code Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Reviewed-by: Shweta Khatri --- .../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 27 ++++++++++++++++++- .../gpu/drm/amd/include/kgd_kfd_interface.h | 6 +++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index c1c184babcaf3..a577e1ff00401 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -550,6 +550,30 @@ static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, target_simd, target_wave_slot, method, inst); } +static uint32_t kgd_v9_4_3_setup_stoch_sampling(struct amdgpu_device *adev, + uint32_t compute_vmid_bitmap, + bool enable, + enum kfd_ioctl_pc_sample_type type, + uint64_t intval, + uint32_t inst) +{ + uint32_t value = 0; + + /* turn on all VMID for this instance */ + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, VMID_MASK, compute_vmid_bitmap); + + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, COUNT_INTVAL, ffs(intval >> 9)); + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, COUNT_SEL, type - 1); + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, ENABLE, enable); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), regSQ_PERF_SNAPSHOT_CTRL, value); + mutex_unlock(&adev->grbm_idx_mutex); + + return 0; +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -587,5 +611,6 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, - .override_core_cg = kgd_gfx_v9_4_3_override_core_cg + .override_core_cg = kgd_gfx_v9_4_3_override_core_cg, + .setup_stoch_sampling = kgd_v9_4_3_setup_stoch_sampling, }; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 26f5a542877cc..df5b578a5e6b1 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -349,6 +349,12 @@ struct kfd2kgd_calls { void (*override_core_cg)(struct amdgpu_device *adev, uint32_t value, uint32_t inst); + uint32_t (*setup_stoch_sampling)(struct amdgpu_device *adev, + uint32_t compute_vmid_bitmap, + bool enable, + enum kfd_ioctl_pc_sample_type type, + uint64_t intval, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From eb4379810187fbaccb1d0adfadbb83ae58e3602b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:01:57 -0400 Subject: [PATCH 1398/2070] drm/amdkfd: add stochastic PC sampling support Add stochastic PC sampling support. -v3: use compute_vmid_bitmap instead of hardcode -v4: use clock cycles instead of the exponent of clock cycle -v5: use KFD_IOCTL_PCS_FLAG_POWER_OF_2 subtract 8 before pass clock cycle exponent value to register -v6: use shift instead of subtract -v7: move interval conversion into soc specified code Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Acked-by: Shweta Khatri --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 173 ++++++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 + 2 files changed, 137 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 7a78592fe450a..e8addf8817d9d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -27,6 +27,7 @@ #include "kfd_debug.h" #include "kfd_device_queue_manager.h" +#include /* * PC Sampling revision change log * @@ -45,6 +46,10 @@ struct supported_pc_sample_info { const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; +const struct kfd_pc_sample_info sample_info_stoch_cycle_9_4_3 = { + 0, 256, (1ULL << 31), KFD_IOCTL_PCS_FLAG_POWER_OF_2, + KFD_IOCTL_PCS_METHOD_STOCHASTIC, KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES }; + struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, @@ -169,14 +174,30 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, ret = 0; mutex_lock(&pdd->dev->pcs_data.mutex); if (user_args->flags != KFD_IOCTL_PCS_QUERY_TYPE_FULL && - pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + (pdd->dev->pcs_data.hosttrap_entry.base.use_count || + pdd->dev->pcs_data.stoch_entry.base.use_count)) { + user_args->num_sample_info = 0; + /* If we already have a session, restrict returned list to current method */ - user_args->num_sample_info = 1; + if (pdd->dev->pcs_data.stoch_entry.base.use_count) { + user_args->num_sample_info++; + if (user_args->sample_info_ptr && + user_args->num_sample_info <= user_num_sample_info) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + user_args->sample_info_ptr += sizeof(struct kfd_pc_sample_info); + } + } - if (user_args->sample_info_ptr) - ret = copy_to_user((void __user *) user_args->sample_info_ptr, - &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, - sizeof(struct kfd_pc_sample_info)); + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + user_args->num_sample_info++; + if (user_args->sample_info_ptr && + user_args->num_sample_info <= user_num_sample_info) + ret |= copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + } mutex_unlock(&pdd->dev->pcs_data.mutex); return ret ? -EFAULT : 0; } @@ -220,25 +241,47 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, pcs_entry->enabled = true; mutex_lock(&pdd->dev->pcs_data.mutex); - kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, - pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, true); + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, true); + + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_start = true; - if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) - pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + if (!pdd->dev->pcs_data.stoch_entry.base.active_count) + pc_sampling_start = true; - pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + pdd->dev->pcs_data.stoch_entry.base.active_count++; + } mutex_unlock(&pdd->dev->pcs_data.mutex); while (pc_sampling_start) { - /* true means pc_sample_thread stop is in progress */ - if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { - usleep_range(1000, 2000); - } else { - ret = kfd_pc_sample_thread_start(pdd->dev); + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + /* true means pc_sample_thread stop is in progress */ + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { + usleep_range(1000, 2000); + } else { + ret = kfd_pc_sample_thread_start(pdd->dev); + break; + } + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + struct amdgpu_device *adev = pdd->dev->adev; + struct kfd_node *node = pdd->dev; + uint64_t interval; + uint32_t inst; + + interval = node->pcs_data.stoch_entry.base.pc_sample_info.interval; + if (pdd->dev->kfd2kgd->setup_stoch_sampling) + for_each_inst(inst, node->xcc_mask) + pdd->dev->kfd2kgd->setup_stoch_sampling(adev, + node->compute_vmid_bitmap, true, + node->pcs_data.stoch_entry.base.pc_sample_info.type, + interval, + inst); break; } } - return ret; } @@ -249,19 +292,38 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, pcs_entry->enabled = false; mutex_lock(&pdd->dev->pcs_data.mutex); - pdd->dev->pcs_data.hosttrap_entry.base.active_count--; - if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) - pc_sampling_stop = true; - + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + pdd->dev->pcs_data.hosttrap_entry.base.active_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_stop = true; + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + pdd->dev->pcs_data.stoch_entry.base.active_count--; + if (!pdd->dev->pcs_data.stoch_entry.base.active_count) + pc_sampling_stop = true; + } mutex_unlock(&pdd->dev->pcs_data.mutex); - kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, - pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, false); remap_queue(pdd->dev->dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); - if (pc_sampling_stop) - kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); + if (pc_sampling_stop) { + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + struct amdgpu_device *adev = pdd->dev->adev; + struct kfd_node *node = pdd->dev; + uint32_t inst; + + if (pdd->dev->kfd2kgd->setup_stoch_sampling) { + for_each_inst(inst, node->xcc_mask) + pdd->dev->kfd2kgd->setup_stoch_sampling(adev, + node->compute_vmid_bitmap, false, + node->pcs_data.stoch_entry.base.pc_sample_info.type, + 0, inst); + } + } + } return 0; } @@ -309,14 +371,26 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, } mutex_lock(&pdd->dev->pcs_data.mutex); - if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && - memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, - &user_info, sizeof(user_info))) { - ret = copy_to_user((void __user *) user_args->sample_info_ptr, - &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, - sizeof(struct kfd_pc_sample_info)); - mutex_unlock(&pdd->dev->pcs_data.mutex); - return ret ? -EFAULT : -EEXIST; + if (supported_format->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + if (pdd->dev->pcs_data.stoch_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } } pcs_entry = kzalloc(sizeof(*pcs_entry), GFP_KERNEL); @@ -333,13 +407,20 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return i; } - if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) - pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + if (supported_format->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + pdd->dev->pcs_data.hosttrap_entry.base.use_count++; + } else if (supported_format->method == KFD_IOCTL_PCS_METHOD_STOCHASTIC) { + if (!pdd->dev->pcs_data.stoch_entry.base.use_count) + pdd->dev->pcs_data.stoch_entry.base.pc_sample_info = user_info; + pdd->dev->pcs_data.stoch_entry.base.use_count++; + } - pdd->dev->pcs_data.hosttrap_entry.base.use_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); pcs_entry->pdd = pdd; + pcs_entry->method = supported_format->method; user_args->trace_id = (uint32_t)i; /* @@ -350,7 +431,8 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, kfd_dbg_enable_ttmp_setup(pdd->process); pdd->process->pc_sampling_ref++; - pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x method = %d on gpu 0x%x", + pcs_entry, i, pcs_entry->method, pdd->dev->id); return 0; } @@ -363,12 +445,19 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); - pdd->dev->pcs_data.hosttrap_entry.base.use_count--; - idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + pdd->dev->pcs_data.hosttrap_entry.base.use_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + pdd->dev->pcs_data.stoch_entry.base.use_count--; + if (!pdd->dev->pcs_data.stoch_entry.base.use_count) + memset(&pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + } - if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) - memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, - sizeof(struct kfd_pc_sample_info)); + idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); mutex_unlock(&pdd->dev->pcs_data.mutex); kfree(pcs_entry); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 234e51310bcce..786e9963be6f8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -306,11 +306,16 @@ struct kfd_dev_pcs_hosttrap { struct task_struct *pc_sample_thread; }; +struct kfd_dev_stochastic { + struct kfd_dev_pc_sampling_data base; +}; + /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; struct idr sampling_idr; struct kfd_dev_pcs_hosttrap hosttrap_entry; + struct kfd_dev_stochastic stoch_entry; }; struct kfd_node { @@ -835,6 +840,7 @@ enum kfd_pdd_bound { struct pc_sampling_entry { bool enabled; + enum kfd_ioctl_pc_sample_method method; struct kfd_process_device *pdd; }; From d5c50d68106e7510f58eea421721778fd59cc78f Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:14:19 -0400 Subject: [PATCH 1399/2070] drm/amdkfd: enable stochastic PC sampling for gfx943 Enable stochastic PC sampling for gfx943 Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Reviewed-by: Shweta Khatri --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e8addf8817d9d..1cf02035d326d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -34,9 +34,10 @@ * 0.1 - Initial revision * 0.2 - Support gfx9_4_3 Host Trap PC sampling * 0.3 - Fix gfx9_4_3 SQ hang issue + * 1.1 - Support gfx9_4_3 Stochastic PC sampling */ -#define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 3 +#define KFD_IOCTL_PCS_MAJOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 1 struct supported_pc_sample_info { uint32_t ip_version; @@ -53,6 +54,7 @@ const struct kfd_pc_sample_info sample_info_stoch_cycle_9_4_3 = { struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, }; static int kfd_pc_sample_thread(void *param) From bb13544643e974755795421fa12c852fc2ce64ff Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 13:24:23 +0800 Subject: [PATCH 1400/2070] drm/amdkcl: test drm_display_info->source_physical_address is available It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- drivers/gpu/drm/amd/dkms/config/config.h | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_drm_display_info.m4 | 17 +++++++++++++++++ 4 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb72d19f759a6..47fd5cbf841f1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2883,9 +2883,11 @@ void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector) if (!n) return; - + +#ifdef HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS cec_notifier_set_phys_addr(n, connector->display_info.source_physical_address); +#endif } static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0bae0e1fbf50d..99d0b39c1b1c7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -307,6 +307,15 @@ /* display_info->max_dsc_bpp is available */ #define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + +/* struct drm_display_info->source_physical_address is available */ +#define HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS 1 + +/* drm_dp_add_payload_part2 has three arguments */ +/* #undef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS */ + /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d0dbf43547819..e8f2c885eabe8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -233,6 +233,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CLIENT AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT + AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 new file mode 100644 index 0000000000000..87a29c5cd5f4d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.5-rc2-871-g82b599ece3b8 +dnl # drm/edid: parse source physical address +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->source_physical_address = 0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS, 1, + [struct drm_display_info->source_physical_address is available]) + ]) + ]) +]) From dbec2f98741be093e7763adb7695159dd7340a89 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 14:20:35 +0800 Subject: [PATCH 1401/2070] drm/amdkcl: test cec_notifier_conn_register() is available It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/cec_notifier_conn_register.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 47fd5cbf841f1..90aa1081a8913 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7826,8 +7826,9 @@ static void amdgpu_dm_connector_unregister(struct drm_connector *connector) if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); - +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); +#endif drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); } static void amdgpu_dm_connector_destroy(struct drm_connector *connector) @@ -9391,12 +9392,14 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) } cec_fill_conn_info_from_drm(&conn_info, &aconnector->base); +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER aconnector->notifier = cec_notifier_conn_register(hdmi_dev, NULL, &conn_info); if (!aconnector->notifier) { drm_err(ddev, "Failed to create cec notifier\n"); return -ENOMEM; } +#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1d57076153c17..4108cb6ccd81b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -2972,7 +2972,9 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, } else { if (!aconnector->notifier) return -EINVAL; +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER cec_notifier_conn_unregister(aconnector->notifier); +#endif aconnector->notifier = NULL; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 99d0b39c1b1c7..77bdfe0afb84a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -74,6 +74,9 @@ /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 +/* cec_notifier_conn_register() is available */ +#define HAVE_CEC_NOTIFIER_CONN_REGISTER 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 b/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 new file mode 100644 index 0000000000000..b672c855b13f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-393-gb48cb35c6a7b +dnl # media: cec-notifier: add new notifier functions +dnl # +AC_DEFUN([AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cec_notifier_conn_register(NULL, NULL, NULL); + ], [cec_notifier_conn_register], [drivers/media/cec/core/cec-notifier.c], [ + AC_DEFINE(HAVE_CEC_NOTIFIER_CONN_REGISTER, 1, + [cec_notifier_conn_register() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e8f2c885eabe8..a4e13a51a5a10 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -234,6 +234,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS + AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e5bb247552463bd0829830070933ee9ed7ff62d4 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 17:23:33 +0800 Subject: [PATCH 1402/2070] drm/amdkcl: fake the macro define DEFINE_SHOW_STORE_ATTRIBUTE It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_seq_file.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h index b884645a14388..bc9d5c08ecfc1 100644 --- a/include/kcl/kcl_seq_file.h +++ b/include/kcl/kcl_seq_file.h @@ -21,6 +21,23 @@ static const struct file_operations __name ## _fops = { \ } #endif +#ifndef DEFINE_SHOW_STORE_ATTRIBUTE +#define DEFINE_SHOW_STORE_ATTRIBUTE(__name) \ +static int __name ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __name ## _show, inode->i_private); \ +} \ + \ +static const struct file_operations __name ## _fops = { \ + .owner = THIS_MODULE, \ + .open = __name ## _open, \ + .read = seq_read, \ + .write = __name ## _write, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} +#endif + #ifndef HAVE_SEQ_HEX_DUMP void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, int rowsize, int groupsize, const void *buf, size_t len, From c4ddd24365257f7c3a838719efb89695b95ba5ad Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 15:01:04 +0800 Subject: [PATCH 1403/2070] drm/amdkcl: test struct cec_connector_info is available It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c | 23 +++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../gpu/drm/amd/dkms/m4/cec_connector_info.m4 | 23 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_cec.h | 60 +++++++++++++++++++ 7 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 create mode 100644 include/kcl/kcl_cec.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 62baea5001d4a..3889ca890a77d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c b/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c new file mode 100644 index 0000000000000..3a94597bac3a2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * cec-adap.c - HDMI Consumer Electronics Control framework - CEC adapter + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ +#include +#include +#include +#include + +#if !defined(HAVE_CEC_CONNECTOR_INFO) +void _kcl_cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector) +{ + memset(conn_info, 0, sizeof(*conn_info)); + conn_info->type = CEC_CONNECTOR_TYPE_DRM; + conn_info->drm.card_no = connector->dev->primary->index; + conn_info->drm.connector_id = connector->base.id; +} +EXPORT_SYMBOL_GPL(_kcl_cec_fill_conn_info_from_drm); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e70437bc74ea7..e0ef66a41ac64 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -131,4 +131,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77bdfe0afb84a..a60568d432e72 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -74,6 +74,9 @@ /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 +/* struct cec_connector_info is available */ +#define HAVE_CEC_CONNECTOR_INFO 1 + /* cec_notifier_conn_register() is available */ #define HAVE_CEC_NOTIFIER_CONN_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 b/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 new file mode 100644 index 0000000000000..112e9335801c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # +dnl # v5.2-rc5-392-g32a847f9fa40 +dnl # media: cec: add struct cec_connector_info support +dnl # +dnl # v5.4-rc1-53-g9098c1c251ff +dnl # media: cec: expose the new connector info API +dnl # The structure cec_connector_info has been moved from the media/cec.h to the uapi/linux/cec.h +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct cec_connector_info conn_info; + memset(&conn_info, 0, sizeof(conn_info)); + ], [ + AC_DEFINE(HAVE_CEC_CONNECTOR_INFO, 1, + [struct cec_connector_info is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a4e13a51a5a10..d7a630cf22acd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -235,6 +235,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER + AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_cec.h b/include/kcl/kcl_cec.h new file mode 100644 index 0000000000000..da8ed4471095b --- /dev/null +++ b/include/kcl/kcl_cec.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * cec - HDMI Consumer Electronics Control public header + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef _KCL_CEC_UAPI_H +#define _KCL_CEC_UAPI_H + +#include +#include + +#if !defined(HAVE_CEC_CONNECTOR_INFO) +/** + * struct cec_drm_connector_info - tells which drm connector is + * associated with the CEC adapter. + * @card_no: drm card number + * @connector_id: drm connector ID + */ +struct cec_drm_connector_info { + __u32 card_no; + __u32 connector_id; +}; + +#define CEC_CONNECTOR_TYPE_NO_CONNECTOR 0 +#define CEC_CONNECTOR_TYPE_DRM 1 + +/** + * struct cec_connector_info - tells if and which connector is + * associated with the CEC adapter. + * @type: connector type (if any) + * @drm: drm connector info + * @raw: array to pad the union + */ +struct cec_connector_info { + __u32 type; + union { + struct cec_drm_connector_info drm; + __u32 raw[16]; + }; +}; + +#if IS_REACHABLE(CONFIG_CEC_CORE) +void _kcl_cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector); +#define cec_fill_conn_info_from_drm _kcl_cec_fill_conn_info_from_drm + +#else +static inline void +cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector) +{ + memset(conn_info, 0, sizeof(*conn_info)); +} +#endif + +#endif + +#endif From a53ac5c29182403cdc4600b34468a4b56b4f7f1c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 7 Jan 2025 15:43:54 +0800 Subject: [PATCH 1404/2070] drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DMABUF_OPS These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Asher Song drm/amdgpu: Remove remaining AMDKCL_AMDGPU_DMABUF_OPS refs These were missed in the cleanup patch, so remove them to allow the kernel to compile again Fixes: 083e622bbba3 ("drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DMABUF_OPS") Signed-off-by: Kent Russell Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 - .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 51 ------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 5 -- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 --- include/kcl/backport/kcl_drm_backport.h | 4 -- 7 files changed, 76 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f73ac297f17d4..4382c0d823319 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -384,9 +384,7 @@ struct amdgpu_clock { uint32_t max_pixel_clock; }; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) extern const struct dma_buf_ops amdgpu_dmabuf_ops; -#endif /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 1b41c01e01525..eb232c5c5e41f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -551,11 +551,9 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, if (IS_ERR(dma_buf)) return PTR_ERR(dma_buf); -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* Can't handle non-graphics buffers */ goto out_put; -#endif obj = dma_buf->priv; if (obj->dev->driver != adev_to_drm(adev)->driver) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 106339c29e117..bdf1ac7e4e93a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -849,7 +849,6 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) return 0; } -#ifdef AMDKCL_AMDGPU_DMABUF_OPS static int kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo **bo) @@ -870,7 +869,6 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, return 0; } -#endif /** * @kfd_mem_attach_vram_bo: Acquires the handle of a VRAM BO that could @@ -994,7 +992,6 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = create_dmamap_sg_bo(adev, mem, &bo[i]); if (ret) goto unwind; -#ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { attachment[i]->type = KFD_MEM_ATT_DMABUF; @@ -1002,7 +999,6 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); -#endif /* Enable peer acces to VRAM BO's */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { ret = kfd_mem_attach_vram_bo(adev, mem, @@ -1010,11 +1006,9 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; } else { -#ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; goto unwind; -#endif attachment[i]->type = KFD_MEM_ATT_SHARED; bo[i] = mem->bo; drm_gem_object_get(&bo[i]->tbo.base); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index b63b0c06474bc..edfbe2b449e18 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -92,7 +92,6 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, } #endif -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) #if defined(HAVE_DMA_BUF_OPS_LEGACY) static int __dma_resv_make_exclusive(struct dma_resv *obj) @@ -571,7 +570,6 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .vmap = amdgpu_dma_buf_vmap, .vunmap = amdgpu_dma_buf_vunmap, }; -#endif /** * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation @@ -620,9 +618,7 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, #ifdef AMDKCL_DMA_BUF_SHARE_ADDR_SPACE buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; #endif -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) buf->ops = &amdgpu_dmabuf_ops; -#endif } return buf; @@ -711,7 +707,6 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, return ERR_PTR(ret); } -#ifdef AMDKCL_AMDGPU_DMABUF_OPS /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -742,7 +737,6 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, return drm_gem_prime_import(dev, dma_buf); } -#endif #else /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import @@ -929,49 +923,6 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, } #endif -#ifndef AMDKCL_AMDGPU_DMABUF_OPS -int amdgpu_gem_prime_pin(struct drm_gem_object *obj) -{ - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - long ret = 0; - - ret = amdgpu_bo_reserve(bo, false); - if (unlikely(ret != 0)) - return ret; - - /* - * Wait for all shared fences to complete before we switch to future - * use of exclusive fence on this prime shared bo. - */ - ret = dma_resv_wait_timeout(bo->tbo.resv, true, false, - MAX_SCHEDULE_TIMEOUT); - if (unlikely(ret < 0)) { - DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); - amdgpu_bo_unreserve(bo); - return ret; - } - - /* pin buffer into GTT */ - ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); - - amdgpu_bo_unreserve(bo); - return ret; -} - -void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) -{ - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - int ret = 0; - - ret = amdgpu_bo_reserve(bo, true); - if (unlikely(ret != 0)) - return; - - amdgpu_bo_unpin(bo); - amdgpu_bo_unreserve(bo); -} -#endif - /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer * @@ -993,11 +944,9 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, if (drm_gem_is_imported(obj)) { struct dma_buf *dma_buf = obj->import_attach->dmabuf; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* No XGMI with non AMD GPUs */ return false; -#endif gobj = dma_buf->priv; bo = gem_to_amdgpu_bo(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index dbc9384febd43..9db5f1d2a29c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -41,13 +41,8 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, struct drm_gem_object *gobj, #endif int flags); -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); -#else -int amdgpu_gem_prime_pin(struct drm_gem_object *obj); -void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); -#endif bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 516b6bf82e3e9..47a035a13c9a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3197,13 +3197,7 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_export = amdgpu_gem_prime_export, #endif -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, -#else - .gem_prime_import = drm_gem_prime_import, - .gem_prime_pin = amdgpu_gem_prime_pin, - .gem_prime_unpin = amdgpu_gem_prime_unpin, -#endif #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index c17c10af84c09..1aba914420638 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -10,10 +10,6 @@ #define AMDKCL_AMDGPU_DEBUGFS_CLEANUP #endif -#if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) -#define AMDKCL_AMDGPU_DMABUF_OPS -#endif - /* * commit v5.4-rc4-1120-gb3fac52c5193 * drm: share address space for dma bufs From 4baa49b0bf18570adf694ec15d411c2b66c1eaad Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Jan 2025 14:35:12 +0800 Subject: [PATCH 1405/2070] drm/amdkcl: cleanup macro AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 21 --------------------- include/kcl/backport/kcl_drm_backport.h | 8 -------- 2 files changed, 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 322f0b0794919..850de5fe218c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -208,33 +208,12 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, return ret; } -#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY -static int -amdgpu_vkms_connector_dpms(struct drm_connector *connector, int mode) -{ - return 0; -} - - -static int -amdgpu_vkms_connector_set_property(struct drm_connector *connector, - struct drm_property *property, - uint64_t val) -{ - return 0; -} -#endif - static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = drm_atomic_helper_connector_reset, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY - .set_property = amdgpu_vkms_connector_set_property, - .dpms = amdgpu_vkms_connector_dpms, -#endif }; static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 1aba914420638..135a5e5c499af 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -18,12 +18,4 @@ #define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE #endif -/* - * commit v4.13-rc2-365-g144a7999d633 - * drm: Handle properties in the core for atomic drivers - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 14, 0) -#define AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY -#endif - #endif/*AMDKCL_DRM_BACKPORT_H*/ From fc231e31e9f472840b0cba14284700eb83dfc31c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Jan 2025 14:39:57 +0800 Subject: [PATCH 1406/2070] drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DEBUGFS_CLEANUP These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 19 ------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 5 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ------ include/kcl/backport/kcl_drm_backport.h | 8 -------- 4 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 6d67492cd88c5..da1efb8baaad9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -42,25 +42,6 @@ #if defined(CONFIG_DEBUG_FS) -#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) -void amdgpu_debugfs_cleanup(struct drm_minor *minor) -{ - struct drm_info_node *node, *tmp; - - if (!&minor->debugfs_root) - return; - - mutex_lock(&minor->debugfs_lock); - list_for_each_entry_safe(node, tmp, - &minor->debugfs_list, list) { - debugfs_remove(node->dent); - list_del(&node->list); - kfree(node); - } - mutex_unlock(&minor->debugfs_lock); -} -#endif - /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 5696dcb7f3be4..aabfabbd5e3e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,11 +25,6 @@ /* * Debugfs */ -#if defined(CONFIG_DEBUG_FS) -#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) -void amdgpu_debugfs_cleanup(struct drm_minor *minor); -#endif -#endif int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 47a035a13c9a4..840627c4bc0bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3156,12 +3156,6 @@ static struct drm_driver amdgpu_kms_driver = { , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, -#if defined(CONFIG_DEBUG_FS) -#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) - .debugfs_cleanup = amdgpu_debugfs_cleanup, -#endif -#endif - #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, .enable_vblank = kcl_amdgpu_enable_vblank_kms, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 135a5e5c499af..56326c6a61e89 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -2,14 +2,6 @@ #ifndef AMDKCL_DRM_BACKPORT_H #define AMDKCL_DRM_BACKPORT_H -/* - * commit v4.10-rc3-539-g086f2e5cde74 - * drm: debugfs: Remove all files automatically on cleanup - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 11, 0) -#define AMDKCL_AMDGPU_DEBUGFS_CLEANUP -#endif - /* * commit v5.4-rc4-1120-gb3fac52c5193 * drm: share address space for dma bufs From e508290cd07ac572dc606363792baac3bf4ceeed Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 3 Jan 2025 16:48:10 +0800 Subject: [PATCH 1407/2070] drm/amdkcl: Replace drm_dp_mst_topology_mgr.base check with drm_private_obj.lock The check for the 'base' field in the struct drm_dp_mst_topology_mgr is no longer necessary.This patch removes the check for 'base' and replaces it with a check for the 'lock' field in struct drm_private_obj. And The base.lock was introduced in version 4.20, while the write lock was added in DRM version 5.4.0. Since RHEL 7.9 uses DRM version 5.0.10, write operations do not include locking. Consequently, read operations here also do not require locking. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 26 ++++++++++--------- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++--- .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 20 -------------- .../drm/amd/dkms/m4/drm_private_obj_lock.m4 | 19 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 5 files changed, 37 insertions(+), 36 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 4108cb6ccd81b..e918686a46937 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -345,7 +345,6 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, return size; } -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) { bool is_end_device = false; @@ -356,11 +355,20 @@ static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) mgr = &aconnector->mst_root->mst_mgr; port = aconnector->mst_output_port; + /* The base.lock was introduced in version 4.20, while the write + * lock was added in DRM version 5.4.0. Since RHEL 7.9 uses DRM version + * 5.0.10, write operations do not include locking. Consequently, read + * operations here also do not require locking. + */ +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_lock(&mgr->base.lock, NULL); +#endif if (port->pdt == DP_PEER_DEVICE_SST_SINK || port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) is_end_device = true; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_unlock(&mgr->base.lock); +#endif } return is_end_device; @@ -492,7 +500,6 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, kfree(wr_buf); return size; } -#endif /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * @@ -2824,7 +2831,6 @@ static int target_backlight_show(struct seq_file *m, void *unused) * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector * */ -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static int dp_is_mst_connector_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -2845,11 +2851,15 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) mgr = &aconnector->mst_root->mst_mgr; port = aconnector->mst_output_port; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_lock(&mgr->base.lock, NULL); +#endif if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && port->mcs) role = "branch"; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_unlock(&mgr->base.lock); +#endif } else { role = "no"; @@ -2861,7 +2871,6 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) return 0; } -#endif /* * function description: Read out the mst progress status @@ -2990,9 +2999,7 @@ DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); DEFINE_SHOW_ATTRIBUTE(replay_capability); DEFINE_SHOW_ATTRIBUTE(psr_capability); -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); -#endif DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); @@ -3093,13 +3100,12 @@ static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { .write = dp_dsc_passthrough_set, .llseek = default_llseek }; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE + static const struct file_operations dp_mst_link_settings_debugfs_fops = { .owner = THIS_MODULE, .write = dp_mst_link_setting, .llseek = default_llseek }; -#endif static const struct { char *name; @@ -3122,14 +3128,10 @@ static const struct { {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"is_mst_connector", &dp_is_mst_connector_fops}, -#endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} -#endif }; static const struct { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a60568d432e72..1a2cf662a757f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -418,9 +418,6 @@ /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ -/* struct drm_dp_mst_topology_mgr.base is available */ -#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 - /* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ @@ -654,6 +651,9 @@ /* drm_print_memory_stats() is available */ #define HAVE_DRM_PRINT_MEMORY_STATS 1 +/* struct drm_private_obj.lock is available */ +#define HAVE_DRM_PRIVATE_OBJ_LOCK 1 + /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 deleted file mode 100644 index c674432e635f2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit v4.14-rc1-a4370c7774 -dnl # drm/atomic: Make private objs proper objects -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_dp_mst_topology_mgr *mst_mgr = 0; - int i = 0; - if ((&mst_mgr->base) && (&mst_mgr->base.lock)) - i++; - ], [ - AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE, 1, - [struct drm_dp_mst_topology_mgr.base is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 new file mode 100644 index 0000000000000..79e2de01aed3f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v4.20-rc4-945-gb962a12050a3 +dnl # drm/atomic: integrate modeset lock with private objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIVATE_OBJ_LOCK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_private_obj *obj = NULL; + struct drm_modeset_lock lock = {}; + obj->lock = lock; + ], [ + AC_DEFINE(HAVE_DRM_PRIVATE_OBJ_LOCK, 1, + [struct drm_private_obj.lock is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d7a630cf22acd..316b62a4848a6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -167,7 +167,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG - AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE + AC_AMDGPU_DRM_PRIVATE_OBJ_LOCK AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DP_READ_DPCD_CAPS AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART From d4a548827d9e0d638a4e4c591600e874758eb76b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 15 Jan 2025 11:36:56 +0800 Subject: [PATCH 1408/2070] drm/amdkcl: include $CC condition to pre-build Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 4 +++- drivers/gpu/drm/amd/dkms/pre-build.sh | 29 +++++++++++++++------------ 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index abb5fa4da4920..6c767056f76a8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -7,6 +7,7 @@ module_src_dir := $(CURDIR) module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) module_build_flags := num_cpu_cores := $(shell which nproc > /dev/null && nproc || echo "1") +CC := gcc Q := @ ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) @@ -31,6 +32,7 @@ $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif ifneq ($(CONFIG_CC_IS_CLANG),) +CC := clang module_build_flags += CC=clang endif ifneq ($(CONFIG_LD_IS_LLD),) @@ -53,7 +55,7 @@ sanity-check: pre-build $(config-file) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) pre-build: - $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) clean: $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7f3e5f9323673..b9fc82557aac6 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -7,6 +7,7 @@ SRC="amd/dkms" KERNELVER=$1 DKMS_TREE=$2 MODULE_BUILD_DIR=$3 +CC=$4 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -62,19 +63,21 @@ done export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR -# Enable gcc-toolset for kernels that are built with non-default compiler -# perform this check only when permissions allow -if [[ -d /opt/rh && `id -u` -eq 0 ]]; then - for f in $(find /opt/rh -type f -a -name gcc); do - [[ -f /boot/config-$KERNELVER ]] || continue - config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) - IFS='.' read -ra ver <<<$($f -dumpfullversion) - gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) - if [[ "$config_gcc_version" = "$gcc_version" ]]; then - . ${f%/*}/../../../enable - break - fi - done +if [ "$CC" == "gcc" ]; then + # Enable gcc-toolset for kernels that are built with non-default compiler + # perform this check only when permissions allow + if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done + fi fi echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env From be3ed247cb876f83c7d53e6f973874248d4eb572 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 17 Jan 2025 14:55:25 +0800 Subject: [PATCH 1409/2070] drm/amdkcl: test whether struct drm_connector_state->hdmi.broadcast_rgb is available It's caused by the commit: 0865e2aef5ca "drm/amd/display: Support "Broadcast RGB" drm property" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/struct_drm_connector_state.m4 | 21 ++++++++++++++++++- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 90aa1081a8913..912b2c4078b98 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6612,8 +6612,10 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, default: if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { color_space = COLOR_SPACE_SRGB; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if (connector_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED) color_space = COLOR_SPACE_SRGB_LIMITED; +#endif /* * 27030khz is the separation point between HDTV and SDTV * according to HDMI spec, we use YCbCr709 and YCbCr601 @@ -9237,9 +9239,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, dm->ddev->mode_config.scaling_mode_property, DRM_MODE_SCALE_NONE); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if (connector_type == DRM_MODE_CONNECTOR_HDMIA || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root)) drm_connector_attach_broadcast_rgb_property(&aconnector->base); +#endif drm_object_attach_property(&aconnector->base.base, adev->mode_info.underscan_property, @@ -11168,10 +11172,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) scaling_changed = is_scaling_state_different(dm_new_con_state, dm_old_con_state); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && (dm_old_crtc_state->stream->output_color_space != get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) output_color_space_changed = true; +#endif abm_changed = dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1a2cf662a757f..317ff0601392c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -239,6 +239,9 @@ /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 +/* drm_connector_state->hdmi.broadcast_rgb is available */ +#define HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB 1 + /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 index 845426d6fe7bf..fbcca17fe167a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 @@ -16,6 +16,25 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE], [ ]) ]) +dnl # +dnl # commit v6.10-rc1-219-gab52af4ba7c7 +dnl # drm/connector: hdmi: Add Broadcast RGB property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->hdmi.broadcast_rgb = DRM_HDMI_BROADCAST_RGB_AUTO; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB, 1, + [drm_connector_state->hdmi.broadcast_rgb is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE], [ AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE -]) \ No newline at end of file + AC_AMDGPU_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB +]) From b5f689a5e414e93b1e39efa203f4cd4f1c29c434 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 20 Jan 2025 18:01:47 +0800 Subject: [PATCH 1410/2070] drm/amdkcl: fix unused function amdgpu_vkms_early_init() The wrong merge to miss amdgpu_vkms_early_init(), so remerge it. Fixes: 1e30d5a2c81b("drm/amdgpu: Clean the functions pointer set as NULL") Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 850de5fe218c9..cb4a279fa39ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -765,6 +765,9 @@ static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block, static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { .name = "amdgpu_vkms", +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .early_init = amdgpu_vkms_early_init, +#endif .sw_init = amdgpu_vkms_sw_init, .sw_fini = amdgpu_vkms_sw_fini, .hw_init = amdgpu_vkms_hw_init, From a3d537c348b284590220e0f133504ce2db8717aa Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 17 Jan 2025 16:32:20 +0800 Subject: [PATCH 1411/2070] drm/amdgpu: Fix parameter compatibility issue in amdgpu_vkms_early_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GCC raises a parameter compatibility error log for the amdgpu_vkms_early_init function because it previously accepted a generic `void *handle` parameter. This change updates the function signature to accept a specific `struct amdgpu_ip_block *` parameter instead. error log: /tmp/amd.fwXY79Rm/amd/amdgpu/amdgpu_vkms.c:805:16: error: initialization of ‘int (*)(struct amdgpu_ip_block *)’ from incompatible pointer type ‘int (*)(void *)’ [-Werror=incompatible-pointer-types] .early_init = amdgpu_vkms_early_init, Reviewed-by: Alex Deucher Acked-by: Yifan Zhang Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index cb4a279fa39ac..33f33e1ba2366 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -597,9 +597,9 @@ static const struct amdgpu_irq_src_funcs amdgpu_vkms_crtc_irq_funcs = { .process = NULL, }; -static int amdgpu_vkms_early_init(void *handle) +static int amdgpu_vkms_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->crtc_irq.num_types = adev->mode_info.num_crtc; adev->crtc_irq.funcs = &amdgpu_vkms_crtc_irq_funcs; From dc6c52138e929340dd4e16fd80d74a0808b52647 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 21 Jan 2025 14:29:02 +0800 Subject: [PATCH 1412/2070] drm/amdkcl: Fix kfd->profiler_lock Initialization Order [Why] In GFX version < 11.0.0 (like navi22), the origin patch will cause kernel (version < 4.9) hangs due to Uninitialized mutex in kfd_init_node(). Since v4.9-rc2-42-g3ca0ff571b09 ("locking/mutex: Rework mutex::owner"), it has increased the tolerance of mutex locks, preventing the kernel hang. But it remains an incorrect usage. Here are the call paths: kgd2kfd_device_init() kfd_init_node() kfd_resume() start_cpsch() pm_init() kernel_queue_init() kq_initialize() init_mqd() mutex_lock(&mm->dev->kfd->profiler_lock) mutex_init(&kfd->profiler_lock) [How] Reorder the mutex_init() before kfd_init_node() to fix it. Fixes: b58289f0abf7 ("Add kfd_ioctl_profiler to contain profiler kernel driver changes") Signed-off-by: chengjya Signed-off-by: Bob Zhou Reviewed-by: Benjamin Welton --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 0ac215d723a0b..3c2e15968883e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -890,6 +890,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", kfd->num_nodes); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); /* Allocate the KFD nodes */ for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); @@ -977,6 +979,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, node_alloc_error: kfd_cleanup_nodes(kfd, i); kfd_doorbell_fini(kfd); + mutex_destroy(&kfd->profiler_lock); kfd_doorbell_error: kfd_gtt_sa_fini(kfd); kfd_gtt_sa_init_error: From 5dc19fd39707ba64c56bc162b31b3530d79b8b8f Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 20 Jan 2025 15:29:48 +0800 Subject: [PATCH 1413/2070] drm/amdkcl: fake the macro define ULL(x) It's caused by the commit: 9bb53d2c "drm/amd/pm: Add capability flags for SMU v13.0.6" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_const.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_const.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e0ef66a41ac64..03674a4e58521 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -132,4 +132,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_const.h b/include/kcl/kcl_const.h new file mode 100644 index 0000000000000..676de2be9f96a --- /dev/null +++ b/include/kcl/kcl_const.h @@ -0,0 +1,11 @@ +#ifndef _KCL_LINUX_CONST_H +#define _KCL_LINUX_CONST_H + +#include + +#ifndef _ULL +#define _ULL(x) (_AC(x, ULL)) +#define ULL(x) (_ULL(x)) +#endif + +#endif /* _KCL_LINUX_CONST_H */ From 734f809f2a9bdd8f57607724bfdd77bd0b86f30a Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 20 Jan 2025 16:00:12 -0500 Subject: [PATCH 1414/2070] drm/amdgpu: apply psp_config_sq_perfmon on gfx_9_5_0 which is with psp_13_0_12. Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index d24078970cb36..f324c736e50e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4049,7 +4049,8 @@ int psp_config_sq_perfmon(struct psp_context *psp, if (amdgpu_sriov_vf(psp->adev)) return 0; - if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { + if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6) && + amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) { dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); return -EINVAL; From b7f285e4f8b457cb56e7e58ac7d14ec490805caa Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 14 Jan 2025 14:12:21 -0500 Subject: [PATCH 1415/2070] drm/kfd: add Host Trap PC sampling support for gfx_9_5_0. Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 1cf02035d326d..7573eb3f88cbe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -35,6 +35,7 @@ * 0.2 - Support gfx9_4_3 Host Trap PC sampling * 0.3 - Fix gfx9_4_3 SQ hang issue * 1.1 - Support gfx9_4_3 Stochastic PC sampling + * 1.2 - Support gfx9_5_0 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 #define KFD_IOCTL_PCS_MINOR_VERSION 1 @@ -55,6 +56,7 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From 6a8568dd76a4ed0dfc410b7fd0331315cbbba5cb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Jan 2025 10:25:55 +0800 Subject: [PATCH 1416/2070] drm/amdkcl: Handle GCC change in advance Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 34 +++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index b9fc82557aac6..3dca4caa9855d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -30,6 +30,23 @@ version_le () { [ "$KERNELVER_BASE" = "$oldest" ] } +if [ "$CC" == "gcc" ]; then + # Enable gcc-toolset for kernels that are built with non-default compiler + # perform this check only when permissions allow + if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done + fi +fi + source $KCL/files sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ @@ -62,23 +79,6 @@ done export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR - -if [ "$CC" == "gcc" ]; then - # Enable gcc-toolset for kernels that are built with non-default compiler - # perform this check only when permissions allow - if [[ -d /opt/rh && `id -u` -eq 0 ]]; then - for f in $(find /opt/rh -type f -a -name gcc); do - [[ -f /boot/config-$KERNELVER ]] || continue - config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) - IFS='.' read -ra ver <<<$($f -dumpfullversion) - gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) - if [[ "$config_gcc_version" = "$gcc_version" ]]; then - . ${f%/*}/../../../enable - break - fi - done - fi -fi echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env (cd $SRC && ./configure) From a3ea2aa74ab2bcfc75e9cec331f7ba5b916451c7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Jan 2025 10:41:27 +0800 Subject: [PATCH 1417/2070] drm/amdkcl: modify gcc check into pre-build.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 8 -------- drivers/gpu/drm/amd/dkms/pre-build.sh | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 0821ba268d9a4..df676cf4a33a7 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -25,14 +25,6 @@ endif endif -include $(src)/amd/dkms/Makefile.compiler - -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifneq ($(call gcc-min-version, 40805), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 3dca4caa9855d..f27b5d9204a3e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -45,6 +45,14 @@ if [ "$CC" == "gcc" ]; then fi done fi + + gcc_version=$($CC -dumpfullversion | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') + kernel_version=$(uname -r | awk -F. '{printf "%d%02d", $1, $2}') + # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. + if [ "$gcc_version" -lt 40805 ] && [ "$kernel_version" -ge 0504 ]; then + echo "Error: The GCC is too old for this kernel, please update the GCC to higher than 9.3" + exit 1 + fi fi source $KCL/files From 403dd93a995630816cf78e95dcf91416c6c0e36b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Jan 2025 13:12:18 +0800 Subject: [PATCH 1418/2070] drm/amdkcl: fix undefined CONFIG_GCC_VERSION When kernel < v4.17-6936-ga4353898980c(like rhel7.9), the CONFIG_GCC_VERSION isn't defined. So include the varb in vmlinuz. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index f27b5d9204a3e..7411801636c29 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -37,6 +37,10 @@ if [ "$CC" == "gcc" ]; then for f in $(find /opt/rh -type f -a -name gcc); do [[ -f /boot/config-$KERNELVER ]] || continue config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + # CONFIG_GCC_VERSION is included in kernel v4.17-6936-ga4353898980c + if [ ! "$config_gcc_version" ]; then + config_gcc_version=$(strings /boot/vmlinuz-$KERNELVER | grep -F $KERNELVER | grep gcc | grep -oP 'gcc version \K[\d.]+') + fi IFS='.' read -ra ver <<<$($f -dumpfullversion) gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) if [[ "$config_gcc_version" = "$gcc_version" ]]; then From 45511cf28bb7c9a7c0be863fa9b9ee926e1cb7fd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 21 Jan 2025 11:15:40 +0800 Subject: [PATCH 1419/2070] drm/amdkcl: cleanup config CONFIG_DRM_TTM_DMA_PAGE_POOL Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index df676cf4a33a7..2b0db273109f1 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -141,7 +141,6 @@ LINUXINCLUDE := \ export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m -export CONFIG_DRM_TTM_DMA_PAGE_POOL=y export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m export CONFIG_DRM_AMDGPU_CIK=y @@ -150,7 +149,6 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y subdir-ccflags-y += -DCONFIG_HSA_AMD -subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From 2e7d19d1ac3b8ebeebe72681aebc836d2c47f600 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 21 Jan 2025 11:20:47 +0800 Subject: [PATCH 1420/2070] drm/amdkcl: cleanup config CONFIG_DRM_AMD_DC_HDCP It's caused 1e88eb1b2c259994d034b0833cb489105a984ebb drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +-- drivers/gpu/drm/amd/dkms/Kbuild | 3 --- include/kcl/kcl_drm_hdcp.h | 2 -- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3889ca890a77d..6b4d598138cac 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,9 +16,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o -amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 2b0db273109f1..2ff5206d47931 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -162,9 +162,6 @@ subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif endif -export CONFIG_DRM_AMD_DC_HDCP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP - ifeq (y,$(CONFIG_PCI_P2PDMA)) ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) export CONFIG_HSA_AMD_P2P=y diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index 76c7823fe6f88..7b6bb3b69a57a 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -8,7 +8,6 @@ #ifndef AMDKCL_DRM_HDCP_H #define AMDKCL_DRM_HDCP_H -#ifdef CONFIG_DRM_AMD_DC_HDCP #include #include @@ -318,6 +317,5 @@ void drm_hdcp_update_content_protection(struct drm_connector *connector, } #endif /* HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION */ -#endif /* CONFIG_DRM_AMD_DC_HDCP */ #endif /* AMDKCL_DRM_HDCP_H */ From 533ac4a12a0ac7ba50df15a5c975cbcd4964d6d1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 21 Jan 2025 11:38:57 +0800 Subject: [PATCH 1421/2070] drm/amdkcl: split dkms config to dkms-config.mk Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 13 ++------- drivers/gpu/drm/amd/dkms/Makefile | 6 +++- drivers/gpu/drm/amd/dkms/dkms-config.sh | 37 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 12 deletions(-) create mode 100755 drivers/gpu/drm/amd/dkms/dkms-config.sh diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 2ff5206d47931..d78b0c1265832 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -25,6 +25,7 @@ endif endif +include $(src)/amd/dkms/dkms-config.mk _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") @@ -139,20 +140,10 @@ LINUXINCLUDE := \ -I$(src)/include/uapi \ $(USER_INCLUDE) -export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m -export CONFIG_DRM_AMDGPU_CIK=y -export CONFIG_DRM_AMDGPU_SI=y -export CONFIG_DRM_AMDGPU_USERPTR=y -export CONFIG_DRM_AMD_DC=y - -subdir-ccflags-y += -DCONFIG_HSA_AMD -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC + subdir-ccflags-y += -Wno-error ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6c767056f76a8..dcaaf349feece 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -39,10 +39,11 @@ ifneq ($(CONFIG_LD_IS_LLD),) module_build_flags += LD=ld.lld endif +dkms-config ?= amd/dkms/dkms-config.mk config-file ?= amd/dkms/config/config.h KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") -modules: sanity-check +modules: sanity-check $(dkms-config) $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ TTM_NAME=amdttm \ SCHED_NAME=amd-sched \ @@ -54,6 +55,9 @@ sanity-check: pre-build $(config-file) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) +$(dkms-config): pre-build + $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) + pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh new file mode 100755 index 0000000000000..9b245874f09e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +local_config=$1 +KERNELVER=$2 +local_config_tmp=${local_config}.tmp +config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" + +rm -f ${local_config_tmp} + +append_mk () { + echo $1 >> ${local_config_tmp} +} + +export_macro_mk () { +cat <<_DKMS_CONFIG >> ${local_config_tmp} +export $1=y +subdir-ccflags-y += -D$1 + +_DKMS_CONFIG +} + +get_config() { + grep "^$1=" "${config_file}" | awk -F= '{print $2}' +} + +is_enabled() { + grep -q "^$1=\[ym]" "${config_file}" +} + +export_macro_mk CONFIG_HSA_AMD +export_macro_mk CONFIG_DRM_AMDGPU_CIK +export_macro_mk CONFIG_DRM_AMDGPU_SI +export_macro_mk CONFIG_DRM_AMDGPU_USERPTR +export_macro_mk CONFIG_DRM_AMD_DC + +cat ${local_config_tmp} +mv ${local_config_tmp} ${local_config} \ No newline at end of file From ca4cc0c2de518176fcdb965dc2eefadb8d8c936f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 11 Feb 2025 14:54:23 +0800 Subject: [PATCH 1422/2070] drm/amdkcl: Add cleanup of dkms-config and config-file in clean target Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index dcaaf349feece..b16e2e453fe3e 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -62,5 +62,7 @@ pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) clean: + $(Q)echo "Cleaning build files..." $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean + $(Q)rm -f $(dkms-config) $(config-file) endif From 90802e827e9fd685e663ae8620d96f38e5cab1d3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 11 Feb 2025 15:56:28 +0800 Subject: [PATCH 1423/2070] drm/amdkcl: modify CONFIG_HSA_AMD_P2P to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 7 ------- drivers/gpu/drm/amd/dkms/dkms-config.sh | 8 +++++++- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index d78b0c1265832..ec9ed6319527a 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -153,13 +153,6 @@ subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif endif -ifeq (y,$(CONFIG_PCI_P2PDMA)) - ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) - export CONFIG_HSA_AMD_P2P=y - subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P - endif -endif - # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 9b245874f09e1..59a09af509429 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -27,6 +27,12 @@ is_enabled() { grep -q "^$1=\[ym]" "${config_file}" } +if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then + if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then + export_macro_mk CONFIG_HSA_AMD_P2P + fi +fi + export_macro_mk CONFIG_HSA_AMD export_macro_mk CONFIG_DRM_AMDGPU_CIK export_macro_mk CONFIG_DRM_AMDGPU_SI @@ -34,4 +40,4 @@ export_macro_mk CONFIG_DRM_AMDGPU_USERPTR export_macro_mk CONFIG_DRM_AMD_DC cat ${local_config_tmp} -mv ${local_config_tmp} ${local_config} \ No newline at end of file +mv ${local_config_tmp} ${local_config} From 78cebcb7c24a69acda877d2d6c0380c89f92b280 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Feb 2025 11:27:55 +0800 Subject: [PATCH 1424/2070] drm/amdkcl: fix is_enabled judge for dkms_config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 59a09af509429..01e2a91ce242f 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -24,7 +24,7 @@ get_config() { } is_enabled() { - grep -q "^$1=\[ym]" "${config_file}" + grep -q "^$1=" "${config_file}" } if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then From 5d2990be14c63cc211d78a40dfdc2ef43dac1df6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 17:00:19 +0800 Subject: [PATCH 1425/2070] drm/amdkcl: modify CONFIG_HSA_AMD_SVM to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 9 --------- drivers/gpu/drm/amd/dkms/dkms-config.sh | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index ec9ed6319527a..8ce585dc8463f 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -27,8 +27,6 @@ endif include $(src)/amd/dkms/dkms-config.mk -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) @@ -146,13 +144,6 @@ export CONFIG_DRM_SCHED=m subdir-ccflags-y += -Wno-error -ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) -ifdef CONFIG_DEVICE_PRIVATE -export CONFIG_HSA_AMD_SVM=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM -endif -endif - # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 01e2a91ce242f..e36cab0da0394 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -4,6 +4,7 @@ local_config=$1 KERNELVER=$2 local_config_tmp=${local_config}.tmp config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" +kcl_config_file="amd/dkms/config/config.h" rm -f ${local_config_tmp} @@ -27,12 +28,23 @@ is_enabled() { grep -q "^$1=" "${config_file}" } +is_kcl_macro_defined() { + grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" +} + if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P fi fi +# Check for HMM mirror configuration +if [[ "$(is_kcl_macro_defined HAVE_AMDKCL_HMM_MIRROR_ENABLED)" == "y" ]]; then + if is_enabled CONFIG_DEVICE_PRIVATE; then + export_macro_mk CONFIG_HSA_AMD_SVM + fi +fi + export_macro_mk CONFIG_HSA_AMD export_macro_mk CONFIG_DRM_AMDGPU_CIK export_macro_mk CONFIG_DRM_AMDGPU_SI From f4398f1e536aaeaecd77724dac64f683d9134483 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 13:52:40 +0800 Subject: [PATCH 1426/2070] drm/amdkcl: move OS check to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 84 ---------------------- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms-config.sh | 96 +++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 85 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 8ce585dc8463f..b71d645dc6264 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -39,90 +39,6 @@ subdir-ccflags-y += \ -DDRM_PATCH=$(DRM_PATCH) \ -DDRM_SUB="0" -define get_rhel_version -printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) -endef -RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) -RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) - -ifneq (,$(RHEL_MAJOR)) -OS_NAME = "rhel" -OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" -else ifneq (,$(wildcard /etc/os-release)) -OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" -# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL -ifeq ("centos",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("rhel",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("linuxmint",$(OS_NAME)) -OS_NAME="ubuntu" -endif -OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) -else -OS_NAME = "unknown" -OS_VERSION = "0.0" -endif - -OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) - -ifeq ("ubuntu",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_UBUNTU -else ifeq ("rhel",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_RHEL -else ifeq ("steamos",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_STEAMOS -else ifeq ("sled",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("sles",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("amzn",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_AMZ -else ifeq ("debian",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_DEBIAN -else -subdir-ccflags-y += -DOS_NAME_UNKNOWN -endif - -subdir-ccflags-y += \ - -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ - -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) - -ifeq ($(OS_NAME),"opensuse-leap") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sled") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sles") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"ubuntu") -OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) -subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) -OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" -ifeq ($(OS_OEM),"oem") -subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM -endif -subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"rhel") -subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) - -ifeq ($(RHEL_MAJOR),7) -subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ - -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h -else ifeq ($(RHEL_MAJOR),8) -subdir-ccflags-y += -DOS_NAME_RHEL_8_X -endif -endif - -export OS_NAME OS_VERSION - _KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b16e2e453fe3e..5f9b0ca95f2fd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -56,7 +56,7 @@ sanity-check: pre-build $(config-file) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) $(dkms-config): pre-build - $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) + $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) $(CC) pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index e36cab0da0394..3aef516a11857 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -2,9 +2,11 @@ local_config=$1 KERNELVER=$2 +CC=$3 local_config_tmp=${local_config}.tmp config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" +kernel_include="/lib/modules/$KERNELVER/build/include" rm -f ${local_config_tmp} @@ -32,6 +34,100 @@ is_kcl_macro_defined() { grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" } +# Get RHEL version +get_rhel_version() { + printf "#include \n$1" | $CC -I${kernel_include} -E -x c - | tail -n 1 | grep -v "$1" +} + +# Get RHEL major and minor version +RHEL_MAJOR=$(get_rhel_version "RHEL_MAJOR") +RHEL_MINOR=$(get_rhel_version "RHEL_MINOR") + +# Determine OS name and version +if [[ -n "${RHEL_MAJOR}" ]]; then + OS_NAME="rhel" + OS_VERSION="${RHEL_MAJOR}.${RHEL_MINOR}" +elif [[ -f /etc/os-release ]]; then + OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') + + # Handle special cases + case "${OS_NAME}" in + "centos") + OS_NAME="custom-rhel" + ;; + "rhel") + OS_NAME="custom-rhel" + ;; + "linuxmint") + OS_NAME="ubuntu" + ;; + esac + OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') +else + OS_NAME="unknown" + OS_VERSION="0.0" +fi + +OS_VERSION_STR=${OS_VERSION//./_} + +# Add OS specific defines +case "${OS_NAME}" in + "ubuntu") + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU" + ;; + "rhel") + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL" + ;; + "steamos") + append_mk "subdir-ccflags-y += -DOS_NAME_STEAMOS" + ;; + "sled"|"sles") + append_mk "subdir-ccflags-y += -DOS_NAME_SLE" + ;; + "amzn") + append_mk "subdir-ccflags-y += -DOS_NAME_AMZ" + ;; + "debian") + append_mk "subdir-ccflags-y += -DOS_NAME_DEBIAN" + ;; + *) + append_mk "subdir-ccflags-y += -DOS_NAME_UNKNOWN" + ;; +esac + +# Add OS specific compile flags +append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1)" +append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2)" + +# Add additional OS specific configurations +case "${OS_NAME}" in + "opensuse-leap"|"sled"|"sles") + append_mk "subdir-ccflags-y += -DOS_NAME_SUSE_${OS_VERSION_STR}" + ;; + "ubuntu") + OS_BUILD_NUM=$(echo "${KERNELVER}" | cut -d '-' -f 2) + append_mk "subdir-ccflags-y += -DUBUNTU_BUILD_NUM=${OS_BUILD_NUM}" + OS_OEM=$(echo "${KERNELVER}" | cut -d '-' -f 3) + if [[ "${OS_OEM}" == "oem" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM" + fi + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU_${OS_VERSION_STR}" + ;; + "rhel") + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" + if [[ "${RHEL_MAJOR}" == "7" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" + append_mk "-include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" + elif [[ "${RHEL_MAJOR}" == "8" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" + fi + ;; +esac + +# Export variables +append_mk "export OS_NAME=${OS_NAME}" +append_mk "export OS_VERSION=${OS_VERSION}" + if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P From ae75fed7f0d430fb05ce4d7a5bd74e2d00cc2677 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 15:52:24 +0800 Subject: [PATCH 1427/2070] drm/amdkcl: unify VERSION_MAJOR and VERSION_MINOR Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 28 +++++++------------------ 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 3aef516a11857..ddefbf6bed8ae 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -6,7 +6,6 @@ CC=$3 local_config_tmp=${local_config}.tmp config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" -kernel_include="/lib/modules/$KERNELVER/build/include" rm -f ${local_config_tmp} @@ -34,21 +33,9 @@ is_kcl_macro_defined() { grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" } -# Get RHEL version -get_rhel_version() { - printf "#include \n$1" | $CC -I${kernel_include} -E -x c - | tail -n 1 | grep -v "$1" -} - -# Get RHEL major and minor version -RHEL_MAJOR=$(get_rhel_version "RHEL_MAJOR") -RHEL_MINOR=$(get_rhel_version "RHEL_MINOR") - -# Determine OS name and version -if [[ -n "${RHEL_MAJOR}" ]]; then - OS_NAME="rhel" - OS_VERSION="${RHEL_MAJOR}.${RHEL_MINOR}" -elif [[ -f /etc/os-release ]]; then +if [[ -f /etc/os-release ]]; then OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') + OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') # Handle special cases case "${OS_NAME}" in @@ -62,12 +49,13 @@ elif [[ -f /etc/os-release ]]; then OS_NAME="ubuntu" ;; esac - OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') else OS_NAME="unknown" OS_VERSION="0.0" fi +VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1) +VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2) OS_VERSION_STR=${OS_VERSION//./_} # Add OS specific defines @@ -96,8 +84,8 @@ case "${OS_NAME}" in esac # Add OS specific compile flags -append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1)" -append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2)" +append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=${VERSION_MAJOR}" +append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=${VERSION_MINOR}" # Add additional OS specific configurations case "${OS_NAME}" in @@ -115,10 +103,10 @@ case "${OS_NAME}" in ;; "rhel") append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" - if [[ "${RHEL_MAJOR}" == "7" ]]; then + if [[ "${VERSION_MAJOR}" == "7" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" append_mk "-include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" - elif [[ "${RHEL_MAJOR}" == "8" ]]; then + elif [[ "${VERSION_MAJOR}" == "8" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" fi ;; From 2fdd7d73f7159e43527e81dd95561aa1d763ff44 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 17 Feb 2025 11:07:38 +0800 Subject: [PATCH 1428/2070] drm/amdkcl: test time64_to_tm() is available It's caused by the commit: 705048fb "drm/amdgpu: Get timestamp from system time" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c | 144 ++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 | 17 +++ include/kcl/kcl_time.h | 13 ++ 7 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 create mode 100644 include/kcl/kcl_time.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6b4d598138cac..7672f3fe2b06a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c b/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c new file mode 100644 index 0000000000000..a32d8dd1a0c6e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: LGPL-2.0+ +/* +* Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. +* This file is part of the GNU C Library. +* Contributed by Paul Eggert (eggert@twinsun.com). +* +* The GNU C Library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Library General Public License as +* published by the Free Software Foundation; either version 2 of the +* License, or (at your option) any later version. +* +* The GNU C Library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Library General Public License for more details. +* +* You should have received a copy of the GNU Library General Public +* License along with the GNU C Library; see the file COPYING.LIB. If not, +* write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +* Boston, MA 02111-1307, USA. +*/ + +/* +* Converts the calendar time to broken-down time representation +* +* 2009-7-14: +* Moved from glibc-2.6 to kernel by Zhaolei +* 2021-06-02: +* Reimplemented by Cassio Neri +*/ + +#ifndef HAVE_TIME64_TO_TM +#include +#include +#include +#include + +#define SECS_PER_HOUR (60 * 60) +#define SECS_PER_DAY (SECS_PER_HOUR * 24) + +/** + * time64_to_tm - converts the calendar time to local broken-down time + * + * @totalsecs: the number of seconds elapsed since 00:00:00 on January 1, 1970, + * Coordinated Universal Time (UTC). +* @offset: offset seconds adding to totalsecs. +* @result: pointer to struct tm variable to receive broken-down time +*/ +void time64_to_tm(time64_t totalsecs, int offset, struct tm *result) +{ + u32 u32tmp, day_of_century, year_of_century, day_of_year, month, day; + u64 u64tmp, udays, century, year; + bool is_Jan_or_Feb, is_leap_year; + long days, rem; + int remainder; + + days = div_s64_rem(totalsecs, SECS_PER_DAY, &remainder); + rem = remainder; + rem += offset; + while (rem < 0) { + rem += SECS_PER_DAY; + --days; + } + while (rem >= SECS_PER_DAY) { + rem -= SECS_PER_DAY; + ++days; + } + + result->tm_hour = rem / SECS_PER_HOUR; + rem %= SECS_PER_HOUR; + result->tm_min = rem / 60; + result->tm_sec = rem % 60; + + /* January 1, 1970 was a Thursday. */ + result->tm_wday = (4 + days) % 7; + if (result->tm_wday < 0) + result->tm_wday += 7; + + /* + * The following algorithm is, basically, Proposition 6.3 of Neri + * and Schneider [1]. In a few words: it works on the computational + * (fictitious) calendar where the year starts in March, month = 2 + * (*), and finishes in February, month = 13. This calendar is + * mathematically convenient because the day of the year does not + * depend on whether the year is leap or not. For instance: + * + * March 1st 0-th day of the year; + * ... + * April 1st 31-st day of the year; + * ... + * January 1st 306-th day of the year; (Important!) + * ... + * February 28th 364-th day of the year; + * February 29th 365-th day of the year (if it exists). + * + * After having worked out the date in the computational calendar + * (using just arithmetics) it's easy to convert it to the + * corresponding date in the Gregorian calendar. + * + * [1] "Euclidean Affine Functions and Applications to Calendar + * Algorithms". https://arxiv.org/abs/2102.06959 + * + * (*) The numbering of months follows tm more closely and thus, + * is slightly different from [1]. + */ + + udays = ((u64) days) + 2305843009213814918ULL; + + u64tmp = 4 * udays + 3; + century = div64_u64_rem(u64tmp, 146097, &u64tmp); + day_of_century = (u32) (u64tmp / 4); + + u32tmp = 4 * day_of_century + 3; + u64tmp = 2939745ULL * u32tmp; + year_of_century = upper_32_bits(u64tmp); + day_of_year = lower_32_bits(u64tmp) / 2939745 / 4; + + year = 100 * century + year_of_century; + is_leap_year = year_of_century ? !(year_of_century % 4) : !(century % 4); + + u32tmp = 2141 * day_of_year + 132377; + month = u32tmp >> 16; + day = ((u16) u32tmp) / 2141; + + /* + * Recall that January 1st is the 306-th day of the year in the + * computational (not Gregorian) calendar. + */ + is_Jan_or_Feb = day_of_year >= 306; + + /* Convert to the Gregorian calendar and adjust to Unix time. */ + year = year + is_Jan_or_Feb - 6313183731940000ULL; + month = is_Jan_or_Feb ? month - 12 : month; + day = day + 1; + day_of_year += is_Jan_or_Feb ? -306 : 31 + 28 + is_leap_year; + + /* Convert to tm's format. */ + result->tm_year = (long) (year - 1900); + result->tm_mon = (int) month; + result->tm_mday = (int) day; + result->tm_yday = (int) day_of_year; +} +EXPORT_SYMBOL(time64_to_tm); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 03674a4e58521..73c3645380d93 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -133,4 +133,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 317ff0601392c..65137ab901040 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1108,6 +1108,12 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 +/* time64_to_tm() is available */ +#define HAVE_TIME64_TO_TM 1 + +/* topology_num_cores_per_package is availablea */ +#define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 + /* totalram_pages() is available */ #define HAVE_TOTALRAM_PAGES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 316b62a4848a6..ac968ee902466 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -236,6 +236,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO + AC_AMDGPU_TIME64_TO_TM AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 b/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 new file mode 100644 index 0000000000000..052fe9b7b541f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.7-rc2-4-ge6c2682a1da3 +dnl # time: Add time64_to_tm() +dnl # +AC_DEFUN([AC_AMDGPU_TIME64_TO_TM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + time64_to_tm(0, 0, NULL); + ], [time64_to_tm],[kernel/time/timeconv.c], [ + AC_DEFINE(HAVE_TIME64_TO_TM, 1, + [time64_to_tm() is available]) + + ]) + ]) +]) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h new file mode 100644 index 0000000000000..89856adc192a5 --- /dev/null +++ b/include/kcl/kcl_time.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_TIME_H +#define _KCL_TIME_H + +#include +#include +#include + +#ifndef HAVE_TIME64_TO_TM +void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); +#endif + +#endif /* _KCL_TIME_H */ From e0780a09d4f4d8c742064dde184fac25506a0fd3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 16:04:52 +0800 Subject: [PATCH 1429/2070] drm/amdkcl: unify OS compile flags Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 48 ++++--------------------- 1 file changed, 7 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index ddefbf6bed8ae..df28038e77b55 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -33,55 +33,25 @@ is_kcl_macro_defined() { grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" } +# Export OS variables if [[ -f /etc/os-release ]]; then OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') - - # Handle special cases - case "${OS_NAME}" in - "centos") - OS_NAME="custom-rhel" - ;; - "rhel") - OS_NAME="custom-rhel" - ;; - "linuxmint") - OS_NAME="ubuntu" - ;; - esac else OS_NAME="unknown" OS_VERSION="0.0" fi +append_mk "export OS_NAME=${OS_NAME}" +append_mk "export OS_VERSION=${OS_VERSION}" VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1) VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2) OS_VERSION_STR=${OS_VERSION//./_} +OS_NAME_STR=$(echo ${OS_NAME} | tr a-z A-Z) -# Add OS specific defines -case "${OS_NAME}" in - "ubuntu") - append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU" - ;; - "rhel") - append_mk "subdir-ccflags-y += -DOS_NAME_RHEL" - ;; - "steamos") - append_mk "subdir-ccflags-y += -DOS_NAME_STEAMOS" - ;; - "sled"|"sles") - append_mk "subdir-ccflags-y += -DOS_NAME_SLE" - ;; - "amzn") - append_mk "subdir-ccflags-y += -DOS_NAME_AMZ" - ;; - "debian") - append_mk "subdir-ccflags-y += -DOS_NAME_DEBIAN" - ;; - *) - append_mk "subdir-ccflags-y += -DOS_NAME_UNKNOWN" - ;; -esac +# Generate macros related to the operating system to support compilation. +# The OS name is converted to uppercase and appended as a flag, e.g., -DOS_NAME_UBUNTU, -DOS_NAME_RHEL. +append_mk "subdir-ccflags-y += -DOS_NAME_${OS_NAME_STR}" # Add OS specific compile flags append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=${VERSION_MAJOR}" @@ -112,10 +82,6 @@ case "${OS_NAME}" in ;; esac -# Export variables -append_mk "export OS_NAME=${OS_NAME}" -append_mk "export OS_VERSION=${OS_VERSION}" - if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P From 728accbcc77953adba5888a869c7a5981d46099b Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 18 Feb 2025 16:37:33 +0800 Subject: [PATCH 1430/2070] drm/amdkcl: fix the compiler error with not include drm_backport.h correctly in rhel7.9 Signed-off-by: chengjya reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index df28038e77b55..35cc0edc29944 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -75,7 +75,7 @@ case "${OS_NAME}" in append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" if [[ "${VERSION_MAJOR}" == "7" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" - append_mk "-include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" + append_mk "subdir-ccflags-y += -include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" elif [[ "${VERSION_MAJOR}" == "8" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" fi From 36227d7ae9f23242f72966516599042727aaf7d0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 18 Feb 2025 14:15:30 +0800 Subject: [PATCH 1431/2070] drm/amdkcl: test the marco define umin is available It's caused by the commit: b4930d6c "drm/amdgpu: add data write function for CPER ring" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/minmax.h | 12 ++++++++++++ include/kcl/kcl_minmax.h | 12 ++++++++++++ 5 files changed, 33 insertions(+) create mode 100644 include/kcl/header/linux/minmax.h create mode 100644 include/kcl/kcl_minmax.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 73c3645380d93..03727052579cd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -134,4 +134,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 65137ab901040..63931589ac7ef 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -858,6 +858,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MINMAX_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 661896d6ee4c2..1fc123af76d47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -149,4 +149,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #drm: Implement DRM aperture helpers under video/ dnl AC_KERNEL_CHECK_HEADERS([linux/aperture.h]) + + dnl #v5.9-7812-gb296a6d53339 + dnl #kernel.h: split out min()/max() et al. helpers + dnl + AC_KERNEL_CHECK_HEADERS([linux/minmax.h]) ]) diff --git a/include/kcl/header/linux/minmax.h b/include/kcl/header/linux/minmax.h new file mode 100644 index 0000000000000..5bc1bc525e230 --- /dev/null +++ b/include/kcl/header/linux/minmax.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_MINMAX_H +#define _KCL_HEADER_LINUX_MINMAX_H + +#ifdef HAVE_LINUX_MINMAX_H +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_minmax.h b/include/kcl/kcl_minmax.h new file mode 100644 index 0000000000000..618e166564d98 --- /dev/null +++ b/include/kcl/kcl_minmax.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_MINMAX_H +#define _KCL_MINMAX_H + +#include + +#ifndef umin +#define umin(x, y) \ + min((x) + 0u + 0ul + 0ull, (y) + 0u + 0ul + 0ull) +#endif + +#endif /* _KCL_MINMAX_H */ From 3cf826d442af403fd07adaaed1fba8a80df29526 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 19 Feb 2025 18:08:18 +0800 Subject: [PATCH 1432/2070] drm/amdkcl: fix the range of macro define HAVE_DRM_SHOW_FDINFO Signed-off-by: chengjya --- drivers/gpu/drm/amd/backport/kcl_drm_file.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index a6d0cea48cecf..1a0fb154a34c2 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -67,6 +67,7 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) amdgpu_show_fdinfo(&p, file); } +#endif #ifndef HAVE_DRM_PRINT_MEMORY_STATS static void print_size(struct drm_printer *p, const char *stat, @@ -101,5 +102,3 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, } EXPORT_SYMBOL(_kcl_drm_print_memory_stats); #endif - -#endif From b26ffdb94e547cc25af1a5b37b0d9d40d9180942 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Feb 2025 15:21:42 +0800 Subject: [PATCH 1433/2070] drm/amdkcl: move drm check to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 12 ------------ drivers/gpu/drm/amd/dkms/dkms-config.sh | 18 +++++++++++++++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index b71d645dc6264..9e50bcdaab092 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -27,18 +27,6 @@ endif include $(src)/amd/dkms/dkms-config.mk -DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) -DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) -ifeq ($(DRM_VER),) -DRM_VER = $(VERSION) -DRM_PATCH = $(PATCHLEVEL) -endif - -subdir-ccflags-y += \ - -DDRM_VER=$(DRM_VER) \ - -DDRM_PATCH=$(DRM_PATCH) \ - -DDRM_SUB="0" - _KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 35cc0edc29944..3c30f3d4735c6 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -4,7 +4,8 @@ local_config=$1 KERNELVER=$2 CC=$3 local_config_tmp=${local_config}.tmp -config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" +kernel_build_dir="/lib/modules/$KERNELVER/build" +kconfig_file="${kernel_build_dir}/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" rm -f ${local_config_tmp} @@ -22,11 +23,11 @@ _DKMS_CONFIG } get_config() { - grep "^$1=" "${config_file}" | awk -F= '{print $2}' + grep "^$1=" "${kconfig_file}" | awk -F= '{print $2}' } is_enabled() { - grep -q "^$1=" "${config_file}" + grep -q "^$1=" "${kconfig_file}" } is_kcl_macro_defined() { @@ -82,6 +83,17 @@ case "${OS_NAME}" in ;; esac +# Extract DRM version and patch level from the main Makefile +DRM_VER=$(sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' ${kernel_build_dir}/Makefile) +DRM_PATCH=$(sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' ${kernel_build_dir}/Makefile) + +if [ -z "${DRM_VER}" ]; then + DRM_VER=$(echo ${KERNELVER} | cut -d. -f1) + DRM_PATCH=$(echo ${KERNELVER} | cut -d. -f2) +fi + +append_mk "subdir-ccflags-y += -DDRM_VER=${DRM_VER} -DDRM_PATCH=${DRM_PATCH} -DDRM_SUB=\"0\"" + if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P From 8351463f491ca1b6cbb2388cf61b989b797eef08 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Feb 2025 15:26:24 +0800 Subject: [PATCH 1434/2070] drm/amdkcl: fix macro _KCL_HEADER_DRM_ELD_H_H_ Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- include/kcl/header/drm/drm_eld.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/header/drm/drm_eld.h b/include/kcl/header/drm/drm_eld.h index e531edccae0d7..e9bd6120c7b93 100644 --- a/include/kcl/header/drm/drm_eld.h +++ b/include/kcl/header/drm/drm_eld.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ #ifndef _KCL_HEADER_DRM_ELD_H_ -#define _KCL_HEADER_DRM_ELD_H_H_ +#define _KCL_HEADER_DRM_ELD_H_ #ifdef HAVE_DRM_DRM_ELD_H #include_next From 346870abb22af40d5215b4ad866dc88ffbd3d27d Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 24 Feb 2025 11:25:39 +0800 Subject: [PATCH 1435/2070] drm/amdkcl: fix the redefinetion about the struct dc_link *dc_link It's caused by the following commit: 69b01ad9e "drm/amd/display: restore edid reading from a given i2c adapter" It re-defines 'dc_link' , will conflicts with its definition in KCL. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 912b2c4078b98..8db43de966c85 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8059,10 +8059,10 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_VIRTUAL }; + struct i2c_adapter *ddc; #ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; const struct edid *edid; - struct i2c_adapter *ddc; if (dc_link && dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; @@ -8073,9 +8073,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { #else - struct dc_link *dc_link = aconnector->dc_link; struct edid *edid; - struct i2c_adapter *ddc; if (dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; From 0e8760bf9ae1d9fe26e01acf2642a8d3fc555cfe Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 24 Feb 2025 10:37:02 +0800 Subject: [PATCH 1436/2070] drm/amdkcl: Fix compilation error when CONFIG_PM is undefined When CONFIG_PM is not defined, pm_runtime_get_if_active() is not exported as a symbol but exists as an inline function. Remove the CONFIG_PM limitation in kcl_pm_runtime.h and simply include pm_runtime. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 | 8 ++++---- include/kcl/kcl_pm_runtime.h | 2 -- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 index 9615da53282ad..f694f53991e2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 @@ -4,19 +4,19 @@ dnl # PM: runtime: Add pm_runtime_get_if_active() dnl # AC_DEFUN([AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ],[ pm_runtime_get_if_active(NULL); - ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + ],[ AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS, 1, [pm_runtime_get_if_active() has one parameters]) ],[ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ],[ pm_runtime_get_if_active(NULL, 0); - ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + ],[ AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS, 1, [pm_runtime_get_if_active() has two parameters]) ]) diff --git a/include/kcl/kcl_pm_runtime.h b/include/kcl/kcl_pm_runtime.h index 54df71e7b5b24..cf5a65586fc55 100644 --- a/include/kcl/kcl_pm_runtime.h +++ b/include/kcl/kcl_pm_runtime.h @@ -24,7 +24,6 @@ static inline int pm_runtime_resume_and_get(struct device *dev) } #endif -#ifdef CONFIG_PM #if defined(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS) static inline int _kcl_pm_runtime_get_if_active(struct device *dev) { @@ -38,6 +37,5 @@ static inline int _kcl_pm_runtime_get_if_active(struct device *dev) } #define pm_runtime_get_if_active _kcl_pm_runtime_get_if_active #endif /* HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ -#endif /* CONFIG_PM */ #endif /* KCL_KCL_PM_RUNTIME_H */ \ No newline at end of file From a954b723a402c75e801b2861dce04db0761fadcf Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 24 Feb 2025 10:43:05 +0800 Subject: [PATCH 1437/2070] drm/amdkcl: Fix compilation error caused by assigning a pointer to a constant to a normal pointer Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8db43de966c85..a84514201de84 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3988,11 +3988,12 @@ void amdgpu_dm_update_connector_after_detect( drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { - const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; #ifdef HAVE_DRM_DP_MST_EDID_READ + const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); drm_edid_connector_update(connector, aconnector->drm_edid); #else + struct edid *edid = (struct edid *)sink->dc_edid.raw_edid; aconnector->edid = edid; #endif From 8d9bc0f5d166f18aeca302ece556a0c74c78f8dd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Feb 2025 15:21:47 +0800 Subject: [PATCH 1438/2070] drm/amdkcl: fix dml Makefile to support clang Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 2690778645354..e6883e2f0c325 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -49,9 +49,11 @@ endif include $(src)/../dkms/Makefile.compiler +ifdef CONFIG_CC_IS_GCC ifneq ($(call gcc-min-version, 70100),y) IS_OLD_GCC = 1 endif +endif ifdef CONFIG_X86 ifdef IS_OLD_GCC From dc8db3ca06ff9dfaf70893cc8eb8464b2a372f02 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Feb 2025 11:29:43 +0800 Subject: [PATCH 1439/2070] drm/amdkcl: fix autoconf compiler CFLAGS for clang Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index f8f51b0d19c7a..4eb72d9844e0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -13,7 +13,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") - CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-.*-variable|error=unused-.*-variable)( |$)//g') + CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') CPPFLAGS=$(echo $CFLAGS | \ cut -d ';' -f 1 | \ From 06babfb04a5be551fbb81cf436fe920bbbc767ab Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Feb 2025 18:11:57 +0800 Subject: [PATCH 1440/2070] drm/amdkcl: open CONFIG_DRM_AMD_DC_FP for clang compiler Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 9e50bcdaab092..d4ab165eeaf09 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -53,10 +53,13 @@ subdir-ccflags-y += -Wno-error # if the compiler is using core2 optimizations and only build DCN2/3 # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 -ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_FP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP -endif + ifeq ($(CC), clang) + export CONFIG_DRM_AMD_DC_FP=y + subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP + else ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) + export CONFIG_DRM_AMD_DC_FP=y + subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP + endif endif # v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) From 9727fbcdc82ad946a2b352e6289e332b89016b13 Mon Sep 17 00:00:00 2001 From: tiancyin Date: Thu, 27 Feb 2025 15:40:16 +0800 Subject: [PATCH 1441/2070] drm/amdgpu: [hybrid] disable dGMA when iommu is enabled and not in PT mode [why] In direct GMA(peer to peer vram access), the initiator GPU's PTE is populated with system physical address, which should be IOVA(from dma_map_page). Just disable the dGMA when IOMMU is enabled and not in pass through mode. Reviewed-by: Flora Cui Signed-off-by: tiancyin --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 36b5ca860842a..b4433c1865694 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2176,6 +2176,14 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) unsigned long size; int r; + if (amdgpu_direct_gma_size > 0) { + struct iommu_domain *dom = iommu_get_domain_for_dev(adev->dev); + if (dom && domain->type != IOMMU_DOMAIN_IDENTITY) { + DRM_INFO("IOMMU is enabled and not in pass through mode, disable direct GMA\n"); + amdgpu_direct_gma_size = 0; + } + } + if (amdgpu_direct_gma_size == 0) return 0; From f1684ccf278388feee1bb59c560f276067146aec Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 27 Feb 2025 18:18:26 +0800 Subject: [PATCH 1442/2070] drm/amdkcl : Corrected the usage of an incorrect variable name It's caused by the following commit: 3529abc32 "drm/amdgpu: [hybrid] disable dGMA when iommu is enabled and not in PT mode" Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index b4433c1865694..764053cce393c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2178,7 +2178,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) if (amdgpu_direct_gma_size > 0) { struct iommu_domain *dom = iommu_get_domain_for_dev(adev->dev); - if (dom && domain->type != IOMMU_DOMAIN_IDENTITY) { + if (dom && dom->type != IOMMU_DOMAIN_IDENTITY) { DRM_INFO("IOMMU is enabled and not in pass through mode, disable direct GMA\n"); amdgpu_direct_gma_size = 0; } From d855bd5d631ed75235a740dc57de494164b85eff Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 26 Nov 2024 11:08:02 -0500 Subject: [PATCH 1443/2070] drm/amdkfd: update cwsr trap handler to support both Host Trap and Stochastic PC sampling running simultaneously. -v2: read register HW_REG_TRAPSTS to check TRAPSTS_PERF_SNAPSHOT Co-developed-by: Lancelot SIX Co-developed-by: Joseph Greathouse Signed-off-by: James Zhu Reviewed-by: Shweta Khatri --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2798 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 71 +- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 +- 3 files changed, 1467 insertions(+), 1405 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 98061af544db2..077885df30fb9 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,13 +274,13 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820267, + 0xbf820001, 0xbf820268, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, - 0x00000400, 0xbf850065, + 0x00000400, 0xbf850066, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03800900, 0xbf850019, @@ -296,7 +296,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x00000800, 0xbf850005, 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -309,230 +309,187 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e799779, - 0x8977ff77, 0x01800000, + 0x8977ff77, 0x03800000, 0x87777977, 0xbf0d986d, - 0xbf840009, 0xbf0d9877, - 0xbf850007, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef71898, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b77, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2a05, 0x807a817a, - 0x8e7a8a7a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2a05, + 0x807a817a, 0x8e7a8a7a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840063, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84005f, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840063, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84005f, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -551,145 +508,188 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850051, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbf8200c7, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001e, - 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf840019, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, - 0xbefe00c1, 0xbeff00c1, - 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbf8200c7, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001e, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf840019, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, + 0x8078ff78, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, -}; - -static const uint32_t cwsr_trap_nv1x_hex[] = { - 0xbf820001, 0xbf820393, - 0xb0804004, 0xb978f802, - 0x8a78ff78, 0x00020006, - 0xb97bf803, 0x876eff78, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, +}; + +static const uint32_t cwsr_trap_nv1x_hex[] = { + 0xbf820001, 0xbf820393, + 0xb0804004, 0xb978f802, + 0x8a78ff78, 0x00020006, + 0xb97bf803, 0x876eff78, 0x00002000, 0xbf840009, 0x876eff6d, 0x00ff0000, 0xbf85001e, 0x876eff7b, @@ -1310,13 +1310,13 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202e3, + 0xbf820001, 0xbf8202e4, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, - 0x00000400, 0xbf850065, + 0x00000400, 0xbf850066, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03800900, 0xbf850019, @@ -1332,7 +1332,7 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x00000800, 0xbf850005, 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1345,232 +1345,189 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e799779, - 0x8977ff77, 0x01800000, + 0x8977ff77, 0x03800000, 0x87777977, 0xbf0d986d, - 0xbf840009, 0xbf0d9877, - 0xbf850007, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef71898, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b77, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2a05, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2a05, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1589,222 +1546,265 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850051, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbefc0080, 0xbf11017c, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, - 0xd2890000, 0x00000900, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200e3, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200e3, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbefc0080, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ee, + 0xbf820001, 0xbf8202ef, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, - 0x00000400, 0xbf850065, + 0x00000400, 0xbf850066, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03800900, 0xbf850019, @@ -1820,7 +1820,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000800, 0xbf850005, 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1833,188 +1833,126 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e799779, - 0x8977ff77, 0x01800000, + 0x8977ff77, 0x03800000, 0x87777977, 0xbf0d986d, - 0xbf840009, 0xbf0d9877, - 0xbf850007, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef71898, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b77, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2985, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, 0xb8f02985, 0x80708170, 0x8e708a70, 0x8e708170, 0xb8fa1605, 0x807a817a, 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bba, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bfa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2034,31 +1972,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2077,51 +2034,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2161,139 +2098,202 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, + 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, - 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, - 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, - 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, - 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, - 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, + 0x00000078, 0x80788478, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, + 0x00000078, 0x80788478, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, + 0x00000078, 0x80788478, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, + 0x00000078, 0x80788478, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, + 0x00000078, 0x80788478, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3175,27 +3175,29 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202ea, + 0xbf820001, 0xbf8202fa, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840008, 0xbf0d986d, - 0xbf85001f, 0x866eff7b, - 0x00000400, 0xbf850061, + 0xbf84000a, 0xbf0d986d, + 0xbf850023, 0xbf0d9a7b, + 0xbf850021, 0x866eff7b, + 0x00000400, 0xbf85006f, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, - 0x03800900, 0xbf850015, + 0x03800900, 0xbf850017, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0xbf0d986d, + 0xbf85000c, 0xbf0d986d, 0xbf850003, 0x866eff6d, - 0x00ff0000, 0xbf850005, - 0xbf0d986d, 0xbf850004, + 0x00ff0000, 0xbf850007, + 0xbf0d986d, 0xbf850006, + 0xbf0d9a7b, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850052, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -3208,14 +3210,20 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e739773, - 0x8979ff79, 0x01800000, + 0x8979ff79, 0x03800000, 0x87797379, 0xbf0d986d, - 0xbf840009, 0xbf0d9879, - 0xbf850007, 0x896dff6d, + 0xbf840008, 0xbf0d9879, + 0xbf840002, 0xbeed1a9d, + 0xbf820004, 0x896dff6d, 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef91898, 0xbeed189d, + 0x00000000, 0xb8f3f803, + 0xbf0d9a73, 0xbf840006, + 0xbf0d9979, 0xbf840002, + 0xbeed1a9d, 0xbf820002, + 0xba7f0683, 0x00000000, + 0xbf0d9d6d, 0xbeed189d, + 0xbf840013, 0xbef91898, + 0xbef91899, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -4131,25 +4139,29 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202c9, + 0xbf820001, 0xbf8202e8, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0xbf84000a, 0xbf0d986d, + 0xbf850023, 0xbf0d9a7b, + 0xbf850021, 0x866eff7b, + 0x00000400, 0xbf85006f, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850017, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000c, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xbf0d986d, 0xbf850006, + 0xbf0d9a7b, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, - 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850052, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -4158,187 +4170,136 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031cfd, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b79, - 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0xbf8cc07f, 0x8e739773, + 0x8979ff79, 0x03800000, + 0x87797379, 0xbf0d986d, + 0xbf840008, 0xbf0d9879, + 0xbf840002, 0xbeed1a9d, + 0xbf820004, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xb8f3f803, + 0xbf0d9a73, 0xbf840006, + 0xbf0d9979, 0xbf840002, + 0xbeed1a9d, 0xbf820002, + 0xba7f0683, 0x00000000, + 0xbf0d9d6d, 0xbeed189d, + 0xbf840013, 0xbef91898, + 0xbef91899, 0xbeed189d, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b79, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb5306, - 0x867bc17b, 0xbf840052, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84004e, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85001d, 0x24040682, - 0xd86c0000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4348,95 +4309,94 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000100, - 0xd0c9006a, 0x0000f702, - 0xbf87ffe5, 0xbf820016, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbefe016a, - 0xbf87fff6, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb5306, 0x867bc17b, + 0xbf840052, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84004e, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85001d, + 0x24040682, 0xd86c0000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000100, 0xd0c9006a, + 0x0000f702, 0xbf87ffe5, + 0xbf820016, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbefe016a, 0xbf87fff6, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4475,142 +4435,206 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200f4, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf840025, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200f4, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf840025, 0xbefe00c1, + 0xbeff00c1, 0xb8ef5306, + 0x866fc16f, 0xbf840020, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0xe0510200, 0x781d0000, + 0xe0510300, 0x781d0000, + 0xe0510400, 0x781d0000, + 0x807cff7c, 0x00000500, + 0x8078ff78, 0x00000500, + 0xbf0a6f7c, 0xbf85fff0, 0xbefe00c1, 0xbeff00c1, - 0xb8ef5306, 0x866fc16f, - 0xbf840020, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0xe0510200, - 0x781d0000, 0xe0510300, - 0x781d0000, 0xe0510400, - 0x781d0000, 0x807cff7c, - 0x00000500, 0x8078ff78, - 0x00000500, 0xbf0a6f7c, - 0xbf85fff0, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 8014b010654cf..96b80284ba386 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -113,6 +113,8 @@ var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 +var SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK = 0x4000000 +var SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT = 26 var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 @@ -129,7 +131,9 @@ var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 var TTMP_HOST_TRAP_ENABLED_SHIFT = 24 var TTMP_HOST_TRAP_ENABLED_MASK = 0x1000000 var TTMP_FEATURES_ENABLED_FLAGS_SHIFT = TTMP_DEBUG_TRAP_ENABLED_SHIFT -var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK +var TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT = 25 +var TTMP_STOCHASTIC_TRAP_ENABLED_MASK = 0x2000000 +var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK | TTMP_STOCHASTIC_TRAP_ENABLED_MASK /* Save */ var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes @@ -137,10 +141,10 @@ var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 var S_SAVE_PC_HI_HT_MASK = 0x01000000 var S_SAVE_PC_HI_HT_SHIFT = 24 -var S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP = 29 // Only used by the 1st level trap handler to remember if - // we saw a trap type that the driver could not mask, so that - // we can still go to the 2nd-level handler if we driver-mask another - // simultaneous trap. +var S_SAVE_PC_HI_NEED_2ND_LVL_TH = 29 // Only used by the 1st level trap handler to remember if + // we saw a trap type that the driver could not mask, or + // a maskable trap that should not be masked. This is + // indicates that we must go to the 2nd level trap handler. var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 @@ -245,6 +249,10 @@ L_HALTED: // Host trap may occur while wave is halted. s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_bitcmp1_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#endif L_CHECK_SAVE: s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save @@ -311,11 +319,17 @@ end s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // Check for perf snapshot + s_bitcmp1_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#endif + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: - s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH L_FETCH_2ND_TRAP_DRIVER_MASKABLE: // Preserve and clear scalar XNACK state before issuing scalar reads. save_and_clear_ib_sts(ttmp14) @@ -336,8 +350,8 @@ L_NO_SIGN_EXTEND_TMA: s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - // Put debug enable bit and host trap bit into SAVE_IB_STS register, bits - // 23 and 24, respectively. + // Put debug enable bit, stochastic trap bit, and host trap bit into SAVE_IB_STS register, bits + // 23-25, respectively s_lshl_b32 s_tma_flags, s_tma_flags, TTMP_FEATURES_ENABLED_FLAGS_SHIFT s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_FEATURES_ENABLED_FLAGS_MASK s_or_b32 s_save_ib_sts, s_save_ib_sts, s_tma_flags @@ -345,28 +359,51 @@ L_NO_SIGN_EXTEND_TMA: // If not a host trap, then driver cannot mask this. Go to the 2nd-level // trap handler now. s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT - s_cbranch_scc0 L_GOTO_2ND_TRAP + s_cbranch_scc0 L_CHECK_STOC // If driver said host traps are OK, go to the 2nd-level handler now. s_bitcmp1_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT - s_cbranch_scc1 L_GOTO_2ND_TRAP + s_cbranch_scc0 L_MASKED_HT + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_branch L_CHECK_STOC +L_MASKED_HT: // The driver said host traps are masked, zero out host trap and trapID. s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) +#if ASIC_FAMILY >= CHIP_GC_9_4_3 s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0x0 +#endif + +L_CHECK_STOC: +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // If TRAPSTS says we did not have a stochastic sampling trap, then driver cannot mask this + s_getreg_b32 ttmp7, hwreg(HW_REG_TRAPSTS) + s_bitcmp1_b32 ttmp7, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc0 L_CHECK_REMAINING_EXCP + // If stochastic sampling trap was requested, should it be masked by the driver? + s_bitcmp1_b32 s_save_ib_sts, TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT + // If driver said stochastic traps are OK, allow the 2nd-level handler to take host trap + s_cbranch_scc0 L_MASKED_STOC + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_branch L_CHECK_REMAINING_EXCP + +L_MASKED_STOC: + // Otherwise, zero out TRAPSTS.stochastic_perf_snapshot bit, so possible 2nd level does not handle it + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT, 1), 0x0 +#endif - // If there was another trap besides this masked host trap, go handle it in - // 2nd-level handler. - s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP - s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP // zero this out - s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler +L_CHECK_REMAINING_EXCP: + // Check if we found any reason to go to the 2nd level trap handler. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH // zero this out + s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler L_GOTO_2ND_TRAP: // Reset bits used temporarily by 1st level trap handler so they do not // leak to the 2nd level trap handler. s_bitset0_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT - s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP - + s_bitset0_b32 s_save_ib_sts, TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 7573eb3f88cbe..1f6342ea5c547 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -36,9 +36,10 @@ * 0.3 - Fix gfx9_4_3 SQ hang issue * 1.1 - Support gfx9_4_3 Stochastic PC sampling * 1.2 - Support gfx9_5_0 Host Trap PC sampling + * 1.3 - Update 1st level trap handler for Stochastic PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 3 struct supported_pc_sample_info { uint32_t ip_version; From 7713b03146c71b249f4d196f1fad0489ac6bcfd5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Feb 2025 12:42:15 +0800 Subject: [PATCH 1444/2070] drm/amdkcl: Optimize configuration management in dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 39 ++++++++++++++++++++----- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 3c30f3d4735c6..efe7089df9c36 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -3,21 +3,32 @@ local_config=$1 KERNELVER=$2 CC=$3 -local_config_tmp=${local_config}.tmp kernel_build_dir="/lib/modules/$KERNELVER/build" kconfig_file="${kernel_build_dir}/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" +local_config_tmp=${local_config}.tmp +disabled_config_tmp=${local_config}.disabled.tmp -rm -f ${local_config_tmp} +echo "" > ${local_config_tmp} +echo "" > ${disabled_config_tmp} append_mk () { echo $1 >> ${local_config_tmp} } -export_macro_mk () { -cat <<_DKMS_CONFIG >> ${local_config_tmp} -export $1=y -subdir-ccflags-y += -D$1 +export_macro_mk() { + local config_name=$1 + local enable=${2:-1} + + if [ "$enable" -eq 1 ]; then + output=${local_config_tmp} + else + output=${disabled_config_tmp} + fi + + cat <<_DKMS_CONFIG >> ${output} +export ${config_name}=y +subdir-ccflags-y += -D${config_name} _DKMS_CONFIG } @@ -94,18 +105,23 @@ fi append_mk "subdir-ccflags-y += -DDRM_VER=${DRM_VER} -DDRM_PATCH=${DRM_PATCH} -DDRM_SUB=\"0\"" +# Check for P2PDMA configuration +_enable=0 if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then - export_macro_mk CONFIG_HSA_AMD_P2P + _enable=1 fi fi +export_macro_mk CONFIG_HSA_AMD_P2P ${_enable} # Check for HMM mirror configuration +_enable=0 if [[ "$(is_kcl_macro_defined HAVE_AMDKCL_HMM_MIRROR_ENABLED)" == "y" ]]; then if is_enabled CONFIG_DEVICE_PRIVATE; then - export_macro_mk CONFIG_HSA_AMD_SVM + _enable=1 fi fi +export_macro_mk CONFIG_HSA_AMD_SVM ${_enable} export_macro_mk CONFIG_HSA_AMD export_macro_mk CONFIG_DRM_AMDGPU_CIK @@ -113,5 +129,12 @@ export_macro_mk CONFIG_DRM_AMDGPU_SI export_macro_mk CONFIG_DRM_AMDGPU_USERPTR export_macro_mk CONFIG_DRM_AMD_DC +echo "Enabled configurations:" cat ${local_config_tmp} +echo "****************" +echo "Disabled configurations:" +cat ${disabled_config_tmp} +echo "****************" + +rm -f ${disabled_config_tmp} mv ${local_config_tmp} ${local_config} From 7d89b6186336fe99cdebf352fc70cbc8be5ec433 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 7 Mar 2025 22:06:54 +0800 Subject: [PATCH 1445/2070] drm/amdkcl: fake linux/cgroup_dmem.h It's caused by v6.13-rc6-1-gb168ed458dde kernel/cgroup: Add "dmem" memory accounting cgroup v6.13-rc6-3-g2b624a2c1865 drm/ttm: Handle cgroup based eviction in TTM Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/header/linux/cgroup_dmem.h | 10 ++++ include/kcl/kcl_cgroup_dmem.h | 51 ++++++++++++++++++++ 4 files changed, 67 insertions(+) create mode 100644 include/kcl/header/linux/cgroup_dmem.h create mode 100644 include/kcl/kcl_cgroup_dmem.h diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 1fc123af76d47..d7942c5fa0573 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -154,4 +154,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kernel.h: split out min()/max() et al. helpers dnl AC_KERNEL_CHECK_HEADERS([linux/minmax.h]) + + dnl #v6.13-rc6-1-gb168ed458dde + dnl #kernel/cgroup: Add "dmem" memory accounting cgroup + dnl + AC_KERNEL_CHECK_HEADERS([linux/cgroup_dmem.h]) ]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index f9e3e75824090..5e944f8950bbb 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -21,5 +21,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/header/linux/cgroup_dmem.h b/include/kcl/header/linux/cgroup_dmem.h new file mode 100644 index 0000000000000..11cbf3b03d712 --- /dev/null +++ b/include/kcl/header/linux/cgroup_dmem.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CGROUP_DMEM_H +#define _KCL_HEADER_LINUX_CGROUP_DMEM_H + +#ifdef HAVE_LINUX_CGROUP_DMEM_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_cgroup_dmem.h b/include/kcl/kcl_cgroup_dmem.h new file mode 100644 index 0000000000000..772e06860ca11 --- /dev/null +++ b/include/kcl/kcl_cgroup_dmem.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/ipc/util.c + * Copyright (C) 1992 Krishna Balasubramanian + * For kvmalloc/kvzalloc + */ +#ifndef AMDKCL_CGROUP_DMEM_H +#define AMDKCL_CGROUP_DMEM_H + +#ifndef HAVE_LINUX_CGROUP_DMEM_H +struct dmem_cgroup_pool_state; + +/* Opaque definition of a cgroup region, used internally */ +struct dmem_cgroup_region; +static inline __printf(2,3) struct dmem_cgroup_region * +dmem_cgroup_register_region(u64 size, const char *name_fmt, ...) +{ + return NULL; +} + +static inline void dmem_cgroup_unregister_region(struct dmem_cgroup_region *region) +{ } + +static inline int dmem_cgroup_try_charge(struct dmem_cgroup_region *region, u64 size, + struct dmem_cgroup_pool_state **ret_pool, + struct dmem_cgroup_pool_state **ret_limit_pool) +{ + *ret_pool = NULL; + + if (ret_limit_pool) + *ret_limit_pool = NULL; + + return 0; +} + +static inline void dmem_cgroup_uncharge(struct dmem_cgroup_pool_state *pool, u64 size) +{ } + +static inline +bool dmem_cgroup_state_evict_valuable(struct dmem_cgroup_pool_state *limit_pool, + struct dmem_cgroup_pool_state *test_pool, + bool ignore_low, bool *ret_hit_low) +{ + return true; +} + +static inline void dmem_cgroup_pool_state_put(struct dmem_cgroup_pool_state *pool) +{ } +#endif /*HAVE_LINUX_CGROUP_DMEM_H*/ + +#endif From c181bad0b26eb9c5af0ee949228de299e2fd8936 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 15 Mar 2025 15:47:19 +0800 Subject: [PATCH 1446/2070] drm/amdkcl: test whether drm_memory_stats_is_zero exits It's caused by v6.13-rc2-231-gfd265d9e0c33 drm: add drm_memory_stats_is_zero v6.13-rc2-235-g74ef9527bd87 drm/amdgpu: track bo memory stats at runtime Signed-off-by: Asher Song --- .../amd/backport/include/kcl/kcl_drm_file.h | 4 ++ drivers/gpu/drm/amd/backport/kcl_drm_file.c | 11 +++++ drivers/gpu/drm/amd/dkms/m4/drm-file.m4 | 42 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- 4 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-file.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index 91ea254aa7434..435dcf5ceea08 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -25,4 +25,8 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, #define drm_print_memory_stats _kcl_drm_print_memory_stats; #endif +#ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO +int drm_memory_stats_is_zero(const struct drm_memory_stats *stats); +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index 1a0fb154a34c2..e28ba0dd163d4 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -102,3 +102,14 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, } EXPORT_SYMBOL(_kcl_drm_print_memory_stats); #endif + +#ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO +int drm_memory_stats_is_zero(const struct drm_memory_stats *stats) +{ + return (stats->shared == 0 && + stats->private == 0 && + stats->resident == 0 && + stats->purgeable == 0 && + stats->active == 0); +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 new file mode 100644 index 0000000000000..8e907a5616852 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit fd265d9e0c3358e6 +dnl # drm: add drm_memory_stats_is_zero +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMORY_STATS_IS_ZERO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memory_stats_is_zero(NULL); + ], [ + AC_DEFINE(HAVE_DRM_MEMORY_STATS_IS_ZERO, 1, + [drm_memory_stats_is_zero() is available]) + ]) + ]) +]) + +dnl # +dnl # commit fd265d9e0c3358e6 +dnl # drm: add drm_memory_stats_is_zero +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_memory_stats *stats; + stats = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_MEMORY_STATS, 1, + [struct drm_memory_stats is defined]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MEMORY_STATS], [ + AC_AMDGPU_DRM_MEMORY_STATS_IS_ZERO + AC_AMDGPU_STRUCT_DRM_MEMORY_STATS +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ac968ee902466..75058b61290f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -237,7 +237,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO AC_AMDGPU_TIME64_TO_TM - + AC_AMDGPU_DRM_MEMORY_STATS + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" From bb44e58d7d93691cbe8cda6593c712bb1b526b62 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 9 Mar 2025 11:42:29 +0800 Subject: [PATCH 1447/2070] drm/amdkcl: test fd_empty whether exist It's caused by v6.11-rc1-2-g88a2f6468d01 struct fd: representation change v6.12-rc2-14-g6348be02eead fdget(), trivial conversions Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 | 20 ++++++++++++++++++++ include/kcl/kcl_file.h | 7 +++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 index 07011778633f9..f025643ea5b56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 @@ -16,6 +16,26 @@ AC_DEFUN([AC_AMDGPU_FILE_OPERATION_FOP_FLAGS], [ ]) ]) +dnl # +dnl # commit v6.11-rc1-2-g88a2f6468d01 +dnl # struct fd: representation change +dnl # +AC_DEFUN([AC_AMDGPU_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct fd f; + f.word = 0; + fd_empty(f); + ],[ + AC_DEFINE(HAVE_FD_EMPTY, 1, + [fd_empty is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_FILE_OPERATION], [ AC_AMDGPU_FILE_OPERATION_FOP_FLAGS + AC_AMDGPU_FD ]) diff --git a/include/kcl/kcl_file.h b/include/kcl/kcl_file.h index 2b81dc3f31644..4c8a92d981141 100644 --- a/include/kcl/kcl_file.h +++ b/include/kcl/kcl_file.h @@ -8,4 +8,11 @@ #define fd_file(f) ((f).file) #endif +#ifndef HAVE_FD_EMPTY +static inline bool fd_empty(struct fd f) +{ + return !fd_file(f); +} +#endif + #endif From 381c2a3b95eeba745e56394d6ecadc61599135b7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 13:48:19 +0800 Subject: [PATCH 1448/2070] drm/amdkcl: test the argument in attribut callback of bin_is_visible wether is constant It's caused by v6.12-rc6-16-gb626816fdd7f sysfs: treewide: constify attribute callback of bin_is_visible() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_attribute_group.m4 | 27 +++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index f324c736e50e1..4c7cdaf90db6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4340,7 +4340,10 @@ static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribu } static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, - const struct bin_attribute *attr, +#ifdef HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE + const +#endif + struct bin_attribute *attr, int idx) { struct device *dev = kobj_to_dev(kobj); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 75058b61290f7..126e0ebfcb5e4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 new file mode 100644 index 0000000000000..b61c1e580fd07 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit v6.12-rc6-16-gb626816fdd7f +dnl # sysfs: treewide: constify attribute callback of bin_is_visible() +dnl # +AC_DEFUN([AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + static umode_t amdgpu_bin_attr_is_visible(struct kobject *kobj, + const struct bin_attribute *attr, + int idx) + { + return 0; + } + struct attribute_group amdgpu_attr_group = { + .is_bin_visible = amdgpu_bin_attr_is_visible, + }; + + ],[ + (void)amdgpu_attr_group; + ],[ + AC_DEFINE(HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE, 1, + [need a const argument in member func .is_bin_visible]) + ]) + ]) +]) From c02012e121f2cad3fd82926bd04ffddd708cc9b7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 17:39:51 +0800 Subject: [PATCH 1449/2070] drm/amdkcl: test drm_connector_dynamic_init whether exits It's caused by v6.13-rc2-201-g1d985ddabbe0 drm/connector: Add a way to init/add a connector in separate steps Signed-off-by: Asher Song --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 18 ++++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 ++- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 870700f436229..1ef14ac1240b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -760,12 +760,20 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_PROBE, true); +#ifdef HAVE_DRM_CONNECTOR_DYNAMIC_INIT if (drm_connector_dynamic_init( +#else + if (drm_connector_init( +#endif dev, connector, &dm_dp_mst_connector_funcs, +#ifdef HAVE_DRM_CONNECTOR_DYNAMIC_INIT DRM_MODE_CONNECTOR_DisplayPort, NULL)) { +#else + DRM_MODE_CONNECTOR_DisplayPort)) { +#endif kfree(aconnector); return NULL; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 653c3e1e1ec98..34702411114b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -16,5 +16,19 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ ]) ]) - - +dnl # +dnl # v6.13-rc2-201-g1d985ddabbe0 +dnl # drm/connector: Add a way to init/add a connector in separate steps +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_dynamic_init(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_DYNAMIC_INIT, 1, + [drm_connector_dynamic_init is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 126e0ebfcb5e4..1e0463ea17b7a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -238,7 +238,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO AC_AMDGPU_TIME64_TO_TM - AC_AMDGPU_DRM_MEMORY_STATS + AC_AMDGPU_DRM_MEMORY_STATS + AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 5050502d1e95cfeeacc55bfa11a96c74b770878e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 18:19:59 +0800 Subject: [PATCH 1450/2070] drm/amdkcl: test drm_connector->eld_mutex whether exist It's caused by v6.13-rc2-179-gdf7c8e3dde37 drm/connector: add mutex to protect ELD from concurrent access Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++- drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a84514201de84..a39f116094487 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1141,11 +1141,14 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, continue; *enabled = true; +#ifdef HAVE_DRM_CONNECTOR_ELD_MUTEX mutex_lock(&connector->eld_mutex); +#endif ret = drm_eld_size(connector->eld); memcpy(buf, connector->eld, min(max_bytes, ret)); +#ifdef HAVE_DRM_CONNECTOR_ELD_MUTEX mutex_unlock(&connector->eld_mutex); - +#endif break; } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 34702411114b7..01791b2a42e79 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -16,6 +16,29 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ ]) ]) +dnl # +dnl # v6.13-rc2-179-gdf7c8e3dde37 +dnl # drm/connector: add mutex to protect ELD from concurrent access +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ELD_MUTEX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector connector; + void *ptr = &connector.eld_mutex; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_ELD_MUTEX, 1, + [drm_connector->eld_mutex is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STRUCT_MEMBER], [ + AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE + AC_AMDGPU_DRM_CONNECTOR_ELD_MUTEX +]) + dnl # dnl # v6.13-rc2-201-g1d985ddabbe0 dnl # drm/connector: Add a way to init/add a connector in separate steps diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1e0463ea17b7a..ababa733954be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -84,7 +84,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS - AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE + AC_AMDGPU_DRM_CONNECTOR_STRUCT_MEMBER AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From 195900de1604ef46e414bb7d9ffc1ccd33f684c7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 25 Mar 2025 16:56:27 +0800 Subject: [PATCH 1451/2070] drm/amdkcl: test macro MODULE_IMPORT_NS whether need a string argument It's caused by v6.13-rc1-2-gcdd30ebb1b9f module: Convert symbol namespace to string literal Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 | 15 +++++++++++++++ 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 764053cce393c..cc06e430c5c53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -64,7 +64,11 @@ #include "amdgpu_res_cursor.h" #include "bif/bif_4_1_d.h" +#ifdef HAVE_MODULE_IMPORT_NS_NEED_A_STRING MODULE_IMPORT_NS("DMA_BUF"); +#else +MODULE_IMPORT_NS(DMA_BUF); +#endif #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ababa733954be..444d2807ea8be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -240,6 +240,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TIME64_TO_TM AC_AMDGPU_DRM_MEMORY_STATS AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT + AC_AMDGPU_MODULE_IMPORT_NS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 b/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 new file mode 100644 index 0000000000000..bdc84e5d287c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v6.13-rc1-2-gcdd30ebb1b9f +dnl # module: Convert symbol namespace to string literal +dnl # +AC_DEFUN([AC_AMDGPU_MODULE_IMPORT_NS], [ + AC_KERNEL_DO_BACKGROUND([ + header_file_src=$LINUX/include/linux/module.h + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -qE '^#define MODULE_IMPORT_NS\(ns\)\s+MODULE_INFO\(import_ns, ns\)$' $header_file_src ], [ + AC_DEFINE(HAVE_MODULE_IMPORT_NS_NEED_A_STRING, 1, + [MODULE_IMPORT_NS() wants a string arguments]) + ]) + ]) + ]) +]) From fb5e08f8f8c0f485a8a43a9797c61ec65f966afe Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 3 Mar 2025 16:32:35 +0800 Subject: [PATCH 1452/2070] drm/amdkcl: fake the macro defintion DP_EDP_MSO_LINK_CAPABILITIES It' caused by the following commit: 23746f2b6 "drm/amd/display: read mso dpcd caps" Signed-off-by: chengjya --- include/kcl/kcl_drm_dp.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 7f3607f89c6a4..80f2aecf50394 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -84,4 +84,8 @@ #define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ #endif +#ifndef DP_EDP_MSO_LINK_CAPABILITIES +#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ +#endif + #endif \ No newline at end of file From c599e2a8ffa7d23b6a3bcc538528299539e27bb1 Mon Sep 17 00:00:00 2001 From: Luca Bruni Date: Tue, 25 Feb 2025 14:08:47 -0500 Subject: [PATCH 1453/2070] drm/dkms: fix conflict with per-user temp directories setting of libpam-tmpdir package Signed-off-by: Luca Bruni Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7411801636c29..6044697f8ac62 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -93,6 +93,10 @@ export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env +# unset TMPDIR in this shell +# otherwise conflicting package libpam-tmpdir incorrectly generates config +unset TMPDIR + (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From 17860e3b09717267542246467dd40afb7c0ef7e7 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 27 Feb 2025 12:45:18 -0500 Subject: [PATCH 1454/2070] drm/amdkfd: remove non-upstream deprecated debug gws support definitions Definition of gws_debug_workaround was replaced by upstreamed kfd_dbg_has_gws_support a long time go so remove the definition. Signed-off-by: Jonathan Kim Reviewed-by: Amber Lin --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 3c2e15968883e..4198dd810f12e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -596,19 +596,6 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } - if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) - && kfd->mec2_fw_version < 0x81b6) || - (KFD_GC_VERSION(kfd) >= IP_VERSION(9, 1, 0) - && KFD_GC_VERSION(kfd) <= IP_VERSION(9, 2, 2) - && kfd->mec2_fw_version < 0x1b6) || - (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) - && kfd->mec2_fw_version < 0x1b6) || - (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) - && kfd->mec2_fw_version < 0x30) || - (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && - KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) - node->gws_debug_workaround = true; - return ret; } From d10f127cc8b5628aaf88fde981ceda1799909d88 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 3 Mar 2025 10:08:54 +0800 Subject: [PATCH 1455/2070] drm/amdkcl: fake __cleanup() based infrastructure It's caused by the following commits: 8b9024152314 "drm/amd/display: Use _free() macro for amdgpu_dm_commit_zero_streams()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/cleanup.h | 12 ++++++++++++ include/kcl/kcl_cleanup.h | 15 +++++++++++++++ include/kcl/kcl_compiler_attributes.h | 8 ++++++++ include/kcl/kcl_slab.h | 5 +++++ 7 files changed, 49 insertions(+) create mode 100644 include/kcl/header/linux/cleanup.h create mode 100644 include/kcl/kcl_cleanup.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 03727052579cd..5865e3ee3385e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -135,4 +135,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 63931589ac7ef..3f67ee4aca1bf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -819,6 +819,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CLEANUP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index d7942c5fa0573..303ac32f4e8e5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -159,4 +159,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kernel/cgroup: Add "dmem" memory accounting cgroup dnl AC_KERNEL_CHECK_HEADERS([linux/cgroup_dmem.h]) + + dnl #v6.5-rc3-2-g85be6d842447 + dnl #locking: Introduce __cleanup() based infrastructure + dnl + AC_KERNEL_CHECK_HEADERS([linux/cleanup.h]) ]) diff --git a/include/kcl/header/linux/cleanup.h b/include/kcl/header/linux/cleanup.h new file mode 100644 index 0000000000000..2787010580598 --- /dev/null +++ b/include/kcl/header/linux/cleanup.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CLEANUP_H +#define _KCL_HEADER_LINUX_CLEANUP_H + +#ifdef HAVE_LINUX_CLEANUP_H +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_cleanup.h b/include/kcl/kcl_cleanup.h new file mode 100644 index 0000000000000..ce4ba4cd69b0a --- /dev/null +++ b/include/kcl/kcl_cleanup.h @@ -0,0 +1,15 @@ +#ifndef _KCL_CLEANUP_H +#define _KCL_CLEANUP_H + +#include +#include + +#ifndef HAVE_LINUX_CLEANUP_H +#define DEFINE_FREE(_name, _type, _free) \ + static inline void __free_##_name(void *p) { _type _T = *(_type *)p; _free; } + +#define __free(_name) __cleanup(__free_##_name) + +#endif + +#endif /* KCL_CLEANUP_H_ */ diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h index e844e68139479..9b21509fb3017 100644 --- a/include/kcl/kcl_compiler_attributes.h +++ b/include/kcl/kcl_compiler_attributes.h @@ -22,4 +22,12 @@ #endif #endif +#ifndef __cleanup +#ifdef __clang__ +#define __cleanup(func) __maybe_unused __attribute__((__cleanup__(func))) +#else +#define __cleanup(func) __attribute__((__cleanup__(func))) +#endif +#endif + #endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index a23a565eab992..bac4078a6e36a 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -13,6 +13,7 @@ #include #include +#include #ifndef HAVE_KREALLOC_ARRAY /** @@ -38,4 +39,8 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) size_t kmalloc_size_roundup(size_t size); #endif +#ifndef HAVE_LINUX_CLEANUP_H +DEFINE_FREE(kfree, void *, if (_T) kfree(_T)) +#endif + #endif From 3d9e9fe7dfdad34586471f3161405ab4aa161a3a Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 5 Mar 2025 12:16:57 +0800 Subject: [PATCH 1456/2070] drm/amdkcl: fake the macro defintion scoped_guard It's caused by the commit: a0dbab7 "drm/amd/display: Use scoped guards for handle_hpd_irq_helper()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cleanup.h | 25 +++++++++++++++++++++++++ include/kcl/kcl_mutex.h | 21 +++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 include/kcl/kcl_mutex.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5865e3ee3385e..171b06ca93468 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -136,4 +136,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cleanup.h b/include/kcl/kcl_cleanup.h index ce4ba4cd69b0a..73ad9f618de67 100644 --- a/include/kcl/kcl_cleanup.h +++ b/include/kcl/kcl_cleanup.h @@ -10,6 +10,31 @@ #define __free(_name) __cleanup(__free_##_name) +#define DEFINE_CLASS(_name, _type, _exit, _init, _init_args...) \ +typedef _type class_##_name##_t; \ +static inline void class_##_name##_destructor(_type *p) \ +{ _type _T = *p; _exit; } \ +static inline _type class_##_name##_constructor(_init_args) \ +{ _type t = _init; return t; } + +#define DEFINE_GUARD(_name, _type, _lock, _unlock) \ + DEFINE_CLASS(_name, _type, if (_T) { _unlock; }, ({ _lock; _T; }), _type _T); \ + static inline void * class_##_name##_lock_ptr(class_##_name##_t *_T) \ + { return *_T; } + +#define CLASS(_name, var) \ + class_##_name##_t var __cleanup(class_##_name##_destructor) = \ + class_##_name##_constructor + +#define guard(_name) \ + CLASS(_name, __UNIQUE_ID(guard)) + +#define __guard_ptr(_name) class_##_name##_lock_ptr + +#define scoped_guard(_name, args...) \ + for (CLASS(_name, scope)(args), \ + *done = NULL; __guard_ptr(_name)(&scope) && !done; done = (void *)1) + #endif #endif /* KCL_CLEANUP_H_ */ diff --git a/include/kcl/kcl_mutex.h b/include/kcl/kcl_mutex.h new file mode 100644 index 0000000000000..4f04f50c91acd --- /dev/null +++ b/include/kcl/kcl_mutex.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Mutexes: blocking mutual exclusion locks + * + * started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar + * + * This file contains the main data structure and API definitions. + */ +#ifndef __KCL_MUTEX_H +#define __KCL_MUTEX_H + +#include +#include + +#ifndef HAVE_LINUX_CLEANUP_H +DEFINE_GUARD(mutex, struct mutex *, mutex_lock(_T), mutex_unlock(_T)) +#endif + +#endif /* __LINUX_MUTEX_H */ From bda9a679100e6ec5927e54d0e90720189346bcc6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Mar 2025 16:20:02 +0800 Subject: [PATCH 1457/2070] drm/amdkcl: add fd class definition It's caused by 6.4-3-g54da6a092431 locking: Introduce __cleanup() based infrastructure v6.12-rc2-14-g6348be02eead fdget(), trivial conversions Signed-off-by: Asher Song --- include/kcl/kcl_file.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_file.h b/include/kcl/kcl_file.h index 4c8a92d981141..f037be89b452c 100644 --- a/include/kcl/kcl_file.h +++ b/include/kcl/kcl_file.h @@ -15,4 +15,8 @@ static inline bool fd_empty(struct fd f) } #endif +#ifndef HAVE_LINUX_CLEANUP_H +DEFINE_CLASS(fd, struct fd, fdput(_T), fdget(fd), int fd) +#endif + #endif From ddd83a26566860365fed1bc85b03a1dd50d11a7d Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 26 Feb 2025 11:12:19 -0500 Subject: [PATCH 1458/2070] drm/amdkfd: Limit use of USE_DEFAULT_GRACE_PERIOD Limit the use of macro USE_DEFAULT_GRACE_PERIOD to kfd_device_queue_manager.c. At this point it is not required outside this file. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Amber Lin --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 ++--- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 3 +-- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 4538b4a7623b4..c2d76db378a39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3640,12 +3640,11 @@ int debug_refresh_runlist(struct device_queue_manager *dqm) void remap_queue(struct device_queue_manager *dqm, enum kfd_unmap_queues_filter filter, - uint32_t filter_param, - uint32_t grace_period) + uint32_t filter_param) { dqm_lock(dqm); if (!dqm->dev->kfd->shared_resources.enable_mes) - execute_queues_cpsch(dqm, filter, filter_param, grace_period); + execute_queues_cpsch(dqm, filter, filter_param, USE_DEFAULT_GRACE_PERIOD); dqm_unlock(dqm); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 0b902433cb888..607098044ea7b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -334,8 +334,7 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, void remap_queue(struct device_queue_manager *dqm, enum kfd_unmap_queues_filter filter, - uint32_t filter_param, - uint32_t grace_period); + uint32_t filter_param); static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 1f6342ea5c547..3af88cdd0d62b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -310,7 +310,7 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, false); remap_queue(pdd->dev->dqm, - KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); if (pc_sampling_stop) { if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { From 362705bf7906320bb1015fedb19525bcc91add41 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Mar 2025 12:29:48 +0800 Subject: [PATCH 1459/2070] drm/amdkcl: fake drm_dev_wedged_event It's caused by v6.14-rc1-238-gb7cf9f4ac1b8 drm: Introduce device wedged event Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 97 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/drm-dev-wedged-event.m4 | 17 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_drv.h | 25 +++++ 6 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 create mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 7672f3fe2b06a..2b9aaff208749 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c new file mode 100644 index 0000000000000..fcd6eab44d280 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -0,0 +1,97 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_DRM_DEV_WEDGED_EVENT +/* + * Available recovery methods for wedged device. To be sent along with device + * wedged uevent. + */ +static const char *drm_get_wedge_recovery(unsigned int opt) +{ + switch (BIT(opt)) { + case DRM_WEDGE_RECOVERY_NONE: + return "none"; + case DRM_WEDGE_RECOVERY_REBIND: + return "rebind"; + case DRM_WEDGE_RECOVERY_BUS_RESET: + return "bus-reset"; + default: + return NULL; + } +} + +/** + * drm_dev_wedged_event - generate a device wedged uevent + * @dev: DRM device + * @method: method(s) to be used for recovery + * + * This generates a device wedged uevent for the DRM device specified by @dev. + * Recovery @method\(s) of choice will be sent in the uevent environment as + * ``WEDGED=[,..,]`` in order of less to more side-effects. + * If caller is unsure about recovery or @method is unknown (0), + * ``WEDGED=unknown`` will be sent instead. + * + * Refer to "Device Wedging" chapter in Documentation/gpu/drm-uapi.rst for more + * details. + * + * Returns: 0 on success, negative error code otherwise. + */ +int drm_dev_wedged_event(struct drm_device *dev, unsigned long method) +{ + const char *recovery = NULL; + unsigned int len, opt; + /* Event string length up to 28+ characters with available methods */ + char event_string[32]; + char *envp[] = { event_string, NULL }; + + len = scnprintf(event_string, sizeof(event_string), "%s", "WEDGED="); + + for_each_set_bit(opt, &method, BITS_PER_TYPE(method)) { + recovery = drm_get_wedge_recovery(opt); + if (drm_WARN_ONCE(dev, !recovery, "invalid recovery method %u\n", opt)) + break; + + len += scnprintf(event_string + len, sizeof(event_string), "%s,", recovery); + } + if (recovery) + /* Get rid of trailing comma */ + event_string[len - 1] = '\0'; + else + /* Caller is unsure about recovery, do the best we can at this point. */ + snprintf(event_string, sizeof(event_string), "%s", "WEDGED=unknown"); + + drm_info(dev, "device wedged, %s\n", method == DRM_WEDGE_RECOVERY_NONE ? + "but recovered through reset" : "needs recovery"); + + return kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); +} +EXPORT_SYMBOL(drm_dev_wedged_event); + +#endif /* HAVE_DRM_DEV_WEDGED_EVENT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 171b06ca93468..a489110bfe891 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -137,4 +137,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 new file mode 100644 index 0000000000000..63ed3acc6c04c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.14-rc1-238-gb7cf9f4ac1b8 +dnl # drm: Introduce device wedged event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_WEDGED_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dev_wedged_event(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DEV_WEDGED_EVENT, 1, + [drm_dev_wedged_event() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 444d2807ea8be..04524cfa29f41 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -241,6 +241,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MEMORY_STATS AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_AMDGPU_MODULE_IMPORT_NS + AC_AMDGPU_DRM_DEV_WEDGED_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h new file mode 100644 index 0000000000000..631e84df47a9e --- /dev/null +++ b/include/kcl/kcl_drm_drv.h @@ -0,0 +1,25 @@ + +#ifndef AMDKCL_DRM_DRV_H +#define AMDKCL_DRM_DRV_H + +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_DEV_WEDGED_EVENT +/* + * Recovery methods for wedged device in order of less to more side-effects. + * To be used with drm_dev_wedged_event() as recovery @method. Callers can + * use any one, multiple (or'd) or none depending on their needs. + */ +#define DRM_WEDGE_RECOVERY_NONE BIT(0) /* optional telemetry collection */ +#define DRM_WEDGE_RECOVERY_REBIND BIT(1) /* unbind + bind driver */ +#define DRM_WEDGE_RECOVERY_BUS_RESET BIT(2) /* unbind + reset bus device + bind */ + +int drm_dev_wedged_event(struct drm_device *dev, unsigned long method); +#endif /* HAVE_DRM_DEV_WEDGED_EVENT */ + +#endif /* AMDKCL_DRM_DRV_H */ + From 878a040cb55e534689fdb66a9048ff5b56514b8c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Mar 2025 13:26:55 +0800 Subject: [PATCH 1460/2070] drm/amdkcl: Check Whether the argument is const in .mode_valid It's caused by v6.13-rc2-288-g26d6fd81916e drm/connector: make mode_valid take a const struct drm_display_mode Signed-off-by: Asher Song --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 18 ++++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 20 +++++++++++++++++++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 7b9da8c3a89f9..a7c78899fd0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -712,7 +712,11 @@ static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); @@ -875,7 +879,11 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -1273,7 +1281,11 @@ static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) * Return: drm_mode_status indicating whether the mode is valid. */ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -1571,7 +1583,11 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) } static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, - const struct drm_display_mode *mode) +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT + const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a39f116094487..031064388eefc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8307,7 +8307,11 @@ create_validate_stream_for_sink(struct drm_connector *connector, } enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { int result = MODE_ERROR; struct dc_sink *dc_sink; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 29f6b2f3d8d10..14bc935cdf17e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1065,7 +1065,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, int link_index); enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode); +#else + struct drm_display_mode *mode); +#endif void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index c31a4f9b86b56..b0930aa8e97cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -36,7 +36,27 @@ AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER], [ ]) ]) +dnl # +dnl # v6.13-rc2-288-g26d6fd81916e +dnl # drm/connector: make mode_valid take a const struct drm_display_mode +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_connector_helper_funcs test_funcs = { + .mode_valid = (enum drm_mode_status (*)(struct drm_connector *, const struct drm_display_mode *))0 + }; + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT, 1, + [.mode_valid need a const drm_display_mode argument]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS], [ AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT ]) From 2b0d9677f7c80ee5736603c0f0053ad6ea39e5f2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Mar 2025 14:06:23 +0800 Subject: [PATCH 1461/2070] drm/amdkcl: test .atomic_async_check in drm_plane_helper_funcs need three arguments It's caused by v6.14-rc1-243-gfd40a63c63a1 drm/atomic: Let drivers decide which planes to async flip Signed-off-by: Asher Song --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 16 ++++++++++++++-- .../amd/dkms/m4/struct_drm_plane_helper_funcs.m4 | 16 ++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index abd25f9abd468..8799dd6725f9e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1292,22 +1292,30 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, } static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS struct drm_atomic_state *state, bool flip) +#elif HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) #else - struct drm_plane_state *state, bool flip) + struct drm_plane_state *state) #endif { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; struct dm_crtc_state *dm_new_crtc_state; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS if (flip) { if (plane->type != DRM_PLANE_TYPE_OVERLAY) return -EINVAL; } else if (plane->type != DRM_PLANE_TYPE_CURSOR) { return -EINVAL; } +#else + /* Only support async updates on cursor planes. */ + if (plane->type != DRM_PLANE_TYPE_CURSOR) + return -EINVAL; +#endif #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1317,7 +1325,11 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, #endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); /* Reject overlay cursors for now*/ +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS if (!flip && dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) +#else + if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) +#endif return -EINVAL; return 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index fce9bda9696c0..eb9f77f9d6b37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -32,8 +32,24 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER], [ ]) ]) +dnl # commit v6.14-rc1-243-gfd40a63c63a1 +dnl # drm/atomic: Let drivers decide which planes to async flip +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs* funcs = NULL; + funcs->atomic_async_check(NULL, NULL, true); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS, 1, + [drm_plane_helper_funcs->atomic_async_check() have three arguments]) + ]) + ]) +]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS ]) From da4c1b4dc2f1e0f6579615eb8184067a200b0f28 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Mar 2025 18:08:42 +0800 Subject: [PATCH 1462/2070] drm/amdkcl: test whether drm_driver->date exists It's caused by commit v6.13-rc1-117-gcb2e1c2136f7 drm: remove driver date from struct drm_driver and all drivers v4.9-rc4-834-g85e634bce01a drm: Extract drm_drv.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-driver-date.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 840627c4bc0bf..86150d5b7841e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3211,6 +3211,9 @@ static struct drm_driver amdgpu_kms_driver = { .name = DRIVER_NAME, .desc = DRIVER_DESC, +#ifdef HAVE_DRM_DRIVER_DATE + .date = DRIVER_DATE, +#endif .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, @@ -3244,6 +3247,9 @@ const struct drm_driver amdgpu_partition_driver = { .name = DRIVER_NAME, .desc = DRIVER_DESC, +#ifdef HAVE_DRM_DRIVER_DATE + .date = DRIVER_DATE, +#endif .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h index 2d86cc6f7f4dd..664f98371451f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h @@ -40,6 +40,9 @@ #define DRIVER_NAME "amdgpu" #define DRIVER_DESC "AMD GPU" +#ifdef HAVE_DRM_DRIVER_DATE +#define DRIVER_DATE "20150101" +#endif extern const struct drm_driver amdgpu_partition_driver; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 new file mode 100644 index 0000000000000..b936fb17b95c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.13-rc1-117-gcb2e1c2136f7 +dnl # drm: remove driver date from struct drm_driver and all drivers +dnl # +dnl # v4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_DATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_driver *drm_driver = NULL; + drm_driver->date = NULL; + ],[ + AC_DEFINE(HAVE_DRM_DRIVER_DATE, 1, + [drm_driver->date is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 04524cfa29f41..32bed205dc922 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -242,6 +242,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_AMDGPU_MODULE_IMPORT_NS AC_AMDGPU_DRM_DEV_WEDGED_EVENT + AC_AMDGPU_DRM_DRIVER_DATE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 24e8f0472240d35296e2e5ec9925795584c4928f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 14 Mar 2025 10:25:03 +0800 Subject: [PATCH 1463/2070] drm/amdkcl: fix drm_device release leak on legacy kernel Reviewed-by: Bob Zhou Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c index 44009aa8216ed..7231caaa04f1e 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c @@ -25,6 +25,10 @@ #include #include #include +#ifndef HAVE_DRM_DRM_MANAGED_H +#include +#include +#endif #include @@ -108,6 +112,10 @@ static void free_xcp_dev(int8_t index) devres_release_group(&pdev->dev, NULL); platform_device_unregister(pdev); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(&(xcp_dev[index]->drm)); + kfree(xcp_dev[index]); +#endif xcp_dev[index] = NULL; pdev_num--; } From 9d9b269018e5b6a64c3d3475cb7e240d7605e411 Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 20 Mar 2025 10:39:03 +0800 Subject: [PATCH 1464/2070] drm/amdkcl: use GFP_NOWAIT for memory allocations on non-upstream code It's caused by the commit: 7d3a3a2 "drm/amdgpu: use GFP_NOWAIT for memory allocations" Signed-off-by: chengjya Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c index 432072b28f5ae..b418bfe412589 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -408,7 +408,7 @@ int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, mutex_lock(¢ity->sem_lock); list_for_each_entry_safe(dep, tmp, ¢ity->sem_dep_list, list) { - r = amdgpu_sync_fence(sync, dep->fence); + r = amdgpu_sync_fence(sync, dep->fence, GFP_KERNEL); if (r) goto err; dma_fence_put(dep->fence); From c785048b7626a82829524b64927035d7b6dee697 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 18 Mar 2025 14:59:55 -0400 Subject: [PATCH 1465/2070] drm/kfd: add Stochastic PC sampling support for gfx9_5_0. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 3af88cdd0d62b..b2fefc190db39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -37,9 +37,10 @@ * 1.1 - Support gfx9_4_3 Stochastic PC sampling * 1.2 - Support gfx9_5_0 Host Trap PC sampling * 1.3 - Update 1st level trap handler for Stochastic PC sampling + * 1.4 - Support gfx9_5_0 Stochastic PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 3 +#define KFD_IOCTL_PCS_MINOR_VERSION 4 struct supported_pc_sample_info { uint32_t ip_version; @@ -58,6 +59,7 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, }; static int kfd_pc_sample_thread(void *param) From 80d02667061235deb32d3a5b6f955978a3cf432b Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 20 Mar 2025 17:30:32 +0800 Subject: [PATCH 1466/2070] drm/amdkcl: test whether __assign_str() wants 1 arguments It's caused by 5c05f70f "drm/amdgpu: add cleaner shader trace point" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 72f13cd5f5407..e0435f69cf858 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -479,7 +479,7 @@ TRACE_EVENT(amdgpu_cleaner_shader, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->seqno = fence->seqno; ), TP_printk("ring=%s, seqno=%Lu", __get_str(ring), __entry->seqno) From f3026af0a27da6bfa700cd395709105d47cb6619 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Aug 2024 16:42:05 +0800 Subject: [PATCH 1467/2070] drm/amdkcl: test whether __assign_str() wants 1 arguments It's caused by 2c92ca849fcc6ee7d0c358e9959abc9f58661aea "tracing/treewide: Remove second parameter of __assign_str()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 14 +++++++------- drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 6 +++--- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/assign_str.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 2 +- drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- include/kcl/kcl_tracepoint.h | 13 +++++++++++++ 11 files changed, 51 insertions(+), 16 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/assign_str.m4 create mode 100644 include/kcl/kcl_tracepoint.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index e0435f69cf858..eb878eadf8461 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -176,10 +176,10 @@ TRACE_EVENT(amdgpu_cs_ioctl, ), TP_fast_assign( - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u", @@ -199,10 +199,10 @@ TRACE_EVENT(amdgpu_sched_run_job, ), TP_fast_assign( - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u", @@ -227,7 +227,7 @@ TRACE_EVENT(amdgpu_vm_grab_id, TP_fast_assign( __entry->pasid = vm->pasid; - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = job->vmid; __entry->vm_hub = ring->vm_hub, __entry->pd_addr = job->vm_pd_addr; @@ -421,7 +421,7 @@ TRACE_EVENT(amdgpu_vm_flush, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = vmid; __entry->vm_hub = ring->vm_hub; __entry->pd_addr = pd_addr; @@ -553,7 +553,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, sched_job->base.sched->name); __entry->fence = fence; __entry->ctx = fence->context; __entry->seqno = fence->seqno; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h index 7c857ba3c31c0..5a74e165c087f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -3,7 +3,7 @@ #if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) #define _TRACE_KCL_FENCE_H -#include +#include #undef TRACE_SYSTEM #define TRACE_SYSTEM kcl_fence @@ -25,8 +25,8 @@ DECLARE_EVENT_CLASS(kcl_fence, ), TP_fast_assign( - __assign_str(driver, fence->ops->get_driver_name(fence)) - __assign_str(timeline, fence->ops->get_timeline_name(fence)) + __amdkcl_assign_str(driver, fence->ops->get_driver_name(fence)); + __amdkcl_assign_str(timeline, fence->ops->get_timeline_name(fence)); __entry->context = fence->context; __entry->seqno = fence->seqno; ), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h index 5d27a98055377..16470bec1c317 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -61,7 +61,7 @@ TRACE_EVENT(kfd_map_memory_to_gpu_end, TP_fast_assign( __entry->pasid = p->pasid; __entry->array_size = array_size; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", __entry->pasid, @@ -109,7 +109,7 @@ TRACE_EVENT(kfd_evict_process_worker_end, ), TP_fast_assign( __entry->pasid = p->pasid; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid=%u, StatusMsg=%s", __entry->pasid, __get_str(pStatusMsg)) @@ -137,7 +137,7 @@ TRACE_EVENT(kfd_restore_process_worker_end, ), TP_fast_assign( entry->pasid = p->pasid; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid=%u, StatusMsg=%s", __entry->pasid, __get_str(pStatusMsg)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a489110bfe891..5eaa06c2afc62 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -123,6 +123,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index cf168868a0f16..d7b955f964f4f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -89,7 +89,7 @@ TRACE_EVENT(amdgpu_dc_performance, __entry->writes = write_count; __entry->read_delta = read_count - *last_read; __entry->write_delta = write_count - *last_write; - __assign_str(func); + __amdkcl_assign_str(func, func); __entry->line = line; *last_read = read_count; *last_write = write_count; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3f67ee4aca1bf..372cf4d0f6cf6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -660,6 +660,9 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + /* follow_pfn() is available */ /* #undef HAVE_FOLLOW_PFN */ diff --git a/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 new file mode 100644 index 0000000000000..477d281b98373 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.9-11925-g2c92ca849fcc +dnl # tracing/treewide: Remove second parameter of __assign_str() +dnl # Due to trace system bases on runtime, so use script to handle specially +dnl # +AC_DEFUN([AC_AMDGPU_ASSIGN_STR], [ + AC_KERNEL_DO_BACKGROUND([ + header_file=stage6_event_callback.h + header_file_src=$LINUX/include/trace/stages/$header_file + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -q '^#define __assign_str(dst)' $header_file_src], [ + AC_DEFINE(HAVE_ASSIGN_STR_ONE_ARGUMENT, 1, + [__assign_str() wants 1 arguments]) + ]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 32bed205dc922..e384153277cca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -225,6 +225,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS + AC_AMDGPU_ASSIGN_STR AC_AMDGPU_DRM_DP_MST_EDID_READ AC_AMDGPU_DRM_DP_CEC_ATTACH AC_AMDGPU_STRUCT_FILE_OPERATION diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 97113f7b2c0db..fac6271bf3095 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,5 +8,5 @@ #include #include #include - +#include #endif diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index 0f965676764f7..0bd32514d54c4 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -68,7 +68,7 @@ DECLARE_EVENT_CLASS(drm_sched_job, ), TP_fast_assign( - __assign_str(name); + __amdkcl_assign_str(name, sched_job->sched->name); __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->credit_count); diff --git a/include/kcl/kcl_tracepoint.h b/include/kcl/kcl_tracepoint.h new file mode 100644 index 0000000000000..10eafc91c9486 --- /dev/null +++ b/include/kcl/kcl_tracepoint.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_TRACEPOINT_H_ +#define _KCL_TRACEPOINT_H_ + +#include + +#ifdef HAVE_ASSIGN_STR_ONE_ARGUMENT +#define __amdkcl_assign_str(dst, src) __assign_str(dst) +#else +#define __amdkcl_assign_str(dst, src) __assign_str(dst, src) +#endif + +#endif From a33a68c823911a278abb1da03fb5d2e2a84e369a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Feb 2025 16:49:31 +0800 Subject: [PATCH 1468/2070] drm/amdkcl: spilt amdkcl_gem_resvp to kcl_drm_gem.h Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_gem.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index cea563821fa86..da5df184d9d58 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -36,6 +36,12 @@ #include +#ifdef HAVE_DRM_GEM_OBJECT_RESV +#define amdkcl_gem_resvp(bo) (bo->resv) +#else +#define amdkcl_gem_resvp(bo) (container_of(bo, struct ttm_buffer_object, base)->resv) +#endif + #ifndef HAVE_DRM_PRINT_MEMORY_STATS enum drm_gem_object_status { DRM_GEM_OBJECT_RESIDENT = BIT(0), From 5a7c8f25b445ff8ad7451920971ab0561586925c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Feb 2025 17:41:11 +0800 Subject: [PATCH 1469/2070] drm/amdkcl: include drm_exec.ko from kernel Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Kbuild | 2 +- drivers/gpu/drm/amd/dkms/Makefile.drm_exec | 6 ++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 10 +++++++--- drivers/gpu/drm/amd/dkms/sources | 2 ++ 5 files changed, 17 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_exec diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 20534a90dbb86..64e285805c292 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_buddy.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_exec.c drm_buddy.c" diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index d4ab165eeaf09..02fb141c1d995 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -73,7 +73,7 @@ $(warning "The local C standard(gnu89) doesn't match kernel default C standard(g endif include $(src)/amd/dkms/Makefile.drm_ttm_helper - +include $(src)/amd/dkms/Makefile.drm_exec include $(src)/amd/dkms/Makefile.drm_buddy obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec new file mode 100644 index 0000000000000..3c01e88c56700 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec @@ -0,0 +1,6 @@ +export CONFIG_DRM_EXEC=m + +subdir-ccflags-y += -DCONFIG_DRM_EXEC +CFLAGS_drm_exec.o += -include linux/module.h -DHAVE_CONFIG_H +amddrm_exec-y := drm_exec.o +obj-$(CONFIG_DRM_EXEC) += amddrm_exec.o diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 7d262536848b6..15287e5222ac3 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -31,9 +31,13 @@ BUILT_MODULE_NAME[5]="amddrm_buddy" BUILT_MODULE_LOCATION[5]="." DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" -BUILT_MODULE_NAME[6]="amdxcp" -BUILT_MODULE_LOCATION[6]="amd/amdxcp" -DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" +BUILT_MODULE_NAME[6]="amddrm_exec" +BUILT_MODULE_LOCATION[6]="." +DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm" + +BUILT_MODULE_NAME[7]="amdxcp" +BUILT_MODULE_LOCATION[7]="amd/amdxcp" +DEST_MODULE_LOCATION[7]="/kernel/drivers/gpu/drm/amd/amdxcp" MAKE[0]="'make' KERNELVER=$kernelver" diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 373b38d0d2325..34f51478f5472 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -33,3 +33,5 @@ drivers/gpu/drm/drm_gem_ttm_helper.c . include/drm/drm_gem_ttm_helper.h include/drm/ drivers/gpu/drm/drm_buddy.c . include/drm/drm_buddy.h include/drm/ +drivers/gpu/drm/drm_exec.c . +include/drm/drm_exec.h include/drm/ From 4f355046b79c17b6d35f7cbfb69bdf40189dac88 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Mar 2025 15:25:51 +0800 Subject: [PATCH 1470/2070] drm/amdkcl: fake kvrealloc for drm_exec Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 18 ++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 35 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 10 ++++++ include/kcl/kcl_memory.h | 4 +++ 6 files changed, 69 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index f5d947730e628..606ae29de54ae 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -29,6 +29,7 @@ * Authors: Thomas Hellstrom */ #include +#include /* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ #ifndef HAVE_VMF_INSERT_MIXED_PROT @@ -71,3 +72,20 @@ vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long ad } EXPORT_SYMBOL(_kcl_vmf_insert_pfn_prot); #endif + +/* Copied from mm/util.c and modified for KCL */ +#ifdef HAVE_NO_KVREALLOC +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) +{ + void *newp; + if (oldsize >= newsize) + return (void *)p; + newp = kvmalloc(newsize, flags); + if (!newp) + return NULL; + memcpy(newp, p, oldsize); + kvfree(p); + return newp; +} +EXPORT_SYMBOL(kvrealloc); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 372cf4d0f6cf6..18853f69d3e91 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -930,6 +930,7 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 +>>>>>>> 2bee6dffc998 (drm/amdkcl: fake kvrealloc for drm_exec) /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e384153277cca..95136f7709de3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -205,6 +205,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_KFIFO_OUT_LINEAR AC_AMDGPU_DRM_CLIENT_REGISTER diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 index f9f0fa0a1862f..98fd7ba684a15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -16,3 +16,38 @@ AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ ]) ]) ]) + +dnl # +dnl #v6.11-rc6-3-g590b9d576cae mm: kvmalloc: align kvrealloc() with krealloc() +dnl #v6.9-rc4-85-g7bd230a26648 mm/slab: enable slab allocation tagging for kmalloc and friends +dnl #v5.15-11-g8587ca6f3415 mm: move kvmalloc-related functions to slab.h +dnl #v5.14-rc4-23-gde2860f46362 mm: Add kvrealloc() +dnl # +AC_DEFUN([AC_AMDGPU_KVREALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC_3ARG, 1, [kvrealloc() has 3 arguments]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC_4ARG, 1, [kvrealloc() has 4 arguments]) + ],[ + AC_DEFINE(HAVE_NO_KVREALLOC, 1, [kvrealloc() isn't available]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 6044697f8ac62..d9c0043de57cc 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -106,3 +106,13 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi + +# v6.11-rc6-3-g590b9d576cae mm: kvmalloc: align kvrealloc() with krealloc() +# Hardcoded modification for `drm_exec.c` to adapt `kvrealloc` function usage to four arguments. +# WARNING: Do NOT optimize this section. The change is essential to guarantee that if there are +# any semantic changes to 'size', it will trigger a DKMS installation failure. +# This ensures any changes to 'size' usage must be manually reviewed and addressed in this context. +if ! grep -q 'define HAVE_KVREALLOC_3ARG ' $SRC/config/config.h; then + sed -i -e 's/kvrealloc(exec->objects, size + PAGE_SIZE, GFP_KERNEL)/kvrealloc(exec->objects, size, size + PAGE_SIZE, GFP_KERNEL)/' \ + drm_exec.c +fi diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index e0dac3be04b47..aeebb157b0d57 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -58,4 +58,8 @@ vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, } #endif /* HAVE_VMF_INSERT_PFN_PROT */ +#ifdef HAVE_NO_KVREALLOC +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); +#endif + #endif From c749f1de23a4f39bcda9f1ea487b6410b276eba6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Mar 2025 16:16:25 +0800 Subject: [PATCH 1471/2070] drm/amdkcl: wrap code under amdkcl_gem_resvp Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.drm_exec | 3 ++- drivers/gpu/drm/amd/dkms/backport_drm_exec.h | 10 +++++++++ drivers/gpu/drm/drm_exec.c | 22 ++++++++++++-------- 3 files changed, 25 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/backport_drm_exec.h diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec index 3c01e88c56700..2177496115aa2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec @@ -1,6 +1,7 @@ export CONFIG_DRM_EXEC=m subdir-ccflags-y += -DCONFIG_DRM_EXEC -CFLAGS_drm_exec.o += -include linux/module.h -DHAVE_CONFIG_H +CFLAGS_drm_exec.o += -include $(src)/amd/dkms/backport_drm_exec.h \ + -include linux/module.h -DHAVE_CONFIG_H amddrm_exec-y := drm_exec.o obj-$(CONFIG_DRM_EXEC) += amddrm_exec.o diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h new file mode 100644 index 0000000000000..3051f5460bd8c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_DRM_EXEC_H +#define _KCL_BACKPORT_DRM_EXEC_H + +#include +#include +#include +#include + +#endif diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c index 8d06014001828..1f485faeb69ac 100644 --- a/drivers/gpu/drm/drm_exec.c +++ b/drivers/gpu/drm/drm_exec.c @@ -6,6 +6,10 @@ #include #include +#ifndef amdkcl_gem_resvp +#define amdkcl_gem_resvp(obj) ((obj)->resv) +#endif + /** * DOC: Overview * @@ -59,7 +63,7 @@ static void drm_exec_unlock_all(struct drm_exec *exec) unsigned long index; drm_exec_for_each_locked_object_reverse(exec, index, obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); drm_gem_object_put(obj); } @@ -172,12 +176,12 @@ static int drm_exec_lock_contended(struct drm_exec *exec) /* Always cleanup the contention so that error handling can kick in */ exec->contended = NULL; if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { - ret = dma_resv_lock_slow_interruptible(obj->resv, + ret = dma_resv_lock_slow_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret)) goto error_dropref; } else { - dma_resv_lock_slow(obj->resv, &exec->ticket); + dma_resv_lock_slow(amdkcl_gem_resvp(obj), &exec->ticket); } ret = drm_exec_obj_locked(exec, obj); @@ -188,7 +192,7 @@ static int drm_exec_lock_contended(struct drm_exec *exec) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); error_dropref: drm_gem_object_put(obj); @@ -221,9 +225,9 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) } if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) - ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + ret = dma_resv_lock_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); else - ret = dma_resv_lock(obj->resv, &exec->ticket); + ret = dma_resv_lock(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret == -EDEADLK)) { drm_gem_object_get(obj); @@ -245,7 +249,7 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); return ret; } EXPORT_SYMBOL(drm_exec_lock_obj); @@ -265,7 +269,7 @@ void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) for (i = exec->num_objects; i--;) { if (exec->objects[i] == obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); for (++i; i < exec->num_objects; ++i) exec->objects[i - 1] = exec->objects[i]; --exec->num_objects; @@ -297,7 +301,7 @@ int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, if (ret) return ret; - ret = dma_resv_reserve_fences(obj->resv, num_fences); + ret = dma_resv_reserve_fences(amdkcl_gem_resvp(obj), num_fences); if (ret) { drm_exec_unlock_obj(exec, obj); return ret; From bd3418c2cf55bee95a9f62fe1d32f133567609e2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Mar 2025 16:27:12 +0800 Subject: [PATCH 1472/2070] drm/amdkcl: add fake kvrealloc support for drm_exec Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/backport_drm_exec.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h index 3051f5460bd8c..9e2b544d7ef73 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -6,5 +6,6 @@ #include #include #include +#include #endif From 75ffa2962660d7a594350528964b10f2c9422bc4 Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Thu, 27 Mar 2025 23:02:08 -0500 Subject: [PATCH 1473/2070] Revert "drm/amdgpu: Increase KIQ invalidate_tlbs timeout" This reverts commit fdb90033846e2f23dfaaa01dc47fec7b94704d0e. Reportedly causing unknown issue in memory management code: [ 128.047288] amdgpu 0000:65:00.0: amdgpu: Failed to map peer:0000:46:00.0 mem_domain:2 [...] [ 137.815340] WARNING: CPU: 81 PID: 1006 at drivers/gpu/drm/ttm/ttm_bo.c:613 ttm_bo_unpin+0x7e/0x90 [ttm] Signed-off-by: Jay Cornwall Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 ++++------------ 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4382c0d823319..e8c87fbaf1a86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -354,6 +354,7 @@ enum amdgpu_kiq_irq { AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, AMDGPU_CP_KIQ_IRQ_LAST }; +#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ #define MAX_KIQ_REG_TRY 1000 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 20e1395b39882..509be09a413dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -771,10 +771,12 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) { + u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : + adev->usec_timeout; struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; unsigned int ndw; - int r, cnt = 0; + int r; uint32_t seq; /* @@ -837,17 +839,7 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, amdgpu_ring_commit(ring); spin_unlock(&adev->gfx.kiq[inst].ring_lock); - - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); - - might_sleep(); - while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && - !amdgpu_reset_pending(adev->reset_domain)) { - msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); - } - - if (cnt > MAX_KIQ_REG_TRY) { + if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) { dev_err(adev->dev, "timeout waiting for kiq fence\n"); r = -ETIME; } else From 78c84c52bd615a6a98cfcd5e31d5a91a0fc5588f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 2 Apr 2025 17:29:42 +0800 Subject: [PATCH 1474/2070] drm/amdkcl: use TTM reference for vm mapping for old OS It's caused by the following patches: v6.13-rc1-107-g39b1acfddfd5 drm/ttm: use GEM references for VM mappings v5.9-rc5-1077-gd693def4fd1c drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver Since drm_gem_object.funs is null in some old OS, drm_gem_object_put can not be used to to reference drm_gem_object and release it. Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index b205e25702a99..1f3bbef32a66e 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -64,13 +64,21 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, if (vmf->flags & FAULT_FLAG_RETRY_NOWAIT) return VM_FAULT_RETRY; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif mmap_read_unlock(vma->vm_mm); (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); dma_resv_unlock(amdkcl_ttm_resvp(bo)); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_put(&bo->base); +#else + ttm_bo_put(bo); +#endif return VM_FAULT_RETRY; } @@ -137,12 +145,20 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, */ if (fault_flag_allow_retry_first(vmf->flags)) { if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif mmap_read_unlock(vma->vm_mm); if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) dma_resv_unlock(amdkcl_ttm_resvp(bo)); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_put(&bo->base); +#else + ttm_bo_put(bo); +#endif } return VM_FAULT_RETRY; @@ -371,7 +387,11 @@ void ttm_bo_vm_open(struct vm_area_struct *vma) WARN_ON(bo->bdev->dev_mapping != vma->vm_file->f_mapping); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif } EXPORT_SYMBOL(ttm_bo_vm_open); @@ -379,7 +399,11 @@ void ttm_bo_vm_close(struct vm_area_struct *vma) { struct ttm_buffer_object *bo = vma->vm_private_data; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_put(&bo->base); +#else + ttm_bo_put(bo); +#endif vma->vm_private_data = NULL; } EXPORT_SYMBOL(ttm_bo_vm_close); @@ -587,7 +611,11 @@ int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct ttm_buffer_object *bo) if (is_cow_mapping(vma->vm_flags)) return -EINVAL; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif /* * Drivers may want to override the vm_ops field. Otherwise we From 80f3bc5d43a7789c8031c6e84c57012e571f59e5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 3 Apr 2025 14:32:27 +0800 Subject: [PATCH 1475/2070] drm/amdkcl: update kmod-amdgpu.spec to support extra amddrm_exec.ko Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec index 79795b24bb7c8..b071bb677652a 100644 --- a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -32,7 +32,7 @@ popd %install mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu -%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko src/amddrm_exec.ko # Make .ko objects temporarily executable for automatic stripping find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ @@ -59,6 +59,7 @@ if [ -x "/usr/sbin/weak-modules" ]; then printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules fi dracut -f --kver %{kernel}.%{_arch} @@ -70,6 +71,7 @@ echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy. echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" >> /var/run/rpm-%{pkg}-modules.list echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" >> /var/run/rpm-%{pkg}-modules.list echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko" >> /var/run/rpm-%{pkg}-modules.list %postun depmod -a > /dev/null 2>&1 @@ -89,6 +91,7 @@ dracut -f --kver %{kernel}.%{_arch} /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko %defattr(644,root,root,755) %license licenses %config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf From 5a8955ea1736b6366709af855d7f27695d70e72e Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 16:22:40 +0800 Subject: [PATCH 1476/2070] drm/amdkcl: fake COUNT_ARGS() and CONCATENATE() macro definition It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++++ include/kcl/header/linux/args.h | 12 ++++++++++ include/kcl/kcl_args.h | 25 ++++++++++++++++++++ 4 files changed, 48 insertions(+) create mode 100644 include/kcl/header/linux/args.h create mode 100644 include/kcl/kcl_args.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 18853f69d3e91..42ad825970a93 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -813,6 +813,12 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ARGS_H 1 + +/* atomic_long_try_cmpxchg() is available */ +#define HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 303ac32f4e8e5..3c103aabdb1bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -164,4 +164,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #locking: Introduce __cleanup() based infrastructure dnl AC_KERNEL_CHECK_HEADERS([linux/cleanup.h]) + + dnl #v6.5-rc4-31-gb229baa374db + dnl #kernel.h: split out COUNT_ARGS() and CONCATENATE() to args.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/args.h]) ]) diff --git a/include/kcl/header/linux/args.h b/include/kcl/header/linux/args.h new file mode 100644 index 0000000000000..b0dc14d7351c2 --- /dev/null +++ b/include/kcl/header/linux/args.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_ARGS_H +#define _KCL_HEADER_LINUX_ARGS_H + +#ifdef HAVE_LINUX_ARGS_H +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_args.h b/include/kcl/kcl_args.h new file mode 100644 index 0000000000000..33ec593ff9b75 --- /dev/null +++ b/include/kcl/kcl_args.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _KCL_KCL_ARGS_H +#define _KCL_KCL_ARGS_H + +#include + +#ifndef __COUNT_ARGS +#define __COUNT_ARGS(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _n, X...) _n +#endif + +#ifndef COUNT_ARGS +#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) +#endif + +/* Concatenate two parameters, but allow them to be expanded beforehand. */ +#ifndef __CONCAT +#define __CONCAT(a, b) a ## b +#endif + +#ifndef CONCATENATE +#define CONCATENATE(a, b) __CONCAT(a, b) +#endif + +#endif /* _KCL_KCL_ARGS_H */ From 0757e8e399c2420eb7cffee4d89ec4b019ecf7f1 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 16:48:19 +0800 Subject: [PATCH 1477/2070] drm/amdkcl: fake the __annotated macro defintion It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++++ include/kcl/header/linux/compiler_types.h | 10 ++++++++ include/kcl/kcl_compiler_types.h | 24 ++++++++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 include/kcl/header/linux/compiler_types.h create mode 100644 include/kcl/kcl_compiler_types.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 42ad825970a93..8072d0881009c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -834,6 +834,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_TYPES_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CONTAINER_OF_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 3c103aabdb1bc..7b6f715c04fa8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -169,4 +169,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kernel.h: split out COUNT_ARGS() and CONCATENATE() to args.h dnl AC_KERNEL_CHECK_HEADERS([linux/args.h]) + + dnl #v4.14-rc6-20-gd15155824c50 + dnl #linux/compiler.h: Split into compiler.h and compiler_types.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/compiler_types.h]) ]) diff --git a/include/kcl/header/linux/compiler_types.h b/include/kcl/header/linux/compiler_types.h new file mode 100644 index 0000000000000..a7e97e404c9e7 --- /dev/null +++ b/include/kcl/header/linux/compiler_types.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_COMPILER_TYPES_H +#define _KCL_HEADER_LINUX_COMPILER_TYPES_H + +#ifdef HAVE_LINUX_COMPILER_TYPES_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_compiler_types.h b/include/kcl/kcl_compiler_types.h new file mode 100644 index 0000000000000..09f2b603b68dd --- /dev/null +++ b/include/kcl/kcl_compiler_types.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_COMPILER_TYPES_H +#define _KCL_KCL_COMPILER_TYPES_H + +#include + +/* + * __has_builtin is supported on gcc >= 10, clang >= 3 and icc >= 21. + * In the meantime, to support gcc < 10, we implement __has_builtin + * by hand. + */ +#ifndef __has_builtin +#define __has_builtin(x) (0) +#endif + +#ifndef __annotated +#if __has_builtin(__builtin_has_attribute) +#define __annotated(var, attr) __builtin_has_attribute(var, attr) +#else +#define __annotated(var, attr) (false) +#endif +#endif + +#endif /* _KCL_KCL_COMPILER_TYPES_H */ \ No newline at end of file From c6acdb50fb536e3f9db0acc194fd2d4c4d85f062 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 17:12:48 +0800 Subject: [PATCH 1478/2070] drm/amdkcl: fake __must_be_cstr macro defintion It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ include/kcl/kcl_compiler.h | 12 ++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 include/kcl/kcl_compiler.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8072d0881009c..83709ad510c18 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -831,6 +831,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CLEANUP_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/include/kcl/kcl_compiler.h b/include/kcl/kcl_compiler.h new file mode 100644 index 0000000000000..9fa1e4ff5d81a --- /dev/null +++ b/include/kcl/kcl_compiler.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_COMPILER_H +#define _KCL_KCL_COMPILER_H + +#include +#include + +#ifndef __must_be_cstr +#define __must_be_cstr(p) BUILD_BUG_ON_ZERO(__annotated(p, nonstring)) +#endif + +#endif /* _KCL_KCL_COMPILER_H */ \ No newline at end of file From f3ce0282afc406b82005c1f5d27047b02dd0b0d8 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 16:53:14 +0800 Subject: [PATCH 1479/2070] drm/amdkcl: drm/amdkcl: check whether strscpy allow 2 argument It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 8 ++------ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/strscpy.m4 | 18 ++++++++++++++++ include/kcl/kcl_string.h | 26 ++++++++++++++++++++++++ 5 files changed, 49 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/strscpy.m4 create mode 100644 include/kcl/kcl_string.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5eaa06c2afc62..781ca32ef03aa 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -139,4 +139,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 83709ad510c18..60a5a5e8dc7ea 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -942,7 +942,6 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 ->>>>>>> 2bee6dffc998 (drm/amdkcl: fake kvrealloc for drm_exec) /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1036,11 +1035,8 @@ /* enum SMCA_UMC_V2 is available */ #define HAVE_SMCA_UMC_V2 1 -/* strscpy() is available */ -#define HAVE_STRSCPY 1 - -/* struct dma_buf_ops->allow_peer2peer is available */ -#define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 +/* strscpy() allows two arguments */ +#define HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS 1 /* struct dma_buf_attach_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 95136f7709de3..ac4818a6c6d28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -245,7 +245,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MODULE_IMPORT_NS AC_AMDGPU_DRM_DEV_WEDGED_EVENT AC_AMDGPU_DRM_DRIVER_DATE - + AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 new file mode 100644 index 0000000000000..f3044c21f6b68 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.8-rc2-15-ge6584c3964f2 +dnl # string: Allow 2-argument strscpy() +dnl # +AC_DEFUN([AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + char name[8]; + strscpy(name, "foo"); + ],[ + AC_DEFINE(HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS, 1, + [strscpy() allows two arguments]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string.h b/include/kcl/kcl_string.h new file mode 100644 index 0000000000000..bda61d800bf1f --- /dev/null +++ b/include/kcl/kcl_string.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_STRING_H +#define _KCL_KCL_STRING_H + +#include +#include +#include + +#ifndef HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS +extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __asm__("strscpy"); + +/* + * The 2 argument style can only be used when dst is an array with a + * known size. + */ +#define kcl_strscpy0(dst, src, ...) \ + real_kcl_strscpy(dst, src, sizeof(dst) + __must_be_array(dst) + \ + __must_be_cstr(dst) + __must_be_cstr(src)) +#define kcl_strscpy1(dst, src, size) \ + real_kcl_strscpy(dst, src, size + __must_be_cstr(dst) + __must_be_cstr(src)) + +#define strscpy(dst, src, ...) \ + CONCATENATE(kcl_strscpy, COUNT_ARGS(__VA_ARGS__))(dst, src, __VA_ARGS__) +#endif + +#endif /* _KCL_KCL_STRING_H */ From 635679d2ea78074b9180dbdb58a811587f02d93e Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 1 Apr 2025 16:03:17 +0800 Subject: [PATCH 1480/2070] drm/amdkcl: Use drm_gem_object_put_unlocked to avoid warnings on RHEL 7.9 Replace drm_gem_object_put with drm_gem_object_put_unlocked to prevent warnings on RHEL 7.9. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/backport_drm_exec.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h index 9e2b544d7ef73..5a0c2434244c8 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #endif From 057bb2dec9c75b6d671e5248729bb7ecdb044a9d Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 9 Apr 2025 12:10:44 +0800 Subject: [PATCH 1481/2070] drm/amdkcl: wrap code under the HAVE_PM_SUSPEND_TARGET_STATE It's caused by the commit: fe01a75b042f "drm/amd: Forbid suspending into non-default suspend states" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 86150d5b7841e..37ad4fd39001f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2685,6 +2685,7 @@ static int amdgpu_pmops_suspend(struct device *dev) else if (amdgpu_acpi_is_s3_active(adev)) adev->in_s3 = true; if (!adev->in_s0ix && !adev->in_s3) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE #if IS_ENABLED(CONFIG_SUSPEND) /* don't allow going deep first time followed by s2idle the next time */ if (adev->last_suspend_state != PM_SUSPEND_ON && @@ -2693,13 +2694,16 @@ static int amdgpu_pmops_suspend(struct device *dev) pm_suspend_target_state); return -EINVAL; } +#endif #endif return 0; } +#ifdef HAVE_PM_SUSPEND_TARGET_STATE #if IS_ENABLED(CONFIG_SUSPEND) /* cache the state last used for suspend */ adev->last_suspend_state = pm_suspend_target_state; +#endif #endif return amdgpu_device_suspend(drm_dev, true); From 84125bd4d2f81ef72c471bd4bfb9ec97c5432083 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 9 Apr 2025 12:14:57 +0800 Subject: [PATCH 1482/2070] drm/amdkcl: fake the macro defintion drm_err_once It's caused by the commit: fe01a75b042f "drm/amd: Forbid suspending into non-default suspend states" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a4e435d18106e..f650bc4988a84 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -108,6 +108,11 @@ void kcl_drm_err(const char *format, ...); dev_warn_once((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) #endif /* drm_warn_once */ +#ifndef drm_err_once +#define drm_err_once(drm, fmt, ...) \ + __drm_printk((drm), err, _once, "*ERROR* " fmt, ##__VA_ARGS__) +#endif + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From 02901a55cf6a31d26ff5f440df38f750556b26a6 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 1 Apr 2025 11:19:29 +0800 Subject: [PATCH 1483/2070] drm/amdkcl: fake __RENAME macro defintion Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_fortify_string.h | 10 ++++++++++ include/kcl/kcl_string.h | 3 ++- 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_fortify_string.h diff --git a/include/kcl/kcl_fortify_string.h b/include/kcl/kcl_fortify_string.h new file mode 100644 index 0000000000000..9dc5b48ee77b9 --- /dev/null +++ b/include/kcl/kcl_fortify_string.h @@ -0,0 +1,10 @@ +#ifndef _KCL_KCL_FORTIFY_STRING_H_ +#define _KCL_KCL_FORTIFY_STRING_H_ + +#include + +#ifndef __RENAME +#define __RENAME(x) __asm__(#x) +#endif + +#endif /* _KCL_KCL_FORTIFY_STRING_H_ */ \ No newline at end of file diff --git a/include/kcl/kcl_string.h b/include/kcl/kcl_string.h index bda61d800bf1f..cb4416f1f99a9 100644 --- a/include/kcl/kcl_string.h +++ b/include/kcl/kcl_string.h @@ -3,11 +3,12 @@ #define _KCL_KCL_STRING_H #include +#include #include #include #ifndef HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS -extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __asm__("strscpy"); +extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __RENAME(strscpy); /* * The 2 argument style can only be used when dst is an array with a From f6f43d9fb57d4b8d38d75cd688fb53806fc94fa6 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 10 Apr 2025 11:24:57 +0800 Subject: [PATCH 1484/2070] drm/amdkcl: fake macro VFM_MODEL It's caused by the commit:f4f55ab3 "drm/amd/amdgpu: disable ASPM in some situations" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cpu_device_id.h | 27 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/kcl/kcl_cpu_device_id.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 781ca32ef03aa..38b197e1b1243 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -140,4 +140,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cpu_device_id.h b/include/kcl/kcl_cpu_device_id.h new file mode 100644 index 0000000000000..e08314fb54b9f --- /dev/null +++ b/include/kcl/kcl_cpu_device_id.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_CPU_DEVICE_ID_H +#define AMDKCL_CPU_DEVICE_ID_H + +#ifdef CONFIG_X86 + +#include +/* Copied froma arch/x86/include/asm/cpu_device_id.h*/ +#ifndef VFM_MODEL +#define VFM_MODEL_BIT 0 +#define VFM_FAMILY_BIT 8 +#define VFM_VENDOR_BIT 16 + +#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT) + +#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT) + +#define VFM_MAKE(_vendor, _family, _model) ( \ + ((_model) << VFM_MODEL_BIT) | \ + ((_family) << VFM_FAMILY_BIT) | \ + ((_vendor) << VFM_VENDOR_BIT) \ +) + +#endif + +#endif /* CONFIG_X86 */ +#endif From 079765c8e41a9fd10f934b9d0f22366612da3dc0 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 10 Apr 2025 11:18:03 +0800 Subject: [PATCH 1485/2070] drm/amdkcl: fake macro INTEL_ALDERLAKE & INTEL_ROCKETLAKE It's caused by the commit:f4f55ab3 "drm/amd/amdgpu: disable ASPM in some situations" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- include/kcl/kcl_intel_family.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index 90793a772861b..bc2516933d89c 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -5,6 +5,7 @@ #ifdef CONFIG_X86 #include +#include /* Copied froma asm/intel-family.h*/ #ifndef INTEL_FAM6_ROCKETLAKE #define INTEL_FAM6_ROCKETLAKE 0xA7 @@ -14,5 +15,20 @@ #define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ #endif +#ifndef IFM +#define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) +#endif + +#ifndef INTEL_ALDERLAKE +#define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ +#define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ +#endif + +#ifndef INTEL_ROCKETLAKE +#define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */ +#define INTEL_RAPTORLAKE_P IFM(6, 0xBA) +#define INTEL_RAPTORLAKE_S IFM(6, 0xBF) +#endif + #endif /* CONFIG_X86 */ #endif From a2f441bb947623ecc5b63387a29550de5a70a07b Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Tue, 15 Apr 2025 11:14:15 +0800 Subject: [PATCH 1486/2070] drm/amdgpu: skip execution of already queued recovery jobs skip execution of already queued recovery jobs, if the device is already reset. [ 241.356426] BUG: unable to handle page fault for address: 000000001de37ef8 [ 241.364167] #PF: supervisor read access in kernel mode [ 241.369948] #PF: error_code(0x0000) - not-present page [ 241.375716] PGD 0 [ 241.377988] Oops: 0000 [#1] SMP NOPTI [ 241.382115] CPU: 19 PID: 1669 Comm: kworker/u448:1 Tainted: G OE 5.15.0-70-generic #77-Ubuntu [ 241.393066] Hardware name: Microsoft C278A/C278A, BIOS C2789.5.BS.1C23.AG.2 11/21/2024 [ 241.401953] Workqueue: amdgpu-reset-hive amdgpu_amdkfd_reset_work [amdgpu] [ 241.410280] RIP: 0010:amdgpu_reset_perform_reset+0x1d/0x70 [amdgpu] [ 241.417639] Code: f0 66 66 2e 0f 1f 84 00 00 00 00 00 90 0f 1f 44 00 00 55 48 89 e5 41 55 41 54 53 48 89 fb 48 8b bf 28 4f 05 00 48 85 ff 74 49 <48> 8b 47 58 49 89 f4 ff d0 0f 1f 00 49 89 c5 48 85 c0 74 35 48 8b [ 241.438732] RSP: 0018:ffa000001de37d40 EFLAGS: 00010206 [ 241.444598] RAX: ffa000001de37dd0 RBX: ffa000001dde2f68 RCX: ffa000001de37dd0 [ 241.452599] RDX: ff11000118aadf40 RSI: ffa000001de37e20 RDI: 000000001de37ea0 [ 241.460610] RBP: ffa000001de37d58 R08: 0000000000000003 R09: ffffffffffe6b508 [ 241.468621] R10: ffffffffffffffff R11: 0000000000000001 R12: ffa000001dde2f68 [ 241.476631] R13: ffa000001de37e20 R14: ff11000121800000 R15: ff11000100049400 [ 241.484634] FS: 0000000000000000(0000) GS:ff11007e7e8c0000(0000) knlGS:0000000000000000 [ 241.493730] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 241.500182] CR2: 000000001de37ef8 CR3: 0000000006810004 CR4: 0000000000771ee0 [ 241.508193] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 241.516202] DR3: 0000000000000000 DR6: 00000000fffe07f0 DR7: 0000000000000400 [ 241.524210] PKRU: 55555554 [ 241.527248] Call Trace: [ 241.529994] [ 241.532351] amdgpu_do_asic_reset+0x2b/0x190 [amdgpu] [ 241.538253] amdgpu_device_gpu_recover.cold+0x532/0xd92 [amdgpu] [ 241.545431] ? ttwu_queue_wakelist+0x131/0x1c0 [ 241.550437] amdgpu_amdkfd_reset_work+0x6f/0x90 [amdgpu] [ 241.556737] process_one_work+0x228/0x3d0 [ 241.561254] worker_thread+0x53/0x420 [ 241.565366] ? process_one_work+0x3d0/0x3d0 [ 241.570061] kthread+0x127/0x150 [ 241.573700] ? set_kthread_struct+0x50/0x50 [ 241.578404] ret_from_fork+0x1f/0x30 [ 241.582434] Fixes 76e3985a6c62("drm/amdgpu: refactor amdgpu_device_gpu_recover") Signed-off-by: Ce Sun Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 75858db0f1ed0..507304027ea9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6239,9 +6239,6 @@ static void amdgpu_device_recovery_prepare(struct amdgpu_device *adev, { struct amdgpu_device *tmp_adev = NULL; - if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) - return 0; - /* * Build list of devices to reset. * In case we are in XGMI hive mode, resort the device list @@ -6514,6 +6511,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, /* save the pasid here as the job may be freed before the end of the reset */ int pasid = job ? job->pasid : -EINVAL; + if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) + return 0; + /* * If it reaches here because of hang/timeout and a RAS error is * detected at the same time, let RAS recovery take care of it. From 86f3edc09586fa9b341e45b3ab57cc9199fc7669 Mon Sep 17 00:00:00 2001 From: Shane Xiao Date: Wed, 16 Apr 2025 16:39:26 +0800 Subject: [PATCH 1487/2070] drm/amdkfd: Ignore userptr bad address error in non-HMM path The userptr can be unmapped by app and still registered to driver. Pretend the -EFAULT bad address error as succeed without HMM support. If GPU tries to access it, it will fail with a VM fault. This patch specifically addresses the restore userptr stage from MMU notifier and corrects the non-HMM code path on DKMS branch. v2: Update the commit description (Felix) Signed-off-by: Shane Xiao Reviewed-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index bdf1ac7e4e93a..3be543a926b7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2980,13 +2980,19 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { mem->user_pages[0] = NULL; - pr_info("%s: Failed to get user pages: %d\n", + pr_debug("%s: Failed to get user pages: %d\n", __func__, ret); /* Pretend it succeeded. It will fail later * with a VM fault if the GPU tries to access * it. Better than hanging indefinitely with * stalled user mode queues. + * + * Return other error -EBUSY or -ENOMEM to retry restore */ + if (ret != -EFAULT) + return ret; + + ret = 0; } #endif mutex_lock(&process_info->notifier_lock); From b9f521e4334626bd67acde3a6b846ce6d68b9fd9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Apr 2025 10:14:48 +0800 Subject: [PATCH 1488/2070] drm/amdkcl: update CPP variable for autoconf Autoconf will detect the CPP variale to handle AC_CHECK_HEADERS, so update it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 4eb72d9844e0e..486bb816b43df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ _conftest_cmd=$(head -1 .conftest.o.cmd) CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CPP="$CC -E" CFLAGS=$(echo $_conftest_cmd | \ cut -d ' ' -f 4- | \ @@ -27,6 +28,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ sed -e "s|nostdinc|nostdinc -I../tiny_wrapper/include|") AC_SUBST(CC) + AC_SUBST(CPP) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) ], [ From 820873ab53d3066a4c3bcbc1cd8b5a003a3e0b98 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 2 Apr 2025 13:33:43 +0800 Subject: [PATCH 1489/2070] drm/amdkcl: fix autoconf missing llvm series tool Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 3 +-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 5f9b0ca95f2fd..9f4c9c123ccf8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -34,9 +34,8 @@ endif ifneq ($(CONFIG_CC_IS_CLANG),) CC := clang module_build_flags += CC=clang -endif -ifneq ($(CONFIG_LD_IS_LLD),) module_build_flags += LD=ld.lld +module_build_flags += LLVM=1 endif dkms-config ?= amd/dkms/dkms-config.mk diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ac4818a6c6d28..892db0156ddb3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -456,7 +456,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ kbuild_cc='' if test -s ${LINUX_OBJ}/.config; then if grep -q 'CONFIG_CC_IS_CLANG=y' "${LINUX_OBJ}/.config"; then - kbuild_cc='CC=clang' + kbuild_cc='CC=clang LD=ld.lld LLVM=1' fi fi test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index d9c0043de57cc..ec589e5ad3d2b 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -97,7 +97,7 @@ echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env # otherwise conflicting package libpam-tmpdir incorrectly generates config unset TMPDIR -(cd $SRC && ./configure) +(cd $SRC && ./configure CC=${CC}) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o # for kernel version < 5.3 From 2f171ad8885e90bd0275b07366170c7e5b540655 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 24 Apr 2025 12:27:39 +0800 Subject: [PATCH 1490/2070] drm/amdkcl: wrap code under HAVE_DRM_GEM_OBJECT_RESV It's caused by following commit b75818d0d2 "drm/amdgpu: add the evf attached gem obj resv dump" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index a472583cff495..6dfe08a5e64e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1736,9 +1736,9 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); /* Add the gem obj resv fence dump*/ - if (dma_resv_trylock(bo->tbo.base.resv)) { - dma_resv_describe(bo->tbo.base.resv, m); - dma_resv_unlock(bo->tbo.base.resv); + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { + dma_resv_describe(amdkcl_ttm_resvp(&bo->tbo), m); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } seq_puts(m, "\n"); From f19d45f83455312a49dfe7beb322ee1ee310bb73 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Sun, 27 Apr 2025 12:24:36 +0800 Subject: [PATCH 1491/2070] Revert "drm/amdgpu: Fail DMABUF map of XGMI-accessible memory" This reverts commit 90a5538e4619abc08ab0335d1c0dbc87cb21243e. The reverted patch causes a jira issue SWDEV-529564 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index edfbe2b449e18..0ae97b08f0d8e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -408,11 +408,6 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, break; case TTM_PL_VRAM: - /* XGMI-accessible memory should never be DMA-mapped */ - if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible( - dma_buf_attach_adev(attach), bo))) - return ERR_PTR(-EINVAL); - r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0, bo->tbo.base.size, attach->dev, dir, &sgt); From 0c90b1e264597efff9a54db8db68b11cac6eb386 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 29 Apr 2025 16:10:42 +0800 Subject: [PATCH 1492/2070] drm/amdkcl: detect clang tools for autoconf Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 9f4c9c123ccf8..987ac180e8fbd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -32,6 +32,13 @@ $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif ifneq ($(CONFIG_CC_IS_CLANG),) +ifeq ($(shell command -v clang > /dev/null && echo "y"),) +$(error "clang is not installed, exit...") +endif +ifeq ($(shell command -v ld.lld > /dev/null && echo "y"),) +$(error "ld.lld is not installed, exit...") +endif + CC := clang module_build_flags += CC=clang module_build_flags += LD=ld.lld From b60b8e5459a13581f3558a4e98568ccde1fb2d6a Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 30 Apr 2025 13:46:31 +0800 Subject: [PATCH 1493/2070] drm/amdkcl: test whether dma_fence_array_first() exist It's caused by 96d61ad387 "drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ" Signed-off-by: Yang Su --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_array.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/dma_fence_array_first.m4 | 16 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_array.h | 27 ++++++++++++ 7 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 create mode 100644 include/kcl/kcl_dma_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 2b9aaff208749..2adf1f003a5f7 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ + kcl_dma_fence_array.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c new file mode 100644 index 0000000000000..f4b4040005a68 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dma-fence-array: aggregate fences to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + */ + +#ifndef HAVE_DMA_FENCE_ARRAY_FIRST +#include + +struct dma_fence *kcl_dma_fence_array_first(struct dma_fence *head) +{ + struct dma_fence_array *array; + + if (!head) + return NULL; + + array = to_dma_fence_array(head); + if (!array) + return head; + + if (!array->num_fences) + return NULL; + + return array->fences[0]; +} +EXPORT_SYMBOL(kcl_dma_fence_array_first); + +struct dma_fence *kcl_dma_fence_array_next(struct dma_fence *head, + unsigned int index) +{ + struct dma_fence_array *array = to_dma_fence_array(head); + + if (!array || index >= array->num_fences) + return NULL; + + return array->fences[index]; +} +EXPORT_SYMBOL(kcl_dma_fence_array_next); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 38b197e1b1243..b8b8e529683cd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -141,4 +141,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 60a5a5e8dc7ea..2f52c9b4ec3a2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -119,6 +119,9 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ +/* dma_fence_array_first() is available */ +#define HAVE_DMA_FENCE_ARRAY_FIRST 1 + /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 new file mode 100644 index 0000000000000..47bf06c5e0b65 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.17-rc6-1495-gcaaf2ae712b7 +dnl # dma-buf: Add dma_fence_array_for_each (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_ARRAY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_array_first(NULL); + ], [dma_fence_array_first], [drivers/dma-buf/dma-fence-array.c],[ + AC_DEFINE(HAVE_DMA_FENCE_ARRAY_FIRST, 1, + [dma_fence_array_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 892db0156ddb3..2117958ae8e5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -246,6 +246,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_WEDGED_EVENT AC_AMDGPU_DRM_DRIVER_DATE AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS + AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_array.h b/include/kcl/kcl_dma_fence_array.h new file mode 100644 index 0000000000000..242812385623f --- /dev/null +++ b/include/kcl/kcl_dma_fence_array.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * fence-array: aggregates fence to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + */ + +#ifndef __KCL_LINUX_DMA_FENCE_ARRAY_H +#define __KCL_LINUX_DMA_FENCE_ARRAY_H + +#ifndef HAVE_DMA_FENCE_ARRAY_FIRST +#include +#include + +struct dma_fence *kcl_dma_fence_array_first(struct dma_fence *head); +#define dma_fence_array_first kcl_dma_fence_array_first + +struct dma_fence *kcl_dma_fence_array_next(struct dma_fence *head, + unsigned int index); +#define dma_fence_array_next kcl_dma_fence_array_next + +#endif +#endif From 7752b497704e6b74e88cdb3d2983d072e80939ef Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 30 Apr 2025 11:29:17 +0800 Subject: [PATCH 1494/2070] drm/amdkcl: fake the macro defintion dma_fence_unwrap_for_each It's caused by the commit: 96d61ad387ab8 "drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ" Signed-off-by: Yang Su --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_dma_fence_unwrap.h | 95 +++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 include/kcl/kcl_dma_fence_unwrap.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b8b8e529683cd..0ed3cb9b26045 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -142,5 +142,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_dma_fence_unwrap.h b/include/kcl/kcl_dma_fence_unwrap.h new file mode 100644 index 0000000000000..0269bd945071a --- /dev/null +++ b/include/kcl/kcl_dma_fence_unwrap.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ + +#ifndef __KCL_LINUX_DMA_FENCE_UNWRAP_H +#define __KCL_LINUX_DMA_FENCE_UNWRAP_H + +#include +#include + +#ifndef HAVE_LINUX_DMA_FENCE_UNWRAP_H +/** + * struct dma_fence_unwrap - cursor into the container structure + * + * Should be used with dma_fence_unwrap_for_each() iterator macro. + */ +struct dma_fence_unwrap { + /** + * @chain: potential dma_fence_chain, but can be other fence as well + */ + struct dma_fence *chain; + /** + * @array: potential dma_fence_array, but can be other fence as well + */ + struct dma_fence *array; + /** + * @index: last returned index if @array is really a dma_fence_array + */ + unsigned int index; +}; + +/* Internal helper to start new array iteration, don't use directly */ +static inline struct dma_fence * +kcl__dma_fence_unwrap_array(struct dma_fence_unwrap * cursor) +{ + cursor->array = dma_fence_chain_contained(cursor->chain); + cursor->index = 0; + return dma_fence_array_first(cursor->array); +} + +/** + * dma_fence_unwrap_first - return the first fence from fence containers + * @head: the entrypoint into the containers + * @cursor: current position inside the containers + * + * Unwraps potential dma_fence_chain/dma_fence_array containers and return the + * first fence. + */ +static inline struct dma_fence * +kcl_dma_fence_unwrap_first(struct dma_fence *head, struct dma_fence_unwrap *cursor) +{ + cursor->chain = dma_fence_get(head); + return kcl__dma_fence_unwrap_array(cursor); +} + +/** + * dma_fence_unwrap_next - return the next fence from a fence containers + * @cursor: current position inside the containers + * + * Continue unwrapping the dma_fence_chain/dma_fence_array containers and return + * the next fence from them. + */ +static inline struct dma_fence * +kcl_dma_fence_unwrap_next(struct dma_fence_unwrap *cursor) +{ + struct dma_fence *tmp; + + ++cursor->index; + tmp = dma_fence_array_next(cursor->array, cursor->index); + if (tmp) + return tmp; + + cursor->chain = dma_fence_chain_walk(cursor->chain); + return kcl__dma_fence_unwrap_array(cursor); +} + +/** + * dma_fence_unwrap_for_each - iterate over all fences in containers + * @fence: current fence + * @cursor: current position inside the containers + * @head: starting point for the iterator + * + * Unwrap dma_fence_chain and dma_fence_array containers and deep dive into all + * potential fences in them. If @head is just a normal fence only that one is + * returned. + */ +#define dma_fence_unwrap_for_each(fence, cursor, head) \ + for (fence = kcl_dma_fence_unwrap_first(head, cursor); fence; \ + fence = kcl_dma_fence_unwrap_next(cursor)) + +#endif +#endif From fd948774cf9e6f3f3edc54705a9b8c5b4d8f972a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 13:07:48 +0800 Subject: [PATCH 1495/2070] drm/amdkcl: enable KCL macro for dma-resv.c In intree build, HAVE_DMA_FENCE_OPS_SET_DEADLINE KCL macro should be enabled for dma-resv.c. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/dma-buf/dma-resv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 2e78a095eaaf6..76bcda500be45 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -40,6 +40,9 @@ #include #include #include +#ifndef HAVE_CONFIG_H +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE +#endif /** * DOC: Reservation Object Overview From 331c53f1aec72633dcc1b7a0a3e144483efca0d9 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 13:58:18 +0800 Subject: [PATCH 1496/2070] drm/amdkcl: Correct macro definition syntax Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index 435dcf5ceea08..381da116a67ac 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -22,7 +22,7 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, const struct drm_memory_stats *stats, enum drm_gem_object_status supported_status, const char *region); -#define drm_print_memory_stats _kcl_drm_print_memory_stats; +#define drm_print_memory_stats _kcl_drm_print_memory_stats #endif #ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO From bbaed935a07116f1533480182e012530ac34936b Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 13 May 2025 16:55:57 +0800 Subject: [PATCH 1497/2070] drm/amdkcl: fix warning about panic_abo not used Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 10d1921c13382..c37dfaee50012 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1907,12 +1907,12 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) return 0; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used in amdgpu_dm_set_pixel() * they are called from the panic handler, and protected by the drm_panic spinlock. */ static struct amdgpu_bo *panic_abo; -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* Use the indirect MMIO to write each pixel to the GPU VRAM, * This is a simplified version of amdgpu_device_mm_access() */ From dc4d8fdcd8c620b8522490a0a640bc714757df7c Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 10:28:59 +0800 Subject: [PATCH 1498/2070] drm/amdkcl: Standardize the use of HAVE_DRM_CLIENT_SETUP macro Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 37ad4fd39001f..ffd80887e374e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2502,23 +2502,20 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, */ if (adev->mode_info.mode_config_initialized && !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { +#ifdef HAVE_DRM_CLIENT_SETUP const struct drm_format_info *format; /* select 8 bpp console on low vram cards */ if (adev->gmc.real_vram_size <= (32*1024*1024)) -#if HAVE_DRM_CLIENT_SETUP format = drm_format_info(DRM_FORMAT_C8); -#else - drm_fbdev_ttm_setup(adev_to_drm(adev), 8); -#endif else -#if HAVE_DRM_CLIENT_SETUP format = NULL; + drm_client_setup(adev_to_drm(adev), format); #else + if (adev->gmc.real_vram_size <= (32*1024*1024)) + drm_fbdev_ttm_setup(adev_to_drm(adev), 8); + else drm_fbdev_ttm_setup(adev_to_drm(adev), 32); -#endif -#if HAVE_DRM_CLIENT_SETUP - drm_client_setup(adev_to_drm(adev), format); #endif } From c4f68c998d0f635970c13373af9d1210f7e92151 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 13:27:42 +0800 Subject: [PATCH 1499/2070] drm/amdkcl: Include for missing declaration Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c | 3 +-- include/kcl/kcl_kfifo.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c index fad3a2306bdad..86e0115437fbc 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include +#include #ifndef HAVE_KFIFO_OUT_LINEAR - #define __KFIFO_PEEK(data, out, mask) \ ((data)[(out) & (mask)]) /* diff --git a/include/kcl/kcl_kfifo.h b/include/kcl/kcl_kfifo.h index 3be41b4d98708..5e4da40bb35ee 100644 --- a/include/kcl/kcl_kfifo.h +++ b/include/kcl/kcl_kfifo.h @@ -3,10 +3,9 @@ #ifndef KCL_LINUX_KFIFO_H #define KCL_LINUX_KFIFO_H -#ifndef HAVE_KFIFO_OUT_LINEAR - #include +#ifndef HAVE_KFIFO_OUT_LINEAR /** * commit 4edd7e96a1f159f43bd1cb82616f81eaddd54262 * Author: Jiri Slaby (SUSE) From 69d64240eff5ef782ee2fbe95af13bf05cc9dc0d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:43:20 +0800 Subject: [PATCH 1500/2070] drm/amdkcl: fix return void warning Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- include/kcl/backport/kcl_drm_fbdev_ttm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h index 5d504414c4478..a00b1a6a17a80 100644 --- a/include/kcl/backport/kcl_drm_fbdev_ttm.h +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -8,7 +8,7 @@ static inline void _kcl_drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp) { - return drm_fbdev_generic_setup(dev, preferred_bpp); + drm_fbdev_generic_setup(dev, preferred_bpp); } #define drm_fbdev_ttm_setup _kcl_drm_fbdev_ttm_setup #endif From b105f4fb88429ae829ade1b7168c4ae99bc79446 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:07:05 +0800 Subject: [PATCH 1501/2070] drm/amdkcl: cleanup _kcl_drm_atomic_helper_resume These autoconf fake function always is used, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../backport/kcl_drm_atomic_helper_backport.h | 27 ------------------- 1 file changed, 27 deletions(-) diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index eaa2464b77353..44ea7b0f771d3 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -30,33 +30,6 @@ #include -/* - * commit v4.14-rc4-1-g78279127253a - * drm/atomic: Unref duplicated drm_atomic_state in drm_atomic_helper_resume() - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) -static inline -int _kcl_drm_atomic_helper_resume(struct drm_device *dev, - struct drm_atomic_state *state) -{ - unsigned int prev, after; - int ret; - - prev = kref_read(&state->ref); - - drm_atomic_state_get(state); - ret = drm_atomic_helper_resume(dev, state); - - after = kref_read(&state->ref); - drm_atomic_state_put(state); - if (prev != after) - drm_atomic_state_put(state); - - return ret; -} -#define drm_atomic_helper_resume _kcl_drm_atomic_helper_resume -#endif - #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET #define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset #endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ From 19fc08f3b8cbd6fee7655cbe7fed0c18cba7b02f Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 14 May 2025 17:37:13 +0800 Subject: [PATCH 1502/2070] drm/amdkcl: test whether dma_fence_dedup_array() exist It's caused by 554f79d8cf32cd7a3352b "dma-fence: Add helper to sort and deduplicate dma_fence arrays" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c | 64 +++++++++++++++++++ .../drm/amd/dkms/m4/dma_fence_dedup_array.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_unwrap.h | 9 ++- 5 files changed, 90 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 2adf1f003a5f7..4e692b75892f6 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c new file mode 100644 index 0000000000000..cb179499f98e9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2007 Jens Axboe + * + * Scatterlist handling helpers. + */ +#include +#include + +#ifndef HAVE_DMA_FENCE_DEDUP_ARRAY +static int fence_cmp(const void *_a, const void *_b) +{ + struct dma_fence *a = *(struct dma_fence **)_a; + struct dma_fence *b = *(struct dma_fence **)_b; + + if (a->context < b->context) + return -1; + else if (a->context > b->context) + return 1; + + if (dma_fence_is_later(b, a)) + return 1; + else if (dma_fence_is_later(a, b)) + return -1; + + return 0; +} + +/** + * dma_fence_dedup_array - Sort and deduplicate an array of dma_fence pointers + * @fences: Array of dma_fence pointers to be deduplicated + * @num_fences: Number of entries in the @fences array + * + * Sorts the input array by context, then removes duplicate + * fences with the same context, keeping only the most recent one. + * + * The array is modified in-place and unreferenced duplicate fences are released + * via dma_fence_put(). The function returns the new number of fences after + * deduplication. + * + * Return: Number of unique fences remaining in the array. + */ +int kcl_dma_fence_dedup_array(struct dma_fence **fences, int num_fences) +{ + int i, j; + + sort(fences, num_fences, sizeof(*fences), fence_cmp, NULL); + + /* + * Only keep the most recent fence for each context. + */ + j = 0; + for (i = 1; i < num_fences; i++) { + if (fences[i]->context == fences[j]->context) + dma_fence_put(fences[i]); + else + fences[++j] = fences[i]; + } + + return ++j; +} +EXPORT_SYMBOL_GPL(kcl_dma_fence_dedup_array); + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 new file mode 100644 index 0000000000000..6d00ba9d43f37 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-1919-g554f79d8cf32 +dnl # dma-buf: Add dma_fence_dedup_array +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_dedup_array(NULL, 0); + ], [dma_fence_dedup_array], [drivers/dma-buf/dma-fence-unwrap.c],[ + AC_DEFINE(HAVE_DMA_FENCE_DEDUP_ARRAY, 1, + [dma_fence_dedup_array() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2117958ae8e5a..2efe5482d822e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -247,6 +247,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_DATE AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST + AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_unwrap.h b/include/kcl/kcl_dma_fence_unwrap.h index 0269bd945071a..7c7cac6616168 100644 --- a/include/kcl/kcl_dma_fence_unwrap.h +++ b/include/kcl/kcl_dma_fence_unwrap.h @@ -8,7 +8,8 @@ #ifndef __KCL_LINUX_DMA_FENCE_UNWRAP_H #define __KCL_LINUX_DMA_FENCE_UNWRAP_H -#include +#include +#include #include #ifndef HAVE_LINUX_DMA_FENCE_UNWRAP_H @@ -92,4 +93,10 @@ kcl_dma_fence_unwrap_next(struct dma_fence_unwrap *cursor) fence = kcl_dma_fence_unwrap_next(cursor)) #endif + +#ifndef HAVE_DMA_FENCE_DEDUP_ARRAY +int kcl_dma_fence_dedup_array(struct dma_fence **array, int num_fences); + +#define dma_fence_dedup_array kcl_dma_fence_dedup_array +#endif #endif From e7f9d005bdf00fc18cc65a9fdee8feaa8831ee25 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 09:50:15 +0800 Subject: [PATCH 1503/2070] drm/amdkcl: cleanup macro AMDKCL_FENCE_WAIT_ANY_TIMEOUT These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 79 +---------------------- include/kcl/backport/kcl_fence_backport.h | 8 --- include/kcl/kcl_fence.h | 11 ---- 3 files changed, 1 insertion(+), 97 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index e79e331222d00..49b98dd78dfa1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -26,7 +26,7 @@ #include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ -#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) || defined(AMDKCL_FENCE_WAIT_ANY_TIMEOUT) +#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) static bool dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, uint32_t *idx) @@ -124,83 +124,6 @@ _kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) EXPORT_SYMBOL(_kcl_fence_default_wait); #endif - -/* - * Modifications [2017-09-19] (c) [2017] - * Advanced Micro Devices, Inc. - */ -#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT -signed long -_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, - bool intr, signed long timeout, uint32_t *idx) -{ - struct default_wait_cb *cb; - signed long ret = timeout; - unsigned i; - - if (WARN_ON(!fences || !count || timeout < 0)) - return -EINVAL; - - if (timeout == 0) { - for (i = 0; i < count; ++i) - if (dma_fence_is_signaled(fences[i])) { - if (idx) - *idx = i; - return 1; - } - - return 0; - } - - cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); - if (cb == NULL) { - ret = -ENOMEM; - goto err_free_cb; - } - - for (i = 0; i < count; ++i) { - struct dma_fence *fence = fences[i]; - - - cb[i].task = current; - if (dma_fence_add_callback(fence, &cb[i].base, - _kcl_fence_default_wait_cb)) { - /* This fence is already signaled */ - if (idx) - *idx = i; - goto fence_rm_cb; - } - } - - while (ret > 0) { - if (intr) - set_current_state(TASK_INTERRUPTIBLE); - else - set_current_state(TASK_UNINTERRUPTIBLE); - - if (dma_fence_test_signaled_any(fences, count, idx)) - break; - - ret = schedule_timeout(ret); - - if (ret > 0 && intr && signal_pending(current)) - ret = -ERESTARTSYS; - } - - __set_current_state(TASK_RUNNING); - -fence_rm_cb: - while (i-- > 0) - dma_fence_remove_callback(fences[i], &cb[i].base); - -err_free_cb: - kfree(cb); - - return ret; -} -EXPORT_SYMBOL(_kcl_fence_wait_any_timeout); -#endif - #ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT signed long _kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index a29c3293c6c88..43d13b95da2be 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -4,14 +4,6 @@ #include #include -/* - * commit v4.18-rc2-533-g418cc6ca0607 - * dma-fence: Allow wait_any_timeout for all fences) - */ -#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT -#define dma_fence_wait_any_timeout _kcl_fence_wait_any_timeout -#endif - /* * commit v4.9-rc2-472-gbcc004b629d2 * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index a4a94e8a03e54..c96d716ce94b4 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,17 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.18-rc2-533-g418cc6ca0607 - * dma-fence: Allow wait_any_timeout for all fences) - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) -#define AMDKCL_FENCE_WAIT_ANY_TIMEOUT -signed long -_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, - bool intr, signed long timeout, uint32_t *idx); -#endif - /* * commit v4.9-rc2-472-gbcc004b629d2 * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) From f9ae897f9ed2eb26b95d2000311ceb92008d7951 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 9 May 2025 13:28:48 +0800 Subject: [PATCH 1504/2070] drm/amdkcl: test whether drm_file_err() exist It's caused by ec0a2cc40756 "drm: add drm_file_err function to add process info" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- .../amd/backport/include/kcl/kcl_drm_file.h | 5 +++ drivers/gpu/drm/amd/backport/kcl_drm_file.c | 31 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 56 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index 381da116a67ac..2472c61b0e26d 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -29,4 +29,9 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, int drm_memory_stats_is_zero(const struct drm_memory_stats *stats); #endif +#ifndef HAVE_DRM_FILE_ERR +void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...); +#define drm_file_err kcl_drm_file_err +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index e28ba0dd163d4..70327a98cee90 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "amdgpu_fdinfo.h" #ifndef HAVE_DRM_SHOW_FDINFO /** @@ -113,3 +114,33 @@ int drm_memory_stats_is_zero(const struct drm_memory_stats *stats) stats->active == 0); } #endif + +#ifndef HAVE_DRM_FILE_ERR +void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) +{ + va_list args; + struct va_format vaf; + struct pid *pid; + struct task_struct *task; + struct drm_device *dev = file_priv->minor->dev; + + va_start(args, fmt); + vaf.fmt = fmt; + vaf.va = &args; + + rcu_read_lock(); + pid = rcu_dereference(file_priv->pid); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PGID); +#endif + drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", + task ? task->pid : 0, "Unset", &vaf); + + va_end(args); + rcu_read_unlock(); +} +EXPORT_SYMBOL(kcl_drm_file_err); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2f52c9b4ec3a2..9677ad2791aa1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -558,6 +558,9 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ +/* drm_file_err() is available */ +#define HAVE_DRM_FILE_ERR 1 + /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 new file mode 100644 index 0000000000000..fd413cbd2300a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-1914-gec0a2cc40756 +dnl # dma-buf: Add drm_file_err (v1) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_ERR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_file_err(NULL, NULL); + ], [drm_file_err], [drivers/gpu/drm/drm_file.c],[ + AC_DEFINE(HAVE_DRM_FILE_ERR, 1, + [drm_file_err() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2efe5482d822e..5a5a0c42db610 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -248,6 +248,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY + AC_AMDGPU_DRM_FILE_ERR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From ded7b613d0c742cbb5ea5416a6d911ece43dc024 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 16 May 2025 12:30:10 +0800 Subject: [PATCH 1505/2070] drm/amdkcl: test whether drm_file->client_name exist It's caused by 4c26d90bcd "drm: add DRM_SET_CLIENT_NAME ioctl" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/kcl_drm_file.c | 11 +++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_file.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_file.m4 diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index 70327a98cee90..24e3d0b5ffd00 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -128,6 +128,9 @@ void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) vaf.fmt = fmt; vaf.va = &args; +#ifdef HAVE_DRM_FILE_CLIENT_NAME + mutex_lock(&file_priv->client_name_lock); +#endif rcu_read_lock(); pid = rcu_dereference(file_priv->pid); task = pid_task(pid, @@ -136,11 +139,19 @@ void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) #else PIDTYPE_PGID); #endif +#ifdef HAVE_DRM_FILE_CLIENT_NAME + drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", + task ? task->pid : 0, file_priv->client_name ?: "Unset", &vaf); +#else drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", task ? task->pid : 0, "Unset", &vaf); +#endif va_end(args); rcu_read_unlock(); +#ifdef HAVE_DRM_FILE_CLIENT_NAME + mutex_unlock(&file_priv->client_name_lock); +#endif } EXPORT_SYMBOL(kcl_drm_file_err); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9677ad2791aa1..9ce1aa97716fd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -558,6 +558,9 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ +/* drm_file->client_name is available */ +#define HAVE_DRM_FILE_CLIENT_NAME 1 + /* drm_file_err() is available */ #define HAVE_DRM_FILE_ERR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 new file mode 100644 index 0000000000000..ad9fe77b06a05 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.12-rc1-309-g56c594d8df64 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_file *filp = NULL; + filp->client_name = NULL; + ], [ + AC_DEFINE(HAVE_DRM_FILE_CLIENT_NAME, 1, + [struct drm_file->client_name is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5a5a0c42db610..0f67faa1e3c30 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -249,6 +249,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY AC_AMDGPU_DRM_FILE_ERR + AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 951dabbc2b05c9ba5f1e8068e457766c70d182d8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:04:57 +0800 Subject: [PATCH 1506/2070] drm/amdkcl: cleanup macro AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 133 ---------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - include/kcl/backport/kcl_fence_backport.h | 17 --- include/kcl/kcl_fence.h | 15 --- 4 files changed, 167 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 49b98dd78dfa1..ca679c5e1f165 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -25,129 +25,6 @@ #define CREATE_TRACE_POINTS #include "kcl_fence_trace.h" -/* Copied from drivers/dma-buf/dma-fence.c */ -#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) -static bool -dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, - uint32_t *idx) -{ - int i; - - for (i = 0; i < count; ++i) { - struct dma_fence *fence = fences[i]; - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { - if (idx) - *idx = i; - return true; - } - } - return false; -} -#endif - -struct default_wait_cb { - struct dma_fence_cb base; - struct task_struct *task; -}; - -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT -static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); - -signed long -_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) -{ - struct default_wait_cb cb; - unsigned long flags; - signed long ret = timeout ? timeout : 1; - bool was_set; - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - return ret; - - spin_lock_irqsave(fence->lock, flags); - - if (intr && signal_pending(current)) { - ret = -ERESTARTSYS; - goto out; - } - - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - goto out; - - if (!was_set && fence->ops->enable_signaling) { - /* - * Modifications [2017-03-29] (c) [2017] - * Advanced Micro Devices, Inc. - */ - trace_kcl_fence_enable_signal(fence); - - if (!fence->ops->enable_signaling(fence)) { - dma_fence_signal_locked(fence); - goto out; - } - } - - if (!timeout) { - ret = 0; - goto out; - } - - cb.base.func = _kcl_fence_default_wait_cb; - cb.task = current; - list_add(&cb.base.node, &fence->cb_list); - - while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { - if (intr) - __set_current_state(TASK_INTERRUPTIBLE); - else - __set_current_state(TASK_UNINTERRUPTIBLE); - spin_unlock_irqrestore(fence->lock, flags); - - ret = schedule_timeout(ret); - - spin_lock_irqsave(fence->lock, flags); - if (ret > 0 && intr && signal_pending(current)) - ret = -ERESTARTSYS; - } - - if (!list_empty(&cb.base.node)) - list_del(&cb.base.node); - __set_current_state(TASK_RUNNING); - -out: - spin_unlock_irqrestore(fence->lock, flags); - return ret; -} -EXPORT_SYMBOL(_kcl_fence_default_wait); -#endif - -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT -signed long -_kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) -{ - signed long ret; - - if (WARN_ON(timeout < 0)) - return -EINVAL; - - /* - * Modifications [2017-03-29] (c) [2017] - * Advanced Micro Devices, Inc. - */ - trace_kcl_fence_wait_start(fence); - if (fence->ops->wait) - ret = fence->ops->wait(fence, intr, timeout); - else - ret = _kcl_fence_default_wait(fence, intr, timeout); - trace_kcl_fence_wait_end(fence); - return ret; -} -EXPORT_SYMBOL(_kcl_fence_wait_timeout); -#endif - #ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING bool _kcl_fence_enable_signaling(struct dma_fence *f) { @@ -155,16 +32,6 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f) } EXPORT_SYMBOL(_kcl_fence_enable_signaling); #endif -/* - * Modifications [2016-12-23] (c) [2016] - * Advanced Micro Devices, Inc. - */ -void amdkcl_fence_init(void) -{ -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT - _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); -#endif -} #if !defined(HAVE_DMA_FENCE_DESCRIBE) /** diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 7b33f819a874f..9b461ef77d2a3 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,7 +3,6 @@ #include extern void amdkcl_dev_cgroup_init(void); -extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); @@ -14,7 +13,6 @@ extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { amdkcl_dev_cgroup_init(); - amdkcl_fence_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 43d13b95da2be..e70e8a809c228 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -4,23 +4,6 @@ #include #include -/* - * commit v4.9-rc2-472-gbcc004b629d2 - * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) - * - * commit v4.9-rc2-473-g698c0f7ff216 - * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) - */ -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT - -#ifdef dma_fence_default_wait -#undef dma_fence_default_wait -#endif - -#define dma_fence_default_wait _kcl_fence_default_wait -#define dma_fence_wait_timeout _kcl_fence_wait_timeout -#endif - /* * commit v4.14-rc3-601-g5f72db59160c * dma-buf/fence: Sparse wants __rcu on the object itself diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index c96d716ce94b4..04457fcb86e36 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,21 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.9-rc2-472-gbcc004b629d2 - * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) - * - * commit v4.9-rc2-473-g698c0f7ff216 - * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) -#define AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT -signed long -_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout); -extern signed long _kcl_fence_wait_timeout(struct fence *fence, bool intr, - signed long timeout); -#endif - /* * commit v4.14-rc3-601-g5f72db59160c * dma-buf/fence: Sparse wants __rcu on the object itself From 04b5aa691f52df7c2c111785f8d1f99478c57d67 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:15:41 +0800 Subject: [PATCH 1507/2070] drm/amdkcl: cleanup macro AMDKCL_DRM_DP_CEC_XXX_CHECK_CB These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../kcl/backport/kcl_drm_dp_helper_backport.h | 10 ---- include/kcl/kcl_drm_dp_cec.h | 47 +------------------ 2 files changed, 1 insertion(+), 56 deletions(-) diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 61b4a14bb0151..3955ccaa33951 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -4,16 +4,6 @@ #include -/* - * commit v4.19-rc1-100-g5ce70c799ac2 - * drm_dp_cec: check that aux has a transfer function - */ -#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) -#define drm_dp_cec_irq _kcl_drm_dp_cec_irq -#define drm_dp_cec_set_edid _kcl_drm_dp_cec_set_edid -#define drm_dp_cec_unset_edid _kcl_drm_dp_cec_unset_edid -#endif - #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) #define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector #endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index a50c290cc7248..6c5e559ca9f35 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,52 +8,7 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#include - -/* - * commit v4.19-rc1-100-g5ce70c799ac2 - * drm_dp_cec: check that aux has a transfer function - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) -#define AMDKCL_DRM_DP_CEC_XXX_CHECK_CB -#endif - -/* Copied from gpu/drm/drm_dp_cec.c and modified for KCL */ -#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) -static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) -{ -#ifdef CONFIG_DRM_DP_CEC - /* No transfer function was set, so not a DP connector */ - if (!aux->transfer) - return; -#endif - - drm_dp_cec_irq(aux); -} - -static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, - const struct edid *edid) -{ -#ifdef CONFIG_DRM_DP_CEC - /* No transfer function was set, so not a DP connector */ - if (!aux->transfer) - return; -#endif - - drm_dp_cec_set_edid(aux, edid); -} - -static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) -{ -#ifdef CONFIG_DRM_DP_CEC - /* No transfer function was set, so not a DP connector */ - if (!aux->transfer) - return; -#endif - - drm_dp_cec_unset_edid(aux); -} -#endif +#include #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, From 33998252e73afa45789e7fba4e9133834431a633 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:09:17 +0800 Subject: [PATCH 1508/2070] drm/amdkcl: cleanup macro AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 20 ---------- drivers/gpu/drm/amd/backport/backport.h | 2 +- .../backport/kcl_drm_atomic_helper_backport.h | 37 ------------------- include/kcl/kcl_drm_atomic_helper.h | 10 ----- 4 files changed, 1 insertion(+), 68 deletions(-) delete mode 100644 include/kcl/backport/kcl_drm_atomic_helper_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c0f145df309d3..0851d46f3a17e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -29,26 +29,6 @@ #include #include -#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET -/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c and modified for KCL */ -void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, - struct drm_plane_state *state) -{ - state->plane = plane; - state->rotation = DRM_MODE_ROTATE_0; - -#ifdef DRM_BLEND_ALPHA_OPAQUE - state->alpha = DRM_BLEND_ALPHA_OPAQUE; -#endif -#ifdef DRM_MODE_BLEND_PREMULTI - state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; -#endif - - plane->state = state; -} -EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); -#endif - #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET /* Copied from drivers/gpu/drm/drm_atomic_state_helper.c */ void diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0ed3cb9b26045..0852f0938c44d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h deleted file mode 100644 index 44ea7b0f771d3..0000000000000 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2014 Red Hat - * Copyright (C) 2014 Intel Corp. - * Copyright (C) 2018 Intel Corp. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rob Clark - * Daniel Vetter - */ -#ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H -#define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H - -#include - -#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET -#define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset -#endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ - -#endif diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 3af6d075cbe99..98f936123fc5f 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -39,16 +39,6 @@ #define DRM_PLANE_NO_SCALING (1<<16) #endif -/* - * v4.19-rc1-206-ge267364a6e1b - * drm/atomic: Initialise planes with opaque alpha values - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) -#define AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET -void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, - struct drm_plane_state *state); -#endif - #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); From 15e56d8273da0b39f5bdf5794625af033d6dfe21 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:49:26 +0800 Subject: [PATCH 1509/2070] drm/amdkcl: cleanup macro AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 - drivers/gpu/drm/scheduler/sched_fence.c | 2 -- include/kcl/kcl_fence.h | 11 ----------- 4 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 984a752542a54..31b8fa52b42fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -190,6 +190,5 @@ static const struct dma_fence_ops amdkfd_fence_ops = { .get_driver_name = amdkfd_fence_get_driver_name, .get_timeline_name = amdkfd_fence_get_timeline_name, .enable_signaling = amdkfd_fence_enable_signaling, - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdkfd_fence_release, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 27c018d6c20e1..db7cfc4ea1c09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -854,7 +854,6 @@ static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, .enable_signaling = amdgpu_fence_enable_signaling, - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_fence_release, }; diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 5cba4c3477a18..5ff1a309d9b1b 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -191,7 +191,6 @@ static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_scheduled, }; @@ -199,7 +198,6 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, #ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 04457fcb86e36..d8e22bae79a09 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -105,17 +105,6 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f); #define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL #endif -/* - * commit v4.18-rc2-533-g418cc6ca0607 - * dma-fence: Make ->wait callback optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) -#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL \ - .wait = dma_fence_default_wait, -#else -#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL -#endif - #if !defined(HAVE_DMA_FENCE_DESCRIBE) void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); #endif From d5222d1b55f95987c68cd1fb7f1a3f14de0ca860 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:37:15 +0800 Subject: [PATCH 1510/2070] drm/amdkcl: cleanup macro AMDKCL_FENCE_GET_RCU_SAFE These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 3 +- drivers/gpu/drm/scheduler/backport/backport.h | 3 +- drivers/gpu/drm/ttm/backport/backport.h | 3 +- include/kcl/backport/kcl_fence_backport.h | 14 ------- include/kcl/kcl_dma-resv.h | 3 +- include/kcl/kcl_fence.h | 41 ------------------- 6 files changed, 8 insertions(+), 59 deletions(-) delete mode 100644 include/kcl/backport/kcl_fence_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0852f0938c44d..4617ff7768e8a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,7 +32,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index fac6271bf3095..d83c01b771f71 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -4,7 +4,8 @@ #include #include -#include +#include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 5e944f8950bbb..2f31d6a8191f3 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -9,7 +9,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h deleted file mode 100644 index e70e8a809c228..0000000000000 --- a/include/kcl/backport/kcl_fence_backport.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMDKCL_FENCE_BACKPORT_H -#define AMDKCL_FENCE_BACKPORT_H -#include -#include - -/* - * commit v4.14-rc3-601-g5f72db59160c - * dma-buf/fence: Sparse wants __rcu on the object itself - */ -#ifdef AMDKCL_FENCE_GET_RCU_SAFE -#define dma_fence_get_rcu_safe _kcl_fence_get_rcu_safe -#endif -#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 4c2b2576374ed..c183ea930a4d8 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -47,7 +47,8 @@ #define KCL_KCL_DMA_RESV_H #include -#include +#include +#include #include #include #include diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index d8e22bae79a09..bd158dc0f6907 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,47 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.14-rc3-601-g5f72db59160c - * dma-buf/fence: Sparse wants __rcu on the object itself - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) -#define AMDKCL_FENCE_GET_RCU_SAFE -static inline struct dma_fence * -_kcl_fence_get_rcu_safe(struct dma_fence __rcu **fencep) -{ - do { - struct dma_fence *fence; - - fence = rcu_dereference(*fencep); - if (!fence) - return NULL; - - if (!dma_fence_get_rcu(fence)) - continue; - - /* The atomic_inc_not_zero() inside dma_fence_get_rcu() - * provides a full memory barrier upon success (such as now). - * This is paired with the write barrier from assigning - * to the __rcu protected fence pointer so that if that - * pointer still matches the current fence, we know we - * have successfully acquire a reference to it. If it no - * longer matches, we are holding a reference to some other - * reallocated pointer. This is possible if the allocator - * is using a freelist like SLAB_TYPESAFE_BY_RCU where the - * fence remains valid for the RCU grace period, but it - * may be reallocated. When using such allocators, we are - * responsible for ensuring the reference we get is to - * the right fence, as below. - */ - if (fence == rcu_access_pointer(*fencep)) - return rcu_pointer_handoff(fence); - - dma_fence_put(fence); - } while (1); -} -#endif - /* * commit v4.18-rc2-519-gc701317a3eb8 * dma-fence: Make ->enable_signaling optional From e8915b2660fad2d6980e688cbdf0bc45fc02fe3d Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 14:21:33 +0800 Subject: [PATCH 1511/2070] drm/amdkcl: Include for missing declaration Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c | 1 + include/kcl/kcl_shrinker.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c index fb57e87ff981b..7175409637df9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c @@ -10,6 +10,7 @@ * Multiqueue VM started 5.8.00, Rik van Riel. */ #include +#include #ifndef HAVE_SYNCHRONIZE_SHRINKERS static DECLARE_RWSEM(shrinker_rwsem); diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index ca93cd0197f9f..81270e3330cea 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -3,6 +3,8 @@ #ifndef AMDKCL_SHRINKER_H #define AMDKCL_SHRINKER_H +#include + #ifndef HAVE_SYNCHRONIZE_SHRINKERS extern void synchronize_shrinkers(void); #endif From 6298c53be58a6e2b079e38888b0d3ca6fce83f1c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 15:55:53 +0800 Subject: [PATCH 1512/2070] drm/amdkcl: Fall back to dumpversion if dumpfullversion is unsupported Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ec589e5ad3d2b..f69be8865e1b8 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -50,7 +50,7 @@ if [ "$CC" == "gcc" ]; then done fi - gcc_version=$($CC -dumpfullversion | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') + gcc_version=$(($CC -dumpfullversion 2>/dev/null || $CC -dumpversion) | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') kernel_version=$(uname -r | awk -F. '{printf "%d%02d", $1, $2}') # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. if [ "$gcc_version" -lt 40805 ] && [ "$kernel_version" -ge 0504 ]; then From e1aecb2195edd82c70249022dc1f578aaa557718 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 16 May 2025 17:35:20 +0800 Subject: [PATCH 1513/2070] drm/amdkcl: initialize the rename_symbol.h Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 987ac180e8fbd..7a9682c51f0c8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -47,6 +47,7 @@ endif dkms-config ?= amd/dkms/dkms-config.mk config-file ?= amd/dkms/config/config.h +rename_header ?= include/rename_symbol.h KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") modules: sanity-check $(dkms-config) @@ -57,7 +58,7 @@ modules: sanity-check $(dkms-config) M=$(module_build_dir) $(module_build_flags) $(Q)amd/dkms/post-build.sh $(module_build_dir) -sanity-check: pre-build $(config-file) +sanity-check: pre-build $(config-file) $(rename_header) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) @@ -70,5 +71,5 @@ pre-build: clean: $(Q)echo "Cleaning build files..." $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean - $(Q)rm -f $(dkms-config) $(config-file) + $(Q)rm -f $(dkms-config) $(config-file) $(rename_header) endif From 1f7c7e5d74811268cc9e1d8157bf943da671da87 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:56:19 +0800 Subject: [PATCH 1514/2070] drm/amdkcl: cleanup macro AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 8 -------- drivers/gpu/drm/scheduler/sched_fence.c | 2 -- include/kcl/kcl_fence.h | 13 ------------- 3 files changed, 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index ca679c5e1f165..1214d429aaf28 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -25,14 +25,6 @@ #define CREATE_TRACE_POINTS #include "kcl_fence_trace.h" -#ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING -bool _kcl_fence_enable_signaling(struct dma_fence *f) -{ - return true; -} -EXPORT_SYMBOL(_kcl_fence_enable_signaling); -#endif - #if !defined(HAVE_DMA_FENCE_DESCRIBE) /** * dma_fence_describe - Dump fence describtion into seq_file diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 5ff1a309d9b1b..179c86488a5d4 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -190,14 +190,12 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, - AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL .release = drm_sched_fence_release_scheduled, }; static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, - AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL .release = drm_sched_fence_release_finished, #ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index bd158dc0f6907..525268df513de 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,19 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.18-rc2-519-gc701317a3eb8 - * dma-fence: Make ->enable_signaling optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) -#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING -bool _kcl_fence_enable_signaling(struct dma_fence *f); -#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL \ - .enable_signaling = _kcl_fence_enable_signaling, -#else -#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL -#endif - #if !defined(HAVE_DMA_FENCE_DESCRIBE) void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); #endif From f5dcb0de1b0ff18c0ead05266031e603e667dbc9 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 2 Dec 2024 13:17:39 +0800 Subject: [PATCH 1515/2070] drm/amdkcl: wrap under code HAVE_STRUCT_XARRAY It's caused by the following commit:bf83e8c28 "drm/amdgpu: enable userqueue secure sem for GFX 12" Signed-off-by: chengjya Reviewed-by: Bob Zhou drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by following commit:6ec4ee09b510a880a1ba69529cab28b8e7550fc4 "drm/amdgpu: Implement userqueue signal/wait IOCTL " Signed-off-by: chengjya Reviewed-by: Bob Zhou drm/amdkcl: wrap under code HAVE_STRUCT_XARRAY It's caused byIt's caused by following commit 7a3b085cf7c1 "drm/amdgpu: Enable userq fence interrupt support" Signed-off-by: chengjya Reviewed-by: Bob Zhou drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by 65718b00d8291 "drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ" Signed-off-by: Yang Su Reviewed-by: Bob Zhou drm/amdkcl: Replace xarray with idr in kernel < 4.20 Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 5 ++ .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 73 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 ++- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 12 ++- 7 files changed, 114 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e8c87fbaf1a86..2d5029f3ae7bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1117,6 +1117,7 @@ struct amdgpu_device { * in the EOP interrupt handler to signal the particular user * queue fence. */ +#ifdef HAVE_STRUCT_XARRAY struct xarray userq_xa; /** * @userq_doorbell_xa: Global user queue map (doorbell index → queue) @@ -1124,6 +1125,10 @@ struct amdgpu_device { * Value: struct amdgpu_usermode_queue */ struct xarray userq_doorbell_xa; +#else + struct idr userq_idr; + spinlock_t userq_lock; +#endif /* df */ struct amdgpu_df df; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 507304027ea9a..32bad98bacc06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4483,7 +4483,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->virt.rlcg_reg_lock); spin_lock_init(&adev->wb.lock); +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->userq_xa, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->userq_idr); + spin_lock_init(&adev->userq_lock); +#endif INIT_LIST_HEAD(&adev->reset_list); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b700c2b914654..762792abba3dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -819,7 +819,12 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } queue->doorbell_index = index; +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); +#else + idr_init(&queue->fence_drv_idr); + spin_lock_init(&queue->fence_drv_lock); +#endif r = amdgpu_userq_fence_driver_alloc(adev, queue); if (r) { drm_file_err(uq_mgr->file, "Failed to alloc fence driver\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index f4d1d46ae15ec..c0d20343d662f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -66,7 +66,12 @@ struct amdgpu_usermode_queue { struct amdgpu_userq_obj db_obj; struct amdgpu_userq_obj fw_obj; struct amdgpu_userq_obj wptr_obj; +#ifdef HAVE_STRUCT_XARRAY struct xarray fence_drv_xa; +#else + struct idr fence_drv_idr; + spinlock_t fence_drv_lock; +#endif struct amdgpu_userq_fence_driver *fence_drv; struct dma_fence *last_fence; u32 xcp_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 3502ca2f595d8..1a8b89942d9a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -102,10 +102,17 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, fence_drv->context = dma_fence_context_alloc(1); get_task_comm(fence_drv->timeline_name, current); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->userq_xa, flags); r = xa_err(__xa_store(&adev->userq_xa, userq->doorbell_index, fence_drv, GFP_KERNEL)); xa_unlock_irqrestore(&adev->userq_xa, flags); +#else + spin_lock_irqsave(&adev->userq_lock, flags); + r = idr_alloc(&adev->userq_idr, fence_drv, userq->doorbell_index, + userq->doorbell_index + 1, GFP_KERNEL); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif if (r) goto free_seq64; @@ -121,11 +128,16 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, return r; } +#ifdef HAVE_STRUCT_XARRAY static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) +#else +static void amdgpu_userq_walk_and_drop_fence_drv(struct idr *idr, spinlock_t *idr_lock) +#endif { struct amdgpu_userq_fence_driver *fence_drv; unsigned long index; +#ifdef HAVE_STRUCT_XARRAY if (xa_empty(xa)) return; @@ -136,6 +148,18 @@ static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) } xa_unlock(xa); +#else + if (idr_is_empty(idr)) + return; + + spin_lock(idr_lock); + idr_for_each_entry(idr, fence_drv, index) { + idr_remove(idr, index); + amdgpu_userq_fence_driver_put(fence_drv); + } + + spin_unlock(idr_lock); +#endif } void @@ -143,8 +167,16 @@ amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) { dma_fence_put(userq->last_fence); +#ifdef HAVE_STRUCT_XARRAY amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); xa_destroy(&userq->fence_drv_xa); +#else + unsigned long flags; + amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_idr, &userq->fence_drv_lock); + spin_lock_irqsave(&userq->fence_drv_lock, flags); + idr_destroy(&userq->fence_drv_idr); + spin_unlock_irqrestore(&userq->fence_drv_lock, flags); +#endif /* Drop the fence_drv reference held by user queue */ amdgpu_userq_fence_driver_put(userq->fence_drv); } @@ -188,7 +220,12 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref) struct amdgpu_userq_fence_driver *xa_fence_drv; struct amdgpu_device *adev = fence_drv->adev; struct amdgpu_userq_fence *fence, *tmp; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; + struct spinlock *idr_lock = &adev->userq_lock; +#endif unsigned long index, flags; struct dma_fence *f; @@ -206,11 +243,19 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref) } spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); xa_for_each(xa, index, xa_fence_drv) if (xa_fence_drv == fence_drv) __xa_erase(xa, index); xa_unlock_irqrestore(xa, flags); +#else + spin_lock_irqsave(idr_lock, flags); + idr_for_each_entry(idr, xa_fence_drv, index) + if (xa_fence_drv == fence_drv) + idr_remove(idr, index); + spin_unlock_irqrestore(idr_lock, flags); +#endif /* Free seq64 memory */ amdgpu_seq64_free(adev, fence_drv->va); @@ -256,13 +301,22 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, amdgpu_userq_fence_driver_get(fence_drv); dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY if (!xa_empty(&userq->fence_drv_xa)) { +#else + if (!idr_is_empty(&userq->fence_drv_idr)) { +#endif struct amdgpu_userq_fence_driver *stored_fence_drv; unsigned long index, count = 0; int i = 0; +#ifdef HAVE_STRUCT_XARRAY xa_lock(&userq->fence_drv_xa); xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) +#else + spin_lock(&userq->fence_drv_lock); + idr_for_each_entry(&userq->fence_drv_idr, stored_fence_drv, index) +#endif count++; userq_fence->fence_drv_array = @@ -271,15 +325,25 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, GFP_ATOMIC); if (userq_fence->fence_drv_array) { +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) { userq_fence->fence_drv_array[i] = stored_fence_drv; __xa_erase(&userq->fence_drv_xa, index); +#else + idr_for_each_entry(&userq->fence_drv_idr, stored_fence_drv, index) { + userq_fence->fence_drv_array[i] = stored_fence_drv; + idr_remove(&userq->fence_drv_idr, index); +#endif i++; } } userq_fence->fence_drv_array_count = i; +#ifdef HAVE_STRUCT_XARRAY xa_unlock(&userq->fence_drv_xa); +#else + spin_unlock(&userq->fence_drv_lock); +#endif } else { userq_fence->fence_drv_array = NULL; userq_fence->fence_drv_array_count = 0; @@ -334,7 +398,6 @@ static void amdgpu_userq_fence_free(struct rcu_head *rcu) /* Release the fence driver reference */ amdgpu_userq_fence_driver_put(fence_drv); - kvfree(userq_fence->fence_drv_array); kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); } @@ -948,9 +1011,17 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, * Otherwise, we would gather those references until we don't * have any more space left and crash. */ +#ifdef HAVE_STRUCT_XARRAY r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, xa_limit_32b, GFP_KERNEL); if (r) +#else + spin_lock(&waitq->fence_drv_lock); + r = idr_alloc(&waitq->fence_drv_idr, fence_drv, 0, 0, GFP_KERNEL); + index = r; + spin_unlock(&waitq->fence_drv_lock); + if (r < 0) +#endif goto free_fences; amdgpu_userq_fence_driver_get(fence_drv); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index b1a1b8a10a08b..a57942dc1c984 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6489,14 +6489,24 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; - struct xarray *xa = &adev->userq_xa; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY + struct xarray *xa = &adev->userq_xa; xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + struct idr *idr = &adev->userq_idr; + + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index a418ae609c363..dc4b5162163f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4855,14 +4855,24 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; - struct xarray *xa = &adev->userq_xa; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY + struct xarray *xa = &adev->userq_xa; xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + struct idr *idr = &adev->userq_idr; + + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; From d6e27a424068a63e09b49a3873f66757aa19dcf3 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 16 May 2025 17:08:15 +0800 Subject: [PATCH 1516/2070] drm/amdkcl: wrap code under amdkcl_gem_resvp It's caused by the commit: 6a0f144be2 "drm/amdgpu: Add separate array of read and write for BO handles" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 1a8b89942d9a6..a1b2fe42328c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -661,18 +661,18 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } for (i = 0; i < num_read_bo_handles; i++) { - if (!gobj_read || !gobj_read[i]->resv) + if (!gobj_read || !amdkcl_gem_resvp(gobj_read[i])) continue; - dma_resv_add_fence(gobj_read[i]->resv, fence, + dma_resv_add_fence(amdkcl_gem_resvp(gobj_read[i]), fence, DMA_RESV_USAGE_READ); } for (i = 0; i < num_write_bo_handles; i++) { - if (!gobj_write || !gobj_write[i]->resv) + if (!gobj_write || !amdkcl_gem_resvp(gobj_write[i])) continue; - dma_resv_add_fence(gobj_write[i]->resv, fence, + dma_resv_add_fence(amdkcl_gem_resvp(gobj_write[i]), fence, DMA_RESV_USAGE_WRITE); } @@ -855,7 +855,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), DMA_RESV_USAGE_READ, fence) num_fences++; } @@ -864,7 +864,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), DMA_RESV_USAGE_WRITE, fence) num_fences++; } @@ -896,7 +896,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), DMA_RESV_USAGE_READ, fence) { if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { r = -EINVAL; @@ -913,7 +913,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), DMA_RESV_USAGE_WRITE, fence) { if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { r = -EINVAL; From b852cf5417d2d95ca17491714ef8b6aa6f321e91 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 20 May 2025 18:07:36 +0800 Subject: [PATCH 1517/2070] drm/amdkcl: fake ttm_backup_backup_page Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 | 16 ++++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_folio_backport.h | 24 ++++++++++++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 create mode 100644 include/kcl/kcl_folio_backport.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f67faa1e3c30..1b9335bdca53b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -244,6 +244,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_AMDGPU_MODULE_IMPORT_NS AC_AMDGPU_DRM_DEV_WEDGED_EVENT + AC_AMDGPU_SHMEM_READ_FOLIO AC_AMDGPU_DRM_DRIVER_DATE AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 new file mode 100644 index 0000000000000..fa41d75272979 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-rc4-463-gf01b2b3ed873 +dnl # shmem: add shmem_read_folio() and shmem_read_folio_gfp() +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_READ_FOLIO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + shmem_read_folio(NULL, 0); + ], [ + AC_DEFINE(HAVE_SHMEM_READ_FOLIO, 1, + [shmem_read_folio() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 2f31d6a8191f3..031c823e94bcd 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -23,5 +23,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_folio_backport.h b/include/kcl/kcl_folio_backport.h new file mode 100644 index 0000000000000..d21357052755e --- /dev/null +++ b/include/kcl/kcl_folio_backport.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_FOLIO_BACKPORT_H +#define _KCL_FOLIO_BACKPORT_H +#include + +#ifndef HAVE_SHMEM_READ_FOLIO + +#define folio page +#define folio_file_page(p, i) p +#define shmem_read_folio shmem_read_mapping_page +#define shmem_read_folio_gfp shmem_read_mapping_page_gfp +#define folio_lock lock_page +#define folio_unlock unlock_page +#define folio_mark_accessed mark_page_accessed +#define folio_mark_dirty set_page_dirty +#define folio_mapped page_mapcount +#define folio_clear_dirty_for_io clear_page_dirty_for_io +#define folio_set_reclaim SetPageReclaim +#define folio_clear_reclaim ClearPageReclaim +#define folio_test_writeback PageWriteback +#define folio_put put_page +#endif + +#endif From 393c3ff33c70d43b9298a8d8e5eca1d9b490d97e Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 27 May 2025 10:31:33 +0800 Subject: [PATCH 1518/2070] drm/amdkcl: wrap code under amdkcl_ttm_resvp It's cause by the commit: 70d645deac98 "drm/ttm: Add helpers for shrinking" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 567b3f12f23e2..e8c22d55761d5 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -1113,7 +1113,7 @@ long ttm_bo_shrink(struct ttm_operation_ctx *ctx, struct ttm_buffer_object *bo, struct ttm_device *bdev = bo->bdev; long lret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (flags.allow_move && bo->resource->mem_type != TTM_PL_SYSTEM) { int ret = ttm_bo_validate(bo, &sys_placement, ctx); From fcc9b4da97ce0e64a60e66b5de96b0022cd9a709 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 27 May 2025 11:30:46 +0800 Subject: [PATCH 1519/2070] drm/amdkcl: include writeback.h for pre-v4.2 kernels ttm_backup.c requires struct writeback_control, but pre-v4.2 kernels lack the memcontrol.h -> writeback.h include path. Directly include writeback.h in backport.h to fix this. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/ttm/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 031c823e94bcd..b5c736e2211d9 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,6 +3,7 @@ #define AMDTTM_BACKPORT_H #include +#include #include #include #include From 9051843419754d3b4a52668b9ec81f2485d85e0d Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 27 May 2025 13:15:01 +0800 Subject: [PATCH 1520/2070] drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by the commit: 61a039d1757b "drm/amdgpu: add initial support for sdma v6.0" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index b005672f2f96b..377f9fb7aa438 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1663,16 +1663,30 @@ static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; + struct spinlock_t *idr_lock = &adev->userq_lock; +#endif unsigned long flags; doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); +#else + spin_lock_irqsave(idr_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); +#endif if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(xa, flags); +#else + spin_unlock_irqrestore(idr_lock, flags); +#endif } return 0; From fb9c4a427138de64140016f14e492518dbf2182e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 May 2025 15:24:28 +0800 Subject: [PATCH 1521/2070] drm/amdkcl: fix module build to adapt for kbuild It's caused by v6.9-rc5-21-gb1992c3772e6 "kbuild: use $(src) instead of $(srctree)/$(src) for source directory" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 7fea74ffe51d6..ce2e02ff1f395 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,7 +23,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) +FULL_AMD_PATH := $(src)/.. DISPLAY_FOLDER_NAME := display FULL_AMD_DISPLAY_PATH := $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) From cdd7373976a40ff07f4bb33cada6889046c931c4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 27 May 2025 09:30:31 +0800 Subject: [PATCH 1522/2070] drm/amdkcl: string objtool from cflags for conftest objtool is unnecessary for conftest. Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 486bb816b43df..122ed7720922c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -3,13 +3,13 @@ dnl # extract cc, cflags, cppflags dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ AS_IF([test -s .conftest.o.cmd], [ - _conftest_cmd=$(head -1 .conftest.o.cmd) + _conftest_cmd=$(head -1 .conftest.o.cmd | sed 's/.*:= //;s/;.*//;s/^[[[:space:]]]*//') - CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[1]}') CPP="$CC -E" CFLAGS=$(echo $_conftest_cmd | \ - cut -d ' ' -f 4- | \ + cut -d ' ' -f 2- | \ sed -e "s|\./|${LINUX_OBJ}/|g" \ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ @@ -17,7 +17,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') CPPFLAGS=$(echo $CFLAGS | \ - cut -d ';' -f 1 | \ sed 's| -|\n&|g' | \ sed -n -e '/conftest/d' \ -e '/KBUILD/d' \ From 89698b2896ca546583e8e0935a96f92d0d65b72d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 23 Mar 2025 13:43:43 +0800 Subject: [PATCH 1523/2070] drm/amdkcl: fake kunit_fail_current_test It's caused by v5.12-rc2-4-g359a376081d4 kunit: support failure from dynamic analysis tools Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/Makefile.drm_buddy | 3 ++- drivers/gpu/drm/amd/dkms/backport_drm_buddy.h | 7 +++++++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/kunit/test-bug.h | 9 +++++++++ include/kcl/kcl_test-bug.h | 18 ++++++++++++++++++ 5 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/backport_drm_buddy.h create mode 100644 include/kcl/header/kunit/test-bug.h create mode 100644 include/kcl/kcl_test-bug.h diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy index 208c05b48758d..6af49f111bc9c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy @@ -1,6 +1,7 @@ export CONFIG_DRM_BUDDY=m subdir-ccflags-y += -DCONFIG_DRM_BUDDY -CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +CFLAGS_drm_buddy.o += -include $(src)/amd/dkms/backport_drm_buddy.h \ + -DHAVE_CONFIG_H amddrm_buddy-y := drm_buddy.o obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h new file mode 100644 index 0000000000000..c5ccbc3a8741c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_DRM_BUDDY_H +#define _KCL_BACKPORT_DRM_BUDDY_H + +#include + +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 7b6f715c04fa8..bf27afe78e544 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -174,4 +174,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #linux/compiler.h: Split into compiler.h and compiler_types.h dnl AC_KERNEL_CHECK_HEADERS([linux/compiler_types.h]) + + dnl #v5.12-rc2-4-g359a376081d4 + dnl #kunit: support failure from dynamic analysis tools + dnl + AC_KERNEL_CHECK_HEADERS([kunit/test-bug.h]) ]) diff --git a/include/kcl/header/kunit/test-bug.h b/include/kcl/header/kunit/test-bug.h new file mode 100644 index 0000000000000..5f0fde68c25c6 --- /dev/null +++ b/include/kcl/header/kunit/test-bug.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_KUNIT_TEST_BUG_H_H +#define _KCL_HEADER_KUNIT_TEST_BUG_H_H + +#ifdef HAVE_KUNIT_TEST_BUG_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_test-bug.h b/include/kcl/kcl_test-bug.h new file mode 100644 index 0000000000000..dad04656f158b --- /dev/null +++ b/include/kcl/kcl_test-bug.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * KUnit API providing hooks for non-test code to interact with tests. + * + * Copyright (C) 2020, Google LLC. + * Author: Uriel Guajardo + */ + +#ifndef _KCL_KUNIT_TEST_BUG_H +#define _KCL_KUNIT_TEST_BUG_H + +#include +#include + +#ifndef kunit_fail_current_test +#define kunit_fail_current_test(fmt, ...) do {} while (0) +#endif +#endif From 4aeebcd6adee3a544882c5c61f778a2c51815b07 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 3 Jun 2025 17:07:11 +0800 Subject: [PATCH 1524/2070] drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by 96236ac46 "drm/amdgpu: Add userq fence support to SDMAv7.0" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 5679a94d0815e..60e8453638896 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1595,16 +1595,28 @@ static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; +#endif unsigned long flags; doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } return 0; From 6b6e4f7f9829a8e37fb0143855feceb21de8eacb Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 4 Jun 2025 14:46:14 +0800 Subject: [PATCH 1525/2070] drm/amdkcl: test whether size_mul() exist It's caused by c72e473642e23d "drm/amdgpu: Fix integer overflow issues in amdgpu_userq_fence.c" Signed-off-by: Yang Su --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/overflow.m4 | 16 ++++++++++++++++ include/kcl/kcl_overflow.h | 9 +++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/overflow.m4 create mode 100644 include/kcl/kcl_overflow.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4617ff7768e8a..6638b87f2ec8d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -144,5 +144,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9ce1aa97716fd..b5186f2c2f818 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1035,6 +1035,9 @@ /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ +/* size_mul() is available */ +#define HAVE_SIZE_MUL 1 + /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1b9335bdca53b..396815947e45d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -251,6 +251,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME + AC_AMDGPU_SIZE_MUL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 new file mode 100644 index 0000000000000..1e56299b3693f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.17-rc3-2-ge1be43d9b5d0 +dnl # overflow: Implement size_t saturating arithmetic helpers +dnl # +AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_mul(NULL, NULL); + ], [ + AC_DEFINE(HAVE_SIZE_MUL, 1, + [size_mul() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_overflow.h b/include/kcl/kcl_overflow.h new file mode 100644 index 0000000000000..6a0403d4c05ec --- /dev/null +++ b/include/kcl/kcl_overflow.h @@ -0,0 +1,9 @@ +#ifndef __KCL_LINUX_OVERFLOW_H +#define __KCL_LINUX_OVERFLOW_H + +#include + +#ifndef HAVE_SIZE_MUL +#define size_mul array_size +#endif +#endif From 7d1b3f6f66a9d4384ff62d4a507969f17c0f591f Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 10 Jun 2025 10:59:14 +0800 Subject: [PATCH 1526/2070] drm/amdkcl: fix size_mul() unused cause m4 detect fail size_mul is declared with __attribute__((warn_unused_result)), but it's not being used. use a size_t variable to store the size_mul() return value. It's caused by f73fa446f6e "drm/amdkcl: test whether size_mul() exist" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/overflow.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 index 1e56299b3693f..7ee5a99374193 100644 --- a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - size_mul(NULL, NULL); + size_t offset; + offset = size_mul(0, 0); ], [ AC_DEFINE(HAVE_SIZE_MUL, 1, [size_mul() is available]) From b33920cea9d06caaa9dd162afc1d65b7b1eec194 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 6 Jun 2025 14:04:21 +0800 Subject: [PATCH 1527/2070] drm/amdkcl: fix drm_edid_is_valid const warning drm_edid_is_valid() need the non const parm, so update kcl drm_edid->edid. Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- include/kcl/kcl_drm_edid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 05afadb754485..b992c2f76a6c5 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -29,7 +29,7 @@ struct drm_edid { /* Size allocated for edid */ size_t size; - const struct edid *edid; + struct edid *edid; }; #endif From 628208b8bef55762bc757e93695d3d002045b165 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 19 Jun 2025 10:55:38 +0800 Subject: [PATCH 1528/2070] drm/amdkcl:test whether drm_crtc_helper_mode_valid_fixed() is available It's caused by 216b9bbaeaea9 "drm/probe-helper: Add drm_crtc_helper_mode_valid_fixed()" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c | 27 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_probe_helper.m4 | 16 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_probe_helper.h | 17 ++++++++++++ 7 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 create mode 100644 include/kcl/kcl_drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4e692b75892f6..a1f29af59da14 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c new file mode 100644 index 0000000000000..9af3a1dd37f26 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c @@ -0,0 +1,27 @@ +#include + +#ifndef HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED +/** + * drm_crtc_helper_mode_valid_fixed - Validates a display mode + * @crtc: the crtc + * @mode: the mode to validate + * @fixed_mode: the display hardware's mode + * + * Returns: + * MODE_OK on success, or another mode-status code otherwise. + */ +enum drm_mode_status kcl_drm_crtc_helper_mode_valid_fixed(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + const struct drm_display_mode *fixed_mode) +{ + if (mode->hdisplay != fixed_mode->hdisplay && mode->vdisplay != fixed_mode->vdisplay) + return MODE_ONE_SIZE; + else if (mode->hdisplay != fixed_mode->hdisplay) + return MODE_ONE_WIDTH; + else if (mode->vdisplay != fixed_mode->vdisplay) + return MODE_ONE_HEIGHT; + + return MODE_OK; +} +EXPORT_SYMBOL(kcl_drm_crtc_helper_mode_valid_fixed); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6638b87f2ec8d..3c32a0857a69a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -145,5 +145,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b5186f2c2f818..33f87fa31cced 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -259,6 +259,9 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 +/* drm_crtc_helper_mode_valid_fixed() is available */ +#define HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED 1 + /* drm_dbg_printer() is available */ #define HAVE_DRM_DBG_PRINTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 new file mode 100644 index 0000000000000..12aea115000fb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc6-1875-g216b9bbaeaea +dnl # drm/probe-helper: Add drm_crtc_helper_mode_valid_fixed() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_crtc_helper_mode_valid_fixed(NULL, NULL, NULL); + ], [drm_crtc_helper_mode_valid_fixed], [drivers/gpu/drm/drm_probe_helper.c],[ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED, 1, + [drm_crtc_helper_mode_valid_fixed() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 396815947e45d..1b8b8e1f9d2ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -252,6 +252,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL + AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_probe_helper.h b/include/kcl/kcl_drm_probe_helper.h new file mode 100644 index 0000000000000..0b2fdfbe04a08 --- /dev/null +++ b/include/kcl/kcl_drm_probe_helper.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#ifndef __KCL_DRM_PROBE_HELPER_H__ +#define __KCL_DRM_PROBE_HELPER_H__ + +#ifndef HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED +#include +#include +#include + +enum drm_mode_status kcl_drm_crtc_helper_mode_valid_fixed(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + const struct drm_display_mode *fixed_mode); + +#define drm_crtc_helper_mode_valid_fixed kcl_drm_crtc_helper_mode_valid_fixed +#endif +#endif From a4bfefd228cd50c42ef9ce1a959245b903a5f643 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 18 Jun 2025 22:14:00 -0400 Subject: [PATCH 1529/2070] drm/amdgpu: Set HDP_MMHUB_RO_OVERRIDE Set HDP_MMHUB_CNTL.HDP_MMHUB_RO_OVERRIDE = 0x0 for gfx943 dGPU. This is needed for enhanced RCCL performance v2: Set the register only if not already set Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index e6c0d86d34865..239b3c8b1237b 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -36,6 +36,9 @@ #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK 0x00000010L +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT 0x4 + static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { @@ -136,6 +139,9 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, static void hdp_v4_0_init_registers(struct amdgpu_device *adev) { + uint32_t aid_mask = adev->aid_mask; + u32 tmp, i; + switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { case IP_VERSION(4, 2, 1): WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); @@ -152,6 +158,17 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0)) WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); + else if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) && + !adev->gmc.is_app_apu) { + for_each_inst(i, aid_mask) { + tmp = RREG32_SOC15(HDP, GET_INST(HDP, i), mmHDP_MMHUB_CNTL); + if (tmp & HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK ) { + tmp = REG_SET_FIELD(tmp, HDP_MMHUB_CNTL, HDP_MMHUB_RO_OVERRIDE, 0); + WREG32_SOC15(HDP, GET_INST(HDP, i), mmHDP_MMHUB_CNTL, tmp); + } + } + + } WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); From 115088a9dd458d3bd352e125b47f71f274f37746 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 24 Jun 2025 17:00:15 +0800 Subject: [PATCH 1530/2070] drm/amdkcl: fake macro funciton timer_container_of() It's caused by 41cb08555c4164996d67c78b3bf1c658075b75f1 "treewide, timers: Rename from_timer() to timer_container_of()" Signed-off-by: Bob Zhou --- include/kcl/kcl_time.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h index 89856adc192a5..cf6a011f8ffbb 100644 --- a/include/kcl/kcl_time.h +++ b/include/kcl/kcl_time.h @@ -10,4 +10,9 @@ void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); #endif +#ifndef timer_container_of +#define timer_container_of(var, callback_timer, timer_fieldname) \ + container_of(callback_timer, typeof(*var), timer_fieldname) +#endif + #endif /* _KCL_TIME_H */ From d333dc09760708d2e2c61ba5fb29e391f8390f4b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 10:29:44 +0800 Subject: [PATCH 1531/2070] drm/amdkcl: detect bin_attribute.read is const args It's casued by v6.15-rc1-7-g97d06802d10a sysfs: constify bin_attribute argument of bin_attribute::read/write() Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 8 ++++++++ .../drm/amd/dkms/m4/bin_attr_const_read.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 32bad98bacc06..9188d4bce56b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -258,7 +258,11 @@ static void amdgpu_device_attr_sysfs_fini(struct amdgpu_device *adev) } static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *attr, char *buf, +#else + struct bin_attribute *attr, char *buf, +#endif loff_t ppos, size_t count) { struct device *dev = kobj_to_dev(kobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 4c7cdaf90db6d..bde879114f07d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4197,8 +4197,13 @@ int is_psp_fw_valid(struct psp_bin_desc bin) } static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, +#else + struct bin_attribute *bin_attr, +#endif char *buffer, loff_t pos, size_t count) + { struct device *dev = kobj_to_dev(kobj); struct drm_device *ddev = dev_get_drvdata(dev); @@ -4233,7 +4238,11 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, } static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct device *dev = kobj_to_dev(kobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 8c0b39062b67a..a1033547ffddb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1886,7 +1886,11 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags) */ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, +#ifdef HAVE_BIN_ATTR_CONST_ARGS struct kobject *kobj, const struct bin_attribute *attr, +#else + struct kobject *kobj, struct bin_attribute *attr, +#endif char *buf, loff_t ppos, size_t count) { struct amdgpu_ras *con = diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 37e8f717c17ea..c2661d7ce179a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -659,7 +659,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) * incorrect/corrupted and we should correct our SRM by getting it from PSP */ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct hdcp_workqueue *work; @@ -683,7 +687,11 @@ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, } static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct hdcp_workqueue *work; diff --git a/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 new file mode 100644 index 0000000000000..555b5b4729a0a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v6.15-rc1-7-g97d06802d10a +dnl # sysfs: constify bin_attribute argument of bin_attribute::read/write() +dnl # +AC_DEFUN([AC_AMDGPU_BIN_ATTR_CONST_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ssize_t (*p)(struct file *, struct kobject *, const struct bin_attribute *, + char *, loff_t, size_t) = NULL; + + struct bin_attribute bin_attr; + bin_attr.read = p; + ], [ + AC_DEFINE(HAVE_BIN_ATTR_CONST_ARGS, 1, + [bin_attribute.read is const args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1b8b8e1f9d2ca..92d6aaab9e691 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -253,6 +253,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED + AC_AMDGPU_BIN_ATTR_CONST_ARGS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d43c7725d3d60cbe555f655867ef9ca3545797af Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 11:07:12 +0800 Subject: [PATCH 1532/2070] drm/amdkcl: test if drmm_cgroup_register_region() is available It's caused by 1b5447d773d461b670f29af7c5a9091cff915259 "drm/amdgpu: Add cgroups implementation" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 ++ .../amd/dkms/m4/drmm_cgroup_register_region.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 997c8f8a19d7a..3487bc738ba46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -931,9 +931,11 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) int ret; #endif +#ifdef HAVE_DRMM_CGROUP_REGISTER_REGION man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size); if (IS_ERR(man->cg)) return PTR_ERR(man->cg); +#endif ttm_resource_manager_init(man, &adev->mman.bdev, adev->gmc.real_vram_size); diff --git a/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 b/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 new file mode 100644 index 0000000000000..37cc1db772586 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.13-rc6-2-g7b0af165e2d4 +dnl # drm/drv: Add drmm managed registration helper for dmem cgroups. +dnl # +AC_DEFUN([AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drmm_cgroup_register_region(NULL,NULL,0); + ],[drmm_cgroup_register_region], [drivers/gpu/drm/drm_drv.c],[ + AC_DEFINE(HAVE_DRMM_CGROUP_REGISTER_REGION, 1, + [drmm_cgroup_register_region() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 92d6aaab9e691..5668c5ac2c167 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -254,6 +254,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SIZE_MUL AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_AMDGPU_BIN_ATTR_CONST_ARGS + AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From f7959a57b2f919f43fc69650bd62ad35bebfd0ab Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 14:27:16 +0800 Subject: [PATCH 1533/2070] drm/amdkcl: test if hrtimer_setup() is available It's caused by 690d59fee83cb0f45fae21ce3aed2b335c87c1c2 "drm/amdgpu: Switch to use hrtimer_setup()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 +++++ drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 33f33e1ba2366..5cb7848d3a7a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -202,8 +202,13 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, amdgpu_crtc->connector = NULL; amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; +#ifdef HAVE_HRTIMER_SETUP hrtimer_setup(&amdgpu_crtc->vblank_timer, &amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC, HRTIMER_MODE_REL); +#else + hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate; +#endif return ret; } diff --git a/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 b/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 new file mode 100644 index 0000000000000..456d238010a25 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.12-rc1-119-g908a1d775422 +dnl # hrtimers: Introduce hrtimer_setup() to replace hrtimer_init() +dnl # +AC_DEFUN([AC_AMDGPU_HRTIMER_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + hrtimer_setup(NULL,NULL,0,0); + ],[hrtimer_setup], [kernel/time/hrtimer.c],[ + AC_DEFINE(HAVE_HRTIMER_SETUP, 1, + [hrtimer_setup() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5668c5ac2c167..ecf44bb842f88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -255,6 +255,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_AMDGPU_BIN_ATTR_CONST_ARGS AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION + AC_AMDGPU_HRTIMER_SETUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From b8d7a7a8b7ccd5e85395911384be607450b1102d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 15:23:46 +0800 Subject: [PATCH 1534/2070] drm/amdkcl: test if ratelimit_state_reset_interval() is available It's caused by c6f7f1b2c0ff46b9069a8fbc7d167c9ead66dfce "drm/amd/pm: Avoid open-coded use of ratelimit_state structure's internals" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/ratelimit_state_reset_interval.m4 | 16 ++++++++++ include/kcl/kcl_ratelimit.h | 30 +++++++++++++++++++ 4 files changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 create mode 100644 include/kcl/kcl_ratelimit.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3c32a0857a69a..4d493712acdeb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -146,5 +146,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ecf44bb842f88..f42dcef88dfca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -256,6 +256,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BIN_ATTR_CONST_ARGS AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_AMDGPU_HRTIMER_SETUP + AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 b/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 new file mode 100644 index 0000000000000..bc80daac823ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.15-rc1-1-g56a7b9f8b059 +dnl # ratelimit: Create functions to handle ratelimit_state internals +dnl # +AC_DEFUN([AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ratelimit_state_reset_interval(NULL,0); + ],[ + AC_DEFINE(HAVE_RATELIMIT_STATE_RESET_INTERVAL, 1, + [ratelimit_state_reset_interval() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_ratelimit.h b/include/kcl/kcl_ratelimit.h new file mode 100644 index 0000000000000..29a8aaf9885d6 --- /dev/null +++ b/include/kcl/kcl_ratelimit.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_RATELIMIT_H +#define AMDKCL_RATELIMIT_H + +#include + +#ifndef HAVE_RATELIMIT_STATE_RESET_INTERVAL + +static inline int ratelimit_state_reset_miss(struct ratelimit_state *rs) +{ + int ret = rs->missed; + + rs->missed = 0; + return ret; +} + +static inline void ratelimit_state_reset_interval(struct ratelimit_state *rs, int interval_init) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&rs->lock, flags); + rs->interval = interval_init; + rs->begin = 0; + rs->printed = 0; + ratelimit_state_reset_miss(rs); + raw_spin_unlock_irqrestore(&rs->lock, flags); +} +#endif + +#endif From f6d18e67697d9f2a4a76331b5d5f7ebd8cfb0db6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 17:11:33 +0800 Subject: [PATCH 1535/2070] drm/amdkcl: wrap code out of HAVE_DRM_DP_MST_EDID_READ It's caused by 880ab14a4acace958eaaf780231ca3f60454f718 "drm/amd/display: convert more DRM_ERROR to drm_err" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 031064388eefc..d6f033b2898d5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7976,10 +7976,10 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dc_link *dc_link = aconnector->dc_link; struct dc_sink *dc_em_sink = aconnector->dc_em_sink; + struct drm_device *dev = connector->dev; #ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; struct i2c_adapter *ddc; - struct drm_device *dev = connector->dev; if (dc_link && dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; From dea21b0739a355957ed975fd6eafc071a47df67b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 13:16:24 +0800 Subject: [PATCH 1536/2070] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY Introduce macro HAVE_STRUCT_XARRAY to wrap code related to struct xarray, improving modularity and compatibility with different kernel configurations. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 82e5782652c7f..11e4c5cbf8bae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -54,7 +54,11 @@ static const guid_t amd_xcc_dsm_guid = GUID_INIT(0x8267f5d5, 0xa556, 0x44f2, #define AMD_XCC_MAX_HID 24 +#ifdef HAVE_STRUCT_XARRAY struct xarray numa_info_xa; +#else +struct idr numa_info_idr; +#endif /* Encapsulates the XCD acpi object information */ struct amdgpu_acpi_xcc_info { @@ -892,7 +896,11 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) struct amdgpu_numa_info *numa_info; int nid; +#ifdef HAVE_STRUCT_XARRAY numa_info = xa_load(&numa_info_xa, pxm); +#else + numa_info = idr_find(&numa_info_idr, pxm); +#endif if (!numa_info) { struct sysinfo info; @@ -911,7 +919,11 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) } else { numa_info->size = amdgpu_acpi_get_numa_size(nid); } +#ifdef HAVE_STRUCT_XARRAY xa_store(&numa_info_xa, numa_info->pxm, numa_info, GFP_KERNEL); +#else + idr_alloc(&numa_info_idr, numa_info, numa_info->pxm, numa_info->pxm + 1, GFP_KERNEL); +#endif } return numa_info; @@ -1152,8 +1164,11 @@ int amdgpu_acpi_enumerate_xcc(void) u32 sbdf; INIT_LIST_HEAD(&amdgpu_acpi_dev_list); +#ifdef HAVE_STRUCT_XARRAY xa_init(&numa_info_xa); - +#else + idr_init(&numa_info_idr); +#endif for (id = 0; id < AMD_XCC_MAX_HID; id++) { sprintf(hid, "%s%d", "AMD", AMD_XCC_HID_START + id); acpi_dev = acpi_dev_get_first_match_dev(hid, NULL, -1); @@ -1513,10 +1528,17 @@ void amdgpu_acpi_release(void) struct amdgpu_numa_info *numa_info; unsigned long index; +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&numa_info_xa, index, numa_info) { kfree(numa_info); xa_erase(&numa_info_xa, index); } +#else + idr_for_each_entry(&numa_info_idr, numa_info, index) { + kfree(numa_info); + idr_remove(&numa_info_idr, index); + } +#endif if (list_empty(&amdgpu_acpi_dev_list)) return; From 6f78ff6ef7a24cd5cc8e36f4a9dad2a07b3ad68f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 13:20:10 +0800 Subject: [PATCH 1537/2070] drm/amdkcl: fake acpi_dev_put() Introduces a static inline function `acpi_dev_put` to handle ACPI device reference release. Signed-off-by: Bob Zhou --- include/kcl/kcl_acpi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h index 4ad8d53bf3cec..9db57f1252d5b 100644 --- a/include/kcl/kcl_acpi.h +++ b/include/kcl/kcl_acpi.h @@ -29,6 +29,7 @@ acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) { return NULL; } +static inline void acpi_dev_put(struct acpi_device *adev) {} #endif #endif /* AMDKCL_ACPI_H */ From 1b13309220f150713f0a914e49f0e533919aaa3e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 14:09:59 +0800 Subject: [PATCH 1538/2070] drm/amdkcl: rename timer_delete* to del_timer* It's caused by 8fa7292fee5c5240402371ea89ab285ec856c916 "treewide: Switch/rename to timer_delete[_sync]()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 | 16 ++++++++++++++++ include/kcl/kcl_time.h | 7 +++++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f42dcef88dfca..aa4faa66682c9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -257,6 +257,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_AMDGPU_HRTIMER_SETUP AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL + AC_AMDGPU_TIMER_DELETE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 b/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 new file mode 100644 index 0000000000000..9f9ba523b4a56 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.1-rc1-12-gbb663f0f3c39 +dnl # timers: Rename del_timer() to timer_delete() +dnl # +AC_DEFUN([AC_AMDGPU_TIMER_DELETE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + timer_delete(NULL); + ],[ + AC_DEFINE(HAVE_TIMER_DELETE, 1, + [timer_delete() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h index cf6a011f8ffbb..ec7f479add4cf 100644 --- a/include/kcl/kcl_time.h +++ b/include/kcl/kcl_time.h @@ -5,6 +5,7 @@ #include #include #include +#include #ifndef HAVE_TIME64_TO_TM void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); @@ -15,4 +16,10 @@ void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); container_of(callback_timer, typeof(*var), timer_fieldname) #endif +#ifndef HAVE_TIMER_DELETE +#define timer_delete del_timer +#define timer_delete_sync del_timer_sync +#endif + + #endif /* _KCL_TIME_H */ From 7a640e2b1a2ae59bd769d10dd4a60c7cf4147b3b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 15:01:49 +0800 Subject: [PATCH 1539/2070] drm/amdkcl: test shmem_writeout() is available It's caused by fe75adffac33eeb167b378861d80c805b234495c "ttm: Call shmem_writeout() from ttm_backup_backup_page()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 | 16 ++++++++++++++++ drivers/gpu/drm/ttm/ttm_backup.c | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index aa4faa66682c9..a25c2a8e6550f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -258,6 +258,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_HRTIMER_SETUP AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_AMDGPU_TIMER_DELETE + AC_AMDGPU_SHMEM_WRITEOUT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 new file mode 100644 index 0000000000000..92f9099fb34e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.15-rc1-5-g7b73c12c6ebf +dnl # shmem: Add shmem_writeout() +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_WRITEOUT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT, 1, + [shmem_writeout() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_backup.c b/drivers/gpu/drm/ttm/ttm_backup.c index 32530c75f0385..3c65b024fee49 100644 --- a/drivers/gpu/drm/ttm/ttm_backup.c +++ b/drivers/gpu/drm/ttm/ttm_backup.c @@ -115,7 +115,11 @@ ttm_backup_backup_page(struct file *backup, struct page *page, if (writeback && !folio_mapped(to_folio) && folio_clear_dirty_for_io(to_folio)) { folio_set_reclaim(to_folio); +#ifdef HAVE_SHMEM_WRITEOUT ret = shmem_writeout(to_folio, NULL, NULL); +#else + ret = mapping->a_ops->writepage(folio_file_page(to_folio, idx), NULL); +#endif if (!folio_test_writeback(to_folio)) folio_clear_reclaim(to_folio); /* From 88681d6b2bf0f5700be1f4d86c670871bc3b3dbf Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 16:51:55 +0800 Subject: [PATCH 1540/2070] drm/amdkcl: test shmem_writeout want 3 args Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 | 13 +++++++++++++ drivers/gpu/drm/ttm/ttm_backup.c | 13 +++++++++++++ 3 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 33f87fa31cced..479b59fa957b1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1032,6 +1032,18 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 +/* sg_alloc_table_from_pages_segment() is available */ +#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 + +/* shmem_read_folio() is available */ +#define HAVE_SHMEM_READ_FOLIO 1 + +/* shmem_writeout() is available */ +#define HAVE_SHMEM_WRITEOUT 1 + +/* shmem_writeout() wants 3 arguments */ +/* #undef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS */ + /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 index 92f9099fb34e0..1becbe3ee7c21 100644 --- a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 @@ -11,6 +11,19 @@ AC_DEFUN([AC_AMDGPU_SHMEM_WRITEOUT], [ ],[shmem_writeout], [mm/shmem.c],[ AC_DEFINE(HAVE_SHMEM_WRITEOUT, 1, [shmem_writeout() is available]) + ],[ + dnl # + dnl # commit v6.16-rc5-20-g44b1b073eb36 + dnl # mm: stop passing a writeback_control structure to shmem_writeout + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL,NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS, 1, + [shmem_writeout() wants 3 arguments]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_backup.c b/drivers/gpu/drm/ttm/ttm_backup.c index 3c65b024fee49..b31b324735b50 100644 --- a/drivers/gpu/drm/ttm/ttm_backup.c +++ b/drivers/gpu/drm/ttm/ttm_backup.c @@ -115,7 +115,20 @@ ttm_backup_backup_page(struct file *backup, struct page *page, if (writeback && !folio_mapped(to_folio) && folio_clear_dirty_for_io(to_folio)) { folio_set_reclaim(to_folio); + +#ifndef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS + struct writeback_control wbc = { + .sync_mode = WB_SYNC_NONE, + .nr_to_write = SWAP_CLUSTER_MAX, + .range_start = 0, + .range_end = LLONG_MAX, + .for_reclaim = 1, + }; +#endif + #ifdef HAVE_SHMEM_WRITEOUT + ret = shmem_writeout(to_folio, &wbc); +#elif defined(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS) ret = shmem_writeout(to_folio, NULL, NULL); #else ret = mapping->a_ops->writepage(folio_file_page(to_folio, idx), NULL); From f7b6e5597f1dd9a8499ffa922f06025a412421a5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Jun 2025 15:46:08 +0800 Subject: [PATCH 1541/2070] drm/amdkcl: fix m4 include path to drm/drm_file.h Signed-off-by: Bob Zhou Reviewed-by: Yang Su --- drivers/gpu/drm/amd/dkms/m4/drm_file.m4 | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 index ad9fe77b06a05..c4144b607fbb7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 @@ -3,8 +3,8 @@ dnl # v6.12-rc1-309-g56c594d8df64 dnl # AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_NAME], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include ], [ struct drm_file *filp = NULL; filp->client_name = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 index fd413cbd2300a..5483d555b35eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FILE_ERR], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + #include ], [ drm_file_err(NULL, NULL); ], [drm_file_err], [drivers/gpu/drm/drm_file.c],[ From f6ff99ad3a488eaa7767a7aeff1dc0d6d823c975 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 1 Jul 2025 14:44:32 +0800 Subject: [PATCH 1542/2070] drm/amdkcl: update check usleep_range_state() The usleep_range_state() move to sleep_timeout.c from timer.c now Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 index 7540052fefc59..cac1023aef491 100644 --- a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 @@ -6,12 +6,12 @@ AC_DEFUN([AC_AMDGPU_USLEEP_RANGE_STATE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include - #include + #include ], [ - usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); - ], [usleep_range_state], [kernel/time/timer.c], [ - AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, - [usleep_range_state() is available]) - ]) + usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); + ], [usleep_range_state], [kernel/time/timer.c kernel/time/sleep_timeout.c], [ + AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, + [usleep_range_state() is available]) + ]) ]) ]) From 2b517773906675994ec64927fe6a8da839eb0131 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Jun 2025 15:58:18 +0800 Subject: [PATCH 1543/2070] drm/amdkcl: fix m4 macro define for test_funcs.mode_valid Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index b0930aa8e97cf..4495fbe5cb695 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -45,9 +45,10 @@ AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct drm_connector_helper_funcs test_funcs = { - .mode_valid = (enum drm_mode_status (*)(struct drm_connector *, const struct drm_display_mode *))0 - }; + enum drm_mode_status (*p)(struct drm_connector *, const struct drm_display_mode *) = NULL; + + struct drm_connector_helper_funcs test_funcs; + test_funcs.mode_valid = p; ], [ AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT, 1, [.mode_valid need a const drm_display_mode argument]) From 7d8dae38fc5688bac94d83dbf0fb9c3f74c08214 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 9 Apr 2021 12:30:43 -0400 Subject: [PATCH 1544/2070] drm/amdkfd: CRIU implement gpu_id remapping v2 When doing a restore on a different node, the gpu_id's on the restore node may be different. But the user space application will still refer use the original gpu_id's in the ioctl calls. Adding code to create a gpu id mapping so that kfd can determine actual gpu_id during the user ioctl's. Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin Signed-off-by: Rajneesh Bhardwaj Change-Id: I89ca4a2f5e534391e0e13cbdaf58aafee2ba6021 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 0a7e0cc02d885..cf515cb990318 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1678,14 +1678,16 @@ static int kfd_ioctl_ipc_export_handle(struct file *filep, void *data) { struct kfd_ioctl_ipc_export_handle_args *args = data; - struct kfd_dev *dev; + struct kfd_process_device *pdd; int r; - dev = kfd_device_by_id(args->gpu_id); - if (!dev) + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) return -EINVAL; - r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle, + r = kfd_ipc_export_as_handle(pdd->dev, p, args->handle, args->share_handle, args->flags); if (r) pr_err("Failed to export IPC handle\n"); From bfac837038f5461328b3da1efd9a847b45b13ab8 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 1 Apr 2020 16:35:06 -0500 Subject: [PATCH 1545/2070] drm/amdgpu: replace per_device_list by array v2 Remove per_device_list from kfd_process and replace it with a kfd_process_device pointers array of MAX_GPU_INSTANCES size. This helps to manage the kfd_process_devices binded to a specific kfd_process. Also, functions used by kfd_chardev to iterate over the list were removed, since they are not valid anymore. Instead, it was replaced by a local loop iterating the array. v2: This change aligns with 'commit 56096e4ac889 ("drm/amdgpu: replace per_device_list by array")' in amd-staging-drm-next. Signed-off-by: Alex Sierra Signed-off-by: Felix Kuehling Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index b4b93e72f2be7..49ea76b34d6b2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1043,7 +1043,6 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * local memory object */ idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { - struct kfd_process_device *peer_pdd; for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -1776,6 +1775,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->sdma_past_activity_counter = 0; pdd->user_gpu_id = dev->id; atomic64_set(&pdd->evict_duration_counter, 0); + kfd_spm_init_process_device(pdd); p->pdds[p->n_pdds++] = pdd; if (kfd_dbg_is_per_vmid_supported(pdd->dev)) @@ -2259,24 +2259,24 @@ void kfd_process_schedule_restore(struct kfd_process *p) static void kfd_process_unmap_doorbells(struct kfd_process *p) { - struct kfd_process_device *pdd; struct mm_struct *mm = p->mm; + int i; mmap_write_lock(mm); - list_for_each_entry(pdd, &p->per_device_data, per_device_list) - kfd_doorbell_unmap(pdd); + for (i = 0; i < p->n_pdds; i++) + kfd_doorbell_unmap(p->pdds[i]); mmap_write_unlock(mm); } int kfd_process_remap_doorbells_locked(struct kfd_process *p) { - struct kfd_process_device *pdd; int ret = 0; + int i; - list_for_each_entry(pdd, &p->per_device_data, per_device_list) - ret = kfd_doorbell_remap(pdd); + for (i = 0; i < p->n_pdds; i++) + ret = kfd_doorbell_remap(p->pdds[i]); return ret; } @@ -2301,8 +2301,8 @@ static int kfd_process_remap_doorbells(struct kfd_process *p) */ static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) { - struct kfd_process_device *pdd; bool busy = false; + int i; if (!keep_idle_process_evicted) return false; @@ -2313,7 +2313,9 @@ static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) */ kfd_process_unmap_doorbells(p); - list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); if (busy) break; From 904e8a1a911fdbeeeeefe61882341f290c82faf7 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 16 Nov 2021 23:15:55 -0500 Subject: [PATCH 1546/2070] drm/amdkfd: Implement DMA buf fd export from KFD v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Exports a DMA buf fd of a given KFD buffer handle. This is intended for being able to import KFD BOs into GEM contexts to leverage the amdgpu_bo_va API for more flexible virtual address mappings. It will also be used for the new upstreamable RDMA solution coming to UCX and RCCL. The corresponding user mode change (Thunk API and kfdtest) is here: https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabuf Signed-off-by: Felix Kuehling Acked-by: Christian König Reviewed-by: Xiaogang Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 3be543a926b7e..f05e9ae851922 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2788,11 +2788,12 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, goto unlock_out; } - dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); - if (IS_ERR(dmabuf)) { - r = PTR_ERR(dmabuf); + r = kfd_mem_export_dmabuf(mem); + if (r) goto unlock_out; - } + + get_dma_buf(mem->dmabuf); + dmabuf = mem->dmabuf; r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); if (r) From befff06680aefef91e8db76884011a3557ebb534 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 1 Mar 2022 22:28:53 +0800 Subject: [PATCH 1547/2070] drm/amdgpu: convert code name to ip version for noretry set v2 Use IP version rather than codename for noretry set. Signed-off-by: Yifan Zhang Reviewed-by: Alex Deucher Change-Id: I171004a0b31f27903f2db30c66f21379294aba70 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 509be09a413dd..685139592e262 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -997,6 +997,27 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) gmc->noretry = 1; else gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; + + /* keep this for kfd test fail */ + switch (adev->asic_type) { + case CHIP_VEGA10: + case CHIP_NAVI10: + case CHIP_NAVI14: + case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: + case CHIP_DIMGREY_CAVEFISH: + /* + * noretry = 0 will cause kfd page fault tests fail + * for some ASICs, so set default to 1 for these ASICs. + */ + if (amdgpu_noretry == -1) + gmc->noretry = 1; + else + gmc->noretry = amdgpu_noretry; + break; + default: + break; + } } void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, From 2c2bf50d5e62115f378264002b21ce86f8729cc3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 8 Jan 2025 16:11:42 -0500 Subject: [PATCH 1548/2070] drm/amdgpu/swsmu: set workload profile to bootup default v2 Now that we can select a workload profile dynamically when we submit work, it's best to default to the bootup default workload profile. Defaulting to other profiles prevents some power management features from kicking in during idle periods. Once all jobs have finished, the workload profile will automatically move back to default bootup for max power savings. Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 00d8a273b46dd..317ec380af788 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1318,7 +1318,7 @@ static void smu_init_power_profile(struct smu_context *smu) if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - smu_power_profile_mode_get(smu, smu->power_profile_mode); + } void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) From d3d3ca2601d2138a0f5d58c8195b86c9e1e58ac9 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 17 Apr 2024 23:19:25 -0400 Subject: [PATCH 1549/2070] drm/amdkfd: Run restore_workers on freezable WQs v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make restore workers freezable so we don't have to explicitly flush them in suspend and GPU reset code paths, and we don't accidentally try to restore BOs while the GPU is suspended. Not having to flush restore_work also helps avoid lock/fence dependencies in the GPU reset case where we're not allowed to wait for fences. A side effect of this is, that we can now have multiple concurrent threads trying to signal the same eviction fence. Rework eviction fence signaling and replacement to account for that. The GPU reset path can no longer rely on restore_process_worker to resume queues because evict/restore workers can run independently of it. Instead call a new restore_process_helper directly. v2: - Reworked eviction fence signaling - Introduced restore_process_helper v3: - Handle unsignaled eviction fences in restore_process_bos v4: - Ported to DKMS branch and squashed with "drm/amdkfd: Fix eviction fence handling" Signed-off-by: Felix Kuehling Acked-by: Christian König Tested-by: Emily Deng Signed-off-by: Alex Deucher Tested-by: Gang BA Reviewed-by: Gang BA Tested-by: Vitaly Prosyak --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 49ea76b34d6b2..5b33080fed9d4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2239,7 +2239,6 @@ static bool signal_eviction_fence(struct kfd_process *p) void kfd_process_schedule_restore(struct kfd_process *p) { - int ret; unsigned long evicted_jiffies; unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); @@ -2252,9 +2251,8 @@ void kfd_process_schedule_restore(struct kfd_process *p) delay_jiffies = 0; pr_debug("Process %d schedule restore work\n", p->pasid); - ret = queue_delayed_work(kfd_restore_wq, &p->restore_work, - delay_jiffies); - WARN(!ret, "Schedule restore work failed\n"); + if (mod_delayed_work(kfd_restore_wq, &p->restore_work, delay_jiffies)) + kfd_process_restore_queues(p); } static void kfd_process_unmap_doorbells(struct kfd_process *p) @@ -2375,7 +2373,6 @@ static int restore_process_helper(struct kfd_process *p) } ret = kfd_process_restore_queues(p); - trace_kfd_restore_process_worker_end(p, ret ? "Failed" : "Success"); if (!ret) pr_debug("Finished restoring process pid %d\n", p->lead_thread->pid); @@ -2398,6 +2395,13 @@ static void restore_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, restore_work); + + if (kfd_process_unmap_doorbells_if_idle(p)) { + pr_debug("Process %d queues idle, doorbell unmapped\n", + p->pasid); + return; + } + pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); trace_kfd_restore_process_worker_start(p); From 37f0634f13c1f2ab1258c572a0d81be8c949d100 Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Tue, 7 Jan 2025 21:59:06 -0600 Subject: [PATCH 1550/2070] drm/amdkfd: Clear MODE.VSKIP in gfx9 trap handler v2 If user shader issues S_SETVSKIP then this state will persist when executing the trap handler, causing vector instructions to be skipped. VSKIP state is already saved/restored through the MODE register. Signed-off-by: Jay Cornwall Reviewed-by: Lancelot Six --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2635 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 4 +- 2 files changed, 1322 insertions(+), 1317 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 077885df30fb9..af5c8850023ab 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,7 +274,7 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820268, + 0xbf820001, 0xbf820269, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -398,141 +398,98 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840063, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84005f, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, - 0xd2890000, 0x00000900, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840063, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84005f, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -552,137 +509,181 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850051, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbf8200c7, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001e, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf840019, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbf8200c7, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001e, + 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf840019, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, + 0xbefe00c1, 0xbeff00c1, 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1310,7 +1311,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202e4, + 0xbf820001, 0xbf8202e5, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1435,99 +1436,143 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1546,259 +1591,216 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200e3, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, - 0xbefe00c1, 0xbeff00c1, - 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200e3, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, + 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ef, + 0xbf820001, 0xbf8202f0, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1923,99 +1925,37 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2034,31 +1974,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2078,51 +2037,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2161,139 +2100,203 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, - 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, 0x80788178, 0x8e788a78, 0x8e788178, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, + 0xbefe00c1, 0xbeff00c1, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3175,7 +3178,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202fa, + 0xbf820001, 0xbf8202fb, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -3306,98 +3309,142 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, + 0xbf108080, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3417,31 +3464,51 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3480,203 +3547,139 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { @@ -4139,7 +4142,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202e8, + 0xbf820001, 0xbf8202e9, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -4270,98 +4273,133 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbf108080, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb5306, + 0x867bc17b, 0xbf840052, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84004e, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85001d, 0x24040682, + 0xd86c0000, 0x00000002, + 0xbf8cc07f, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000100, + 0xd0c9006a, 0x0000f702, + 0xbf87ffe5, 0xbf820016, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbefe016a, + 0xbf87fff6, 0xbef70000, + 0xbef000ff, 0x00000400, 0xbefe00c1, 0xbeff00c1, - 0xb8fb5306, 0x867bc17b, - 0xbf840052, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84004e, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85001d, - 0x24040682, 0xd86c0000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -4371,32 +4409,61 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000100, 0xd0c9006a, - 0x0000f702, 0xbf87ffe5, - 0xbf820016, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbefe016a, 0xbf87fff6, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4435,206 +4502,142 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200f4, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf840025, 0xbefe00c1, - 0xbeff00c1, 0xb8ef5306, - 0x866fc16f, 0xbf840020, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0xe0510200, 0x781d0000, - 0xe0510300, 0x781d0000, - 0xe0510400, 0x781d0000, - 0x807cff7c, 0x00000500, - 0x8078ff78, 0x00000500, - 0xbf0a6f7c, 0xbf85fff0, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200f4, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf840025, 0xbefe00c1, 0xbeff00c1, + 0xb8ef5306, 0x866fc16f, + 0xbf840020, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0xe0510200, + 0x781d0000, 0xe0510300, + 0x781d0000, 0xe0510400, + 0x781d0000, 0x807cff7c, + 0x00000500, 0x8078ff78, + 0x00000500, 0xbf0a6f7c, + 0xbf85fff0, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 96b80284ba386..4d959e219c2b4 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -535,7 +535,9 @@ L_SAVE: s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) - + // Clear VSKIP state now that MODE.VSKIP has been saved. + // If user shader set it then vector instructions would be skipped. + s_setvskip 0,0 /* the first wave in the threadgroup */ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit From 7b0970403ed872bcbdd4153a5fd414bf5d17e4db Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 10:39:06 +0800 Subject: [PATCH 1551/2070] drm/amdkfd: Import DMABufs for interop through DRM v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use drm_gem_prime_fd_to_handle to import DMABufs for interop. This ensures that a GEM handle is created on import and that obj->dma_buf will be set and remain set as long as the object is imported into KFD. Signed-off-by: Felix Kuehling Reviewed-by: Ramesh Errabolu Reviewed-by: Xiaogang.Chen Acked-by: Christian König Signed-off-by: Alex Deucher Signed-off-by: Bob Zhou drm/amdgpu: Remove remaining AMDKCL_AMDGPU_DMABUF_OPS refs These were missed in the cleanup patch, so remove them to allow the kernel to compile again Fixes: 083e622bbba3 ("drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DMABUF_OPS") Signed-off-by: Kent Russell Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 35 +++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 24 +------------ drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 4 --- 5 files changed, 36 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 03234bc217e6d..5006d803d456c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -386,7 +386,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, struct sg_table *sg); -int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f05e9ae851922..b1d358a24c03c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2096,7 +2096,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); - drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); + if (!mem->ipc_obj) + drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); if (mem->dmabuf) { dma_buf_put(mem->dmabuf); mem->dmabuf = NULL; @@ -2686,7 +2687,6 @@ static int import_obj_create(struct amdgpu_device *adev, get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; (*mem)->bo = bo; - (*mem)->ipc_obj = ipc_obj; (*mem)->va = va; (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->apu_prefer_gtt ? @@ -2717,6 +2717,37 @@ static int import_obj_create(struct amdgpu_device *adev, return ret; } +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, + struct dma_buf *dma_buf, + struct kfd_ipc_obj *ipc_obj, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset) +{ + struct drm_gem_object *obj; + int ret; + + if (WARN_ON(!ipc_obj)) + return -EINVAL; + + obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + ret = import_obj_create(adev, dma_buf, obj, va, drm_priv, mem, size, + mmap_offset); + if (ret) + goto err_put_obj; + + (*mem)->ipc_obj = ipc_obj; + + return 0; + +err_put_obj: + drm_gem_object_put(obj); + return ret; +} + int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index cf515cb990318..8dc64ee8cc7d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1667,7 +1667,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, - pdd->drm_priv, NULL); + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index ab5769b0fe078..055a4c9364471 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -158,7 +158,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, if (IS_ERR(pdd)) return PTR_ERR(pdd); - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, + r = amdgpu_amdkfd_gpuvm_import_ipcobj(dev->adev, dmabuf, ipc_obj, va_addr, pdd->drm_priv, &mem, &size, mmap_offset); if (r) @@ -180,28 +180,6 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, return r; } -int kfd_ipc_import_dmabuf(struct kfd_node *dev, - struct kfd_process *p, - uint32_t gpu_id, int dmabuf_fd, - uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) -{ - int r; - struct dma_buf *dmabuf = dma_buf_get(dmabuf_fd); - - if (!dmabuf) - return -EINVAL; - - mutex_lock(&p->mutex); - - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, - va_addr, handle, mmap_offset, false); - - mutex_unlock(&p->mutex); - dma_buf_put(dmabuf); - return r; -} - int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 6e92cce265d9e..ade507630818d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -43,10 +43,6 @@ int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore); -int kfd_ipc_import_dmabuf(struct kfd_node *kfd, struct kfd_process *p, - uint32_t gpu_id, int dmabuf_fd, - uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset); int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags); From 956ab3d8784c1c55e26c38a2997c4eb529a21268 Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 16 Jan 2025 10:50:51 +0800 Subject: [PATCH 1552/2070] drm/amdkcl: Have kfd driver use same PASID values from graphic driver in non-upstream code It's caused by the following commit: 77b5e44 "drm/amdkfd: Have kfd driver use same PASID values from graphic driver" Signed-off-by: chengjya Reviewed-by: Xiaogang Chen Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 22 +++++----- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 ++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 10 ++--- drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 50 +++++++++++------------ 4 files changed, 43 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 99e0d445ff2d9..c171da2dba587 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -141,7 +141,7 @@ static int kfd_doorbell_vm_fault(struct vm_area_struct *vma, struct vm_fault *vm if (!pdd) return VM_FAULT_SIGBUS; - pr_debug("Process %d doorbell vm page fault\n", pdd->process->pasid); + pr_debug("Process pid %d doorbell vm page fault\n", pdd->process->lead_thread->pid); kfd_process_remap_doorbells_locked(pdd->process); @@ -171,8 +171,8 @@ static void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) return; } - pr_debug("Process %d unmapping doorbell 0x%lx\n", - process->pasid, vma->vm_start); + pr_debug("Process pid %d unmapping doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); size = kfd_doorbell_process_slice(pdd->dev->kfd); zap_vma_ptes(vma, vma->vm_start, size); @@ -203,13 +203,13 @@ int kfd_doorbell_remap(struct kfd_process_device *pdd) vma = pdd->qpd.doorbell_vma; size = kfd_doorbell_process_slice(pdd->dev->kfd); - pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, - vma->vm_start); + pr_debug("Process pid %d remap doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); ret = vm_iomap_memory(vma, address, size); if (ret) - pr_err("Process %d failed to remap doorbell 0x%lx\n", - process->pasid, vma->vm_start); + pr_err("Process pid %d failed to remap doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); out_unlock: pdd->qpd.doorbell_mapped = 1; @@ -245,12 +245,12 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("Process %d mapping doorbell page\n" + pr_debug("Process pid %d mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - process->pasid, (unsigned long long) vma->vm_start, + process->lead_thread->pid, (unsigned long long) vma->vm_start, address, vma->vm_flags, kfd_doorbell_process_slice(dev->kfd)); pdd = kfd_get_process_device_data(dev, process); @@ -275,8 +275,8 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, * doorbell is accessed the first time */ if (pdd->qpd.doorbell_mapped == -1) { - pr_debug("Process %d evicted, unmapping doorbell\n", - process->pasid); + pr_debug("Process pid %d evicted, unmapping doorbell\n", + process->lead_thread->pid); kfd_doorbell_unmap_locked(pdd); } else { pdd->qpd.doorbell_mapped = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 5b33080fed9d4..971c672c659ca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2250,7 +2250,7 @@ void kfd_process_schedule_restore(struct kfd_process *p) else delay_jiffies = 0; - pr_debug("Process %d schedule restore work\n", p->pasid); + pr_debug("Process pid %d schedule restore work\n", p->lead_thread->pid); if (mod_delayed_work(kfd_restore_wq, &p->restore_work, delay_jiffies)) kfd_process_restore_queues(p); } @@ -2397,12 +2397,12 @@ static void restore_process_worker(struct work_struct *work) p = container_of(dwork, struct kfd_process, restore_work); if (kfd_process_unmap_doorbells_if_idle(p)) { - pr_debug("Process %d queues idle, doorbell unmapped\n", - p->pasid); + pr_debug("Process pid %d queues idle, doorbell unmapped\n", + (int)p->lead_thread->pid); return; } - pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); + pr_debug("Started restoring process pid %d\n", (int)p->lead_thread->pid); trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index c7dc812b5a483..8f458d998e872 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -682,7 +682,7 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) switch (args->op) { case KFD_IOCTL_SPM_OP_ACQUIRE: - dev->spm_pasid = p->pasid; + dev->spm_pasid = pdd->pasid; return kfd_acquire_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_RELEASE: @@ -711,17 +711,13 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) fls(amdgpu_xcp_get_partition(kfd->adev->xcp_mgr, AMDGPU_XCP_GFX, xcc_id)) - 1 : 0; dev = kfd->nodes[xcp_id]; pasid = dev->spm_pasid; - p = kfd_lookup_process_by_pasid(pasid); + p = kfd_lookup_process_by_pasid(pasid, &pdd); - if (!p) { + if (!pdd) { dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); return; /* Presumably process exited. */ } - pdd = kfd_get_process_device_data(dev, p); - if (!pdd) - return; - spin_lock_irqsave(&pdd->spm_irq_lock, flags); if (pdd->spm_cntr && pdd->spm_cntr->spm[xcc_id].is_spm_started) pdd->spm_cntr->spm[xcc_id].has_data_loss = true; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h index 16470bec1c317..5265efb3728be 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -41,12 +41,12 @@ TRACE_EVENT(kfd_map_memory_to_gpu_start, TP_PROTO(struct kfd_process *p), TP_ARGS(p), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; ), - TP_printk("pasid =%u", __entry->pasid) + TP_printk("Process pid =%u", __entry->pid) ); @@ -54,17 +54,17 @@ TRACE_EVENT(kfd_map_memory_to_gpu_end, TP_PROTO(struct kfd_process *p, u32 array_size, char *pStatusMsg), TP_ARGS(p, array_size, pStatusMsg), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __field(unsigned int, array_size) __string(pStatusMsg, pStatusMsg) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; __entry->array_size = array_size; __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), - TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", - __entry->pasid, + TP_printk("Process pid = %u, array_size = %u, StatusMsg=%s", + __entry->pid, __entry->array_size, __get_str(pStatusMsg)) ); @@ -74,15 +74,15 @@ TRACE_EVENT(kfd_kgd2kfd_schedule_evict_and_restore_process, TP_PROTO(struct kfd_process *p, u32 delay_jiffies), TP_ARGS(p, delay_jiffies), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __field(unsigned int, delay_jiffies) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; __entry->delay_jiffies = delay_jiffies; ), - TP_printk("pasid = %u, delay_jiffies = %u", - __entry->pasid, + TP_printk("Process pid = %u, delay_jiffies = %u", + __entry->pid, __entry->delay_jiffies) ); @@ -91,12 +91,12 @@ TRACE_EVENT(kfd_evict_process_worker_start, TP_PROTO(struct kfd_process *p), TP_ARGS(p), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; ), - TP_printk("pasid=%u", __entry->pasid) + TP_printk("Process pid=%u", __entry->pid) ); @@ -104,15 +104,15 @@ TRACE_EVENT(kfd_evict_process_worker_end, TP_PROTO(struct kfd_process *p, char *pStatusMsg), TP_ARGS(p, pStatusMsg), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __string(pStatusMsg, pStatusMsg) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), - TP_printk("pasid=%u, StatusMsg=%s", - __entry->pasid, __get_str(pStatusMsg)) + TP_printk("Process pid=%u, StatusMsg=%s", + __entry->pid, __get_str(pStatusMsg)) ); @@ -120,27 +120,27 @@ TRACE_EVENT(kfd_restore_process_worker_start, TP_PROTO(struct kfd_process *p), TP_ARGS(p), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; ), - TP_printk("pasid=%u", __entry->pasid) + TP_printk("Process pid=%u", __entry->pid) ); TRACE_EVENT(kfd_restore_process_worker_end, TP_PROTO(struct kfd_process *p, char *pStatusMsg), TP_ARGS(p, pStatusMsg), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __string(pStatusMsg, pStatusMsg) ), TP_fast_assign( - entry->pasid = p->pasid; + entry->pid = p->lead_thread->pid; __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), - TP_printk("pasid=%u, StatusMsg=%s", - __entry->pasid, __get_str(pStatusMsg)) + TP_printk("Process pid=%u, StatusMsg=%s", + __entry->pid, __get_str(pStatusMsg)) ); #endif From 89f36f027b03e7a471f6d91eb5b8cd4f768c8fb5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Jul 2025 16:37:05 +0800 Subject: [PATCH 1553/2070] drm/amdkcl: update drm_dev_wedged_event to 3 args It's caused by a72002cb181f350734108228b24c5d10d358f95a "drm/amdgpu: Make use of drm_wedge_task_info" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 25 +++++++++++++------ drivers/gpu/drm/amd/backport/backport.h | 2 +- .../drm/amd/dkms/m4/drm-dev-wedged-event.m4 | 9 ++++--- include/kcl/kcl_drm_drv.h | 14 ++++++++++- 4 files changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c index fcd6eab44d280..9f3cf9fbfb434 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -47,6 +47,10 @@ static const char *drm_get_wedge_recovery(unsigned int opt) } } +#define WEDGE_STR_LEN 32 +#define PID_STR_LEN 15 +#define COMM_STR_LEN (TASK_COMM_LEN + 5) + /** * drm_dev_wedged_event - generate a device wedged uevent * @dev: DRM device @@ -63,13 +67,13 @@ static const char *drm_get_wedge_recovery(unsigned int opt) * * Returns: 0 on success, negative error code otherwise. */ -int drm_dev_wedged_event(struct drm_device *dev, unsigned long method) +int kcl_drm_dev_wedged_event(struct drm_device *dev, unsigned long method, + struct drm_wedge_task_info *info) { - const char *recovery = NULL; - unsigned int len, opt; - /* Event string length up to 28+ characters with available methods */ - char event_string[32]; - char *envp[] = { event_string, NULL }; + char event_string[WEDGE_STR_LEN], pid_string[PID_STR_LEN], comm_string[COMM_STR_LEN]; + char *envp[] = { event_string, NULL, NULL, NULL }; + const char *recovery = NULL; + unsigned int len, opt; len = scnprintf(event_string, sizeof(event_string), "%s", "WEDGED="); @@ -90,8 +94,15 @@ int drm_dev_wedged_event(struct drm_device *dev, unsigned long method) drm_info(dev, "device wedged, %s\n", method == DRM_WEDGE_RECOVERY_NONE ? "but recovered through reset" : "needs recovery"); + if (info && (info->comm[0] != '\0') && (info->pid >= 0)) { + snprintf(pid_string, sizeof(pid_string), "PID=%u", info->pid); + snprintf(comm_string, sizeof(comm_string), "TASK=%s", info->comm); + envp[1] = pid_string; + envp[2] = comm_string; + } + return kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); } -EXPORT_SYMBOL(drm_dev_wedged_event); +EXPORT_SYMBOL(kcl_drm_dev_wedged_event); #endif /* HAVE_DRM_DEV_WEDGED_EVENT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4d493712acdeb..20925e7c2c3e3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -66,6 +66,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" @@ -139,7 +140,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 index 63ed3acc6c04c..64e4926c74f1d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 @@ -1,14 +1,17 @@ dnl # +dnl # commit v6.16-rc1-333-g183bccafa176 +dnl # drm: Create a task info option for wedge events +dnl # dnl # commit v6.14-rc1-238-gb7cf9f4ac1b8 dnl # drm: Introduce device wedged event dnl # AC_DEFUN([AC_AMDGPU_DRM_DEV_WEDGED_EVENT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - drm_dev_wedged_event(NULL, 0); - ], [ + drm_dev_wedged_event(NULL, 0, NULL); + ], [drm_dev_wedged_event], [drivers/gpu/drm/drm_drv.c], [ AC_DEFINE(HAVE_DRM_DEV_WEDGED_EVENT, 1, [drm_dev_wedged_event() is available]) ]) diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h index 631e84df47a9e..6715dd046571a 100644 --- a/include/kcl/kcl_drm_drv.h +++ b/include/kcl/kcl_drm_drv.h @@ -7,8 +7,18 @@ #include #include #include +#include +#include #ifndef HAVE_DRM_DEV_WEDGED_EVENT +/** + * struct drm_wedge_task_info - information about the guilty task of a wedge dev + */ +struct drm_wedge_task_info { + pid_t pid; + char comm[TASK_COMM_LEN]; +}; + /* * Recovery methods for wedged device in order of less to more side-effects. * To be used with drm_dev_wedged_event() as recovery @method. Callers can @@ -18,7 +28,9 @@ #define DRM_WEDGE_RECOVERY_REBIND BIT(1) /* unbind + bind driver */ #define DRM_WEDGE_RECOVERY_BUS_RESET BIT(2) /* unbind + reset bus device + bind */ -int drm_dev_wedged_event(struct drm_device *dev, unsigned long method); +int kcl_drm_dev_wedged_event(struct drm_device *dev, unsigned long method, + struct drm_wedge_task_info *info); +#define drm_dev_wedged_event kcl_drm_dev_wedged_event #endif /* HAVE_DRM_DEV_WEDGED_EVENT */ #endif /* AMDKCL_DRM_DRV_H */ From 6068071524fca4cbd52e24ccab0e53be3c9837c8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Jul 2025 17:39:12 +0800 Subject: [PATCH 1554/2070] drm/amdkcl: test if kmap_local_page_try_from_panic() is available It's caused by 718370ff283284f191155a5eb9d4f376aaf93bb8 "drm/ttm: Add ttm_bo_kmap_try_from_panic()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/kmap_local_page_try_from_panic.m4 | 17 +++++++++++++++++ include/kcl/kcl_highmem-internal.h | 19 ++++++++++++++++++- 3 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a25c2a8e6550f..e5fe2a8f60ca2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -259,6 +259,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_AMDGPU_TIMER_DELETE AC_AMDGPU_SHMEM_WRITEOUT + AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 b/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 new file mode 100644 index 0000000000000..d5e1f0fe49cab --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.15-rc1-272-g8702048bb831 +dnl # mm/kmap: Add kmap_local_page_try_from_panic() +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kmap_local_page_try_from_panic(NULL); + ], [ + AC_DEFINE(HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC, 1, + [kmap_local_page_try_from_panic() is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_highmem-internal.h b/include/kcl/kcl_highmem-internal.h index 7304f188d7c2d..c5f1aa90b5c7d 100644 --- a/include/kcl/kcl_highmem-internal.h +++ b/include/kcl/kcl_highmem-internal.h @@ -36,6 +36,23 @@ do { \ } while (0) #endif /* kunmap_local */ - +#ifdef CONFIG_HIGHMEM +#ifndef HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC +static inline void *kmap_local_page_try_from_panic(struct page *page) +{ + if (!PageHighMem(page)) + return page_address(page); + /* If the page is in HighMem, it's not safe to kmap it.*/ + return NULL; +} +#endif +#else +#ifndef HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC +static inline void *kmap_local_page_try_from_panic(struct page *page) +{ + return page_address(page); +} +#endif +#endif #endif From 82ca0741473c60e028e90045a65f1a74e7a1c2d9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 10:57:53 +0800 Subject: [PATCH 1555/2070] drm/amdkcl: test if pm_hibernate_is_recovering() is available It's caused by aba06c660d01fc8c8634d45cdb451439c4695d6c "drm/amdgpu: do not resume device in thaw for normal hibernation" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_hibernate_is_recovering.m4 | 17 +++++++++++++++++ include/kcl/kcl_suspend.h | 11 +++++++++-- 4 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ffd80887e374e..0016156bd8fd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2762,11 +2762,13 @@ static int amdgpu_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); +#if defined(HAVE_PM_HIBERNATE_IS_RECOVERING) || !defined(CONFIG_PM_SLEEP) /* do not resume device if it's normal hibernation */ if (console_suspend_enabled && !pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) return 0; +#endif return amdgpu_device_resume(drm_dev, true); } diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e5fe2a8f60ca2..1384afbdc060a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -260,6 +260,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TIMER_DELETE AC_AMDGPU_SHMEM_WRITEOUT AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC + AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 new file mode 100644 index 0000000000000..43400adb13498 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc6-1339-g9b934e465aaf +dnl # PM: hibernate: add new api pm_hibernate_is_recovering() +dnl # +AC_DEFUN([AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pm_hibernate_is_recovering(); + ], [ + AC_DEFINE(HAVE_PM_HIBERNATE_IS_RECOVERING, 1, + [pm_hibernate_is_recovering() is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index a5299f997479f..c112660bd0b6b 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -4,16 +4,23 @@ #include -#ifndef HAVE_KSYS_SYNC_HELPER #ifdef CONFIG_PM_SLEEP +#ifndef HAVE_KSYS_SYNC_HELPER extern void _kcl_ksys_sync_helper(void); static inline void ksys_sync_helper(void) { _kcl_ksys_sync_helper(); } +#endif /* HAVE_KSYS_SYNC_HELPER */ #else +#ifndef HAVE_KSYS_SYNC_HELPER static inline void ksys_sync_helper(void) {} -#endif /* CONFIG_PM_SLEEP */ #endif /* HAVE_KSYS_SYNC_HELPER */ + +#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING +static inline bool pm_hibernate_is_recovering(void) { return false; } +#endif +#endif /* CONFIG_PM_SLEEP */ + #endif /* AMDKCL_SUSPEND_H */ From 6bb0fe32e6971fd40bd021ca7978862ffe912150 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 26 Jun 2025 16:45:25 +0800 Subject: [PATCH 1556/2070] drm/amdkcl: test whether drm_gem_is_imported() is available It's caused by 5f8ab7454 "drm/amdgpu: Test for imported buffers with drm_gem_is_imported()" Signed-off-by: Yang Su Reviewed-by: Bob Zhou drm/amdkcl:fix dma_buf is NULL in amdgpu_dmabuf_is_xgmi_accessible The function drm_gem_is_imported() directly accesses obj->dma without first verifying its validity. Add a NULL check to prevent potential kernel crashes when handling imported objects without DMA buffers. Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_gem.h | 17 +++++++++++++++++ 4 files changed, 36 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 479b59fa957b1..f4981cadbaf12 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -573,8 +573,8 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 - /* drm_gem_plane_helper_prepare_fb() is available */ - #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 +/* drm_gem_is_imported() is available */ +#define HAVE_DRM_GEM_IS_IMPORTED 1 /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 new file mode 100644 index 0000000000000..a8110c2b201b0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-rc4-395-gb57aa47d39e9 +dnl # drm/gem: Test for imported GEM buffers with helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_IS_IMPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_is_imported(NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_IS_IMPORTED, 1, + [drm_gem_is_imported() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1384afbdc060a..05826499a383c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -261,6 +261,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SHMEM_WRITEOUT AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING + AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index da5df184d9d58..82485f6798b69 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,6 +35,9 @@ #define __KCL_KCL_DRM_GEM_H__ #include +#ifndef HAVE_DRM_GEM_IS_IMPORTED +#include +#endif #ifdef HAVE_DRM_GEM_OBJECT_RESV #define amdkcl_gem_resvp(bo) (bo->resv) @@ -79,4 +82,18 @@ static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_obje } #endif /* HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS */ +#ifndef HAVE_DRM_GEM_IS_IMPORTED +/** + * drm_gem_is_imported() - Tests if GEM object's buffer has been imported + * @obj: the GEM object + * + * Returns: + * True if the GEM object's buffer has been imported, false otherwise + */ +static inline bool drm_gem_is_imported(const struct drm_gem_object *obj) +{ + /* The dma-buf's priv field points to the original GEM object. */ + return obj->dma_buf && (obj->dma_buf->priv != obj); +} +#endif #endif From da0e05c15e8b9e885465dd0649af67cad0b685b5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 11:37:09 +0800 Subject: [PATCH 1557/2070] drm/amdkcl: test if dma_fence_init64() is available It's caused by bf33a0003d9e3b0546f2d7e91bebfd67af59f275 "dma-fence: Use a flag for 64-bit seqnos" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 4 ++++ 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 new file mode 100644 index 0000000000000..d39fec01539a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.15-rc5-1889-gbf33a0003d9e +dnl # dma-fence: Use a flag for 64-bit seqnos +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_INIT64], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_init64(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_INIT64, 1, + [dma_fence_init64() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 05826499a383c..1915d058b308f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -262,6 +262,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_AMDGPU_DRM_GEM_IS_IMPORTED + AC_AMDGPU_DMA_FENCE_INIT64 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index a24278c214244..cd1f7814fceee 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -74,4 +74,8 @@ static inline bool dma_fence_is_later_or_same(struct dma_fence *f1, return f1 == f2 || dma_fence_is_later(f1, f2); } #endif /*HAVE_DMA_FENCE_IS_LATER_OR_SAME*/ + +#ifndef HAVE_DMA_FENCE_INIT64 +#define dma_fence_init64 dma_fence_init +#endif #endif From 1aef3842e7e70d56d8dc464e7f0b211b6ed3ae03 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 13:15:16 +0800 Subject: [PATCH 1558/2070] drm/amdkcl: test if drm_file->debugfs_client is available It's caused by c03ea34cbf88dd778197a929b3269003567def55 "drm/amdgpu: add support of debugfs for mqd information" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/struct_drm_file_debugfs_client.m4 | 18 ++++++++++++++++++ 4 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index da1efb8baaad9..66ca14073948c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2162,8 +2162,10 @@ static const struct file_operations amdgpu_pt_info_fops = { void amdgpu_debugfs_vm_init(struct drm_file *file) { +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT debugfs_create_file("vm_pagetable_info", 0444, file->debugfs_client, file, &amdgpu_pt_info_fops); +#endif } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 762792abba3dd..c7d570f1d5c03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -880,6 +880,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } } +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT queue_name = kasprintf(GFP_KERNEL, "queue-%d", qid); if (!queue_name) { r = -ENOMEM; @@ -893,6 +894,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) #endif amdgpu_userq_init_hang_detect_work(queue); kfree(queue_name); +#endif args->out.queue_id = qid; atomic_inc(&uq_mgr->userq_count[queue->queue_type]); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1915d058b308f..2c0626afa6db7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -263,6 +263,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 + AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 new file mode 100644 index 0000000000000..67e95bb8cf7a8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.16-rc1-406-g1fd45bc21cec +dnl # drm: add debugfs support on per client-id basis +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file file; + file.debugfs_client = NULL; + ], [ + AC_DEFINE(STRUCT_DRM_FILE_DEBUGFS_CLIENT, 1, + [drm_file->debugfs_client is available]) + ]) + ]) +]) + From 252ffc941e6e0725e3a34034c35a4fc393419061 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 17:34:03 +0800 Subject: [PATCH 1559/2070] drm/amdkcl: wrap code under __amdkcl_assign_str It's caused by d6b7b46232b78510a12e351b738f493021edf8c3 "drm/sched: Add device name to the drm_sched_process_job event" Signed-off-by: Bob Zhou --- drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index 0bd32514d54c4..6e1ce1fe8807f 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -72,7 +72,7 @@ DECLARE_EVENT_CLASS(drm_sched_job, __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->credit_count); - __assign_str(dev); + __amdkcl_assign_str(dev, dev_name(sched_job->sched->dev)); __entry->fence_context = sched_job->s_fence->finished.context; __entry->fence_seqno = sched_job->s_fence->finished.seqno; __entry->client_id = sched_job->s_fence->drm_client_id; From 6cf038d3df3c79d870efff78c1d6013477b7c878 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 23 Jul 2025 14:19:10 +0800 Subject: [PATCH 1560/2070] drm/amdkcl: test if drm_file->client_id is available It's caused by 2956554823cedb390b7ec4534afa898176317638 "drm/sched: Store the drm client_id in drm_sched_fence" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +++++ .../amd/dkms/m4/struct_drm_memoty_status.m4 | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index f7f164704b07b..6cb5d9f698cba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -285,9 +285,14 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, } for (i = 0; i < p->gang_size; ++i) { +#ifdef HAVE_DRM_FILE_CLIENT_ID ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm, num_ibs[i], &p->jobs[i], p->filp->client_id); +#else + ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm, + num_ibs[i], &p->jobs[i], 0); +#endif if (ret) goto free_all_kdata; switch (p->adev->enforce_isolation[fpriv->xcp_id]) { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 index 3e25ff65320cf..62c60fa842710 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 @@ -18,6 +18,25 @@ AC_DEFUN([AC_AMDGPU_DRM_PRINT_MEMORY_STATS], [ ]) ]) +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3 +dnl # drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file *filp = NULL; + filp->client_id = 0; + ], [ + AC_DEFINE(HAVE_DRM_FILE_CLIENT_ID, 1, + [struct drm_file->client_id is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_FILE], [ AC_AMDGPU_DRM_PRINT_MEMORY_STATS + AC_AMDGPU_DRM_FILE_CLIENT_ID ]) From a904861d324b76a7eb41100147318cf3082965c6 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 16 Apr 2025 13:43:35 -0400 Subject: [PATCH 1561/2070] drm/amdgu: add host trap interface to support gfx12.0.* PC Sampling. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic --- .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c | 72 ++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c index e0ceab400b2da..3396a5bf31147 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c @@ -25,6 +25,8 @@ #include "gc/gc_12_0_0_offset.h" #include "gc/gc_12_0_0_sh_mask.h" #include "soc24.h" +#include "navi10_enum.h" + #include static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, @@ -367,6 +369,73 @@ static uint32_t kgd_gfx_v12_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return 0; } +static uint32_t kgd_gfx_v12_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_debug_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_debug_hosttrap_status = + RREG32_SOC15(GC, GET_INST(GC, inst), regSQ_DEBUG_HOST_TRAP_STATUS); + + if (sq_debug_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_debug_hosttrap_status; +} + +/* + * gfx12 has no way to broadcast to all WGPs but only a single SIMD within + * that WGP. Here we broadcast to 1 wave-slot on all 4 SIMDs within all WGPs, + * so target_simd is not really used for gfx12. +*/ +static uint32_t kgd_v12_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t __always_unused *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_gfx_v12_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), regSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= 16; + } else { + dev_dbg(adev->dev, "PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } + return 0; +} + const struct kfd2kgd_calls gfx_v12_kfd2kgd = { .init_interrupts = init_interrupts_v12, .hqd_dump = hqd_dump_v12, @@ -380,5 +449,6 @@ const struct kfd2kgd_calls gfx_v12_kfd2kgd = { .set_wave_launch_mode = kgd_gfx_v12_set_wave_launch_mode, .set_address_watch = kgd_gfx_v12_set_address_watch, .clear_address_watch = kgd_gfx_v12_clear_address_watch, - .hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_v12_trigger_pc_sample_trap, }; From becd3ea379aeeb7e05377df9553b21932fa870f6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 24 Jul 2025 11:10:55 +0800 Subject: [PATCH 1562/2070] drm/amdkcl: wrap code under amdkcl_ttm_resv() It's caused by 97e000acf2e20a86a50a0ec8c2739f0846f37509 "drm/ttm: fix error handling in ttm_buffer_object_transfer" Signed-off-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index e8c22d55761d5..cd2dc2e95b107 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -277,7 +277,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, ret = dma_resv_trylock(&amdkcl_ttm_resv(&fbo->base)); WARN_ON(!ret); - ret = dma_resv_reserve_fences(&fbo->base.base._resv, TTM_NUM_MOVE_FENCES); + ret = dma_resv_reserve_fences(&amdkcl_ttm_resv(&fbo->base), TTM_NUM_MOVE_FENCES); if (ret) { dma_resv_unlock(&fbo->base.base._resv); kfree(fbo); From c1e0c0e0abd33e47d882419314ae08d1c16f979c Mon Sep 17 00:00:00 2001 From: Lancelot SIX Date: Mon, 24 Mar 2025 10:59:10 +0000 Subject: [PATCH 1563/2070] drm/amdkfd: ignore sampling traps if SAVECTX also present in trap handler The trap handler can be entered for multiple reasons at the same time. It is possible to enter the trap handler to process both a context save and a sampling trap (host trap or stochastic sampling based). In that case, the general principle applies: jump to the 2nd level trap handler to let it handler the trap, and when the 2nd level trap handler calls s_rfe, the wave will re-enter the trap handler to handle the context save. However, it is possible that the sampling rate is too high, in which case a new sample trap might come in to the wave before re-entering for context save, effectively preventing the context save to succeed. This patch proposes to ignore sampling traps if a context save request is present. Signed-off-by: Lancelot SIX Reviewed-by: James Zhu Tested-by: James Zhu Reviewed-by: Jay Cornwall --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 1563 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 22 + 2 files changed, 817 insertions(+), 768 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index af5c8850023ab..ff68bba330d46 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,9 +274,12 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820269, + 0xbf820001, 0xbf82026f, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, @@ -1311,9 +1314,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202e5, + 0xbf820001, 0xbf8202eb, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, @@ -1800,9 +1806,12 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202f0, + 0xbf820001, 0xbf8202f6, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, @@ -3178,230 +3187,176 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202fb, + 0xbf820001, 0xbf82030c, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, - 0x866eff78, 0x00002000, - 0xbf84000a, 0xbf0d986d, - 0xbf850023, 0xbf0d9a7b, - 0xbf850021, 0x866eff7b, - 0x00000400, 0xbf85006f, - 0xbf8e0010, 0xb8fbf803, - 0xbf82fffa, 0x866eff7b, - 0x03800900, 0xbf850017, - 0x866eff7b, 0x000071ff, - 0xbf840008, 0x866fff7b, - 0x00007080, 0xbf840001, - 0xbeee1a87, 0xb8eff801, - 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000c, 0xbf0d986d, - 0xbf850003, 0x866eff6d, - 0x00ff0000, 0xbf850007, - 0xbf0d986d, 0xbf850006, - 0xbf0d9a7b, 0xbf850004, - 0x866eff7b, 0x00000400, - 0xbf850052, 0xbeed1a9d, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031cfd, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8e739773, - 0x8979ff79, 0x03800000, - 0x87797379, 0xbf0d986d, - 0xbf840008, 0xbf0d9879, - 0xbf840002, 0xbeed1a9d, - 0xbf820004, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xb8f3f803, - 0xbf0d9a73, 0xbf840006, - 0xbf0d9979, 0xbf840002, - 0xbeed1a9d, 0xbf820002, + 0x866eff7b, 0x04000400, + 0xbf06ff6e, 0x04000400, + 0xbf840003, 0xbefb189a, 0xba7f0683, 0x00000000, - 0xbf0d9d6d, 0xbeed189d, - 0xbf840013, 0xbef91898, - 0xbef91899, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b79, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf0c8a7b, 0xbf850007, + 0xbf0c986d, 0xbf850005, + 0xbefb1896, 0xba7f0583, + 0x00000000, 0x896dff6d, + 0x01ff0000, 0x866eff78, + 0x00002000, 0xbf84000a, + 0xbf0d986d, 0xbf850023, + 0xbf0d9a7b, 0xbf850021, + 0x866eff7b, 0x00000400, + 0xbf85006f, 0xbf8e0010, + 0xb8fbf803, 0xbf82fffa, + 0x866eff7b, 0x03800900, + 0xbf850017, 0x866eff7b, + 0x000071ff, 0xbf840008, + 0x866fff7b, 0x00007080, + 0xbf840001, 0xbeee1a87, + 0xb8eff801, 0x8e6e8c6e, + 0x866e6f6e, 0xbf85000c, + 0xbf0d986d, 0xbf850003, + 0x866eff6d, 0x00ff0000, + 0xbf850007, 0xbf0d986d, + 0xbf850006, 0xbf0d9a7b, + 0xbf850004, 0x866eff7b, + 0x00000400, 0xbf850052, + 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, 0x87797a79, 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2985, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031cfd, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8e739773, 0x8979ff79, + 0x03800000, 0x87797379, + 0xbf0d986d, 0xbf840008, + 0xbf0d9879, 0xbf840002, + 0xbeed1a9d, 0xbf820004, + 0x896dff6d, 0x01ff0000, + 0xba7f0583, 0x00000000, + 0xb8f3f803, 0xbf0d9a73, + 0xbf840006, 0xbf0d9979, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0xba7f0683, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef91898, 0xbef91899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b79, + 0x867aff7a, 0x001f8000, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8979ff79, 0xfc000000, + 0x87797a79, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0xbf108080, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3420,95 +3375,94 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3547,139 +3501,203 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, - 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, - 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, - 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, - 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, - 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, + 0x00000078, 0x80788478, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, + 0x00000078, 0x80788478, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, + 0x00000078, 0x80788478, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, + 0x00000078, 0x80788478, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, + 0x00000078, 0x80788478, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { @@ -4142,230 +4160,176 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202e9, + 0xbf820001, 0xbf8202fa, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, - 0x866eff78, 0x00002000, - 0xbf84000a, 0xbf0d986d, - 0xbf850023, 0xbf0d9a7b, - 0xbf850021, 0x866eff7b, - 0x00000400, 0xbf85006f, - 0xbf8e0010, 0xb8fbf803, - 0xbf82fffa, 0x866eff7b, - 0x03800900, 0xbf850017, - 0x866eff7b, 0x000071ff, - 0xbf840008, 0x866fff7b, - 0x00007080, 0xbf840001, - 0xbeee1a87, 0xb8eff801, - 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000c, 0xbf0d986d, - 0xbf850003, 0x866eff6d, - 0x00ff0000, 0xbf850007, - 0xbf0d986d, 0xbf850006, - 0xbf0d9a7b, 0xbf850004, - 0x866eff7b, 0x00000400, - 0xbf850052, 0xbeed1a9d, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031cfd, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8e739773, - 0x8979ff79, 0x03800000, - 0x87797379, 0xbf0d986d, - 0xbf840008, 0xbf0d9879, - 0xbf840002, 0xbeed1a9d, - 0xbf820004, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xb8f3f803, - 0xbf0d9a73, 0xbf840006, - 0xbf0d9979, 0xbf840002, - 0xbeed1a9d, 0xbf820002, + 0x866eff7b, 0x04000400, + 0xbf06ff6e, 0x04000400, + 0xbf840003, 0xbefb189a, 0xba7f0683, 0x00000000, - 0xbf0d9d6d, 0xbeed189d, - 0xbf840013, 0xbef91898, - 0xbef91899, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b79, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf0c8a7b, 0xbf850007, + 0xbf0c986d, 0xbf850005, + 0xbefb1896, 0xba7f0583, + 0x00000000, 0x896dff6d, + 0x01ff0000, 0x866eff78, + 0x00002000, 0xbf84000a, + 0xbf0d986d, 0xbf850023, + 0xbf0d9a7b, 0xbf850021, + 0x866eff7b, 0x00000400, + 0xbf85006f, 0xbf8e0010, + 0xb8fbf803, 0xbf82fffa, + 0x866eff7b, 0x03800900, + 0xbf850017, 0x866eff7b, + 0x000071ff, 0xbf840008, + 0x866fff7b, 0x00007080, + 0xbf840001, 0xbeee1a87, + 0xb8eff801, 0x8e6e8c6e, + 0x866e6f6e, 0xbf85000c, + 0xbf0d986d, 0xbf850003, + 0x866eff6d, 0x00ff0000, + 0xbf850007, 0xbf0d986d, + 0xbf850006, 0xbf0d9a7b, + 0xbf850004, 0x866eff7b, + 0x00000400, 0xbf850052, + 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, 0x87797a79, 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2985, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031cfd, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8e739773, 0x8979ff79, + 0x03800000, 0x87797379, + 0xbf0d986d, 0xbf840008, + 0xbf0d9879, 0xbf840002, + 0xbeed1a9d, 0xbf820004, + 0x896dff6d, 0x01ff0000, + 0xba7f0583, 0x00000000, + 0xb8f3f803, 0xbf0d9a73, + 0xbf840006, 0xbf0d9979, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0xba7f0683, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef91898, 0xbef91899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b79, + 0x867aff7a, 0x001f8000, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8979ff79, 0xfc000000, + 0x87797a79, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0xbf108080, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb5306, - 0x867bc17b, 0xbf840052, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84004e, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85001d, 0x24040682, - 0xd86c0000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4375,95 +4339,94 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000100, - 0xd0c9006a, 0x0000f702, - 0xbf87ffe5, 0xbf820016, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbefe016a, - 0xbf87fff6, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb5306, 0x867bc17b, + 0xbf840052, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84004e, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85001d, + 0x24040682, 0xd86c0000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000100, 0xd0c9006a, + 0x0000f702, 0xbf87ffe5, + 0xbf820016, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbefe016a, 0xbf87fff6, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4502,142 +4465,206 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200f4, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf840025, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200f4, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf840025, 0xbefe00c1, + 0xbeff00c1, 0xb8ef5306, + 0x866fc16f, 0xbf840020, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0xe0510200, 0x781d0000, + 0xe0510300, 0x781d0000, + 0xe0510400, 0x781d0000, + 0x807cff7c, 0x00000500, + 0x8078ff78, 0x00000500, + 0xbf0a6f7c, 0xbf85fff0, 0xbefe00c1, 0xbeff00c1, - 0xb8ef5306, 0x866fc16f, - 0xbf840020, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0xe0510200, - 0x781d0000, 0xe0510300, - 0x781d0000, 0xe0510400, - 0x781d0000, 0x807cff7c, - 0x00000500, 0x8078ff78, - 0x00000500, 0xbf0a6f7c, - 0xbf85fff0, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 4d959e219c2b4..dd2d93f6824ee 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -242,6 +242,28 @@ L_SKIP_RESTORE: s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // Ignore PERF_SNAPSHOT if SAVECTX is also present + s_and_b32 ttmp2, s_save_trapsts, (SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK) + s_cmp_eq_u32 ttmp2, (SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK) + s_cbranch_scc0 L_NO_SAVE_AND_PERF_SNAP + s_bitset0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT, 1), 0 +L_NO_SAVE_AND_PERF_SNAP: +#endif + + // Ignore Host Trap if SAVECTX is also present + s_bitcmp0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT + s_bitcmp0_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_bitset0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0 +#endif + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_HT_MASK | S_SAVE_PC_HI_TRAP_ID_MASK) +L_NO_SAVE_AND_HT: + s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK s_cbranch_scc0 L_NOT_HALTED From 1aa78f60c062cdf5accbd3885439412d391cf8b2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 25 Jul 2025 14:41:59 +0800 Subject: [PATCH 1564/2070] drm/amdkcl: test if __dma_fence_is_later() has fence args It's caused v6.15-rc5-762-g549810e91815 "dma-fence: Change signature of __dma_fence_is_later" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 14 ++++++++++++++ include/kcl/kcl_fence.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index 0523264d08807..d7dea8e24310d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -24,6 +24,20 @@ AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ ], [ AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, [__dma_fence_is_later() is available and has 2 args]) + ],[ + dnl # + dnl # v6.15-rc5-762-g549810e91815 + dnl # dma-fence: Change signature of __dma_fence_is_later + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence *fence = NULL; + __dma_fence_is_later(fence, 0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, + [__dma_fence_is_later() is available and has fence args]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 525268df513de..971500bce8566 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -16,6 +16,7 @@ #include #include +#ifndef HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG #if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) #if !defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) @@ -50,6 +51,7 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ +#endif /* HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG */ #if !defined(HAVE_DMA_FENCE_DESCRIBE) void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); From abaaa0ba58a8d0f2042ac7397f44bda01686df07 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 25 Jul 2025 14:51:42 +0800 Subject: [PATCH 1565/2070] drm/amdkcl: fix m4 detect issue Update CFLAGS and add NULL support for m4 detect Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 | 1 + .../dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 index 6d00ba9d43f37..17b182f9f186a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include + #include ], [ dma_fence_dedup_array(NULL, 0); ], [dma_fence_dedup_array], [drivers/dma-buf/dma-fence-unwrap.c],[ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 index 0f644628eb68c..8596ee2770a7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include struct drm_driver; ], [ const struct drm_driver *drv = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 122ed7720922c..6c1a805826365 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -15,7 +15,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') - + CFLAGS=$(echo $CFLAGS | sed -E "s/-Wunused/-Wno-unused/g") CPPFLAGS=$(echo $CFLAGS | \ sed 's| -|\n&|g' | \ sed -n -e '/conftest/d' \ From 737809bd2bd34d35fd641fdda9a5825b3f5fcf2b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Aug 2025 10:15:28 +0800 Subject: [PATCH 1566/2070] drm/amdkcl: fix intree build detect issue for __dma_fence_is_later Signed-off-by: Bob Zhou --- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index d7dea8e24310d..deb282b53858e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -1,43 +1,43 @@ dnl # -dnl # v5.1-rc2-1115-g5e498abf1485 -dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # v6.15-rc5-762-g549810e91815 +dnl # dma-fence: Change signature of __dma_fence_is_later dnl # AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - const struct dma_fence_ops *ops = NULL; - __dma_fence_is_later(0, 0, ops); - ], [ - AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, - [__dma_fence_is_later() is available and has ops arg]) - ], [ - dnl # - dnl # v4.20-rc4-931-gb312d8ca3a7c - dnl # dma-buf: make fence sequence numbers 64 bit v2 - dnl # AC_KERNEL_TRY_COMPILE([ #include ], [ - __dma_fence_is_later(0, 0); + struct dma_fence *fence = NULL; + __dma_fence_is_later(fence, 0, 0); ], [ - AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, - [__dma_fence_is_later() is available and has 2 args]) + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, + [__dma_fence_is_later() is available and has fence args]) ],[ dnl # - dnl # v6.15-rc5-762-g549810e91815 - dnl # dma-fence: Change signature of __dma_fence_is_later + dnl # v5.1-rc2-1115-g5e498abf1485 + dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno dnl # AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_fence *fence = NULL; - __dma_fence_is_later(fence, 0, 0); + const struct dma_fence_ops *ops = NULL; + __dma_fence_is_later(0, 0, ops); ], [ - AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, - [__dma_fence_is_later() is available and has fence args]) - ]) + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, + [__dma_fence_is_later() is available and has ops arg]) + ], [ + dnl # + dnl # v4.20-rc4-931-gb312d8ca3a7c + dnl # dma-buf: make fence sequence numbers 64 bit v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + __dma_fence_is_later(0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, + [__dma_fence_is_later() is available and has 2 args]) + ]) ]) ]) ]) From 79dbcd54b50c394632ab847a7eb848adaa3b7f45 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 16 Apr 2025 13:53:05 -0400 Subject: [PATCH 1567/2070] drm/amdkfd: enable host trap PC Sampling on gfx12 Signed-off-by: James Zhu Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index b2fefc190db39..7e21b69f635bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -38,9 +38,10 @@ * 1.2 - Support gfx9_5_0 Host Trap PC sampling * 1.3 - Update 1st level trap handler for Stochastic PC sampling * 1.4 - Support gfx9_5_0 Stochastic PC sampling + * 1.5 - Support gfx12_0_0 and gfx12_0_1 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 4 +#define KFD_IOCTL_PCS_MINOR_VERSION 5 struct supported_pc_sample_info { uint32_t ip_version; @@ -60,6 +61,8 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(12, 0, 0), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(12, 0, 1), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From 104e4db964f40ecac0a52b7f77a7ce0c91c8622a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 6 Aug 2025 13:27:04 +0800 Subject: [PATCH 1568/2070] drm/amdkcl: wrap code under HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW It's caused by 2d0f5001b61c4831d413d12c10caed0e99d73b25 "drm/amdgpu: Constify 'struct bin_attribute'" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index bde879114f07d..9775436c0392a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4294,7 +4294,11 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, * Writing to this file will stage an IFWI for update. Reading from this file * will trigger the update process. */ +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW static const struct bin_attribute psp_vbflash_bin_attr = { +#else +static struct bin_attribute psp_vbflash_bin_attr = { +#endif .attr = {.name = "psp_vbflash", .mode = 0660}, .size = 0, .write = amdgpu_psp_vbflash_write, From 2f493b27f0549e7e4a908dd0576aa1f30a3a3060 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Aug 2025 13:26:31 +0800 Subject: [PATCH 1569/2070] drm/amdkcl: add ttm_bo_internal.h support for ttm_bo_vm.c It's caused by 9ec1ac835e489b9ab2776c0cbbb1b1ca813923a2 "drm/ttm: make ttm_bo_get internal" som old kernel need ttm_bo_get() that has been moved into ttm_bo_internal.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 1f3bbef32a66e..5d6af369a8a8c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -42,6 +42,9 @@ #include #include +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +#include "ttm_bo_internal.h" +#endif static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, struct vm_fault *vmf, From 19b97020223b491644dbe9590dde75fdc5b834c8 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 16:34:22 +0800 Subject: [PATCH 1570/2070] drm/amdkcl: test whether drm_err_ratelimited() exist It's caused by dfc4b4c439b22da891b7e092e7be53bc62f47c5a "drm/amd: Use drm_*() macros instead of DRM_*() for amdgpu_cs" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- include/kcl/kcl_drm_print.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index f650bc4988a84..5a270ea5fafdb 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -218,4 +218,8 @@ enum drm_debug_category { __drm_printk((drm), info, _once, fmt, ##__VA_ARGS__) #endif +#ifndef drm_err_ratelimited +#define drm_err_ratelimited(drm, fmt, ...) \ + __drm_printk((drm), err, _ratelimited, "*ERROR* " fmt, ##__VA_ARGS__) +#endif #endif From 4cc1335f6ea73f5dcff8fb887c4b19bb2417b617 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 4 Aug 2025 14:50:28 +0800 Subject: [PATCH 1571/2070] drm/amdkcl: add kcl_cleanup support to amdgpu_xcp module it's caused by ef49fe639b "drm/amd/amdgpu: Release xcp drm memory after unplug" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdxcp/backport/backport.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdxcp/backport/backport.h b/drivers/gpu/drm/amd/amdxcp/backport/backport.h index 155f55d669456..d23a4e6be9d11 100644 --- a/drivers/gpu/drm/amd/amdxcp/backport/backport.h +++ b/drivers/gpu/drm/amd/amdxcp/backport/backport.h @@ -1 +1,3 @@ #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_cleanup.h" +#include "kcl/kcl_mutex.h" From f0bc09c5a5fc5c569153d5e67bd179b50838c21c Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 5 Aug 2025 15:01:39 +0800 Subject: [PATCH 1572/2070] drm/amdkcl: test whether pm_sleep_ptr() exist It's caused by d96437e2b14 "drm/amdgpu: fix link error for !PM_SLEEP" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- include/kcl/kcl_pm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 37c761718589e..05350df61dafc 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -35,4 +35,11 @@ #define DPM_FLAG_MAY_SKIP_RESUME BIT(3) #endif +/* + * v5.16-rc5-3-g1a3c7bb08826 + * PM: core: Add new *_PM_OPS macros, deprecate old ones + */ +#ifndef pm_sleep_ptr +#define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr)) +#endif #endif From 7211dbbdd243450b9aabdf2e8572ab13ad175c68 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 15:14:42 +0800 Subject: [PATCH 1573/2070] drm/amdkcl: test whether PTR_IF() exist It's caused by d96437e2b14 "drm/amdgpu: fix link error for !PM_SLEEP" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- include/kcl/kcl_kernel.h | 4 ++++ include/kcl/kcl_pm.h | 1 + 2 files changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index 47e8853f7e144..64e242971f3dc 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -34,4 +34,8 @@ #define TAINT_CPU_OUT_OF_SPEC TAINT_UNSAFE_SMP #endif +#ifndef PTR_IF +#define PTR_IF(cond, ptr) ((cond) ? (ptr) : NULL) +#endif + #endif /* AMDKCL_KERNEL_H */ diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 05350df61dafc..f3279a503a8ed 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -9,6 +9,7 @@ #include #include +#include /* * v5.7-rc2-7-ge07515563d01 From b22634dfa7cf711631228a9b6ef1321dae3f3c5a Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 15:16:25 +0800 Subject: [PATCH 1574/2070] drm/amdkcl: wrap code under HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE it's caused by 192650eee "drm/amd/display: Add primary plane to commits for correct VRR handling" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 9943f44951d3a..ff72cdd5b5ac8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -707,6 +707,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } +#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) { struct drm_plane_state *primary_state; @@ -715,6 +716,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, if (IS_ERR(primary_state)) return PTR_ERR(primary_state); } +#endif /* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) From 17a38bd13ecc1a5cfe59f69a1875f8b0014c5cc3 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 16:34:09 +0800 Subject: [PATCH 1575/2070] drm/amdkcl: test whether pm_ptr() exist It's caused by d96437e2b14f621ba4cb8ec96cccd0c60a6ef7d9 "drm/amdgpu: fix link error for !PM_SLEEP" Signed-off-by: Yang Su --- include/kcl/kcl_pm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index f3279a503a8ed..57795e4497d0c 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -43,4 +43,12 @@ #ifndef pm_sleep_ptr #define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr)) #endif + +/* + * v5.8-rc7-1-g7a82e97a11b9 + * PM: core: introduce pm_ptr() macro + */ +#ifndef pm_ptr +#define pm_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM), (_ptr)) #endif +#endif \ No newline at end of file From 9e298316264d9babebcbd070edd30be86a6f46d2 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 8 Aug 2025 10:45:58 +0800 Subject: [PATCH 1576/2070] drm/amdkcl: Fix atomic state access in crtc_helper_atomic_check When HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE is not enabled, the atomic check helper lacks direct access to the drm_atomic_state Signed-off-by: Yang Su --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index ff72cdd5b5ac8..576320a5f743f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -663,6 +663,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, #else struct drm_crtc_state *crtc_state) { + struct drm_atomic_state *state = crtc_state->state; #endif struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; @@ -707,7 +708,6 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } -#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) { struct drm_plane_state *primary_state; @@ -716,7 +716,6 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, if (IS_ERR(primary_state)) return PTR_ERR(primary_state); } -#endif /* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) From fc78214aa179c4fa515c5ea7e130363489f3f084 Mon Sep 17 00:00:00 2001 From: Matt Ezell Date: Thu, 31 Jul 2025 17:44:39 -0400 Subject: [PATCH 1577/2070] drm/amdgpu: Propagate amd_acquire errors in rdma_get_pages amd_acquire returns 1 on success and 0 on failure. rdma_get_pages needs to return non-zero if amd_acquire fails. Originally found by Chuck Fossen from HPE Signed-off-by: Matt Ezell Signed-off-by: Kent Russell Reviewed-by: Amber Lin --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index ed93247d83caa..09461f004377e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -557,6 +557,7 @@ static int rdma_get_pages(uint64_t address, uint64_t length, struct pid *pid, kfd_unref_process(p); if (r == 0) { pr_debug("acquire failed: %d\n", r); + r = -EINVAL; goto err_acquire; } From 3713bb92714d043a424462dda1299e4d3d5f50d1 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 21 Aug 2025 11:13:31 +0800 Subject: [PATCH 1578/2070] drm/amdkcl: test whether MIN() exist it's caused by 3a02acd7ed124c9 "drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%" Signed-off-by: Yang Su --- include/kcl/kcl_minmax.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_minmax.h b/include/kcl/kcl_minmax.h index 618e166564d98..208a5a940b92e 100644 --- a/include/kcl/kcl_minmax.h +++ b/include/kcl/kcl_minmax.h @@ -9,4 +9,12 @@ min((x) + 0u + 0ul + 0ull, (y) + 0u + 0ul + 0ull) #endif +#ifndef MIN +#define __cmp_op_min < + +#define __cmp(op, x, y) ((x) __cmp_op_##op (y) ? (x) : (y)) + +#define MIN(a, b) __cmp(min, a, b) +#endif + #endif /* _KCL_MINMAX_H */ From c93202c330e3a380a78e52f1ea744cfd82dfce56 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 20 Aug 2025 17:36:45 +0800 Subject: [PATCH 1579/2070] drm/amdkcl: wrap code under HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG in the old kernel version, struct drm_vblank_crtc doesn't have member "config". so bypass in the code. it's cuased by 142fc1c2ce2684 "drm/amd/display: Fix Xorg desktop unresponsive on Replay panel" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 576320a5f743f..fdbdce6063f59 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -307,6 +307,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); if (enable) { +#ifdef HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; @@ -325,6 +326,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); +#endif } if (dc_supports_vrr(dm->dc->ctx->dce_version)) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f4981cadbaf12..8e7127b9d68aa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -691,7 +691,10 @@ #define HAVE_DRM_TASK_BARRIER_H 1 /* drm_vblank_crtc_config is available */ -/* #undef HAVE_DRM_VBLANK_CRTC_CONFIG */ +#define HAVE_DRM_VBLANK_CRTC_CONFIG 1 + +/* struct vblank->config is available */ +#define HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG 1 /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 new file mode 100644 index 0000000000000..f7f9216f54f2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.10-rc1-595-g0d5040e406d2 +dnl # drm/vblank: add dynamic per-crtc vblank configuration support +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc *vblank = NULL; + vblank->config = NULL; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG, 1, + [struct vblank->config is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2c0626afa6db7..6f4c20c897082 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -264,6 +264,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT + AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From a90009d461bcd6d2cde7c991dd0a0ca13498f538 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 21 Aug 2025 13:48:49 +0800 Subject: [PATCH 1580/2070] drm/amdkcl: fake the drm/drm_privacy_screen_consumer.h header it's caused by b5a33ca93 "drm/amd/display: Attach privacy screen to DRM connector" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_privacy_screen_consumer.h | 9 +++++++++ 3 files changed, 18 insertions(+) create mode 100644 include/kcl/header/drm/drm_privacy_screen_consumer.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8e7127b9d68aa..38b726aa32b7a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -367,6 +367,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index bca9e1778fa23..3f4ae2301335a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -44,6 +44,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + dnl # + dnl # v5.15-rc1-290-ga1a98689301b + dnl # drm: Add privacy-screen class (v4) + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_privacy_screen_consumer.h]) + dnl # dnl # v5.16-rc5-872-g5b529e8d9c38 dnl # drm/dp: Move public DisplayPort headers into dp/ diff --git a/include/kcl/header/drm/drm_privacy_screen_consumer.h b/include/kcl/header/drm/drm_privacy_screen_consumer.h new file mode 100644 index 0000000000000..aa456f80dd3c6 --- /dev/null +++ b/include/kcl/header/drm/drm_privacy_screen_consumer.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PRIVACY_SCREEN_CONSUMER_H_H_ +#define _KCL_HEADER_DRM_PRIVACY_SCREEN_CONSUMER_H_H_ + +#ifdef HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H +#include_next +#endif + +#endif From d933a6d0776b7f4cfd9680b5b1c0c20542bfd356 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 21 Aug 2025 15:54:41 +0800 Subject: [PATCH 1581/2070] drm/amdkcl: wrap code under HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN old kernel doesn't enable CONFIG_DRM_PRIVACY_SCREEN, so bypass this feature by HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN it's caused by b5a33ca934120fdc "drm/amd/display: Attach privacy screen to DRM connector" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++---- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d6f033b2898d5..d06c9e0b6d9f8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8459,7 +8459,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, if (!crtc) return 0; - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8467,7 +8467,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, new_crtc_state->mode_changed = true; } - +#endif if (new_con_state->colorspace != old_con_state->colorspace) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -9297,7 +9297,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_content_protection_property(&aconnector->base); #endif } - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN if (connector_type == DRM_MODE_CONNECTOR_eDP) { struct drm_privacy_screen *privacy_screen; @@ -9309,6 +9309,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); } } +#endif } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -11261,8 +11262,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) &stream_update); mutex_unlock(&dm->dc_lock); kfree(dummy_updates); - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN drm_connector_update_privacy_screen(new_con_state); +#endif } /** diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 38b726aa32b7a..642e0e40a0e4f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -248,6 +248,9 @@ /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 +/* drm_connector_update_privacy_screen() is available */ +#define HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN 1 + /* drm_connector_attach_colorspace_property() is available */ #define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 new file mode 100644 index 0000000000000..8636cef864a78 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc1-293-g334f74ee85dc +dnl # drm/connector: Add a drm_connector privacy-screen helper functions (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_connector_state *drm_con_state = NULL; + drm_connector_update_privacy_screen(drm_con_state); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN, 1, + [drm_connector_update_privacy_screen() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f4c20c897082..e5ba9a360f9b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -265,6 +265,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_INIT64 AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG + AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 60c8c4e7e84792606c6e6aaf8508377c45eeac3d Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 1 Sep 2025 12:18:56 +0800 Subject: [PATCH 1582/2070] drm/amdkcl: fix conflict of the __cmp macro function The __cmp function varies significantly across different kernel versions, so rename to __kcl_cmp to avoid conflicts. Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- include/kcl/kcl_minmax.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/kcl/kcl_minmax.h b/include/kcl/kcl_minmax.h index 208a5a940b92e..21b3450c40efb 100644 --- a/include/kcl/kcl_minmax.h +++ b/include/kcl/kcl_minmax.h @@ -10,11 +10,11 @@ #endif #ifndef MIN -#define __cmp_op_min < +#define __kcl_cmp_op_min < -#define __cmp(op, x, y) ((x) __cmp_op_##op (y) ? (x) : (y)) +#define __kcl_cmp(op, x, y) ((x) __kcl_cmp_op_##op (y) ? (x) : (y)) -#define MIN(a, b) __cmp(min, a, b) +#define MIN(a, b) __kcl_cmp(min, a, b) #endif #endif /* _KCL_MINMAX_H */ From 661955dcd7309fd5828baff278e06f2028414938 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 1 Sep 2025 12:22:43 +0800 Subject: [PATCH 1583/2070] drm/amdkcl: test whether no_free_ptr exist it's caused by 6614cce880 "drm/amd/pm: Make use of __free for cleanup" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- include/kcl/kcl_cleanup.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_cleanup.h b/include/kcl/kcl_cleanup.h index 73ad9f618de67..2f62410fe1932 100644 --- a/include/kcl/kcl_cleanup.h +++ b/include/kcl/kcl_cleanup.h @@ -35,6 +35,23 @@ static inline _type class_##_name##_constructor(_init_args) \ for (CLASS(_name, scope)(args), \ *done = NULL; __guard_ptr(_name)(&scope) && !done; done = (void *)1) +#ifndef no_free_ptr +#define __get_and_null(p, nullvalue) \ + ({ \ + __auto_type __ptr = &(p); \ + __auto_type __val = *__ptr; \ + *__ptr = nullvalue; \ + __val; \ + }) + +static inline __must_check +const volatile void * __must_check_fn(const volatile void *val) +{ return val; } + +#define no_free_ptr(p) \ + ((typeof(p)) __must_check_fn((__force const volatile void *)__get_and_null(p, NULL))) +#endif + #endif #endif /* KCL_CLEANUP_H_ */ From 1d279c63b1d70260e5f3963dadb7f542973bf683 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 1 Sep 2025 15:07:59 +0800 Subject: [PATCH 1584/2070] drm/amdkcl: wrap code under HAVE_DRM_DP_AUX_DRM_DEV it's caused by 540bb15535b834 "drm/amd/display: Skip Check Runtime Link Setting for Specific Branch Device" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 1ef14ac1240b8..4ae6acfe18cdc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -392,8 +392,13 @@ static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector (branch_desc.ident.oui[1] << 8) + (branch_desc.ident.oui[2]); +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n", aconnector->branch_ieee_oui, connector->name); +#else + DRM_DEBUG_KMS("MST branch oui 0x%x detected at %s\n", + aconnector->branch_ieee_oui, connector->name); +#endif return true; } @@ -2094,9 +2099,13 @@ static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_lin dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET]; link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET]; lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n", dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); +#else + DRM_DEBUG_KMS("MST_DSC downlink setting: %d, 0x%x x %d\n", + dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); +#endif switch (dp_link_encoding) { case DP_8b_10b_ENCODING: From 7074743e2b434b440d0650d0c0f1e8b4087ee438 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Sep 2025 14:05:50 +0800 Subject: [PATCH 1585/2070] drm/amdkcl: Fix HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG not generated correctly Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 index f7f9216f54f2e..c034421d9cdd7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 @@ -8,7 +8,8 @@ AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG], [ #include ],[ struct drm_vblank_crtc *vblank = NULL; - vblank->config = NULL; + struct drm_vblank_crtc_config config; + vblank->config = config; ],[ AC_DEFINE(HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG, 1, [struct vblank->config is available]) From d8c56171950c1a396118672ca8adf33d2e21b23f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Sep 2025 13:39:23 +0800 Subject: [PATCH 1586/2070] drm/amdkcl: Test whether drm_dp_aux->dpcd_probe_disabled is available It's caused by the commit:aef403b "drm/amd/display: Disable DPCD Probe Quirk" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4ae6acfe18cdc..449715733903b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1053,7 +1053,9 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, drm_dp_aux_init(&aconnector->dm_dp_aux.aux); drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, &aconnector->base); +#ifdef HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false); +#endif if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) return; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 642e0e40a0e4f..167095e1da7f1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -349,6 +349,9 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ #define HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES 1 +/* drm_dp_aux->dpcd_probe_disabled is available */ +#define HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED 1 + /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 new file mode 100644 index 0000000000000..ab697ac5c5a3b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc1-124-gb87ed522b364 +dnl # drm/dp: Add an EDID quirk for the DPCD register access probe +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + aux->dpcd_probe_disabled = false; + ], [ + AC_DEFINE(HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED, 1, + [drm_dp_aux->dpcd_probe_disabled is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e5ba9a360f9b0..5a5a3984be73e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -266,6 +266,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN + AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 51ef3aa56cba617bbde5c7a7a961724eae2d923a Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 9 Sep 2025 13:45:27 +0800 Subject: [PATCH 1587/2070] drm/amdkcl: modify the makefile for dc/soc_and_ip_translator It's cauesd by the commit: f833377 "drm/amd/display: Add Component To Handle Bounding Box Values and IP Caps" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../display/dc/soc_and_ip_translator/Makefile | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile index bc93356a0b5b9..897a5e3f14663 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile @@ -4,8 +4,46 @@ # Makefile for bounding box component. # Floating point required due to nature of bounding box values +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT soc_and_ip_translator_ccflags := $(CC_FLAGS_FPU) soc_and_ip_translator_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +soc_and_ip_translator_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +soc_and_ip_translator_ccflags := $(soc_and_ip_translator_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +soc_and_ip_translator_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +soc_and_ip_translator_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +soc_and_ip_translator_ccflags := -mfpu=64 +soc_and_ip_translator_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +soc_and_ip_translator_ccflags += -mpreferred-stack-boundary=4 +else +soc_and_ip_translator_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) From 6fe87d292d660c6954f4664d9b1d58c2db2c4da4 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 4 Sep 2025 11:10:13 +0800 Subject: [PATCH 1588/2070] drm/amdkcl: test if ITER_SOURCE/ITER_DEST exist it's caused by 7f12d388fc290 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_uio.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_uio.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 20925e7c2c3e3..55ff334ebbfaf 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -147,5 +147,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_uio.h b/include/kcl/kcl_uio.h new file mode 100644 index 0000000000000..79c013014604f --- /dev/null +++ b/include/kcl/kcl_uio.h @@ -0,0 +1,11 @@ +#ifndef _KCL_UIO_H_ +#define _KCL_UIO_H_ + +#include + +#ifndef ITER_SOURCE +#define ITER_SOURCE 1 // == WRITE +#define ITER_DEST 0 // == READ +#endif + +#endif From 781b90bd727794fbb37cf50acc07cffc263cda05 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 10 Sep 2025 14:14:44 +0800 Subject: [PATCH 1589/2070] drm/amdkcl: test whether vmemdup_array_user() exist It's caused by the commit: 93b0be48 "drm/amdgpu: Use vmemdup_array_user in amdgpu_bo_create_list_entry_array" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- .../gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 | 16 +++++++ include/kcl/kcl_string.h | 47 +++++++++++++++++++ 4 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 167095e1da7f1..08cc6ff987faf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1192,6 +1192,9 @@ /* vma_lookup() is available */ #define HAVE_VMA_LOOKUP 1 +/* vmemdup_array_user() is available */ +#define HAVE_VMEMDUP_ARRAY_USER 1 + /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5a5a3984be73e..a91de9bc5a8e2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -267,7 +267,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED - + AC_AMDGPU_VMEMDUP_ARRAY_USER + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 b/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 new file mode 100644 index 0000000000000..90161018d5bac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.6-rc5-1-g313ebe47d755 +dnl # kernel: string.h: add array-wrappers for (v)memdup_user() +dnl # +AC_DEFUN([AC_AMDGPU_VMEMDUP_ARRAY_USER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vmemdup_array_user(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_VMEMDUP_ARRAY_USER, 1, + [vmemdup_array_user() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string.h b/include/kcl/kcl_string.h index cb4416f1f99a9..7ba4ffbe1be37 100644 --- a/include/kcl/kcl_string.h +++ b/include/kcl/kcl_string.h @@ -24,4 +24,51 @@ extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __RENAME(strscpy); CONCATENATE(kcl_strscpy, COUNT_ARGS(__VA_ARGS__))(dst, src, __VA_ARGS__) #endif +#ifndef HAVE_VMEMDUP_ARRAY_USER +#ifndef __realloc_size +#define __realloc_size(x, y) +#endif +/** + * memdup_array_user - duplicate array from user space + * @src: source address in user space + * @n: number of array members to copy + * @size: size of one array member + * + * Return: an ERR_PTR() on failure. Result is physically + * contiguous, to be freed by kfree(). + */ +static inline __realloc_size(2, 3) +void *kcl_memdup_array_user(const void __user *src, size_t n, size_t size) +{ + size_t nbytes; + + if (check_mul_overflow(n, size, &nbytes)) + return ERR_PTR(-EOVERFLOW); + + return memdup_user(src, nbytes); +} +#define memdup_array_user kcl_memdup_array_user + +/** + * vmemdup_array_user - duplicate array from user space + * @src: source address in user space + * @n: number of array members to copy + * @size: size of one array member + * + * Return: an ERR_PTR() on failure. Result may be not + * physically contiguous. Use kvfree() to free. + */ +static inline __realloc_size(2, 3) +void *kcl_vmemdup_array_user(const void __user *src, size_t n, size_t size) +{ + size_t nbytes; + + if (check_mul_overflow(n, size, &nbytes)) + return ERR_PTR(-EOVERFLOW); + + return vmemdup_user(src, nbytes); +} +#define vmemdup_array_user kcl_vmemdup_array_user +#endif /* HAVE_VMEMDUP_ARRAY_USER */ + #endif /* _KCL_KCL_STRING_H */ From c7c8bd0f94249b1fc570b77a88ef356448472ced Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 11 Sep 2025 15:38:36 +0800 Subject: [PATCH 1590/2070] drm/amdkcl: Add CONFIG_DRM_SUBALLOC_HELPER check in drm_suballoc.m4 Introduces a preprocessor check for the CONFIG_DRM_SUBALLOC_HELPER configuration option in the drm_suballoc.m4 file. It will fix driver build failure while the kernel config has no drm_suballoc built. Reviewed-by: Bob Zhou Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 index bcb026ad2c36d..46363385a7097 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -7,7 +7,11 @@ AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ + #ifdef CONFIG_DRM_SUBALLOC_HELPER drm_suballoc_manager_init(NULL, 0, 0); + #else + #error CONFIG_DRM_SUBALLOC_HELPER is not enabled + #endif ], [ AC_DEFINE(HAVE_DRM_SUBALLOC_MANAGER_INIT, 1, [Has function drm_suballoc_manager_init()]) From 0da2dda72ceaf2b98102ef9b39fdc4071cf1910a Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 10:08:33 +0800 Subject: [PATCH 1591/2070] drm/amdkcl: test whether bitmap_read() available It's caused by the commit: a80bb1c0 "drm/amdgpu: Add generic capability class" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_bitmap.h | 82 ++++++++++++++++++++++ 5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 55ff334ebbfaf..88f3fc8b23c2e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include #include #include @@ -79,7 +80,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 08cc6ff987faf..331fc29ceb98f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -68,6 +68,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* bitmap_read() is available */ +#define HAVE_BITMAP_READ 1 + /* bitmap_to_arr32() is available */ #define HAVE_BITMAP_TO_ARR32 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 new file mode 100644 index 0000000000000..233756077854c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc1-324-g63c15822b8dd +dnl # lib/bitmap: add bitmap_{read,write}() +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_read(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_READ, 1, + [bitmap_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a91de9bc5a8e2..9827acd3ca959 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -268,6 +268,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_AMDGPU_VMEMDUP_ARRAY_USER + AC_AMDGPU_BITMAP_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index f2c0863b7b7d8..1d23536e1cd17 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -22,6 +22,9 @@ #ifndef KCL_BITMAP_H #define KCL_BITMAP_H +#ifndef __ASSEMBLY__ +#include + #ifndef HAVE_BITMAP_FUNCS /* Copied from include/linux/bitmap.h*/ @@ -51,4 +54,83 @@ void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, #endif #endif /* HAVE_BITMAP_TO_ARR32 */ +#ifndef HAVE_BITMAP_READ + +/** + * bitmap_read - read a value of n-bits from the memory region + * @map: address to the bitmap memory region + * @start: bit offset of the n-bit value + * @nbits: size of value in bits, nonzero, up to BITS_PER_LONG + * + * Returns: value of @nbits bits located at the @start bit offset within the + * @map memory region. For @nbits = 0 and @nbits > BITS_PER_LONG the return + * value is undefined. + */ +static inline unsigned long kcl_bitmap_read(const unsigned long *map, + unsigned long start, + unsigned long nbits) +{ + size_t index = BIT_WORD(start); + unsigned long offset = start % BITS_PER_LONG; + unsigned long space = BITS_PER_LONG - offset; + unsigned long value_low, value_high; + + if (unlikely(!nbits || nbits > BITS_PER_LONG)) + return 0; + + if (space >= nbits) + return (map[index] >> offset) & BITMAP_LAST_WORD_MASK(nbits); + + value_low = map[index] & BITMAP_FIRST_WORD_MASK(start); + value_high = map[index + 1] & BITMAP_LAST_WORD_MASK(start + nbits); + return (value_low >> offset) | (value_high << space); +} +#define bitmap_read kcl_bitmap_read + +/** + * bitmap_write - write n-bit value within a memory region + * @map: address to the bitmap memory region + * @value: value to write, clamped to nbits + * @start: bit offset of the n-bit value + * @nbits: size of value in bits, nonzero, up to BITS_PER_LONG. + * + * bitmap_write() behaves as-if implemented as @nbits calls of __assign_bit(), + * i.e. bits beyond @nbits are ignored: + * + * for (bit = 0; bit < nbits; bit++) + * __assign_bit(start + bit, bitmap, val & BIT(bit)); + * + * For @nbits == 0 and @nbits > BITS_PER_LONG no writes are performed. + */ +static inline void kcl_bitmap_write(unsigned long *map, unsigned long value, + unsigned long start, unsigned long nbits) +{ + size_t index; + unsigned long offset; + unsigned long space; + unsigned long mask; + bool fit; + + if (unlikely(!nbits || nbits > BITS_PER_LONG)) + return; + + mask = BITMAP_LAST_WORD_MASK(nbits); + value &= mask; + offset = start % BITS_PER_LONG; + space = BITS_PER_LONG - offset; + fit = space >= nbits; + index = BIT_WORD(start); + + map[index] &= (fit ? (~(mask << offset)) : ~BITMAP_FIRST_WORD_MASK(start)); + map[index] |= value << offset; + if (fit) + return; + + map[index + 1] &= BITMAP_FIRST_WORD_MASK(start + nbits); + map[index + 1] |= (value >> space); +} +#define bitmap_write kcl_bitmap_write +#endif + +#endif /* __ASSEMBLY__ */ #endif /* KCL_BITMAP_H */ From c13b4941e39239ab83eef15f8b7e7918c6b7d953 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 16 Sep 2025 14:47:27 +0800 Subject: [PATCH 1592/2070] drm/amdkcl: remove unnecessary vm_insert_mixed & vmf_insert_mixed_prot() check Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 14 ------ drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 14 ------ .../drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 | 20 --------- include/kcl/kcl_memory.h | 45 ------------------- 6 files changed, 100 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index 606ae29de54ae..b835dd0f0e28b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -31,20 +31,6 @@ #include #include -/* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ -#ifndef HAVE_VMF_INSERT_MIXED_PROT -vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot) -{ - struct vm_area_struct cvma = *vma; - - cvma.vm_page_prot = pgprot; - - return vmf_insert_mixed(&cvma, addr, pfn); -} -EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); -#endif - #ifndef HAVE_VMF_INSERT_PFN_PROT #ifndef HAVE_VM_INSERT_PFN_PROT int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 331fc29ceb98f..80c2403b4d16f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -999,9 +999,6 @@ /* pfn_t is defined */ #define HAVE_PFN_T 1 -/* vm_insert_mixed() wants pfn_t arg */ -/* #undef HAVE_PFN_T_VM_INSERT_MIXED */ - /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 @@ -1201,9 +1198,6 @@ /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 -/* vmf_insert_mixed_prot() is available */ -#define HAVE_VMF_INSERT_MIXED_PROT 1 - /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9827acd3ca959..f024053503eee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,7 +28,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FSLEEP AC_AMDGPU_USLEEP_RANGE_STATE AC_AMDGPU_VMF_INSERT - AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index 89789fd059839..eb41c2919fae8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -25,20 +25,6 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ ], [ AC_DEFINE(HAVE_VMF_INSERT, 1, [vmf_insert_*() are available]) - ], [ - dnl # - dnl # commit v4.4-6475-g01c8f1c44b83 - dnl # mm, dax, gpu: convert vm_insert_mixed to pfn_t - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pfn_t pfn = {}; - vm_insert_mixed(NULL, 0, pfn); - ], [vm_insert_mixed], [mm/memory.c], [ - AC_DEFINE(HAVE_PFN_T_VM_INSERT_MIXED, 1, - [vm_insert_mixed() wants pfn_t arg]) - ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 deleted file mode 100644 index 53da9747196ea..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # 5379e4dd3220 mm, drm/ttm: Fix vm page protection handling -dnl # 574c5b3d0e4c mm: Add a vmf_insert_mixed_prot() function -dnl # -AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_PROT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - #include - ],[ - pfn_t pfn; - pgprot_t prot; - vmf_insert_mixed_prot(NULL, 0, pfn, prot); - ],[vmf_insert_mixed_prot],[mm/memory.c],[ - AC_DEFINE(HAVE_VMF_INSERT_MIXED_PROT, - 1, - [vmf_insert_mixed_prot() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index aeebb157b0d57..571c570dd2c42 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -2,51 +2,6 @@ #ifndef _KCL_KCL_MEMORY_H #define _KCL_KCL_MEMORY_H -#ifndef HAVE_VMF_INSERT -static inline vm_fault_t vmf_insert_mixed(struct vm_area_struct *vma, - unsigned long addr, - pfn_t pfn) -{ - int err; -#if !defined(HAVE_PFN_T_VM_INSERT_MIXED) - err = vm_insert_mixed(vma, addr, pfn_t_to_pfn(pfn)); -#else - err = vm_insert_mixed(vma, addr, pfn); -#endif - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} - -static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn) -{ - int err = vm_insert_pfn(vma, addr, pfn); - - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} - -#endif /* HAVE_VMF_INSERT */ - -#ifndef HAVE_VMF_INSERT_MIXED_PROT -vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot); -static inline -vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot) -{ - return _kcl_vmf_insert_mixed_prot(vma, addr, pfn, pgprot); -} -#endif /* HAVE_VMF_INSERT_MIXED_PROT */ - #ifndef HAVE_VMF_INSERT_PFN_PROT vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, pgprot_t pgprot); From f21870039597d7294d1fcf266dd19ea848b783f2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 16 Sep 2025 14:51:23 +0800 Subject: [PATCH 1593/2070] drm/amdkcl: test whether vmf_insert_mixed_mkwrite() has long pfn arg Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm_types.h | 3 +-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 80c2403b4d16f..7521534c4f822 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1198,6 +1198,9 @@ /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 +/* vmf_insert_mixed_mkwrite() has long pfn arg */ +/* #undef HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN */ + /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f024053503eee..cac8f0703e004 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -268,6 +268,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ + AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index eb41c2919fae8..cd07c76959799 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -29,3 +29,20 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ ]) ]) ]) + +dnl # +dnl # commit v6.16-rc5-105-g21aa65bf82a7 +dnl # mm: remove callers of pfn_t functionality +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + vmf_insert_mixed_mkwrite(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN, 1, + [vmf_insert_mixed_mkwrite() has long pfn arg]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h index 6cf223e559d02..a180469fd2508 100644 --- a/include/kcl/kcl_mm_types.h +++ b/include/kcl/kcl_mm_types.h @@ -31,9 +31,8 @@ static inline unsigned long pfn_t_to_pfn(pfn_t pfn) } #endif -#ifndef HAVE_VMF_INSERT +#if !defined(HAVE_VMF_INSERT) && !defined(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN) typedef int vm_fault_t; #endif #endif /* AMDKCL_MM_TYPES_H */ - From 74b5fad769a2c882d1eae8fed422104a51bccc49 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 17:09:43 +0800 Subject: [PATCH 1594/2070] drm/amdkcl: test drm_helper_mode_fill_fb_struct() wants 4 arguments Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index c37dfaee50012..db28bd110e3db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1206,7 +1206,12 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, { int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS + drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); +#else drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1233,7 +1238,14 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); +#else + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif + + #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7521534c4f822..21fe67c358438 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -627,11 +627,8 @@ /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 -/* drm_helper_mode_fill_fb_struct() wants dev arg */ -#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV 1 - -/* drm_is_current_master() is available */ -#define HAVE_DRM_IS_CURRENT_MASTER 1 +/* drm_helper_mode_fill_fb_struct() wants 4 arguments */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS 1 /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 new file mode 100644 index 0000000000000..e1e4dc10eb1ed --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc2-1239-ga34cc7bf1034 +dnl # drm: Allow the caller to pass in the format info to drm_helper_mode_fill_fb_struct() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + drm_helper_mode_fill_fb_struct(NULL, NULL, NULL, NULL); + ],[drm_helper_mode_fill_fb_struct], [drivers/gpu/drm/drm_modeset_helper.c],[ + AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS, 1, + [drm_helper_mode_fill_fb_struct() wants 4 arguments]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cac8f0703e004..9fa60b23c90af 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -269,6 +269,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN + AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 24ce4218221411e476891f6df0f9dcfd122851ec Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 17:32:56 +0800 Subject: [PATCH 1595/2070] drm/amdkcl: test whether fb_create has const struct drm_format_info * parameter Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 +-- .../amd/dkms/m4/drm_fb_create_format_info.m4 | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index db28bd110e3db..f847a0fda8634 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1231,7 +1231,9 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { @@ -1354,7 +1356,9 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd) { struct amdgpu_framebuffer *amdgpu_fb; @@ -1392,7 +1396,11 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, } ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO info, mode_cmd, obj); +#else + mode_cmd, obj); +#endif if (ret) { kfree(amdgpu_fb); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 85a7ebbc469ef..dd4c421510685 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -44,7 +44,9 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd); const struct drm_format_info * amdgpu_lookup_format_info(u32 format, uint64_t modifier); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 21fe67c358438..51702408f8f7b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -561,8 +561,8 @@ /* drm_edid_valid() is available */ #define HAVE_DRM_EDID_VALID 1 -/* drm_exec() has 3 arguments */ -#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 +/* fb_create has const struct drm_format_info * parameter */ +#define HAVE_DRM_FB_CREATE_FORMAT_INFO 1 /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 new file mode 100644 index 0000000000000..25f464b720203 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit v6.16-rc2-1238-g81112eaac559 +dnl # drm: Pass the format info to .fb_create() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_framebuffer *test_fb_create_new( + struct drm_device *dev, + struct drm_file *file_priv, + const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .fb_create = test_fb_create_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_FB_CREATE_FORMAT_INFO, 1, + [fb_create has const struct drm_format_info * parameter]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9fa60b23c90af..c42eab99e63ac 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -270,6 +270,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BITMAP_READ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 7e6b3fecd9342b6b82fcb55f3b8539c55527a288 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 18:43:18 +0800 Subject: [PATCH 1596/2070] drm/amdkcl: get_format_info uses pixel_format and modifier parameters Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 7 ++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ .../dkms/m4/drm_get_format_info_signature.m4 | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 42 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8799dd6725f9e..3fa963f7f0ae5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -96,10 +96,17 @@ enum dm_micro_swizzle { }; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { return amdgpu_lookup_format_info(pixel_format, modifier); } +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); +} +#endif #endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index ea2619b507db7..3b583bbca535a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -58,7 +58,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, unsigned long possible_crtcs, const struct dc_plane_cap *plane_cap); +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier); +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 51702408f8f7b..01025e4f6842f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -615,6 +615,12 @@ /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 +/* get_format_info uses pixel_format and modifier parameters */ +#define HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS 1 + +/* drm_get_panel_min_brightness_quirk() is available */ +#define HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK 1 + /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 new file mode 100644 index 0000000000000..71d0f4e7eb9d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 @@ -0,0 +1,24 @@ +dnl # +dnl # v6.16-rc2-1235-g0389e4256eb2 +dnl # drm: Pass pixel_format+modifier to .get_format_info() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + const struct drm_format_info *test_get_format_info_new( + u32 pixel_format, u64 modifier) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .get_format_info = test_get_format_info_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS, 1, + [get_format_info uses pixel_format and modifier parameters]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c42eab99e63ac..719c373a73ce1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -271,6 +271,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO + AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From be7464219a85693bb4341b8d9fe90ad81a1f8673 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 15 Sep 2025 15:59:23 +0800 Subject: [PATCH 1597/2070] drm/amdkcl: test vfs_iocb_iter_read() is available It's caused by the commit: b70e506 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +- .../gpu/drm/amd/amdkcl/kcl_fs_read_write.c | 98 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_security.c | 24 +++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 | 16 +++ include/kcl/kcl_fs.h | 9 ++ 8 files changed, 155 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_security.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a1f29af59da14..8914c816115e3 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,13 +5,13 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_io.o kcl_seq_file.o \ + kcl_io.o kcl_seq_file.o kcl_security.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o \ + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c new file mode 100644 index 0000000000000..d021e8955bc40 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c @@ -0,0 +1,98 @@ +/* + * linux/fs/read_write.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include +#include +#include +#include + +#ifndef HAVE_VFS_IOCB_ITER_READ +int kcl_security_file_permission(struct file *file, int mask); + +static inline bool kcl_unsigned_offsets(struct file *file) +{ + return file->f_mode & FMODE_UNSIGNED_OFFSET; +} + +int kcl_rw_verify_area(int read_write, struct file *file, const loff_t *ppos, size_t count) +{ + if (unlikely((ssize_t) count < 0)) + return -EINVAL; + + if (ppos) { + loff_t pos = *ppos; + + if (unlikely(pos < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + if (count >= -pos) /* both values are in 0..LLONG_MAX */ + return -EOVERFLOW; + } else if (unlikely((loff_t) (pos + count) < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + } + } + + return kcl_security_file_permission(file, + read_write == READ ? MAY_READ : MAY_WRITE); +} + +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->read_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_READ)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_READ)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + goto out; + ret = kcl_rw_verify_area(READ, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_read_iter(file, iocb, iter); +out: + if (ret >= 0) + fsnotify_access(file); + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_read); + +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->write_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_WRITE)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_WRITE)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + return 0; + ret = kcl_rw_verify_area(WRITE, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_write_iter(file, iocb, iter); + if (ret > 0) + fsnotify_modify(file); + + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_write); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_security.c b/drivers/gpu/drm/amd/amdkcl/kcl_security.c new file mode 100644 index 0000000000000..6ba63cf49ef7a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_security.c @@ -0,0 +1,24 @@ +#include +#ifdef CONFIG_SECURITY +#include +#endif +#include "kcl_common.h" + +#ifndef HAVE_VFS_IOCB_ITER_READ +struct file; // Forward declaration + +int (*kcl_security_file_permission)(struct file *file, int mask); + +int _kcl_security_file_permission(struct file *file, int mask) +{ + pr_warn_once("This kernel version not support API: security_file_permission !\n"); + return 0; +} +#endif + +void amdkcl_security_init(void) +{ +#ifndef HAVE_VFS_IOCB_ITER_READ + kcl_security_file_permission = amdkcl_fp_setup("security_file_permission", _kcl_security_file_permission); +#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 9b461ef77d2a3..ad8aad6122de6 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -9,6 +9,7 @@ extern void amdkcl_suspend_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); +extern void amdkcl_security_init(void); int __init amdkcl_init(void) { @@ -19,6 +20,7 @@ int __init amdkcl_init(void) amdkcl_numa_init(); amdkcl_workqueue_init(); amdkcl_prime_init(); + amdkcl_security_init(); return 0; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 01025e4f6842f..76471b3635592 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1183,6 +1183,9 @@ /* usleep_range_stat() is available */ #define HAVE_USLEEP_RANGE_STATE 1 +/* vfs_iocb_iter_read() is available */ +#define HAVE_VFS_IOCB_ITER_READ 1 + /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 719c373a73ce1..84c227a993cc4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -272,6 +272,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS + AC_AMDGPU_VFS_IOCB_ITER_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 new file mode 100644 index 0000000000000..5c70d0482dc09 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit: v5.5-rc7-11-g5dcdc43e24a1 +dnl # vfs: add vfs_iocb_iter_[read|write] helper functions +dnl # +AC_DEFUN([AC_AMDGPU_VFS_IOCB_ITER_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + vfs_iocb_iter_read(NULL, NULL, NULL); + ],[vfs_iocb_iter_read],[fs/read_write.c], [ + AC_DEFINE(HAVE_VFS_IOCB_ITER_READ, 1, + [vfs_iocb_iter_read() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index e05a4edacabda..14f4d2330a8b2 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -26,4 +26,13 @@ static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, #endif #endif +#ifndef HAVE_VFS_IOCB_ITER_READ +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter); +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter); +#define vfs_iocb_iter_read kcl_vfs_iocb_iter_read +#define vfs_iocb_iter_write kcl_vfs_iocb_iter_write +#endif + #endif From c0b7bf6156a6c7ab53168180206b473678d823ff Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 17 Sep 2025 15:49:37 +0800 Subject: [PATCH 1598/2070] drm/amdkcl: test list_is_head() is available It's caused by the commit: feb3191 "drm/amdgpu: fix userq VM validation v4" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 | 16 ++++++++++++++++ include/kcl/kcl_list.h | 7 +++++++ 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 76471b3635592..9854755b82efa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -930,6 +930,9 @@ /* list_is_first() is available */ #define HAVE_LIST_IS_FIRST 1 +/* list_is_head() is available */ +#define HAVE_LIST_IS_HEAD 1 + /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 84c227a993cc4..88c1060b47d27 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -273,6 +273,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_AMDGPU_VFS_IOCB_ITER_READ + AC_AMDGPU_LIST_IS_HEAD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 b/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 new file mode 100644 index 0000000000000..81db7cc617a1d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.16-23-g0425473037db +dnl # list: introduce list_is_head() helper and re-use it in list.h +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_HEAD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_head(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_HEAD, 1, + [list_is_head() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_list.h b/include/kcl/kcl_list.h index 20e2bee6bef61..a4790734f86c9 100644 --- a/include/kcl/kcl_list.h +++ b/include/kcl/kcl_list.h @@ -21,4 +21,11 @@ static inline int list_is_first(const struct list_head *list, } #endif +#if !defined(HAVE_LIST_IS_HEAD) +static inline int list_is_head(const struct list_head *list, const struct list_head *head) +{ + return list == head; +} +#endif + #endif /*AMDKCL_LIST_H*/ From c99a0d8228890b3b3bf52ed20826d511cfd861d4 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 17 Sep 2025 14:05:28 +0800 Subject: [PATCH 1599/2070] drm/amdkcl: test whether devm_i2c_add_adapter() is available It's caused by the commit: 379acbb3 "drm/amd/display: Use devm_i2c_add_adapter to simplify i2c cleanup logic" Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_i2c_core_base.c | 30 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/devm_i2c_add_adapter.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_i2c.h | 4 +++ 6 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8914c816115e3..505b07b3c3820 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c b/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c new file mode 100644 index 0000000000000..5f6690633f9ef --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c @@ -0,0 +1,30 @@ +/* + * i2c-core-base.c - a device driver for the i2c bus interface + * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2013-2019 Wolfram Sang + * + * With some changes from Kyösti Mälkki and + * Frodo Looijaard + */ + +#include +#include + +#ifndef HAVE_DEVM_I2C_ADD_ADAPTER +static void kcl_devm_i2c_del_adapter(void *adapter) +{ + i2c_del_adapter(adapter); +} + +int kcl_devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter) +{ + int ret; + + ret = i2c_add_adapter(adapter); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, kcl_devm_i2c_del_adapter, adapter); +} +EXPORT_SYMBOL_GPL(kcl_devm_i2c_add_adapter); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9854755b82efa..64031287b2176 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -101,6 +101,9 @@ /* MEMORY_DEVICE_COHERENT is availablea */ #define HAVE_DEVICE_COHERENT 1 +/* devm_i2c_add_adapter() is available */ +#define HAVE_DEVM_I2C_ADD_ADAPTER 1 + /* dev_is_removable() is available */ #define HAVE_DEV_IS_REMOVABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 b/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 new file mode 100644 index 0000000000000..372c0904e731a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc6-34-g07740c92ae57 +dnl # i2c: core: add managed function for adding i2c adapters +dnl # +AC_DEFUN([AC_AMDGPU_DEVM_I2C_ADD_ADAPTER], [ +AC_KERNEL_DO_BACKGROUND([ +AC_KERNEL_TRY_COMPILE_SYMBOL([ +#include + ], [ + devm_i2c_add_adapter(NULL, NULL); + ],[devm_i2c_add_adapter], [drivers/i2c/i2c-core-base.c],[ + AC_DEFINE(HAVE_DEVM_I2C_ADD_ADAPTER, 1, + [devm_i2c_add_adapter() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 88c1060b47d27..5895ca619685b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -274,6 +274,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_LIST_IS_HEAD + AC_AMDGPU_DEVM_I2C_ADD_ADAPTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h index 2e7f36acdeadc..064fa63c6d2d6 100644 --- a/include/kcl/kcl_i2c.h +++ b/include/kcl/kcl_i2c.h @@ -29,5 +29,9 @@ i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *inf #define I2C_AQ_NO_ZERO_LEN (I2C_AQ_NO_ZERO_LEN_READ | I2C_AQ_NO_ZERO_LEN_WRITE) #endif +#ifndef HAVE_DEVM_I2C_ADD_ADAPTER +extern int kcl_devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter); +#define devm_i2c_add_adapter kcl_devm_i2c_add_adapter +#endif #endif From 58aee0d1ccad58caea49c2e5ad0fe0431f79b0e7 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 19 Sep 2025 13:29:23 +0800 Subject: [PATCH 1600/2070] drm/amdkcl: Move pgmap to amdgpu_kfd_dev structure It's caused by the commit: 610dab11 "drm/amdkfd: Move pgmap to amdgpu_kfd_dev structure" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 7b959bcdef62c..4669c90064108 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -215,7 +215,7 @@ svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) #ifdef HAVE_DEV_PAGEMAP_RANGE return (addr + adev->kfd.pgmap.range.start) >> PAGE_SHIFT; #else - return (addr + adev->kfd.dev->pgmap.res.start) >> PAGE_SHIFT; + return (addr + adev->kfd.pgmap.res.start) >> PAGE_SHIFT; #endif } @@ -249,7 +249,7 @@ svm_migrate_addr(struct amdgpu_device *adev, struct page *page) #ifdef HAVE_DEV_PAGEMAP_RANGE return (addr - adev->kfd.pgmap.range.start); #else - return (addr - adev->kfd.dev->pgmap.res.start); + return (addr - adev->kfd.pgmap.res.start); #endif } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index f79b4ebbda6a5..5d3cf3757b13e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -188,7 +188,7 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange, #ifdef HAVE_DEV_PAGEMAP_RANGE bo_adev->kfd.pgmap.range.start; #else - bo_adev->kfd.dev->pgmap.res.start; + bo_adev->kfd.pgmap.res.start; #endif addr[i] |= SVM_RANGE_VRAM_DOMAIN; pr_debug_ratelimited("vram address: 0x%llx\n", addr[i]); From 08e0165c50973447475c4891f31761e6c03b7a5b Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 23 Sep 2025 11:38:03 +0800 Subject: [PATCH 1601/2070] drm/amdkcl: wrap code under macro define HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by the commit: 88eaa016 "drm/amdgpu: use hmm_pfns instead of array of pages Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou drm/amdkcl: wrap code under macro define HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by the commit: 7fa2cac7 "drm/amdgpu/userqueue: validate userptrs for userqueues" Signed-off-by: Chengjun Yao Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 9 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 16 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 23 +++++++++++++++---- 5 files changed, 51 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index b1d358a24c03c..a46df145f2a53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1151,13 +1151,13 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, return 0; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; } -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { amdgpu_hmm_range_free(range); @@ -1197,7 +1197,9 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto release_out; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); +#endif amdgpu_bo_placement_from_domain(bo, mem->domain); ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); @@ -2927,9 +2929,10 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(mem->range); mem->range = NULL; - +#endif /* BO reservations and getting user pages (hmm_range_fault) * must happen outside the notifier lock */ @@ -2950,11 +2953,11 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, return -EAGAIN; } } - + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mem->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!mem->range)) return -ENOMEM; -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index f7fb857cc1fa7..43862a8082110 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -43,6 +43,7 @@ struct amdgpu_bo_list_entry { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; #else + struct page **user_pages; int user_invalidated; struct ttm_validate_buffer tv; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 1a951f7c7ccaa..8d5dc0df4ded5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -612,19 +612,28 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto release_object; if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); +#else + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, + &range); +#endif if (r) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(range); +#endif goto release_object; } r = amdgpu_bo_reserve(bo, true); if (r) goto user_pages_done; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); +#endif amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 1c9d811c6e65b..1c8fa910cc48d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -212,14 +212,26 @@ void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range); #else +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); +#endif +#else +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range) { return -EPERM; } +#else +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) +{ + return -EPERM; +} +#endif #endif /** @@ -243,7 +255,11 @@ static inline u64 amdgpu_gtt_node_to_byte_offset(const struct drm_mm_node *gtt_n return gtt_node->start * (u64)PAGE_SIZE; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); +#else +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); +#endif int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index c7d570f1d5c03..9e0cb31946733 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1099,21 +1099,28 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_bo_va *bo_va; + struct drm_exec exec; + int ret; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool invalidated = false, new_addition = false; struct ttm_operation_ctx ctx = { true, false }; - struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_hmm_range *range; - struct amdgpu_vm *vm = &fpriv->vm; unsigned long key, tmp_key; - struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; - struct drm_exec exec; struct xarray xa; - int ret; xa_init(&xa); retry_lock: +#else + dev_warn_once(adev->dev, "HMM is not functional; falling back to legacy path. " + "Legacy path is untested and may be unstable. " + "Please enable HMM or refer to documentation for supported kernels.\n"); + WARN_ON_ONCE(1); +#endif drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -1140,6 +1147,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (invalidated) { xa_for_each(&xa, tmp_key, range) { bo = range->bo; @@ -1157,11 +1165,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) } invalidated = false; } +#endif ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED key = 0; /* Validate User Ptr BOs */ list_for_each_entry(bo_va, &vm->done, base.vm_status) { @@ -1207,6 +1217,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) new_addition = false; goto retry_lock; } +#endif ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) @@ -1227,6 +1238,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED xa_for_each(&xa, tmp_key, range) { if (!range) continue; @@ -1234,6 +1246,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) amdgpu_hmm_range_free(range); } xa_destroy(&xa); +#endif return ret; } From 5ce6fd4b621297fe76194f6b191ac65470bbcdb4 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 24 Sep 2025 10:44:48 +0800 Subject: [PATCH 1602/2070] drm/amdkcl: revert "rework reserved VMID handling" v2 on non-upstream code It's caused by the commit: c2e6ff53 "drm/amdgpu: revert "rework reserved VMID handling" v2" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index b1105f1f15f17..97e5ed3a1212f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,12 +58,9 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { - r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); if (r) return r; - vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; - } /* init spm vmid with 0x0 */ adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0); @@ -88,10 +85,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - if (vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { - amdgpu_vmid_free_reserved(adev,AMDGPU_GFXHUB(0)); - vm->reserved_vmid[AMDGPU_GFXHUB(0)] = false; - } + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From f2d95847b8e0ad51a973e749c1d50d76f3983100 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 24 Sep 2025 13:36:49 +0800 Subject: [PATCH 1603/2070] =?UTF-8?q?drm/amdkcl=EF=BC=9AAdd=20kcl=5F=20pre?= =?UTF-8?q?fix=20to=20fake=20drm=5Fsuballoc=5F*=20functions=20for=20avoid?= =?UTF-8?q?=20symbol=20conflict?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit KCL's fake drm_suballoc_* implementations may conflict with upstream DRM symbols,causing module loading issues Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c | 72 +++++++++---------- include/kcl/kcl_drm_suballoc.h | 29 +++++--- 2 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c index 8ad6e3d9b60eb..c0dcc45d0666f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -50,8 +50,8 @@ #include #ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT -static void drm_suballoc_remove_locked(struct drm_suballoc *sa); -static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); /** * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager @@ -61,7 +61,7 @@ static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); * * Prepares the suballocation manager for suballocations. */ -void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { unsigned int i; @@ -83,7 +83,7 @@ void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) INIT_LIST_HEAD(&sa_manager->flist[i]); } -EXPORT_SYMBOL(drm_suballoc_manager_init); +EXPORT_SYMBOL(kcl_drm_suballoc_manager_init); /** * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager @@ -93,7 +93,7 @@ EXPORT_SYMBOL(drm_suballoc_manager_init); * with drm_suballoc_free() must be signaled, or we cannot clean up * the entire manager. */ -void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) { struct drm_suballoc *sa, *tmp; @@ -102,19 +102,19 @@ void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) if (!list_empty(&sa_manager->olist)) { sa_manager->hole = &sa_manager->olist; - drm_suballoc_try_free(sa_manager); + kcl_drm_suballoc_try_free(sa_manager); if (!list_empty(&sa_manager->olist)) DRM_ERROR("sa_manager is not empty, clearing anyway\n"); } list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { - drm_suballoc_remove_locked(sa); + kcl_drm_suballoc_remove_locked(sa); } sa_manager->size = 0; } -EXPORT_SYMBOL(drm_suballoc_manager_fini); +EXPORT_SYMBOL(kcl_drm_suballoc_manager_fini); -static void drm_suballoc_remove_locked(struct drm_suballoc *sa) +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa) { struct drm_suballoc_manager *sa_manager = sa->manager; @@ -127,7 +127,7 @@ static void drm_suballoc_remove_locked(struct drm_suballoc *sa) kfree(sa); } -static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) { struct drm_suballoc *sa, *tmp; @@ -139,11 +139,11 @@ static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) if (!sa->fence || !dma_fence_is_signaled(sa->fence)) return; - drm_suballoc_remove_locked(sa); + kcl_drm_suballoc_remove_locked(sa); } } -static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +static size_t kcl_drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) { struct list_head *hole = sa_manager->hole; @@ -153,7 +153,7 @@ static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) return 0; } -static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +static size_t kcl_drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) { struct list_head *hole = sa_manager->hole; @@ -162,14 +162,14 @@ static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) return sa_manager->size; } -static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, struct drm_suballoc *sa, size_t size, size_t align) { size_t soffset, eoffset, wasted; - soffset = drm_suballoc_hole_soffset(sa_manager); - eoffset = drm_suballoc_hole_eoffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); wasted = round_up(soffset, align) - soffset; if ((eoffset - soffset) >= (size + wasted)) { @@ -186,7 +186,7 @@ static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, return false; } -static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, +static bool kcl___drm_suballoc_event(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { size_t soffset, eoffset, wasted; @@ -196,8 +196,8 @@ static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, if (!list_empty(&sa_manager->flist[i])) return true; - soffset = drm_suballoc_hole_soffset(sa_manager); - eoffset = drm_suballoc_hole_eoffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); wasted = round_up(soffset, align) - soffset; return ((eoffset - soffset) >= (size + wasted)); @@ -213,18 +213,18 @@ static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, * enough free memory to satisfy the allocation directly. * false otherwise. */ -static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_event(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { bool ret; spin_lock(&sa_manager->wq.lock); - ret = __drm_suballoc_event(sa_manager, size, align); + ret = kcl___drm_suballoc_event(sa_manager, size, align); spin_unlock(&sa_manager->wq.lock); return ret; } -static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, struct dma_fence **fences, unsigned int *tries) { @@ -239,7 +239,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, return true; } - soffset = drm_suballoc_hole_soffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); /* to handle wrap around we add sa_manager->size */ best = sa_manager->size * 2; /* go over all fence list and try to find the closest sa @@ -287,7 +287,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, * We know that this one is signaled, * so it's safe to remove it. */ - drm_suballoc_remove_locked(best_bo); + kcl_drm_suballoc_remove_locked(best_bo); return true; } return false; @@ -313,7 +313,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, * Return: a new suballocated bo, or an ERR_PTR. */ struct drm_suballoc * -drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, gfp_t gfp, bool intr, size_t align) { struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; @@ -344,16 +344,16 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, tries[i] = 0; do { - drm_suballoc_try_free(sa_manager); + kcl_drm_suballoc_try_free(sa_manager); - if (drm_suballoc_try_alloc(sa_manager, sa, + if (kcl_drm_suballoc_try_alloc(sa_manager, sa, size, align)) { spin_unlock(&sa_manager->wq.lock); return sa; } /* see if we can skip over some allocations */ - } while (drm_suballoc_next_hole(sa_manager, fences, tries)); + } while (kcl_drm_suballoc_next_hole(sa_manager, fences, tries)); for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) if (fences[i]) @@ -375,11 +375,11 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, /* if we have nothing to wait for block */ r = wait_event_interruptible_locked (sa_manager->wq, - __drm_suballoc_event(sa_manager, size, align)); + kcl___drm_suballoc_event(sa_manager, size, align)); } else { spin_unlock(&sa_manager->wq.lock); wait_event(sa_manager->wq, - drm_suballoc_event(sa_manager, size, align)); + kcl_drm_suballoc_event(sa_manager, size, align)); r = 0; spin_lock(&sa_manager->wq.lock); } @@ -389,7 +389,7 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, kfree(sa); return ERR_PTR(r); } -EXPORT_SYMBOL(drm_suballoc_new); +EXPORT_SYMBOL(kcl_drm_suballoc_new); /** * drm_suballoc_free - Free a suballocation @@ -398,7 +398,7 @@ EXPORT_SYMBOL(drm_suballoc_new); * * Free the suballocation. The suballocation can be re-used after @fence signals. */ -void drm_suballoc_free(struct drm_suballoc *suballoc, +void kcl_drm_suballoc_free(struct drm_suballoc *suballoc, struct dma_fence *fence) { struct drm_suballoc_manager *sa_manager; @@ -416,15 +416,15 @@ void drm_suballoc_free(struct drm_suballoc *suballoc, idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); } else { - drm_suballoc_remove_locked(suballoc); + kcl_drm_suballoc_remove_locked(suballoc); } wake_up_all_locked(&sa_manager->wq); spin_unlock(&sa_manager->wq.lock); } -EXPORT_SYMBOL(drm_suballoc_free); +EXPORT_SYMBOL(kcl_drm_suballoc_free); #ifdef CONFIG_DEBUG_FS -void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base) { @@ -453,7 +453,7 @@ void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, } spin_unlock(&sa_manager->wq.lock); } -EXPORT_SYMBOL(drm_suballoc_dump_debug_info); +EXPORT_SYMBOL(kcl_drm_suballoc_dump_debug_info); #endif MODULE_AUTHOR("Multiple"); MODULE_DESCRIPTION("Range suballocator helper"); diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h index 46c61883e392f..7629274cc4a0a 100644 --- a/include/kcl/kcl_drm_suballoc.h +++ b/include/kcl/kcl_drm_suballoc.h @@ -52,16 +52,21 @@ struct drm_suballoc { struct dma_fence *fence; }; -void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, size_t size, size_t align); +#define drm_suballoc_manager_init kcl_drm_suballoc_manager_init -void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); +#define drm_suballoc_manager_fini kcl_drm_suballoc_manager_fini struct drm_suballoc * -drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, gfp_t gfp, bool intr, size_t align); +#define drm_suballoc_new kcl_drm_suballoc_new -void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); +void kcl_drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); +#define drm_suballoc_free kcl_drm_suballoc_free /** * drm_suballoc_soffset - Range start. @@ -69,10 +74,11 @@ void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); * * Return: The start of the allocated range. */ -static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_soffset(struct drm_suballoc *sa) { return sa->soffset; } +#define drm_suballoc_soffset kcl_drm_suballoc_soffset /** * drm_suballoc_eoffset - Range end. @@ -80,10 +86,11 @@ static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) * * Return: The end of the allocated range + 1. */ -static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_eoffset(struct drm_suballoc *sa) { return sa->eoffset; } +#define drm_suballoc_eoffset kcl_drm_suballoc_eoffset /** * drm_suballoc_size - Range size. @@ -91,23 +98,27 @@ static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) * * Return: The size of the allocated range. */ -static inline size_t drm_suballoc_size(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_size(struct drm_suballoc *sa) { return sa->eoffset - sa->soffset; } +#define drm_suballoc_size kcl_drm_suballoc_size #ifdef CONFIG_DEBUG_FS -void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base); #else static inline void -drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base) { } #endif +#define drm_suballoc_dump_debug_info kcl_drm_suballoc_dump_debug_info +#endif /* HAVE_DRM_SUBALLOC_MANAGER_INIT */ + #endif /*HAVE_DRM_DRM_SUBALLOC_H*/ #endif /* _KCL_DRM_SUBALLOC_H_ */ From 6f0a6fa60cb2133dadfc0815423a9df6dec77046 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 23 Sep 2025 19:25:31 +0800 Subject: [PATCH 1604/2070] drm/amdkcl: fix detection of built-in drm_suballoc_helper The autoconf test added to probe for the presence of CONFIG_DRM_SUBALLOC_HELPER uses #ifdef, which is not visible to built-in code when the helper is configured as a module. As a result HAVE_DRM_SUBALLOC_MANAGER_INIT is never defined and amdgpu keeps its own duplicate implementation even when the kernel already provides one. Replace the #ifdef with IS_ENABLED() so that the test passes whenever the helper is enabled (y or m) and the KCL wrapper is dropped as intended. Reviewed-by: Bob Zhou Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 index 46363385a7097..e735965113377 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - #ifdef CONFIG_DRM_SUBALLOC_HELPER + #if IS_ENABLED(CONFIG_DRM_SUBALLOC_HELPER) drm_suballoc_manager_init(NULL, 0, 0); #else #error CONFIG_DRM_SUBALLOC_HELPER is not enabled From e6295ba715617409eedc15d2b2450bab4626dc4e Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 15 Oct 2025 11:12:39 +0800 Subject: [PATCH 1605/2070] drm/amdkcl: fake dev_printk.h header It's caused by the commit: 19da88431 "drm/amd/ras: Add amdgpu ras system functions" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/dev_printk.h | 11 +++++++++++ 3 files changed, 22 insertions(+) create mode 100644 include/kcl/header/linux/dev_printk.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 64031287b2176..c2fa80232369c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -876,6 +876,12 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CONTAINER_OF_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEVICE_CLASS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEV_PRINTK_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index bf27afe78e544..640ce25dcfd15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -179,4 +179,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kunit: support failure from dynamic analysis tools dnl AC_KERNEL_CHECK_HEADERS([kunit/test-bug.h]) + + dnl #v5.5-rc2-4-gaf628aae8640 + dnl #device.h: move dev_printk()-like functions to dev_printk.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dev_printk.h]) ]) diff --git a/include/kcl/header/linux/dev_printk.h b/include/kcl/header/linux/dev_printk.h new file mode 100644 index 0000000000000..876e5c2928554 --- /dev/null +++ b/include/kcl/header/linux/dev_printk.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_DEV_PRINTK_H +#define _KCL_HEADER_LINUX_DEV_PRINTK_H + +#ifdef HAVE_LINUX_DEV_PRINTK_H +#include_next +#else +#include +#endif + +#endif \ No newline at end of file From 4cf1231bb31f703a2ba599cb14d47c8e49c89d60 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 15 Oct 2025 13:56:35 +0800 Subject: [PATCH 1606/2070] drm/amdkcl: test whether mempool_alloc_preallocated is available It's caused by the commit: 0d5cdd74 "drm/amd/ras: Use ring buffer to record ras ecc data" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_mempool.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mempool_alloc_preallocated.m4 | 17 ++++++++ include/kcl/kcl_mempool.h | 15 +++++++ 7 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mempool.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 create mode 100644 include/kcl/kcl_mempool.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 505b07b3c3820..b7bcc57a9a977 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o \ + kcl_mempool.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c b/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c new file mode 100644 index 0000000000000..aaa84255aff5d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c @@ -0,0 +1,40 @@ +#include +#include + +#ifndef HAVE_MEMPOOL_ALLOC_PREALLOCATED +/* + * Backport of mempool_alloc_preallocated from commit 37dcc69ad17a0 + * (mempool: introduce mempool_use_prealloc_only). + */ +static void *remove_element(mempool_t *pool) +{ + void *element = pool->elements[--pool->curr_nr]; + + BUG_ON(pool->curr_nr < 0); + return element; +} + +void *kcl_mempool_alloc_preallocated(mempool_t *pool) +{ + void *element; + unsigned long flags; + + spin_lock_irqsave(&pool->lock, flags); + if (likely(pool->curr_nr)) { + element = remove_element(pool); + spin_unlock_irqrestore(&pool->lock, flags); + /* paired with rmb in mempool_free(), read comment there */ + smp_wmb(); + /* + * Update the allocation stack trace as this is more useful + * for debugging. + */ + kmemleak_update_trace(element); + return element; + } + spin_unlock_irqrestore(&pool->lock, flags); + + return NULL; +} +EXPORT_SYMBOL_GPL(kcl_mempool_alloc_preallocated); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 88f3fc8b23c2e..8cfe0a15ed591 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -148,5 +148,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c2fa80232369c..947f84549b6ef 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -954,6 +954,9 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 +/* mempool_alloc_preallocated() is available */ +#define HAVE_MEMPOOL_ALLOC_PREALLOCATED 1 + /* migrate_disable() is available */ #define HAVE_MIGRATE_DISABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5895ca619685b..97c79d20fa391 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -275,6 +275,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_LIST_IS_HEAD AC_AMDGPU_DEVM_I2C_ADD_ADAPTER + AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 b/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 new file mode 100644 index 0000000000000..8f11b7597c3a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.7-rc4-323-g37dcc69ad17a +dnl # mempool: introduce mempool_use_prealloc_only +dnl # +AC_DEFUN([AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + mempool_alloc_preallocated(NULL); + ],[mempool_alloc_preallocated], [mm/mempool.c],[ + AC_DEFINE(HAVE_MEMPOOL_ALLOC_PREALLOCATED, 1, + [mempool_alloc_preallocated() is available]) + ]) + ]) +]) + \ No newline at end of file diff --git a/include/kcl/kcl_mempool.h b/include/kcl/kcl_mempool.h new file mode 100644 index 0000000000000..4bcc809d30aee --- /dev/null +++ b/include/kcl/kcl_mempool.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_MEMPOOL_H +#define AMDGPU_BACKPORT_KCL_MEMPOOL_H + +#include + +#ifndef HAVE_MEMPOOL_ALLOC_PREALLOCATED + +extern void *kcl_mempool_alloc_preallocated(mempool_t *pool) __malloc; + +#define mempool_alloc_preallocated kcl_mempool_alloc_preallocated + +#endif + +#endif From c547f89f55493deaf8a5aad2fca44695bf35ca21 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Fri, 28 Mar 2025 12:10:33 -0400 Subject: [PATCH 1607/2070] drm/amdkcl: Add Peerdirect checks for KFD Certain kernels may have integrated peer_mem into their base Linux module, while others may have it as a separate module. Link against the ofa_kernel as a last resort in case that's the only option available. Some older NICs can't support dma_buf, so this is required in order to get PeerDirect to work on NICs that don't support dma_buf Signed-off-by: Kent Russell Reviewed-by: Perry Yuan --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 13 ++++++--- drivers/gpu/drm/amd/dkms/Kbuild | 9 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 | 31 +++++++++++++++++++++ 5 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 09461f004377e..aa4333548daeb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -86,7 +86,6 @@ */ #define IB_PEER_MEMORY_NAME_MAX 64 #define IB_PEER_MEMORY_VER_MAX 16 - struct peer_memory_client { char name[IB_PEER_MEMORY_NAME_MAX]; char version[IB_PEER_MEMORY_VER_MAX]; @@ -117,7 +116,6 @@ void *ib_register_peer_memory_client(struct peer_memory_client *peer_client, invalidate_peer_memory *invalidate_callback); void ib_unregister_peer_memory_client(void *reg_handle); - /*------------------- PeerDirect bridge driver ------------------------------*/ #define AMD_PEER_BRIDGE_DRIVER_VERSION "1.0" @@ -442,6 +440,10 @@ void kfd_init_peer_direct(void) pr_debug("Try to initialize PeerDirect support\n"); +#if defined(HAVE_KFD_PEERDIRECT_SUPPORT) + pfn_ib_register_peer_memory_client = ib_register_peer_memory_client; + pfn_ib_unregister_peer_memory_client = ib_unregister_peer_memory_client; +#else pfn_ib_register_peer_memory_client = (void *(*)(struct peer_memory_client *, invalidate_peer_memory *)) @@ -450,6 +452,7 @@ void kfd_init_peer_direct(void) pfn_ib_unregister_peer_memory_client = (void (*)(void *)) symbol_request(ib_unregister_peer_memory_client); +#endif if (!pfn_ib_register_peer_memory_client || !pfn_ib_unregister_peer_memory_client) { pr_debug("PeerDirect interface was not detected\n"); @@ -482,13 +485,15 @@ void kfd_close_peer_direct(void) if (pfn_ib_unregister_peer_memory_client) { if (ib_reg_handle) pfn_ib_unregister_peer_memory_client(ib_reg_handle); - +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) symbol_put(ib_unregister_peer_memory_client); +#endif } +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) if (pfn_ib_register_peer_memory_client) symbol_put(ib_register_peer_memory_client); - +#endif /* Reset pointers to be safe */ pfn_ib_unregister_peer_memory_client = NULL; diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 02fb141c1d995..96a6424ce8378 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -32,6 +32,15 @@ LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) +# In the peerdirect m4, we determine if the p2p symbols are in the ofa_kernel's Module.symvers +# If so, we need to include the path for the function pointers, as well as the include path for +# rdma/peer_mem.h, since the ofa_kernel isn't integrated into the base kernel in that configuration +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(call _is_kcl_macro_defined,HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH),y) +KBUILD_EXTRA_SYMBOLS += /usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/Module.symvers +USER_INCLUDE += -I/usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/include +endif + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/kcl/header \ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 947f84549b6ef..0bf169391b0d6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -798,6 +798,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* HAVE_KFD_PEERDIRECT_SUPPORT is available */ +/* #undef HAVE_KFD_PEERDIRECT_SUPPORT */ + /* kfifo_out_linear() available */ #define HAVE_KFIFO_OUT_LINEAR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 97c79d20fa391..3044f254d5495 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -276,6 +276,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_HEAD AC_AMDGPU_DEVM_I2C_ADD_ADAPTER AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED + AC_AMDGPU_KFD_PEERDIRECT_SUPPORT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 new file mode 100644 index 0000000000000..6447b6c16afac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # +dnl # PEER DIRECT support +dnl # +dnl # Note that some kernels will have rdma/peer_mem.h and general P2P +dnl # support included. We should check for that case first. If so, we +dnl # set p2p support to 1. +dnl # If the system uses the ofa_kernel, which is present outside of the +dnl # base kernel, then check if it exists and has a p2p symbol present. +dnl # If so, we set p2p support to 1, but also require setting the path +dnl # to the ofa_kernel, which is checked in Kbuild. +dnl # This way we can support configs that have p2p integrated into the +dnl # base kernel, or configs using the ofa_kernel +AC_DEFUN([AC_AMDGPU_KFD_PEERDIRECT_SUPPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct peer_memory_client client; + ib_register_peer_memory_client(&client, NULL); + ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + ], [ + AS_IF([ grep -qw ib_register_peer_memory_client /usr/src/ofa_kernel/x86_64/${KERNELVER}/Module.symvers ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path]) + ]) + ]) + ]) +]) + From 0753c1200c3664b8ab413e496dd13177d10dcc42 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 14 Oct 2025 10:17:44 +0800 Subject: [PATCH 1608/2070] drm/amdkcl: update the functions to use amdgpu version of hmm on non-upstream code It's caused by the commit: 5e0ed4b "drm/amdgpu: update the functions to use amdgpu version of hmm" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +-- 5 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a46df145f2a53..35fb1c3b4aee3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1182,7 +1182,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -3012,7 +3012,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); if (ret) { mem->user_pages[0] = NULL; pr_debug("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6cb5d9f698cba..850aa2cd4abbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1059,7 +1059,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); if (r) { DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); kvfree(e->user_pages); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 8d5dc0df4ded5..bd8d2a8244509 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -618,8 +618,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); #else - r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, - &range); + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index cc06e430c5c53..67c88d483cd9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -841,8 +841,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 1c8fa910cc48d..b77bcec1e8dc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -226,8 +226,7 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return -EPERM; } #else -static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range) +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) { return -EPERM; } From f0394dde4b117328f491e4ac3ef45e147030bb3a Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 23 Oct 2025 11:30:16 +0800 Subject: [PATCH 1609/2070] drm/amdkcl: test whether pm_hibernation_mode_is_suspend() is available It's caused by the commit: 1fcbc0b6a8 "drm/amd: Fix hybrid sleep" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pm_hibernation_mode_is_suspend.m4 | 16 ++++++++++++++++ include/kcl/kcl_suspend.h | 8 ++++++-- 5 files changed, 30 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0016156bd8fd6..cea3da3bd7728 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2762,7 +2762,7 @@ static int amdgpu_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); -#if defined(HAVE_PM_HIBERNATE_IS_RECOVERING) || !defined(CONFIG_PM_SLEEP) +#if defined(HAVE_PM_HIBERNATION_MODE_IS_SUSPEND) || defined(HAVE_PM_HIBERNATE_IS_RECOVERING) /* do not resume device if it's normal hibernation */ if (console_suspend_enabled && !pm_hibernate_is_recovering() && diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0bf169391b0d6..b20cab23a3ae8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1023,6 +1023,12 @@ /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 +/* pm_hibernate_is_recovering() is available */ +#define HAVE_PM_HIBERNATE_IS_RECOVERING 1 + +/* pm_hibernation_mode_is_suspend() is available */ +#define HAVE_PM_HIBERNATION_MODE_IS_SUSPEND 1 + /* pm_runtime_get_if_active() has one parameters */ #define HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3044f254d5495..b76f8e8b247e0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -260,6 +260,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SHMEM_WRITEOUT AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING + AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 new file mode 100644 index 0000000000000..c160029bddfd1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.16-2076-gbed9bcd014c2 +dnl # PM: hibernate: Add pm_hibernation_mode_is_suspend() +dnl # +AC_DEFUN([AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pm_hibernation_mode_is_suspend(); + ], [ + AC_DEFINE(HAVE_PM_HIBERNATION_MODE_IS_SUSPEND, 1, + [pm_hibernation_mode_is_suspend() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index c112660bd0b6b..dbad9ba7b0abe 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -17,10 +17,14 @@ static inline void ksys_sync_helper(void) #ifndef HAVE_KSYS_SYNC_HELPER static inline void ksys_sync_helper(void) {} #endif /* HAVE_KSYS_SYNC_HELPER */ +#endif /* CONFIG_PM_SLEEP */ #ifndef HAVE_PM_HIBERNATE_IS_RECOVERING static inline bool pm_hibernate_is_recovering(void) { return false; } -#endif -#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_PM_HIBERNATE_IS_RECOVERING */ + +#ifndef HAVE_PM_HIBERNATION_MODE_IS_SUSPEND +static inline bool pm_hibernation_mode_is_suspend(void) { return false; } +#endif /* HAVE_PM_HIBERNATEION_MODE_IS_SUSPEND */ #endif /* AMDKCL_SUSPEND_H */ From baf02e33fecd0123449f788d10e2ca19da640ebf Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 3 Nov 2025 11:34:09 +0800 Subject: [PATCH 1610/2070] drm/amdkcl: modify the return of drm_gem_is_imported() in KCL The dma_buf retrieval method was changed by Revert "drm/amdgpu: Use dma_buf from GEM object instance". The KCL must be updated accordingly to stay in sync with driver&kernel. Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_gem.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index 82485f6798b69..af931dc7d12ce 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -92,8 +92,7 @@ static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_obje */ static inline bool drm_gem_is_imported(const struct drm_gem_object *obj) { - /* The dma-buf's priv field points to the original GEM object. */ - return obj->dma_buf && (obj->dma_buf->priv != obj); + return !!obj->import_attach; } #endif #endif From 302f82ffc2a868e02cdc07e2ad201ac6b17691e3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Nov 2025 11:10:10 +0800 Subject: [PATCH 1611/2070] drm/amdkcl: cleanup vmf_insert_*() Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 28 -------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 - drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 32 ---------------- .../drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 35 ----------------- drivers/gpu/drm/ttm/backport/backport.h | 1 - include/kcl/kcl_memory.h | 11 ------ include/kcl/kcl_mm.h | 4 -- include/kcl/kcl_mm_types.h | 38 ------------------- 8 files changed, 151 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 delete mode 100644 include/kcl/kcl_mm_types.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index b835dd0f0e28b..788b0224d6e59 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -31,34 +31,6 @@ #include #include -#ifndef HAVE_VMF_INSERT_PFN_PROT -#ifndef HAVE_VM_INSERT_PFN_PROT -int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, - unsigned long pfn, pgprot_t pgprot) -{ - struct vm_area_struct cvma = *vma; - - cvma.vm_page_prot = pgprot; - - return vm_insert_pfn(&cvma, addr, pfn); -} -#endif - -vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, - unsigned long pfn, pgprot_t pgprot) -{ - int err = vm_insert_pfn_prot(vma, addr, pfn, pgprot); - - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} -EXPORT_SYMBOL(_kcl_vmf_insert_pfn_prot); -#endif - /* Copied from mm/util.c and modified for KCL */ #ifdef HAVE_NO_KVREALLOC void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b76f8e8b247e0..101000021b5f9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,8 +27,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_FSLEEP AC_AMDGPU_USLEEP_RANGE_STATE - AC_AMDGPU_VMF_INSERT - AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index cd07c76959799..74e2dd24ae725 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -1,35 +1,3 @@ -dnl # -dnl # commit v4.4-6466-g34c0fd540e79 -dnl # mm, dax, pmem: introduce pfn_t -dnl # -AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - pfn_t pfn; - pfn.val = 0; - ], [ - dnl # - dnl # commit v4.16-7358-g1c8f422059ae - dnl # mm: change return type to vm_fault_t - dnl # - AC_DEFINE(HAVE_PFN_T, 1, [pfn_t is defined]) - - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - pfn_t pfn = {}; - vmf_insert_mixed(NULL, 0, pfn); - vmf_insert_pfn(NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_VMF_INSERT, 1, - [vmf_insert_*() are available]) - ]) - ]) - ]) -]) - dnl # dnl # commit v6.16-rc5-105-g21aa65bf82a7 dnl # mm: remove callers of pfn_t functionality diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 deleted file mode 100644 index 192bb1767dda5..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 +++ /dev/null @@ -1,35 +0,0 @@ -dnl # -dnl # commit v4.19-6927-gf5e6d1d5f8f3 -dnl # mm: introduce vmf_insert_pfn_prot() -dnl # -AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ],[ - pgprot_t prot = {0}; - vmf_insert_pfn_prot(NULL, 0, 0, prot); - ],[ - AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, - 1, - [vmf_insert_pfn_prot() is available]) - ],[ - dnl # - dnl # commit v4.4-528-g1745cbc5d0de - dnl # mm: Add vm_insert_pfn_prot() - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - #include - ],[ - pgprot_t prot = {0}; - vm_insert_pfn_prot(NULL, 0, 0, prot); - ],[ - AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, - 1, - [vm_insert_pfn_prot() is available]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index b5c736e2211d9..297cadab1232a 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -25,5 +25,4 @@ #include #include #include - #endif diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index 571c570dd2c42..c90c5d520e8dd 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -2,17 +2,6 @@ #ifndef _KCL_KCL_MEMORY_H #define _KCL_KCL_MEMORY_H -#ifndef HAVE_VMF_INSERT_PFN_PROT -vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, - unsigned long pfn, pgprot_t pgprot); -static inline -vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, - unsigned long pfn, pgprot_t pgprot) -{ - return _kcl_vmf_insert_pfn_prot(vma, addr, pfn, pgprot); -} -#endif /* HAVE_VMF_INSERT_PFN_PROT */ - #ifdef HAVE_NO_KVREALLOC void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index a009a7159cc4a..0987388f106aa 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -7,15 +7,11 @@ #ifndef AMDKCL_MM_H #define AMDKCL_MM_H -#include -#include -#include #include #include #include #include #include -#include #include #ifndef untagged_addr diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h deleted file mode 100644 index a180469fd2508..0000000000000 --- a/include/kcl/kcl_mm_types.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_MM_TYPES_H -#define AMDKCL_MM_TYPES_H - -#include -#ifdef HAVE_PFN_T -#include -#else -/* Copied from include/linux/pfn_t.h */ -typedef struct { - u64 val; -} pfn_t; - -#define PFN_FLAGS_MASK (((unsigned long) ~PAGE_MASK) \ - << (BITS_PER_LONG - PAGE_SHIFT)) -#define PFN_SG_CHAIN (1UL << (BITS_PER_LONG - 1)) -#define PFN_SG_LAST (1UL << (BITS_PER_LONG - 2)) -#define PFN_DEV (1UL << (BITS_PER_LONG - 3)) -#define PFN_MAP (1UL << (BITS_PER_LONG - 4)) - -static inline pfn_t __pfn_to_pfn_t(unsigned long pfn, unsigned long flags) -{ - pfn_t pfn_t = { .val = pfn | (flags & PFN_FLAGS_MASK), }; - - return pfn_t; -} - -static inline unsigned long pfn_t_to_pfn(pfn_t pfn) -{ - return pfn.val & ~PFN_FLAGS_MASK; -} -#endif - -#if !defined(HAVE_VMF_INSERT) && !defined(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN) -typedef int vm_fault_t; -#endif - -#endif /* AMDKCL_MM_TYPES_H */ From e797f0fcb8bd0e4ecdb0d22e04b6234994c0dccf Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Nov 2025 13:59:19 +0800 Subject: [PATCH 1612/2070] drm/amdkcl: update detect macro HAVE_MIGRATE_DISABLE migrate_disable is modified to sched.h, so update m4. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 index 5ffb95e258143..6de719a9bc6da 100644 --- a/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_AMDGPU_MIGRATE_DISABLE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ],[ migrate_disable(); ],[ From f80cafa8dd27e367b6866e75335d9e31ac52606e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Nov 2025 14:13:42 +0800 Subject: [PATCH 1613/2070] drm/amdkcl: add linux/printk.h for dkms backport Signed-off-by: Bob Zhou --- include/kcl/kcl_i2c.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h index 064fa63c6d2d6..5b3c096afdf65 100644 --- a/include/kcl/kcl_i2c.h +++ b/include/kcl/kcl_i2c.h @@ -11,6 +11,7 @@ #define _KCL_KCL_I2C_H #include +#include #ifdef HAVE_I2C_NEW_CLIENT_DEVICE extern struct i2c_client * From 8181a0a9b9ead794b03d66286a9b4c2ac31fcc37 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 4 Sep 2025 09:57:25 +0800 Subject: [PATCH 1614/2070] drm/amd/pm: unified smu feature cap for vcn reset [v2] unified vcn reset smu feature cap Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 6f95abcc8ea44..b8fa554559814 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3310,6 +3310,15 @@ static int smu_v13_0_6_post_init(struct smu_context *smu) struct smu_phase_det_ctl *pd_ctl; bool enable; + if (smu_v13_0_6_is_link_reset_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET); + + if (smu_v13_0_6_reset_sdma_is_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); + + if (smu_v13_0_6_reset_vcn_is_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET); + pd_ctl = smu_dpm->pd_ctl; if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) @@ -4052,7 +4061,6 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num, .send_rma_reason = smu_v13_0_6_send_rma_reason, .reset_sdma = smu_v13_0_6_reset_sdma, - .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, .post_init = smu_v13_0_6_post_init, .ras_send_msg = smu_v13_0_6_ras_send_msg, From 04538ca74730c5b8131d351a50cba6f9e7ca5349 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Nov 2025 16:56:25 +0800 Subject: [PATCH 1615/2070] drm/amdkcl: test if range_overflows() is available It's caused by d507ae0dc83b7f43cdf6760b8f1a30aac4fc405a drm/buddy: Add start address support to trim function Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/backport_drm_buddy.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/overflow.m4 | 14 +++++++++++ include/kcl/kcl_overflow.h | 24 +++++++++++++++++++ 4 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h index c5ccbc3a8741c..297561aba8334 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -3,5 +3,6 @@ #define _KCL_BACKPORT_DRM_BUDDY_H #include +#include #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 101000021b5f9..058cc2a3f5f04 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -249,6 +249,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL + AC_AMDGPU_RANGE_OVERFLOWS AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_AMDGPU_BIN_ATTR_CONST_ARGS AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 index 7ee5a99374193..e62b784d85e4c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -14,4 +14,18 @@ AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ [size_mul() is available]) ]) ]) +]) + +AC_DEFUN([AC_AMDGPU_RANGE_OVERFLOWS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool ret; + ret = range_overflows(0, 0, 0); + ], [ + AC_DEFINE(HAVE_RANGE_OVERFLOWS, 1, + [range_overflows() is available]) + ]) + ]) ]) \ No newline at end of file diff --git a/include/kcl/kcl_overflow.h b/include/kcl/kcl_overflow.h index 6a0403d4c05ec..95a8a93d6a9f9 100644 --- a/include/kcl/kcl_overflow.h +++ b/include/kcl/kcl_overflow.h @@ -6,4 +6,28 @@ #ifndef HAVE_SIZE_MUL #define size_mul array_size #endif + +#ifndef HAVE_RANGE_OVERFLOWS +/** + * range_overflows() - Check if a range is out of bounds + * @start: Start of the range. + * @size: Size of the range. + * @max: Exclusive upper boundary. + * + * A strict check to determine if the range [@start, @start + @size) is + * invalid with respect to the allowable range [0, @max). Any range + * starting at or beyond @max is considered an overflow, even if @size is 0. + * + * Returns: true if the range is out of bounds. + */ +#define range_overflows(start, size, max) ({ \ + typeof(start) start__ = (start); \ + typeof(size) size__ = (size); \ + typeof(max) max__ = (max); \ + (void)(&start__ == &size__); \ + (void)(&start__ == &max__); \ + start__ >= max__ || size__ > max__ - start__; \ +}) #endif + +#endif // _KCL_OVERFLOW_H_ From 5af3805a3607856fd1dabb48885fb87360038c38 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 10 Nov 2025 08:22:34 +0800 Subject: [PATCH 1616/2070] drm/amdkcl: test if drm_get_panel_backlight_quirk() is available Signed-off-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d06c9e0b6d9f8..59592f4dddde3 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3809,7 +3809,9 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { +#ifdef HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK const struct drm_panel_backlight_quirk *panel_backlight_quirk; +#endif struct amdgpu_dm_backlight_caps *caps; struct drm_connector *conn_base; struct amdgpu_device *adev; @@ -3859,6 +3861,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_min_input_signal = 1; #endif +#ifdef HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK panel_backlight_quirk = drm_get_panel_backlight_quirk(aconnector->drm_edid); if (!IS_ERR_OR_NULL(panel_backlight_quirk)) { @@ -3877,6 +3880,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) panel_backlight_quirk->brightness_mask; } } +#endif } DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 new file mode 100644 index 0000000000000..4ff1d15d7f9a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc1-123-g1234567890ab +dnl # drm/utils: add drm_get_panel_backlight_quirk +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PANEL_BACKLIGHT_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_get_panel_backlight_quirk(NULL); + ],[ + AC_DEFINE(HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK, 1, + [drm_get_panel_backlight_quirk() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 058cc2a3f5f04..8a3ca7ca553ed 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -73,6 +73,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE + AC_AMDGPU_DRM_PANEL_BACKLIGHT_QUIRK AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS From 4a103aadc464b286f766d180ee32ed6296afaaff Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 10 Nov 2025 08:29:27 +0800 Subject: [PATCH 1617/2070] drm/amdkcl: wrap code under macro HAVE_DRM_DP_ATOMIC_SETUP_COMMIT Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 59592f4dddde3..7dfbdd892950f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -231,7 +231,9 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state); +#endif static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, @@ -11081,6 +11083,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) } } +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) { struct drm_crtc *crtc; @@ -11113,6 +11116,7 @@ static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) return 0; } +#endif /** * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. From d088cda48d46addcf6939145a883f1b39b3330fd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 10 Nov 2025 08:30:56 +0800 Subject: [PATCH 1618/2070] drm/amdkcl: wrap code under HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7dfbdd892950f..9cd5839297506 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11146,7 +11146,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) trace_amdgpu_dm_atomic_commit_tail_begin(state); drm_atomic_helper_update_legacy_modeset_state(dev, state); +#ifdef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES drm_dp_mst_atomic_wait_for_dependencies(state); +#endif dm_state = dm_atomic_get_new_state(state); if (dm_state && dm_state->context) { From 4cac08c8aa2e05cbfcba49189f7d74604e5cae01 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 10 Nov 2025 09:43:32 +0800 Subject: [PATCH 1619/2070] drm/amdkcl: test if drm_gem_dmabuf_vmap() has struct iosys_map arg Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 7 ++++++ drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 24 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 0ae97b08f0d8e..79828c6f694b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -511,6 +511,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, return ret; } +#ifdef HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) { struct drm_gem_object *obj = dma_buf->priv; @@ -540,6 +541,7 @@ static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map drm_gem_dmabuf_vunmap(dma_buf, map); amdgpu_bo_unpin(bo); } +#endif const struct dma_buf_ops amdgpu_dmabuf_ops = { #if defined(HAVE_DMA_BUF_OPS_LEGACY) @@ -562,8 +564,13 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, +#ifdef HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG .vmap = amdgpu_dma_buf_vmap, .vunmap = amdgpu_dma_buf_vunmap, +#else + .vmap = drm_gem_dmabuf_vmap, + .vunmap = drm_gem_dmabuf_vunmap, +#endif }; /** diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index 5d14a0d6b877a..6bc1bbb0b3346 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -34,3 +34,27 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD], [ ]) ]) ]) + +dnl # +dnl # commit 6619ccf1bb1d +dnl # dma-buf: Use struct dma_buf_map in dma_buf_vmap() interfaces +dnl # +dnl # commit 20e76f1a7059 +dnl # dma-buf: Use struct dma_buf_map in dma_buf_vunmap() interfaces +dnl # +dnl # commit c67e62790f5c +dnl # drm/prime: split array import functions v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + struct iosys_map map; + drm_gem_dmabuf_vmap(NULL, &map); + ],[drm_gem_dmabuf_vmap], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG, 1, + [drm_gem_dmabuf_vmap() has struct iosys_map arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8a3ca7ca553ed..9724ea1030c7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -104,6 +104,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG + AC_AMDGPU_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT AC_AMDGPU_FS_RECLAIM_ACQUIRE From 3921dc29c0c740263fc2048901519f8da9675284 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Nov 2025 17:47:15 +0800 Subject: [PATCH 1620/2070] drm/amdkcl: test if bin_attrs in struct attribute_group is const Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_attribute_group.m4 | 21 +++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 9775436c0392a..62721aed139df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4329,10 +4329,17 @@ static ssize_t amdgpu_psp_vbflash_status(struct device *dev, } static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW static const struct bin_attribute *const bin_flash_attrs[] = { &psp_vbflash_bin_attr, NULL }; +#else +static struct bin_attribute *bin_flash_attrs[] = { + &psp_vbflash_bin_attr, + NULL +}; +#endif static struct attribute *flash_attrs[] = { &dev_attr_psp_vbflash_status.attr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a1033547ffddb..2446d4266edf6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2311,10 +2311,17 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) &con->event_state_attr.attr, NULL }; +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW const struct bin_attribute *bin_attrs[] = { NULL, NULL, }; +#else + struct bin_attribute *bin_attrs[] = { + NULL, + NULL, + }; +#endif int r; group.attrs = attrs; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9724ea1030c7f..cc55e1542893d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE + AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 index b61c1e580fd07..1ad8e20e51b6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 @@ -25,3 +25,24 @@ AC_DEFUN([AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE], [ ]) ]) ]) + +dnl # +dnl # commit v5.10-rc1 or later +dnl # sysfs: Make bin_attrs in struct attribute_group const +dnl # +AC_DEFUN([AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + const struct bin_attribute *const test_bin_attrs[] = { NULL }; + struct attribute_group test_group = { + .bin_attrs = test_bin_attrs, + }; + (void)test_group; + ],[ + AC_DEFINE(HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW, 1, + [bin_attrs in struct attribute_group is const]) + ]) + ]) +]) From 44c6576c42257571b1a428a9dcb98c75eb3276cd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Nov 2025 14:48:39 +0800 Subject: [PATCH 1621/2070] drm/amdkcl: test if system_percpu_wq is available Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 | 16 ++++++++++++++++ drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/kcl_workqueue.h | 4 ++++ 4 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cc55e1542893d..4da6691863bbe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -280,6 +280,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DEVM_I2C_ADD_ADAPTER AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED AC_AMDGPU_KFD_PEERDIRECT_SUPPORT + AC_AMDGPU_SYSTEM_PERCPU_WQ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 b/drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 new file mode 100644 index 0000000000000..ef97bed7949dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit id: v6.15-1-g128ea9f6ccfb +dnl # workqueue: Add system_percpu_wq and system_dfl_wq +dnl # +AC_DEFUN([AC_AMDGPU_SYSTEM_PERCPU_WQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct workqueue_struct *wq = system_percpu_wq; + ], [system_percpu_wq], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_SYSTEM_PERCPU_WQ, 1, + [system_percpu_wq is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index d83c01b771f71..948afae3208a8 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -10,4 +10,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_workqueue.h b/include/kcl/kcl_workqueue.h index 345bd0f2cc384..7df2a25b7a61c 100644 --- a/include/kcl/kcl_workqueue.h +++ b/include/kcl/kcl_workqueue.h @@ -16,4 +16,8 @@ */ extern struct workqueue_struct *system_highpri_wq; +#ifndef HAVE_SYSTEM_PERCPU_WQ +#define system_percpu_wq system_wq +#endif + #endif From ededa8429e874bb3188e29ed84845fbefef1d401 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 17 Nov 2025 11:00:26 +0800 Subject: [PATCH 1622/2070] drm/amdkcl: test whether DIV_U64_ROUND_UP exist It's caused by d96c6e251830 "drm/amd/display: Fix pbn to kbps Conversion" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- include/kcl/kcl_math64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_math64.h b/include/kcl/kcl_math64.h index f1d04dee6b8c5..423f1d7ea28f9 100644 --- a/include/kcl/kcl_math64.h +++ b/include/kcl/kcl_math64.h @@ -8,4 +8,8 @@ ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) #endif +#ifndef DIV_U64_ROUND_UP +#define DIV_U64_ROUND_UP(ll, d) ({ u32 _tmp = (d); div_u64((ll) + _tmp - 1, _tmp); }) +#endif + #endif \ No newline at end of file From 6e67f88ef9e14a537468609d4ae5589171bd3a59 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Nov 2025 16:36:08 +0800 Subject: [PATCH 1623/2070] drm/amdkcl: test __drm_private_objs_state->state_to_destroy is available It's caused by 1226cd7c7686aee9363ec39a8a80292e27216c6b "drm/atomic: Change state pointers to a more meaningful name" Signed-off-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/struct_drm_private_objs_state.m4 | 21 +++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9cd5839297506..5eb2599b69e63 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13229,7 +13229,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, int j = state->num_private_objs-1; dm_atomic_destroy_state(obj, - state->private_objs[i].state_to_destroy); +#ifdef HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY + state->private_objs[i].state_to_destroy +#else + state->private_objs[i].state +#endif + ); /* If i is not at the end of the array then the * last element needs to be moved to where i was @@ -13240,7 +13245,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, state->private_objs[j]; state->private_objs[j].ptr = NULL; +#ifdef HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY state->private_objs[j].state_to_destroy = NULL; +#else + state->private_objs[j].state = NULL; +#endif state->private_objs[j].old_state = NULL; state->private_objs[j].new_state = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4da6691863bbe..67f42d2f8835b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -94,6 +94,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE + AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 new file mode 100644 index 0000000000000..bd630c670c8c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v6.18-rc1-214-g1226cd7c7686 +dnl # drm/atomic: Change state pointers to a more meaningful name +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct __drm_private_objs_state *obj_state = NULL; + obj_state->state_to_destroy = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY, 1, + [struct __drm_private_objs_state->state_to_destroy is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE], [ + AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY +]) \ No newline at end of file From a103eccfdcadbac3d245fa528801d2ede518d868 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Nov 2025 14:28:36 +0800 Subject: [PATCH 1624/2070] drm/amdkcl: update drm_client_dev_resume to 1arg It's caused by 7910d69376cde30e5871970d97d1a2e360568474 "drm/client: Remove holds_console_lock parameter from suspend/resume" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c | 13 ++++++------- drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 4 +--- include/kcl/kcl_drm_client_event.h | 7 +++++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c index f49f9e059e17b..23326cab0ea77 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c @@ -1,16 +1,15 @@ #include #ifndef HAVE_DRM_CLIENT_DEV_RESUME -void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock) +void _kcl_drm_client_dev_resume(struct drm_device *dev) { - drm_fb_helper_set_suspend_unlocked(dev->fb_helper, holds_console_lock); + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, true); } -EXPORT_SYMBOL(drm_client_dev_resume); +EXPORT_SYMBOL(_kcl_drm_client_dev_resume); -void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock) +void _kcl_drm_client_dev_suspend(struct drm_device *dev) { - bool suspend = !holds_console_lock; - drm_fb_helper_set_suspend_unlocked(dev->fb_helper, suspend); + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, false); } -EXPORT_SYMBOL(drm_client_dev_suspend); +EXPORT_SYMBOL(_kcl_drm_client_dev_suspend); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 index 2c58adc325572..c0d45ec249beb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -30,7 +30,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CLIENT_DEV_RESUME], [ #include #include ], [ - drm_client_dev_resume(NULL, false); + drm_client_dev_resume(NULL); ], [ AC_DEFINE(HAVE_DRM_CLIENT_DEV_RESUME, 1, [drm_client_dev_resume() is available]) @@ -38,8 +38,6 @@ AC_DEFUN([AC_AMDGPU_DRM_CLIENT_DEV_RESUME], [ ]) ]) - - AC_DEFUN([AC_AMDGPU_DRM_CLIENT], [ AC_AMDGPU_DRM_CLIENT_SETUP AC_AMDGPU_DRM_CLIENT_DEV_RESUME diff --git a/include/kcl/kcl_drm_client_event.h b/include/kcl/kcl_drm_client_event.h index 52f3342a5e573..f3f6d03fc10ee 100644 --- a/include/kcl/kcl_drm_client_event.h +++ b/include/kcl/kcl_drm_client_event.h @@ -3,10 +3,13 @@ #define KCL_KCL_DRM_CLIENT_EVENT_H #include +#include #ifndef HAVE_DRM_CLIENT_DEV_RESUME -void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock); -void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock); +void _kcl_drm_client_dev_resume(struct drm_device *dev); +void _kcl_drm_client_dev_suspend(struct drm_device *dev); +#define drm_client_dev_resume _kcl_drm_client_dev_resume +#define drm_client_dev_suspend _kcl_drm_client_dev_suspend #endif #endif From 6ebea3a7bd9b011ecab941cb9fcae585a9364c0b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 15:52:24 +0800 Subject: [PATCH 1625/2070] drm/amdkcl: kcl-cleanup HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS Also removed HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP Change-Id: Ic77c42f0aebab15c6efece839c0ad7796ab1acf8 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 12 +++--------- drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ ...rture_remove_conflicting_pci_framebuffers.m4 | 17 ----------------- 3 files changed, 3 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h index b734ca7c3d36a..5275dfcb6b6ca 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -5,17 +5,13 @@ #include #include -/* Copied from include/linux/fb.h */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ - !defined(HAVE_DRM_DRM_APERTURE_H) -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name); -#endif static inline int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP + return remove_conflicting_pci_framebuffers(pdev, name); +#else /** * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures * handle bar 0 directly. @@ -32,8 +28,6 @@ int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, */ pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); return remove_conflicting_pci_framebuffers(pdev, 0, name); -#else - return remove_conflicting_pci_framebuffers(pdev, name); #endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b20cab23a3ae8..dec74c40023c6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1053,12 +1053,6 @@ /* whether register_shrinker(x, x) is available */ /* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ -/* remove_conflicting_pci_framebuffers() is available */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - -/* remove_conflicting_pci_framebuffers() wants p,i,p args */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ - /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 index 87f2f1c951581..f4c7be22ebded 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -16,23 +16,6 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ ], [ AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, [remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # v4.19-rc1-110-g4d18975c78f2 fbdev: add remove_conflicting_pci_framebuffers() - dnl # - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ], [ - remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [remove_conflicting_pci_framebuffers() is available]) - ]) ]) ]) ]) From cc157a5a70d256fa766fcfa4a8e47b5b6f6cdc6b Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 11 Dec 2025 16:41:19 +0800 Subject: [PATCH 1626/2070] drm/amdkcl: kcl-cleanup macro HAVE_IDR_REMOVE_RETURN_VOID_POINTER idr_remove() returning void pointer was introduced by kernel v4.11-rc1. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/idr.m4 | 20 -------------------- include/kcl/kcl_idr.h | 13 ------------- 3 files changed, 36 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dec74c40023c6..7c0c19f94b2d9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -768,9 +768,6 @@ /* idr_init_base() is available */ #define HAVE_IDR_INIT_BASE 1 -/* idr_remove return void pointer */ -#define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 - /* import_guid() is available */ #define HAVE_IMPORT_GUID 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 1c678e3c401b7..3f579b7ee7620 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -1,22 +1,3 @@ -dnl # -dnl # commit d3e709e63e97e5f3f129b639991cfe266da60bae -dnl # Author: Matthew Wilcox -dnl # Date: Thu Dec 22 13:30:22 2016 -0500 -dnl # idr: Return the deleted entry from idr_remove -dnl # -AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - void *i; - i = idr_remove(NULL, 0); - ], [ - AC_DEFINE(HAVE_IDR_REMOVE_RETURN_VOID_POINTER, 1, - [idr_remove return void pointer]) - ]) - ]) -]) dnl # dnl # commit v6.1-rc1~27-c4f306e31632 @@ -55,7 +36,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_IDE_IDR_BASE], [ AC_DEFUN([AC_AMDGPU_IDR], [ - AC_AMDGPU_IDR_REMOVE AC_AMDGPU_IDR_INIT_BASE AC_AMDGPU_STRUCT_IDE_IDR_BASE ]) diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h index 1cdea5ec45d67..43d211385f2e4 100644 --- a/include/kcl/kcl_idr.h +++ b/include/kcl/kcl_idr.h @@ -21,19 +21,6 @@ ++id, (entry) = idr_get_next((idr), &(id))) #endif -#ifndef HAVE_IDR_REMOVE_RETURN_VOID_POINTER -static inline void *_kcl_idr_remove(struct idr *idr, int id) -{ - void *ptr; - - ptr = idr_find(idr, id); - if (ptr) - idr_remove(idr, id); - - return ptr; -} -#define idr_remove _kcl_idr_remove -#endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ #ifndef HAVE_IDR_INIT_BASE #ifdef HAVE_STRUCT_IDE_IDR_BASE From c932b298599fafc709f6aa406eb20938a0931f79 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 9 Dec 2025 14:50:25 +0800 Subject: [PATCH 1627/2070] drm/amdkcl: kcl-cleanup HAVE_GET_USER_PAGES_GUP_FLAGS & HAVE_GET_USER_PAGES_6ARGS Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 41 ++++--------------- include/kcl/backport/kcl_mm_backport.h | 13 ++---- 4 files changed, 11 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 67c88d483cd9a..7a6a520d719e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -886,7 +886,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) spin_unlock(>t->guptasklock); if (mm == current->mm) - r = get_user_pages(userptr, num_pages, flags, p, NULL); + r = get_user_pages(userptr, num_pages, flags, p); else r = kcl_get_user_pages_remote(gtt->usertask, mm, userptr, num_pages, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7c0c19f94b2d9..96e546ad271ca 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -732,12 +732,6 @@ /* generic_handle_domain_irq() is available */ #define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 -/* get_user_pages() wants 6 args */ -/* #undef HAVE_GET_USER_PAGES_6ARGS */ - -/* get_user_pages() wants gup_flags parameter */ -#define HAVE_GET_USER_PAGES_GUP_FLAGS 1 - /* get_user_pages_remote() wants gup_flags parameter */ /* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 index 8042f69a0228e..4350eefb61a2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -1,43 +1,16 @@ dnl # -dnl # commit v4.8-14095-g768ae309a961 -dnl # mm: replace get_user_pages() write/force parameters with gup_flags +dnl # commit v6.4-rc4-53-g54d020692b34 +dnl # mm/gup: remove unused vmas parameter from get_user_pages() dnl # AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages(0, 0, 0, NULL, NULL); + get_user_pages(0, 0, 0, NULL); ], [get_user_pages], [mm/gup.c], [ - AC_DEFINE(HAVE_GET_USER_PAGES_GUP_FLAGS, 1, - [get_user_pages() wants gup_flags parameter]) - ], [ - dnl # - dnl # commit v4.6-rc2-1-gc12d2da56d0e - dnl # mm/gup: Remove the macro overload API migration helpers - dnl # from the get_user*() APIs - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - get_user_pages(0, 0, 0, 0, NULL, NULL); - ], [get_user_pages], [mm/gup.c], [ - AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, - [get_user_pages() wants 6 args]) - ],[ - dnl # - dnl # commit v6.4-rc4-53-g54d020692b34 - dnl # mm/gup: remove unused vmas parameter from get_user_pages() - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - get_user_pages(0, 0, 0, NULL); - ], [get_user_pages], [mm/gup.c], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOVE_VMAS, 1, - [get_user_pages() remove vmas argument]) - ]) - ]) - ]) - ]) + AC_DEFINE(HAVE_GET_USER_PAGES_REMOVE_VMAS, 1, + [get_user_pages() remove vmas argument]) + ]) + ]) ]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 27c77cd60bbea..c1fb6266fb090 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -39,23 +39,16 @@ long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, #endif } -#ifndef HAVE_GET_USER_PAGES_GUP_FLAGS static inline long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, - unsigned int gup_flags, struct page **pages, - struct vm_area_struct **vmas) + unsigned int gup_flags, struct page **pages) { -#if defined(HAVE_GET_USER_PAGES_6ARGS) - return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), - !!(gup_flags & FOLL_FORCE), pages, vmas); -#elif defined(HAVE_GET_USER_PAGES_REMOVE_VMAS) +#if defined(HAVE_GET_USER_PAGES_REMOVE_VMAS) return get_user_pages(start, nr_pages, gup_flags, pages); #else - return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), - !!(gup_flags & FOLL_FORCE), pages, vmas); + return get_user_pages(start, nr_pages, gup_flags, pages, NULL); #endif } #define get_user_pages _kcl_get_user_pages -#endif /* HAVE_GET_USER_PAGES_GUP_FLAGS */ #endif From 34fbffd7a18bafee4a048e931bffab69da9c5903 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Dec 2025 15:58:07 +0800 Subject: [PATCH 1628/2070] drm/amdkcl: kcl-cleanup HAVE_TIME64_TO_TM time64_to_tm() introduced by kernel v4.7-rc2-4-ge6c2682a1da3 Since all supported kernels now have this function, remove the compatibility layer. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c | 144 -------------------- drivers/gpu/drm/amd/dkms/config/config.h | 7 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 | 17 --- include/kcl/kcl_time.h | 4 - 6 files changed, 6 insertions(+), 169 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index b7bcc57a9a977..7277d3ad73a96 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_drm_drv.o \ kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o \ kcl_mempool.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c b/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c deleted file mode 100644 index a32d8dd1a0c6e..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: LGPL-2.0+ -/* -* Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. -* This file is part of the GNU C Library. -* Contributed by Paul Eggert (eggert@twinsun.com). -* -* The GNU C Library is free software; you can redistribute it and/or -* modify it under the terms of the GNU Library General Public License as -* published by the Free Software Foundation; either version 2 of the -* License, or (at your option) any later version. -* -* The GNU C Library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* Library General Public License for more details. -* -* You should have received a copy of the GNU Library General Public -* License along with the GNU C Library; see the file COPYING.LIB. If not, -* write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -* Boston, MA 02111-1307, USA. -*/ - -/* -* Converts the calendar time to broken-down time representation -* -* 2009-7-14: -* Moved from glibc-2.6 to kernel by Zhaolei -* 2021-06-02: -* Reimplemented by Cassio Neri -*/ - -#ifndef HAVE_TIME64_TO_TM -#include -#include -#include -#include - -#define SECS_PER_HOUR (60 * 60) -#define SECS_PER_DAY (SECS_PER_HOUR * 24) - -/** - * time64_to_tm - converts the calendar time to local broken-down time - * - * @totalsecs: the number of seconds elapsed since 00:00:00 on January 1, 1970, - * Coordinated Universal Time (UTC). -* @offset: offset seconds adding to totalsecs. -* @result: pointer to struct tm variable to receive broken-down time -*/ -void time64_to_tm(time64_t totalsecs, int offset, struct tm *result) -{ - u32 u32tmp, day_of_century, year_of_century, day_of_year, month, day; - u64 u64tmp, udays, century, year; - bool is_Jan_or_Feb, is_leap_year; - long days, rem; - int remainder; - - days = div_s64_rem(totalsecs, SECS_PER_DAY, &remainder); - rem = remainder; - rem += offset; - while (rem < 0) { - rem += SECS_PER_DAY; - --days; - } - while (rem >= SECS_PER_DAY) { - rem -= SECS_PER_DAY; - ++days; - } - - result->tm_hour = rem / SECS_PER_HOUR; - rem %= SECS_PER_HOUR; - result->tm_min = rem / 60; - result->tm_sec = rem % 60; - - /* January 1, 1970 was a Thursday. */ - result->tm_wday = (4 + days) % 7; - if (result->tm_wday < 0) - result->tm_wday += 7; - - /* - * The following algorithm is, basically, Proposition 6.3 of Neri - * and Schneider [1]. In a few words: it works on the computational - * (fictitious) calendar where the year starts in March, month = 2 - * (*), and finishes in February, month = 13. This calendar is - * mathematically convenient because the day of the year does not - * depend on whether the year is leap or not. For instance: - * - * March 1st 0-th day of the year; - * ... - * April 1st 31-st day of the year; - * ... - * January 1st 306-th day of the year; (Important!) - * ... - * February 28th 364-th day of the year; - * February 29th 365-th day of the year (if it exists). - * - * After having worked out the date in the computational calendar - * (using just arithmetics) it's easy to convert it to the - * corresponding date in the Gregorian calendar. - * - * [1] "Euclidean Affine Functions and Applications to Calendar - * Algorithms". https://arxiv.org/abs/2102.06959 - * - * (*) The numbering of months follows tm more closely and thus, - * is slightly different from [1]. - */ - - udays = ((u64) days) + 2305843009213814918ULL; - - u64tmp = 4 * udays + 3; - century = div64_u64_rem(u64tmp, 146097, &u64tmp); - day_of_century = (u32) (u64tmp / 4); - - u32tmp = 4 * day_of_century + 3; - u64tmp = 2939745ULL * u32tmp; - year_of_century = upper_32_bits(u64tmp); - day_of_year = lower_32_bits(u64tmp) / 2939745 / 4; - - year = 100 * century + year_of_century; - is_leap_year = year_of_century ? !(year_of_century % 4) : !(century % 4); - - u32tmp = 2141 * day_of_year + 132377; - month = u32tmp >> 16; - day = ((u16) u32tmp) / 2141; - - /* - * Recall that January 1st is the 306-th day of the year in the - * computational (not Gregorian) calendar. - */ - is_Jan_or_Feb = day_of_year >= 306; - - /* Convert to the Gregorian calendar and adjust to Unix time. */ - year = year + is_Jan_or_Feb - 6313183731940000ULL; - month = is_Jan_or_Feb ? month - 12 : month; - day = day + 1; - day_of_year += is_Jan_or_Feb ? -306 : 31 + 28 + is_leap_year; - - /* Convert to tm's format. */ - result->tm_year = (long) (year - 1900); - result->tm_mon = (int) month; - result->tm_mday = (int) day; - result->tm_yday = (int) day_of_year; -} -EXPORT_SYMBOL(time64_to_tm); -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 96e546ad271ca..73465d04a7092 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1177,8 +1177,11 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 -/* time64_to_tm() is available */ -#define HAVE_TIME64_TO_TM 1 +/* system_percpu_wq is available */ +#define HAVE_SYSTEM_PERCPU_WQ 1 + +/* timer_delete() is available */ +#define HAVE_TIMER_DELETE 1 /* topology_num_cores_per_package is availablea */ #define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 67f42d2f8835b..138cd1fa9e76e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -240,7 +240,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO - AC_AMDGPU_TIME64_TO_TM AC_AMDGPU_DRM_MEMORY_STATS AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_AMDGPU_MODULE_IMPORT_NS diff --git a/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 b/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 deleted file mode 100644 index 052fe9b7b541f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # v4.7-rc2-4-ge6c2682a1da3 -dnl # time: Add time64_to_tm() -dnl # -AC_DEFUN([AC_AMDGPU_TIME64_TO_TM], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - time64_to_tm(0, 0, NULL); - ], [time64_to_tm],[kernel/time/timeconv.c], [ - AC_DEFINE(HAVE_TIME64_TO_TM, 1, - [time64_to_tm() is available]) - - ]) - ]) -]) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h index ec7f479add4cf..7db18d2e0271d 100644 --- a/include/kcl/kcl_time.h +++ b/include/kcl/kcl_time.h @@ -7,10 +7,6 @@ #include #include -#ifndef HAVE_TIME64_TO_TM -void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); -#endif - #ifndef timer_container_of #define timer_container_of(var, callback_timer, timer_fieldname) \ container_of(callback_timer, typeof(*var), timer_fieldname) From b35bc83fdb191a230d5193ded72cd0c69287f54f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Dec 2025 16:22:39 +0800 Subject: [PATCH 1629/2070] drm/amdkcl: kcl-cleanup HAVE_DRM_CRTC_FORCE_DISABLE_ALL drm_crtc_force_disable_all() introduced by kernel v4.3-rc1~22^2~26 Since all supported kernels now have this function, remove the compatibility layer. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../amd/dkms/m4/drm-crtc-force-disable-all.m4 | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 deleted file mode 100644 index 68ccba497ae81..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 6a0d95285035c43361c72776b4c618f60c0f4ab4 -dnl # drm: Add helpers to turn off CRTCs -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_crtc_force_disable_all(NULL); - ], [drm_crtc_force_disable_all], [drivers/gpu/drm/drm_crtc.c], [ - AC_DEFINE(HAVE_DRM_CRTC_FORCE_DISABLE_ALL, 1, - [drm_crtc_force_disable_all() is available]) - ]) - ]) -]) From 48305b39e00a07255bc078b3eb0f3446e60e1a68 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 4 Dec 2025 16:04:11 +0800 Subject: [PATCH 1630/2070] drm/amdkcl: kcl-cleanup HAVE_SEQ_HEX_DUMP Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c | 57 --------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 | 16 ------ include/kcl/kcl_seq_file.h | 11 ---- 6 files changed, 1 insertion(+), 89 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 7277d3ad73a96..8fa0d5fcf7cbb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_io.o kcl_seq_file.o kcl_security.o \ + kcl_io.o kcl_security.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c deleted file mode 100644 index 725ca1cafbfc8..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/fs/seq_file.c - * - * helper functions for making synthetic files from sequences of records. - * initial implementation -- AV, Oct 2001. - */ -#include - -/* Copied from fs/seq_file.c */ -#ifndef HAVE_SEQ_HEX_DUMP -static void seq_set_overflow(struct seq_file *m) -{ - m->count = m->size; -} - -/* A complete analogue of print_hex_dump() */ -void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, - int rowsize, int groupsize, const void *buf, size_t len, - bool ascii) -{ - const u8 *ptr = buf; - int i, linelen, remaining = len; - int ret; - - if (rowsize != 16 && rowsize != 32) - rowsize = 16; - - for (i = 0; i < len && !seq_has_overflowed(m); i += rowsize) { - linelen = min(remaining, rowsize); - remaining -= rowsize; - - switch (prefix_type) { - case DUMP_PREFIX_ADDRESS: - seq_printf(m, "%s%p: ", prefix_str, ptr + i); - break; - case DUMP_PREFIX_OFFSET: - seq_printf(m, "%s%.8x: ", prefix_str, i); - break; - default: - seq_printf(m, "%s", prefix_str); - break; - } - - ret = hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize, - m->buf + m->count, m->size - m->count, - ascii); - if (ret >= m->size - m->count) { - seq_set_overflow(m); - } else { - m->count += ret; - seq_putc(m, '\n'); - } - } -} -EXPORT_SYMBOL(_kcl_seq_hex_dump); -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 73465d04a7092..6ba6b2b450302 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1053,9 +1053,6 @@ /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 -/* seq_hex_dump() is available */ -#define HAVE_SEQ_HEX_DUMP 1 - /* sg_alloc_table_from_pages_segment() is available */ #define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 138cd1fa9e76e..6acc5a1565c2e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,7 +17,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS - AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI diff --git a/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 deleted file mode 100644 index 5765baa40af2d..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 37607102c4426cf92aeb5da1b1d9a79ba6d95e3f -dnl # seq_file: provide an analogue of print_hex_dump() -dnl # -AC_DEFUN([AC_AMDGPU_SEQ_HEX_DUMP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - seq_hex_dump(NULL,NULL,0,0,0,NULL,0,0); - ], [seq_hex_dump],[fs/seq_file.c], [ - AC_DEFINE(HAVE_SEQ_HEX_DUMP, 1, - [seq_hex_dump() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h index bc9d5c08ecfc1..db16fc41eb424 100644 --- a/include/kcl/kcl_seq_file.h +++ b/include/kcl/kcl_seq_file.h @@ -38,16 +38,5 @@ static const struct file_operations __name ## _fops = { \ } #endif -#ifndef HAVE_SEQ_HEX_DUMP -void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, - int rowsize, int groupsize, const void *buf, size_t len, - bool ascii); -static inline void seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, - int rowsize, int groupsize, const void *buf, size_t len, - bool ascii) -{ - _kcl_seq_hex_dump(m, prefix_str, prefix_type, rowsize, groupsize, buf, len, ascii); -} -#endif #endif From bbb0e16e9d61003e37198ab489612de966bdcc71 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 5 Dec 2025 16:48:21 +0800 Subject: [PATCH 1631/2070] drm/amdkcl: kcl-cleanup HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_backlight.c | 14 -------------- drivers/gpu/drm/amd/dkms/config/config.h | 9 ++++++--- .../dkms/m4/backlight-device-set-brightness.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_backlight.h | 4 ---- 6 files changed, 7 insertions(+), 39 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_backlight.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8fa0d5fcf7cbb..a5bf08c182096 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o -amdkcl-y += kcl_backlight.o kcl_ioctl.o \ +amdkcl-y += kcl_ioctl.o \ kcl_io.o kcl_security.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c deleted file mode 100644 index 1e1da40b92c05..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Backlight Lowlevel Control Abstraction - * - * Copyright (C) 2003,2004 Hewlett-Packard Company - * - */ -#include - -#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS -amdkcl_dummy_symbol(backlight_device_set_brightness, int, return 0, - struct backlight_device *bd, unsigned long brightness) -#endif - diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6ba6b2b450302..4160ecd618a74 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -62,10 +62,13 @@ /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 -/* backlight_device_set_brightness() is available */ -#define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 +/* amdgpu_attr_group->is_bin_visible is available */ +#define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 -/* bitmap_free() is available */ +/* bin_attribute.read is const args */ +#define HAVE_BIN_ATTR_CONST_ARGS 1 + +/* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ #define HAVE_BITMAP_FUNCS 1 /* bitmap_read() is available */ diff --git a/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 deleted file mode 100644 index b021cbc2ab976..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v4.6-rc6-1-gf6a4790a5471 -dnl # video / backlight: add two APIs for drivers to use -dnl # -AC_DEFUN([AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - backlight_device_set_brightness(NULL, 0); - ], [backlight_device_set_brightness], [drivers/video/backlight/backlight.c], [ - AC_DEFINE(HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS, 1, - [backlight_device_set_brightness() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6acc5a1565c2e..0ed0453c4e880 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -11,7 +11,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IDR AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE - AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST diff --git a/include/kcl/kcl_backlight.h b/include/kcl/kcl_backlight.h index bc2696815393d..a3831242c0150 100644 --- a/include/kcl/kcl_backlight.h +++ b/include/kcl/kcl_backlight.h @@ -9,10 +9,6 @@ #define AMDKCL_BACKLIGHT_H #include -#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS -int backlight_device_set_brightness(struct backlight_device *bd, - unsigned long brightness); -#endif /* HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS */ #ifndef BACKLIGHT_POWER_ON #define BACKLIGHT_POWER_ON (0) From f6046bb3a1f62a60f6182efc65c78318552aab54 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 5 Dec 2025 15:54:03 +0800 Subject: [PATCH 1632/2070] drm/amdkcl: kcl-cleanup HAVE_PFN_T Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 9 --------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 16 ---------------- 3 files changed, 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4160ecd618a74..b854c35bf23ec 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,15 +1213,6 @@ /* vmemdup_array_user() is available */ #define HAVE_VMEMDUP_ARRAY_USER 1 -/* vmf_insert_*() are available */ -#define HAVE_VMF_INSERT 1 - -/* vmf_insert_mixed_mkwrite() has long pfn arg */ -/* #undef HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN */ - -/* vmf_insert_pfn_prot() is available */ -#define HAVE_VMF_INSERT_PFN_PROT 1 - /* vm_fault->{address/vma} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0ed0453c4e880..86905fc24a586 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -269,7 +269,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ - AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 deleted file mode 100644 index 74e2dd24ae725..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v6.16-rc5-105-g21aa65bf82a7 -dnl # mm: remove callers of pfn_t functionality -dnl # -AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - vmf_insert_mixed_mkwrite(NULL, 0, 0); - ],[ - AC_DEFINE(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN, 1, - [vmf_insert_mixed_mkwrite() has long pfn arg]) - ]) - ]) -]) From c694093c58029e718d69acf5c512ca239b4dc0a2 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 11 Oct 2024 13:40:42 -0400 Subject: [PATCH 1633/2070] drm/amdkfd: refactor rlc/gfx spm v2 for later adding multiple xcc support. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 12 ++--- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 49 ++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 8 +-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 2 +- 7 files changed, 52 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 5006d803d456c..ece4271b58359 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -462,12 +462,12 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif -void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl); -int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, int xcc_id, bool cntl); +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm, u64 gpu_addr, u32 size); -void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm); -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr); -void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr); +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id); #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); @@ -480,7 +480,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) #endif /* KGD2KFD callbacks */ -void kgd2kfd_spm_interrupt(struct kfd_dev *kfd); +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id); int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 97e5ed3a1212f..3d60abcad5861 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -25,32 +25,33 @@ #include #include "amdgpu_ids.h" -void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, int xcc_id, bool cntl) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); if (cntl) - adev->gfx.spmfuncs->start(adev); + adev->gfx.spmfuncs->start(adev, xcc_id); else - adev->gfx.spmfuncs->stop(adev); + adev->gfx.spmfuncs->stop(adev, xcc_id); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); } -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); - adev->gfx.spmfuncs->set_rdptr(adev, rptr); + adev->gfx.spmfuncs->set_rdptr(adev, xcc_id, rptr); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); } -int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; int r = 0; @@ -63,38 +64,38 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * return r; /* init spm vmid with 0x0 */ - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0); + adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0); /* set spm ring registers */ - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); - adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); + adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, xcc_id, gpu_addr, size); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); return r; } -void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; /* stop spm stream and interrupt */ - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); - adev->gfx.spmfuncs->stop(adev); + adev->gfx.spmfuncs->stop(adev, xcc_id); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0xf); } -void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id) { if (adev->kfd.dev) - kgd2kfd_spm_interrupt(adev->kfd.dev); + kgd2kfd_spm_interrupt(adev->kfd.dev, xcc_id); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 08f16f86c6530..5126134713ee1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -165,10 +165,10 @@ struct amdgpu_kiq { }; struct spm_funcs { - void (*start)(struct amdgpu_device *adev); - void (*stop)(struct amdgpu_device *adev); - void (*set_rdptr)(struct amdgpu_device *adev, u32 rptr); - void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, u64 gpu_rptr, u32 size); + void (*start)(struct amdgpu_device *adev, int xcc_id); + void (*stop)(struct amdgpu_device *adev, int xcc_id); + void (*set_rdptr)(struct amdgpu_device *adev, int xcc_id, u32 rptr); + void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, int xcc_id, u64 gpu_rptr, u32 size); /* Packet sizes */ int set_spm_config_size; }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 48f28eac78306..75cbb468c8421 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7796,7 +7796,7 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static void gfx_v10_0_spm_start(struct amdgpu_device *adev) +static void gfx_v10_0_spm_start(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -7826,7 +7826,7 @@ static void gfx_v10_0_spm_start(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } -static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) +static void gfx_v10_0_spm_stop(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -7842,7 +7842,7 @@ static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); } -static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -7851,7 +7851,7 @@ static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) } static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, - u64 gpu_addr, u32 size) + int xcc_id, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -9924,7 +9924,7 @@ static int gfx_v10_0_spm_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - amdgpu_amdkfd_rlc_spm_interrupt(adev); + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 9796777113a50..99c68d4db3777 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5275,7 +5275,7 @@ static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, amdgpu_ring_write(ring, val); } -static void gfx_v8_0_spm_start(struct amdgpu_device *adev) +static void gfx_v8_0_spm_start(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -5300,7 +5300,7 @@ static void gfx_v8_0_spm_start(struct amdgpu_device *adev) gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_INT_CNTL, 1); } -static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) +static void gfx_v8_0_spm_stop(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -5314,7 +5314,7 @@ static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); } -static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -5322,7 +5322,7 @@ static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) } static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, - u64 gpu_addr, u32 size) + int xcc_id, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -6911,7 +6911,7 @@ static int gfx_v8_0_spm_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - amdgpu_amdkfd_rlc_spm_interrupt(adev); + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b6bcefc251519..8c4edb863c17b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4801,7 +4801,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) return r; } -static void gfx_v9_0_spm_start(struct amdgpu_device *adev) +static void gfx_v9_0_spm_start(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -4826,7 +4826,7 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } -static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) +static void gfx_v9_0_spm_stop(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -4848,7 +4848,7 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); } -static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -4856,7 +4856,8 @@ static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); } -static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) +static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -7223,7 +7224,7 @@ static int gfx_v9_0_spm_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - amdgpu_amdkfd_rlc_spm_interrupt(adev); + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 8f458d998e872..271bb1c57561b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -698,7 +698,7 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) return -EINVAL; } -void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id) { struct kfd_process_device *pdd; struct kfd_node *dev; From bfdcec008d7014aa70d87e19cbb87df4a81f3235 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 14:12:56 +0800 Subject: [PATCH 1634/2070] drm/amdkcl: test if pci_rebar_get_max_size() is available It's caused by c7df7059e3baa1df96d03429923cc137f134658c "drm/amdgpu: Use pci_rebar_get_max_size()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pci_rebar_get_max_size.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 13 +++++++++++++ 3 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 86905fc24a586..a0aebd551c675 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -20,6 +20,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE + AC_AMDGPU_PCI_REBAR_GET_MAX_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 new file mode 100644 index 0000000000000..76b876c4b3ec3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.18-rc1-19-g1c680f2acdbb +dnl # PCI: Add pci_rebar_get_max_size() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_REBAR_GET_MAX_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_rebar_get_max_size(NULL, 0); + ], [ + AC_DEFINE(HAVE_PCI_REBAR_GET_MAX_SIZE, 1, + [pci_rebar_get_max_size() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index c40f95b9507c1..96089d809248d 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -216,4 +216,17 @@ static inline struct pci_dev *pci_get_base_class(unsigned int class, #define PCI_IRQ_INTX PCI_IRQ_LEGACY #endif +#ifndef HAVE_PCI_REBAR_GET_MAX_SIZE +static inline int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) +{ + u32 sizes; + + sizes = pci_rebar_get_possible_sizes(pdev, bar); + if (!sizes) + return -ENOENT; + + return __fls(sizes); +} +#endif + #endif /* AMDKCL_PCI_H */ From 848aeb4ca8ebc1509c3f25c47fbcb12395c88d0f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 14:31:04 +0800 Subject: [PATCH 1635/2070] drm/amdkcl: test if pci_resize_resource() has align parameter It's caused by 337b1b566db087347194e4543ddfdfa5645275cc "PCI: Fix restoring BARs on BAR resize rollback path" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci_resize_resource.m4 | 17 +++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9188d4bce56b9..c17a4ff69b1c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1881,9 +1881,14 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) /* Tear down doorbell as resizing will release BARs */ amdgpu_doorbell_fini(adev); +#ifdef HAVE_PCI_RESIZE_RESOURCE_ALIGN r = pci_resize_resource(adev->pdev, 0, rbar_size, (adev->asic_type >= CHIP_BONAIRE) ? 1 << 5 : 1 << 2); +#else + r = pci_resize_resource(adev->pdev, 0, rbar_size); +#endif + if (r == -ENOSPC) dev_info(adev->dev, "Not enough PCI address space for a large BAR."); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a0aebd551c675..8e6ab849cb1c7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -21,6 +21,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_PCI_REBAR_GET_MAX_SIZE + AC_AMDGPU_PCI_RESIZE_RESOURCE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 new file mode 100644 index 0000000000000..29a6f5dc91d1b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.18-rc1-12-g9f71938cd77f +dnl # PCI: Move Resizable BAR code to rebar.c +dnl # +AC_DEFUN([AC_AMDGPU_PCI_RESIZE_RESOURCE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret = 0; + ret = pci_resize_resource(NULL, 0, 0, 0); + ], [ + AC_DEFINE(HAVE_PCI_RESIZE_RESOURCE_ALIGN, 1, + [pci_resize_resource() has align parameter]) + ]) + ]) +]) \ No newline at end of file From aeca87458133319c8855f96b7050014b2928244f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 15:22:28 +0800 Subject: [PATCH 1636/2070] drm/amdkcl: test if struct drm_atomic_state->plane_color_pipeline is available Signed-off-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5eb2599b69e63..d501e7d13f0f7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6087,8 +6087,10 @@ fill_plane_color_attributes(const struct drm_plane_state *plane_state, *color_space = COLOR_SPACE_SRGB; /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE if (plane_state->state && plane_state->state->plane_color_pipeline) return 0; +#endif /* DRM color properties only affect non-RGB formats. */ if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 index cd7227d5c12eb..33ab26677d24f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 @@ -16,3 +16,19 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED], [ ]) ]) +dnl # +dnl # drm/atomic: Add drm_atomic_state->plane_color_pipeline +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_atomic_state *state = NULL; + state->plane_color_pipeline = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE, 1, + [struct drm_atomic_state->plane_color_pipeline is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8e6ab849cb1c7..f4298cbbdf0a2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -102,6 +102,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG From ca8aa75900462b384b78be0f2c4b9220efacdfe5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 14:52:52 +0800 Subject: [PATCH 1637/2070] drm/amdkcl: test if drm_plane->color_pipeline_property is available It's caused by 18a4127e9315645d30c6b93a820efa0cba299c20 "drm/amd/display: Disable CRTC degamma when color pipeline is enabled" Signed-off-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_drm_plane.m4 | 21 +++++++++++++++++++ 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index fdbdce6063f59..739737a51279b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -789,9 +789,11 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, * 2. DCE since it doesn't support programmable degamma anywhere. * 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor. */ +#ifdef HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY if (plane->color_pipeline_property) has_degamma = false; else +#endif has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 3fa963f7f0ae5..a7e5b79f58c5f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -2008,9 +2008,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, #ifdef AMD_PRIVATE_COLOR dm_atomic_plane_attach_color_mgmt_properties(dm, plane); #else +#ifdef HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY res = dm_plane_init_colorops(plane); if (res) return res; +#endif #endif /* Create (reset) the plane state */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f4298cbbdf0a2..4ea6277dfe2aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_STRUCT_DRM_PLANE AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 new file mode 100644 index 0000000000000..0260e0a4432b3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.8-rc1-123-gd35b4e13b8b8 +dnl # drm/plane: Add color pipeline property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PLANE_COLOR_PIPELINE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_plane *plane = NULL; + plane->color_pipeline_property = NULL; + ],[ + AC_DEFINE(HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY, 1, + [drm_plane->color_pipeline_property is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE], [ + AC_AMDGPU_DRM_PLANE_COLOR_PIPELINE_PROPERTY +]) \ No newline at end of file From a6624b868893ace967708bad5ec84534e364aea8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 15:21:25 +0800 Subject: [PATCH 1638/2070] drm/amdkcl: test struct drm_color_lut32 is available Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/include/kcl/kcl_drm_color_mgmt.h | 32 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_drm_color_lut32.m4 | 57 +++++++++++++++++++ 4 files changed, 91 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8cfe0a15ed591..6a40041b3b06b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h new file mode 100644 index 0000000000000..3ff7751079283 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h @@ -0,0 +1,32 @@ +#ifndef __AMDGPU_BACKPORT_KCL_DRM_COLOR_MGMT_H__ +#define __AMDGPU_BACKPORT_KCL_DRM_COLOR_MGMT_H__ + +#include + +#ifndef HAVE_STRUCT_DRM_COLOR_LUT32 +struct drm_color_lut32 { + __u32 red; + __u32 green; + __u32 blue; + __u32 reserved; +}; +#endif + +#ifndef HAVE_DRM_COLOR_LUT32_SIZE +static inline int drm_color_lut32_size(const struct drm_property_blob *blob) +{ + return blob->length / sizeof(struct drm_color_lut32); +} +#endif + +#ifndef HAVE_DRM_COLOR_LUT32_EXTRACT +static inline u32 drm_color_lut32_extract(u32 user_input, int bit_precision) +{ + u64 max = (bit_precision >= 64) ? ~0ULL : (1ULL << bit_precision) - 1; + + return DIV_ROUND_CLOSEST_ULL((u64)user_input * max, + (1ULL << 32) - 1); +} +#endif + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ea6277dfe2aa..176877997427f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -102,6 +102,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + AC_AMDGPU_DRM_COLOR_LUT32 AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE AC_AMDGPU_DRM_DP_SUBCONNECTOR diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 new file mode 100644 index 0000000000000..156b6ff4ea7a8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # v6.18-rc2-1333-g621c45ca12ed +dnl # drm: Add Enhanced LUT precision structure +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_COLOR_LUT32], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_color_lut32 lut32; + lut32.red = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_COLOR_LUT32, 1, + [struct drm_color_lut32 is available]) + ]) + ]) +]) + +dnl # +dnl # v6.18-rc2-1333-g621c45ca12ed +dnl # drm: Add Enhanced LUT precision structure +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_LUT32_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_color_lut32_size(NULL); + ], [ + AC_DEFINE(HAVE_DRM_COLOR_LUT32_SIZE, 1, + [drm_color_lut32_size() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.18-rc2-1334-g94529775135c +dnl # drm: Add helper to extract lut from struct drm_color_lut32 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_LUT32_EXTRACT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_color_lut32_extract(0, 0); + ], [ + AC_DEFINE(HAVE_DRM_COLOR_LUT32_EXTRACT, 1, + [drm_color_lut32_extract() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_COLOR_LUT32], [ + AC_AMDGPU_STRUCT_DRM_COLOR_LUT32 + AC_AMDGPU_DRM_COLOR_LUT32_SIZE + AC_AMDGPU_DRM_COLOR_LUT32_EXTRACT +]) From 3a557bd7dafd458ff5b7ff67b45b0d33eec57653 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 17:13:07 +0800 Subject: [PATCH 1639/2070] drm/amdkcl: test if drm_colorop.h is available Signed-off-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 12 ++++++++++-- .../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 2 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 7 +++++-- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 +++++ include/kcl/header/drm/drm_colorop.h | 10 ++++++++++ 5 files changed, 32 insertions(+), 4 deletions(-) create mode 100644 include/kcl/header/drm/drm_colorop.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 20a76d81d532d..863b4d67bd27d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -880,6 +880,7 @@ amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) } } +#ifdef HAVE_DRM_DRM_COLOROP_H static enum dc_transfer_func_predefined amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf) { @@ -900,6 +901,7 @@ amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf) return TRANSFER_FUNCTION_LINEAR; } } +#endif static void __to_dc_lut3d_color(struct dc_rgb *rgb, const struct drm_color_lut lut, @@ -1464,6 +1466,7 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, return 0; } +#ifdef HAVE_DRM_DRM_COLOROP_H static int __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state, struct drm_colorop_state *colorop_state) @@ -1492,6 +1495,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state, return 0; } + static int __set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state, @@ -1817,6 +1821,7 @@ __set_dm_plane_colorop_blend(struct drm_plane_state *plane_state, return 0; } +#endif static int amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, @@ -1868,6 +1873,7 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, return 0; } +#ifdef HAVE_DRM_DRM_COLOROP_H static int amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) @@ -1954,7 +1960,7 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, return 0; } - +#endif /** * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. * @crtc: amdgpu_dm crtc state @@ -2050,9 +2056,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, dc_plane_state->gamut_remap_matrix.enable_remap = false; dc_plane_state->input_csc_color_matrix.enable_adjustment = false; } - + +#ifdef HAVE_DRM_DRM_COLOROP_H if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state)) return 0; +#endif return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c index a2de3bba83464..8c03ee28d31d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c @@ -33,6 +33,7 @@ #include "amdgpu_dm_colorop.h" #include "dc.h" +#ifdef HAVE_DRM_DRM_COLOROP_H const u64 amdgpu_dm_supported_degam_tfs = BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) | BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) | @@ -209,3 +210,4 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr return ret; } +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a7e5b79f58c5f..5e41385820683 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1856,7 +1856,7 @@ dm_atomic_plane_get_property(struct drm_plane *plane, return 0; } #else - +#ifdef HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY #define MAX_COLOR_PIPELINES 5 static int @@ -1875,14 +1875,16 @@ dm_plane_init_colorops(struct drm_plane *plane) /* initialize pipeline */ if (dc->ctx->dce_version >= DCN_VERSION_3_0) { +#ifdef HAVE_DRM_DRM_COLOROP_H ret = amdgpu_dm_initialize_default_pipeline(plane, &pipelines[len]); if (ret) { drm_err(plane->dev, "Failed to create color pipeline for plane %d: %d\n", plane->base.id, ret); goto out; } - len++; + len++; +#endif /* Create COLOR_PIPELINE property and attach */ drm_plane_create_color_pipeline_property(plane, pipelines, len); } @@ -1894,6 +1896,7 @@ dm_plane_init_colorops(struct drm_plane *plane) return ret; } #endif +#endif static const struct drm_plane_funcs dm_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 3f4ae2301335a..b2892203adf76 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -146,4 +146,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/client: Move client event handlers to drm_client_event.c dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_client_event.h]) + + dnl # + dnl # drm: Add color operation + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_colorop.h]) ]) diff --git a/include/kcl/header/drm/drm_colorop.h b/include/kcl/header/drm/drm_colorop.h new file mode 100644 index 0000000000000..4f172f73cda8d --- /dev/null +++ b/include/kcl/header/drm/drm_colorop.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_COLOROP_H_H_ +#define _KCL_HEADER_DRM_COLOROP_H_H_ + +#ifdef HAVE_DRM_DRM_COLOROP_H +#include_next +#endif + +#endif + From fe4dc83725ad3256bbedc2bfe3764537303bc735 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jan 2026 17:48:52 +0800 Subject: [PATCH 1640/2070] drm/amdkcl: test if dev_pagemap_ops has folio_free member It's caused by 3a5a06554566fcc9f7de7327cfc365ed384d396c "mm/zone_device: rename page_free callback to folio_free" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 17 ++++++++++++++++- drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 | 19 +++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 4669c90064108..8cde3b0a48484 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -586,7 +586,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, node->xcp ? node->xcp->id : 0); return r < 0 ? r : 0; } - +#ifdef HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE static void svm_migrate_folio_free(struct folio *folio) { struct page *page = &folio->page; @@ -597,6 +597,17 @@ static void svm_migrate_folio_free(struct folio *folio) svm_range_bo_unref_async(svm_bo); } } +#else +static void svm_migrate_page_free(struct page *page) +{ + struct svm_range_bo *svm_bo = page->zone_device_data; + + if (svm_bo) { + pr_debug_ratelimited("ref: %d\n", kref_read(&svm_bo->kref)); + svm_range_bo_unref_async(svm_bo); + } +} +#endif static int svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, @@ -1038,7 +1049,11 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) } static const struct dev_pagemap_ops svm_migrate_pgmap_ops = { +#ifdef HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE .folio_free = svm_migrate_folio_free, +#else + .page_free = svm_migrate_page_free, +#endif .migrate_to_ram = svm_migrate_to_ram, }; diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 index b33ceb61643ce..ad4b11459528a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 @@ -15,7 +15,26 @@ AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_RANGE], [ ]) ]) ]) + +dnl # +dnl # Check for folio_free in dev_pagemap_ops +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_OPS_FOLIO_FREE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct dev_pagemap_ops *ops = NULL; + void (*func)(struct folio *) = ops->folio_free; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE, 1, + [dev_pagemap_ops has folio_free member]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP], [ AC_AMDGPU_DEV_PAGEMAP_RANGE + AC_AMDGPU_DEV_PAGEMAP_OPS_FOLIO_FREE ]) From 769c030306818f3035b6569930bf2ebf4cf9e25c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 29 Jan 2026 15:46:55 +0800 Subject: [PATCH 1641/2070] drm/amdkcl: test if zone_device_page_init() takes 3 arguments It's caused by d245f9b4ab806733a77e51a218ca7b8bc3135cd9 "mm/zone_device: support large zone device private folios" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 14 ++++++++++++-- .../gpu/drm/amd/dkms/m4/zone_device_page_init.m4 | 9 +++++++++ include/kcl/backport/kcl_mm_backport.h | 5 +++++ include/kcl/kcl_mm.h | 4 ---- 4 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 637ecefbb9773..a6d38823dc68c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -17,9 +17,10 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT_3ARG #ifndef HAVE_ZONE_DEVICE_PAGE_INIT /* copied from v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c and modified for kcl usage */ -void zone_device_page_init(struct page *page) +void _kcl_zone_device_page_init(struct page *page, struct dev_pagemap *pgmap, unsigned int order) { /* v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount */ #if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) @@ -27,8 +28,17 @@ void zone_device_page_init(struct page *page) #endif lock_page(page); } -EXPORT_SYMBOL_GPL(zone_device_page_init); +#else +void _kcl_zone_device_page_init(struct page *page, struct dev_pagemap *pgmap, unsigned int order) +{ + VM_WARN_ON_ONCE(order > MAX_ORDER_NR_PAGES); + + WARN_ONCE(order, "legacy kernel without zone_device_page_init pgmap and order arg\n"); + zone_device_page_init(page); +} #endif +EXPORT_SYMBOL_GPL(_kcl_zone_device_page_init); +#endif /* HAVE_ZONE_DEVICE_PAGE_INIT_3ARG */ #ifndef HAVE_KMALLOC_SIZE_ROUNDUP #ifndef CONFIG_SLOB diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 index 56eaeb4b6d888..0e397f6383fc4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -12,6 +12,15 @@ AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ ], [zone_device_page_init], [mm/memremap.c], [ AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + ], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + zone_device_page_init(NULL,NULL, 0); + ], [zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT_3ARG, 1, + [zone_device_page_init() takes 3 arguments]) + ]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index c1fb6266fb090..8696439eda4c5 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -51,4 +51,9 @@ long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, } #define get_user_pages _kcl_get_user_pages +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT_3ARG +void _kcl_zone_device_page_init(struct page *page, struct dev_pagemap *pgmap, unsigned int order); +#define zone_device_page_init _kcl_zone_device_page_init +#endif + #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 0987388f106aa..d46be8b686744 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -23,10 +23,6 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif -#ifndef HAVE_ZONE_DEVICE_PAGE_INIT -void zone_device_page_init(struct page *page); -#endif - #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From e87750e8d83bcd7f28ed99e0e96318e9fb8fe38c Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 16 Apr 2025 13:46:39 -0400 Subject: [PATCH 1642/2070] drm/amdkfd: enhance host trap process in 1st trap handler to support multiple processes, and process correctly when s_trap and context saving exception occur simultaneously. -v2: update comments advised from Lancelot -v3: update advised from Jay -v4: remove state bit S_SAVE_PC_HI_NEED_2ND_LVL_TH_SHIFT -v5: add STATUS.HALT handling Co-authored-by: Lancelot SIX Co-authored-by: Joseph Greathouse Signed-off-by: James Zhu Reviewed-by: Lancelot SIX Reviewed-by: Jay Cornwall --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 1931 +++++++++-------- .../amd/amdkfd/cwsr_trap_handler_gfx12.asm | 77 +- 2 files changed, 1046 insertions(+), 962 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index ff68bba330d46..1831f1fecebdc 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -3701,18 +3701,22 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { }; static const uint32_t cwsr_trap_gfx12_hex[] = { - 0xbfa00001, 0xbfa00239, + 0xbfa00001, 0xbfa0024a, 0xb0804009, 0xb8eef81a, 0xbf880000, 0xb980081a, 0x00000000, 0xb8f8f804, 0x9177ff77, 0x0c000000, 0x846e9a6e, 0x8c776e77, 0x9178ff78, 0x00008c00, - 0xb8fbf811, 0x8b6eff78, - 0x00004000, 0xbfa10008, - 0x8b6eff7b, 0x00000080, + 0xb8fbf811, 0xbf0c877b, + 0xbfa20002, 0x916dff6d, + 0xf0000000, 0xbf0c857b, + 0xbfa20003, 0xbefb1087, + 0xb98001d1, 0x00000000, + 0x8b6eff78, 0x00004000, + 0xbfa10007, 0xbf0d877b, 0xbfa20018, 0x8b6ea07b, - 0xbfa2004a, 0xbf830010, + 0xbfa20053, 0xbf830010, 0xb8fbf811, 0xbfa0fffb, 0x8b6eff7b, 0x00000bd0, 0xbfa20010, 0xb8eef812, @@ -3723,174 +3727,144 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xf0000000, 0xbfa20005, 0x8b6fff6f, 0x00000200, 0xbfa20002, 0x8b6ea07b, - 0xbfa20034, 0xbefa4d82, - 0xbf8a0000, 0x84fa887a, - 0xbf0d8f7b, 0xbfa10002, - 0x8c7bff7b, 0xffff0000, - 0x8b6eff77, 0x0c000000, - 0x916dff6d, 0x0c000000, - 0x8c6d6e6d, 0xf4601bbd, - 0xf8000010, 0xbf8a0000, - 0x846e976e, 0x9177ff77, - 0x00800000, 0x8c776e77, - 0xf4603bbd, 0xf8000000, - 0xbf8a0000, 0xf4603ebd, - 0xf8000008, 0xbf8a0000, - 0x8bee6e6e, 0xbfa10001, - 0xbe80486e, 0x8b6eff6d, - 0xf0000000, 0xbfa20009, - 0xb8eef811, 0x8b6eff6e, - 0x00000080, 0xbfa20007, - 0x8c78ff78, 0x00004000, - 0x80ec886c, 0x82ed806d, - 0xbfa00002, 0x806c846c, - 0x826d806d, 0x8b6dff6d, - 0x0000ffff, 0x8bfe7e7e, - 0x8bea6a6a, 0x85788978, - 0x936eff77, 0x0002001a, - 0xb96ef81a, 0xb9783244, - 0xbe804a6c, 0xb8faf802, - 0xbf0d987a, 0xbfa10001, - 0xbfb00000, 0x8b6dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0151, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbefe4d84, 0xbf8a0000, - 0x8b7aff7f, 0x04000000, - 0x847a857a, 0x8c6d7a6d, - 0xbefa007e, 0x8b7bff7f, - 0x0000ffff, 0xbefe00c1, - 0xbeff00c1, 0xee0a407a, - 0x000c0000, 0x00000000, - 0x7e000280, 0xbefe007a, - 0xbeff007b, 0xb8fb0742, - 0x847b997b, 0xb8fa3b05, - 0x807a817a, 0xbf0d997b, - 0xbfa20002, 0x847a897a, - 0xbfa00001, 0x847a8a7a, + 0xbfa2003d, 0xbeef007b, + 0xbefa4d82, 0xbf8a0000, + 0x84fa887a, 0xbf0d8f7b, + 0xbfa10002, 0x8c7bff7b, + 0xffff0000, 0x8b6eff77, + 0x0c000000, 0x916dff6d, + 0x0c000000, 0x8c6d6e6d, + 0xf4601bbd, 0xf8000010, + 0xbf8a0000, 0x846e976e, + 0x9177ff77, 0x01800000, + 0x8c776e77, 0xbf0d876f, + 0xbfa10006, 0xbf0d8e78, + 0xbfa20002, 0xbf0d9877, + 0xbfa20002, 0xb98001d1, + 0x00000000, 0xf4603bbd, + 0xf8000000, 0xbf8a0000, + 0xf4603ebd, 0xf8000008, + 0xbf8a0000, 0x8bee6e6e, + 0xbfa10001, 0xbe80486e, + 0x8b6eff6d, 0xf0000000, + 0xbfa20009, 0xb8eef811, + 0x8b6eff6e, 0x00000080, + 0xbfa20007, 0x8c78ff78, + 0x00004000, 0x80ec886c, + 0x82ed806d, 0xbfa00002, + 0x806c846c, 0x826d806d, + 0x8b6dff6d, 0x0000ffff, + 0x8bfe7e7e, 0x8bea6a6a, + 0x85788978, 0x936eff77, + 0x0002001a, 0xb96ef81a, + 0xb9783244, 0xbe804a6c, + 0xb8faf802, 0xbf0d987a, + 0xbfa10001, 0xbfb00000, + 0x8b6dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0151, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbefe4d84, + 0xbf8a0000, 0x8b7aff7f, + 0x04000000, 0x847a857a, + 0x8c6d7a6d, 0xbefa007e, 0x8b7bff7f, 0x0000ffff, - 0x807aff7a, 0x00000240, - 0x807a7e7a, 0x827b807b, - 0xd7610000, 0x00010870, - 0xd7610000, 0x00010a71, - 0xd7610000, 0x00010c72, - 0xd7610000, 0x00010e73, - 0xd7610000, 0x00011074, - 0xd7610000, 0x00011275, - 0xd7610000, 0x00011476, - 0xd7610000, 0x00011677, - 0xd7610000, 0x00011a79, - 0xd7610000, 0x00011c7e, - 0xd7610000, 0x00011e7f, - 0xbefe00ff, 0x00003fff, - 0xbeff0080, 0xee0a407a, - 0x000c0000, 0x00000000, - 0xd760007a, 0x00011d00, - 0xd760007b, 0x00011f00, + 0xbefe00c1, 0xbeff00c1, + 0xee0a407a, 0x000c0000, + 0x00000000, 0x7e000280, 0xbefe007a, 0xbeff007b, - 0xbef4007e, 0x8b75ff7f, - 0x0000ffff, 0xbef1007d, - 0xb8f30742, 0x84739973, - 0xbefe00c1, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbfa20002, 0xbeff0080, - 0xbfa00002, 0xbeff00c1, - 0xbfa0000a, 0xee0a4074, - 0x008c0000, 0x00008000, - 0xee0a4074, 0x010c0000, + 0xb8fb0742, 0x847b997b, + 0xb8fa3b05, 0x807a817a, + 0xbf0d997b, 0xbfa20002, + 0x847a897a, 0xbfa00001, + 0x847a8a7a, 0x8b7bff7f, + 0x0000ffff, 0x807aff7a, + 0x00000240, 0x807a7e7a, + 0x827b807b, 0xd7610000, + 0x00010870, 0xd7610000, + 0x00010a71, 0xd7610000, + 0x00010c72, 0xd7610000, + 0x00010e73, 0xd7610000, + 0x00011074, 0xd7610000, + 0x00011275, 0xd7610000, + 0x00011476, 0xd7610000, + 0x00011677, 0xd7610000, + 0x00011a79, 0xd7610000, + 0x00011c7e, 0xd7610000, + 0x00011e7f, 0xbefe00ff, + 0x00003fff, 0xbeff0080, + 0xee0a407a, 0x000c0000, + 0x00000000, 0xd760007a, + 0x00011d00, 0xd760007b, + 0x00011f00, 0xbefe007a, + 0xbeff007b, 0xbef4007e, + 0x8b75ff7f, 0x0000ffff, + 0xbef1007d, 0xb8f30742, + 0x84739973, 0xbefe00c1, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00002, + 0xbeff00c1, 0xbfa0000a, + 0xee0a4074, 0x008c0000, + 0x00008000, 0xee0a4074, + 0x010c0000, 0x00010000, + 0xee0a4074, 0x018c0000, + 0x00018000, 0xbfa00009, + 0xee0a4074, 0x008c0000, 0x00010000, 0xee0a4074, - 0x018c0000, 0x00018000, - 0xbfa00009, 0xee0a4074, - 0x008c0000, 0x00010000, - 0xee0a4074, 0x010c0000, - 0x00020000, 0xee0a4074, - 0x018c0000, 0x00030000, - 0xb8f03b05, 0x80708170, - 0xbf0d9973, 0xbfa20002, - 0x84708970, 0xbfa00001, - 0x84708a70, 0x8070ff70, - 0x00000200, 0x7e000280, - 0x7e020280, 0x7e040280, - 0xbefd0080, 0xd7610002, - 0x0000fa71, 0x807d817d, - 0xbe804ec2, 0xbf94fffe, - 0xb8faf804, 0x8b7a847a, - 0x91788478, 0x8c787a78, - 0xd7610002, 0x0000fa6c, - 0x807d817d, 0x8b7aff6d, - 0x0000ffff, 0xd7610002, - 0x0000fa7a, 0x807d817d, - 0xd7610002, 0x0000fa6e, - 0x807d817d, 0xd7610002, - 0x0000fa6f, 0x807d817d, - 0xd7610002, 0x0000fa78, - 0x807d817d, 0xb8faf811, - 0xd7610002, 0x0000fa7a, - 0x807d817d, 0xbefa0080, - 0xd7610002, 0x0000fa7a, - 0x807d817d, 0xb8f1f801, - 0xd7610002, 0x0000fa71, - 0x807d817d, 0xb8f1f814, - 0xd7610002, 0x0000fa71, - 0x807d817d, 0xb8f1f815, - 0xd7610002, 0x0000fa71, - 0x807d817d, 0xb8f1f812, - 0xd7610002, 0x0000fa71, - 0x807d817d, 0xb8f1f813, - 0xd7610002, 0x0000fa71, - 0x807d817d, 0xb8faf802, - 0xd7610002, 0x0000fa7a, - 0x807d817d, 0xbefa50c1, - 0xbfc70000, 0xd7610002, - 0x0000fa7a, 0x807d817d, - 0xbefe00ff, 0x0000ffff, - 0xbeff0080, 0x80767074, - 0x82778075, 0xee0a4076, - 0x010c0000, 0x00000000, - 0xbefe00c1, 0xb8f03b05, + 0x010c0000, 0x00020000, + 0xee0a4074, 0x018c0000, + 0x00030000, 0xb8f03b05, 0x80708170, 0xbf0d9973, 0xbfa20002, 0x84708970, 0xbfa00001, 0x84708a70, - 0xbef90080, 0xbefd0080, - 0xbf800000, 0xbe804100, - 0xbe824102, 0xbe844104, - 0xbe864106, 0xbe884108, - 0xbe8a410a, 0xbe8c410c, - 0xbe8e410e, 0xd7610002, - 0x0000f200, 0x80798179, - 0xd7610002, 0x0000f201, - 0x80798179, 0xd7610002, - 0x0000f202, 0x80798179, - 0xd7610002, 0x0000f203, - 0x80798179, 0xd7610002, - 0x0000f204, 0x80798179, - 0xd7610002, 0x0000f205, - 0x80798179, 0xd7610002, - 0x0000f206, 0x80798179, - 0xd7610002, 0x0000f207, - 0x80798179, 0xd7610002, - 0x0000f208, 0x80798179, - 0xd7610002, 0x0000f209, - 0x80798179, 0xd7610002, - 0x0000f20a, 0x80798179, - 0xd7610002, 0x0000f20b, - 0x80798179, 0xd7610002, - 0x0000f20c, 0x80798179, - 0xd7610002, 0x0000f20d, - 0x80798179, 0xd7610002, - 0x0000f20e, 0x80798179, - 0xd7610002, 0x0000f20f, - 0x80798179, 0xbf06a079, - 0xbfa10009, 0x80767074, - 0x82778075, 0xee0a4076, - 0x010c0000, 0x00000000, - 0x8070ff70, 0x00000080, - 0xbef90080, 0x7e040280, - 0x807d907d, 0xbf0aff7d, - 0x00000060, 0xbfa2ffb9, + 0x8070ff70, 0x00000200, + 0x7e000280, 0x7e020280, + 0x7e040280, 0xbefd0080, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xbe804ec2, + 0xbf94fffe, 0xb8faf804, + 0x8b7a847a, 0x91788478, + 0x8c787a78, 0xd7610002, + 0x0000fa6c, 0x807d817d, + 0x8b7aff6d, 0x0000ffff, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xd7610002, + 0x0000fa6e, 0x807d817d, + 0xd7610002, 0x0000fa6f, + 0x807d817d, 0xd7610002, + 0x0000fa78, 0x807d817d, + 0xb8faf811, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xbefa0080, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xb8f1f801, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f814, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f815, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f812, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f813, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8faf802, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xbefa50c1, 0xbfc70000, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xbefe00ff, + 0x0000ffff, 0xbeff0080, + 0x80767074, 0x82778075, + 0xee0a4076, 0x010c0000, + 0x00000000, 0xbefe00c1, + 0xb8f03b05, 0x80708170, + 0xbf0d9973, 0xbfa20002, + 0x84708970, 0xbfa00001, + 0x84708a70, 0xbef90080, + 0xbefd0080, 0xbf800000, 0xbe804100, 0xbe824102, 0xbe844104, 0xbe864106, 0xbe884108, 0xbe8a410a, + 0xbe8c410c, 0xbe8e410e, 0xd7610002, 0x0000f200, 0x80798179, 0xd7610002, 0x0000f201, 0x80798179, @@ -3909,38 +3883,62 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xd7610002, 0x0000f20a, 0x80798179, 0xd7610002, 0x0000f20b, 0x80798179, + 0xd7610002, 0x0000f20c, + 0x80798179, 0xd7610002, + 0x0000f20d, 0x80798179, + 0xd7610002, 0x0000f20e, + 0x80798179, 0xd7610002, + 0x0000f20f, 0x80798179, + 0xbf06a079, 0xbfa10009, 0x80767074, 0x82778075, 0xee0a4076, 0x010c0000, - 0x00000000, 0xbefe00c1, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa20002, - 0xbeff0080, 0xbfa00001, - 0xbeff00c1, 0xb8fb4306, - 0x8b7bc17b, 0xbfa10042, - 0x8b7aff6d, 0x80000000, - 0xbfa1003f, 0x847b897b, - 0xb8f03b05, 0x80708170, - 0xbf0d9973, 0xbfa20002, - 0x84708970, 0xbfa00001, - 0x84708a70, 0x8070ff70, - 0x00000200, 0x8070ff70, - 0x00000080, 0xd71f0000, - 0x000100c1, 0xd7200000, - 0x000200c1, 0x16000084, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbefd0080, - 0xbfa20015, 0xbe8300ff, - 0x00000080, 0xbf800000, - 0xbf800000, 0xbf800000, - 0xd8d80000, 0x01000000, - 0xbf8a0000, 0x80767074, - 0x82778075, 0xee0a4076, - 0x008c0000, 0x00000000, - 0x807d037d, 0x80700370, - 0xd5250000, 0x0001ff00, - 0x00000080, 0xbf0a7b7d, - 0xbfa2fff1, 0xbfa00014, - 0xbe8300ff, 0x00000100, + 0x00000000, 0x8070ff70, + 0x00000080, 0xbef90080, + 0x7e040280, 0x807d907d, + 0xbf0aff7d, 0x00000060, + 0xbfa2ffb9, 0xbe804100, + 0xbe824102, 0xbe844104, + 0xbe864106, 0xbe884108, + 0xbe8a410a, 0xd7610002, + 0x0000f200, 0x80798179, + 0xd7610002, 0x0000f201, + 0x80798179, 0xd7610002, + 0x0000f202, 0x80798179, + 0xd7610002, 0x0000f203, + 0x80798179, 0xd7610002, + 0x0000f204, 0x80798179, + 0xd7610002, 0x0000f205, + 0x80798179, 0xd7610002, + 0x0000f206, 0x80798179, + 0xd7610002, 0x0000f207, + 0x80798179, 0xd7610002, + 0x0000f208, 0x80798179, + 0xd7610002, 0x0000f209, + 0x80798179, 0xd7610002, + 0x0000f20a, 0x80798179, + 0xd7610002, 0x0000f20b, + 0x80798179, 0x80767074, + 0x82778075, 0xee0a4076, + 0x010c0000, 0x00000000, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20002, 0xbeff0080, + 0xbfa00001, 0xbeff00c1, + 0xb8fb4306, 0x8b7bc17b, + 0xbfa10042, 0x8b7aff6d, + 0x80000000, 0xbfa1003f, + 0x847b897b, 0xb8f03b05, + 0x80708170, 0xbf0d9973, + 0xbfa20002, 0x84708970, + 0xbfa00001, 0x84708a70, + 0x8070ff70, 0x00000200, + 0x8070ff70, 0x00000080, + 0xd71f0000, 0x000100c1, + 0xd7200000, 0x000200c1, + 0x16000084, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbefd0080, 0xbfa20015, + 0xbe8300ff, 0x00000080, 0xbf800000, 0xbf800000, 0xbf800000, 0xd8d80000, 0x01000000, 0xbf8a0000, @@ -3948,215 +3946,225 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xee0a4076, 0x008c0000, 0x00000000, 0x807d037d, 0x80700370, 0xd5250000, - 0x0001ff00, 0x00000100, + 0x0001ff00, 0x00000080, 0xbf0a7b7d, 0xbfa2fff1, - 0xbefe00c1, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbfa20004, 0xbef000ff, - 0x00000200, 0xbeff0080, - 0xbfa00003, 0xbef000ff, - 0x00000400, 0xbeff00c1, - 0xb8fb3b05, 0x807b817b, - 0x847b827b, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbfa2001b, 0xbefd0084, - 0xbf0a7b7d, 0xbfa10032, - 0x7e008700, 0x7e028701, - 0x7e048702, 0x7e068703, - 0x80767074, 0x82778075, - 0xee0a4076, 0x000c0000, - 0x00000000, 0xee0a4076, - 0x008c0000, 0x00008000, - 0xee0a4076, 0x010c0000, - 0x00010000, 0xee0a4076, - 0x018c0000, 0x00018000, - 0x807d847d, 0x8070ff70, - 0x00000200, 0xbf0a7b7d, - 0xbfa2ffe9, 0xbfa0001a, + 0xbfa00014, 0xbe8300ff, + 0x00000100, 0xbf800000, + 0xbf800000, 0xbf800000, + 0xd8d80000, 0x01000000, + 0xbf8a0000, 0x80767074, + 0x82778075, 0xee0a4076, + 0x008c0000, 0x00000000, + 0x807d037d, 0x80700370, + 0xd5250000, 0x0001ff00, + 0x00000100, 0xbf0a7b7d, + 0xbfa2fff1, 0xbefe00c1, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbfa20004, + 0xbef000ff, 0x00000200, + 0xbeff0080, 0xbfa00003, + 0xbef000ff, 0x00000400, + 0xbeff00c1, 0xb8fb3b05, + 0x807b817b, 0x847b827b, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbfa2001b, 0xbefd0084, 0xbf0a7b7d, - 0xbfa10017, 0x7e008700, + 0xbfa10032, 0x7e008700, 0x7e028701, 0x7e048702, 0x7e068703, 0x80767074, 0x82778075, 0xee0a4076, 0x000c0000, 0x00000000, 0xee0a4076, 0x008c0000, - 0x00010000, 0xee0a4076, - 0x010c0000, 0x00020000, + 0x00008000, 0xee0a4076, + 0x010c0000, 0x00010000, 0xee0a4076, 0x018c0000, - 0x00030000, 0x807d847d, - 0x8070ff70, 0x00000400, + 0x00018000, 0x807d847d, + 0x8070ff70, 0x00000200, 0xbf0a7b7d, 0xbfa2ffe9, - 0xbfa0014c, 0xbef4007e, - 0x8b75ff7f, 0x0000ffff, - 0xbef1007f, 0xb8f20742, - 0x84729972, 0x8b6eff7f, - 0x04000000, 0xbfa10044, + 0xbfa0001a, 0xbefd0084, + 0xbf0a7b7d, 0xbfa10017, + 0x7e008700, 0x7e028701, + 0x7e048702, 0x7e068703, + 0x80767074, 0x82778075, + 0xee0a4076, 0x000c0000, + 0x00000000, 0xee0a4076, + 0x008c0000, 0x00010000, + 0xee0a4076, 0x010c0000, + 0x00020000, 0xee0a4076, + 0x018c0000, 0x00030000, + 0x807d847d, 0x8070ff70, + 0x00000400, 0xbf0a7b7d, + 0xbfa2ffe9, 0xbfa0014c, + 0xbef4007e, 0x8b75ff7f, + 0x0000ffff, 0xbef1007f, + 0xb8f20742, 0x84729972, + 0x8b6eff7f, 0x04000000, + 0xbfa10044, 0xbefe00c1, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8ef4306, + 0x8b6fc16f, 0xbfa10039, + 0x846f896f, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0x8078ff78, 0x00000200, + 0x8078ff78, 0x00000080, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbefd0080, + 0xd71f0001, 0x000100c1, + 0xd7200001, 0x000202c1, + 0x30020282, 0xbfa20012, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xbf8a0000, + 0xd8340000, 0x00000001, + 0xd5250001, 0x0001ff01, + 0x00000080, 0x807dff7d, + 0x00000080, 0x8078ff78, + 0x00000080, 0xbf0a6f7d, + 0xbfa2ffef, 0xbfa00011, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xbf8a0000, + 0xd8340000, 0x00000001, + 0xd5250001, 0x0001ff01, + 0x00000100, 0x807dff7d, + 0x00000100, 0x8078ff78, + 0x00000100, 0xbf0a6f7d, + 0xbfa2ffef, 0xbef80080, 0xbefe00c1, 0x857d9972, 0x8b7d817d, 0xbf06817d, 0xbfa20002, 0xbeff0080, 0xbfa00001, 0xbeff00c1, - 0xb8ef4306, 0x8b6fc16f, - 0xbfa10039, 0x846f896f, - 0xb8f83b05, 0x80788178, - 0xbf0d9972, 0xbfa20002, - 0x84788978, 0xbfa00001, - 0x84788a78, 0x8078ff78, - 0x00000200, 0x8078ff78, - 0x00000080, 0x857d9972, + 0xb8ef3b05, 0x806f816f, + 0x846f826f, 0x857d9972, 0x8b7d817d, 0xbf06817d, - 0xbefd0080, 0xd71f0001, - 0x000100c1, 0xd7200001, - 0x000202c1, 0x30020282, - 0xbfa20012, 0x80767874, + 0xbfa2002c, 0xbeee0078, + 0x8078ff78, 0x00000200, + 0xbefd0084, 0x80767874, 0x82778075, 0xee0a0076, 0x000c0000, 0x00000000, - 0xbf8a0000, 0xd8340000, - 0x00000001, 0xd5250001, - 0x0001ff01, 0x00000080, - 0x807dff7d, 0x00000080, - 0x8078ff78, 0x00000080, - 0xbf0a6f7d, 0xbfa2ffef, - 0xbfa00011, 0x80767874, + 0xee0a0076, 0x000c0001, + 0x00008000, 0xee0a0076, + 0x000c0002, 0x00010000, + 0xee0a0076, 0x000c0003, + 0x00018000, 0xbf8a0000, + 0x7e008500, 0x7e028501, + 0x7e048502, 0x7e068503, + 0x807d847d, 0x8078ff78, + 0x00000200, 0xbf0a6f7d, + 0xbfa2ffe8, 0x80766e74, 0x82778075, 0xee0a0076, 0x000c0000, 0x00000000, - 0xbf8a0000, 0xd8340000, - 0x00000001, 0xd5250001, - 0x0001ff01, 0x00000100, - 0x807dff7d, 0x00000100, - 0x8078ff78, 0x00000100, - 0xbf0a6f7d, 0xbfa2ffef, - 0xbef80080, 0xbefe00c1, - 0x857d9972, 0x8b7d817d, - 0xbf06817d, 0xbfa20002, - 0xbeff0080, 0xbfa00001, - 0xbeff00c1, 0xb8ef3b05, - 0x806f816f, 0x846f826f, - 0x857d9972, 0x8b7d817d, - 0xbf06817d, 0xbfa2002c, - 0xbeee0078, 0x8078ff78, - 0x00000200, 0xbefd0084, - 0x80767874, 0x82778075, - 0xee0a0076, 0x000c0000, - 0x00000000, 0xee0a0076, - 0x000c0001, 0x00008000, - 0xee0a0076, 0x000c0002, + 0xee0a0076, 0x000c0001, + 0x00008000, 0xee0a0076, + 0x000c0002, 0x00010000, + 0xee0a0076, 0x000c0003, + 0x00018000, 0xbf8a0000, + 0xbfa0002d, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefd0084, 0xbf0a6f7d, + 0xbfa10018, 0x80767874, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xee0a0076, 0x000c0001, 0x00010000, 0xee0a0076, - 0x000c0003, 0x00018000, - 0xbf8a0000, 0x7e008500, - 0x7e028501, 0x7e048502, - 0x7e068503, 0x807d847d, - 0x8078ff78, 0x00000200, - 0xbf0a6f7d, 0xbfa2ffe8, - 0x80766e74, 0x82778075, - 0xee0a0076, 0x000c0000, - 0x00000000, 0xee0a0076, - 0x000c0001, 0x00008000, - 0xee0a0076, 0x000c0002, + 0x000c0002, 0x00020000, + 0xee0a0076, 0x000c0003, + 0x00030000, 0xbf8a0000, + 0x7e008500, 0x7e028501, + 0x7e048502, 0x7e068503, + 0x807d847d, 0x8078ff78, + 0x00000400, 0xbf0a6f7d, + 0xbfa2ffe8, 0x80766e74, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xee0a0076, 0x000c0001, 0x00010000, 0xee0a0076, - 0x000c0003, 0x00018000, - 0xbf8a0000, 0xbfa0002d, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefd0084, - 0xbf0a6f7d, 0xbfa10018, - 0x80767874, 0x82778075, - 0xee0a0076, 0x000c0000, - 0x00000000, 0xee0a0076, - 0x000c0001, 0x00010000, - 0xee0a0076, 0x000c0002, - 0x00020000, 0xee0a0076, - 0x000c0003, 0x00030000, - 0xbf8a0000, 0x7e008500, - 0x7e028501, 0x7e048502, - 0x7e068503, 0x807d847d, - 0x8078ff78, 0x00000400, - 0xbf0a6f7d, 0xbfa2ffe8, - 0x80766e74, 0x82778075, - 0xee0a0076, 0x000c0000, - 0x00000000, 0xee0a0076, - 0x000c0001, 0x00010000, - 0xee0a0076, 0x000c0002, - 0x00020000, 0xee0a0076, - 0x000c0003, 0x00030000, - 0xbf8a0000, 0xb8f83b05, - 0x80788178, 0xbf0d9972, - 0xbfa20002, 0x84788978, - 0xbfa00001, 0x84788a78, - 0x8078ff78, 0x00000200, - 0x80f8ff78, 0x00000060, - 0x80767874, 0x82778075, - 0xbefd00ff, 0x0000006c, - 0xf460403b, 0xf8000000, - 0xbf8a0000, 0x80fd847d, - 0xbf800000, 0xbe804300, - 0xbe824302, 0x80f6a076, - 0x82f78077, 0xf460603b, + 0x000c0002, 0x00020000, + 0xee0a0076, 0x000c0003, + 0x00030000, 0xbf8a0000, + 0xb8f83b05, 0x80788178, + 0xbf0d9972, 0xbfa20002, + 0x84788978, 0xbfa00001, + 0x84788a78, 0x8078ff78, + 0x00000200, 0x80f8ff78, + 0x00000060, 0x80767874, + 0x82778075, 0xbefd00ff, + 0x0000006c, 0xf460403b, 0xf8000000, 0xbf8a0000, - 0x80fd887d, 0xbf800000, + 0x80fd847d, 0xbf800000, 0xbe804300, 0xbe824302, - 0xbe844304, 0xbe864306, - 0x80f6c076, 0x82f78077, - 0xf460803b, 0xf8000000, - 0xbf8a0000, 0x80fd907d, + 0x80f6a076, 0x82f78077, + 0xf460603b, 0xf8000000, + 0xbf8a0000, 0x80fd887d, 0xbf800000, 0xbe804300, 0xbe824302, 0xbe844304, - 0xbe864306, 0xbe884308, - 0xbe8a430a, 0xbe8c430c, - 0xbe8e430e, 0xbf06807d, - 0xbfa1ffef, 0xb980f801, - 0x00000000, 0xb8f83b05, - 0x80788178, 0xbf0d9972, - 0xbfa20002, 0x84788978, - 0xbfa00001, 0x84788a78, - 0x8078ff78, 0x00000200, - 0x80767874, 0x82778075, - 0xbeff0071, 0xf4601bfb, - 0xf8000000, 0xf4601b3b, - 0xf8000004, 0xf4601b7b, - 0xf8000008, 0xf4601c3b, - 0xf800000c, 0xf4601c7b, - 0xf8000010, 0xf4601ebb, - 0xf8000014, 0xf4601efb, - 0xf8000018, 0xf4601e7b, - 0xf800001c, 0xf4601cfb, - 0xf8000020, 0xf4601bbb, - 0xf8000024, 0xbf8a0000, - 0xb96ef814, 0xf4601bbb, - 0xf8000028, 0xbf8a0000, - 0xb96ef815, 0xf4601bbb, - 0xf800002c, 0xbf8a0000, - 0xb96ef812, 0xf4601bbb, - 0xf8000030, 0xbf8a0000, - 0xb96ef813, 0x8b6eff7f, - 0x04000000, 0xbfa1000b, - 0xf4601bbb, 0xf8000038, - 0xbf8a0000, 0xbf0d806e, - 0xbfa10006, 0x856e906e, - 0x8b6e6e6e, 0xbfa10003, - 0xbe804ec1, 0x816ec16e, - 0xbfa0fffb, 0xbefd006f, - 0xbefe0070, 0xbeff0071, - 0xb97b2011, 0x857b867b, - 0xb97b0191, 0x857b827b, - 0xb97bba11, 0xb973f801, - 0xb8ee3b05, 0x806e816e, + 0xbe864306, 0x80f6c076, + 0x82f78077, 0xf460803b, + 0xf8000000, 0xbf8a0000, + 0x80fd907d, 0xbf800000, + 0xbe804300, 0xbe824302, + 0xbe844304, 0xbe864306, + 0xbe884308, 0xbe8a430a, + 0xbe8c430c, 0xbe8e430e, + 0xbf06807d, 0xbfa1ffef, + 0xb980f801, 0x00000000, + 0xb8f83b05, 0x80788178, 0xbf0d9972, 0xbfa20002, - 0x846e896e, 0xbfa00001, - 0x846e8a6e, 0x806eff6e, - 0x00000240, 0x806e746e, - 0x826f8075, 0xf4605c37, - 0xf8000010, 0xf4605d37, - 0xf8000020, 0xf4601e77, - 0xf8000034, 0xbf8a0000, - 0x8b6dff6d, 0x0000ffff, - 0x8bfe7e7e, 0x8bea6a6a, - 0x936eff77, 0x0002001a, - 0xb96ef81a, 0xb97af804, + 0x84788978, 0xbfa00001, + 0x84788a78, 0x8078ff78, + 0x00000200, 0x80767874, + 0x82778075, 0xbeff0071, + 0xf4601bfb, 0xf8000000, + 0xf4601b3b, 0xf8000004, + 0xf4601b7b, 0xf8000008, + 0xf4601c3b, 0xf800000c, + 0xf4601c7b, 0xf8000010, + 0xf4601ebb, 0xf8000014, + 0xf4601efb, 0xf8000018, + 0xf4601e7b, 0xf800001c, + 0xf4601cfb, 0xf8000020, + 0xf4601bbb, 0xf8000024, + 0xbf8a0000, 0xb96ef814, + 0xf4601bbb, 0xf8000028, + 0xbf8a0000, 0xb96ef815, + 0xf4601bbb, 0xf800002c, + 0xbf8a0000, 0xb96ef812, + 0xf4601bbb, 0xf8000030, + 0xbf8a0000, 0xb96ef813, + 0x8b6eff7f, 0x04000000, + 0xbfa1000b, 0xf4601bbb, + 0xf8000038, 0xbf8a0000, + 0xbf0d806e, 0xbfa10006, + 0x856e906e, 0x8b6e6e6e, + 0xbfa10003, 0xbe804ec1, + 0x816ec16e, 0xbfa0fffb, + 0xbefd006f, 0xbefe0070, + 0xbeff0071, 0xb97b2011, + 0x857b867b, 0xb97b0191, + 0x857b827b, 0xb97bba11, + 0xb973f801, 0xb8ee3b05, + 0x806e816e, 0xbf0d9972, + 0xbfa20002, 0x846e896e, + 0xbfa00001, 0x846e8a6e, + 0x806eff6e, 0x00000240, + 0x806e746e, 0x826f8075, + 0xf4605c37, 0xf8000010, + 0xf4605d37, 0xf8000020, + 0xf4601e77, 0xf8000034, + 0xbf8a0000, 0x8b6dff6d, + 0x0000ffff, 0x8bfe7e7e, + 0x8bea6a6a, 0x936eff77, + 0x0002001a, 0xb96ef81a, + 0xb97af804, 0xbe804ec2, + 0xbf94fffe, 0xbe804a6c, 0xbe804ec2, 0xbf94fffe, - 0xbe804a6c, 0xbe804ec2, - 0xbf94fffe, 0xbfb10000, + 0xbfb10000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, - 0xbf9f0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { @@ -4668,14 +4676,16 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { - 0xbfa00001, 0xbfa003be, + 0xbfa00001, 0xbfa003cb, 0xb0804009, 0xb8f8f804, 0x9178ff78, 0x00008c00, - 0xb8fbf811, 0x8b6eff78, - 0x00004000, 0xbfa10008, - 0x8b6eff7b, 0x00000080, + 0xb8fbf811, 0xbf0c857b, + 0xbfa20003, 0xbefb1087, + 0xb98001d1, 0x00000000, + 0x8b6eff78, 0x00004000, + 0xbfa10007, 0xbf0d877b, 0xbfa20018, 0x8b6ea07b, - 0xbfa200da, 0xbf830010, + 0xbfa200e3, 0xbf830010, 0xb8fbf811, 0xbfa0fffb, 0x8b6eff7b, 0x00000bd0, 0xbfa20010, 0xb8eef812, @@ -4686,337 +4696,376 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xf0000000, 0xbfa20005, 0x8b6fff6f, 0x00000200, 0xbfa20002, 0x8b6ea07b, - 0xbfa200c4, 0x9177ff77, + 0xbfa200cd, 0x9177ff77, 0x007fc000, 0xb8fa04a1, 0x847a967a, 0x8c777a77, 0xb8fa0421, 0x847a957a, 0x8c777a77, 0xb8fa3021, 0x847a8e7a, 0x8c777a77, 0xb980f821, 0x00000000, - 0xbefa4d82, 0xbf8a0000, - 0x84fa887a, 0xbf0d987b, - 0xbfa10002, 0x8c7bff7b, - 0xfe000000, 0xf4601bbd, - 0xf8000010, 0xbf8a0000, - 0x846e976e, 0x9177ff77, - 0x00800000, 0x8c776e77, - 0xf4603bbd, 0xf8000000, - 0xbf8a0000, 0xf4603ebd, - 0xf8000008, 0xbf8a0000, - 0x8bee6e6e, 0xbfa10001, - 0xbe80486e, 0x8b6eff6d, - 0xf0000000, 0xbfa20009, - 0xb8eef811, 0x8b6eff6e, - 0x00000080, 0xbfa20007, - 0x8c78ff78, 0x00004000, - 0x80ec886c, 0x82ed806d, - 0xbfa00002, 0x806c846c, - 0x826d806d, 0x8b6dff6d, - 0x01ffffff, 0xb8fbf811, - 0xbf0d847b, 0xbfa20081, - 0xf4003eb6, 0xf8000000, - 0xbfc70000, 0xf4003bb6, - 0xf8000008, 0x8b76ff7a, - 0x80000000, 0xbfa20027, - 0x9376ff7a, 0x00060019, - 0x81f9a376, 0xbf0b8179, - 0xbfa2006e, 0x81f9ac76, - 0xbf0b8179, 0xbfa20068, - 0x81f9b776, 0xbf0b8179, - 0xbfa20065, 0x8b76ff7a, - 0x000001ff, 0xbf06ff76, - 0x000000fe, 0xbfa20063, - 0xbf06ff76, 0x000000ff, - 0xbfa2005d, 0xbf06ff76, - 0x000000fa, 0xbfa2005a, - 0x81f9ff76, 0x000000e9, - 0xbf0b8179, 0xbfa20056, - 0x8b76ff7b, 0xffff0000, - 0xbf06ff76, 0xbf860000, - 0xbfa1005a, 0x9376ff7b, - 0x0002000e, 0x8b79ff7b, - 0x00003f00, 0x85798679, - 0x8c767976, 0xb9763b01, - 0xbfa00052, 0x8b76ff7a, - 0xfc000000, 0xbf06ff76, - 0xd4000000, 0xbfa20019, - 0xbf06ff76, 0xc8000000, - 0xbfa2002d, 0x8b76ff7a, - 0xff000000, 0xbf06ff76, - 0xcf000000, 0xbfa2003f, - 0x8b79ff7a, 0xffff0000, - 0xbf06ff79, 0xcc330000, - 0xbfa2003d, 0xbf06ff79, - 0xcc880000, 0xbfa2003a, - 0xbf06ff79, 0xcc350000, - 0xbfa2003a, 0xbf06ff79, - 0xcc3a0000, 0xbfa20037, - 0xbf06ff76, 0xcc000000, - 0xbfa10034, 0x8b76ff7b, - 0x000001ff, 0xbf06ff76, - 0x000000ff, 0xbfa20029, - 0xbf06ff76, 0x000000fa, - 0xbfa20026, 0x81f6ff76, - 0x000000e9, 0xbf0b8176, - 0xbfa20022, 0x8b76ff7b, - 0x0003fe00, 0xbf06ff76, - 0x0001fe00, 0xbfa2001d, - 0x8b76ff7b, 0x07fc0000, - 0xbf06ff76, 0x03fc0000, - 0xbfa20018, 0xbfa00014, - 0x9376ff7a, 0x00040016, - 0x81f68176, 0xbf0b8176, - 0xbfa20012, 0x9376ff7a, - 0x00050011, 0x81f68176, - 0xbf0b8176, 0xbfa2000d, + 0xbeef007b, 0xbefa4d82, + 0xbf8a0000, 0x84fa887a, + 0xbf0d987b, 0xbfa10002, + 0x8c7bff7b, 0xfe000000, + 0xf4601bbd, 0xf8000010, + 0xbf8a0000, 0x846e976e, + 0x9177ff77, 0x01800000, + 0x8c776e77, 0xbf0d876f, + 0xbfa10006, 0xbf0d8e78, + 0xbfa20002, 0xbf0d9877, + 0xbfa20002, 0xb98001d1, + 0x00000000, 0xf4603bbd, + 0xf8000000, 0xbf8a0000, + 0xf4603ebd, 0xf8000008, + 0xbf8a0000, 0x8bee6e6e, + 0xbfa10001, 0xbe80486e, + 0x8b6eff6d, 0xf0000000, + 0xbfa20009, 0xb8eef811, + 0x8b6eff6e, 0x00000080, + 0xbfa20007, 0x8c78ff78, + 0x00004000, 0x80ec886c, + 0x82ed806d, 0xbfa00002, + 0x806c846c, 0x826d806d, + 0x8b6dff6d, 0x01ffffff, + 0xb8fbf811, 0xbf0d847b, + 0xbfa20081, 0xf4003eb6, + 0xf8000000, 0xbfc70000, + 0xf4003bb6, 0xf8000008, + 0x8b76ff7a, 0x80000000, + 0xbfa20027, 0x9376ff7a, + 0x00060019, 0x81f9a376, + 0xbf0b8179, 0xbfa2006e, + 0x81f9ac76, 0xbf0b8179, + 0xbfa20068, 0x81f9b776, + 0xbf0b8179, 0xbfa20065, 0x8b76ff7a, 0x000001ff, + 0xbf06ff76, 0x000000fe, + 0xbfa20063, 0xbf06ff76, + 0x000000ff, 0xbfa2005d, + 0xbf06ff76, 0x000000fa, + 0xbfa2005a, 0x81f9ff76, + 0x000000e9, 0xbf0b8179, + 0xbfa20056, 0x8b76ff7b, + 0xffff0000, 0xbf06ff76, + 0xbf860000, 0xbfa1005a, + 0x9376ff7b, 0x0002000e, + 0x8b79ff7b, 0x00003f00, + 0x85798679, 0x8c767976, + 0xb9763b01, 0xbfa00052, + 0x8b76ff7a, 0xfc000000, + 0xbf06ff76, 0xd4000000, + 0xbfa20019, 0xbf06ff76, + 0xc8000000, 0xbfa2002d, + 0x8b76ff7a, 0xff000000, + 0xbf06ff76, 0xcf000000, + 0xbfa2003f, 0x8b79ff7a, + 0xffff0000, 0xbf06ff79, + 0xcc330000, 0xbfa2003d, + 0xbf06ff79, 0xcc880000, + 0xbfa2003a, 0xbf06ff79, + 0xcc350000, 0xbfa2003a, + 0xbf06ff79, 0xcc3a0000, + 0xbfa20037, 0xbf06ff76, + 0xcc000000, 0xbfa10034, + 0x8b76ff7b, 0x000001ff, 0xbf06ff76, 0x000000ff, - 0xbfa20008, 0x8b76ff7b, - 0x000001ff, 0xbf06ff76, - 0x000000ff, 0xbfa20003, - 0xbfc70000, 0xbefb006e, - 0xbfa0ffa7, 0xbfc70000, - 0xbefb006f, 0xbfa0ffa4, - 0x80ec886c, 0x82ed806d, - 0xbfa0fff7, 0xbfc70000, - 0x857a9677, 0xb97a04a1, - 0x857a9577, 0xb97a0421, - 0x857a8e77, 0xb97a3021, - 0x8bfe7e7e, 0x8bea6a6a, - 0x85788978, 0xb9783244, - 0xbe804a6c, 0xb8faf802, - 0xbf0d987a, 0xbfa10001, - 0xbfb00000, 0x8b6dff6d, - 0x01ffffff, 0xbefa0080, - 0xb97a0151, 0x9177ff77, - 0x007fc000, 0xb8fa04a1, - 0x847a967a, 0x8c777a77, - 0xb8fa0421, 0x847a957a, - 0x8c777a77, 0xb8fa3021, - 0x847a8e7a, 0x8c777a77, - 0xb980f821, 0x00000000, - 0xbf0d847b, 0xbfa20081, - 0xf4003eb6, 0xf8000000, - 0xbfc70000, 0xf4003bb6, - 0xf8000008, 0x8b76ff7a, - 0x80000000, 0xbfa20027, - 0x9376ff7a, 0x00060019, - 0x81f9a376, 0xbf0b8179, - 0xbfa2006e, 0x81f9ac76, - 0xbf0b8179, 0xbfa20068, - 0x81f9b776, 0xbf0b8179, - 0xbfa20065, 0x8b76ff7a, + 0xbfa20029, 0xbf06ff76, + 0x000000fa, 0xbfa20026, + 0x81f6ff76, 0x000000e9, + 0xbf0b8176, 0xbfa20022, + 0x8b76ff7b, 0x0003fe00, + 0xbf06ff76, 0x0001fe00, + 0xbfa2001d, 0x8b76ff7b, + 0x07fc0000, 0xbf06ff76, + 0x03fc0000, 0xbfa20018, + 0xbfa00014, 0x9376ff7a, + 0x00040016, 0x81f68176, + 0xbf0b8176, 0xbfa20012, + 0x9376ff7a, 0x00050011, + 0x81f68176, 0xbf0b8176, + 0xbfa2000d, 0x8b76ff7a, 0x000001ff, 0xbf06ff76, - 0x000000fe, 0xbfa20063, + 0x000000ff, 0xbfa20008, + 0x8b76ff7b, 0x000001ff, 0xbf06ff76, 0x000000ff, - 0xbfa2005d, 0xbf06ff76, - 0x000000fa, 0xbfa2005a, - 0x81f9ff76, 0x000000e9, - 0xbf0b8179, 0xbfa20056, - 0x8b76ff7b, 0xffff0000, - 0xbf06ff76, 0xbf860000, - 0xbfa1005a, 0x9376ff7b, - 0x0002000e, 0x8b79ff7b, - 0x00003f00, 0x85798679, - 0x8c767976, 0xb9763b01, - 0xbfa00052, 0x8b76ff7a, - 0xfc000000, 0xbf06ff76, - 0xd4000000, 0xbfa20019, - 0xbf06ff76, 0xc8000000, - 0xbfa2002d, 0x8b76ff7a, - 0xff000000, 0xbf06ff76, - 0xcf000000, 0xbfa2003f, - 0x8b79ff7a, 0xffff0000, - 0xbf06ff79, 0xcc330000, - 0xbfa2003d, 0xbf06ff79, - 0xcc880000, 0xbfa2003a, - 0xbf06ff79, 0xcc350000, - 0xbfa2003a, 0xbf06ff79, - 0xcc3a0000, 0xbfa20037, - 0xbf06ff76, 0xcc000000, - 0xbfa10034, 0x8b76ff7b, - 0x000001ff, 0xbf06ff76, - 0x000000ff, 0xbfa20029, - 0xbf06ff76, 0x000000fa, - 0xbfa20026, 0x81f6ff76, - 0x000000e9, 0xbf0b8176, - 0xbfa20022, 0x8b76ff7b, - 0x0003fe00, 0xbf06ff76, - 0x0001fe00, 0xbfa2001d, - 0x8b76ff7b, 0x07fc0000, - 0xbf06ff76, 0x03fc0000, - 0xbfa20018, 0xbfa00014, - 0x9376ff7a, 0x00040016, - 0x81f68176, 0xbf0b8176, - 0xbfa20012, 0x9376ff7a, - 0x00050011, 0x81f68176, - 0xbf0b8176, 0xbfa2000d, + 0xbfa20003, 0xbfc70000, + 0xbefb006e, 0xbfa0ffa7, + 0xbfc70000, 0xbefb006f, + 0xbfa0ffa4, 0x80ec886c, + 0x82ed806d, 0xbfa0fff7, + 0xbfc70000, 0x857a9677, + 0xb97a04a1, 0x857a9577, + 0xb97a0421, 0x857a8e77, + 0xb97a3021, 0x8bfe7e7e, + 0x8bea6a6a, 0x85788978, + 0xb9783244, 0xbe804a6c, + 0xb8faf802, 0xbf0d987a, + 0xbfa10001, 0xbfb00000, + 0x8b6dff6d, 0x01ffffff, + 0xbefa0080, 0xb97a0151, + 0x9177ff77, 0x007fc000, + 0xb8fa04a1, 0x847a967a, + 0x8c777a77, 0xb8fa0421, + 0x847a957a, 0x8c777a77, + 0xb8fa3021, 0x847a8e7a, + 0x8c777a77, 0xb980f821, + 0x00000000, 0xbf0d847b, + 0xbfa20081, 0xf4003eb6, + 0xf8000000, 0xbfc70000, + 0xf4003bb6, 0xf8000008, + 0x8b76ff7a, 0x80000000, + 0xbfa20027, 0x9376ff7a, + 0x00060019, 0x81f9a376, + 0xbf0b8179, 0xbfa2006e, + 0x81f9ac76, 0xbf0b8179, + 0xbfa20068, 0x81f9b776, + 0xbf0b8179, 0xbfa20065, 0x8b76ff7a, 0x000001ff, + 0xbf06ff76, 0x000000fe, + 0xbfa20063, 0xbf06ff76, + 0x000000ff, 0xbfa2005d, + 0xbf06ff76, 0x000000fa, + 0xbfa2005a, 0x81f9ff76, + 0x000000e9, 0xbf0b8179, + 0xbfa20056, 0x8b76ff7b, + 0xffff0000, 0xbf06ff76, + 0xbf860000, 0xbfa1005a, + 0x9376ff7b, 0x0002000e, + 0x8b79ff7b, 0x00003f00, + 0x85798679, 0x8c767976, + 0xb9763b01, 0xbfa00052, + 0x8b76ff7a, 0xfc000000, + 0xbf06ff76, 0xd4000000, + 0xbfa20019, 0xbf06ff76, + 0xc8000000, 0xbfa2002d, + 0x8b76ff7a, 0xff000000, + 0xbf06ff76, 0xcf000000, + 0xbfa2003f, 0x8b79ff7a, + 0xffff0000, 0xbf06ff79, + 0xcc330000, 0xbfa2003d, + 0xbf06ff79, 0xcc880000, + 0xbfa2003a, 0xbf06ff79, + 0xcc350000, 0xbfa2003a, + 0xbf06ff79, 0xcc3a0000, + 0xbfa20037, 0xbf06ff76, + 0xcc000000, 0xbfa10034, + 0x8b76ff7b, 0x000001ff, 0xbf06ff76, 0x000000ff, - 0xbfa20008, 0x8b76ff7b, + 0xbfa20029, 0xbf06ff76, + 0x000000fa, 0xbfa20026, + 0x81f6ff76, 0x000000e9, + 0xbf0b8176, 0xbfa20022, + 0x8b76ff7b, 0x0003fe00, + 0xbf06ff76, 0x0001fe00, + 0xbfa2001d, 0x8b76ff7b, + 0x07fc0000, 0xbf06ff76, + 0x03fc0000, 0xbfa20018, + 0xbfa00014, 0x9376ff7a, + 0x00040016, 0x81f68176, + 0xbf0b8176, 0xbfa20012, + 0x9376ff7a, 0x00050011, + 0x81f68176, 0xbf0b8176, + 0xbfa2000d, 0x8b76ff7a, 0x000001ff, 0xbf06ff76, - 0x000000ff, 0xbfa20003, - 0xbfc70000, 0xbefb006e, - 0xbfa0ffa7, 0xbfc70000, - 0xbefb006f, 0xbfa0ffa4, - 0x80ec886c, 0x82ed806d, - 0xbfa0fff7, 0xbfc70000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbefe4d84, - 0xbf8a0000, 0x8b7aff7f, - 0x04000000, 0x847a857a, - 0x8c6d7a6d, 0xb8eff822, - 0xb980f822, 0x00000000, - 0xb8fa2b01, 0x847a997a, - 0x8c6d7a6d, 0xbefa0080, - 0xb97a2b01, 0xbefa007e, + 0x000000ff, 0xbfa20008, + 0x8b76ff7b, 0x000001ff, + 0xbf06ff76, 0x000000ff, + 0xbfa20003, 0xbfc70000, + 0xbefb006e, 0xbfa0ffa7, + 0xbfc70000, 0xbefb006f, + 0xbfa0ffa4, 0x80ec886c, + 0x82ed806d, 0xbfa0fff7, + 0xbfc70000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbefe4d84, 0xbf8a0000, + 0x8b7aff7f, 0x04000000, + 0x847a857a, 0x8c6d7a6d, + 0xb8eff822, 0xb980f822, + 0x00000000, 0xb8fa2b01, + 0x847a997a, 0x8c6d7a6d, + 0xbefa0080, 0xb97a2b01, + 0xbefa007e, 0x8b7bff7f, + 0x01ffffff, 0xbefe00c1, + 0xbeff00c1, 0xee0a407a, + 0x000c0000, 0x00000000, + 0x7e000280, 0xbefe007a, + 0xbeff007b, 0xb8fb0742, + 0x847b997b, 0xb8fa3b05, + 0x807a817a, 0xbf0d997b, + 0xbfa20002, 0x847a897a, + 0xbfa00001, 0x847a8a7a, 0x8b7bff7f, 0x01ffffff, - 0xbefe00c1, 0xbeff00c1, - 0xee0a407a, 0x000c0000, - 0x00000000, 0x7e000280, + 0x807aff7a, 0x000001c0, + 0x807a7e7a, 0x827b807b, + 0xd7610000, 0x00010870, + 0xd7610000, 0x00010a71, + 0xd7610000, 0x00010c72, + 0xd7610000, 0x00010e73, + 0xd7610000, 0x00011074, + 0xd7610000, 0x00011275, + 0xd7610000, 0x00011476, + 0xd7610000, 0x00011677, + 0xd7610000, 0x00011a79, + 0xd7610000, 0x00011c7e, + 0xd7610000, 0x00011e7f, + 0xbefe00ff, 0x00003fff, + 0xbeff0080, 0xee0a407a, + 0x000c0000, 0x00000000, + 0xd760007a, 0x00011d00, + 0xd760007b, 0x00011f00, 0xbefe007a, 0xbeff007b, - 0xb8fb0742, 0x847b997b, - 0xb8fa3b05, 0x807a817a, - 0xbf0d997b, 0xbfa20002, - 0x847a897a, 0xbfa00001, - 0x847a8a7a, 0x8b7bff7f, - 0x01ffffff, 0x807aff7a, - 0x000001c0, 0x807a7e7a, - 0x827b807b, 0xd7610000, - 0x00010870, 0xd7610000, - 0x00010a71, 0xd7610000, - 0x00010c72, 0xd7610000, - 0x00010e73, 0xd7610000, - 0x00011074, 0xd7610000, - 0x00011275, 0xd7610000, - 0x00011476, 0xd7610000, - 0x00011677, 0xd7610000, - 0x00011a79, 0xd7610000, - 0x00011c7e, 0xd7610000, - 0x00011e7f, 0xbefe00ff, - 0x00003fff, 0xbeff0080, - 0xee0a407a, 0x000c0000, - 0x00000000, 0xd760007a, - 0x00011d00, 0xd760007b, - 0x00011f00, 0xbefe007a, - 0xbeff007b, 0xbef4007e, - 0x8b75ff7f, 0x01ffffff, - 0xbef1007d, 0xb8f30742, - 0x84739973, 0xbefe00c1, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa20002, - 0xbeff0080, 0xbfa00002, - 0xbeff00c1, 0xbfa0000a, - 0xee0a4074, 0x008c0000, - 0x00008000, 0xee0a4074, - 0x010c0000, 0x00010000, - 0xee0a4074, 0x018c0000, - 0x00018000, 0xbfa00009, - 0xee0a4074, 0x008c0000, + 0xbef4007e, 0x8b75ff7f, + 0x01ffffff, 0xbef1007d, + 0xb8f30742, 0x84739973, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20002, 0xbeff0080, + 0xbfa00002, 0xbeff00c1, + 0xbfa0000a, 0xee0a4074, + 0x008c0000, 0x00008000, + 0xee0a4074, 0x010c0000, 0x00010000, 0xee0a4074, - 0x010c0000, 0x00020000, - 0xee0a4074, 0x018c0000, - 0x00030000, 0xb8f03b05, - 0x80708170, 0xbf0d9973, - 0xbfa20002, 0x84708970, - 0xbfa00001, 0x84708a70, - 0x8070ff70, 0x00000200, - 0x7e000280, 0x7e020280, - 0x7e040280, 0xbefd0080, - 0xd7610002, 0x0000fa71, - 0x807d817d, 0xb8faf802, - 0xbf0c8b7a, 0xbfa20003, - 0xbe804fc2, 0xbf94fffe, - 0xbfa10001, 0xbe804ec4, - 0xbf94fffc, 0xbefa4c88, - 0xbfc70000, 0xbf0c807a, - 0xbfa20006, 0x9371ff7a, - 0x00070004, 0x937aff7a, - 0x00070010, 0xbf06717a, - 0xbfa2fff6, 0xb8faf804, - 0x8b7aff7a, 0x0001000c, - 0x9178ff78, 0x0001000c, - 0x8c787a78, 0xd7610002, - 0x0000fa6c, 0x807d817d, - 0x8b7aff6d, 0x01ffffff, - 0xd7610002, 0x0000fa7a, - 0x807d817d, 0xd7610002, - 0x0000fa6e, 0x807d817d, - 0xbefa0080, 0xd7610002, + 0x018c0000, 0x00018000, + 0xbfa00009, 0xee0a4074, + 0x008c0000, 0x00010000, + 0xee0a4074, 0x010c0000, + 0x00020000, 0xee0a4074, + 0x018c0000, 0x00030000, + 0xb8f03b05, 0x80708170, + 0xbf0d9973, 0xbfa20002, + 0x84708970, 0xbfa00001, + 0x84708a70, 0x8070ff70, + 0x00000200, 0x7e000280, + 0x7e020280, 0x7e040280, + 0xbefd0080, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8faf802, 0xbf0c8b7a, + 0xbfa20003, 0xbe804fc2, + 0xbf94fffe, 0xbfa10001, + 0xbe804ec4, 0xbf94fffc, + 0xbefa4c88, 0xbfc70000, + 0xbf0c807a, 0xbfa20006, + 0x9371ff7a, 0x00070004, + 0x937aff7a, 0x00070010, + 0xbf06717a, 0xbfa2fff6, + 0xb8faf804, 0x8b7aff7a, + 0x0001000c, 0x9178ff78, + 0x0001000c, 0x8c787a78, + 0xd7610002, 0x0000fa6c, + 0x807d817d, 0x8b7aff6d, + 0x01ffffff, 0xd7610002, 0x0000fa7a, 0x807d817d, - 0xd7610002, 0x0000fa78, - 0x807d817d, 0xb8faf811, + 0xd7610002, 0x0000fa6e, + 0x807d817d, 0xbefa0080, 0xd7610002, 0x0000fa7a, 0x807d817d, 0xd7610002, - 0x0000fa6f, 0x807d817d, - 0xb8f1f801, 0x937aff6d, - 0x00060019, 0x847a8c7a, - 0x8c717a71, 0xd7610002, - 0x0000fa71, 0x807d817d, - 0xb8f1f814, 0xd7610002, - 0x0000fa71, 0x807d817d, - 0xb8f1f815, 0xd7610002, - 0x0000fa71, 0x807d817d, - 0xb8f1f812, 0xd7610002, - 0x0000fa71, 0x807d817d, - 0xb8f1f813, 0xd7610002, - 0x0000fa71, 0x807d817d, - 0xb8faf802, 0xd7610002, + 0x0000fa78, 0x807d817d, + 0xb8faf811, 0xd7610002, 0x0000fa7a, 0x807d817d, - 0xbefa50c1, 0xbfc70000, + 0xd7610002, 0x0000fa6f, + 0x807d817d, 0xb8f1f801, + 0x937aff6d, 0x00060019, + 0x847a8c7a, 0x8c717a71, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f814, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f815, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f812, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f813, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8faf802, 0xd7610002, 0x0000fa7a, - 0x807d817d, 0xbefa4c88, + 0x807d817d, 0xbefa50c1, 0xbfc70000, 0xd7610002, 0x0000fa7a, 0x807d817d, - 0xb8faf81a, 0xd7610002, - 0x0000fa7a, 0x807d817d, - 0xbefe00c1, 0xbeff0080, - 0x80767074, 0x82778075, + 0xbefa4c88, 0xbfc70000, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xb8faf81a, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xbefe00c1, + 0xbeff0080, 0x80767074, + 0x82778075, 0xee0a4076, + 0x010c0000, 0x00000000, + 0xbefe00c1, 0x7e040280, + 0xbefa5081, 0xbfc70000, + 0xd7610002, 0x0001007a, + 0xbefa5082, 0xbfc70000, + 0xd7610002, 0x0001027a, + 0xbefa5083, 0xbfc70000, + 0xd7610002, 0x0001047a, + 0xbefa5084, 0xbfc70000, + 0xd7610002, 0x0001067a, + 0xbefa5085, 0xbfc70000, + 0xd7610002, 0x0001087a, + 0xbefa5086, 0xbfc70000, + 0xd7610002, 0x00010a7a, + 0xbefa5087, 0xbfc70000, + 0xd7610002, 0x00010c7a, + 0xbefa5088, 0xbfc70000, + 0xd7610002, 0x00010e7a, + 0xbefa5089, 0xbfc70000, + 0xd7610002, 0x0001107a, + 0xbefa508a, 0xbfc70000, + 0xd7610002, 0x0001127a, + 0xbefa508b, 0xbfc70000, + 0xd7610002, 0x0001147a, + 0xbefa508c, 0xbfc70000, + 0xd7610002, 0x0001167a, + 0xbefa508d, 0xbfc70000, + 0xd7610002, 0x0001187a, + 0xbefa508e, 0xbfc70000, + 0xd7610002, 0x00011a7a, + 0xbefa508f, 0xbfc70000, + 0xd7610002, 0x00011c7a, + 0xbefa5090, 0xbfc70000, + 0xd7610002, 0x00011e7a, 0xee0a4076, 0x010c0000, - 0x00000000, 0xbefe00c1, - 0x7e040280, 0xbefa5081, - 0xbfc70000, 0xd7610002, - 0x0001007a, 0xbefa5082, - 0xbfc70000, 0xd7610002, - 0x0001027a, 0xbefa5083, - 0xbfc70000, 0xd7610002, - 0x0001047a, 0xbefa5084, - 0xbfc70000, 0xd7610002, - 0x0001067a, 0xbefa5085, - 0xbfc70000, 0xd7610002, - 0x0001087a, 0xbefa5086, - 0xbfc70000, 0xd7610002, - 0x00010a7a, 0xbefa5087, - 0xbfc70000, 0xd7610002, - 0x00010c7a, 0xbefa5088, - 0xbfc70000, 0xd7610002, - 0x00010e7a, 0xbefa5089, - 0xbfc70000, 0xd7610002, - 0x0001107a, 0xbefa508a, - 0xbfc70000, 0xd7610002, - 0x0001127a, 0xbefa508b, - 0xbfc70000, 0xd7610002, - 0x0001147a, 0xbefa508c, - 0xbfc70000, 0xd7610002, - 0x0001167a, 0xbefa508d, - 0xbfc70000, 0xd7610002, - 0x0001187a, 0xbefa508e, - 0xbfc70000, 0xd7610002, - 0x00011a7a, 0xbefa508f, - 0xbfc70000, 0xd7610002, - 0x00011c7a, 0xbefa5090, - 0xbfc70000, 0xd7610002, - 0x00011e7a, 0xee0a4076, - 0x010c0000, 0x00008000, - 0xb8f03b05, 0x80708170, - 0xbf0d9973, 0xbfa20002, - 0x84708970, 0xbfa00001, - 0x84708a70, 0xbef90080, - 0xbefd0080, 0xbf800000, + 0x00008000, 0xb8f03b05, + 0x80708170, 0xbf0d9973, + 0xbfa20002, 0x84708970, + 0xbfa00001, 0x84708a70, + 0xbef90080, 0xbefd0080, + 0xbf800000, 0xbe804100, + 0xbe824102, 0xbe844104, + 0xbe864106, 0xbe884108, + 0xbe8a410a, 0xbe8c410c, + 0xbe8e410e, 0xd7610002, + 0x0000f200, 0x80798179, + 0xd7610002, 0x0000f201, + 0x80798179, 0xd7610002, + 0x0000f202, 0x80798179, + 0xd7610002, 0x0000f203, + 0x80798179, 0xd7610002, + 0x0000f204, 0x80798179, + 0xd7610002, 0x0000f205, + 0x80798179, 0xd7610002, + 0x0000f206, 0x80798179, + 0xd7610002, 0x0000f207, + 0x80798179, 0xd7610002, + 0x0000f208, 0x80798179, + 0xd7610002, 0x0000f209, + 0x80798179, 0xd7610002, + 0x0000f20a, 0x80798179, + 0xd7610002, 0x0000f20b, + 0x80798179, 0xd7610002, + 0x0000f20c, 0x80798179, + 0xd7610002, 0x0000f20d, + 0x80798179, 0xd7610002, + 0x0000f20e, 0x80798179, + 0xd7610002, 0x0000f20f, + 0x80798179, 0xbf06a079, + 0xbfa10009, 0x80767074, + 0x82778075, 0xee0a4076, + 0x010c0000, 0x00000000, + 0x8070ff70, 0x00000080, + 0xbef90080, 0x7e040280, + 0x807d907d, 0xbf0aff7d, + 0x00000060, 0xbfa2ffb9, 0xbe804100, 0xbe824102, 0xbe844104, 0xbe864106, 0xbe884108, 0xbe8a410a, - 0xbe8c410c, 0xbe8e410e, 0xd7610002, 0x0000f200, 0x80798179, 0xd7610002, 0x0000f201, 0x80798179, @@ -5035,63 +5084,39 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xd7610002, 0x0000f20a, 0x80798179, 0xd7610002, 0x0000f20b, 0x80798179, - 0xd7610002, 0x0000f20c, - 0x80798179, 0xd7610002, - 0x0000f20d, 0x80798179, - 0xd7610002, 0x0000f20e, - 0x80798179, 0xd7610002, - 0x0000f20f, 0x80798179, - 0xbf06a079, 0xbfa10009, + 0xbefe00ff, 0x0000ffff, 0x80767074, 0x82778075, 0xee0a4076, 0x010c0000, - 0x00000000, 0x8070ff70, - 0x00000080, 0xbef90080, - 0x7e040280, 0x807d907d, - 0xbf0aff7d, 0x00000060, - 0xbfa2ffb9, 0xbe804100, - 0xbe824102, 0xbe844104, - 0xbe864106, 0xbe884108, - 0xbe8a410a, 0xd7610002, - 0x0000f200, 0x80798179, - 0xd7610002, 0x0000f201, - 0x80798179, 0xd7610002, - 0x0000f202, 0x80798179, - 0xd7610002, 0x0000f203, - 0x80798179, 0xd7610002, - 0x0000f204, 0x80798179, - 0xd7610002, 0x0000f205, - 0x80798179, 0xd7610002, - 0x0000f206, 0x80798179, - 0xd7610002, 0x0000f207, - 0x80798179, 0xd7610002, - 0x0000f208, 0x80798179, - 0xd7610002, 0x0000f209, - 0x80798179, 0xd7610002, - 0x0000f20a, 0x80798179, - 0xd7610002, 0x0000f20b, - 0x80798179, 0xbefe00ff, - 0x0000ffff, 0x80767074, + 0x00000000, 0xbefe00c1, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8fb4306, + 0x8b7bc17b, 0xbfa10042, + 0x8b7aff6d, 0x80000000, + 0xbfa1003f, 0x847b8a7b, + 0xb8f03b05, 0x80708170, + 0xbf0d9973, 0xbfa20002, + 0x84708970, 0xbfa00001, + 0x84708a70, 0x8070ff70, + 0x00000200, 0x8070ff70, + 0x00000200, 0xd71f0000, + 0x000100c1, 0xd7200000, + 0x000200c1, 0x16000084, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbefd0080, + 0xbfa20015, 0xbe8300ff, + 0x00000080, 0xbf800000, + 0xbf800000, 0xbf800000, + 0xd8d80000, 0x01000000, + 0xbf8a0000, 0x80767074, 0x82778075, 0xee0a4076, - 0x010c0000, 0x00000000, - 0xbefe00c1, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbfa20002, 0xbeff0080, - 0xbfa00001, 0xbeff00c1, - 0xb8fb4306, 0x8b7bc17b, - 0xbfa10042, 0x8b7aff6d, - 0x80000000, 0xbfa1003f, - 0x847b8a7b, 0xb8f03b05, - 0x80708170, 0xbf0d9973, - 0xbfa20002, 0x84708970, - 0xbfa00001, 0x84708a70, - 0x8070ff70, 0x00000200, - 0x8070ff70, 0x00000200, - 0xd71f0000, 0x000100c1, - 0xd7200000, 0x000200c1, - 0x16000084, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbefd0080, 0xbfa20015, - 0xbe8300ff, 0x00000080, + 0x008c0000, 0x00000000, + 0x807d037d, 0x80700370, + 0xd5250000, 0x0001ff00, + 0x00000080, 0xbf0a7b7d, + 0xbfa2fff1, 0xbfa00014, + 0xbe8300ff, 0x00000100, 0xbf800000, 0xbf800000, 0xbf800000, 0xd8d80000, 0x01000000, 0xbf8a0000, @@ -5099,254 +5124,244 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xee0a4076, 0x008c0000, 0x00000000, 0x807d037d, 0x80700370, 0xd5250000, - 0x0001ff00, 0x00000080, + 0x0001ff00, 0x00000100, 0xbf0a7b7d, 0xbfa2fff1, - 0xbfa00014, 0xbe8300ff, - 0x00000100, 0xbf800000, - 0xbf800000, 0xbf800000, - 0xd8d80000, 0x01000000, - 0xbf8a0000, 0x80767074, - 0x82778075, 0xee0a4076, - 0x008c0000, 0x00000000, - 0x807d037d, 0x80700370, - 0xd5250000, 0x0001ff00, - 0x00000100, 0xbf0a7b7d, - 0xbfa2fff1, 0xbefe00c1, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa20004, - 0xbef000ff, 0x00000200, - 0xbeff0080, 0xbfa00003, - 0xbef000ff, 0x00000400, - 0xbeff00c1, 0xb8fb3b05, - 0x807b817b, 0x847b827b, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa2001b, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20004, 0xbef000ff, + 0x00000200, 0xbeff0080, + 0xbfa00003, 0xbef000ff, + 0x00000400, 0xbeff00c1, + 0xb8fb3b05, 0x807b817b, + 0x847b827b, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa2001b, 0xbefd0084, + 0xbf0a7b7d, 0xbfa10032, + 0x7e008700, 0x7e028701, + 0x7e048702, 0x7e068703, + 0x80767074, 0x82778075, + 0xee0a4076, 0x000c0000, + 0x00000000, 0xee0a4076, + 0x008c0000, 0x00008000, + 0xee0a4076, 0x010c0000, + 0x00010000, 0xee0a4076, + 0x018c0000, 0x00018000, + 0x807d847d, 0x8070ff70, + 0x00000200, 0xbf0a7b7d, + 0xbfa2ffe9, 0xbfa0001a, 0xbefd0084, 0xbf0a7b7d, - 0xbfa10032, 0x7e008700, + 0xbfa10017, 0x7e008700, 0x7e028701, 0x7e048702, 0x7e068703, 0x80767074, 0x82778075, 0xee0a4076, 0x000c0000, 0x00000000, 0xee0a4076, 0x008c0000, - 0x00008000, 0xee0a4076, - 0x010c0000, 0x00010000, + 0x00010000, 0xee0a4076, + 0x010c0000, 0x00020000, 0xee0a4076, 0x018c0000, - 0x00018000, 0x807d847d, - 0x8070ff70, 0x00000200, + 0x00030000, 0x807d847d, + 0x8070ff70, 0x00000400, 0xbf0a7b7d, 0xbfa2ffe9, - 0xbfa0001a, 0xbefd0084, - 0xbf0a7b7d, 0xbfa10017, - 0x7e008700, 0x7e028701, - 0x7e048702, 0x7e068703, - 0x80767074, 0x82778075, - 0xee0a4076, 0x000c0000, - 0x00000000, 0xee0a4076, - 0x008c0000, 0x00010000, - 0xee0a4076, 0x010c0000, - 0x00020000, 0xee0a4076, - 0x018c0000, 0x00030000, - 0x807d847d, 0x8070ff70, - 0x00000400, 0xbf0a7b7d, - 0xbfa2ffe9, 0xbfa00184, - 0xbef4007e, 0x8b75ff7f, - 0x01ffffff, 0xbef1007f, - 0xb8f20742, 0x84729972, - 0x8b6eff7f, 0x04000000, - 0xbfa10044, 0xbefe00c1, - 0x857d9972, 0x8b7d817d, - 0xbf06817d, 0xbfa20002, - 0xbeff0080, 0xbfa00001, - 0xbeff00c1, 0xb8ef4306, - 0x8b6fc16f, 0xbfa10039, - 0x846f8a6f, 0xb8f83b05, - 0x80788178, 0xbf0d9972, - 0xbfa20002, 0x84788978, - 0xbfa00001, 0x84788a78, - 0x8078ff78, 0x00000200, - 0x8078ff78, 0x00000200, - 0x857d9972, 0x8b7d817d, - 0xbf06817d, 0xbefd0080, - 0xd71f0001, 0x000100c1, - 0xd7200001, 0x000202c1, - 0x30020282, 0xbfa20012, - 0x80767874, 0x82778075, - 0xee0a0076, 0x000c0000, - 0x00000000, 0xbf8a0000, - 0xd8340000, 0x00000001, - 0xd5250001, 0x0001ff01, - 0x00000080, 0x807dff7d, - 0x00000080, 0x8078ff78, - 0x00000080, 0xbf0a6f7d, - 0xbfa2ffef, 0xbfa00011, - 0x80767874, 0x82778075, - 0xee0a0076, 0x000c0000, - 0x00000000, 0xbf8a0000, - 0xd8340000, 0x00000001, - 0xd5250001, 0x0001ff01, - 0x00000100, 0x807dff7d, - 0x00000100, 0x8078ff78, - 0x00000100, 0xbf0a6f7d, - 0xbfa2ffef, 0xbef80080, + 0xbfa00184, 0xbef4007e, + 0x8b75ff7f, 0x01ffffff, + 0xbef1007f, 0xb8f20742, + 0x84729972, 0x8b6eff7f, + 0x04000000, 0xbfa10044, 0xbefe00c1, 0x857d9972, 0x8b7d817d, 0xbf06817d, 0xbfa20002, 0xbeff0080, 0xbfa00001, 0xbeff00c1, - 0xb8ef3b05, 0x806f816f, - 0x846f826f, 0x857d9972, + 0xb8ef4306, 0x8b6fc16f, + 0xbfa10039, 0x846f8a6f, + 0xb8f83b05, 0x80788178, + 0xbf0d9972, 0xbfa20002, + 0x84788978, 0xbfa00001, + 0x84788a78, 0x8078ff78, + 0x00000200, 0x8078ff78, + 0x00000200, 0x857d9972, 0x8b7d817d, 0xbf06817d, - 0xbfa2002c, 0xbeee0078, - 0x8078ff78, 0x00000200, - 0xbefd0084, 0x80767874, - 0x82778075, 0xee0a0076, - 0x000c0000, 0x00000000, - 0xee0a0076, 0x000c0001, - 0x00008000, 0xee0a0076, - 0x000c0002, 0x00010000, - 0xee0a0076, 0x000c0003, - 0x00018000, 0xbf8a0000, - 0x7e008500, 0x7e028501, - 0x7e048502, 0x7e068503, - 0x807d847d, 0x8078ff78, - 0x00000200, 0xbf0a6f7d, - 0xbfa2ffe8, 0x80766e74, + 0xbefd0080, 0xd71f0001, + 0x000100c1, 0xd7200001, + 0x000202c1, 0x30020282, + 0xbfa20012, 0x80767874, 0x82778075, 0xee0a0076, 0x000c0000, 0x00000000, - 0xee0a0076, 0x000c0001, - 0x00008000, 0xee0a0076, - 0x000c0002, 0x00010000, - 0xee0a0076, 0x000c0003, - 0x00018000, 0xbf8a0000, - 0xbfa0002d, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefd0084, 0xbf0a6f7d, - 0xbfa10018, 0x80767874, + 0xbf8a0000, 0xd8340000, + 0x00000001, 0xd5250001, + 0x0001ff01, 0x00000080, + 0x807dff7d, 0x00000080, + 0x8078ff78, 0x00000080, + 0xbf0a6f7d, 0xbfa2ffef, + 0xbfa00011, 0x80767874, 0x82778075, 0xee0a0076, 0x000c0000, 0x00000000, - 0xee0a0076, 0x000c0001, + 0xbf8a0000, 0xd8340000, + 0x00000001, 0xd5250001, + 0x0001ff01, 0x00000100, + 0x807dff7d, 0x00000100, + 0x8078ff78, 0x00000100, + 0xbf0a6f7d, 0xbfa2ffef, + 0xbef80080, 0xbefe00c1, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8ef3b05, + 0x806f816f, 0x846f826f, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa2002c, + 0xbeee0078, 0x8078ff78, + 0x00000200, 0xbefd0084, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00008000, + 0xee0a0076, 0x000c0002, 0x00010000, 0xee0a0076, - 0x000c0002, 0x00020000, - 0xee0a0076, 0x000c0003, - 0x00030000, 0xbf8a0000, - 0x7e008500, 0x7e028501, - 0x7e048502, 0x7e068503, - 0x807d847d, 0x8078ff78, - 0x00000400, 0xbf0a6f7d, - 0xbfa2ffe8, 0x80766e74, - 0x82778075, 0xee0a0076, - 0x000c0000, 0x00000000, - 0xee0a0076, 0x000c0001, + 0x000c0003, 0x00018000, + 0xbf8a0000, 0x7e008500, + 0x7e028501, 0x7e048502, + 0x7e068503, 0x807d847d, + 0x8078ff78, 0x00000200, + 0xbf0a6f7d, 0xbfa2ffe8, + 0x80766e74, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00008000, + 0xee0a0076, 0x000c0002, 0x00010000, 0xee0a0076, - 0x000c0002, 0x00020000, - 0xee0a0076, 0x000c0003, - 0x00030000, 0xbf8a0000, - 0xb8f83b05, 0x80788178, - 0xbf0d9972, 0xbfa20002, - 0x84788978, 0xbfa00001, - 0x84788a78, 0x8078ff78, - 0x00000200, 0x80f8ff78, - 0x00000060, 0x80767874, - 0x82778075, 0xbefd00ff, - 0x0000006c, 0xf460403b, - 0xf8000000, 0xbf8a0000, - 0x80fd847d, 0xbf800000, - 0xbe804300, 0xbe824302, - 0x80f6a076, 0x82f78077, - 0xf460603b, 0xf8000000, - 0xbf8a0000, 0x80fd887d, + 0x000c0003, 0x00018000, + 0xbf8a0000, 0xbfa0002d, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefd0084, + 0xbf0a6f7d, 0xbfa10018, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00010000, + 0xee0a0076, 0x000c0002, + 0x00020000, 0xee0a0076, + 0x000c0003, 0x00030000, + 0xbf8a0000, 0x7e008500, + 0x7e028501, 0x7e048502, + 0x7e068503, 0x807d847d, + 0x8078ff78, 0x00000400, + 0xbf0a6f7d, 0xbfa2ffe8, + 0x80766e74, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00010000, + 0xee0a0076, 0x000c0002, + 0x00020000, 0xee0a0076, + 0x000c0003, 0x00030000, + 0xbf8a0000, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0x8078ff78, 0x00000200, + 0x80f8ff78, 0x00000060, + 0x80767874, 0x82778075, + 0xbefd00ff, 0x0000006c, + 0xf460403b, 0xf8000000, + 0xbf8a0000, 0x80fd847d, 0xbf800000, 0xbe804300, - 0xbe824302, 0xbe844304, - 0xbe864306, 0x80f6c076, - 0x82f78077, 0xf460803b, + 0xbe824302, 0x80f6a076, + 0x82f78077, 0xf460603b, 0xf8000000, 0xbf8a0000, - 0x80fd907d, 0xbf800000, + 0x80fd887d, 0xbf800000, 0xbe804300, 0xbe824302, 0xbe844304, 0xbe864306, - 0xbe884308, 0xbe8a430a, - 0xbe8c430c, 0xbe8e430e, - 0xbf06807d, 0xbfa1ffef, - 0xb980f801, 0x00000000, - 0xb8f83b05, 0x80788178, - 0xbf0d9972, 0xbfa20002, - 0x84788978, 0xbfa00001, - 0x84788a78, 0x8078ff78, - 0x00000200, 0x80767874, - 0x82778075, 0xbeff0071, - 0xf4601bfb, 0xf8000000, - 0xf4601b3b, 0xf8000004, - 0xf4601b7b, 0xf8000008, - 0xf4601c3b, 0xf800000c, - 0xf4601c7b, 0xf8000010, - 0xf4601ebb, 0xf8000014, - 0xf4601efb, 0xf8000018, - 0xf4601e7b, 0xf800001c, - 0xf4601cfb, 0xf8000020, - 0xf4601bbb, 0xf8000024, - 0xbf8a0000, 0xb96ef814, - 0xf4601bbb, 0xf8000028, - 0xbf8a0000, 0xb96ef815, - 0xf4601bbb, 0xf800002c, - 0xbf8a0000, 0xb96ef812, - 0xf4601bbb, 0xf8000030, - 0xbf8a0000, 0xb96ef813, - 0x8b6eff7f, 0x04000000, - 0xbfa10022, 0xf4601bbb, - 0xf8000038, 0xbf8a0000, - 0xbf0d806e, 0xbfa1001d, - 0x856e906e, 0x8b6e6e6e, - 0xbfa10003, 0xbe804ec1, - 0x816ec16e, 0xbfa0fffb, - 0xbef800ff, 0x00000080, - 0xbefd0081, 0xf4601bbb, - 0xf0000000, 0xbfc70000, - 0x80788478, 0x937eff6e, - 0x00070004, 0x847e907e, - 0x8c7d7e7d, 0xbe80517d, - 0x917dff7d, 0x007f0000, - 0x856e906e, 0x8b6e6e6e, - 0xbfa10003, 0xbe804e7d, - 0x816ec16e, 0xbfa0fffb, - 0x807d817d, 0xbf08907d, - 0xbfa1ffec, 0xf4601bbb, - 0xf800003c, 0xbfc70000, - 0xbf0d806e, 0xbfa1000c, - 0xbf0d9a7f, 0xbfa10002, - 0xbf068180, 0xbe804fc4, - 0xbf94fffc, 0xbfa10006, - 0x856e906e, 0x8b6e6e6e, - 0xbfa10003, 0xbe804ec3, - 0x816ec16e, 0xbfa0fffb, - 0xf4601bbb, 0xf8000040, - 0xbfc70000, 0xb96ef81a, - 0xbefd006f, 0xbefe0070, - 0xbeff0071, 0xb979f822, - 0xb97b2011, 0x857b867b, - 0xb97b0191, 0x857b827b, - 0xb97bba11, 0xb973f801, - 0xb8ee3b05, 0x806e816e, - 0xbf0d9972, 0xbfa20002, - 0x846e896e, 0xbfa00001, - 0x846e8a6e, 0x806eff6e, - 0x000001c0, 0x806e746e, - 0x826f8075, 0xf4605c37, - 0xf8000010, 0xf4605d37, - 0xf8000020, 0xf4601e77, - 0xf8000034, 0xbf8a0000, - 0x856e9677, 0xb96e04a1, - 0x856e9577, 0xb96e0421, - 0x856e8e77, 0xb96e3021, - 0x8b6dff6d, 0x01ffffff, - 0x8bfe7e7e, 0x8bea6a6a, - 0xb97af804, 0xb8eef802, - 0xbf0c8b6e, 0xbfa20003, - 0xbe804fc2, 0xbf94fffe, - 0xbfa10001, 0xbe804ec4, - 0xbf94fffc, 0x857a897a, - 0xb97a0244, 0xbe804a6c, + 0x80f6c076, 0x82f78077, + 0xf460803b, 0xf8000000, + 0xbf8a0000, 0x80fd907d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0xbe844304, + 0xbe864306, 0xbe884308, + 0xbe8a430a, 0xbe8c430c, + 0xbe8e430e, 0xbf06807d, + 0xbfa1ffef, 0xb980f801, + 0x00000000, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0x8078ff78, 0x00000200, + 0x80767874, 0x82778075, + 0xbeff0071, 0xf4601bfb, + 0xf8000000, 0xf4601b3b, + 0xf8000004, 0xf4601b7b, + 0xf8000008, 0xf4601c3b, + 0xf800000c, 0xf4601c7b, + 0xf8000010, 0xf4601ebb, + 0xf8000014, 0xf4601efb, + 0xf8000018, 0xf4601e7b, + 0xf800001c, 0xf4601cfb, + 0xf8000020, 0xf4601bbb, + 0xf8000024, 0xbf8a0000, + 0xb96ef814, 0xf4601bbb, + 0xf8000028, 0xbf8a0000, + 0xb96ef815, 0xf4601bbb, + 0xf800002c, 0xbf8a0000, + 0xb96ef812, 0xf4601bbb, + 0xf8000030, 0xbf8a0000, + 0xb96ef813, 0x8b6eff7f, + 0x04000000, 0xbfa10022, + 0xf4601bbb, 0xf8000038, + 0xbf8a0000, 0xbf0d806e, + 0xbfa1001d, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804ec1, 0x816ec16e, + 0xbfa0fffb, 0xbef800ff, + 0x00000080, 0xbefd0081, + 0xf4601bbb, 0xf0000000, + 0xbfc70000, 0x80788478, + 0x937eff6e, 0x00070004, + 0x847e907e, 0x8c7d7e7d, + 0xbe80517d, 0x917dff7d, + 0x007f0000, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804e7d, 0x816ec16e, + 0xbfa0fffb, 0x807d817d, + 0xbf08907d, 0xbfa1ffec, + 0xf4601bbb, 0xf800003c, + 0xbfc70000, 0xbf0d806e, + 0xbfa1000c, 0xbf0d9a7f, + 0xbfa10002, 0xbf068180, + 0xbe804fc4, 0xbf94fffc, + 0xbfa10006, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804ec3, 0x816ec16e, + 0xbfa0fffb, 0xf4601bbb, + 0xf8000040, 0xbfc70000, + 0xb96ef81a, 0xbefd006f, + 0xbefe0070, 0xbeff0071, + 0xb979f822, 0xb97b2011, + 0x857b867b, 0xb97b0191, + 0x857b827b, 0xb97bba11, + 0xb973f801, 0xb8ee3b05, + 0x806e816e, 0xbf0d9972, + 0xbfa20002, 0x846e896e, + 0xbfa00001, 0x846e8a6e, + 0x806eff6e, 0x000001c0, + 0x806e746e, 0x826f8075, + 0xf4605c37, 0xf8000010, + 0xf4605d37, 0xf8000020, + 0xf4601e77, 0xf8000034, + 0xbf8a0000, 0x856e9677, + 0xb96e04a1, 0x856e9577, + 0xb96e0421, 0x856e8e77, + 0xb96e3021, 0x8b6dff6d, + 0x01ffffff, 0x8bfe7e7e, + 0x8bea6a6a, 0xb97af804, 0xb8eef802, 0xbf0c8b6e, 0xbfa20003, 0xbe804fc2, 0xbf94fffe, 0xbfa10001, 0xbe804ec4, 0xbf94fffc, - 0xbfb10000, 0xbf9f0000, + 0x857a897a, 0xb97a0244, + 0xbe804a6c, 0xb8eef802, + 0xbf0c8b6e, 0xbfa20003, + 0xbe804fc2, 0xbf94fffe, + 0xbfa10001, 0xbe804ec4, + 0xbf94fffc, 0xbfb10000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, + 0xbf9f0000, 0x00000000, }; diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm index 456db81998993..0fe0a6b0af37e 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm @@ -41,6 +41,7 @@ #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) +#define HAVE_HT_TRAP_ID_WA (ASIC_FAMILY == CHIP_GFX12) #define WAVE32_ONLY (ASIC_FAMILY == CHIP_GC_12_0_3) #define SAVE_TTMPS_IN_SGPR_BLOCK (ASIC_FAMILY >= CHIP_GC_12_0_3) @@ -60,6 +61,7 @@ var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT = 15 var SQ_WAVE_STATUS_WAVE64_SHIFT = 29 var SQ_WAVE_STATUS_WAVE64_SIZE = 1 var SQ_WAVE_STATUS_NO_VGPRS_SHIFT = 24 +var SQ_WAVE_STATUS_HALT_SHIFT = 14 var SQ_WAVE_STATUS_IN_WG_SHIFT = 11 var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK = SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK var S_SAVE_PC_HI_TRAP_ID_MASK = 0xF0000000 @@ -146,6 +148,12 @@ var TTMP11_REPLAY_W64H_MASK = 0x200000 var TTMP11_FXPTR_SHIFT = 14 var TTMP11_FXPTR_MASK = 0x1FC000 +var TTMP11_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP11_HOST_TRAP_ENABLED_MASK = (1 << TTMP11_HOST_TRAP_ENABLED_SHIFT) + +var TTMP11_FEATURES_ENABLED_FLAGS_SHIFT = TTMP11_DEBUG_TRAP_ENABLED_SHIFT +var TTMP11_FEATURES_ENABLED_FLAGS_MASK = TTMP11_DEBUG_TRAP_ENABLED_MASK | TTMP11_HOST_TRAP_ENABLED_MASK + // SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] // when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 @@ -253,12 +261,52 @@ L_SKIP_RESTORE: s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) +#if HAVE_HT_TRAP_ID_WA + // If we have both TRAP_ID (ttmp1[31:28]) != 0, and + // EXCP_FLAG_PRIV.HOST_TRAP == 1, we cannot reliably know if we entered + // the trap handler for an s_trap or a host trap. + // + // In both cases, if we see HOST_TRAP == 1, we can clear the TRAP_ID + // bits: + // - If this was a host trap, all good, those bits should have been 0 + // anyway, so they can be cleared. + // - If this was an s_trap, ttmp[0:1] still points to the s_trap + // instruction, and it will be the first to be executed after s_rfe. + // We do not change the behavior of the program, by not handling the + // trap just yet, assume this was just a host trap and deal with the + // s_trap on next entry. + s_bitcmp0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_cbranch_scc1 L_NOT_HOST_TRAP_WA + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK + +L_NOT_HOST_TRAP_WA: + // From now on in the trap handler, if we see TTMP1.TRAP_ID != 0, then it has + // to be because of a s_trap. If the second level trap handler sees + // both TRAP_ID != 0 and EXCP_FLAG_PRIV.HOST_TRAP == 1, it is because + // a HOST_TRAP was received while we were in the trap handler, future host + // trap can't influence ttmp1. So both the s_trap and host_trap can be handled + // in one go. +#endif + + // Ignore Host Trap if SAVECTX is also present. + // Usually s_trap has a higher priority than context_save, HAVE_HT_TRAP_ID_WA + // will reverse these priority's order when s_trap, host_trap and context save + // are raised at the same time. We will end-up ignoring the s_trap (because of + // the ambiguity with the host trap), ignoring the host trap (to be sure high + // frequency sampling cannot prevent CWSR) and directly doing the context save. + // The s_trap will be re-executed after context save/restore. + s_bitcmp0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT + s_bitset0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT, 1), 0 + +L_NO_SAVE_AND_HT: s_and_b32 ttmp2, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK s_cbranch_scc0 L_NOT_HALTED L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK + s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_SAVE: @@ -319,6 +367,7 @@ L_FETCH_2ND_TRAP: // Read second-level TBA/TMA from first-level TMA and jump if available. // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) // ttmp12 holds SQ_WAVE_STATUS + s_mov_b32 ttmp3, s_save_excp_flag_priv s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) s_wait_idle s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 @@ -335,12 +384,32 @@ L_NO_SIGN_EXTEND_TMA: s_or_b32 ttmp1, ttmp1, ttmp2 #endif - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag + s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // trap enabled flag s_wait_idle - s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK + s_lshl_b32 ttmp2, ttmp2, TTMP11_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 ttmp11, ttmp11, TTMP11_FEATURES_ENABLED_FLAGS_MASK s_or_b32 ttmp11, ttmp11, ttmp2 + // If not a host trap, then driver cannot mask this + s_bitcmp1_b32 ttmp3, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_cbranch_scc0 L_NO_EXCEPTION_MASKING + + s_bitcmp1_b32 s_save_state_priv, SQ_WAVE_STATUS_HALT_SHIFT + s_cbranch_scc1 L_MASK_HOST_TRAP + + // Handle masking host traps if requested by the driver. + s_bitcmp1_b32 ttmp11, TTMP11_HOST_TRAP_ENABLED_SHIFT + + // We got here because of either a non-maskable exception or a maskable + // one (HT). The driver said the maskable HT should not be masked, so + // we can directly carry on to the 2nd level trap handler. + s_cbranch_scc1 L_NO_EXCEPTION_MASKING + +L_MASK_HOST_TRAP: + // The driver asked to mask the HT, be sure to do so. + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT, 1), 0x0 + +L_NO_EXCEPTION_MASKING: s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 scope:SCOPE_SYS // second-level TBA s_wait_idle s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 scope:SCOPE_SYS // second-level TMA From 796f70fb4e22bb0052fa83f5632cc47d7fca5a1f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 3 Dec 2025 13:19:16 +0800 Subject: [PATCH 1643/2070] drm/amdkfd: Replace kfd_get_process with kfd_lookup_process_by_mm in amd_acquire The kfd_get_process() has been removed in "amdkfd: process pointer of a HIQ should be NULL", replace its usages with kfd_lookup_process_by_mm to maintain functionality. Signed-off-by: Chengjun Yao Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index aa4333548daeb..efd692e653f94 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -174,9 +174,10 @@ static int amd_acquire(unsigned long addr, size_t size, if (peer_mem_name == rdma_name) { p = peer_mem_private_data; + kref_get(&p->ref); } else { - p = kfd_get_process(current); - if (IS_ERR(p)) { + p = kfd_lookup_process_by_mm(current->mm); + if (!p) { pr_debug("Not a KFD process\n"); return 0; } @@ -217,6 +218,8 @@ static int amd_acquire(unsigned long addr, size_t size, /* Return pointer to allocated context */ *client_context = mem_context; + kfd_unref_process(p); + /* Return 1 to inform that this address which will be handled * by AMD GPU driver */ @@ -224,6 +227,8 @@ static int amd_acquire(unsigned long addr, size_t size, out_unlock: mutex_unlock(&p->mutex); + kfd_unref_process(p); + return 0; } From bede2103250eb550b71768043f02852c7271d2c4 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 15 Jan 2026 11:05:35 +0800 Subject: [PATCH 1644/2070] drm/amdkcl: Add domain parameter to alloc kernel BO on non-upstream code It's caused by the commit: eff707787fa4 "drm/amdkfd: Add domain parameter to alloc kernel BO" Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 271bb1c57561b..87e52194dc258 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -334,8 +334,8 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, int inst, struct amd spm->ring_size = order_base_2(4 * 1024 * 1024/4); spm->ring_size = (1 << spm->ring_size) * 4; - ret = amdgpu_amdkfd_alloc_gtt_mem(adev, - spm->ring_size, &spm->spm_obj, + ret = amdgpu_amdkfd_alloc_kernel_mem(adev, + spm->ring_size, AMDGPU_GEM_DOMAIN_GTT, &spm->spm_obj, &spm->gpu_addr, (void *)&spm->cpu_addr, false, false); @@ -361,7 +361,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, int inst, struct amd goto out; rlc_spm_acquire_failure: - amdgpu_amdkfd_free_gtt_mem(adev, &spm->spm_obj); + amdgpu_amdkfd_free_kernel_mem(adev, &spm->spm_obj); memset(spm, 0, sizeof(*spm)); out: return ret; @@ -422,7 +422,7 @@ static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct am if (!spm->ring_size) return; amdgpu_amdkfd_rlc_spm_release(adev, inst, drm_priv_to_vm(pdd->drm_priv)); - amdgpu_amdkfd_free_gtt_mem(adev, &(spm->spm_obj)); + amdgpu_amdkfd_free_kernel_mem(adev, &(spm->spm_obj)); spin_lock_irqsave(&pdd->spm_irq_lock, flags); memset(spm, 0, sizeof(*spm)); From 67ef8eaad9765a811b01c49c53b5f53d15b693ec Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Feb 2026 17:57:44 +0800 Subject: [PATCH 1645/2070] drm/amdkcl: test if dma_fence_check_and_signal() is available It's caused by 06bc18e0def7d926265480faa555bf0b67a35a90 "amd/amdkfd: Use dma_fence_check_and_signal()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 ++++- .../amd/dkms/m4/dma_fence_check_and_signal.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 971c672c659ca..279982cd156ec 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2230,8 +2230,11 @@ static bool signal_eviction_fence(struct kfd_process *p) rcu_read_unlock(); if (!ef) return true; - +#ifdef HAVE_DMA_FENCE_CHECK_AND_SIGNAL ret = dma_fence_check_and_signal(ef); +#else + ret = dma_fence_signal(ef); +#endif dma_fence_put(ef); return ret; diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 new file mode 100644 index 0000000000000..a203513509462 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.18-rc2-1390-gc891b99d25dd +dnl # dma-buf/dma-fence: Add dma_fence_check_and_signal() +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHECK_AND_SIGNAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_check_and_signal(NULL); + ], [dma_fence_check_and_signal], [drivers/dma-buf/st-dma-fence.c],[ + AC_DEFINE(HAVE_DMA_FENCE_CHECK_AND_SIGNAL, 1, + [dma_fence_check_and_signal() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 176877997427f..fe754056fecee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -154,6 +154,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_AMDGPU_VMA_LOOKUP + AC_AMDGPU_DMA_FENCE_CHECK_AND_SIGNAL AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO From 6d7e70ff705c62f0dbd17bd2bb272106c7e3ce2a Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 21 Jan 2026 15:54:17 +0800 Subject: [PATCH 1646/2070] drm/amdkcl: test whether macro for_each_or_bit is available It's caused by the commit: 9a42e3eff682 "drm/amdkfd: simplify svm_range_unmap_from_gpus()" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_find.h | 59 +++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 include/kcl/kcl_find.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6a40041b3b06b..4d640199dce25 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -65,6 +65,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_find.h b/include/kcl/kcl_find.h new file mode 100644 index 0000000000000..e798bd5536449 --- /dev/null +++ b/include/kcl/kcl_find.h @@ -0,0 +1,59 @@ +#ifndef KCL_FIND_H +#define KCL_FIND_H + +#include +#include + +#ifndef for_each_or_bit +#define KCL_FIND_NEXT_BIT(FETCH, MUNGE, size, start) \ +({ \ + unsigned long mask, idx, tmp, sz = (size), __start = (start); \ + \ + if (unlikely(__start >= sz)) \ + goto out; \ + \ + mask = MUNGE(BITMAP_FIRST_WORD_MASK(__start)); \ + idx = __start / BITS_PER_LONG; \ + \ + for (tmp = (FETCH) & mask; !tmp; tmp = (FETCH)) { \ + if ((idx + 1) * BITS_PER_LONG >= sz) \ + goto out; \ + idx++; \ + } \ + \ + sz = min(idx * BITS_PER_LONG + __ffs(MUNGE(tmp)), sz); \ +out: \ + sz; \ +}) + +/** + * Backport for: 266f80998f bitmap: add search for a set bit in OR of two bitmaps + * Introduced in kernel v5.19 + * + * Implementation adapted from lib/find_bit.c using FIND_NEXT_BIT macro + * to avoid depending on unexported _find_next_or_bit symbol. + */ +static inline unsigned long kcl_find_next_or_bit(const unsigned long *addr1, + const unsigned long *addr2, unsigned long size, + unsigned long offset) +{ + if (small_const_nbits(size)) { + unsigned long val; + + if (unlikely(offset >= size)) + return size; + + val = (*addr1 | *addr2) & GENMASK(size - 1, offset); + return val ? __ffs(val) : size; + } + + return KCL_FIND_NEXT_BIT(addr1[idx] | addr2[idx], /* nop */, size, offset); +} + +#define for_each_or_bit(bit, addr1, addr2, size) \ + for ((bit) = 0; \ + (bit) = kcl_find_next_or_bit((addr1), (addr2), (size), (bit)), (bit) < (size); \ + (bit)++) +#endif + +#endif /* KCL_FIND_H */ From c62e121b4bb7cdc01273ee17363c676ed8bfc42d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 30 Jan 2026 10:35:36 +0800 Subject: [PATCH 1647/2070] drm/amdkcl: Bump AMDGPU version to 6.19.0 Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 533 +++++++++++---------- drivers/gpu/drm/amd/dkms/config/install-sh | 181 ++++--- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 3 files changed, 387 insertions(+), 329 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b854c35bf23ec..68454fd442252 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -18,11 +18,10 @@ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 - + /* acpi_video_backlight_use_native() is available */ #define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 - /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 @@ -39,19 +38,19 @@ /* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ /* amd_iommu_pc_get_max_banks() declared */ -#define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED */ /* amd_iommu_pc_get_max_banks() arg is unsigned int */ /* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ -/* hmm support is enabled */ -#define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 +/* amd_iommu_pc_supported() is available */ +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ -/* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ -#define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 +/* aperture_remove_conflicting_pci_device() is available */ +#define HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES 1 -/* amd_iommu_pc_supported() is available */ -#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -62,8 +61,11 @@ /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 -/* amdgpu_attr_group->is_bin_visible is available */ -#define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + +/* bin_attrs in struct attribute_group is const */ +#define HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW 1 /* bin_attribute.read is const args */ #define HAVE_BIN_ATTR_CONST_ARGS 1 @@ -92,11 +94,17 @@ /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 +/* need a const argument in member func .is_bin_visible */ +#define HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE 1 + /* cpuinfo_x86.topo is available */ #define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 -/* debugfs_create_file_size() is available */ -#define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 +/* drm_edid_raw() is available */ +#define HAVE_CRTC_DRM_VBLANK_CRTC 1 + +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 /* devcgroup_check_permission() is available */ #define HAVE_DEVCGROUP_CHECK_PERMISSION 1 @@ -110,15 +118,15 @@ /* dev_is_removable() is available */ #define HAVE_DEV_IS_REMOVABLE 1 +/* dev_pagemap_ops has folio_free member */ +#define HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE 1 + /* dev_pagemap->owner is available */ #define HAVE_DEV_PAGEMAP_OWNER 1 /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 -/* dev_pm_set_driver_flags() is available */ -#define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 - /* dma_buf_is_dynamic() is available */ #define HAVE_DMA_BUF_IS_DYNAMIC 1 @@ -134,17 +142,32 @@ /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + +/* dma_fence_check_and_signal() is available */ +#define HAVE_DMA_FENCE_CHECK_AND_SIGNAL 1 + +/* dma_fence_dedup_array() is available */ +#define HAVE_DMA_FENCE_DEDUP_ARRAY 1 + /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 -/* whether dma_fence_get_stub exits */ -#define HAVE_DMA_FENCE_GET_STUB 1 +/* dma_fence_init64() is available */ +#define HAVE_DMA_FENCE_INIT64 1 /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 +/* dma_fence_is_later_or_same() is available */ +#define HAVE_DMA_FENCE_IS_LATER_OR_SAME 1 + +/* struct dma_fence_ops has callback set_deadline */ +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 + /* struct dma_fence_ops has use_64bit_seqno field */ -#define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 +/* #undef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO */ /* dma_fence_TIMESTAMP() is available */ #define HAVE_DMA_FENCE_TIMESTAMP 1 @@ -161,29 +184,17 @@ /* dma_resv->seq is seqcount_ww_mutex_t */ /* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ -/* bug for missing dma_resv->seq */ +/* Reporting dma_resv->seq bug */ /* #undef HAVE_DMA_RESV_SEQ_BUG */ /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 -/* down_write_killable() is available */ -#define HAVE_DOWN_WRITE_KILLABLE 1 - -/* fsleep() is available */ -#define HAVE_FSLEEP 1 - -/* drm_dp_mst_connector_early_unregister() is available */ -#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 - -/* drm_dp_mst_connector_late_register() is available */ -#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 - -/* drm_accurate_vblank_count() is available */ -/* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ +/* drmm_cgroup_register_region() is available */ +#define HAVE_DRMM_CGROUP_REGISTER_REGION 1 -/* DRM_AMDGPU_FENCE_TO_HANDLE is defined */ -#define HAVE_DRM_AMDGPU_FENCE_TO_HANDLE 1 +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ @@ -191,12 +202,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_AMD_ASIC_TYPE_H 1 -/* drm_aperture_remove_* is availablea */ -#define HAVE_DRM_APERTURE 1 - /* drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver* */ -#define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 +/* #undef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 @@ -204,18 +212,43 @@ /* drm_atomic_plane_enabling() is available */ #define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H 1 + +/* drm_client_dev_resume() is available */ +#define HAVE_DRM_CLIENT_DEV_RESUME 1 + /* drm_client_register() is available */ #define HAVE_DRM_CLIENT_REGISTER 1 +/* drm_client_setup() is available */ +#define HAVE_DRM_CLIENT_SETUP 1 + +/* struct drm_color_ctm_3x4 is available */ +#define HAVE_DRM_COLOR_CTM_3X4 1 + +/* drm_color_lut32_extract() is available */ +#define HAVE_DRM_COLOR_LUT32_EXTRACT 1 + +/* drm_color_lut32_size() is available */ +#define HAVE_DRM_COLOR_LUT32_SIZE 1 + /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 /* drm_connector_attach_hdr_output_metadata_property() is available */ #define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 +/* drm_connector_dynamic_init is available */ +#define HAVE_DRM_CONNECTOR_DYNAMIC_INIT 1 + /* drm_connector->edid_override is available */ #define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 +/* drm_connector->eld_mutex is available */ +#define HAVE_DRM_CONNECTOR_ELD_MUTEX 1 + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -227,21 +260,15 @@ arg */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* .mode_valid need a const drm_display_mode argument */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT 1 + /* drm_connector_helper_funcs->prepare_writeback_job is available */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB 1 /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 -/* connector property "max bpc" is available */ -#define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 - -/* drm_connector_put() is available */ -#define HAVE_DRM_CONNECTOR_PUT 1 - -/* connector reference counting is available */ -#define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 - /* drm_connector_set_panel_orientation_with_quirk() is available */ #define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 @@ -283,22 +310,23 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* drm_device->filelist_mutex is available */ -#define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 - /* drm_device->open_count is int */ /* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ +/* drm_dev_wedged_event() is available */ +#define HAVE_DRM_DEV_WEDGED_EVENT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_H 1 /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 -/* Define to 1 if you have the header file. */ +/* Define to 1 if you have the header file. + */ #define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 /* Define to 1 if you have the header file. */ @@ -319,14 +347,8 @@ /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 -/* display_info->hdmi.scdc.scrambling are available */ -#define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 - -/* display_info->max_tmds_clock is available */ -#define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 - -/* struct drm_display_info has monitor_range member */ -#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 /* display_info->luminance_range is available */ #define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 @@ -349,7 +371,11 @@ /* drm_dp_atomic_find_vcpi_slots() wants 5args */ /* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available */ +/* drm_dp_atomic_release_time_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS 1 + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is + available */ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ /* drm_dp_mst_atomic_setup_commit() is available */ @@ -364,11 +390,8 @@ /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 -/* apple_gmux_detect() is available */ -#define HAVE_APPLE_GMUX_DETECT 1 - -/* drm_dp_calc_pbn_mode() wants 3args */ -#define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 +/* drm_dp_calc_pbn_mode() wants 3 args */ +/* #undef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS */ /* drm_dp_cec_attach() is available */ #define HAVE_DRM_DP_CEC_ATTACH 1 @@ -382,9 +405,6 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 - /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 @@ -406,6 +426,12 @@ /* the guid of struct drm_dp_mst_branch is guid_t */ #define HAVE_DRM_DP_MST_BRANCH_GUID_T 1 +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 @@ -425,14 +451,11 @@ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 /* struct drm_dp_mst_port has passthrough_aux member */ -/* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +#define HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX 1 /* drm_dp_mst_root_conn_atomic_check() is available */ #define HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK 1 -/* drm_dp_mst_port struct has full_pbn member */ -#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 - /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ @@ -458,7 +481,10 @@ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 /* struct drm_dp_mst_topology_state has member pbn_div */ -#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV 1 +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT */ + +/* struct drm_dp_mst_topology_state has union member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION 1 /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 @@ -473,44 +499,46 @@ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 /* drm_dp_update_payload_part1() function has start_slot argument */ -#define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 +/* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ + +/* drm_driver->date is available */ +/* #undef HAVE_DRM_DRIVER_DATE */ + +/* drm_driver->gem_prime_mmap() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_MMAP */ -/* drm_driver->gem_prime_res_obj() is available */ /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ -/* drm_vblank struct use ktime_t for time field */ -#define HAVE_DRM_VBLANK_USE_KTIME_T 1 +/* drm_driver->show_fdinfo() is available */ +#define HAVE_DRM_DRIVER_SHOW_FDINFO 1 /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_APERTURE_H 1 +/* #undef HAVE_DRM_DRM_APERTURE_H */ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_CONNECTOR_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DEBUGFS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CLIENT_EVENT_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DEVICE_H 1 +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_CLIENT_SETUP_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DRV_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_COLOROP_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_HDCP_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ELD_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_IOCTL_H 1 +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_FBDEV_GENERIC_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_IRQ_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_TTM_H 1 /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 @@ -521,11 +549,15 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PANIC_H 1 +/* Define to 1 if you have the header + file. */ +#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_SUBALLOC_H 1 /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ @@ -554,13 +586,6 @@ /* drm_edid_override_connector_update() is available */ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 -/* drm_fb_helper_single_add_all_connectors() && - drm_fb_helper_remove_one_connector() are symbol */ -/* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ - -/* drm_fb_helper_alloc_info() is available */ -#define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 - /* drm_edid_raw() is available */ #define HAVE_DRM_EDID_RAW 1 @@ -579,7 +604,10 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ -/* drm_file->client_name is available */ +/* struct drm_file->client_id is available */ +#define HAVE_DRM_FILE_CLIENT_ID 1 + +/* struct drm_file->client_name is available */ #define HAVE_DRM_FILE_CLIENT_NAME 1 /* drm_file_err() is available */ @@ -591,6 +619,9 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 +/* drm_gem_dmabuf_vmap() has struct iosys_map arg */ +/* #undef HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG */ + /* drm_gem_is_imported() is available */ #define HAVE_DRM_GEM_IS_IMPORTED 1 @@ -609,11 +640,11 @@ /* drm_gem_object_put() is exported */ /* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ -/* ttm_buffer_object->base is available */ +/* drm_gem_object->resv/_resv is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gen_fb_init_with_funcs() is available */ -#define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 +/* drm_gem_plane_helper_prepare_fb() is available */ +#define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 /* drm_gem_prime_handle_to_dmabuf() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF 1 @@ -624,8 +655,8 @@ /* get_format_info uses pixel_format and modifier parameters */ #define HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS 1 -/* drm_get_panel_min_brightness_quirk() is available */ -#define HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK 1 +/* drm_get_panel_backlight_quirk() is available */ +#define HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK 1 /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -645,30 +676,39 @@ /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 -/* drm_kms_helper_is_poll_worker() is available */ -#define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 - /* drm_memcpy_from_wc() is availablea */ /* #undef HAVE_DRM_MEMCPY_FROM_WC */ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 +/* drm_memory_stats_is_zero() is available */ +#define HAVE_DRM_MEMORY_STATS_IS_ZERO 1 + /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 +/* drm_mode_config->fb_base is available */ +/* #undef HAVE_DRM_MODE_CONFIG_FB_BASE */ + /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 -/* drm_mode_config_funcs->atomic_state_alloc() is available */ -#define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 /* drm_mode_init() is available */ -#define HAVE_DRM_MODE_INTT 1 +#define HAVE_DRM_MODE_INIT 1 /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 +/* drm_plane->color_pipeline_property is available */ +#define HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY 1 + /* drm_plane_helper_destroy() is available */ #define HAVE_DRM_PLANE_HELPER_DESTROY 1 @@ -693,12 +733,6 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 -/* __assign_str() wants 1 arguments */ -#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 - -/* follow_pfn() is available */ -/* #undef HAVE_FOLLOW_PFN */ - /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 @@ -715,7 +749,7 @@ #define HAVE_DRM_VBLANK_CRTC_CONFIG 1 /* struct vblank->config is available */ -#define HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG 1 +/* #undef HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG */ /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ @@ -726,8 +760,20 @@ /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 -/* drm_mode_object->free_cb is available */ -/* #undef HAVE_FREE_CB_IN_STRUCT_DRM_MODE_OBJECT */ +/* fd_empty is available */ +#define HAVE_FD_EMPTY 1 + +/* file_operation->fop_flags is available */ +#define HAVE_FILE_OPERATION_FOP_FLAGS 1 + +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + +/* follow_pfnmap_start() is available */ +#define HAVE_FOLLOW_PFNMAP_START 1 + +/* fsleep() is available */ +#define HAVE_FSLEEP 1 /* fs_reclaim_acquire() is available */ #define HAVE_FS_RECLAIM_ACQUIRE 1 @@ -745,10 +791,13 @@ /* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ /* get_user_pages_remote() remove task_struct pointer */ -#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT 1 +/* #undef HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT */ -/* drm_connector_hdr_sink_metadata() is available */ -#define HAVE_HDR_SINK_METADATA 1 +/* get_user_pages_remote() remove argument vmas */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS 1 + +/* get_user_pages() remove vmas argument */ +#define HAVE_GET_USER_PAGES_REMOVE_VMAS 1 /* hmm remove the customizable pfn format */ #define HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT 1 @@ -756,8 +805,8 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 -/* struct i2c_lock_operations is defined */ -#define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 +/* hrtimer_setup() is available */ +#define HAVE_HRTIMER_SETUP 1 /* i2c_new_client_device() is enabled */ #define HAVE_I2C_NEW_CLIENT_DEVICE 1 @@ -768,15 +817,9 @@ /* import_guid() is available */ #define HAVE_IMPORT_GUID 1 -/* in_compat_syscall is defined */ -#define HAVE_IN_COMPAT_SYSCALL 1 - /* io_mapping_map_local_wc() is available */ #define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 -/* io_mapping_map_wc() has size argument */ -#define HAVE_IO_MAPPING_MAP_WC_HAS_SIZE_ARG 1 - /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 @@ -789,57 +832,63 @@ /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ -/* kernel_write() take arg type of position as pointer */ -#define HAVE_KERNEL_WRITE_PPOS 1 +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 /* HAVE_KFD_PEERDIRECT_SUPPORT is available */ /* #undef HAVE_KFD_PEERDIRECT_SUPPORT */ +/* HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path */ +/* #undef HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH */ + /* kfifo_out_linear() available */ #define HAVE_KFIFO_OUT_LINEAR 1 -/* kfifo_put() have non pointer parameter */ -#define HAVE_KFIFO_PUT_NON_POINTER 1 - /* kmalloc_size_roundup is available */ #define HAVE_KMALLOC_SIZE_ROUNDUP 1 /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 +/* kmap_local_page_try_from_panic() is available */ +#define HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC 1 + /* krealloc_array() is available */ #define HAVE_KREALLOC_ARRAY 1 -/* kref_read() function is available */ -#define HAVE_KREF_READ 1 +/* ksys_fd() is available */ +/* #undef HAVE_KSYS_CLOSE_FD */ /* ksys_sync_helper() is available */ #define HAVE_KSYS_SYNC_HELPER 1 -/* kthread_{park/unpark/parkme/should_park}() is available */ -#define HAVE_KTHREAD_PARK_XX 1 - /* kthread_{use,unuse}_mm() is available */ #define HAVE_KTHREAD_USE_MM 1 /* ktime_get_boottime_ns() is available */ #define HAVE_KTIME_GET_BOOTTIME_NS 1 -/* ktime_get_mono_fast_ns is available */ -#define HAVE_KTIME_GET_MONO_FAST_NS 1 - /* ktime_get_ns is available */ #define HAVE_KTIME_GET_NS 1 -/* ktime_get_raw_ns is available */ -#define HAVE_KTIME_GET_RAW_NS 1 - -/* ktime_get_real_seconds() is available */ -#define HAVE_KTIME_GET_REAL_SECONDS 1 - /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ +/* Define to 1 if you have the header file. */ +#define HAVE_KUNIT_TEST_BUG_H 1 + +/* kvrealloc() has 3 arguments */ +#define HAVE_KVREALLOC_3ARG 1 + +/* kvrealloc() has 4 arguments */ +/* #undef HAVE_KVREALLOC_4ARG */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ACPI_AMD_WBRF_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APERTURE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 @@ -858,12 +907,12 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CGROUP_DMEM_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CLEANUP_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_COMPILER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 @@ -906,15 +955,15 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_MEM_ENCRYPT_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_MMAP_LOCK_H 1 +/* local_try_cmpchg() is available */ +#define HAVE_LINUX_LOCAL_TRY_CMPXCHG 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MINMAX_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MMAP_LOCK_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 @@ -927,6 +976,12 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNALIGNED_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNITS_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_XARRAY_H 1 @@ -945,9 +1000,6 @@ /* enum MCE_PRIO_UC is available */ #define HAVE_MCE_PRIO_UC 1 -/* memalloc_nofs_{save,restore}() are available */ -#define HAVE_MEMALLOC_NOFS_SAVE 1 - /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 @@ -963,8 +1015,8 @@ /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 -/* mmgrab() is available */ -#define HAVE_MMGRAB 1 +/* mmap_assert_write_locked() is available */ +/* #undef HAVE_MMAP_ASSERT_WRITE_LOCKED */ /* mmput_async() is available */ #define HAVE_MMPUT_ASYNC 1 @@ -981,8 +1033,14 @@ /* mmu_notifier_synchronize() is available */ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 -/* release_pages() wants 2 args */ -#define HAVE_MM_RELEASE_PAGES_2ARGS 1 +/* MODULE_IMPORT_NS() wants a string arguments */ +#define HAVE_MODULE_IMPORT_NS_NEED_A_STRING 1 + +/* kvrealloc() isn't available */ +/* #undef HAVE_NO_KVREALLOC */ + +/* class_create has one argument */ +#define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1005,14 +1063,11 @@ /* pci_rebar_bytes_to_size() is available */ #define HAVE_PCI_REBAR_BYTES_TO_SIZE 1 -/* pci_upstream_bridge() is available */ -#define HAVE_PCI_UPSTREAM_BRIDGE 1 +/* pci_rebar_get_max_size() is available */ +#define HAVE_PCI_REBAR_GET_MAX_SIZE 1 -/* perf_event_update_userpage() is exported */ -#define HAVE_PERF_EVENT_UPDATE_USERPAGE 1 - -/* pfn_t is defined */ -#define HAVE_PFN_T 1 +/* pci_resize_resource() has align parameter */ +#define HAVE_PCI_RESIZE_RESOURCE_ALIGN 1 /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 @@ -1035,12 +1090,18 @@ /* pm_suspend_target_state is available */ #define HAVE_PM_SUSPEND_TARGET_STATE 1 -/* pm_suspend_via_firmware() is available */ -#define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 - /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* queue_work_node() is available */ +#define HAVE_QUEUE_WORK_NODE 1 + +/* range_overflows() is available */ +#define HAVE_RANGE_OVERFLOWS 1 + +/* ratelimit_state_reset_interval() is available */ +#define HAVE_RATELIMIT_STATE_RESET_INTERVAL 1 + /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 @@ -1050,11 +1111,8 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ -/* request_firmware_direct() is available */ -#define HAVE_REQUEST_FIRMWARE_DIRECT 1 - -/* sched_set_fifo_low() is available */ -#define HAVE_SCHED_SET_FIFO_LOW 1 +/* Reporting reservation_ww_class missing */ +/* #undef HAVE_RESERVATION_WW_CLASS_BUG */ /* sg_alloc_table_from_pages_segment() is available */ #define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 @@ -1063,26 +1121,23 @@ #define HAVE_SHMEM_READ_FOLIO 1 /* shmem_writeout() is available */ -#define HAVE_SHMEM_WRITEOUT 1 +/* #undef HAVE_SHMEM_WRITEOUT */ /* shmem_writeout() wants 3 arguments */ -/* #undef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS */ +#define HAVE_SHMEM_WRITEOUT_WANT_3_ARGS 1 /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 -/* smca_get_bank_type(x) is available */ -/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ - /* size_mul() is available */ #define HAVE_SIZE_MUL 1 +/* smca_get_bank_type(x) is available */ +/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ + /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 -/* whether sg_alloc_table_from_pages_segment() is available */ -#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 - /* enum SMCA_UMC_V2 is available */ #define HAVE_SMCA_UMC_V2 1 @@ -1098,12 +1153,15 @@ /* struct dma_fence_chain is available */ #define HAVE_STRUCT_DMA_FENCE_CHAIN 1 -/* dma_fence_chain_contained() is available */ -#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 - /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 +/* struct drm_atomic_state->plane_color_pipeline is available */ +#define HAVE_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE 1 + +/* struct drm_color_lut32 is available */ +#define HAVE_STRUCT_DRM_COLOR_LUT32 1 + /* struct drm_connector_state->colorspace is available */ #define HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE 1 @@ -1116,36 +1174,18 @@ /* struct drm_crtc_funcs->get_vblank_timestamp() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 -/* drm_crtc_funcs->{get,verify}_crc_sources() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 - -/* drm_crtc_funcs->page_flip_target() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET 1 - -/* drm_crtc_funcs->page_flip_target() wants ctx parameter */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX 1 - -/* drm_crtc_funcs->set_config() wants ctx parameter */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 - -/* crtc->funcs->set_crc_source() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 - -/* crtc->funcs->set_crc_source() wants 2 args */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE_2ARGS 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 -/* struct drm_crtc_state has flag for flip */ -#define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 - -/* struct drm_crtc_state->pageflip_flags is available */ -/* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ - /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ +/* struct drm_memory_stats is defined */ +#define HAVE_STRUCT_DRM_MEMORY_STATS 1 + +/* drm_plane_helper_funcs->atomic_async_check() have three arguments */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS 1 + /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 @@ -1153,6 +1193,9 @@ /* struct drm_plane_helper_funcs->get_scanout_buffer is available */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER 1 +/* struct __drm_private_objs_state->state_to_destroy is available */ +#define HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY 1 + /* ide->idr_base is available */ #define HAVE_STRUCT_IDE_IDR_BASE 1 @@ -1189,10 +1232,7 @@ /* totalram_pages() is available */ #define HAVE_TOTALRAM_PAGES 1 -/* __poll_t is available */ -#define HAVE_TYPE__POLL_T 1 - -/* usleep_range_stat() is available */ +/* usleep_range_state() is available */ #define HAVE_USLEEP_RANGE_STATE 1 /* vfs_iocb_iter_read() is available */ @@ -1216,26 +1256,23 @@ /* vm_fault->{address/vma} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 -/* vm_insert_pfn_prot() is available */ -/* #undef HAVE_VM_INSERT_PFN_PROT */ +/* vm_flags_{set, clear} is available */ +#define HAVE_VM_FLAGS_SET 1 /* vm_operations_struct->fault() wants 1 arg */ #define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 -/* wait_queue_entry_t exists */ -#define HAVE_WAIT_QUEUE_ENTRY 1 - /* want_init_on_free() is available */ #define HAVE_WANT_INIT_ON_FREE 1 /* ww_mutex_trylock() has context arg */ #define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 -/* is_device_page is available */ -/* #undef HAVE_ZONE_DEVICE_PUBLIC */ - /* zone_device_page_init() is available */ -#define HAVE_ZONE_DEVICE_PAGE_INIT 1 +/* #undef HAVE_ZONE_DEVICE_PAGE_INIT */ + +/* zone_device_page_init() takes 3 arguments */ +#define HAVE_ZONE_DEVICE_PAGE_INIT_3ARG 1 /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 @@ -1243,30 +1280,15 @@ /* __dma_fence_is_later() is available and has 2 args */ /* #undef HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* __dma_fence_is_later() is available and has ops arg */ -#define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 - -/* struct drm_dsc_config has member simple_422 */ -#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 - -/* drm_dsc_pps_payload_pack() is available */ -#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* __dma_fence_is_later() is available and has fence args */ +#define HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG 1 -/* drm_edid_get_monitor_name is available*/ -#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 - -/* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ -#define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 - -/* __drm_atomic_helper_crtc_destroy_state() wants 1 arg */ -#define HAVE___DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_P 1 +/* __dma_fence_is_later() is available and has ops arg */ +/* #undef HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG */ /* __drm_atomic_helper_crtc_reset() is available */ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 -/* __kthread_should_park() is available */ -/* #undef HAVE___KTHREAD_SHOULD_PARK */ - /* __sg_alloc_table_from_pages() has 9 args */ /* #undef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS */ @@ -1277,7 +1299,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.2.0" +#define PACKAGE_STRING "amdgpu-dkms 6.19.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1286,7 +1308,10 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.2.0" +#define PACKAGE_VERSION "6.19.0" + +/* drm_file->debugfs_client is available */ +#define STRUCT_DRM_FILE_DEBUGFS_CLIENT 1 #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/config/install-sh b/drivers/gpu/drm/amd/dkms/config/install-sh index 59990a1049267..ec298b5374027 100755 --- a/drivers/gpu/drm/amd/dkms/config/install-sh +++ b/drivers/gpu/drm/amd/dkms/config/install-sh @@ -1,7 +1,7 @@ #!/bin/sh # install - install a program, script, or datafile -scriptversion=2014-09-12.12; # UTC +scriptversion=2020-11-14.01; # UTC # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the @@ -69,6 +69,11 @@ posix_mkdir= # Desired mode of installed file. mode=0755 +# Create dirs (including intermediate dirs) using mode 755. +# This is like GNU 'install' as of coreutils 8.32 (2020). +mkdir_umask=22 + +backupsuffix= chgrpcmd= chmodcmd=$chmodprog chowncmd= @@ -99,18 +104,28 @@ Options: --version display version info and exit. -c (ignored) - -C install only if different (preserve the last data modification time) + -C install only if different (preserve data modification time) -d create directories instead of installing files. -g GROUP $chgrpprog installed files to GROUP. -m MODE $chmodprog installed files to MODE. -o USER $chownprog installed files to USER. + -p pass -p to $cpprog. -s $stripprog installed files. + -S SUFFIX attempt to back up existing files, with suffix SUFFIX. -t DIRECTORY install into DIRECTORY. -T report an error if DSTFILE is a directory. Environment variables override the default commands: CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG RMPROG STRIPPROG + +By default, rm is invoked with -f; when overridden with RMPROG, +it's up to you to specify -f if you want it. + +If -S is not specified, no backups are attempted. + +Email bug reports to bug-automake@gnu.org. +Automake home page: https://www.gnu.org/software/automake/ " while test $# -ne 0; do @@ -137,8 +152,13 @@ while test $# -ne 0; do -o) chowncmd="$chownprog $2" shift;; + -p) cpprog="$cpprog -p";; + -s) stripcmd=$stripprog;; + -S) backupsuffix="$2" + shift;; + -t) is_target_a_directory=always dst_arg=$2 @@ -255,6 +275,10 @@ do dstdir=$dst test -d "$dstdir" dstdir_status=$? + # Don't chown directories that already exist. + if test $dstdir_status = 0; then + chowncmd="" + fi else # Waiting for this to be detected by the "$cpprog $src $dsttmp" command @@ -271,15 +295,18 @@ do fi dst=$dst_arg - # If destination is a directory, append the input filename; won't work - # if double slashes aren't ignored. + # If destination is a directory, append the input filename. if test -d "$dst"; then if test "$is_target_a_directory" = never; then echo "$0: $dst_arg: Is a directory" >&2 exit 1 fi dstdir=$dst - dst=$dstdir/`basename "$src"` + dstbase=`basename "$src"` + case $dst in + */) dst=$dst$dstbase;; + *) dst=$dst/$dstbase;; + esac dstdir_status=0 else dstdir=`dirname "$dst"` @@ -288,27 +315,16 @@ do fi fi + case $dstdir in + */) dstdirslash=$dstdir;; + *) dstdirslash=$dstdir/;; + esac + obsolete_mkdir_used=false if test $dstdir_status != 0; then case $posix_mkdir in '') - # Create intermediate dirs using mode 755 as modified by the umask. - # This is like FreeBSD 'install' as of 1997-10-28. - umask=`umask` - case $stripcmd.$umask in - # Optimize common cases. - *[2367][2367]) mkdir_umask=$umask;; - .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; - - *[0-7]) - mkdir_umask=`expr $umask + 22 \ - - $umask % 100 % 40 + $umask % 20 \ - - $umask % 10 % 4 + $umask % 2 - `;; - *) mkdir_umask=$umask,go-w;; - esac - # With -d, create the new directory with the user-specified mode. # Otherwise, rely on $mkdir_umask. if test -n "$dir_arg"; then @@ -318,50 +334,49 @@ do fi posix_mkdir=false - case $umask in - *[123567][0-7][0-7]) - # POSIX mkdir -p sets u+wx bits regardless of umask, which - # is incompatible with FreeBSD 'install' when (umask & 300) != 0. - ;; - *) - # $RANDOM is not portable (e.g. dash); use it when possible to - # lower collision chance - tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ - trap 'ret=$?; rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null; exit $ret' 0 - - # As "mkdir -p" follows symlinks and we work in /tmp possibly; so - # create the $tmpdir first (and fail if unsuccessful) to make sure - # that nobody tries to guess the $tmpdir name. - if (umask $mkdir_umask && - $mkdirprog $mkdir_mode "$tmpdir" && - exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 - then - if test -z "$dir_arg" || { - # Check for POSIX incompatibilities with -m. - # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or - # other-writable bit of parent directory when it shouldn't. - # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. - test_tmpdir="$tmpdir/a" - ls_ld_tmpdir=`ls -ld "$test_tmpdir"` - case $ls_ld_tmpdir in - d????-?r-*) different_mode=700;; - d????-?--*) different_mode=755;; - *) false;; - esac && - $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { - ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` - test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" - } - } - then posix_mkdir=: - fi - rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" - else - # Remove any dirs left behind by ancient mkdir implementations. - rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null - fi - trap '' 0;; - esac;; + # The $RANDOM variable is not portable (e.g., dash). Use it + # here however when possible just to lower collision chance. + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + + trap ' + ret=$? + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null + exit $ret + ' 0 + + # Because "mkdir -p" follows existing symlinks and we likely work + # directly in world-writeable /tmp, make sure that the '$tmpdir' + # directory is successfully created first before we actually test + # 'mkdir -p'. + if (umask $mkdir_umask && + $mkdirprog $mkdir_mode "$tmpdir" && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + test_tmpdir="$tmpdir/a" + ls_ld_tmpdir=`ls -ld "$test_tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null + fi + trap '' 0;; esac if @@ -372,7 +387,7 @@ do then : else - # The umask is ridiculous, or mkdir does not conform to POSIX, + # mkdir does not conform to POSIX, # or it failed possibly due to a race condition. Create the # directory the slow way, step by step, checking for races as we go. @@ -401,7 +416,7 @@ do prefixes= else if $posix_mkdir; then - (umask=$mkdir_umask && + (umask $mkdir_umask && $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break # Don't fail if two instances are running concurrently. test -d "$prefix" || exit 1 @@ -434,14 +449,25 @@ do else # Make a couple of temp file names in the proper directory. - dsttmp=$dstdir/_inst.$$_ - rmtmp=$dstdir/_rm.$$_ + dsttmp=${dstdirslash}_inst.$$_ + rmtmp=${dstdirslash}_rm.$$_ # Trap to clean up those temp files at exit. trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 # Copy the file name to the temp name. - (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + (umask $cp_umask && + { test -z "$stripcmd" || { + # Create $dsttmp read-write so that cp doesn't create it read-only, + # which would cause strip to fail. + if test -z "$doit"; then + : >"$dsttmp" # No need to fork-exec 'touch'. + else + $doit touch "$dsttmp" + fi + } + } && + $doit_exec $cpprog "$src" "$dsttmp") && # and set any options; do chmod last to preserve setuid bits. # @@ -467,6 +493,13 @@ do then rm -f "$dsttmp" else + # If $backupsuffix is set, and the file being installed + # already exists, attempt a backup. Don't worry if it fails, + # e.g., if mv doesn't support -f. + if test -n "$backupsuffix" && test -f "$dst"; then + $doit $mvcmd -f "$dst" "$dst$backupsuffix" 2>/dev/null + fi + # Rename the file to the real destination. $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || @@ -481,9 +514,9 @@ do # file should still install successfully. { test ! -f "$dst" || - $doit $rmcmd -f "$dst" 2>/dev/null || + $doit $rmcmd "$dst" 2>/dev/null || { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && - { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + { $doit $rmcmd "$rmtmp" 2>/dev/null; :; } } || { echo "$0: cannot unlink or rename $dst" >&2 (exit 1); exit 1 @@ -500,9 +533,9 @@ do done # Local variables: -# eval: (add-hook 'write-file-hooks 'time-stamp) +# eval: (add-hook 'before-save-hook 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" -# time-stamp-time-zone: "UTC" +# time-stamp-time-zone: "UTC0" # time-stamp-end: "; # UTC" # End: diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 3feca735c2140..c8b68a0e2e267 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.16.0) +AC_INIT(amdgpu-dkms, 6.19.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From e574b648b5ac35fc39a04848a92bb305e5893b2c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Jan 2026 15:59:33 +0800 Subject: [PATCH 1648/2070] drm/amdkcl: test if pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy It's caused by v6.18-rc1-234-gef4a4b878124 "drm/amd: Remove redundant pm_runtime_mark_last_busy() calls" pm_runtime_put_autosuspend() include a call to pm_runtime_mark_last_busy(), so fake the inclusion. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_runtime_put_autosuspend.m4 | 10 ++++++++++ include/kcl/backport/kcl_pm_runtime.h | 19 +++++++++++++++++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 create mode 100644 include/kcl/backport/kcl_pm_runtime.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4d640199dce25..f2ddb699f6242 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -151,5 +151,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 68454fd442252..8c042af2756e6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1084,6 +1084,9 @@ /* pm_runtime_get_if_active() has two parameters */ /* #undef HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ +/* pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy */ +#define HAVE_PM_RUNTIME_PUT_AUTOSUSPEND_MARK_LAST_BUSY 1 + /* pm_runtime_resume_and_get() is available */ #define HAVE_PM_RUNTIME_RESUME_AND_GET 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fe754056fecee..3633ea7761ff9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -230,6 +230,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE + AC_AMDGPU_PM_RUNTIME_PUT_AUTOSUSPEND AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_ASSIGN_STR AC_AMDGPU_DRM_DP_MST_EDID_READ diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 new file mode 100644 index 0000000000000..ac3809d47fbd8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 @@ -0,0 +1,10 @@ +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_PUT_AUTOSUSPEND], [ + AC_MSG_CHECKING([if pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy]) + AS_IF([sed -n '/static inline int pm_runtime_put_autosuspend/,/^}/p' ${LINUX}/include/linux/pm_runtime.h | grep -q "pm_runtime_mark_last_busy"], [ + AC_MSG_RESULT([yes]) + AC_DEFINE(HAVE_PM_RUNTIME_PUT_AUTOSUSPEND_MARK_LAST_BUSY, 1, + [pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy]) + ], [ + AC_MSG_RESULT([no]) + ]) +]) diff --git a/include/kcl/backport/kcl_pm_runtime.h b/include/kcl/backport/kcl_pm_runtime.h new file mode 100644 index 0000000000000..f9c907c5ca976 --- /dev/null +++ b/include/kcl/backport/kcl_pm_runtime.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_PM_RUNTIME_BACKPORT_H +#define AMDKCL_PM_RUNTIME_BACKPORT_H + +#include +#include + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(6, 18, 0) +#if !defined(HAVE_PM_RUNTIME_PUT_AUTOSUSPEND_MARK_LAST_BUSY) +static inline int _kcl_pm_runtime_put_autosuspend(struct device *dev) +{ + pm_runtime_mark_last_busy(dev); + return pm_runtime_put_autosuspend(dev); +} +#define pm_runtime_put_autosuspend _kcl_pm_runtime_put_autosuspend +#endif +#endif + +#endif From 7c5515c235d8d73f4ece194d9089812c716f52e0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Jan 2026 17:59:53 +0800 Subject: [PATCH 1649/2070] drm/amdkcl: bypass modifing the path of .conftest.o.d After kernel 6.14, kbuild has used the relative path, the m4 detect to "./.conftest.o.d". It is modified to "/.conftest.o.d", so bypass it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 6c1a805826365..97a050953c6d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -10,7 +10,9 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ CFLAGS=$(echo $_conftest_cmd | \ cut -d ' ' -f 2- | \ - sed -e "s|\./|${LINUX_OBJ}/|g" \ + sed -e "s|\./\([[^/ ]]*\.o\.d\)|_OD_\1|g" \ + -e "s|\./|${LINUX_OBJ}/|g" \ + -e "s|_OD_|./|g" \ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") From dded5c2a1c10e49fee21f758dabc10afadc9d58a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jan 2026 14:15:50 +0800 Subject: [PATCH 1650/2070] drm/amdkcl: enable HAVE_STRUCT_XARRAY on gpu_scheduler.h HAVE_STRUCT_XARRAY is closed when drm other driver will include gpu_scheduler.h that cause intree build fail, so enbale it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/drm/gpu_scheduler.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 8dd05a0b7d1c5..a66755dec24ef 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -30,6 +30,10 @@ #include #include +#ifndef HAVE_CONFIG_H +#define HAVE_STRUCT_XARRAY 1 +#endif + #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) /** From 67660cb787db311e4e51fa06f22fb22bff363008 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 5 Jan 2026 17:50:39 +0800 Subject: [PATCH 1651/2070] drm/amdkcl: add fake rb_add function support It's caused by v6.17-rc6-1174-gc178e534fff1 drm/buddy: Optimize free block management with RB tree Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/backport_drm_buddy.h | 1 + include/kcl/kcl_rbtree.h | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h index 297561aba8334..32e17b11c0a7b 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -4,5 +4,6 @@ #include #include +#include #endif diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h index 6a0f687a0801e..7146de25b3f24 100644 --- a/include/kcl/kcl_rbtree.h +++ b/include/kcl/kcl_rbtree.h @@ -94,6 +94,31 @@ rb_add_cached(struct rb_node *node, struct rb_root_cached *tree, return leftmost ? node : NULL; } + +/** + * rb_add() - insert @node into @tree + * @node: node to insert + * @tree: tree to insert @node into + * @less: operator defining the (partial) node order + */ +static __always_inline void +rb_add(struct rb_node *node, struct rb_root *tree, + bool (*less)(struct rb_node *, const struct rb_node *)) +{ + struct rb_node **link = &tree->rb_node; + struct rb_node *parent = NULL; + + while (*link) { + parent = *link; + if (less(node, parent)) + link = &parent->rb_left; + else + link = &parent->rb_right; + } + + rb_link_node(node, parent, link); + rb_insert_color(node, tree); +} #endif #endif From 1521648ba76a2e0da0cc0a295436a8919896644f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 29 Dec 2025 16:29:29 +0800 Subject: [PATCH 1652/2070] drm/amdkcl: Fix uninitialized variable errors in m4 conftests Signed-off-by: Chengjun Yao Reviewed-by: Yang Su --- .../gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 4 ++-- .../drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/list-sort.m4 | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 32db29f7c3936..75d4ab579bdb8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,10 +5,10 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + #include ], [ struct drm_dp_aux *aux = NULL; - const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const u8 dpcd[DP_RECEIVER_CAP_SIZE] = {0}; drm_dp_link_train_channel_eq_delay(aux, dpcd); ], [drm_dp_link_train_channel_eq_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 327cd21b0200c..a9aaff5a764a2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ #include ], [ struct drm_dp_aux *aux = NULL; - const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const u8 dpcd[DP_RECEIVER_CAP_SIZE] = {0}; drm_dp_link_train_clock_recovery_delay(aux, dpcd); ], [drm_dp_link_train_clock_recovery_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 index aa7b739d04961..00495bfaa1f6b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM], [ #include ], [ list_cmp_func_t cmp = NULL; - struct list_head a, b; + struct list_head a = {0}, b = {0}; cmp(NULL, &a, &b); ], [ AC_DEFINE(HAVE_LIST_CMP_FUNC_IS_CONST_PARAM, 1, From ab405b1a5ed4c41582db57050ace3b4703bcabaa Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 21 Jan 2026 10:50:36 +0800 Subject: [PATCH 1653/2070] drm/amdkcl: correct the introduce of HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 98d2982594b7c..b25b157e9d1e1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -1,6 +1,6 @@ dnl # -dnl # v4.10-rc3-517-g7b0a89a6db9a -dnl # drm/dp: Store drm_device in MST topology manager +dnl # v5.12-rc7-1527-g98025a62cb00 +dnl # drm/dp_mst: Use Extended Base Receiver Capability DPCD space dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ From 7a49727105ea5ba60616176cf176e3fa285502db Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 4 Dec 2025 18:58:10 +0800 Subject: [PATCH 1654/2070] drm/amdkcl: fix test wether HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG is available Fix uninitialized variable error in -Werror build Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 index c034421d9cdd7..78e8648f6b335 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG], [ #include ],[ struct drm_vblank_crtc *vblank = NULL; - struct drm_vblank_crtc_config config; + struct drm_vblank_crtc_config config = {}; vblank->config = config; ],[ AC_DEFINE(HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG, 1, From 3e445b011ba5df6267b5f2ec310e555a704a13c1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 19 Jan 2024 10:02:14 +0800 Subject: [PATCH 1655/2070] drm/amdgpu: Fix possible null pointer dereference for dgma mem = bo->tbo.resource may be NULL in amdgpu_vm_bo_update. Fixes: 180253782038 ("drm/ttm: stop allocating dummy resources during BO creation") Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 1890739954f18..1ac46bb0389c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1328,7 +1328,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; - else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + else if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ From 6a3c798dad3f6d537430b6e43d57aa1b5ed76949 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Fri, 9 Jan 2026 22:19:23 +0800 Subject: [PATCH 1656/2070] drm/amdgpu: refine amdgpu_sem_create/import/export() function optimize code release logic to avoid memory leaks and imbalanced references. Signed-off-by: Yang Wang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 72 +++++++++++++++---------- 1 file changed, 44 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c index b418bfe412589..8f42a77b4b6fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -168,7 +168,7 @@ static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) idr_preload(GFP_KERNEL); spin_lock(&fpriv->sem_handles_lock); - ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + ret = idr_alloc(&fpriv->sem_handles, sem, 1, INT_MAX, GFP_NOWAIT); spin_unlock(&fpriv->sem_handles_lock); idr_preload_end(); @@ -177,6 +177,7 @@ static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) return ret; *handle = ret; + return 0; } @@ -217,98 +218,113 @@ static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, } static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, - int fd, u32 *handle) + int fd, u32 *handle) { struct file *file = fget(fd); struct amdgpu_sem *sem; struct amdgpu_sem_core *core; int ret; - if (!file) + if (unlikely(!handle || !fpriv || !file)) return -EINVAL; + if (unlikely(file->f_op != &amdgpu_sem_fops)) { + ret = -EINVAL; + goto err_file; + } + core = file->private_data; - if (!core) { - fput(file); - return -EINVAL; + if (unlikely(!core)) { + ret = -EINVAL; + goto err_file; } kref_get(&core->kref); sem = amdgpu_sem_alloc(); - if (!sem) { + if (unlikely(!sem)) { ret = -ENOMEM; - goto err_sem; + goto err_kref; } sem->base = core; idr_preload(GFP_KERNEL); spin_lock(&fpriv->sem_handles_lock); - - ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); - + ret = idr_alloc(&fpriv->sem_handles, sem, 1, INT_MAX, GFP_NOWAIT); spin_unlock(&fpriv->sem_handles_lock); idr_preload_end(); - if (ret < 0) - goto err_out; + goto err_sem; *handle = ret; fput(file); + return 0; + err_sem: - kref_put(&core->kref, amdgpu_sem_core_free); -err_out: amdgpu_sem_put(sem); +err_kref: + kref_put(&core->kref, amdgpu_sem_core_free); +err_file: fput(file); - return ret; + return ret; } static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, - u32 handle, int *fd) + u32 handle, int *fd) { struct amdgpu_sem *sem; struct amdgpu_sem_core *core; - int ret; + int new_fd, ret; sem = amdgpu_sem_lookup(fpriv, handle); - if (!sem) + if (unlikely(!sem)) return -EINVAL; core = sem->base; + if (unlikely(!core)) { + ret = -EINVAL; + goto err_put_sem; + } + kref_get(&core->kref); mutex_lock(&core->lock); if (!core->file) { core->file = anon_inode_getfile("sem_file", - &amdgpu_sem_fops, - core, 0); + &amdgpu_sem_fops, + core, 0); if (IS_ERR(core->file)) { mutex_unlock(&core->lock); - ret = -ENOMEM; - goto err_put_sem; + ret = PTR_ERR(core->file); + goto err_put_kref; } } else { get_file(core->file); } mutex_unlock(&core->lock); - ret = get_unused_fd_flags(O_CLOEXEC); - if (ret < 0) + new_fd = get_unused_fd_flags(O_CLOEXEC); + if (new_fd < 0) { + ret = new_fd; goto err_put_file; + } + + fd_install(new_fd, core->file); - fd_install(ret, core->file); + *fd = new_fd; - *fd = ret; amdgpu_sem_put(sem); return 0; err_put_file: fput(core->file); -err_put_sem: +err_put_kref: kref_put(&core->kref, amdgpu_sem_core_free); +err_put_sem: amdgpu_sem_put(sem); + return ret; } From 31bf9dc71932719dab4eee7a68cb76d97530ed3d Mon Sep 17 00:00:00 2001 From: Benjamin Welton Date: Wed, 9 Oct 2024 21:32:55 -0700 Subject: [PATCH 1657/2070] Add kfd_ioctl_profiler to contain profiler kernel driver changes kfd_ioctl_profiler takes a similar approach to that of kfd_ioctl_dbg_trap (which contains debugger related IOCTL services) where kfd_ioctl_profiler will contain all profiler related IOCTL services. The IOCTL is designed to be expanded as needed to support additional profiler functionality. The current functionality of the IOCTL is to allow for profilers which need PMC counters from GPU devices to both signal to other profilers that may be on the system that the device has active PMC profiling taking place on it (multiple PMC profilers on the same device can result in corrupted counter data) and to setup the device to allow for the collection of SQ PMC data on all queues on the device. For PMC data for the SQ block (such as SQ_WAVES) to be available to a profiler, mmPERFCOUNT_ENABLE must be set on the queues. When profiling a single process, the profiler can inject PM4 packets into each queue to turn on PERFCOUNT_ENABLE. When profiling system wide, the profiler does not have this option and must have a way to turn on profiling for queues in which it cannot inject packets into directly. Accomplishing this requires a few steps: 1. Checking if the user has the necessary permissions to profile system wide on the device. This check uses the same check that linux perf uses to determine if a user has the necessary permissions to profile at this scope (primarily if the process has CAP_SYS_PERFMON or is root). 2. Locking the device for profiling. This is done by setting a lock bit on the device struct and storing the process that locked the device. 3. Iterating all queues on the device and issuing an MQD Update to enable perfcounting on the queues. 4. Actions to cleanup if the process exits or releases the lock. The IOCTL also contains a link to the existing PC Sampling IOCTL as well. This is per a suggestion that we should potentially remove the PC Sampling IOCTL to have it be a part of the profiler IOCTL. This is a future change. In addition, we do expect to expand the profiler IOCTL to include additional profiler functionality in the future (which necessitates the use of a version number). Signed-off-by: Benjamin Welton Acked-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 84 +++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 ++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 14 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 8 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 15 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 11 +++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 +++ include/uapi/linux/kfd_ioctl.h | 30 ++++++- 12 files changed, 218 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 8dc64ee8cc7d3..e982381624ad0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include @@ -3454,6 +3455,86 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v return 0; } +static inline uint32_t profile_lock_device(struct kfd_process *p, + uint32_t gpu_id, uint32_t op) +{ + struct kfd_process_device *pdd; + struct kfd_dev *kfd; + int status = -EINVAL; + + if (!p) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + kfd = pdd->dev->kfd; + + mutex_lock(&kfd->profiler_lock); + if (op == 1) { + if (!kfd->profiler_process) { + kfd->profiler_process = p; + status = 0; + } else if (kfd->profiler_process == p) { + status = -EALREADY; + } else { + status = -EBUSY; + } + } else if (op == 0 && kfd->profiler_process == p) { + kfd->profiler_process = NULL; + status = 0; + } + mutex_unlock(&kfd->profiler_lock); + + return status; +} + +static inline int kfd_profiler_pmc(struct kfd_process *p, + struct kfd_ioctl_pmc_settings *args) +{ + struct kfd_process_device *pdd; + struct device_queue_manager *dqm; + int status; + + /* Check if we have the correct permissions. */ + if (!perfmon_capable()) + return -EPERM; + + /* Lock/Unlock the device based on the parameter given in OP */ + status = profile_lock_device(p, args->gpu_id, args->lock); + if (status != 0) + return status; + + /* Enable/disable perfcount if requested */ + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + dqm = pdd->dev->dqm; + mutex_unlock(&p->mutex); + + dqm->ops.set_perfcount(dqm, args->perfcount_enable); + return status; +} + +static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_profiler_args *args = data; + + switch (args->op) { + case KFD_IOC_PROFILER_VERSION: + args->version = KFD_IOC_PROFILER_VERSION_NUM; + return 0; + case KFD_IOC_PROFILER_PC_SAMPLE: + return kfd_ioctl_pc_sample(filep, p, &args->pc_sample); + case KFD_IOC_PROFILER_PMC: + return kfd_profiler_pmc(p, &args->pmc); + } + return -EINVAL; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3594,6 +3675,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { /* TODO: KFD_IOC_FLAG_PERFMON is not required for host-trap, disable first */ AMDKFD_IOCTL_DEF(AMDKFD_IOC_PC_SAMPLE, kfd_ioctl_pc_sample, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, + kfd_ioctl_profiler, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 4198dd810f12e..71abdad675b23 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -953,6 +953,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -989,6 +992,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); + mutex_destroy(&kfd->profiler_lock); } kfree(kfd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index c2d76db378a39..cec471ce986d1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -331,6 +331,29 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + pqm_update_mqd(qpd->pqm, q->properties.queue_id, + &minfo); + } + } + dqm_unlock(dqm); +} + static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -2992,6 +3015,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -3012,6 +3036,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 607098044ea7b..9e00a840704f9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -200,6 +200,8 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); + void (*set_perfcount)(struct device_queue_manager *dqm, + int enable); }; struct device_queue_manager_asic_ops { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 0186b3de67c00..729543bc44d11 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -124,10 +124,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -142,6 +141,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -221,6 +226,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index c9e3973667824..7d33ee824417e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -164,10 +164,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -182,6 +181,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -259,6 +263,12 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index 3bbc2648f51d0..cc2da8c6c84bd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -139,10 +139,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -157,6 +156,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index a91bb03519636..6d5687bdfcf90 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -264,10 +264,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) { + if (q->tba_addr) m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); - } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -282,6 +281,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -367,6 +371,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 391a19d95c2c2..2a3fd7042b0e6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -188,6 +188,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -272,6 +277,12 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 786e9963be6f8..f336aff63665b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -443,6 +443,11 @@ struct kfd_dev { int kfd_dev_lock; atomic_t kfd_processes_count; + + /* Lock for profiler process */ + struct mutex profiler_lock; + /* Process currently holding the lock */ + struct kfd_process *profiler_process; }; struct kfd_ipc_obj; @@ -626,6 +631,8 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ + UPDATE_FLAG_PERFCOUNT_ENABLE = 5, + UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 279982cd156ec..47cc8b327ffe0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1098,6 +1098,16 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } +static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->dev->kfd->profiler_lock); + if (pdd->dev->kfd->profiler_process == p) { + pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + pdd->dev->kfd->profiler_process = NULL; + } + mutex_unlock(&pdd->dev->kfd->profiler_lock); +} + static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1110,6 +1120,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + kfd_process_profiler_release(p, pdd); kfd_pc_sample_release(pdd); kfd_spm_release_process_device(pdd); diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index f3b0590c91f61..ae77180bbe75d 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1746,6 +1746,31 @@ struct kfd_ioctl_pc_sample_args { __u32 version; }; +#define KFD_IOC_PROFILER_VERSION_NUM 1 +enum kfd_profiler_ops { + KFD_IOC_PROFILER_PMC = 0, + KFD_IOC_PROFILER_PC_SAMPLE = 1, + KFD_IOC_PROFILER_VERSION = 2, +}; + +/** + * Enables/Disables GPU Specific profiler settings + */ +struct kfd_ioctl_pmc_settings { + __u32 gpu_id; /* This is the user_gpu_id */ + __u32 lock; /* Lock GPU for Profiling */ + __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ +}; + +struct kfd_ioctl_profiler_args { + __u32 op; /* kfd_profiler_op */ + union { + struct kfd_ioctl_pc_sample_args pc_sample; + struct kfd_ioctl_pmc_settings pmc; + __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ + }; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1891,7 +1916,10 @@ struct kfd_ioctl_pc_sample_args { #define AMDKFD_IOC_PC_SAMPLE \ AMDKFD_IOWR(0x85, struct kfd_ioctl_pc_sample_args) +#define AMDKFD_IOC_PROFILER \ + AMDKFD_IOWR(0x86, struct kfd_ioctl_profiler_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x86 +#define AMDKFD_COMMAND_END_2 0x87 #endif From 182a8c02cb088106e39a0b4a6eb660f40dcd9fe7 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 21 Jan 2025 14:29:02 +0800 Subject: [PATCH 1658/2070] drm/amdkcl: Fix kfd->profiler_lock Initialization Order [Why] In GFX version < 11.0.0 (like navi22), the origin patch will cause kernel (version < 4.9) hangs due to Uninitialized mutex in kfd_init_node(). Since v4.9-rc2-42-g3ca0ff571b09 ("locking/mutex: Rework mutex::owner"), it has increased the tolerance of mutex locks, preventing the kernel hang. But it remains an incorrect usage. Here are the call paths: kgd2kfd_device_init() kfd_init_node() kfd_resume() start_cpsch() pm_init() kernel_queue_init() kq_initialize() init_mqd() mutex_lock(&mm->dev->kfd->profiler_lock) mutex_init(&kfd->profiler_lock) [How] Reorder the mutex_init() before kfd_init_node() to fix it. Fixes: b58289f0abf7 ("Add kfd_ioctl_profiler to contain profiler kernel driver changes") Signed-off-by: chengjya Signed-off-by: Bob Zhou Reviewed-by: Benjamin Welton --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 71abdad675b23..59958b1888889 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -953,9 +953,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); - kfd->profiler_process = NULL; - mutex_init(&kfd->profiler_lock); - kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); From f4db717079f176b1529db441e27b5dc9ed26197d Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Tue, 22 Jul 2025 16:24:17 -0400 Subject: [PATCH 1659/2070] drm/amdkfd: Add AMD Infinity Storage (AIS) support Init: Driver during load calls pci_p2pdma_add_resource which creates struct MEMORY_DEVICE_PCI_P2PDMA pages for the whole VRAM region. Operation: Add ioctl AMDKFD_IOC_AIS_OP that provides support for transferring data directly from GPU VRAM to storage device. The storage device has to backed by a PCI device capable of carrying out P2P. Driver (amdgpu) fills in block I/O vector bio_vec with VRAM P2P pages and requests the block device to carry-out out direct DMA. Current support is limited to dGPUs with large BAR v2: Add in/out ioctl arguments to provide more status information to user space. Signed-off-by: Harish Kasiviswanathan Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 265 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 94 ++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 + include/uapi/linux/kfd_ioctl.h | 66 +++++- 6 files changed, 438 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ais.c diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index f03e99f6f3443..d8e20df442622 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -66,7 +66,8 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o \ - $(AMDKFD_PATH)/kfd_pc_sampling.o + $(AMDKFD_PATH)/kfd_pc_sampling.o \ + $(AMDKFD_PATH)/kfd_ais.o ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c new file mode 100644 index 0000000000000..03e76626535c3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include +#include +#include +#include +#include + +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +/* + * get_pci_dev_from_file - Get the PCI device that is hosting the file. + * For e.g., the NVME PCI device that is hosting the file. + * + * @file: The file pointer from which to derive the PCI device. + * Returns: Pointer to the PCI device if found, NULL otherwise. + */ +static struct pci_dev *get_pci_dev_from_file(struct file *file) +{ + struct device *dev; + struct pci_dev *pdev = NULL; + + if (!file->f_path.mnt || !file->f_path.mnt->mnt_sb || + !file->f_path.mnt->mnt_sb->s_bdev) { + pr_err("Invalid file path or mount point\n"); + return NULL; + } + + dev = file->f_path.mnt->mnt_sb->s_bdev->bd_device.parent; + if (!dev) { + pr_debug("No parent device found for the file\n"); + return NULL; + } + + /* Traverse up the device hierarchy to find a PCI device */ + while (dev && !dev_is_pci(dev)) + dev = dev->parent; + + if (dev && dev_is_pci(dev)) + pdev = to_pci_dev(dev); + + + return pdev; +} + +static struct bio_vec *amdgpu_init_bvec(struct sg_table *sgt, uint64_t size, + unsigned int *nr_segs) +{ + struct scatterlist *sg; + struct bio_vec *bvec; + uint64_t sg_len; + int64_t sg_offset = 0; + struct page *page; + unsigned int i, k = 0; + + bvec = kvcalloc(sgt->nents, sizeof(*bvec), GFP_KERNEL); + if (!bvec) + return NULL; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + page = pfn_to_page(PHYS_PFN(sg_dma_address(sg))); + if (!page || !is_pci_p2pdma_page(page)) { + /* If the page is not PCI P2P, we cannot use it */ + pr_err("Invalid PCI P2P page!\n"); + kvfree(bvec); + return NULL; + } + sg_offset = sg_dma_address(sg) - __pfn_to_phys(page_to_pfn(page)); + if (sg_offset < 0 || sg_offset >= sg->length) { + pr_err("Invalid sg_offset: %lld\n", sg_offset); + kvfree(bvec); + return NULL; + } + + sg_len = min(sg->length, size); + pr_debug("sg[%d] offset:%llx, size:%llx\n", i, sg_offset, sg_len); + + bvec[k].bv_page = page; + bvec[k].bv_len = sg_len; + bvec[k].bv_offset = sg_offset; + k++; + + size -= sg_len; + if ((int64_t)size <= 0) + break; + } + + *nr_segs = k; + return bvec; +} + +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +int kfd_ais_init(struct amdgpu_device *adev) +{ +#ifdef CONFIG_PCI_P2PDMA + int ret; + unsigned long size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); + bool is_large_bar = adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + + /* AIS support limited to large BAR dGPUs */ + if (adev->flags & AMD_IS_APU || adev->gmc.xgmi.connected_to_cpu || !is_large_bar) { + dev_dbg(adev->dev, "AIS: only supported for large BAR dGPU\n"); + return 0; + } + + ret = pci_p2pdma_add_resource(adev->pdev, 0 /*bar*/, 0 /*whole VRAM*/, + 0 /*offset*/); + if (ret) { + dev_dbg(adev->dev, "AIS: Failed to add PCI P2PDMA resource for VRAM %d\n", ret); + return 0; + } + dev_dbg(adev->dev, "AIS: reserve %ldMB system memory for VRAM (P2P) pages struct\n", + AIS_P2P_PAGE_STRUCT_SIZE(size) >> 20); + + amdgpu_amdkfd_reserve_system_mem(AIS_P2P_PAGE_STRUCT_SIZE(size)); + dev_info(adev->dev, "AIS: registered %ldMB device memory\n", size >> 20); + + adev->kfd.dev->ais_initialized = true; +#else + dev_dbg(adev->dev, "AIS: not supported. Check CONFIG_PCI_P2PDMA\n"); +#endif + return 0; +} + +void kfd_ais_deinit(struct amdgpu_device *adev) +{ + if (adev->kfd.dev->ais_initialized) { + unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); + struct page *p2p_page = NULL; + + if (pfn_valid(pci_start_pfn)) { + p2p_page = pfn_to_page(pci_start_pfn); + if (p2p_page && is_pci_p2pdma_page(p2p_page) && + page_pgmap(p2p_page)) + devm_memunmap_pages(&adev->pdev->dev, page_pgmap(p2p_page)); + } + adev->kfd.dev->ais_initialized = false; + } +} + +int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, + struct kfd_ais_in_args *in, uint64_t *size_copied) +{ + struct file *filep; + struct pci_dev *pdev; + struct sg_table *sgt; + int nr_segs = 0, retry = 3; + struct iov_iter iter; + struct kiocb kiocb; + struct bio_vec *bvec; + loff_t cur_pos; + int ret = 0; + bool is_read = (in->op == KFD_IOC_AIS_READ); + + /* For now support only page-aligned offsets and sizes. It could be + * improved to fs block size in the future + */ + if (!PAGE_ALIGNED(in->file_offset) || !PAGE_ALIGNED(in->size)) + return -EINVAL; + + filep = fget((unsigned int)in->fd); + if (!filep) + return -EBADF; + + pdev = get_pci_dev_from_file(filep); + if (!pdev) { + ret = -ENODEV; + goto out; + } + + if (pci_p2pdma_distance(pdev, adev->dev, false) < 0) { + dev_info(adev->dev, "DMA-BUF p2p not accessible!\n"); + ret = -ENODEV; + goto out; + } + + if (WARN_ON(bo->preferred_domains != AMDGPU_GEM_DOMAIN_VRAM)) { + ret = -EINVAL; + goto out; + } + /* Use NULL instead of peer pdev. This is deliberate so that + * sg_dma_address is set to physical address instead of dma mapped + * address. This helps in getting struct p2p_page that bvec needs. + * This should work irrespective of iommu + */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table(adev, bo, 0, in->handle_offset, + in->size, NULL, DMA_BIDIRECTIONAL, &sgt); + if (ret) { + dev_err(adev->dev, "AIS: failed to get SG table\n"); + goto out; + } + + bvec = amdgpu_init_bvec(sgt, in->size, &nr_segs); + if (!bvec) { + ret = -ENOMEM; + goto put_sg; + } + + iov_iter_bvec(&iter, is_read ? ITER_DEST : ITER_SOURCE, bvec, nr_segs, in->size); + init_sync_kiocb(&kiocb, filep); + kiocb.ki_pos = cur_pos = in->file_offset; + if (filep->f_flags & O_DIRECT) + kiocb.ki_flags |= IOCB_DIRECT; + + *size_copied = 0; + while (kiocb.ki_pos < in->file_offset + in->size) { + if (is_read) + ret = vfs_iocb_iter_read(filep, &kiocb, &iter); + else + ret = vfs_iocb_iter_write(filep, &kiocb, &iter); + if (ret <= 0) { + dev_err(adev->dev, "AIS: vfs transfer failed %d\n", ret); + break; + } else if (cur_pos == kiocb.ki_pos) { + /* No progress made, retry */ + if (retry-- > 0) { + dev_warn(adev->dev, "AIS: vfs transfer stalled, retrying...\n"); + continue; + } + dev_err(adev->dev, "AIS: vfs transfer stalled, giving up\n"); + ret = -EIO; + break; + } + cur_pos = kiocb.ki_pos; + *size_copied += ret; + } + + if (ret > 0) + dev_dbg(adev->dev, "AIS: vfs transfer %llu bytes\n", *size_copied); + + kvfree(bvec); +put_sg: + amdgpu_amdkfd_gpuvm_put_sg_table(bo, NULL, DMA_BIDIRECTIONAL, sgt); +out: + fput(filep); + return ret < 0 ? ret : 0; + +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e982381624ad0..2e5f8cc2fa6c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3535,6 +3535,97 @@ static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *d return -EINVAL; } +static int kfd_ioctl_ais(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_ais_args *args = data; + struct kfd_ais_in_args *in = &args->in; + struct kfd_ais_out_args __user *out = &args->out, out_args = {0}; + struct kfd_process_device *pdd; + struct kfd_node *dev; + struct kfd_bo *buf_obj; + struct amdgpu_bo *bo; + int err; + + if (in->op != KFD_IOC_AIS_READ && in->op != KFD_IOC_AIS_WRITE) { + pr_debug("AIS: Invalid operation: %d\n", in->op); + err = -EINVAL; + goto err_inval; + } + + if (in->fd < 0) { + pr_debug("AIS: fd: %d\n", in->fd); + err = -EINVAL; + goto err_inval; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(in->handle)); + if (!pdd) { + pr_debug("AIS: Could not find gpu id 0x%llx\n", GET_GPU_ID(in->handle)); + err = -EINVAL; + goto err_pdd; + } + dev = pdd->dev; + if (!dev->kfd->ais_initialized) { + dev_dbg(dev->adev->dev, "AIS: is not initialized for device\n"); + err = -ENODEV; + goto err_pdd; + } + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + err = -ESRCH; + goto err_bind_process; + } + + buf_obj = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(in->handle)); + if (!buf_obj) { + err = -EINVAL; + goto err_bind_process; + } + bo = ((struct kgd_mem *)buf_obj->mem)->bo; + + /* Only VRAM BOs are supported */ + if (((struct kgd_mem *)buf_obj->mem)->domain != AMDGPU_GEM_DOMAIN_VRAM) { + dev_dbg(dev->adev->dev, "AIS: BO not in VRAM, but in %d\n", + ((struct kgd_mem *)buf_obj)->domain); + err = -EINVAL; + goto err_bind_process; + } + + /* + * Concurrent data transfers on the same buffer is allowed. Pin it before + * releasing the lock. This ensures that BO remains valid when file system + * is accessing it + */ + err = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_VRAM); + if (err) { + pr_err("Pinning of buffer failed.\n"); + goto err_bind_process; + } + + mutex_unlock(&p->mutex); + + err = kfd_ais_rw_file(dev->adev, bo, in, &out_args.size_copied); + if (err) { + pr_err("Failed to %s AIS file: %d\n", + in->op == KFD_IOC_AIS_READ ? "read" : "write", err); + out_args.status = err; + } + + amdgpu_amdkfd_gpuvm_unpin_bo(bo); + memcpy(out, &out_args, sizeof(out_args)); + return err; + +err_pdd: +err_bind_process: + mutex_unlock(&p->mutex); +err_inval: + out_args.status = err; + memcpy(out, &out_args, sizeof(out_args)); + return err; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3678,6 +3769,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, kfd_ioctl_profiler, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_AIS_OP, + kfd_ioctl_ais, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 59958b1888889..70017594a08e6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -953,6 +953,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd_ais_init(kfd->adev); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -982,6 +984,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, void kgd2kfd_device_exit(struct kfd_dev *kfd) { if (kfd->init_complete) { + kfd_ais_deinit(kfd->adev); /* Cleanup KFD nodes */ kfd_cleanup_nodes(kfd, kfd->num_nodes); /* Cleanup common/shared resources */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f336aff63665b..062691135a642 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -448,6 +448,9 @@ struct kfd_dev { struct mutex profiler_lock; /* Process currently holding the lock */ struct kfd_process *profiler_process; + + /* flag for AIS */ + bool ais_initialized; }; struct kfd_ipc_obj; @@ -1754,6 +1757,12 @@ static inline bool kfd_is_first_node(struct kfd_node *node) return (node == node->kfd->nodes[0]); } +/* AIS Support */ +int kfd_ais_init(struct amdgpu_device *adev); +void kfd_ais_deinit(struct amdgpu_device *adev); +int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, + struct kfd_ais_in_args *in, uint64_t *size_copied); + /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index ae77180bbe75d..c156a2880a579 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1771,6 +1771,67 @@ struct kfd_ioctl_profiler_args { }; }; +/** + * kfd_ais_ops - AIS ioctl operations + * + * @KFD_IOC_AIS_READ: Direct IO read from a file into VRAM + * @KFD_IOC_AIS_WRITE: Direct IO write into a file into VRAM + */ +enum kfd_ais_ops { + KFD_IOC_AIS_READ = 1, + KFD_IOC_AIS_WRITE = 2, +}; + +/** + * kfd_ais_in_args + * + * Arguments for AMDKFD_IOC_AIS_OP + * AIS (AMD Infinity Storage) operations. + * + * @op (IN) - kfd_ais_ops + * @fd (IN) - file descriptor of the file to read/write + * @handle (IN) - memory handle returned by alloc. Should be mapped to + * the GPU with AMDKFD_IOC_MAP_MEMORY_TO_GPU. + * @handle_offset (IN) - offset into the allocated memory to read/write + * @file_offset (IN) - offset from the beginning of the file to read/write + * @size (IN) - size in bytes to read/write + */ + +struct kfd_ais_in_args { + __u64 handle; /* to KFD */ + __u64 handle_offset; /* to KFD */ + __s64 file_offset; /* to KFD */ + __u64 size; /* to KFD */ + __u32 op; /* to KFD */ + __s32 fd; /* to KFD */ +}; + +/** + * kfd_ais_out_args + * + * @size_copied (OUT) KFD returns number of bytes transferred + * @status (OUT) 0 for success and -ve error values if failure + */ +struct kfd_ais_out_args { + __u64 size_copied; /* from KFD */ + __s32 status; /* from KFD */ + __s32 pad; /* unused */ +}; + +/** + * Arguments for AMDKFD_IOC_AIS_OP + * AIS (AMD Infinity Storage) operations. + * See @kfd_ais_in_args and @kfd_ais_out_args + */ + +struct kfd_ioctl_ais_args { + union { + struct kfd_ais_in_args in; + struct kfd_ais_out_args out; + }; +}; + + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1919,7 +1980,10 @@ struct kfd_ioctl_profiler_args { #define AMDKFD_IOC_PROFILER \ AMDKFD_IOWR(0x86, struct kfd_ioctl_profiler_args) +#define AMDKFD_IOC_AIS_OP \ + AMDKFD_IOWR(0x87, struct kfd_ioctl_ais_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x87 +#define AMDKFD_COMMAND_END_2 0x88 #endif From 49f4f7a7780f6694e605844d6ee988e185400873 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 3 Sep 2025 17:24:54 +0800 Subject: [PATCH 1660/2070] drm/amdkcl: wrap code under HAVE_BLOCK_DEVICE_BD_DEVICE it's caused by 7f12d388fc290 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Yang Su Reviewed-by: Bob Zhou drm/amdkcl: fix check struct block_device has member named 'bd_device' Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 7 +++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/blk_types.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/blk_types.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 03e76626535c3..73d50ecf184f7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -28,7 +28,7 @@ #include #include #include - +#include /* Each VRAM page uses sizeof(struct page) on system memory */ #define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) @@ -49,8 +49,11 @@ static struct pci_dev *get_pci_dev_from_file(struct file *file) pr_err("Invalid file path or mount point\n"); return NULL; } - +#ifdef HAVE_BLOCK_DEVICE_BD_DEVICE dev = file->f_path.mnt->mnt_sb->s_bdev->bd_device.parent; +#else + dev = disk_to_dev(file->f_path.mnt->mnt_sb->s_bdev->bd_disk)->parent; +#endif if (!dev) { pr_debug("No parent device found for the file\n"); return NULL; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8c042af2756e6..289df5a03545a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -79,6 +79,9 @@ /* bitmap_to_arr32() is available */ #define HAVE_BITMAP_TO_ARR32 1 +/* struct block_device has member named 'bd_device' */ +#define HAVE_BLOCK_DEVICE_BD_DEVICE 1 + /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 new file mode 100644 index 0000000000000..d6d3e21a7efea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.10-rc4-97-g0d02129e76ed +dnl # block: merge struct block_device and struct hd_struct +dnl # +AC_DEFUN([AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct block_device *device = NULL; + struct device dev = {}; + device->bd_device = dev; + ], [ + AC_DEFINE(HAVE_BLOCK_DEVICE_BD_DEVICE, 1, + [struct block_device has member named 'bd_device']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3633ea7761ff9..cb522200ea7b8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -274,6 +274,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED + AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT From 49020ee5bad665df7689641e050901050563f986 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 4 Sep 2025 11:09:27 +0800 Subject: [PATCH 1661/2070] drm/amdkcl: wrap code under HAVE_PAGE_PGMAP it's caused by 7f12d388fc290 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 8 +++++++- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/page_flag.m4 | 16 ++++++++++++++++ 4 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/page_flag.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 73d50ecf184f7..f4dd34909cfd4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -160,10 +160,16 @@ void kfd_ais_deinit(struct amdgpu_device *adev) if (pfn_valid(pci_start_pfn)) { p2p_page = pfn_to_page(pci_start_pfn); +#ifdef HAVE_PAGE_PGMAP if (p2p_page && is_pci_p2pdma_page(p2p_page) && page_pgmap(p2p_page)) devm_memunmap_pages(&adev->pdev->dev, page_pgmap(p2p_page)); - } +#else + if (p2p_page && is_pci_p2pdma_page(p2p_page) && + p2p_page->pgmap) + devm_memunmap_pages(&adev->pdev->dev, p2p_page->pgmap); +#endif + } adev->kfd.dev->ais_initialized = false; } } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 289df5a03545a..eb12cab4cf925 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -752,7 +752,7 @@ #define HAVE_DRM_VBLANK_CRTC_CONFIG 1 /* struct vblank->config is available */ -/* #undef HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG */ +#define HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG 1 /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ @@ -1045,6 +1045,9 @@ /* class_create has one argument */ #define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 +/* page_pgmap() is available */ +#define HAVE_PAGE_PGMAP 1 + /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cb522200ea7b8..939d56b40ae1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -275,6 +275,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE + AC_AMDGPU_PAGE_PGMAP AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT diff --git a/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 b/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 new file mode 100644 index 0000000000000..411f154c31e59 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-rc6-302-g82ba975e4c43 +dnl # mm: allow compound zone device pages +dnl # +AC_DEFUN([AC_AMDGPU_PAGE_PGMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + page_pgmap(NULL); + ], [ + AC_DEFINE(HAVE_PAGE_PGMAP, 1, + [page_pgmap() is available]) + ]) + ]) +]) From 63794d691f9da74286eaf8193c03c0e2c00b7343 Mon Sep 17 00:00:00 2001 From: Benjamin Welton Date: Mon, 6 Jan 2025 10:30:01 -0800 Subject: [PATCH 1662/2070] amd/amdkfd: fix double lock aquisition in set_perfcount Seperates out locking from update_queue to allow updating of queues by code already holding the mqd lock. Fixes a hang in set_perfcount. This change was in the original mailing list commit for set_perfcount but was not included in gerrit. Fixes: b58289f0abf7 ("Add kfd_ioctl_profiler to contain profiler kernel driver changes") Signed-off-by: Benjamin Welton Acked-by: Kent Russell Change-Id: Ica4a5881c357a67dfe0922b39574e25f07718687 --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 74 ++++++++++--------- 1 file changed, 40 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index cec471ce986d1..2a24e2deedadf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -331,29 +331,6 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } -static void set_perfcount(struct device_queue_manager *dqm, int enable) -{ - struct device_process_node *cur; - struct qcm_process_device *qpd; - struct queue *q; - struct mqd_update_info minfo = { 0 }; - - if (!dqm) - return; - - minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : - UPDATE_FLAG_PERFCOUNT_DISABLE); - dqm_lock(dqm); - list_for_each_entry(cur, &dqm->queues, list) { - qpd = cur->qpd; - list_for_each_entry(q, &qpd->queues_list, list) { - pqm_update_mqd(qpd->pqm, q->properties.queue_id, - &minfo); - } - } - dqm_unlock(dqm); -} - static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -991,7 +968,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, return retval; } -static int update_queue(struct device_queue_manager *dqm, struct queue *q, +static int update_queue_locked(struct device_queue_manager *dqm, struct queue *q, struct mqd_update_info *minfo) { int retval = 0; @@ -1000,11 +977,9 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, struct kfd_process_device *pdd; bool prev_active = false; - dqm_lock(dqm); pdd = kfd_get_process_device_data(q->device, q->process); if (!pdd) { - retval = -ENODEV; - goto out_unlock; + return -ENODEV; } mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( q->properties.type)]; @@ -1022,13 +997,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, /* queue is reset so inaccessable */ if (pdd->has_reset_queue) { - retval = -EACCES; - goto out_unlock; + return -EACCES; } if (retval) { dev_err(dev, "unmap queue failed\n"); - goto out_unlock; + return retval; } } else if (prev_active && (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || @@ -1037,7 +1011,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, if (!dqm->sched_running) { WARN_ONCE(1, "Update non-HWS queue while stopped\n"); - goto out_unlock; + return retval; } retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, @@ -1047,7 +1021,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); if (retval) { dev_err(dev, "destroy mqd failed\n"); - goto out_unlock; + return retval; } } @@ -1095,11 +1069,43 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, &q->properties, current->mm); } -out_unlock: - dqm_unlock(dqm); return retval; } +static int update_queue(struct device_queue_manager *dqm, struct queue *q, + struct mqd_update_info *minfo) +{ + int retval; + + dqm_lock(dqm); + retval = update_queue_locked(dqm, q, minfo); + dqm_unlock(dqm); + + return retval; +} + +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + update_queue_locked(dqm, q, &minfo); + } + } + dqm_unlock(dqm); +} + /* suspend_single_queue does not lock the dqm like the * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should * lock the dqm before calling, and unlock after calling. From fffa453967d7b649ef1b1bd9c9754d708234eb2a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Feb 2026 15:22:06 +0800 Subject: [PATCH 1663/2070] drm/amdkcl: wrap code under HAVE_PAGE_PGMAP It's caused by 12b2285bf3d14372238d36215b73af02ac3bdfc1 "mm/zone_device: reinitialize large zone device private folios" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 8cde3b0a48484..3ea3c56d4cd08 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -227,7 +227,11 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; +#ifdef HAVE_PAGE_PGMAP zone_device_page_init(page, page_pgmap(page), 0); +#else + zone_device_page_init(page, page->pgmap, 0); +#endif } static void From be0451415f7f5eb41030e3df9cbc5a0f56e7d9c6 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 24 Feb 2026 10:45:38 +0800 Subject: [PATCH 1664/2070] drm/amdkcl: wrap code under macro DRM_FORMAT_XRGB16161616 It's caused by the commit: 65666170f01e "drm/amd/display: Use same max plane scaling limits for all 64 bpp formats" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 5e41385820683..b5963a7d43222 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1085,10 +1085,12 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, case DRM_FORMAT_ARGB16161616F: case DRM_FORMAT_XBGR16161616F: case DRM_FORMAT_ABGR16161616F: +#ifdef DRM_FORMAT_XRGB16161616 case DRM_FORMAT_XRGB16161616: case DRM_FORMAT_ARGB16161616: case DRM_FORMAT_XBGR16161616: case DRM_FORMAT_ABGR16161616: +#endif *max_upscale = plane_cap->max_upscale_factor.fp16; *min_downscale = plane_cap->max_downscale_factor.fp16; break; From 7749159a996f11a8cdd4d7f79b7781ca0a274e8b Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 21 Jan 2026 14:56:38 +0800 Subject: [PATCH 1665/2070] drm/amdkcl: add more info about kcl_mmput_async Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 index bdfb1256a9ccb..cd095610a3c31 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -2,6 +2,7 @@ dnl # dnl # v4.14-rc3-117-ga1b2289cef92 android: binder: drop lru lock in isolate callback dnl # v4.13-4372-g212925802454 mm: oom: let oom_reap_task and exit_mmap run concurrently dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from the oom reaper context +dnl # v6.0-rc1-16-g85eaeb5058f0 IB/core: Fix a nested dead lock as part of ODP flow (export symbol) dnl # AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ AC_KERNEL_DO_BACKGROUND([ From 596d32729c8a5e2ac8fa5d6c0abf19e12b65a50e Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Feb 2026 10:52:27 +0800 Subject: [PATCH 1666/2070] drm/amdkcl: test whether pci_dev_is_disconnected is available It's caused by the commit: ae66e78f26 "drm/amd: Fix hang on amdgpu unload by using pci_dev_is_disconnected()" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pci_dev_is_disconnected.m4 | 15 +++++++++++++++ include/kcl/kcl_pci.h | 8 ++++++++ 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index eb12cab4cf925..0803565edd505 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1057,6 +1057,9 @@ /* pci_dev_id() is available */ #define HAVE_PCI_DEV_ID 1 +/* pci_dev_is_disconnected is available */ +#define HAVE_PCI_DEV_IS_DISCONNECTED 1 + /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 939d56b40ae1e..6093a5f8f7d9d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -287,6 +287,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED AC_AMDGPU_KFD_PEERDIRECT_SUPPORT AC_AMDGPU_SYSTEM_PERCPU_WQ + AC_AMDGPU_PCI_DEV_IS_DISCONNECTED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 new file mode 100644 index 0000000000000..9201093cd8f20 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v6.8-rc3-9-g39714fd73c6b +dnl # PCI: Make pci_dev_is_disconnected() helper public for other drivers +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_IS_DISCONNECTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_dev_is_disconnected(NULL); + ], [ + AC_DEFINE(HAVE_PCI_DEV_IS_DISCONNECTED, 1, [pci_dev_is_disconnected is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 96089d809248d..2f3db90f1841e 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -216,6 +216,14 @@ static inline struct pci_dev *pci_get_base_class(unsigned int class, #define PCI_IRQ_INTX PCI_IRQ_LEGACY #endif +#ifndef HAVE_PCI_DEV_IS_DISCONNECTED +static inline bool kcl_pci_dev_is_disconnected(const struct pci_dev *dev) +{ + return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; +} +#define pci_dev_is_disconnected kcl_pci_dev_is_disconnected +#endif + #ifndef HAVE_PCI_REBAR_GET_MAX_SIZE static inline int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) { From eccad9e7e0e1613be3ebdb64925cf0ea5ccd12c0 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 12 Nov 2025 12:18:14 -0500 Subject: [PATCH 1667/2070] drm/amdkfd: Fix AIS deinit warnings Device manager releases device-specific resources when a driver disconnects from a device, devm_memunmap_pages is redundant. It causes below warning trace when module is removed Call Trace: dump_stack_lvl+0x76/0xa0 dump_stack+0x10/0x20 bad_page+0x76/0x120 free_page_is_bad_report+0x86/0xa0 free_unref_page_prepare+0x279/0x3d0 free_unref_page+0x34/0x180 __free_pages+0x112/0x130 free_pages+0x3d/0x60 free_pagetable+0xc4/0xe0 remove_pud_table+0x1c3/0x270 remove_p4d_table+0xf8/0x1b0 remove_pagetable+0xd7/0x160 arch_remove_memory+0x3d/0x50 memunmap_pages+0xbe/0x300 devm_memremap_pages_release+0xe/0x20 devm_action_release+0x15/0x30 release_nodes+0x45/0xd0 devres_release_all+0x97/0xe0 device_unbind_cleanup+0x12/0x80 device_release_driver_internal+0x230/0x270 driver_detach+0x4a/0xa0 bus_remove_driver+0x83/0x110 driver_unregister+0x2f/0x60 pci_unregister_driver+0x40/0x90 amdgpu_exit+0x15/0x3b [amdgpu] __do_sys_delete_module.constprop.0+0x1a3/0x300 __x64_sys_delete_module+0x12/0x20 x64_sys_call+0x14e9/0x24b0 do_syscall_64+0x81/0x170 entry_SYSCALL_64_after_hwframe+0x78/0x80 Fixes: b70e506746de ("drm/amdkfd: Add AMD Infinity Storage (AIS) support") Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index f4dd34909cfd4..4533393b02249 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -154,24 +154,7 @@ int kfd_ais_init(struct amdgpu_device *adev) void kfd_ais_deinit(struct amdgpu_device *adev) { - if (adev->kfd.dev->ais_initialized) { - unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); - struct page *p2p_page = NULL; - - if (pfn_valid(pci_start_pfn)) { - p2p_page = pfn_to_page(pci_start_pfn); -#ifdef HAVE_PAGE_PGMAP - if (p2p_page && is_pci_p2pdma_page(p2p_page) && - page_pgmap(p2p_page)) - devm_memunmap_pages(&adev->pdev->dev, page_pgmap(p2p_page)); -#else - if (p2p_page && is_pci_p2pdma_page(p2p_page) && - p2p_page->pgmap) - devm_memunmap_pages(&adev->pdev->dev, p2p_page->pgmap); -#endif - } - adev->kfd.dev->ais_initialized = false; - } + adev->kfd.dev->ais_initialized = false; } int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, From e472ac02f3f9589e7bbd7a4632dc51c4b3accfb9 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 19 Nov 2025 20:19:22 +0530 Subject: [PATCH 1668/2070] drm/amdkfd: Disable AIS on virtualized environment AIS is not supported on virtualization yet. Signed-off-by: Lijo Lazar Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 4533393b02249..2742901b55146 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -127,6 +127,11 @@ int kfd_ais_init(struct amdgpu_device *adev) bool is_large_bar = adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + if (amdgpu_sriov_vf(adev)) { + dev_dbg(adev->dev, "AIS: not supported on SRIOV\n"); + return 0; + } + /* AIS support limited to large BAR dGPUs */ if (adev->flags & AMD_IS_APU || adev->gmc.xgmi.connected_to_cpu || !is_large_bar) { dev_dbg(adev->dev, "AIS: only supported for large BAR dGPU\n"); From 27b225c14a3990550f5b73523e02ddc54a5ab12d Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Thu, 13 Nov 2025 16:20:27 -0500 Subject: [PATCH 1669/2070] drm/amdkfd: Don't remap PCI P2P range Commit 502360c9a391 ("drm/amdkfd: Fix AIS deinit warnings") removed devm_memunmap_pages from kfd_ais_deinit(). kfd_ais_init() gets called again when compute or memory partitions are changed. Don't remap P2P range again if P2P range has already been initialized. Fixes: 502360c9a391 ("drm/amdkfd: Fix AIS deinit warnings") Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 2742901b55146..9e59c32f9516f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -123,6 +123,8 @@ int kfd_ais_init(struct amdgpu_device *adev) { #ifdef CONFIG_PCI_P2PDMA int ret; + struct page *p2p_page = NULL; + unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); unsigned long size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); bool is_large_bar = adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size; @@ -138,6 +140,13 @@ int kfd_ais_init(struct amdgpu_device *adev) return 0; } + p2p_page = pfn_valid(pci_start_pfn) ? pfn_to_page(pci_start_pfn) : NULL; + if (p2p_page && is_pci_p2pdma_page(p2p_page)) { + adev->kfd.dev->ais_initialized = true; + dev_dbg(adev->dev, "AIS: PCI P2PDMA resource already exists\n"); + return 0; + } + ret = pci_p2pdma_add_resource(adev->pdev, 0 /*bar*/, 0 /*whole VRAM*/, 0 /*offset*/); if (ret) { From 7ab36c0d4d12eb80b821f53590601abbeab756d4 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 3 Sep 2025 20:03:52 -0400 Subject: [PATCH 1670/2070] amdgpu/amdkfd: peerdirect support address lookup Add look-up for the BO by address. This is required for memory allocations where the virtual address are reserved outside of KFD and then later mapped to GPU memory. Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling ' --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 67 ++++++++++++++------- 3 files changed, 63 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7a6a520d719e9..f407da65ecca3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2905,6 +2905,22 @@ int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) vma->vm_ops = &amdgpu_ttm_vm_ops; return 0; } + +/* This function should be called with mm lock held */ +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + if (vma->vm_ops == &amdgpu_ttm_vm_ops) + return true; + + return false; +} +#else +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + pr_err_once("bo from address verification not supported\n"); + + return false; +} #endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ int amdgpu_copy_buffer(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index b77bcec1e8dc8..adaf520927478 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -186,6 +186,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable); +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma); + int amdgpu_copy_buffer(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, uint64_t src_offset, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index efd692e653f94..34ddd3c48b95b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -169,8 +169,12 @@ static int amd_acquire(unsigned long addr, size_t size, char *peer_mem_name, void **client_context) { struct kfd_process *p; - struct kfd_bo *buf_obj; struct amd_mem_context *mem_context; + struct kfd_bo *buf_obj = NULL; + struct kfd_node *dev = NULL; + struct amdgpu_bo *bo = NULL; + unsigned long offset = 0; + uint32_t flags = 0; if (peer_mem_name == rdma_name) { p = peer_mem_private_data; @@ -186,34 +190,54 @@ static int amd_acquire(unsigned long addr, size_t size, align_addr_size(&addr, &size); mutex_lock(&p->mutex); - buf_obj = kfd_process_find_bo_from_interval(p, addr, - addr + size - 1); - if (!buf_obj) { - pr_debug("Cannot find a kfd_bo for the range\n"); - goto out_unlock; - } + buf_obj = kfd_process_find_bo_from_interval(p, addr, addr + size - 1); + if (buf_obj) { + offset = addr - buf_obj->it.start; + bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, &flags); - /* Initialize context used for operation with given address */ - mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); - if (!mem_context) - goto out_unlock; + dev = buf_obj->dev; + } else { + struct vm_area_struct *vma; + struct amdgpu_device *adev; + + mmap_read_lock(p->mm); + vma = find_vma(p->mm, addr); + + if (!vma || + !amdgpu_vma_is_amdgpu_bo(vma) || + vma->vm_start > addr || + vma->vm_end < addr + size) { + mmap_read_unlock(p->mm); + goto out_unlock; + } - mem_context->pid = p->lead_thread->pid; + bo = ttm_to_amdgpu_bo(vma->vm_private_data); + drm_gem_object_get(&bo->tbo.base); + mmap_read_unlock(p->mm); - pr_debug("addr: %#lx, size: %#lx, pid: %d\n", - addr, size, mem_context->pid); + offset = addr - vma->vm_start; - mem_context->va = addr; - mem_context->size = size; - mem_context->offset = addr - buf_obj->it.start; + flags = bo->kfd_bo->alloc_flags; + adev = amdgpu_ttm_adev(bo->tbo.bdev); + dev = adev->kfd.dev->nodes[bo->xcp_id]; + } - mem_context->bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, - &mem_context->flags); - mem_context->dev = buf_obj->dev; + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (unlikely(!mem_context)) { + drm_gem_object_put(&bo->tbo.base); + goto out_unlock; + } mutex_unlock(&p->mutex); + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", addr, size, mem_context->pid); - pr_debug("Client context: 0x%p\n", mem_context); + mem_context->pid = p->lead_thread->pid; + mem_context->va = addr; + mem_context->size = size; + mem_context->dev = dev; + mem_context->offset = offset; + mem_context->bo = bo; + mem_context->flags = flags; /* Return pointer to allocated context */ *client_context = mem_context; @@ -224,7 +248,6 @@ static int amd_acquire(unsigned long addr, size_t size, * by AMD GPU driver */ return 1; - out_unlock: mutex_unlock(&p->mutex); kfd_unref_process(p); From 55db6bb78cfac8f51a14df0c46aacab11da0faf3 Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Mon, 10 Nov 2025 15:15:05 +0800 Subject: [PATCH 1671/2070] drm/amdgpu: improve VRAM usage reporting safety in KFD interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check if TTM resource manager is initialized and active before attempting to read VRAM usge Signed-off-by: Mangesh Gadre Reviewed-by: Christian König Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index eb232c5c5e41f..d2f1902d0e958 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -594,7 +594,8 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) { - return ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); + return ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? + ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; } int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) From 39ecbd2d68c61f4974dc5ab3deeba5d68672b6a0 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 2 Dec 2025 17:05:47 -0500 Subject: [PATCH 1672/2070] drm/amdkfd: increase host trap pc sampling lower bound for gfx12_0_0 and gfx12_0_1 to allow application get enough time to process pc sampling data. Signed-off-by: James Zhu Acked-by: Shweta Khatri Acked-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 7e21b69f635bb..da1fdb3c9599d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -39,9 +39,10 @@ * 1.3 - Update 1st level trap handler for Stochastic PC sampling * 1.4 - Support gfx9_5_0 Stochastic PC sampling * 1.5 - Support gfx12_0_0 and gfx12_0_1 Host Trap PC sampling + * 1.6 - Increase gfx12_0_0 and gfx12_0_1 Host Trap PC sampling lower bound */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 5 +#define KFD_IOCTL_PCS_MINOR_VERSION 6 struct supported_pc_sample_info { uint32_t ip_version; @@ -51,6 +52,9 @@ struct supported_pc_sample_info { const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; +const struct kfd_pc_sample_info sample_info_hosttrap_12_0_0 = { + 0, 512, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; + const struct kfd_pc_sample_info sample_info_stoch_cycle_9_4_3 = { 0, 256, (1ULL << 31), KFD_IOCTL_PCS_FLAG_POWER_OF_2, KFD_IOCTL_PCS_METHOD_STOCHASTIC, KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES }; @@ -61,8 +65,8 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, - { IP_VERSION(12, 0, 0), &sample_info_hosttrap_9_0_0 }, - { IP_VERSION(12, 0, 1), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(12, 0, 0), &sample_info_hosttrap_12_0_0 }, + { IP_VERSION(12, 0, 1), &sample_info_hosttrap_12_0_0 }, }; static int kfd_pc_sample_thread(void *param) From 0f9dc5cd6722ff1753cd36f9b1a6e703754bb53b Mon Sep 17 00:00:00 2001 From: David Francis Date: Thu, 9 Oct 2025 13:19:00 -0400 Subject: [PATCH 1673/2070] drm/amdkfd: Add sysfs entries for AIS transfers AIS is a feature for direct transfer of data from disk to and from VRAM. This patch adds new sysfs entries that track the total number of bytes that each process has transferred to and from each amd device using AIS. The files are as follows: /sys/class/kfd/kfd/proc//ais_/XX:XX:XX.XX:PCI_in /sys/class/kfd/kfd/proc//ais_/XX:XX:XX.XX:PCI_out With a directory for each gpu and each file named with the ID of the PCI device. v2: Add mutex_init v3: Switch to xarray v4: Use xarray locking v5: Add locking to modification of counters v6: use __xa_insert() Signed-off-by: David Francis --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 89 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 ++++- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 100 +++++++++++++++++++++++ 4 files changed, 205 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 9e59c32f9516f..c832d9f3e3cc0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -171,8 +171,88 @@ void kfd_ais_deinit(struct amdgpu_device *adev) adev->kfd.dev->ais_initialized = false; } +#ifdef HAVE_STRUCT_XARRAY +static int kfd_ais_init_attr(struct attribute *attr, struct pci_dev *pdev, bool is_read) +{ + char *filename = kzalloc(MAX_SYSFS_FILENAME_LEN, GFP_KERNEL); + char *suffix; + + if (!filename) + return -ENOMEM; + + if (is_read) + suffix = "PCI_in"; + else + suffix = "PCI_out"; + + snprintf(filename, MAX_SYSFS_FILENAME_LEN, + "%04x:%02x:%02x.%d:%s", pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), suffix); + + attr->name = filename; + attr->mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(attr); + + return 0; +} + +static int kfd_ais_update_counters(uint64_t size_copied, struct pci_dev *pdev, + struct kfd_process_device *pdd, bool is_read) +{ + struct ais_counter_entry *counter; + int ret = 0; + + xa_lock(&pdd->ais_counters_xa); + counter = (struct ais_counter_entry *)xa_load(&pdd->ais_counters_xa, pdev->devfn); + if (counter) { + if (is_read) + counter->bytes_read += size_copied; + else + counter->bytes_written += size_copied; + + goto out; + } + + counter = kzalloc(sizeof(struct ais_counter_entry), GFP_KERNEL); + if (!counter) { + ret = -ENOMEM; + goto out; + } + + counter->pci_devfn = pdev->devfn; + if (is_read) + counter->bytes_read = size_copied; + else + counter->bytes_written = size_copied; + + ret = __xa_insert(&pdd->ais_counters_xa, pdev->devfn, counter, GFP_KERNEL); + if (ret) { + /* xa_insert failing means the entry is not empty, which shouldn't be possible */ + kvfree(counter); + goto out; + } + + ret = kfd_ais_init_attr(&counter->attr_bytes_read, pdev, true); + if (ret) + goto out; + ret = sysfs_create_file(pdd->kobj_ais, &counter->attr_bytes_read); + if (ret) + goto out; + + ret = kfd_ais_init_attr(&counter->attr_bytes_written, pdev, false); + if (ret) + goto out; + ret = sysfs_create_file(pdd->kobj_ais, &counter->attr_bytes_written); + +out: + xa_unlock(&pdd->ais_counters_xa); + return 0; +} +#endif /* HAVE_STRUCT_XARRAY */ + int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, - struct kfd_ais_in_args *in, uint64_t *size_copied) + struct kfd_ais_in_args *in, struct kfd_process_device *pdd, + uint64_t *size_copied) { struct file *filep; struct pci_dev *pdev; @@ -258,8 +338,13 @@ int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, *size_copied += ret; } - if (ret > 0) + + if (ret > 0) { dev_dbg(adev->dev, "AIS: vfs transfer %llu bytes\n", *size_copied); +#ifdef HAVE_STRUCT_XARRAY + ret = kfd_ais_update_counters(*size_copied, pdev, pdd, is_read); +#endif + } kvfree(bvec); put_sg: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2e5f8cc2fa6c5..7bd8a99a51822 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3606,7 +3606,7 @@ static int kfd_ioctl_ais(struct file *filep, struct kfd_process *p, void *data) mutex_unlock(&p->mutex); - err = kfd_ais_rw_file(dev->adev, bo, in, &out_args.size_copied); + err = kfd_ais_rw_file(dev->adev, bo, in, pdd, &out_args.size_copied); if (err) { pr_err("Failed to %s AIS file: %d\n", in->op == KFD_IOC_AIS_READ ? "read" : "write", err); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 062691135a642..6337848ef1824 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -839,7 +839,7 @@ enum kfd_pdd_bound { PDD_BOUND_SUSPENDED, }; -#define MAX_SYSFS_FILENAME_LEN 15 +#define MAX_SYSFS_FILENAME_LEN 31 /* * SDMA counter runs at 100MHz frequency. @@ -854,6 +854,14 @@ struct pc_sampling_entry { struct kfd_process_device *pdd; }; +struct ais_counter_entry { + int pci_devfn; + struct attribute attr_bytes_read; + struct attribute attr_bytes_written; + uint64_t bytes_read; + uint64_t bytes_written; +}; + /* Data that is per-process-per device. */ struct kfd_process_device { /* The device that owns this data. */ @@ -950,6 +958,12 @@ struct kfd_process_device { uint64_t page_in; uint64_t page_out; + /* xarray of counters for ais; entries are of type struct ais_counter_entry *, indexed by pci_dev_fn */ +#ifdef HAVE_STRUCT_XARRAY + struct kobject *kobj_ais; + struct xarray ais_counters_xa; +#endif + /* Exception code status*/ uint64_t exception_status; void *vm_fault_exc_data; @@ -1761,7 +1775,8 @@ static inline bool kfd_is_first_node(struct kfd_node *node) int kfd_ais_init(struct amdgpu_device *adev); void kfd_ais_deinit(struct amdgpu_device *adev); int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, - struct kfd_ais_in_args *in, uint64_t *size_copied); + struct kfd_ais_in_args *in, struct kfd_process_device *pdd, + uint64_t *size_copied); /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 47cc8b327ffe0..479d7c701143e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -471,6 +471,27 @@ static ssize_t kfd_sysfs_counters_show(struct kobject *kobj, return 0; } +#ifdef HAVE_STRUCT_XARRAY +static ssize_t kfd_sysfs_ais_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct ais_counter_entry *entry; + int len = strlen(attr->name); + + if (len > 6 && !strcmp(((char *)attr->name) + len - 6, "PCI_in")) { + entry = container_of(attr, struct ais_counter_entry, + attr_bytes_read); + return sysfs_emit(buf, "%llu\n", READ_ONCE(entry->bytes_read)); + } + if (len > 7 && !strcmp(((char *)attr->name) + len - 7, "PCI_out")) { + entry = container_of(attr, struct ais_counter_entry, + attr_bytes_written); + return sysfs_emit(buf, "%llu\n", READ_ONCE(entry->bytes_written)); + } + return 0; +} +#endif + static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, }; @@ -497,6 +518,17 @@ static const struct kobj_type sysfs_counters_type = { .release = kfd_procfs_kobj_release, }; +#ifdef HAVE_STRUCT_XARRAY +static const struct sysfs_ops sysfs_ais_ops = { + .show = kfd_sysfs_ais_show, +}; + +static const struct kobj_type sysfs_ais_type = { + .sysfs_ops = &sysfs_ais_ops, + .release = kfd_procfs_kobj_release, +}; +#endif + int kfd_procfs_add_queue(struct queue *q) { struct kfd_process *proc; @@ -661,6 +693,45 @@ static void kfd_procfs_add_sysfs_files(struct kfd_process *p) } } +#ifdef HAVE_STRUCT_XARRAY +static void kfd_procfs_add_sysfs_ais(struct kfd_process *p) +{ + int ret = 0; + int i; + char ais_dir_filename[MAX_SYSFS_FILENAME_LEN]; + + if (!p || !p->kobj) + return; + + /* + * Create sysfs files for each GPU which supports SVM + * - proc//ais_/ + * - proc//ais_/XX:XX:XX.XX:PCI_in (created dynamically) + * - proc//ais_/XX:XX:XX.XX:PCI_out (created dynamically) + */ + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + struct kobject *kobj_ais; + + snprintf(ais_dir_filename, MAX_SYSFS_FILENAME_LEN, + "ais_%u", pdd->dev->id); + kobj_ais = kfd_alloc_struct(kobj_ais); + if (!kobj_ais) + return; + + ret = kobject_init_and_add(kobj_ais, &sysfs_ais_type, + p->kobj, ais_dir_filename); + pdd->kobj_ais = kobj_ais; + if (ret) { + pr_warn("Creating KFD proc/%s folder failed", + ais_dir_filename); + kobject_put(kobj_ais); + return; + } + } +} +#endif + void kfd_procfs_del_queue(struct queue *q) { if (!q) @@ -860,6 +931,9 @@ int kfd_create_process_sysfs(struct kfd_process *process) kfd_procfs_add_sysfs_stats(process); kfd_procfs_add_sysfs_files(process); kfd_procfs_add_sysfs_counters(process); +#ifdef HAVE_STRUCT_XARRAY + kfd_procfs_add_sysfs_ais(process); +#endif return 0; } @@ -1198,6 +1272,29 @@ static void kfd_process_remove_sysfs(struct kfd_process *p) kobject_put(pdd->kobj_counters); pdd->kobj_counters = NULL; } +#ifdef HAVE_STRUCT_XARRAY + for (i = 0; i < p->n_pdds; i++) { + pdd = p->pdds[i]; + struct ais_counter_entry *counter; + unsigned long index; + + xa_for_each(&pdd->ais_counters_xa, index, counter) { + const char *read_filename = counter->attr_bytes_read.name; + const char *write_filename = counter->attr_bytes_written.name; + + sysfs_remove_file(pdd->kobj_ais, &counter->attr_bytes_read); + sysfs_remove_file(pdd->kobj_ais, &counter->attr_bytes_written); + kfree(read_filename); + kfree(write_filename); + kfree(counter); + } + + xa_destroy(&pdd->ais_counters_xa); + + kobject_del(pdd->kobj_ais); + kobject_put(pdd->kobj_ais); + } +#endif kobject_del(p->kobj); kobject_put(p->kobj); @@ -1787,6 +1884,9 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->user_gpu_id = dev->id; atomic64_set(&pdd->evict_duration_counter, 0); kfd_spm_init_process_device(pdd); +#ifdef HAVE_STRUCT_XARRAY + xa_init(&pdd->ais_counters_xa); +#endif p->pdds[p->n_pdds++] = pdd; if (kfd_dbg_is_per_vmid_supported(pdd->dev)) From 96af3b3dfe4cc57bcb7e908b5b442c258b685f67 Mon Sep 17 00:00:00 2001 From: Siwei He Date: Fri, 30 Jan 2026 09:30:20 -0500 Subject: [PATCH 1674/2070] drm/amdkfd: Check return value for kfd_process_device_translate_handle Add a NULL check in kfd_process_device_translate_handle to ensure the pointer returned from kfd_process_device_find_bo is validated before being returned. v2: Add return check for all occurrences of kfd_process_device_find_bo Signed-off-by: Siwei He Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 7bd8a99a51822..fb9a4256ffa0d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2552,6 +2552,11 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, } kfd_bo = kfd_process_device_find_bo(pdd, bo_priv->idr_handle); + if (!kfd_bo) { + pr_err("Failed to find BO\n"); + return -EINVAL; + } + *kgd_mem = kfd_bo->mem; (*kgd_mem)->is_imported = bo_priv->is_imported; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 479d7c701143e..7ed3477cbf2b1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2087,6 +2087,9 @@ void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, buf_obj = kfd_process_device_find_bo(pdd, handle); + if (!buf_obj) + return NULL; + return buf_obj->mem; } @@ -2131,6 +2134,8 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, return; buf_obj = kfd_process_device_find_bo(pdd, handle); + if (!buf_obj) + return; idr_remove(&pdd->alloc_idr, handle); From 15f41beb67cb78aa33496b782f3d2d8a2551e3bf Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 8 Jan 2026 13:41:27 -0500 Subject: [PATCH 1675/2070] drm/kfd: Support Host Trap/Stochastic PC sampling for gfx9.4.4 Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Reviewed-by: Shweta Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 62721aed139df..9854858e4c731 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4050,7 +4050,8 @@ int psp_config_sq_perfmon(struct psp_context *psp, return 0; if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6) && - amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) { + amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12) && + amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) { dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index da1fdb3c9599d..94f67a8c240ec 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -40,9 +40,10 @@ * 1.4 - Support gfx9_5_0 Stochastic PC sampling * 1.5 - Support gfx12_0_0 and gfx12_0_1 Host Trap PC sampling * 1.6 - Increase gfx12_0_0 and gfx12_0_1 Host Trap PC sampling lower bound + * 1.7 - Support gfx9_4_4 Host Trap PC sampling/Stochastic PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 6 +#define KFD_IOCTL_PCS_MINOR_VERSION 7 struct supported_pc_sample_info { uint32_t ip_version; @@ -63,6 +64,8 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(9, 4, 4), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 4), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(12, 0, 0), &sample_info_hosttrap_12_0_0 }, From 4db6bda9c5dfd2eee744e6de9b13de18dbeccd3c Mon Sep 17 00:00:00 2001 From: "Alysa.Liu@amd.com" Date: Wed, 4 Feb 2026 11:26:23 -0500 Subject: [PATCH 1676/2070] drm/amdkfd: Fix spurious AIS error message on EOF vfs_iocb_iter_read() returns 0 on EOF, which is not an error. Remove the incorrect dev_err() log when reaching end of file. Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alysa Liu --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index c832d9f3e3cc0..7eea81b7d54ad 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -321,10 +321,14 @@ int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, ret = vfs_iocb_iter_read(filep, &kiocb, &iter); else ret = vfs_iocb_iter_write(filep, &kiocb, &iter); - if (ret <= 0) { + if (ret < 0) { dev_err(adev->dev, "AIS: vfs transfer failed %d\n", ret); break; - } else if (cur_pos == kiocb.ki_pos) { + } + if (ret == 0 && is_read) { + break; /* EOF */ + } + if (cur_pos == kiocb.ki_pos) { /* No progress made, retry */ if (retry-- > 0) { dev_warn(adev->dev, "AIS: vfs transfer stalled, retrying...\n"); @@ -339,7 +343,7 @@ int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, } - if (ret > 0) { + if (ret > 0 || (ret == 0 && is_read)) { dev_dbg(adev->dev, "AIS: vfs transfer %llu bytes\n", *size_copied); #ifdef HAVE_STRUCT_XARRAY ret = kfd_ais_update_counters(*size_copied, pdev, pdd, is_read); From f5afff92c45f3ebeb872c674fd4686e3bb22b296 Mon Sep 17 00:00:00 2001 From: Amir Shetaia Date: Thu, 5 Feb 2026 16:29:20 -0500 Subject: [PATCH 1677/2070] drm/amdkfd: Fix race between AIS and FREE_MEMORY_OF_GPU ioctls Fix a use-after-free / NULL pointer dereference in kfd_ioctl_ais() that occurs when racing with kfd_ioctl_free_memory_of_gpu() on the same buffer handle. The race window exists because AIS released p->mutex between pinning and unpinning the BO, allowing FREE to destroy the BO while AIS still held a pointer to it. This resulted in NULL deref in amdgpu_bo_unpin(). Fix by taking a GEM object reference before releasing p->mutex and holding it until after unpinning. This ensures the BO cannot be freed while AIS is using it. Crash signature: BUG: kernel NULL pointer dereference in amdgpu_bo_unpin+0x41/0xb0 Call trace: amdgpu_amdkfd_gpuvm_unpin_bo <- kfd_ioctl_ais Signed-off-by: Amir Shetaia Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fb9a4256ffa0d..ab406e5a129dc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3599,13 +3599,17 @@ static int kfd_ioctl_ais(struct file *filep, struct kfd_process *p, void *data) } /* - * Concurrent data transfers on the same buffer is allowed. Pin it before - * releasing the lock. This ensures that BO remains valid when file system - * is accessing it + * Pin the BO before using it for AIS file I/O operations. + * Take a reference to prevent UAF if the BO is freed + * concurrently via FREE_MEMORY_OF_GPU. The reference ensures the + * BO remains valid until we unpin and release it. */ + amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, NULL); + err = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_VRAM); if (err) { pr_err("Pinning of buffer failed.\n"); + amdgpu_amdkfd_gpuvm_put_bo_ref(bo); goto err_bind_process; } @@ -3619,6 +3623,7 @@ static int kfd_ioctl_ais(struct file *filep, struct kfd_process *p, void *data) } amdgpu_amdkfd_gpuvm_unpin_bo(bo); + amdgpu_amdkfd_gpuvm_put_bo_ref(bo); memcpy(out, &out_args, sizeof(out_args)); return err; From d9571e638f7387f50c5141b3da9bebe4371109b5 Mon Sep 17 00:00:00 2001 From: Andrew Martin Date: Mon, 23 Feb 2026 16:08:16 -0500 Subject: [PATCH 1678/2070] drm/amdkfd: Removed commented line for MQD queue priority Missed deleting the commented line in the original patch. Fixes: 3e95063383f5 ("drm/amdkfd: Disable MQD queue priority") Signed-off-by: Andrew Martin Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 1 - 7 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index ec2209928c14d..2ded29c497eb3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -96,7 +96,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct cik_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 729543bc44d11..82f194ea2a211 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -70,7 +70,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 7d33ee824417e..4d8cf6008a776 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -96,7 +96,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index cc2da8c6c84bd..51dde2c86eb38 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -77,7 +77,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index 0d6b601962eb9..6e591103c3b60 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -131,7 +131,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 6d5687bdfcf90..77fcfb549601d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -149,7 +149,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v9_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static bool mqd_on_vram(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 2a3fd7042b0e6..4de4c365d657d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -112,7 +112,6 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct vi_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - /* m->cp_hqd_queue_priority = q->priority; */ } static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, From a73647095ec0a9a3eeaa54019b6d8681de622325 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 23 Feb 2026 12:41:30 +0000 Subject: [PATCH 1679/2070] drm/amdgpu/userq: Fix reference leak in amdgpu_userq_wait_ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop reference to syncobj and timeline fence when aborting the ioctl due output array being too small. Reviewed-by: Alex Deucher Signed-off-by: Tvrtko Ursulin Fixes: a292fdecd728 ("drm/amdgpu: Implement userqueue signal/wait IOCTL") Cc: Arunpravin Paneer Selvam Cc: Christian König Cc: Alex Deucher Cc: # v6.16+ Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index a1b2fe42328c2..ff4042a48501a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -941,6 +941,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, dma_fence_unwrap_for_each(f, &iter, fence) { if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { r = -EINVAL; + dma_fence_put(fence); goto free_fences; } @@ -965,6 +966,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { r = -EINVAL; + dma_fence_put(fence); goto free_fences; } From 18c09584c808502496df832fbaa85ec3d98648f8 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 23 Feb 2026 12:41:31 +0000 Subject: [PATCH 1680/2070] drm/amdgpu/userq: Do not allow userspace to trivially triger kernel warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Userspace can either deliberately pass in the too small num_fences, or the required number can legitimately grow between the two calls to the userq wait ioctl. In both cases we do not want the emit the kernel warning backtrace since nothing is wrong with the kernel and userspace will simply get an errno reported back. So lets simply drop the WARN_ONs. Reviewed-by: Alex Deucher Signed-off-by: Tvrtko Ursulin Fixes: a292fdecd728 ("drm/amdgpu: Implement userqueue signal/wait IOCTL") Cc: Arunpravin Paneer Selvam Cc: Christian König Cc: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index ff4042a48501a..2abb8561592b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -898,7 +898,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), DMA_RESV_USAGE_READ, fence) { - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { + if (num_fences >= wait_info->num_fences) { r = -EINVAL; goto free_fences; } @@ -915,7 +915,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), DMA_RESV_USAGE_WRITE, fence) { - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { + if (num_fences >= wait_info->num_fences) { r = -EINVAL; goto free_fences; } @@ -939,7 +939,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, goto free_fences; dma_fence_unwrap_for_each(f, &iter, fence) { - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { + if (num_fences >= wait_info->num_fences) { r = -EINVAL; dma_fence_put(fence); goto free_fences; @@ -964,7 +964,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, if (r) goto free_fences; - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { + if (num_fences >= wait_info->num_fences) { r = -EINVAL; dma_fence_put(fence); goto free_fences; From 7e2e38243a22875bf656f7732c9a354922d6c634 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 23 Feb 2026 12:41:32 +0000 Subject: [PATCH 1681/2070] drm/amdgpu/userq: Consolidate wait ioctl exit path If we gate the fence destruction with a check telling us whether there are valid pointers in there we can eliminate the need for dual, basically identical, exit paths. Reviewed-by: Alex Deucher Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 28 ++++--------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 2abb8561592b1..65564b336247a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -1044,32 +1044,14 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, r = -EFAULT; goto free_fences; } - - kfree(fences); - kfree(fence_info); } - drm_exec_fini(&exec); - for (i = 0; i < num_read_bo_handles; i++) - drm_gem_object_put(gobj_read[i]); - kfree(gobj_read); - - for (i = 0; i < num_write_bo_handles; i++) - drm_gem_object_put(gobj_write[i]); - kfree(gobj_write); - - kfree(timeline_points); - kfree(timeline_handles); - kfree(syncobj_handles); - kfree(bo_handles_write); - kfree(bo_handles_read); - - return 0; - free_fences: - while (num_fences-- > 0) - dma_fence_put(fences[num_fences]); - kfree(fences); + if (fences) { + while (num_fences-- > 0) + dma_fence_put(fences[num_fences]); + kfree(fences); + } free_fence_info: kfree(fence_info); exec_fini: From 5c4b83657cc1238a88b780cd47cc5565aebf33ba Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 9 Feb 2026 16:29:57 +0800 Subject: [PATCH 1682/2070] drm/amd/ras: use dedicated memory as vf ras command buffer Use dedicated memory as vf ras command buffer. V2: Add lock to ensure serialization of sending vf ras commands. Signed-off-by: YiPeng Chai Reviewed-by: Jinzhou Su Tested-by: Jinzhou Su --- drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 24 +++- .../drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c | 120 +++++++++++++----- .../drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h | 10 +- 3 files changed, 114 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index cffb2f805de24..4870c03627df1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -470,14 +470,22 @@ struct amd_sriov_ras_chk_criti { uint32_t hit; }; +union amd_sriov_ras_host_push { + struct amd_sriov_ras_telemetry_error_count error_count; + struct amd_sriov_ras_cper_dump cper_dump; + struct amd_sriov_ras_chk_criti chk_criti; +}; + +#define AMD_SRIOV_UNIRAS_CMD_MAX_SIZE (PAGE_SIZE * 13) +struct amd_sriov_uniras_shared_mem { + uint8_t blocks_ecc_buf[PAGE_SIZE]; + uint8_t cmd_buf[AMD_SRIOV_UNIRAS_CMD_MAX_SIZE]; +}; + struct amdsriov_ras_telemetry { struct amd_sriov_ras_telemetry_header header; - - union { - struct amd_sriov_ras_telemetry_error_count error_count; - struct amd_sriov_ras_cper_dump cper_dump; - struct amd_sriov_ras_chk_criti chk_criti; - } body; + union amd_sriov_ras_host_push body; + struct amd_sriov_uniras_shared_mem uniras_shared_mem; }; /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ @@ -510,6 +518,10 @@ _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX"); +_Static_assert( + sizeof(struct amdsriov_ras_telemetry) <= AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10, +"amdsriov_ras_telemetry must be " stringification(AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1) " KB"); + #undef _stringification #undef stringification #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c index a754795938647..4a58d6ca9978b 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c @@ -30,28 +30,83 @@ #include "amdgpu_virt_ras_cmd.h" #include "amdgpu_ras_mgr.h" +static int amdgpu_virt_ras_get_cmd_shared_mem(struct ras_core_context *ras_core, + uint32_t cmd, uint32_t mem_size, struct amdgpu_virt_shared_mem *shared_mem) +{ + struct amdgpu_device *adev = ras_core->dev; + struct amdsriov_ras_telemetry *ras_telemetry_cpu; + struct amdsriov_ras_telemetry *ras_telemetry_gpu; + uint64_t fw_vram_usage_start_offset = 0; + uint64_t ras_telemetry_offset = 0; + + if (!adev->virt.fw_reserve.ras_telemetry) + return -EINVAL; + + if (adev->mman.fw_vram_usage_va && + adev->mman.fw_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { + fw_vram_usage_start_offset = adev->mman.fw_vram_usage_start_offset; + ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - + (uintptr_t)adev->mman.fw_vram_usage_va; + } else if (adev->mman.drv_vram_usage_va && + adev->mman.drv_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { + fw_vram_usage_start_offset = adev->mman.drv_vram_usage_start_offset; + ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - + (uintptr_t)adev->mman.drv_vram_usage_va; + } else { + return -EINVAL; + } + + ras_telemetry_cpu = + (struct amdsriov_ras_telemetry *)adev->virt.fw_reserve.ras_telemetry; + ras_telemetry_gpu = + (struct amdsriov_ras_telemetry *)(uintptr_t)(fw_vram_usage_start_offset + + ras_telemetry_offset); + + if (cmd == RAS_CMD__GET_ALL_BLOCK_ECC_STATUS) { + if (mem_size > PAGE_SIZE) + return -ENOMEM; + + shared_mem->cpu_addr = ras_telemetry_cpu->uniras_shared_mem.blocks_ecc_buf; + shared_mem->gpa = + (uintptr_t)ras_telemetry_gpu->uniras_shared_mem.blocks_ecc_buf - + adev->gmc.vram_start; + shared_mem->size = mem_size; + } else { + if (mem_size > AMD_SRIOV_UNIRAS_CMD_MAX_SIZE) + return -ENOMEM; + + shared_mem->cpu_addr = ras_telemetry_cpu->uniras_shared_mem.cmd_buf; + shared_mem->gpa = + (uintptr_t)ras_telemetry_gpu->uniras_shared_mem.cmd_buf - + adev->gmc.vram_start; + shared_mem->size = mem_size; + } + + return 0; +} + static int amdgpu_virt_ras_remote_ioctl_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *output_data, uint32_t output_size) { - struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(ras_core->dev); + struct amdgpu_virt_ras_cmd *virt_ras = ras_mgr->virt_ras_cmd; uint32_t mem_len = ALIGN(sizeof(*cmd) + output_size, AMDGPU_GPU_PAGE_SIZE); struct ras_cmd_ctx *rcmd; - struct amdgpu_bo *rcmd_bo = NULL; - uint64_t mc_addr = 0; - void *cpu_addr = NULL; + struct amdgpu_virt_shared_mem shared_mem = {0}; int ret = 0; - ret = amdgpu_bo_create_kernel(adev, mem_len, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, &rcmd_bo, &mc_addr, (void **)&cpu_addr); + mutex_lock(&virt_ras->remote_access_lock); + + ret = amdgpu_virt_ras_get_cmd_shared_mem(ras_core, cmd->cmd_id, mem_len, &shared_mem); if (ret) - return ret; + goto out; - rcmd = (struct ras_cmd_ctx *)cpu_addr; + rcmd = (struct ras_cmd_ctx *)shared_mem.cpu_addr; memset(rcmd, 0, mem_len); memcpy(rcmd, cmd, sizeof(*cmd)); ret = amdgpu_virt_send_remote_ras_cmd(ras_core->dev, - mc_addr - adev->gmc.vram_start, mem_len); + shared_mem.gpa, mem_len); if (!ret) { if (rcmd->cmd_res) { ret = rcmd->cmd_res; @@ -65,8 +120,7 @@ static int amdgpu_virt_ras_remote_ioctl_cmd(struct ras_core_context *ras_core, } out: - amdgpu_bo_free_kernel(&rcmd_bo, &mc_addr, &cpu_addr); - + mutex_unlock(&virt_ras->remote_access_lock); return ret; } @@ -77,6 +131,9 @@ static int amdgpu_virt_ras_send_remote_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx rcmd = {0}; int ret; + if (input_size > RAS_CMD_MAX_IN_SIZE) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + rcmd.cmd_id = cmd_id; rcmd.input_size = input_size; memcpy(rcmd.input_buff_raw, input_data, input_size); @@ -146,7 +203,7 @@ static int amdgpu_virt_ras_get_batch_records(struct ras_core_context *ras_core, struct ras_cmd_batch_trace_record_rsp *rsp = rsp_cache; struct batch_ras_trace_info *batch; int ret = 0; - uint8_t i; + uint32_t i; if (!rsp->real_batch_num || (batch_id < rsp->start_batch_id) || (batch_id >= (rsp->start_batch_id + rsp->real_batch_num))) { @@ -249,14 +306,14 @@ static int __fill_get_blocks_ecc_cmd(struct amdgpu_device *adev, { struct ras_cmd_ctx *rcmd; - if (!blks_ecc || !blks_ecc->bo || !blks_ecc->cpu_addr) + if (!blks_ecc || !blks_ecc->shared_mem.cpu_addr) return -EINVAL; - rcmd = (struct ras_cmd_ctx *)blks_ecc->cpu_addr; + rcmd = (struct ras_cmd_ctx *)blks_ecc->shared_mem.cpu_addr; rcmd->cmd_id = RAS_CMD__GET_ALL_BLOCK_ECC_STATUS; rcmd->input_size = sizeof(struct ras_cmd_blocks_ecc_req); - rcmd->output_buf_size = blks_ecc->size - sizeof(*rcmd); + rcmd->output_buf_size = blks_ecc->shared_mem.size - sizeof(*rcmd); return 0; } @@ -305,15 +362,15 @@ static int amdgpu_virt_ras_get_block_ecc(struct ras_core_context *ras_core, if (!virt_ras->blocks_ecc.auto_update_actived) { ret = __set_cmd_auto_update(adev, RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, - blks_ecc->mc_addr - adev->gmc.vram_start, - blks_ecc->size, true); + blks_ecc->shared_mem.gpa, + blks_ecc->shared_mem.size, true); if (ret) return ret; blks_ecc->auto_update_actived = true; } - blks_ecc_cmd_ctx = blks_ecc->cpu_addr; + blks_ecc_cmd_ctx = blks_ecc->shared_mem.cpu_addr; blks_ecc_rsp = (struct ras_cmd_blocks_ecc_rsp *)blks_ecc_cmd_ctx->output_buff_raw; output_data->ce_count = blks_ecc_rsp->blocks[input_data->block_id].ce_count; @@ -364,18 +421,24 @@ int amdgpu_virt_ras_handle_cmd(struct ras_core_context *ras_core, int amdgpu_virt_ras_sw_init(struct amdgpu_device *adev) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras_cmd; ras_mgr->virt_ras_cmd = kzalloc(sizeof(struct amdgpu_virt_ras_cmd), GFP_KERNEL); if (!ras_mgr->virt_ras_cmd) return -ENOMEM; + virt_ras_cmd = ras_mgr->virt_ras_cmd; + mutex_init(&virt_ras_cmd->remote_access_lock); + return 0; } int amdgpu_virt_ras_sw_fini(struct amdgpu_device *adev) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras_cmd = ras_mgr->virt_ras_cmd; + mutex_destroy(&virt_ras_cmd->remote_access_lock); kfree(ras_mgr->virt_ras_cmd); ras_mgr->virt_ras_cmd = NULL; @@ -392,11 +455,9 @@ int amdgpu_virt_ras_hw_init(struct amdgpu_device *adev) amdgpu_virt_get_ras_capability(adev); memset(blks_ecc, 0, sizeof(*blks_ecc)); - blks_ecc->size = PAGE_SIZE; - if (amdgpu_bo_create_kernel(adev, blks_ecc->size, - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, - &blks_ecc->bo, &blks_ecc->mc_addr, - (void **)&blks_ecc->cpu_addr)) + if (amdgpu_virt_ras_get_cmd_shared_mem(ras_mgr->ras_core, + RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, + PAGE_SIZE, &blks_ecc->shared_mem)) return -ENOMEM; return 0; @@ -409,18 +470,15 @@ int amdgpu_virt_ras_hw_fini(struct amdgpu_device *adev) (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; struct vram_blocks_ecc *blks_ecc = &virt_ras->blocks_ecc; - if (blks_ecc->bo) { + if (blks_ecc->shared_mem.cpu_addr) { __set_cmd_auto_update(adev, RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, - blks_ecc->mc_addr - adev->gmc.vram_start, - blks_ecc->size, false); + blks_ecc->shared_mem.gpa, + blks_ecc->shared_mem.size, false); - memset(blks_ecc->cpu_addr, 0, blks_ecc->size); - amdgpu_bo_free_kernel(&blks_ecc->bo, - &blks_ecc->mc_addr, &blks_ecc->cpu_addr); - - memset(blks_ecc, 0, sizeof(*blks_ecc)); + memset(blks_ecc->shared_mem.cpu_addr, 0, blks_ecc->shared_mem.size); } + memset(blks_ecc, 0, sizeof(*blks_ecc)); return 0; } diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h index 53b0f3f60103e..482a5fda72abf 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h @@ -30,11 +30,14 @@ struct remote_batch_trace_mgr { struct ras_cmd_batch_trace_record_rsp batch_trace; }; -struct vram_blocks_ecc { - struct amdgpu_bo *bo; - uint64_t mc_addr; +struct amdgpu_virt_shared_mem { + uint64_t gpa; void *cpu_addr; uint32_t size; +}; + +struct vram_blocks_ecc { + struct amdgpu_virt_shared_mem shared_mem; bool auto_update_actived; }; @@ -42,6 +45,7 @@ struct amdgpu_virt_ras_cmd { bool remote_uniras_supported; struct remote_batch_trace_mgr batch_mgr; struct vram_blocks_ecc blocks_ecc; + struct mutex remote_access_lock; }; int amdgpu_virt_ras_sw_init(struct amdgpu_device *adev); From a869fe0e9d7257268bb335474059080242a675dc Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 11:00:18 +0800 Subject: [PATCH 1683/2070] drm/amdkcl: wrap code under macro HAVE_MMU_NOTIFIER_PUT It's caused by 0e9398dcb6ecc5a2cde03a1224cd806278ac13e4 "drm/amdkfd: Fixed kfd_process cleanup on module exit." The non-upstream code in kfd_process_notifier_release() is moved into kfd_process_notifier_release_internal(). Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 7ed3477cbf2b1..b9d6be1464f1e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1417,6 +1417,9 @@ static void kfd_process_table_remove(struct kfd_process *p) void kfd_process_notifier_release_internal(struct kfd_process *p) { int i; +#ifndef HAVE_MMU_NOTIFIER_PUT + struct mm_struct *mm = p->mm; +#endif kfd_process_table_remove(p); cancel_delayed_work_sync(&p->eviction_work); @@ -1460,8 +1463,15 @@ void kfd_process_notifier_release_internal(struct kfd_process *p) srcu_read_unlock(&kfd_processes_srcu, idx); } +#ifdef HAVE_MMU_NOTIFIER_PUT if (p->context_id == KFD_CONTEXT_ID_PRIMARY) mmu_notifier_put(&p->mmu_notifier); +#else + if (p->context_id == KFD_CONTEXT_ID_PRIMARY) { + mmu_notifier_unregister_no_release(&p->mmu_notifier, mm); + mmu_notifier_call_srcu(&p->rcu, &kfd_process_destroy_delayed); + } +#endif } static void kfd_process_notifier_release(struct mmu_notifier *mn, From f3a9b8fbfd24e9949c78c657901575700954691e Mon Sep 17 00:00:00 2001 From: Natalie Vock Date: Mon, 23 Feb 2026 12:45:37 +0100 Subject: [PATCH 1684/2070] drm/amd/display: Use GFP_ATOMIC in dc_create_stream_for_sink This can be called while preemption is disabled, for example by dcn32_internal_validate_bw which is called with the FPU active. Fixes "BUG: scheduling while atomic" messages I encounter on my Navi31 machine. Cc: stable@vger.kernel.org Signed-off-by: Natalie Vock Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 191f6435e7c64..87c0cf7e290ea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -170,11 +170,11 @@ struct dc_stream_state *dc_create_stream_for_sink( if (sink == NULL) goto fail; - stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); + stream = kzalloc(sizeof(struct dc_stream_state), GFP_ATOMIC); if (stream == NULL) goto fail; - stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_KERNEL); + stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC); if (stream->update_scratch == NULL) goto fail; From 17c996a3e86a200cf99701a5a02be5fd6a4612bb Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 23 Feb 2026 12:41:33 +0000 Subject: [PATCH 1685/2070] drm/amdgpu/userq: Use drm_gem_objects_lookup in amdgpu_userq_signal_ioctl Use the existing helper instead of open coding it. Signed-off-by: Tvrtko Ursulin Reviewed-by: Sunil Khatri --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 79 +++++-------------- 1 file changed, 21 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 65564b336247a..62f550908cb07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -523,20 +523,19 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = drm_to_adev(dev); + struct drm_amdgpu_userq_signal *args = data; + const unsigned int num_write_bo_handles = args->num_bo_write_handles; + const unsigned int num_read_bo_handles = args->num_bo_read_handles; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; - struct drm_amdgpu_userq_signal *args = data; - struct drm_gem_object **gobj_write = NULL; - struct drm_gem_object **gobj_read = NULL; - struct amdgpu_usermode_queue *queue; + struct drm_gem_object **gobj_write, **gobj_read; + u32 *syncobj_handles, num_syncobj_handles; struct amdgpu_userq_fence *userq_fence; + struct amdgpu_usermode_queue *queue; struct drm_syncobj **syncobj = NULL; - u32 *bo_handles_write, num_write_bo_handles; - u32 *syncobj_handles, num_syncobj_handles; - u32 *bo_handles_read, num_read_bo_handles; - int r, i, entry, rentry, wentry; struct dma_fence *fence; struct drm_exec exec; + int r, i, entry; u64 wptr; if (!amdgpu_userq_enabled(dev)) @@ -563,51 +562,19 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } } - num_read_bo_handles = args->num_bo_read_handles; - bo_handles_read = memdup_user(u64_to_user_ptr(args->bo_read_handles), - sizeof(u32) * num_read_bo_handles); - if (IS_ERR(bo_handles_read)) { - r = PTR_ERR(bo_handles_read); + r = drm_gem_objects_lookup(filp, + u64_to_user_ptr(args->bo_read_handles), + num_read_bo_handles, + &gobj_read); + if (r) goto free_syncobj; - } - - /* Array of pointers to the GEM read objects */ - gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL); - if (!gobj_read) { - r = -ENOMEM; - goto free_bo_handles_read; - } - - for (rentry = 0; rentry < num_read_bo_handles; rentry++) { - gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]); - if (!gobj_read[rentry]) { - r = -ENOENT; - goto put_gobj_read; - } - } - num_write_bo_handles = args->num_bo_write_handles; - bo_handles_write = memdup_user(u64_to_user_ptr(args->bo_write_handles), - sizeof(u32) * num_write_bo_handles); - if (IS_ERR(bo_handles_write)) { - r = PTR_ERR(bo_handles_write); + r = drm_gem_objects_lookup(filp, + u64_to_user_ptr(args->bo_write_handles), + num_write_bo_handles, + &gobj_write); + if (r) goto put_gobj_read; - } - - /* Array of pointers to the GEM write objects */ - gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL); - if (!gobj_write) { - r = -ENOMEM; - goto free_bo_handles_write; - } - - for (wentry = 0; wentry < num_write_bo_handles; wentry++) { - gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]); - if (!gobj_write[wentry]) { - r = -ENOENT; - goto put_gobj_write; - } - } /* Retrieve the user queue */ queue = xa_load(&userq_mgr->userq_xa, args->queue_id); @@ -686,17 +653,13 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, exec_fini: drm_exec_fini(&exec); put_gobj_write: - while (wentry-- > 0) - drm_gem_object_put(gobj_write[wentry]); + for (i = 0; i < num_write_bo_handles; i++) + drm_gem_object_put(gobj_write[i]); kfree(gobj_write); -free_bo_handles_write: - kfree(bo_handles_write); put_gobj_read: - while (rentry-- > 0) - drm_gem_object_put(gobj_read[rentry]); + for (i = 0; i < num_read_bo_handles; i++) + drm_gem_object_put(gobj_read[i]); kfree(gobj_read); -free_bo_handles_read: - kfree(bo_handles_read); free_syncobj: while (entry-- > 0) if (syncobj[entry]) From 1d19b46e4b9b83160bf378a9fefb6596c3b57f83 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 23 Feb 2026 12:41:34 +0000 Subject: [PATCH 1686/2070] drm/amdgpu/userq: Use drm_gem_objects_lookup in amdgpu_userq_wait_ioctl Use the existing helper instead of open coding it Signed-off-by: Tvrtko Ursulin Reviewed-by: Sunil Khatri --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 80 ++++++------------- 1 file changed, 24 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 62f550908cb07..64180cf015a21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -674,44 +674,30 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { - u32 *syncobj_handles, *timeline_points, *timeline_handles, *bo_handles_read, *bo_handles_write; - u32 num_syncobj, num_read_bo_handles, num_write_bo_handles; - struct drm_amdgpu_userq_fence_info *fence_info = NULL; struct drm_amdgpu_userq_wait *wait_info = data; + const unsigned int num_write_bo_handles = wait_info->num_bo_write_handles; + const unsigned int num_read_bo_handles = wait_info->num_bo_read_handles; + struct drm_amdgpu_userq_fence_info *fence_info = NULL; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; + struct drm_gem_object **gobj_write, **gobj_read; + u32 *timeline_points, *timeline_handles; struct amdgpu_usermode_queue *waitq; - struct drm_gem_object **gobj_write; - struct drm_gem_object **gobj_read; + u32 *syncobj_handles, num_syncobj; struct dma_fence **fences = NULL; u16 num_points, num_fences = 0; - int r, i, rentry, wentry, cnt; struct drm_exec exec; + int r, i, cnt; if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; - num_read_bo_handles = wait_info->num_bo_read_handles; - bo_handles_read = memdup_user(u64_to_user_ptr(wait_info->bo_read_handles), - size_mul(sizeof(u32), num_read_bo_handles)); - if (IS_ERR(bo_handles_read)) - return PTR_ERR(bo_handles_read); - - num_write_bo_handles = wait_info->num_bo_write_handles; - bo_handles_write = memdup_user(u64_to_user_ptr(wait_info->bo_write_handles), - size_mul(sizeof(u32), num_write_bo_handles)); - if (IS_ERR(bo_handles_write)) { - r = PTR_ERR(bo_handles_write); - goto free_bo_handles_read; - } - num_syncobj = wait_info->num_syncobj_handles; syncobj_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_handles), num_syncobj, sizeof(u32)); - if (IS_ERR(syncobj_handles)) { - r = PTR_ERR(syncobj_handles); - goto free_bo_handles_write; - } + if (IS_ERR(syncobj_handles)) + return PTR_ERR(syncobj_handles); + num_points = wait_info->num_syncobj_timeline_handles; timeline_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_timeline_handles), @@ -729,33 +715,19 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, goto free_timeline_handles; } - gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL); - if (!gobj_read) { - r = -ENOMEM; + r = drm_gem_objects_lookup(filp, + u64_to_user_ptr(wait_info->bo_read_handles), + num_read_bo_handles, + &gobj_read); + if (r) goto free_timeline_points; - } - - for (rentry = 0; rentry < num_read_bo_handles; rentry++) { - gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]); - if (!gobj_read[rentry]) { - r = -ENOENT; - goto put_gobj_read; - } - } - gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL); - if (!gobj_write) { - r = -ENOMEM; + r = drm_gem_objects_lookup(filp, + u64_to_user_ptr(wait_info->bo_write_handles), + num_write_bo_handles, + &gobj_write); + if (r) goto put_gobj_read; - } - - for (wentry = 0; wentry < num_write_bo_handles; wentry++) { - gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]); - if (!gobj_write[wentry]) { - r = -ENOENT; - goto put_gobj_write; - } - } drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, (num_read_bo_handles + num_write_bo_handles)); @@ -1020,12 +992,12 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, exec_fini: drm_exec_fini(&exec); put_gobj_write: - while (wentry-- > 0) - drm_gem_object_put(gobj_write[wentry]); + for (i = 0; i < num_write_bo_handles; i++) + drm_gem_object_put(gobj_write[i]); kfree(gobj_write); put_gobj_read: - while (rentry-- > 0) - drm_gem_object_put(gobj_read[rentry]); + for (i = 0; i < num_read_bo_handles; i++) + drm_gem_object_put(gobj_read[i]); kfree(gobj_read); free_timeline_points: kfree(timeline_points); @@ -1033,10 +1005,6 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, kfree(timeline_handles); free_syncobj_handles: kfree(syncobj_handles); -free_bo_handles_write: - kfree(bo_handles_write); -free_bo_handles_read: - kfree(bo_handles_read); return r; } From a7e6cfee4abada5315dcdc7925cfb6bb4447c62d Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 20 Feb 2026 13:47:58 +0530 Subject: [PATCH 1687/2070] drm/amdgpu: add upper bound check on user inputs in signal ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Huge input values in amdgpu_userq_signal_ioctl can lead to a OOM and could be exploited. So check these input value against AMDGPU_USERQ_MAX_HANDLES which is big enough value for genuine use cases and could potentially avoid OOM. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 64180cf015a21..076bbffb58201 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -35,6 +35,8 @@ static const struct dma_fence_ops amdgpu_userq_fence_ops; static struct kmem_cache *amdgpu_userq_fence_slab; +#define AMDGPU_USERQ_MAX_HANDLES (1U << 16) + int amdgpu_userq_fence_slab_init(void) { amdgpu_userq_fence_slab = kmem_cache_create("amdgpu_userq_fence", @@ -541,6 +543,11 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; + if (args->num_syncobj_handles > AMDGPU_USERQ_MAX_HANDLES || + args->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + args->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) + return -EINVAL; + num_syncobj_handles = args->num_syncobj_handles; syncobj_handles = memdup_array_user(u64_to_user_ptr(args->syncobj_handles), num_syncobj_handles, sizeof(u32)); From 687d516525c5810b1bcdb321bf6289f8981ec1d9 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 24 Feb 2026 12:13:09 +0530 Subject: [PATCH 1688/2070] drm/amdgpu: add upper bound check on user inputs in wait ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Huge input values in amdgpu_userq_wait_ioctl can lead to a OOM and could be exploited. So check these input value against AMDGPU_USERQ_MAX_HANDLES which is big enough value for genuine use cases and could potentially avoid OOM. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 076bbffb58201..dc6e133e20e9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -699,6 +699,12 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; + if (wait_info->num_syncobj_handles > AMDGPU_USERQ_MAX_HANDLES || + wait_info->num_syncobj_timeline_handles > AMDGPU_USERQ_MAX_HANDLES || + wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) + return -EINVAL; + num_syncobj = wait_info->num_syncobj_handles; syncobj_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_handles), num_syncobj, sizeof(u32)); From a0eb88b0b32299c8f57d2dddc25cfc926594dc78 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Mon, 23 Feb 2026 14:00:07 -0800 Subject: [PATCH 1689/2070] drm/amdgpu: Unlock a mutex before destroying it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mutexes must be unlocked before these are destroyed. This has been detected by the Clang thread-safety analyzer. Cc: Alex Deucher Cc: Christian König Cc: Yang Wang Cc: Hawking Zhang Cc: amd-gfx@lists.freedesktop.org Fixes: f5e4cc8461c4 ("drm/amdgpu: implement RAS ACA driver framework") Reviewed-by: Yang Wang Acked-by: Christian König Signed-off-by: Bart Van Assche Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index 9b31804491500..3f9b094e93a29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -641,6 +641,7 @@ static void aca_error_fini(struct aca_error *aerr) aca_bank_error_remove(aerr, bank_error); out_unlock: + mutex_unlock(&aerr->lock); mutex_destroy(&aerr->lock); } From 403ecbfa06b74258236e67bbd143553d7d817d75 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Mon, 23 Feb 2026 13:50:23 -0800 Subject: [PATCH 1690/2070] drm/amdgpu: Fix locking bugs in error paths MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not unlock psp->ras_context.mutex if it has not been locked. This has been detected by the Clang thread-safety analyzer. Cc: Alex Deucher Cc: Christian König Cc: YiPeng Chai Cc: Hawking Zhang Cc: amd-gfx@lists.freedesktop.org Fixes: b3fb79cda568 ("drm/amdgpu: add mutex to protect ras shared memory") Acked-by: Christian König Signed-off-by: Bart Van Assche Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c index 6e8aad91bcd30..0d3c18f04ac36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c @@ -332,13 +332,13 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size if (!context || !context->initialized) { dev_err(adev->dev, "TA is not initialized\n"); ret = -EINVAL; - goto err_free_shared_buf; + goto free_shared_buf; } if (!psp->ta_funcs || !psp->ta_funcs->fn_ta_invoke) { dev_err(adev->dev, "Unsupported function to invoke TA\n"); ret = -EOPNOTSUPP; - goto err_free_shared_buf; + goto free_shared_buf; } context->session_id = ta_id; @@ -346,7 +346,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size mutex_lock(&psp->ras_context.mutex); ret = prep_ta_mem_context(&context->mem_context, shared_buf, shared_buf_len); if (ret) - goto err_free_shared_buf; + goto unlock; ret = psp_fn_ta_invoke(psp, cmd_id); if (ret || context->resp_status) { @@ -354,15 +354,17 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size ret, context->resp_status); if (!ret) { ret = -EINVAL; - goto err_free_shared_buf; + goto unlock; } } if (copy_to_user((char *)&buf[copy_pos], context->mem_context.shared_buf, shared_buf_len)) ret = -EFAULT; -err_free_shared_buf: +unlock: mutex_unlock(&psp->ras_context.mutex); + +free_shared_buf: kfree(shared_buf); return ret; From cc8c1556fce987870a74ebf5a17a4c9d6dcc30f8 Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Tue, 10 Feb 2026 15:46:13 +0800 Subject: [PATCH 1691/2070] drm/amd/ras: Add address check structure Add address check command and data structure for uniras. Signed-off-by: Jinzhou Su Reviewed-by: YiPeng Chai --- drivers/gpu/drm/amd/ras/rascore/ras_cmd.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h index b9833812c31fa..32b48023fdbcb 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -77,6 +77,7 @@ enum ras_cmd_id { RAS_CMD__GET_BATCH_TRACE_RECORD, RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, RAS_CMD__SET_CMD_AUTO_UPDATE, + RAS_CMD__CHECK_ADDRESS_VALIDITY, RAS_CMD__SUPPORTED_MAX = RAS_CMD_ID_COMMON_END, }; @@ -427,6 +428,20 @@ struct ras_cmd_auto_update_rsp { uint32_t reserved[4]; }; +struct ras_cmd_address_check_req { + struct ras_cmd_dev_handle dev; + uint64_t address; + uint32_t flags; + uint32_t vf_idx; + uint32_t reserved[4]; +}; + +struct ras_cmd_address_check_rsp { + uint32_t version; + uint32_t result; + uint32_t reserved[6]; +}; + struct ras_cmd_blocks_ecc_req { struct ras_cmd_dev_handle dev; }; From e456c76699d0e3b5a2b859401e5c31b50b61cf6a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Mar 2026 15:34:55 +0800 Subject: [PATCH 1692/2070] drm/amdkcl: fix missing kcl_mce_amd.o Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a5bf08c182096..9af8d03f72b00 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_drm_drv.o \ From 940f075c8bf4bf589312a59e8ce5b24f6d73db90 Mon Sep 17 00:00:00 2001 From: Yujie Liu Date: Thu, 26 Feb 2026 11:00:35 +0800 Subject: [PATCH 1693/2070] drm/amdgpu: fix kernel-doc warning for amdgpu_ttm_alloc_mmio_remap_bo() Warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1923 expecting prototype for amdgpu_ttm_mmio_remap_bo_init(). Prototype was for amdgpu_ttm_alloc_mmio_remap_bo() instead Fixes: 96e97a562d06 ("drm/amdgpu: Drop MMIO_REMAP domain bit and keep it Internal") Signed-off-by: Yujie Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index f407da65ecca3..6cac635535cff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2303,7 +2303,7 @@ static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) } /** - * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton MMIO_REMAP BO + * amdgpu_ttm_alloc_mmio_remap_bo - Allocate the singleton MMIO_REMAP BO * @adev: amdgpu device * * Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the From 1b5289a3d6c63c887a7f9583f91e09458d935540 Mon Sep 17 00:00:00 2001 From: Yujie Liu Date: Thu, 26 Feb 2026 11:00:38 +0800 Subject: [PATCH 1694/2070] drm/amd/ras: fix kernel-doc warning for ras_eeprom_append() Warning: drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_eeprom.c:845 function parameter 'ras_core' not described in 'ras_eeprom_append' Warning: drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_eeprom.c:845 expecting prototype for ras_core_eeprom_append(). Prototype was for ras_eeprom_append() instead Fixes: 5c3be5defc92 ("drm/amd/ras: Add eeprom ras functions") Signed-off-by: Yujie Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c index cd6b057bdaf3b..65c1812a10fb1 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c @@ -829,8 +829,8 @@ static int ras_eeprom_update_header(struct ras_eeprom_control *control) } /** - * ras_core_eeprom_append -- append records to the EEPROM RAS table - * @control: pointer to control structure + * ras_eeprom_append -- append records to the EEPROM RAS table + * @ras_core: pointer to ras core context * @record: array of records to append * @num: number of records in @record array * From 853c62379749619d0c50d5396331a4bb67d0f03d Mon Sep 17 00:00:00 2001 From: Yujie Liu Date: Thu, 26 Feb 2026 11:00:37 +0800 Subject: [PATCH 1695/2070] drm/amd/pm: fix kernel-doc warning for smu_msg_v1_send_msg() Warning: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:415 expecting prototype for smu_msg_proto_v1_send_msg(). Prototype was for smu_msg_v1_send_msg() instead Fixes: 4f379370a49c ("drm/amd/pm: Add smu message control block") Signed-off-by: Yujie Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 91f24aede8560..293cb4d06193a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -405,7 +405,7 @@ static int __smu_msg_v1_ras_filter(struct smu_msg_ctl *ctl, } /** - * smu_msg_proto_v1_send_msg - Complete V1 protocol with all filtering + * smu_msg_v1_send_msg - Complete V1 protocol with all filtering * @ctl: Message control block * @args: Message arguments * From 89690f8b34054bfb1b534ebe9d1d5192d64b8f48 Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Mon, 9 Feb 2026 15:42:25 +0800 Subject: [PATCH 1696/2070] drm/amd/ras: Add convert retired address structure Add convert retired address command and structure for uniras. Signed-off-by: Jinzhou Su Reviewed-by: YiPeng Chai --- drivers/gpu/drm/amd/ras/rascore/ras_cmd.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h index 32b48023fdbcb..7ea35a0289874 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -78,6 +78,7 @@ enum ras_cmd_id { RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, RAS_CMD__SET_CMD_AUTO_UPDATE, RAS_CMD__CHECK_ADDRESS_VALIDITY, + RAS_CMD__CONVERT_RETIRED_ADDRESS, RAS_CMD__SUPPORTED_MAX = RAS_CMD_ID_COMMON_END, }; @@ -442,6 +443,19 @@ struct ras_cmd_address_check_rsp { uint32_t reserved[6]; }; +struct ras_cmd_convert_retired_address_req { + struct ras_cmd_dev_handle dev; + uint64_t address; + uint32_t reserved[6]; +}; + +#define RAS_CMD_MAX_RETIRED_ADDR_COUNT 32 +struct ras_cmd_convert_retired_address_rsp { + uint32_t version; + uint32_t retired_count; + uint64_t retired_addr[RAS_CMD_MAX_RETIRED_ADDR_COUNT]; +}; + struct ras_cmd_blocks_ecc_req { struct ras_cmd_dev_handle dev; }; From c7629d8cfd15fdc95529da9e4cb69b0a1c6e3166 Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Tue, 10 Feb 2026 14:32:40 +0800 Subject: [PATCH 1697/2070] drm/amd/ras: Handle address check in SR-IOV guest Handle address check validity command in SR-IOV guest Signed-off-by: Jinzhou Su Reviewed-by: YiPeng Chai --- .../drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c | 20 +++++++++++++++++++ .../drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h | 2 ++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c index 4a58d6ca9978b..641fe33508c88 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c @@ -381,6 +381,26 @@ static int amdgpu_virt_ras_get_block_ecc(struct ras_core_context *ras_core, return RAS_CMD__SUCCESS; } +int amdgpu_virt_ras_check_address_validity(struct amdgpu_device *adev, + uint64_t address, bool *hit) +{ + struct ras_cmd_address_check_req req = {0}; + struct ras_cmd_address_check_rsp rsp = {0}; + int ret = 0; + + req.address = address; + + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CHECK_ADDRESS_VALIDITY, + &req, sizeof(req), &rsp, sizeof(rsp)); + + if (ret) + return RAS_CMD__ERROR_GENERIC; + + *hit = rsp.result ? true : false; + + return RAS_CMD__SUCCESS; +} + static struct ras_cmd_func_map amdgpu_virt_ras_cmd_maps[] = { {RAS_CMD__GET_CPER_SNAPSHOT, amdgpu_virt_ras_get_cper_snapshot}, {RAS_CMD__GET_CPER_RECORD, amdgpu_virt_ras_get_cper_records}, diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h index 482a5fda72abf..8245e0de6a9ed 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h @@ -58,4 +58,6 @@ int amdgpu_virt_ras_pre_reset(struct amdgpu_device *adev); int amdgpu_virt_ras_post_reset(struct amdgpu_device *adev); void amdgpu_virt_ras_set_remote_uniras(struct amdgpu_device *adev, bool en); bool amdgpu_virt_ras_remote_uniras_enabled(struct amdgpu_device *adev); +int amdgpu_virt_ras_check_address_validity(struct amdgpu_device *adev, + uint64_t address, bool *hit); #endif From d2f6b50f4da121e61e3874fe19d4c9a6534e850b Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Tue, 10 Feb 2026 14:36:48 +0800 Subject: [PATCH 1698/2070] drm/amd/ras: Add function to convert retired address Add function to convert retired address in SR-IOV guest. Signed-off-by: Jinzhou Su Reviewed-by: YiPeng Chai --- .../drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c | 27 +++++++++++++++++++ .../drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c index 641fe33508c88..3e8b500caec1a 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c @@ -401,6 +401,33 @@ int amdgpu_virt_ras_check_address_validity(struct amdgpu_device *adev, return RAS_CMD__SUCCESS; } +int amdgpu_virt_ras_convert_retired_address(struct amdgpu_device *adev, + uint64_t address, uint64_t *pfn, uint32_t max_pfn_sz) +{ + struct ras_cmd_convert_retired_address_req req = {0}; + struct ras_cmd_convert_retired_address_rsp rsp = {0}; + int ret = 0, i; + int retired_page_count; + + if (!pfn || !max_pfn_sz) + return -EINVAL; + + req.address = address; + + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CONVERT_RETIRED_ADDRESS, + &req, sizeof(req), &rsp, sizeof(rsp)); + + if (ret || rsp.retired_count == 0) + return -EINVAL; + + retired_page_count = rsp.retired_count > max_pfn_sz ? max_pfn_sz : rsp.retired_count; + + for (i = 0; i < retired_page_count; i++) + pfn[i] = rsp.retired_addr[i] >> AMDGPU_GPU_PAGE_SHIFT; + + return retired_page_count; +} + static struct ras_cmd_func_map amdgpu_virt_ras_cmd_maps[] = { {RAS_CMD__GET_CPER_SNAPSHOT, amdgpu_virt_ras_get_cper_snapshot}, {RAS_CMD__GET_CPER_RECORD, amdgpu_virt_ras_get_cper_records}, diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h index 8245e0de6a9ed..3000c354b76fd 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h @@ -60,4 +60,6 @@ void amdgpu_virt_ras_set_remote_uniras(struct amdgpu_device *adev, bool en); bool amdgpu_virt_ras_remote_uniras_enabled(struct amdgpu_device *adev); int amdgpu_virt_ras_check_address_validity(struct amdgpu_device *adev, uint64_t address, bool *hit); +int amdgpu_virt_ras_convert_retired_address(struct amdgpu_device *adev, + uint64_t address, uint64_t *pfn, uint32_t max_pfn_sz); #endif From 147f4c2f4b66ef9e1208d32870ae26c7ee99848d Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Tue, 10 Feb 2026 14:49:35 +0800 Subject: [PATCH 1699/2070] drm/amd/ras: Handle check address validity in SR-IOV Handle check address validity command in SR-IOV guest. Signed-off-by: Jinzhou Su Reviewed-by: YiPeng Chai --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 26 ++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 2446d4266edf6..475ca05c87196 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -42,6 +42,7 @@ #include "amdgpu_reset.h" #include "amdgpu_psp.h" #include "amdgpu_ras_mgr.h" +#include "amdgpu_virt_ras_cmd.h" #ifdef CONFIG_X86_MCE_AMD #include @@ -228,19 +229,30 @@ static int amdgpu_check_address_validity(struct amdgpu_device *adev, return 0; if (amdgpu_sriov_vf(adev)) { - if (amdgpu_virt_check_vf_critical_region(adev, address, &hit)) - return -EPERM; - return hit ? -EACCES : 0; + if (amdgpu_uniras_enabled(adev)) { + if (amdgpu_virt_ras_check_address_validity(adev, address, &hit)) + return -EPERM; + if (hit) + return -EACCES; + } else { + if (amdgpu_virt_check_vf_critical_region(adev, address, &hit)) + return -EPERM; + return hit ? -EACCES : 0; + } } if ((address >= adev->gmc.mc_vram_size) || (address >= RAS_UMC_INJECT_ADDR_LIMIT)) return -EFAULT; - if (amdgpu_uniras_enabled(adev)) - count = amdgpu_ras_mgr_lookup_bad_pages_in_a_row(adev, address, - page_pfns, ARRAY_SIZE(page_pfns)); - else + if (amdgpu_uniras_enabled(adev)) { + if (amdgpu_sriov_vf(adev)) + count = amdgpu_virt_ras_convert_retired_address(adev, address, + page_pfns, ARRAY_SIZE(page_pfns)); + else + count = amdgpu_ras_mgr_lookup_bad_pages_in_a_row(adev, address, + page_pfns, ARRAY_SIZE(page_pfns)); + } else count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, address, page_pfns, ARRAY_SIZE(page_pfns)); From 6aa9f32d54a5f178327d951af58c2404c270471d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 25 Feb 2026 09:47:03 -0800 Subject: [PATCH 1700/2070] drm/amd/ras: Fix type size of remainder argument Forcing an int to be dereferenced at uint64_t for div64_u64_rem() runs the risk of endian confusion and stack overflowing writes. Seen while preparing to enable -Warray-bounds globally: In file included from ../arch/x86/include/asm/processor.h:35, from ../include/linux/sched.h:13, from ../include/linux/ratelimit.h:6, from ../include/linux/dev_printk.h:16, from ../drivers/gpu/drm/amd/amdgpu/../ras/ras_mgr/ras_sys.h:29, from ../drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras.h:27, from ../drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_core.c:24: In function 'div64_u64_rem', inlined from 'ras_core_convert_timestamp_to_time' at ../drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_core.c:72:9: ../include/linux/math64.h:56:20: error: array subscript 'u64 {aka long long unsigned int}[0]' is partly outside array bounds of 'int[1]' [-Werror=array-bounds=] 56 | *remainder = dividend % divisor; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ../drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_core.c: In function 'ras_core_convert_timestamp_to_time': ../drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_core.c:70:19: note: object 'remaining_seconds' of size 4 70 | int days, remaining_seconds; | ^~~~~~~~~~~~~~~~~ Use a 64-bit type for the remainder calculation, but leave remaining_seconds as 32-bit to avoid 64-bit division later. The value of remainder will always be less than seconds_per_day, so there's no truncation risk. Fixes: ace232eff50e ("drm/amdgpu: Add ras module files into amdgpu") Signed-off-by: Kees Cook Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index f2fccdf5e3298..65ac18b050e03 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -62,14 +62,16 @@ int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, uint64_t timestamp, struct ras_time *tm) { int days_in_month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - uint64_t month = 0, day = 0, hour = 0, minute = 0, second = 0; + uint64_t month = 0, day = 0, hour = 0, minute = 0, second = 0, remainder; uint32_t year = 0; int seconds_per_day = 24 * 60 * 60; int seconds_per_hour = 60 * 60; int seconds_per_minute = 60; int days, remaining_seconds; - days = div64_u64_rem(timestamp, seconds_per_day, (uint64_t *)&remaining_seconds); + days = div64_u64_rem(timestamp, seconds_per_day, &remainder); + /* remainder will always be less than seconds_per_day. */ + remaining_seconds = remainder; /* utc_timestamp follows the Unix epoch */ year = 1970; From bab8257466b46ddf5689f5c7a72cb1356fc2b283 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 12 Dec 2025 14:16:17 +0800 Subject: [PATCH 1701/2070] drm/amd/ras: add pmfw eeprom smu interfaces add smu interfaces and its data structures for pmfw eeprom in uniras v2: add 'const' to smu messages array, and specify index for each member when initializing. Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou Reviewed-by: Yang Wang --- .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c | 46 +++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras.h | 18 ++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c index 79a51b1603ac1..2098f24d4940c 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c @@ -28,6 +28,16 @@ #define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A #define RAS_MP1_MSG_McaBankCeDumpDW 0x3B +static const enum smu_message_type pmfw_eeprom_msgs[] = { + [RAS_SMU_GetRASTableVersion] = SMU_MSG_GetRASTableVersion, + [RAS_SMU_GetBadPageCount] = SMU_MSG_GetBadPageCount, + [RAS_SMU_SetTimestamp] = SMU_MSG_SetTimestamp, + [RAS_SMU_GetTimestamp] = SMU_MSG_GetTimestamp, + [RAS_SMU_GetBadPageIpid] = SMU_MSG_GetBadPageIpid, + [RAS_SMU_EraseRasTable] = SMU_MSG_EraseRasTable, + [RAS_SMU_GetBadPageMcaAddr] = SMU_MSG_GetBadPageMcaAddr, +}; + static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core, u32 msg, u32 *count) { @@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core, return ret; } +static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core, + enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret = 0; + + if (down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_smu_ras_send_msg(adev, + pmfw_eeprom_msgs[index], param, read_arg); + up_read(&adev->reset_domain->sem); + } else { + ret = -RAS_CORE_GPU_IN_MODE1_RESET; + } + + return ret; +} + +static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core, + uint64_t *enabled_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret = 0; + + if (down_read_trylock(&adev->reset_domain->sem)) { + if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT)) + *enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM; + up_read(&adev->reset_domain->sem); + } else { + ret = -RAS_CORE_GPU_IN_MODE1_RESET; + } + + return ret; +} + const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = { .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count, .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank, + .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg, + .mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask, }; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 71d807e8d2a7b..3a1059bb380c2 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -49,6 +49,10 @@ #define GPU_RESET_CAUSE_FATAL (RAS_CORE_RESET_GPU | 0x0002) #define GPU_RESET_CAUSE_RMA (RAS_CORE_RESET_GPU | 0x0004) +enum ras_core_fw_feature_flags { + RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), +}; + enum ras_block_id { RAS_BLOCK_ID__UMC = 0, RAS_BLOCK_ID__SDMA, @@ -127,6 +131,16 @@ enum ras_gpu_status { RAS_GPU_STATUS__IS_VF = 0x8, }; +enum ras_fw_eeprom_cmd { + RAS_SMU_GetRASTableVersion = 0, + RAS_SMU_GetBadPageCount, + RAS_SMU_SetTimestamp, + RAS_SMU_GetTimestamp, + RAS_SMU_GetBadPageIpid, + RAS_SMU_EraseRasTable, + RAS_SMU_GetBadPageMcaAddr, +}; + struct ras_core_context; struct ras_bank_ecc; struct ras_umc; @@ -141,6 +155,10 @@ struct ras_mp1_sys_func { u32 msg, u32 *count); int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core, u32 msg, u32 idx, u32 reg_idx, u64 *val); + int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core, + enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg); + int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core, + uint64_t *enabled_mask); }; struct ras_eeprom_sys_func { From e3727385e45fd217cb7f4604086c189c97166bae Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 12 Dec 2025 16:04:30 +0800 Subject: [PATCH 1702/2070] drm/amd/ras: add uniras smu feature flag init func add flag to indicate if pmfw eeprom is supported or not, and initialize it v2: change copyright from 2025 to 2026 Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/Makefile | 3 +- drivers/gpu/drm/amd/ras/rascore/ras.h | 3 ++ drivers/gpu/drm/amd/ras/rascore/ras_core.c | 2 + .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 38 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 29 ++++++++++++++ 5 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h diff --git a/drivers/gpu/drm/amd/ras/rascore/Makefile b/drivers/gpu/drm/amd/ras/rascore/Makefile index e826a1f86424c..06b265ec1cde8 100644 --- a/drivers/gpu/drm/amd/ras/rascore/Makefile +++ b/drivers/gpu/drm/amd/ras/rascore/Makefile @@ -36,7 +36,8 @@ RAS_CORE_FILES = ras_core.o \ ras_log_ring.o \ ras_cper.o \ ras_psp.o \ - ras_psp_v13_0.o + ras_psp_v13_0.o \ + ras_eeprom_fw.o RAS_CORE = $(addprefix $(AMD_GPU_RAS_PATH)/rascore/,$(RAS_CORE_FILES)) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 3a1059bb380c2..07ef4e0d53f6b 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -36,6 +36,7 @@ #include "ras_mp1.h" #include "ras_psp.h" #include "ras_log_ring.h" +#include "ras_eeprom_fw.h" #define RAS_HW_ERR "[Hardware Error]: " @@ -335,6 +336,8 @@ struct ras_core_context { spinlock_t seqno_lock; bool ras_core_enabled; + + u64 ras_fw_features; }; struct ras_core_context *ras_core_create(struct ras_core_config *init_config); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 65ac18b050e03..dda7e04bba3d3 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -384,6 +384,8 @@ int ras_core_hw_init(struct ras_core_context *ras_core) if (ret) goto init_err5; + ras_fw_init_feature_flags(ras_core); + ret = ras_eeprom_hw_init(ras_core); if (ret) goto init_err6; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c new file mode 100644 index 0000000000000..e94c368c31594 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" + +void ras_fw_init_feature_flags(struct ras_core_context *ras_core) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint64_t flags = 0ULL; + + if (!sys_func || !sys_func->mp1_get_ras_enabled_mask) + return; + + if (!sys_func->mp1_get_ras_enabled_mask(ras_core, &flags)) + ras_core->ras_fw_features = flags; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h new file mode 100644 index 0000000000000..b416654673685 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_EEPROM_FW_H__ +#define __RAS_EEPROM_FW_H__ + +void ras_fw_init_feature_flags(struct ras_core_context *ras_core); + +#endif From 0b6681b2ad9ceab56797e1c3d78f1d2c1d4d0dd2 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 12 Dec 2025 16:15:56 +0800 Subject: [PATCH 1703/2070] drm/amd/ras: add wrapper funcs for pmfw eeprom add wrapper funcs for pmfw eeprom interface to make them easier to be called Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 125 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 16 +++ 2 files changed, 141 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index e94c368c31594..f880fc49477da 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -36,3 +36,128 @@ void ras_fw_init_feature_flags(struct ras_core_context *ras_core) if (!sys_func->mp1_get_ras_enabled_mask(ras_core, &flags)) ras_core->ras_fw_features = flags; } + +bool ras_fw_eeprom_supported(struct ras_core_context *ras_core) +{ + return !!(ras_core->ras_fw_features & RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM); +} + +int ras_fw_get_table_version(struct ras_core_context *ras_core, + uint32_t *table_version) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + + return sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetRASTableVersion, 0, table_version); +} + +int ras_fw_get_badpage_count(struct ras_core_context *ras_core, + uint32_t *count, uint32_t timeout) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint64_t end, now; + int ret = 0; + + now = (uint64_t)ktime_to_ms(ktime_get()); + end = now + timeout; + + do { + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageCount, 0, count); + /* eeprom is not ready */ + if (ret != -EBUSY) + return ret; + + mdelay(10); + now = (uint64_t)ktime_to_ms(ktime_get()); + } while (now < end); + + RAS_DEV_ERR(ras_core->dev, + "smu get bad page count timeout!\n"); + return ret; +} + +int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core, + uint16_t index, uint64_t *mca_addr) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t temp_arg, temp_addr_lo, temp_addr_high; + int ret; + + temp_arg = index | (1 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_lo); + if (ret) + return ret; + + temp_arg = index | (2 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_high); + + if (!ret) + *mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo; + + return ret; +} + +int ras_fw_set_timestamp(struct ras_core_context *ras_core, + uint64_t timestamp) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + + return sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_SetTimestamp, (uint32_t)timestamp, 0); +} + +int ras_fw_get_timestamp(struct ras_core_context *ras_core, + uint16_t index, uint64_t *timestamp) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t temp = 0; + int ret; + + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetTimestamp, index, &temp); + if (!ret) + *timestamp = temp; + + return ret; +} + +int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, + uint16_t index, uint64_t *ipid) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t temp_arg, temp_ipid_lo, temp_ipid_high; + int ret; + + temp_arg = index | (1 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_lo); + if (ret) + return ret; + + temp_arg = index | (2 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_high); + if (!ret) + *ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo; + + return ret; +} + +int ras_fw_erase_ras_table(struct ras_core_context *ras_core, + uint32_t *result) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + + return sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_EraseRasTable, 0, result); +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index b416654673685..46f45e82a3f3a 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -24,6 +24,22 @@ #ifndef __RAS_EEPROM_FW_H__ #define __RAS_EEPROM_FW_H__ + void ras_fw_init_feature_flags(struct ras_core_context *ras_core); +bool ras_fw_eeprom_supported(struct ras_core_context *ras_core); +int ras_fw_get_table_version(struct ras_core_context *ras_core, + uint32_t *table_version); +int ras_fw_get_badpage_count(struct ras_core_context *ras_core, + uint32_t *count, uint32_t timeout); +int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core, + uint16_t index, uint64_t *mca_addr); +int ras_fw_set_timestamp(struct ras_core_context *ras_core, + uint64_t timestamp); +int ras_fw_get_timestamp(struct ras_core_context *ras_core, + uint16_t index, uint64_t *timestamp); +int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, + uint16_t index, uint64_t *ipid); +int ras_fw_erase_ras_table(struct ras_core_context *ras_core, + uint32_t *result); #endif From bb4afb457dab31cce9efa6983143f35a105fc9f7 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 12 Dec 2025 15:42:49 +0800 Subject: [PATCH 1704/2070] drm/amd/pm: add feature query interface for uniras add amdgpu_smu_ras_feature_is_enabled to query one feature is supported or not v2: change default return value from -EOPNOTSUPP to 0 Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 ++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 317ec380af788..8b39694608fee 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -628,6 +628,18 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms return ret; } +int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, + enum smu_feature_mask mask) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + int ret = 0; + + if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) + ret = smu->ppt_funcs->feature_is_enabled(smu, mask); + + return ret; +} + static int smu_sys_get_pp_table(void *handle, char **table) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index c22de58dc0ec7..99eae4ab839e8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -2035,7 +2035,8 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, uint32_t param, uint32_t *readarg); - +int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, + enum smu_feature_mask mask); #endif void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); From 61115e75772bfea6ac1f734ced34dcb6ee4876aa Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 12:34:41 +0800 Subject: [PATCH 1705/2070] drm/amd/ras: Add table reset func for pmfw eeprom add table reset func for pmfw eeprom, add smu eeprom control structure Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras.h | 1 + drivers/gpu/drm/amd/ras/rascore/ras_cmd.c | 9 ++++-- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 29 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 26 +++++++++++++++++ 4 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 07ef4e0d53f6b..4ceb72d24e355 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -313,6 +313,7 @@ struct ras_core_context { bool ras_eeprom_supported; struct ras_eeprom_control ras_eeprom; + struct ras_fw_eeprom_control ras_fw_eeprom; struct ras_psp ras_psp; struct ras_umc ras_umc; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c index 94e6d7420d94e..4f89810d85a15 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c @@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core, if (cmd->input_size != sizeof(struct ras_cmd_dev_handle)) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; - if (ras_eeprom_reset_table(ras_core)) - return RAS_CMD__ERROR_GENERIC; + if (ras_fw_eeprom_supported(ras_core)) { + if (ras_fw_eeprom_reset_table(ras_core)) + return RAS_CMD__ERROR_GENERIC; + } else { + if (ras_eeprom_reset_table(ras_core)) + return RAS_CMD__ERROR_GENERIC; + } if (ras_umc_clean_badpage_data(ras_core)) return RAS_CMD__ERROR_GENERIC; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index f880fc49477da..ae63e7394829a 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core, return sys_func->mp1_send_eeprom_msg(ras_core, RAS_SMU_EraseRasTable, 0, result); } + +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + u32 erase_res = 0; + int res; + + mutex_lock(&control->ras_tbl_mutex); + + res = ras_fw_erase_ras_table(ras_core, &erase_res); + if (res || erase_res) { + RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d", + res, erase_res); + if (!res) + res = -EIO; + } + + control->ras_num_recs = 0; + control->bad_channel_bitmap = 0; + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + &control->ras_num_recs); + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + &control->bad_channel_bitmap); + control->update_channel_flag = false; + + mutex_unlock(&control->ras_tbl_mutex); + + return res; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index 46f45e82a3f3a..a1003db3c33ba 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -24,6 +24,31 @@ #ifndef __RAS_EEPROM_FW_H__ #define __RAS_EEPROM_FW_H__ +struct ras_fw_eeprom_control { + uint32_t version; + /* record threshold */ + int record_threshold_config; + uint32_t record_threshold_count; + bool update_channel_flag; + + /* Number of records in the table. + */ + u32 ras_num_recs; + + /* Maximum possible number of records + * we could store, i.e. the maximum capacity + * of the table. + */ + u32 ras_max_record_count; + + /* Protect table access via this mutex. + */ + struct mutex ras_tbl_mutex; + + /* Record channel info which occurred bad pages + */ + u32 bad_channel_bitmap; +}; void ras_fw_init_feature_flags(struct ras_core_context *ras_core); bool ras_fw_eeprom_supported(struct ras_core_context *ras_core); @@ -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, uint16_t index, uint64_t *ipid); int ras_fw_erase_ras_table(struct ras_core_context *ras_core, uint32_t *result); +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core); #endif From 3e23b0563023e06ee3a60d12ea81d6dffc06389a Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 13:01:04 +0800 Subject: [PATCH 1706/2070] drm/amd/ras: add check safety watermark func for pmfw eeprom add check safety watermark func for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 3 ++ drivers/gpu/drm/amd/ras/rascore/ras_core.c | 3 ++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 30 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 1 + 4 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index 59c0636259202..4fc29e548ecbe 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -571,6 +571,9 @@ bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev) if (!amdgpu_ras_mgr_is_ready(adev)) return false; + if (ras_fw_eeprom_supported(ras_mgr->ras_core)) + return ras_fw_eeprom_check_safety_watermark(ras_mgr->ras_core); + return ras_eeprom_check_safety_watermark(ras_mgr->ras_core); } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index dda7e04bba3d3..d846894932ada 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -563,6 +563,9 @@ bool ras_core_is_ready(struct ras_core_context *ras_core) bool ras_core_check_safety_watermark(struct ras_core_context *ras_core) { + if (ras_fw_eeprom_supported(ras_core)) + return ras_fw_eeprom_check_safety_watermark(ras_core); + return ras_eeprom_check_safety_watermark(ras_core); } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index ae63e7394829a..34a4161251b3d 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -190,3 +190,33 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core) return res; } + +bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + bool ret = false; + int bad_page_count; + + if (!control->record_threshold_config) + return false; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + + if (bad_page_count > control->record_threshold_count) + RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d", + bad_page_count, control->record_threshold_count); + + if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || + (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { + RAS_DEV_WARN(ras_core->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); + ret = false; + } else { + ras_core->is_rma = true; + RAS_DEV_WARN(ras_core->dev, + "Please consider adjusting the customized threshold.\n"); + ret = true; + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index a1003db3c33ba..b0d3eade43770 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -67,5 +67,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, int ras_fw_erase_ras_table(struct ras_core_context *ras_core, uint32_t *result); int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core); +bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core); #endif From 09b7179d0f8570eeadc8e58b7504f54522ea609a Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 13:22:55 +0800 Subject: [PATCH 1707/2070] drm/amd/ras: add append func for pmfw eeprom add append func for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 39 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 2 + drivers/gpu/drm/amd/ras/rascore/ras_umc.c | 10 +++-- 3 files changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 34a4161251b3d..580dd7b09d00d 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -220,3 +220,42 @@ bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core) return ret; } + +int ras_fw_eeprom_append(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, const u32 num) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int threshold_config = control->record_threshold_config; + int i, bad_page_count; + + mutex_lock(&control->ras_tbl_mutex); + + for (i = 0; i < num; i++) { + /* update bad channel bitmap */ + if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && + !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { + control->bad_channel_bitmap |= 1 << record[i].mem_channel; + control->update_channel_flag = true; + } + } + control->ras_num_recs += num; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + + if (threshold_config != 0 && + bad_page_count > control->record_threshold_count) { + RAS_DEV_WARN(ras_core->dev, + "Saved bad pages %d reaches threshold value %d\n", + bad_page_count, control->record_threshold_count); + + if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) && + (threshold_config != NONSTOP_OVER_THRESHOLD)) + ras_core->is_rma = true; + + /* ignore the -ENOTSUPP return value */ + ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); + } + + mutex_unlock(&control->ras_tbl_mutex); + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index b0d3eade43770..b94d3c9703e34 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -68,5 +68,7 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core, uint32_t *result); int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core); bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core); +int ras_fw_eeprom_append(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, const u32 num); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index b19c26f6feaf7..f329dc60b2a21 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -491,9 +491,13 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core) save_count = data->count - eeprom_record_num; /* only new entries are saved */ if (save_count > 0) { - if (ras_eeprom_append(ras_core, - &data->bps[eeprom_record_num], - save_count)) { + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_append(ras_core, &data->bps[eeprom_record_num], + save_count); + else + ret = ras_eeprom_append(ras_core, &data->bps[eeprom_record_num], + save_count); + if (ret) { RAS_DEV_ERR(ras_core->dev, "Failed to save EEPROM table data!"); ret = -EIO; goto exit; From ccb6956c1d634fdd0affd27b909d034956e1a35c Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Mon, 15 Dec 2025 13:53:59 +0800 Subject: [PATCH 1708/2070] drm/amd/ras: make MCA IPID parse global add a new IPID parse interface for umc, so we can implement it for each ASIC, and so we can call it in other blocks Signed-off-by: Tao Zhou Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_umc.h | 2 ++ drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h index 3aeb04977d53b..1d3026be509b8 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h @@ -108,6 +108,8 @@ struct ras_umc_ip_func { struct umc_bank_addr bank_addr, uint64_t *soc_pa); int (*soc_pa_to_bank)(struct ras_core_context *ras_core, uint64_t soc_pa, struct umc_bank_addr *bank_addr); + void (*mca_ipid_parse)(struct ras_core_context *ras_core, uint64_t ipid, + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid); }; struct eeprom_store_record { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c index 5d9a11c17a864..e2792b239bea9 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -501,11 +501,25 @@ static int umc_12_0_bank_to_soc_pa(struct ras_core_context *ras_core, return 0; } +static void umc_v12_0_mca_ipid_parse(struct ras_core_context *ras_core, uint64_t ipid, + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid) +{ + if (did) + *did = ACA_IPID_2_DIE_ID(ipid); + if (ch) + *ch = ACA_IPID_2_UMC_CH(ipid); + if (umc_inst) + *umc_inst = ACA_IPID_2_UMC_INST(ipid); + if (sid) + *sid = ACA_IPID_2_SOCKET_ID(ipid); +} + const struct ras_umc_ip_func ras_umc_func_v12_0 = { .bank_to_eeprom_record = umc_v12_0_bank_to_eeprom_record, .eeprom_record_to_nps_record = umc_v12_0_eeprom_record_to_nps_record, .eeprom_record_to_nps_pages = umc_v12_0_eeprom_record_to_nps_pages, .bank_to_soc_pa = umc_12_0_bank_to_soc_pa, .soc_pa_to_bank = umc_12_0_soc_pa_to_bank, + .mca_ipid_parse = umc_v12_0_mca_ipid_parse, }; From b1ad771c3db7ad944616ebe34306364229cafe25 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 14:19:34 +0800 Subject: [PATCH 1709/2070] drm/amd/ras: add read func for pmfw eeprom add read func for pmfw eeprom, and adapt address converting for bad pages loaded from pmfw eeprom v2: change lable 'Out' to 'out' Signed-off-by: Tao Zhou Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras.h | 1 + drivers/gpu/drm/amd/ras/rascore/ras_core.c | 5 +- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 70 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 5 ++ drivers/gpu/drm/amd/ras/rascore/ras_umc.c | 27 +++++-- .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 2 +- 6 files changed, 101 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 4ceb72d24e355..04f9e09884aa9 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -241,6 +241,7 @@ struct ras_bank_ecc { uint64_t status; uint64_t ipid; uint64_t addr; + uint64_t ts; }; struct ras_bank_ecc_node { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index d846894932ada..860589920ad87 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -241,7 +241,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core) int count; int ret; - count = ras_eeprom_get_record_count(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + count = ras_fw_eeprom_get_record_count(ras_core); + else + count = ras_eeprom_get_record_count(ras_core); if (!count) return 0; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 580dd7b09d00d..79494ad16ee5a 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -259,3 +259,73 @@ int ras_fw_eeprom_append(struct ras_core_context *ras_core, mutex_unlock(&control->ras_tbl_mutex); return 0; } + +int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, + struct eeprom_umc_record *record_umc, + struct ras_bank_ecc *ras_ecc, + u32 rec_idx, const u32 num) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int i, ret, end_idx; + u64 mca, ipid, ts; + + if (!ras_core->ras_umc.ip_func || + !ras_core->ras_umc.ip_func->mca_ipid_parse) + return -EOPNOTSUPP; + + mutex_lock(&control->ras_tbl_mutex); + + end_idx = rec_idx + num; + for (i = rec_idx; i < end_idx; i++) { + ret = ras_fw_get_badpage_mca_addr(ras_core, i, &mca); + if (ret) + goto out; + + ret = ras_fw_get_badpage_ipid(ras_core, i, &ipid); + if (ret) + goto out; + + ret = ras_fw_get_timestamp(ras_core, i, &ts); + if (ret) + goto out; + + if (record_umc) { + record_umc[i - rec_idx].address = mca; + /* retired_page (pa) is unused now */ + record_umc[i - rec_idx].retired_row_pfn = 0x1ULL; + record_umc[i - rec_idx].ts = ts; + record_umc[i - rec_idx].err_type = RAS_EEPROM_ERR_NON_RECOVERABLE; + + ras_core->ras_umc.ip_func->mca_ipid_parse(ras_core, ipid, + (uint32_t *)&(record_umc[i - rec_idx].cu), + (uint32_t *)&(record_umc[i - rec_idx].mem_channel), + (uint32_t *)&(record_umc[i - rec_idx].mcumc_id), NULL); + + /* update bad channel bitmap */ + if ((record_umc[i - rec_idx].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && + !(control->bad_channel_bitmap & (1 << record_umc[i - rec_idx].mem_channel))) { + control->bad_channel_bitmap |= 1 << record_umc[i - rec_idx].mem_channel; + control->update_channel_flag = true; + } + } + + if (ras_ecc) { + ras_ecc[i - rec_idx].addr = mca; + ras_ecc[i - rec_idx].ipid = ipid; + ras_ecc[i - rec_idx].ts = ts; + } + + } + +out: + mutex_unlock(&control->ras_tbl_mutex); + return ret; +} + +uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core) +{ + if (!ras_core) + return 0; + + return ras_core->ras_fw_eeprom.ras_num_recs; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index b94d3c9703e34..353977a2371eb 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -70,5 +70,10 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core); bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core); int ras_fw_eeprom_append(struct ras_core_context *ras_core, struct eeprom_umc_record *record, const u32 num); +int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, + struct eeprom_umc_record *record_umc, + struct ras_bank_ecc *ras_ecc, + u32 rec_idx, const u32 num); +uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index f329dc60b2a21..6074807ef6b70 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -448,17 +448,27 @@ int ras_umc_load_bad_pages(struct ras_core_context *ras_core) uint32_t ras_num_recs; int ret; - ras_num_recs = ras_eeprom_get_record_count(ras_core); - /* no bad page record, skip eeprom access */ - if (!ras_num_recs || - ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) - return 0; + if (ras_fw_eeprom_supported(ras_core)) { + ras_num_recs = ras_fw_eeprom_get_record_count(ras_core); + /* no bad page record, skip eeprom access */ + if (!ras_num_recs || + ras_core->ras_fw_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) + return 0; + } else { + ras_num_recs = ras_eeprom_get_record_count(ras_core); + if (!ras_num_recs || + ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) + return 0; + } bps = kcalloc(ras_num_recs, sizeof(*bps), GFP_KERNEL); if (!bps) return -ENOMEM; - ret = ras_eeprom_read(ras_core, bps, ras_num_recs); + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_read_idx(ras_core, bps, 0, 0, ras_num_recs); + else + ret = ras_eeprom_read(ras_core, bps, ras_num_recs); if (ret) { RAS_DEV_ERR(ras_core->dev, "Failed to load EEPROM table records!"); } else { @@ -486,7 +496,10 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core) if (!data->bps) return 0; - eeprom_record_num = ras_eeprom_get_record_count(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + eeprom_record_num = ras_fw_eeprom_get_record_count(ras_core); + else + eeprom_record_num = ras_eeprom_get_record_count(ras_core); mutex_lock(&ras_umc->umc_lock); save_count = data->count - eeprom_record_num; /* only new entries are saved */ diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c index e2792b239bea9..53dc59e4de0c2 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -413,7 +413,7 @@ static int umc_v12_0_eeprom_record_to_nps_record(struct ras_core_context *ras_co uint64_t pa = 0; int ret = 0; - if (nps == EEPROM_RECORD_UMC_NPS_MODE(record)) { + if (nps == EEPROM_RECORD_UMC_NPS_MODE(record) && !ras_fw_eeprom_supported(ras_core)) { record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record); } else { ret = convert_eeprom_record_to_nps_addr(ras_core, From 9aa2400cf1243b6205f452afce36b07ef7505022 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 15:18:35 +0800 Subject: [PATCH 1710/2070] drm/amd/ras: adapt page retirement process for pmfw eeprom read bad page data from pmfw eeprom when retirement is triggered, use timestamp read from eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_aca.c | 31 +++++++++----- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 40 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 2 + .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 3 ++ 4 files changed, 66 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c index e433c70d29891..67a35409ff0e9 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c @@ -234,16 +234,27 @@ static int aca_log_bad_bank(struct ras_core_context *ras_core, bank_ecc->de_count) { struct ras_bank_ecc ras_ecc = {0}; - ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); - ras_ecc.addr = bank_ecc->bank_info.addr; - ras_ecc.ipid = bank_ecc->bank_info.ipid; - ras_ecc.status = bank_ecc->bank_info.status; - ras_ecc.seq_no = bank->seq_no; - - if (ras_core_gpu_in_reset(ras_core)) - ras_umc_log_bad_bank_pending(ras_core, &ras_ecc); - else - ras_umc_log_bad_bank(ras_core, &ras_ecc); + if (ras_fw_eeprom_supported(ras_core)) { + ret = ras_fw_eeprom_update_record(ras_core, &ras_ecc); + if (!ret) { + ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); + ras_ecc.status = bank_ecc->bank_info.status; + ras_ecc.seq_no = bank->seq_no; + } + } else { + ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); + ras_ecc.addr = bank_ecc->bank_info.addr; + ras_ecc.ipid = bank_ecc->bank_info.ipid; + ras_ecc.status = bank_ecc->bank_info.status; + ras_ecc.seq_no = bank->seq_no; + } + + if (!ret) { + if (ras_core_gpu_in_reset(ras_core)) + ras_umc_log_bad_bank_pending(ras_core, &ras_ecc); + else + ras_umc_log_bad_bank(ras_core, &ras_ecc); + } } aca_report_ecc_info(ras_core, diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 79494ad16ee5a..4a1b966d22fab 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -24,6 +24,8 @@ #include "ras.h" +#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */ + void ras_fw_init_feature_flags(struct ras_core_context *ras_core) { struct ras_mp1 *mp1 = &ras_core->ras_mp1; @@ -329,3 +331,41 @@ uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core) return ras_core->ras_fw_eeprom.ras_num_recs; } + +int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, + struct ras_bank_ecc *ras_ecc) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int ret, retry = 20; + u32 recs_num_new = control->ras_num_recs; + + do { + /* 1000ms timeout is long enough, smu_get_badpage_count won't + * return -EBUSY before timeout. + */ + ret = ras_fw_get_badpage_count(ras_core, + &recs_num_new, RAS_SMU_MESSAGE_TIMEOUT_MS); + if (!ret && + (recs_num_new == control->ras_num_recs)) { + /* record number update in PMFW needs some time, + * smu_get_badpage_count may return immediately without + * count update, sleep for a while and retry again. + */ + msleep(50); + retry--; + } else { + break; + } + } while (retry); + + if (ret) + return ret; + + if (recs_num_new > control->ras_num_recs) + ret = ras_fw_eeprom_read_idx(ras_core, 0, + ras_ecc, control->ras_num_recs, 1); + else + ret = -EINVAL; + + return ret; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index 353977a2371eb..18d6548e2151e 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -75,5 +75,7 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, struct ras_bank_ecc *ras_ecc, u32 rec_idx, const u32 num); uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core); +int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, + struct ras_bank_ecc *ras_ecc); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c index 53dc59e4de0c2..b809a2f21d731 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -373,6 +373,9 @@ static int umc_v12_0_bank_to_eeprom_record(struct ras_core_context *ras_core, ACA_ADDR_2_ERR_ADDR(bank->addr), ACA_IPID_2_UMC_INST(bank->ipid), &nps_addr, bank->nps, record); + if (ras_fw_eeprom_supported(ras_core) && bank->ts) + record->ts = bank->ts; + lookup_bad_pages_in_a_row(ras_core, record, bank->nps, NULL, 0, bank->seq_no, true); From 79176c39e08adda1c000a56b1b5a213822139fbf Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 15:48:44 +0800 Subject: [PATCH 1711/2070] drm/amd/ras: add initialization func for pmfw eeprom add initialization func for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 15 +++- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 84 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 2 + 3 files changed, 98 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 860589920ad87..7e5489fb5350b 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -389,7 +389,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core) ras_fw_init_feature_flags(ras_core); - ret = ras_eeprom_hw_init(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_hw_init(ras_core); + else + ret = ras_eeprom_hw_init(ras_core); if (ret) goto init_err6; @@ -413,7 +416,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core) return 0; init_err7: - ras_eeprom_hw_fini(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ras_fw_eeprom_hw_fini(ras_core); + else + ras_eeprom_hw_fini(ras_core); init_err6: ras_gfx_hw_fini(ras_core); init_err5: @@ -434,7 +440,10 @@ int ras_core_hw_fini(struct ras_core_context *ras_core) ras_core->is_initialized = false; ras_process_fini(ras_core); - ras_eeprom_hw_fini(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ras_fw_eeprom_hw_fini(ras_core); + else + ras_eeprom_hw_fini(ras_core); ras_gfx_hw_fini(ras_core); ras_nbio_hw_fini(ras_core); ras_umc_hw_fini(ras_core); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 4a1b966d22fab..4362b8a0f3c46 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -369,3 +369,87 @@ int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, return ret; } + +static int __check_ras_fw_table_status(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + uint64_t local_time; + int res; + + mutex_init(&control->ras_tbl_mutex); + + res = ras_fw_get_table_version(ras_core, &(control->version)); + if (res) + return res; + + res = ras_fw_get_badpage_count(ras_core, &(control->ras_num_recs), 100); + if (res) + return res; + + local_time = (uint64_t)ktime_get_real_seconds(); + res = ras_fw_set_timestamp(ras_core, local_time); + if (res) + return res; + + control->ras_max_record_count = 4000; + + + if (control->ras_num_recs > control->ras_max_record_count) { + RAS_DEV_ERR(ras_core->dev, + "RAS header invalid, records in header: %u max allowed :%u", + control->ras_num_recs, control->ras_max_record_count); + return -EINVAL; + } + + return 0; +} + +int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control; + struct ras_eeprom_config *eeprom_cfg; + struct ras_mp1 *mp1; + const struct ras_mp1_sys_func *sys_func; + + if (!ras_core) + return -EINVAL; + + mp1 = &ras_core->ras_mp1; + sys_func = mp1->sys_func; + + if (!sys_func || !sys_func->mp1_send_eeprom_msg) + return -EINVAL; + + ras_core->is_rma = false; + + control = &ras_core->ras_fw_eeprom; + + memset(control, 0, sizeof(*control)); + + eeprom_cfg = &ras_core->config->eeprom_cfg; + control->record_threshold_config = + eeprom_cfg->eeprom_record_threshold_config; + + control->record_threshold_count = 4000; + if (eeprom_cfg->eeprom_record_threshold_count < + control->record_threshold_count) + control->record_threshold_count = + eeprom_cfg->eeprom_record_threshold_count; + + control->update_channel_flag = false; + + return __check_ras_fw_table_status(ras_core); +} + +int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control; + + if (!ras_core) + return -EINVAL; + + control = &ras_core->ras_fw_eeprom; + mutex_destroy(&control->ras_tbl_mutex); + + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index 18d6548e2151e..cb92e6a63cf54 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -77,5 +77,7 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core); int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, struct ras_bank_ecc *ras_ecc); +int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core); +int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core); #endif From 3694bbfd6f19e41f702345574d89765fa89a6131 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Dec 2025 15:54:35 +0800 Subject: [PATCH 1712/2070] drm/amd/ras: add check func for pmfw eeprom add check func for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c | 3 +- drivers/gpu/drm/amd/ras/rascore/ras.h | 7 +++ drivers/gpu/drm/amd/ras/rascore/ras_core.c | 5 +- drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h | 7 --- .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 51 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 3 ++ 6 files changed, 67 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c index 45ed8c3b5563b..7d728e5236042 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c @@ -137,7 +137,8 @@ static int amdgpu_ras_sys_event_notifier(struct ras_core_context *ras_core, break; case RAS_EVENT_ID__DEVICE_RMA: ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_RMA, NULL, NULL); - ret = amdgpu_dpm_send_rma_reason(ras_core->dev); + if (!ras_fw_eeprom_supported(ras_core)) + ret = amdgpu_dpm_send_rma_reason(ras_core->dev); break; case RAS_EVENT_ID__RESET_GPU: ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 04f9e09884aa9..6449d7b8627d6 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -50,6 +50,13 @@ #define GPU_RESET_CAUSE_FATAL (RAS_CORE_RESET_GPU | 0x0002) #define GPU_RESET_CAUSE_RMA (RAS_CORE_RESET_GPU | 0x0004) +enum ras_gpu_health_status { + RAS_GPU_HEALTH_NONE = 0, + RAS_GPU_HEALTH_USABLE = 1, + RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2, + RAS_GPU_IN_BAD_STATUS = 3, +}; + enum ras_core_fw_feature_flags { RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), }; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 7e5489fb5350b..bf980c0e2ff2a 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -403,7 +403,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core) goto init_err6; } - ret = ras_eeprom_check_storage_status(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_check_storage_status(ras_core); + else + ret = ras_eeprom_check_storage_status(ras_core); if (ret) goto init_err6; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h index 2abe566c18b67..f2c001ef64e1f 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h @@ -57,13 +57,6 @@ do { \ (RECORD)->retired_row_pfn = tmp; \ } while (0) -enum ras_gpu_health_status { - RAS_GPU_HEALTH_NONE = 0, - RAS_GPU_HEALTH_USABLE = 1, - RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2, - RAS_GPU_IN_BAD_STATUS = 3, -}; - enum ras_eeprom_err_type { RAS_EEPROM_ERR_NA, RAS_EEPROM_ERR_RECOVERABLE, diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 4362b8a0f3c46..70bbf1334c4f7 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -453,3 +453,54 @@ int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core) return 0; } + +int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int bad_page_count; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + + if ((control->record_threshold_count < bad_page_count) && + (control->record_threshold_config != 0)) { + RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d", + bad_page_count, control->record_threshold_count); + if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || + (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { + RAS_DEV_WARN(ras_core->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); + } else { + ras_core->is_rma = true; + RAS_DEV_ERR(ras_core->dev, + "User defined threshold is set, runtime service will be halt when threshold is reached\n"); + } + return 0; + } + + RAS_DEV_INFO(ras_core->dev, + "Found existing EEPROM table with %d records\n", + bad_page_count); + /* Warn if we are at 90% of the threshold or above + */ + if (10 * bad_page_count >= 9 * control->record_threshold_count) + RAS_DEV_WARN(ras_core->dev, + "RAS records:%u exceeds 90%% of threshold:%d\n", + bad_page_count, + control->record_threshold_count); + + return 0; +} + +enum ras_gpu_health_status + ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + + if (!control->record_threshold_config) + return RAS_GPU_HEALTH_NONE; + + if (ras_core->is_rma) + return RAS_GPU_RETIRED__ECC_REACH_THRESHOLD; + + return RAS_GPU_HEALTH_USABLE; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index cb92e6a63cf54..75d8b95c6923d 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -79,5 +79,8 @@ int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, struct ras_bank_ecc *ras_ecc); int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core); int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core); +int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core); +enum ras_gpu_health_status + ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core); #endif From d46dabc7e10de1ed9544895ab84e351b11dc8819 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Tue, 16 Dec 2025 14:31:23 +0800 Subject: [PATCH 1713/2070] drm/amd/ras: adapt sync info func for pmfw eeprom adapt sync info func for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 5 ++++- drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 14 ++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 1 + 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index bf980c0e2ff2a..10cd398d4ae23 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -258,7 +258,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core) return ret; } - ras_eeprom_sync_info(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ras_fw_eeprom_sync_info(ras_core); + else + ras_eeprom_sync_info(ras_core); return ret; } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c index 70bbf1334c4f7..29001e606d1bc 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -504,3 +504,17 @@ enum ras_gpu_health_status return RAS_GPU_HEALTH_USABLE; } + +void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control; + + if (!ras_core) + return; + + control = &ras_core->ras_fw_eeprom; + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + &control->ras_num_recs); + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + &control->bad_channel_bitmap); +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h index 75d8b95c6923d..762345be075c2 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -82,5 +82,6 @@ int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core); int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core); enum ras_gpu_health_status ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core); +void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core); #endif From bc656556859183df7cc8f819fbacf252ac309119 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Sat, 21 Feb 2026 20:11:03 +0800 Subject: [PATCH 1714/2070] drm/amdgpu: clear related counter after RAS eeprom reset Make eeprom data and its counter consistent. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 6fba9d5b29ea6..44fba4b6aa92a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -508,6 +508,9 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) control->bad_channel_bitmap = 0; amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); con->update_channel_flag = false; + /* there is no record on eeprom now, clear the counter */ + if (con->eh_data) + con->eh_data->count_saved = 0; amdgpu_ras_debugfs_set_ret_size(control); From f8078281a8d1f294c54902dc52636e63911cbe24 Mon Sep 17 00:00:00 2001 From: sguttula Date: Sat, 21 Feb 2026 10:03:32 +0530 Subject: [PATCH 1715/2070] drm/amdgpu/vcn5: Add SMU dpm interface type This will set AMDGPU_VCN_SMU_DPM_INTERFACE_* smu_type based on soc type and fixing ring timeout issue seen for DPM enabled case. Signed-off-by: sguttula Reviewed-by: Pratik Vishwakarma --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 0202df5db1e12..6109124f852e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -174,6 +174,10 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); fw_shared->sq.is_enabled = 1; + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); + fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? + AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; + if (amdgpu_vcnfw_log) amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); From 5d00012d6da00518b755f2062f5939e464e26e1e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 24 Feb 2026 10:18:51 +0530 Subject: [PATCH 1716/2070] drm/amdgpu: Fix error handling in slot reset If the device has not recovered after slot reset is called, it goes to out label for error handling. There it could make decision based on uninitialized hive pointer and could result in accessing an uninitialized list. Initialize the list and hive properly so that it handles the error situation and also releases the reset domain lock which is acquired during error_detected callback. Fixes: 732c6cefc1ec ("drm/amdgpu: Replace tmp_adev with hive in amdgpu_pci_slot_reset") Signed-off-by: Lijo Lazar Reviewed-by: Ce Sun --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c17a4ff69b1c3..e08de06c10b45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -7110,6 +7110,15 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) dev_info(adev->dev, "PCI error: slot reset callback!!\n"); memset(&reset_context, 0, sizeof(reset_context)); + INIT_LIST_HEAD(&device_list); + hive = amdgpu_get_xgmi_hive(adev); + if (hive) { + mutex_lock(&hive->hive_lock); + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) + list_add_tail(&tmp_adev->reset_list, &device_list); + } else { + list_add_tail(&adev->reset_list, &device_list); + } if (adev->pcie_reset_ctx.swus) link_dev = adev->pcie_reset_ctx.swus; @@ -7150,19 +7159,13 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) reset_context.reset_req_dev = adev; set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); - INIT_LIST_HEAD(&device_list); - hive = amdgpu_get_xgmi_hive(adev); if (hive) { - mutex_lock(&hive->hive_lock); reset_context.hive = hive; - list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) tmp_adev->pcie_reset_ctx.in_link_reset = true; - list_add_tail(&tmp_adev->reset_list, &device_list); - } } else { set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); - list_add_tail(&adev->reset_list, &device_list); } r = amdgpu_device_asic_reset(adev, &device_list, &reset_context); From b6668c5a7e954fbce2f207b57414e60b8a9f549d Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 25 Feb 2026 10:51:16 -0600 Subject: [PATCH 1717/2070] drm/amd: Disable MES LR compute W/A A workaround was introduced in commit 1fb710793ce2 ("drm/amdgpu: Enable MES lr_compute_wa by default") to help with some hangs observed in gfx1151. This WA didn't fully fix the issue. It was actually fixed by adjusting the VGPR size to the correct value that matched the hardware in commit cf326449637a5 ("drm/amdkfd: bump minimum vgpr size for gfx1151"). There are reports of instability on other products with newer GC microcode versions, and I believe they're caused by this workaround. As we don't need the workaround any more, remove it. Cc: stable@vger.kernel.org Fixes: cf326449637a5 ("drm/amdkfd: bump minimum vgpr size for gfx1151") Acked-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 5 ----- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 5 ----- 2 files changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 09ebb13ca5e81..a926a330700e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -720,11 +720,6 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; mes_set_hw_res_pkt.oversubscription_timer = 50; - if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) - mes_set_hw_res_pkt.enable_lr_compute_wa = 1; - else - dev_info_once(mes->adev->dev, - "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); if (amdgpu_mes_log_enable) { mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index b1c864dc79a86..5bfa5d1d0b369 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -779,11 +779,6 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; - if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82) - mes_set_hw_res_pkt.enable_lr_compute_wa = 1; - else - dev_info_once(adev->dev, - "MES FW version must be >= 0x82 to enable LR compute workaround.\n"); /* * Keep oversubscribe timer for sdma . When we have unmapped doorbell From 81c35520a5a7d7cede315ad7da9ae245705b0daf Mon Sep 17 00:00:00 2001 From: sguttula Date: Sat, 21 Feb 2026 10:47:59 +0530 Subject: [PATCH 1718/2070] drm/amdgpu: Enable DPG support for VCN5 This will set DPG flags for enabling power gating on GFX11_5_4 Signed-off-by: sguttula Reviewed-by: Pratik Vishwakarma --- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 8122a5cacf07a..a0ad1f8a76f06 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -858,7 +858,9 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) AMD_CG_SUPPORT_IH_CG | AMD_CG_SUPPORT_BIF_MGCG | AMD_CG_SUPPORT_BIF_LS; - adev->pg_flags = AMD_PG_SUPPORT_VCN | + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_JPEG_DPG | AMD_PG_SUPPORT_JPEG | AMD_PG_SUPPORT_GFX_PG; adev->external_rev_id = adev->rev_id + 0x1; From c6c9ed0298c820c29cfc10f50cf56ccfe5bb8469 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 25 Feb 2026 18:31:42 +0530 Subject: [PATCH 1719/2070] drm/amdgpu: Drop redundant timeline handle limit check in userq wait ioctl v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clang warns that comparing a __u16 value against 65536 is always false. num_syncobj_timeline_handles is defined as __u16, so it can never exceed 65535. v2: Drop the unnecessary check instead of changing the limit value. (Christian) Fixes the below: amdgpu_userq_fence.c:642:46: warning: result of comparison of constant 65536 with expression of type '__u16' (aka 'unsigned short') is always false [-Wtautological-constant-out-of-range-compare] wait_info->num_syncobj_timeline_handles > AMDGPU_USERQ_MAX_HANDLES || Fixes: 7d79dc596e6e ("drm/amdgpu: add upper bound check on user inputs in wait ioctl") Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher Change-Id: I40f77dd6659736c769b2dba55007f1c493337bd8 --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index dc6e133e20e9f..86319a9fef211 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -700,7 +700,6 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, return -ENOTSUPP; if (wait_info->num_syncobj_handles > AMDGPU_USERQ_MAX_HANDLES || - wait_info->num_syncobj_timeline_handles > AMDGPU_USERQ_MAX_HANDLES || wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) return -EINVAL; From 3ddd5b32e33e04fcd67de7a51e1df8f87a8e2747 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 15:41:07 +0530 Subject: [PATCH 1720/2070] drm/amdgpu: Move register access functions Move register access methods from amdgpu_device.c to a dedicated file. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 56 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 615 ----------------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 644 ++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 85 +++ 5 files changed, 731 insertions(+), 671 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index ce2e02ff1f395..9d24cf1e77f48 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -47,7 +47,7 @@ subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror amdgpu-y := amdgpu_drv.o # add KMS driver -amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ +amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 2d5029f3ae7bf..9c0bd9f04854a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -82,6 +82,7 @@ #include "amdgpu_sdma.h" #include "amdgpu_lsdma.h" #include "amdgpu_nbio.h" +#include "amdgpu_reg_access.h" #include "amdgpu_hdp.h" #include "amdgpu_dm.h" #include "amdgpu_virt.h" @@ -687,21 +688,6 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); /* * Core structure, functions and helpers. */ -typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); -typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); - -typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); -typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); - -typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); -typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); - -typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); -typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); - -typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); -typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); - struct amdgpu_mmio_remap { u32 reg_offset; resource_size_t bus_addr; @@ -1334,42 +1320,6 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, void *buf, size_t size, bool write); -uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, - uint32_t inst, uint32_t reg_addr, char reg_name[], - uint32_t expected_value, uint32_t mask); -uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags); -u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, - u64 reg_addr); -uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags, - uint32_t xcc_id); -void amdgpu_device_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags); -void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, - u64 reg_addr, u32 reg_data); -void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags, - uint32_t xcc_id); -void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, uint32_t xcc_id); -void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); -uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); - -u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, - u32 reg_addr); -u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, - u32 reg_addr); -u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, - u64 reg_addr); -void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, - u32 reg_addr, u32 reg_data); -void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, - u32 reg_addr, u64 reg_data); -void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, - u64 reg_addr, u64 reg_data); u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, enum amd_asic_type asic_type); @@ -1567,10 +1517,6 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring); void amdgpu_device_halt(struct amdgpu_device *adev); -u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, - u32 reg); -void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, - u32 reg, u32 v); struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, struct dma_fence *gang); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e08de06c10b45..fa9fb200c6635 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -853,558 +853,6 @@ bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) return false; } -/** - * amdgpu_device_rreg - read a memory mapped IO or indirect register - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @acc_flags: access flags which require special behavior - * - * Returns the 32 bit value from the offset specified. - */ -uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags) -{ - uint32_t ret; - - if (amdgpu_device_skip_hw_access(adev)) - return 0; - - if ((reg * 4) < adev->rmmio_size) { - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_kiq_rreg(adev, reg, 0); - up_read(&adev->reset_domain->sem); - } else { - ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - ret = adev->pcie_rreg(adev, reg * 4); - } - - trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); - - return ret; -} - -/* - * MMIO register read with bytes helper functions - * @offset:bytes offset from MMIO start - */ - -/** - * amdgpu_mm_rreg8 - read a memory mapped IO register - * - * @adev: amdgpu_device pointer - * @offset: byte aligned register offset - * - * Returns the 8 bit value from the offset specified. - */ -uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) -{ - if (amdgpu_device_skip_hw_access(adev)) - return 0; - - if (offset < adev->rmmio_size) - return (readb(adev->rmmio + offset)); - BUG(); -} - - -/** - * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @acc_flags: access flags which require special behavior - * @xcc_id: xcc accelerated compute core id - * - * Returns the 32 bit value from the offset specified. - */ -uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags, - uint32_t xcc_id) -{ - uint32_t ret, rlcg_flag; - - if (amdgpu_device_skip_hw_access(adev)) - return 0; - - if ((reg * 4) < adev->rmmio_size) { - if (amdgpu_sriov_vf(adev) && - !amdgpu_sriov_runtime(adev) && - adev->gfx.rlc.rlcg_reg_access_supported && - amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, - GC_HWIP, false, - &rlcg_flag)) { - ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); - } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_kiq_rreg(adev, reg, xcc_id); - up_read(&adev->reset_domain->sem); - } else { - ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - ret = adev->pcie_rreg(adev, reg * 4); - } - - return ret; -} - -/* - * MMIO register write with bytes helper functions - * @offset:bytes offset from MMIO start - * @value: the value want to be written to the register - */ - -/** - * amdgpu_mm_wreg8 - read a memory mapped IO register - * - * @adev: amdgpu_device pointer - * @offset: byte aligned register offset - * @value: 8 bit value to write - * - * Writes the value specified to the offset specified. - */ -void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) -{ - if (amdgpu_device_skip_hw_access(adev)) - return; - - if (offset < adev->rmmio_size) - writeb(value, adev->rmmio + offset); - else - BUG(); -} - -/** - * amdgpu_device_wreg - write to a memory mapped IO or indirect register - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @v: 32 bit value to write to the register - * @acc_flags: access flags which require special behavior - * - * Writes the value specified to the offset specified. - */ -void amdgpu_device_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags) -{ - if (amdgpu_device_skip_hw_access(adev)) - return; - - if ((reg * 4) < adev->rmmio_size) { - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - amdgpu_kiq_wreg(adev, reg, v, 0); - up_read(&adev->reset_domain->sem); - } else { - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - adev->pcie_wreg(adev, reg * 4, v); - } - - trace_amdgpu_device_wreg(adev->pdev->device, reg, v); -} - -/** - * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range - * - * @adev: amdgpu_device pointer - * @reg: mmio/rlc register - * @v: value to write - * @xcc_id: xcc accelerated compute core id - * - * this function is invoked only for the debugfs register access - */ -void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t xcc_id) -{ - if (amdgpu_device_skip_hw_access(adev)) - return; - - if (amdgpu_sriov_fullaccess(adev) && - adev->gfx.rlc.funcs && - adev->gfx.rlc.funcs->is_rlcg_access_range) { - if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) - return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); - } else if ((reg * 4) >= adev->rmmio_size) { - adev->pcie_wreg(adev, reg * 4, v); - } else { - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } -} - -/** - * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @v: 32 bit value to write to the register - * @acc_flags: access flags which require special behavior - * @xcc_id: xcc accelerated compute core id - * - * Writes the value specified to the offset specified. - */ -void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags, uint32_t xcc_id) -{ - uint32_t rlcg_flag; - - if (amdgpu_device_skip_hw_access(adev)) - return; - - if ((reg * 4) < adev->rmmio_size) { - if (amdgpu_sriov_vf(adev) && - !amdgpu_sriov_runtime(adev) && - adev->gfx.rlc.rlcg_reg_access_supported && - amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, - GC_HWIP, true, - &rlcg_flag)) { - amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); - } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - amdgpu_kiq_wreg(adev, reg, v, xcc_id); - up_read(&adev->reset_domain->sem); - } else { - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - adev->pcie_wreg(adev, reg * 4, v); - } -} - -/** - * amdgpu_device_indirect_rreg - read an indirect register - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register address to read from - * - * Returns the value of indirect register @reg_addr - */ -u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, - u32 reg_addr) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - u32 r; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - r = readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, - u64 reg_addr) -{ - unsigned long flags, pcie_index, pcie_index_hi, pcie_data; - u32 r; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - - if (unlikely(!adev->nbio.funcs)) { - pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; - pcie_data = AMDGPU_PCIE_DATA_FALLBACK; - } else { - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - } - - if (reg_addr >> 32) { - if (unlikely(!adev->nbio.funcs)) - pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK; - else - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - } else { - pcie_index_hi = 0; - } - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - r = readl(pcie_data_offset); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -/** - * amdgpu_device_indirect_rreg64 - read a 64bits indirect register - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register address to read from - * - * Returns the value of indirect register @reg_addr - */ -u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, - u32 reg_addr) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - u64 r; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - /* read low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - r = readl(pcie_data_offset); - /* read high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - r |= ((u64)readl(pcie_data_offset) << 32); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, - u64 reg_addr) -{ - unsigned long flags, pcie_index, pcie_data; - unsigned long pcie_index_hi = 0; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - u64 r; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - /* read low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - r = readl(pcie_data_offset); - /* read high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - r |= ((u64)readl(pcie_data_offset) << 32); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -/** - * amdgpu_device_indirect_wreg - write an indirect register address - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register offset - * @reg_data: indirect register data - * - */ -void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, - u32 reg_addr, u32 reg_data) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - writel(reg_data, pcie_data_offset); - readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, - u64 reg_addr, u32 reg_data) -{ - unsigned long flags, pcie_index, pcie_index_hi, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - else - pcie_index_hi = 0; - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - writel(reg_data, pcie_data_offset); - readl(pcie_data_offset); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -/** - * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register offset - * @reg_data: indirect register data - * - */ -void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, - u32 reg_addr, u64 reg_data) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - /* write low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); - readl(pcie_data_offset); - /* write high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - writel((u32)(reg_data >> 32), pcie_data_offset); - readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, - u64 reg_addr, u64 reg_data) -{ - unsigned long flags, pcie_index, pcie_data; - unsigned long pcie_index_hi = 0; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - /* write low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); - readl(pcie_data_offset); - /* write high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - writel((u32)(reg_data >> 32), pcie_data_offset); - readl(pcie_data_offset); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - /** * amdgpu_device_get_rev_id - query device rev_id * @@ -7427,39 +6875,6 @@ void amdgpu_device_halt(struct amdgpu_device *adev) pci_wait_for_pending_transaction(pdev); } -u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, - u32 reg) -{ - unsigned long flags, address, data; - u32 r; - - address = adev->nbio.funcs->get_pcie_port_index_offset(adev); - data = adev->nbio.funcs->get_pcie_port_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - WREG32(address, reg * 4); - (void)RREG32(address); - r = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - return r; -} - -void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, - u32 reg, u32 v) -{ - unsigned long flags, address, data; - - address = adev->nbio.funcs->get_pcie_port_index_offset(adev); - data = adev->nbio.funcs->get_pcie_port_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - WREG32(address, reg * 4); - (void)RREG32(address); - WREG32(data, v); - (void)RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - /** * amdgpu_device_get_gang - return a reference to the current gang * @adev: amdgpu_device pointer @@ -7642,36 +7057,6 @@ bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev) } } -uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, - uint32_t inst, uint32_t reg_addr, char reg_name[], - uint32_t expected_value, uint32_t mask) -{ - uint32_t ret = 0; - uint32_t old_ = 0; - uint32_t tmp_ = RREG32(reg_addr); - uint32_t loop = adev->usec_timeout; - - while ((tmp_ & (mask)) != (expected_value)) { - if (old_ != tmp_) { - loop = adev->usec_timeout; - old_ = tmp_; - } else - udelay(1); - tmp_ = RREG32(reg_addr); - loop--; - if (!loop) { - dev_warn( - adev->dev, - "Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn", - inst, reg_name, (uint32_t)expected_value, - (uint32_t)(tmp_ & (mask))); - ret = -ETIMEDOUT; - break; - } - } - return ret; -} - ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring) { ssize_t size = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c new file mode 100644 index 0000000000000..4b8888f82b64b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "amdgpu.h" +#include "amdgpu_reset.h" +#include "amdgpu_trace.h" +#include "amdgpu_virt.h" +#include "amdgpu_reg_access.h" + +#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2) +#define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) +#define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2) + +/* + * register access helper functions. + */ + +/** + * amdgpu_device_rreg - read a memory mapped IO or indirect register + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @acc_flags: access flags which require special behavior + * + * Returns the 32 bit value from the offset specified. + */ +uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags) +{ + uint32_t ret; + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if ((reg * 4) < adev->rmmio_size) { + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_kiq_rreg(adev, reg, 0); + up_read(&adev->reset_domain->sem); + } else { + ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + ret = adev->pcie_rreg(adev, reg * 4); + } + + trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); + + return ret; +} + +/* + * MMIO register read with bytes helper functions + * @offset:bytes offset from MMIO start + */ + +/** + * amdgpu_mm_rreg8 - read a memory mapped IO register + * + * @adev: amdgpu_device pointer + * @offset: byte aligned register offset + * + * Returns the 8 bit value from the offset specified. + */ +uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) +{ + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if (offset < adev->rmmio_size) + return (readb(adev->rmmio + offset)); + BUG(); +} + +/** + * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @acc_flags: access flags which require special behavior + * @xcc_id: xcc accelerated compute core id + * + * Returns the 32 bit value from the offset specified. + */ +uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags, uint32_t xcc_id) +{ + uint32_t ret, rlcg_flag; + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if ((reg * 4) < adev->rmmio_size) { + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_runtime(adev) && + adev->gfx.rlc.rlcg_reg_access_supported && + amdgpu_virt_get_rlcg_reg_access_flag( + adev, acc_flags, GC_HWIP, false, &rlcg_flag)) { + ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, + GET_INST(GC, xcc_id)); + } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_kiq_rreg(adev, reg, xcc_id); + up_read(&adev->reset_domain->sem); + } else { + ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + ret = adev->pcie_rreg(adev, reg * 4); + } + + return ret; +} + +/* + * MMIO register write with bytes helper functions + * @offset:bytes offset from MMIO start + * @value: the value want to be written to the register + */ + +/** + * amdgpu_mm_wreg8 - read a memory mapped IO register + * + * @adev: amdgpu_device pointer + * @offset: byte aligned register offset + * @value: 8 bit value to write + * + * Writes the value specified to the offset specified. + */ +void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) +{ + if (amdgpu_device_skip_hw_access(adev)) + return; + + if (offset < adev->rmmio_size) + writeb(value, adev->rmmio + offset); + else + BUG(); +} + +/** + * amdgpu_device_wreg - write to a memory mapped IO or indirect register + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @v: 32 bit value to write to the register + * @acc_flags: access flags which require special behavior + * + * Writes the value specified to the offset specified. + */ +void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + uint32_t acc_flags) +{ + if (amdgpu_device_skip_hw_access(adev)) + return; + + if ((reg * 4) < adev->rmmio_size) { + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_kiq_wreg(adev, reg, v, 0); + up_read(&adev->reset_domain->sem); + } else { + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + adev->pcie_wreg(adev, reg * 4, v); + } + + trace_amdgpu_device_wreg(adev->pdev->device, reg, v); +} + +/** + * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range + * + * @adev: amdgpu_device pointer + * @reg: mmio/rlc register + * @v: value to write + * @xcc_id: xcc accelerated compute core id + * + * this function is invoked only for the debugfs register access + */ +void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t xcc_id) +{ + if (amdgpu_device_skip_hw_access(adev)) + return; + + if (amdgpu_sriov_fullaccess(adev) && adev->gfx.rlc.funcs && + adev->gfx.rlc.funcs->is_rlcg_access_range) { + if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) + return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); + } else if ((reg * 4) >= adev->rmmio_size) { + adev->pcie_wreg(adev, reg * 4, v); + } else { + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } +} + +/** + * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @v: 32 bit value to write to the register + * @acc_flags: access flags which require special behavior + * @xcc_id: xcc accelerated compute core id + * + * Writes the value specified to the offset specified. + */ +void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t acc_flags, uint32_t xcc_id) +{ + uint32_t rlcg_flag; + + if (amdgpu_device_skip_hw_access(adev)) + return; + + if ((reg * 4) < adev->rmmio_size) { + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_runtime(adev) && + adev->gfx.rlc.rlcg_reg_access_supported && + amdgpu_virt_get_rlcg_reg_access_flag( + adev, acc_flags, GC_HWIP, true, &rlcg_flag)) { + amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, + GET_INST(GC, xcc_id)); + } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_kiq_wreg(adev, reg, v, xcc_id); + up_read(&adev->reset_domain->sem); + } else { + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + adev->pcie_wreg(adev, reg * 4, v); + } +} + +/** + * amdgpu_device_indirect_rreg - read an indirect register + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register address to read from + * + * Returns the value of indirect register @reg_addr + */ +u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + u32 r; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + r = readl(pcie_data_offset); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + + return r; +} + +u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr) +{ + unsigned long flags, pcie_index, pcie_index_hi, pcie_data; + u32 r; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + + if (unlikely(!adev->nbio.funcs)) { + pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; + pcie_data = AMDGPU_PCIE_DATA_FALLBACK; + } else { + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + } + + if (reg_addr >> 32) { + if (unlikely(!adev->nbio.funcs)) + pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK; + else + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset( + adev); + } else { + pcie_index_hi = 0; + } + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + r = readl(pcie_data_offset); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + + return r; +} + +/** + * amdgpu_device_indirect_rreg64 - read a 64bits indirect register + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register address to read from + * + * Returns the value of indirect register @reg_addr + */ +u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + u64 r; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + /* read low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + r = readl(pcie_data_offset); + /* read high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + r |= ((u64)readl(pcie_data_offset) << 32); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + + return r; +} + +u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr) +{ + unsigned long flags, pcie_index, pcie_data; + unsigned long pcie_index_hi = 0; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + u64 r; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + /* read low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + r = readl(pcie_data_offset); + /* read high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + r |= ((u64)readl(pcie_data_offset) << 32); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + + return r; +} + +/** + * amdgpu_device_indirect_wreg - write an indirect register address + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register offset + * @reg_data: indirect register data + * + */ +void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, + u32 reg_data) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + writel(reg_data, pcie_data_offset); + readl(pcie_data_offset); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, + u32 reg_data) +{ + unsigned long flags, pcie_index, pcie_index_hi, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset(adev); + else + pcie_index_hi = 0; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + writel(reg_data, pcie_data_offset); + readl(pcie_data_offset); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +/** + * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register offset + * @reg_data: indirect register data + * + */ +void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, + u64 reg_data) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + /* write low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); + readl(pcie_data_offset); + /* write high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + writel((u32)(reg_data >> 32), pcie_data_offset); + readl(pcie_data_offset); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, + u64 reg_data) +{ + unsigned long flags, pcie_index, pcie_data; + unsigned long pcie_index_hi = 0; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + /* write low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); + readl(pcie_data_offset); + /* write high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + writel((u32)(reg_data >> 32), pcie_data_offset); + readl(pcie_data_offset); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags, address, data; + u32 r; + + address = adev->nbio.funcs->get_pcie_port_index_offset(adev); + data = adev->nbio.funcs->get_pcie_port_data_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(address, reg * 4); + (void)RREG32(address); + r = RREG32(data); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + return r; +} + +void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags, address, data; + + address = adev->nbio.funcs->get_pcie_port_index_offset(adev); + data = adev->nbio.funcs->get_pcie_port_data_offset(adev); + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(address, reg * 4); + (void)RREG32(address); + WREG32(data, v); + (void)RREG32(data); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, + uint32_t reg_addr, char reg_name[], + uint32_t expected_value, uint32_t mask) +{ + uint32_t ret = 0; + uint32_t old_ = 0; + uint32_t tmp_ = RREG32(reg_addr); + uint32_t loop = adev->usec_timeout; + + while ((tmp_ & (mask)) != (expected_value)) { + if (old_ != tmp_) { + loop = adev->usec_timeout; + old_ = tmp_; + } else + udelay(1); + tmp_ = RREG32(reg_addr); + loop--; + if (!loop) { + dev_warn( + adev->dev, + "Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn", + inst, reg_name, (uint32_t)expected_value, + (uint32_t)(tmp_ & (mask))); + ret = -ETIMEDOUT; + break; + } + } + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h new file mode 100644 index 0000000000000..e03865c0c093f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_REG_ACCESS_H__ +#define __AMDGPU_REG_ACCESS_H__ + +#include + +struct amdgpu_device; + +/* + * Registers read & write functions. + */ +typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); +typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); + +typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); +typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); + +typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); +typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); + +typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); +typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); + +typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, + uint32_t); +typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, + uint32_t); + +uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags); +uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags, uint32_t xcc_id); +void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + uint32_t acc_flags); +void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t acc_flags, uint32_t xcc_id); +void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t xcc_id); +void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, + uint8_t value); +uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); + +u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr); +u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr); +u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr); +u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr); +void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, + u32 reg_data); +void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, + u32 reg_data); +void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, + u64 reg_data); +void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, + u64 reg_data); + +u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg); +void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v); + +uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, + uint32_t reg_addr, char reg_name[], + uint32_t expected_value, uint32_t mask); + +#endif /* __AMDGPU_REG_ACCESS_H__ */ From c787eea2778c1970ca919b1b405b3ad0101d33f8 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 18:26:09 +0530 Subject: [PATCH 1721/2070] drm/amdgpu: Add smc method to register block Define register access block which consolidates different register access methods. Add smc method to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++-- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 25 +++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 18 ++++++++++-- drivers/gpu/drm/amd/amdgpu/cik.c | 16 +++++------ drivers/gpu/drm/amd/amdgpu/nv.c | 2 -- drivers/gpu/drm/amd/amdgpu/si.c | 12 ++++---- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc21.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/vi.c | 28 +++++++++---------- drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 16 +++++------ 14 files changed, 84 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 9c0bd9f04854a..e6b5998bb7f40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -921,10 +921,8 @@ struct amdgpu_device { /* protects concurrent MM_INDEX/DATA based register access */ spinlock_t mmio_idx_lock; struct amdgpu_mmio_remap rmmio_remap; - /* protects concurrent SMC based register access */ - spinlock_t smc_idx_lock; - amdgpu_rreg_t smc_rreg; - amdgpu_wreg_t smc_wreg; + /* Indirect register access blocks */ + struct amdgpu_reg_access reg; /* protects concurrent PCIE register access */ spinlock_t pcie_idx_lock; amdgpu_rreg_t pcie_rreg; @@ -1369,8 +1367,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) -#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) -#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) +#define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) +#define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 66ca14073948c..7495eabd366ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -752,7 +752,7 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, ssize_t result = 0; int r; - if (!adev->smc_rreg) + if (!adev->reg.smc.rreg) return -EOPNOTSUPP; if (size & 0x3 || *pos & 0x3) @@ -810,7 +810,7 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * ssize_t result = 0; int r; - if (!adev->smc_wreg) + if (!adev->reg.smc.wreg) return -EOPNOTSUPP; if (size & 0x3 || *pos & 0x3) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fa9fb200c6635..fa0c914b04b37 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3863,8 +3863,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); - adev->smc_rreg = &amdgpu_invalid_rreg; - adev->smc_wreg = &amdgpu_invalid_wreg; + amdgpu_reg_access_init(adev); + adev->pcie_rreg = &amdgpu_invalid_rreg; adev->pcie_wreg = &amdgpu_invalid_wreg; adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; @@ -3929,7 +3929,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, return r; spin_lock_init(&adev->mmio_idx_lock); - spin_lock_init(&adev->smc_idx_lock); spin_lock_init(&adev->pcie_idx_lock); spin_lock_init(&adev->uvd_ctx_idx_lock); spin_lock_init(&adev->didt_idx_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 4b8888f82b64b..5debc5c39101b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -33,6 +33,31 @@ #define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) #define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2) +void amdgpu_reg_access_init(struct amdgpu_device *adev) +{ + spin_lock_init(&adev->reg.smc.lock); + adev->reg.smc.rreg = NULL; + adev->reg.smc.wreg = NULL; +} + +uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.smc.rreg) { + dev_err_once(adev->dev, "SMC register read not supported\n"); + return 0; + } + return adev->reg.smc.rreg(adev, reg); +} + +void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.smc.wreg) { + dev_err_once(adev->dev, "SMC register write not supported\n"); + return; + } + adev->reg.smc.wreg(adev, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index e03865c0c093f..225d89eabed51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -25,15 +25,27 @@ #define __AMDGPU_REG_ACCESS_H__ #include +#include struct amdgpu_device; -/* - * Registers read & write functions. - */ typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); +struct amdgpu_reg_ind { + spinlock_t lock; + amdgpu_rreg_t rreg; + amdgpu_wreg_t wreg; +}; + +struct amdgpu_reg_access { + struct amdgpu_reg_ind smc; +}; + +void amdgpu_reg_access_init(struct amdgpu_device *adev); +uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); + typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index c081784a19c4f..cd5cd5da4d47e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -179,10 +179,10 @@ static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); r = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -190,10 +190,10 @@ static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); WREG32(mmSMC_IND_DATA_0, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) @@ -1027,7 +1027,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, dw_ptr = (u32 *)bios; length_dw = ALIGN(length_bytes, 4) / 4; /* take the smc lock since we are using the smc index */ - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); /* set rom index to 0 */ WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); WREG32(mmSMC_IND_DATA_0, 0); @@ -1035,7 +1035,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); for (i = 0; i < length_dw; i++) dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return true; } @@ -1984,8 +1984,8 @@ static int cik_common_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->smc_rreg = &cik_smc_rreg; - adev->smc_wreg = &cik_smc_wreg; + adev->reg.smc.rreg = cik_smc_rreg; + adev->reg.smc.wreg = cik_smc_wreg; adev->pcie_rreg = &cik_pcie_rreg; adev->pcie_wreg = &cik_pcie_wreg; adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index f17c3839aea19..2e7cd27e45c97 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -635,8 +635,6 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 509d43b238f3f..cbdf8a1c6511b 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1077,10 +1077,10 @@ static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); r = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -1088,10 +1088,10 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); WREG32(mmSMC_IND_DATA_0, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) @@ -2037,8 +2037,8 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->smc_rreg = &si_smc_rreg; - adev->smc_wreg = &si_smc_wreg; + adev->reg.smc.rreg = si_smc_rreg; + adev->reg.smc.wreg = si_smc_wreg; adev->pcie_rreg = &si_pcie_rreg; adev->pcie_wreg = &si_pcie_wreg; adev->pciep_rreg = &si_pciep_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4e037a6978f09..057787ffd19c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -961,8 +961,6 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index a0ad1f8a76f06..4d4c1adf00d1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -589,8 +589,6 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index ecb6c3fcfbd15..867cc4fdc98fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -362,8 +362,6 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 59ab952d5cce4..f8a49424adeb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -250,8 +250,6 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 6a574b6c8e631..925cc275fe849 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -324,10 +324,10 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -335,10 +335,10 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } /* smu_8_0_d.h */ @@ -350,10 +350,10 @@ static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmMP0PUB_IND_INDEX, (reg)); r = RREG32(mmMP0PUB_IND_DATA); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -361,10 +361,10 @@ static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmMP0PUB_IND_INDEX, (reg)); WREG32(mmMP0PUB_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) @@ -649,7 +649,7 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, dw_ptr = (u32 *)bios; length_dw = ALIGN(length_bytes, 4) / 4; /* take the smc lock since we are using the smc index */ - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); /* set rom index to 0 */ WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); WREG32(mmSMC_IND_DATA_11, 0); @@ -657,7 +657,7 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); for (i = 0; i < length_dw; i++) dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return true; } @@ -1454,11 +1454,11 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; if (adev->flags & AMD_IS_APU) { - adev->smc_rreg = &cz_smc_rreg; - adev->smc_wreg = &cz_smc_wreg; + adev->reg.smc.rreg = cz_smc_rreg; + adev->reg.smc.wreg = cz_smc_wreg; } else { - adev->smc_rreg = &vi_smc_rreg; - adev->smc_wreg = &vi_smc_wreg; + adev->reg.smc.rreg = vi_smc_rreg; + adev->reg.smc.wreg = vi_smc_wreg; } adev->pcie_rreg = &vi_pcie_rreg; adev->pcie_wreg = &vi_pcie_wreg; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c index 281a5e377aee4..e1c509bfc3902 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c @@ -65,7 +65,7 @@ int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, addr = smc_start_address; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); while (byte_count >= 4) { /* SMC address space is BE */ data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; @@ -109,7 +109,7 @@ int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, } done: - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return ret; } @@ -252,7 +252,7 @@ int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) if (ucode_size & 3) return -EINVAL; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, ucode_start_address); WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); while (ucode_size >= 4) { @@ -265,7 +265,7 @@ int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) ucode_size -= 4; } WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return 0; } @@ -276,11 +276,11 @@ int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, unsigned long flags; int ret; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); ret = si_set_smc_sram_address(adev, smc_address, limit); if (ret == 0) *value = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return ret; } @@ -291,11 +291,11 @@ int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, unsigned long flags; int ret; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); ret = si_set_smc_sram_address(adev, smc_address, limit); if (ret == 0) WREG32(mmSMC_IND_DATA_0, value); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return ret; } From 58c48429bbb09c926d72b12175c0ba0f1f650602 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 18:38:52 +0530 Subject: [PATCH 1722/2070] drm/amdgpu: Add uvd indirect to register block Add uvd indirect method to register access block and replace the existing calls from adev. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +++----- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 --- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 25 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 3 +++ drivers/gpu/drm/amd/amdgpu/cik.c | 12 ++++----- drivers/gpu/drm/amd/amdgpu/nv.c | 4 --- drivers/gpu/drm/amd/amdgpu/si.c | 12 ++++----- drivers/gpu/drm/amd/amdgpu/soc15.c | 12 ++++----- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 --- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/vi.c | 12 ++++----- 12 files changed, 55 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e6b5998bb7f40..fd3414a7441f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -934,11 +934,7 @@ struct amdgpu_device { amdgpu_rreg64_t pcie_rreg64; amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; - amdgpu_wreg64_ext_t pcie_wreg64_ext; - /* protects concurrent UVD register access */ - spinlock_t uvd_ctx_idx_lock; - amdgpu_rreg_t uvd_ctx_rreg; - amdgpu_wreg_t uvd_ctx_wreg; + amdgpu_wreg64_ext_t pcie_wreg64_ext; /* protects concurrent DIDT register access */ spinlock_t didt_idx_lock; amdgpu_rreg_t didt_rreg; @@ -1369,8 +1365,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) -#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) -#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) +#define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) +#define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fa0c914b04b37..5065deb4d148a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3875,8 +3875,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; - adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; - adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; adev->didt_rreg = &amdgpu_invalid_rreg; adev->didt_wreg = &amdgpu_invalid_wreg; adev->gc_cac_rreg = &amdgpu_invalid_rreg; @@ -3930,7 +3928,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->pcie_idx_lock); - spin_lock_init(&adev->uvd_ctx_idx_lock); spin_lock_init(&adev->didt_idx_lock); spin_lock_init(&adev->gc_cac_idx_lock); spin_lock_init(&adev->se_cac_idx_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 5debc5c39101b..1f5d6be9a0fde 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -38,6 +38,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) spin_lock_init(&adev->reg.smc.lock); adev->reg.smc.rreg = NULL; adev->reg.smc.wreg = NULL; + + spin_lock_init(&adev->reg.uvd_ctx.lock); + adev->reg.uvd_ctx.rreg = NULL; + adev->reg.uvd_ctx.wreg = NULL; } uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) @@ -58,6 +62,27 @@ void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) adev->reg.smc.wreg(adev, reg, v); } +uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.uvd_ctx.rreg) { + dev_err_once(adev->dev, + "UVD_CTX register read not supported\n"); + return 0; + } + return adev->reg.uvd_ctx.rreg(adev, reg); +} + +void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v) +{ + if (!adev->reg.uvd_ctx.wreg) { + dev_err_once(adev->dev, + "UVD_CTX register write not supported\n"); + return; + } + adev->reg.uvd_ctx.wreg(adev, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 225d89eabed51..0d66a13c8d5c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -40,11 +40,14 @@ struct amdgpu_reg_ind { struct amdgpu_reg_access { struct amdgpu_reg_ind smc; + struct amdgpu_reg_ind uvd_ctx; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index cd5cd5da4d47e..342a496b60204 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -201,10 +201,10 @@ static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); r = RREG32(mmUVD_CTX_DATA); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -212,10 +212,10 @@ static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32(mmUVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) @@ -1988,8 +1988,8 @@ static int cik_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.smc.wreg = cik_smc_wreg; adev->pcie_rreg = &cik_pcie_rreg; adev->pcie_wreg = &cik_pcie_wreg; - adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; - adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; + adev->reg.uvd_ctx.rreg = &cik_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &cik_uvd_ctx_wreg; adev->didt_rreg = &cik_didt_rreg; adev->didt_wreg = &cik_didt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 2e7cd27e45c97..d0bc2dcd30663 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -642,10 +642,6 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_rreg = amdgpu_device_pcie_port_rreg; adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - /* TODO: will add them during VCN v2 implementation */ - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; - adev->didt_rreg = &nv_didt_rreg; adev->didt_wreg = &nv_didt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index cbdf8a1c6511b..bbf352ce8a64d 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1099,10 +1099,10 @@ static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); r = RREG32(mmUVD_CTX_DATA); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -1110,10 +1110,10 @@ static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32(mmUVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { @@ -2043,8 +2043,8 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg = &si_pcie_wreg; adev->pciep_rreg = &si_pciep_rreg; adev->pciep_wreg = &si_pciep_wreg; - adev->uvd_ctx_rreg = si_uvd_ctx_rreg; - adev->uvd_ctx_wreg = si_uvd_ctx_wreg; + adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; adev->didt_rreg = NULL; adev->didt_wreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 057787ffd19c9..44bc1b71e3956 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -245,10 +245,10 @@ static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(address, ((reg) & 0x1ff)); r = RREG32(data); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -259,10 +259,10 @@ static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(address, ((reg) & 0x1ff)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) @@ -969,8 +969,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; - adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; - adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; + adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; adev->didt_rreg = &soc15_didt_rreg; adev->didt_wreg = &soc15_didt_wreg; adev->gc_cac_rreg = &soc15_gc_cac_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 4d4c1adf00d1e..75ed71b1f2423 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -596,10 +596,6 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_rreg = amdgpu_device_pcie_port_rreg; adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - /* TODO: will add them during VCN v2 implementation */ - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; - adev->didt_rreg = &soc21_didt_rreg; adev->didt_wreg = &soc21_didt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 867cc4fdc98fe..d4f3df165090c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -368,8 +368,6 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->pciep_rreg = amdgpu_device_pcie_port_rreg; adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; adev->didt_rreg = NULL; adev->didt_wreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index f8a49424adeb4..6439b09656bff 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -260,8 +260,6 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_wreg = amdgpu_device_pcie_port_wreg; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; adev->didt_rreg = NULL; adev->didt_wreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 925cc275fe849..7d3b331d9217d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -372,10 +372,10 @@ static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); r = RREG32(mmUVD_CTX_DATA); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -383,10 +383,10 @@ static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32(mmUVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) @@ -1462,8 +1462,8 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) } adev->pcie_rreg = &vi_pcie_rreg; adev->pcie_wreg = &vi_pcie_wreg; - adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; - adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; + adev->reg.uvd_ctx.rreg = &vi_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; adev->didt_rreg = &vi_didt_rreg; adev->didt_wreg = &vi_didt_wreg; adev->gc_cac_rreg = &vi_gc_cac_rreg; From fd46fe6fa9a9abe894ad41915acdec2f95878169 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 18:52:42 +0530 Subject: [PATCH 1723/2070] drm/amdgpu: Add didt method to register block Move didt callbacks to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++----- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 --- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 22 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 3 +++ drivers/gpu/drm/amd/amdgpu/cik.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/nv.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/si.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc15.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/soc21.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 -- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/vi.c | 12 +++++----- 13 files changed, 59 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index fd3414a7441f5..8bbb20a807b03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -935,10 +935,6 @@ struct amdgpu_device { amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; amdgpu_wreg64_ext_t pcie_wreg64_ext; - /* protects concurrent DIDT register access */ - spinlock_t didt_idx_lock; - amdgpu_rreg_t didt_rreg; - amdgpu_wreg_t didt_wreg; /* protects concurrent gc_cac register access */ spinlock_t gc_cac_idx_lock; amdgpu_rreg_t gc_cac_rreg; @@ -1367,8 +1363,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) -#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) -#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) +#define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) +#define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 7495eabd366ab..b22ed547a563e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -638,7 +638,7 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, if (size & 0x3 || *pos & 0x3) return -EINVAL; - if (!adev->didt_rreg) + if (!adev->reg.didt.rreg) return -EOPNOTSUPP; r = pm_runtime_get_sync(adev_to_drm(adev)->dev); @@ -696,7 +696,7 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user if (size & 0x3 || *pos & 0x3) return -EINVAL; - if (!adev->didt_wreg) + if (!adev->reg.didt.wreg) return -EOPNOTSUPP; r = pm_runtime_get_sync(adev_to_drm(adev)->dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5065deb4d148a..b0fa1dea4c392 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3875,8 +3875,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; - adev->didt_rreg = &amdgpu_invalid_rreg; - adev->didt_wreg = &amdgpu_invalid_wreg; adev->gc_cac_rreg = &amdgpu_invalid_rreg; adev->gc_cac_wreg = &amdgpu_invalid_wreg; adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; @@ -3928,7 +3926,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->pcie_idx_lock); - spin_lock_init(&adev->didt_idx_lock); spin_lock_init(&adev->gc_cac_idx_lock); spin_lock_init(&adev->se_cac_idx_lock); spin_lock_init(&adev->audio_endpt_idx_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 1f5d6be9a0fde..c31c86bbf18ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -42,6 +42,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) spin_lock_init(&adev->reg.uvd_ctx.lock); adev->reg.uvd_ctx.rreg = NULL; adev->reg.uvd_ctx.wreg = NULL; + + spin_lock_init(&adev->reg.didt.lock); + adev->reg.didt.rreg = NULL; + adev->reg.didt.wreg = NULL; } uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) @@ -83,6 +87,24 @@ void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, adev->reg.uvd_ctx.wreg(adev, reg, v); } +uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.didt.rreg) { + dev_err_once(adev->dev, "DIDT register read not supported\n"); + return 0; + } + return adev->reg.didt.rreg(adev, reg); +} + +void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.didt.wreg) { + dev_err_once(adev->dev, "DIDT register write not supported\n"); + return; + } + adev->reg.didt.wreg(adev, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 0d66a13c8d5c2..239dbd6ef2f6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -41,6 +41,7 @@ struct amdgpu_reg_ind { struct amdgpu_reg_access { struct amdgpu_reg_ind smc; struct amdgpu_reg_ind uvd_ctx; + struct amdgpu_reg_ind didt; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); @@ -48,6 +49,8 @@ uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 342a496b60204..90c9a2e1cf5b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -223,10 +223,10 @@ static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); r = RREG32(mmDIDT_IND_DATA); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -234,10 +234,10 @@ static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); WREG32(mmDIDT_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static const u32 bonaire_golden_spm_registers[] = @@ -1990,8 +1990,8 @@ static int cik_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg = &cik_pcie_wreg; adev->reg.uvd_ctx.rreg = &cik_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &cik_uvd_ctx_wreg; - adev->didt_rreg = &cik_didt_rreg; - adev->didt_wreg = &cik_didt_wreg; + adev->reg.didt.rreg = &cik_didt_rreg; + adev->reg.didt.wreg = &cik_didt_wreg; adev->asic_funcs = &cik_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index d0bc2dcd30663..dd8a85679f8f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -283,10 +283,10 @@ static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); r = RREG32(data); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -297,10 +297,10 @@ static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 nv_get_config_memsize(struct amdgpu_device *adev) @@ -642,8 +642,8 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_rreg = amdgpu_device_pcie_port_rreg; adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - adev->didt_rreg = &nv_didt_rreg; - adev->didt_wreg = &nv_didt_wreg; + adev->reg.didt.rreg = &nv_didt_rreg; + adev->reg.didt.wreg = &nv_didt_wreg; adev->asic_funcs = &nv_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index bbf352ce8a64d..bf9ad3ce4c65a 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2045,8 +2045,6 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_wreg = &si_pciep_wreg; adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; - adev->didt_rreg = NULL; - adev->didt_wreg = NULL; adev->asic_funcs = &si_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 44bc1b71e3956..bf23b1d0fcc82 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -273,10 +273,10 @@ static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); r = RREG32(data); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -287,10 +287,10 @@ static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) @@ -971,8 +971,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; - adev->didt_rreg = &soc15_didt_rreg; - adev->didt_wreg = &soc15_didt_wreg; + adev->reg.didt.rreg = &soc15_didt_rreg; + adev->reg.didt.wreg = &soc15_didt_wreg; adev->gc_cac_rreg = &soc15_gc_cac_rreg; adev->gc_cac_wreg = &soc15_gc_cac_wreg; adev->se_cac_rreg = &soc15_se_cac_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 75ed71b1f2423..8c5157439e9bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -229,10 +229,10 @@ static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); r = RREG32(data); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -243,10 +243,10 @@ static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 soc21_get_config_memsize(struct amdgpu_device *adev) @@ -596,8 +596,8 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_rreg = amdgpu_device_pcie_port_rreg; adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - adev->didt_rreg = &soc21_didt_rreg; - adev->didt_wreg = &soc21_didt_wreg; + adev->reg.didt.rreg = &soc21_didt_rreg; + adev->reg.didt.wreg = &soc21_didt_wreg; adev->asic_funcs = &soc21_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index d4f3df165090c..11e0264617d8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -368,8 +368,6 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->pciep_rreg = amdgpu_device_pcie_port_rreg; adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - adev->didt_rreg = NULL; - adev->didt_wreg = NULL; adev->asic_funcs = &soc24_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 6439b09656bff..0be52dba6a26d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -260,8 +260,6 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) adev->pciep_wreg = amdgpu_device_pcie_port_wreg; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; - adev->didt_rreg = NULL; - adev->didt_wreg = NULL; adev->asic_funcs = &soc_v1_0_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 7d3b331d9217d..9a0856a601c06 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -394,10 +394,10 @@ static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); r = RREG32(mmDIDT_IND_DATA); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -405,10 +405,10 @@ static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); WREG32(mmDIDT_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) @@ -1464,8 +1464,8 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg = &vi_pcie_wreg; adev->reg.uvd_ctx.rreg = &vi_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; - adev->didt_rreg = &vi_didt_rreg; - adev->didt_wreg = &vi_didt_wreg; + adev->reg.didt.rreg = &vi_didt_rreg; + adev->reg.didt.wreg = &vi_didt_wreg; adev->gc_cac_rreg = &vi_gc_cac_rreg; adev->gc_cac_wreg = &vi_gc_cac_wreg; From 053e261f2a8b1b48cf4ad4112ce0d22bd27958b9 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 18:57:47 +0530 Subject: [PATCH 1724/2070] drm/amdgpu: Add gc cac method to register block Move gc cac access callbacks to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++----- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 --- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 24 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/soc15.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/vi.c | 12 +++++----- 6 files changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8bbb20a807b03..aeb74714c328b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -935,10 +935,6 @@ struct amdgpu_device { amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; amdgpu_wreg64_ext_t pcie_wreg64_ext; - /* protects concurrent gc_cac register access */ - spinlock_t gc_cac_idx_lock; - amdgpu_rreg_t gc_cac_rreg; - amdgpu_wreg_t gc_cac_wreg; /* protects concurrent se_cac register access */ spinlock_t se_cac_idx_lock; amdgpu_rreg_t se_cac_rreg; @@ -1365,8 +1361,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) -#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) -#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) +#define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) +#define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b0fa1dea4c392..210d8be119212 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3875,8 +3875,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; - adev->gc_cac_rreg = &amdgpu_invalid_rreg; - adev->gc_cac_wreg = &amdgpu_invalid_wreg; adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; @@ -3926,7 +3924,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->pcie_idx_lock); - spin_lock_init(&adev->gc_cac_idx_lock); spin_lock_init(&adev->se_cac_idx_lock); spin_lock_init(&adev->audio_endpt_idx_lock); spin_lock_init(&adev->mm_stats.lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index c31c86bbf18ab..69db9de507c55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -46,6 +46,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) spin_lock_init(&adev->reg.didt.lock); adev->reg.didt.rreg = NULL; adev->reg.didt.wreg = NULL; + + spin_lock_init(&adev->reg.gc_cac.lock); + adev->reg.gc_cac.rreg = NULL; + adev->reg.gc_cac.wreg = NULL; } uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) @@ -105,6 +109,26 @@ void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) adev->reg.didt.wreg(adev, reg, v); } +uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.gc_cac.rreg) { + dev_err_once(adev->dev, "GC_CAC register read not supported\n"); + return 0; + } + return adev->reg.gc_cac.rreg(adev, reg); +} + +void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v) +{ + if (!adev->reg.gc_cac.wreg) { + dev_err_once(adev->dev, + "GC_CAC register write not supported\n"); + return; + } + adev->reg.gc_cac.wreg(adev, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 239dbd6ef2f6a..3736fd5717713 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -42,6 +42,7 @@ struct amdgpu_reg_access { struct amdgpu_reg_ind smc; struct amdgpu_reg_ind uvd_ctx; struct amdgpu_reg_ind didt; + struct amdgpu_reg_ind gc_cac; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); @@ -51,6 +52,9 @@ uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index bf23b1d0fcc82..3099a5e73e934 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -298,10 +298,10 @@ static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); return r; } @@ -309,10 +309,10 @@ static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); } static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) @@ -973,8 +973,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; adev->reg.didt.rreg = &soc15_didt_rreg; adev->reg.didt.wreg = &soc15_didt_wreg; - adev->gc_cac_rreg = &soc15_gc_cac_rreg; - adev->gc_cac_wreg = &soc15_gc_cac_wreg; + adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; + adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; adev->se_cac_rreg = &soc15_se_cac_rreg; adev->se_cac_wreg = &soc15_se_cac_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 9a0856a601c06..b8b6e1ea0d523 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -416,10 +416,10 @@ static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32(mmGC_CAC_IND_INDEX, (reg)); r = RREG32(mmGC_CAC_IND_DATA); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); return r; } @@ -427,10 +427,10 @@ static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32(mmGC_CAC_IND_INDEX, (reg)); WREG32(mmGC_CAC_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); } @@ -1466,8 +1466,8 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; adev->reg.didt.rreg = &vi_didt_rreg; adev->reg.didt.wreg = &vi_didt_wreg; - adev->gc_cac_rreg = &vi_gc_cac_rreg; - adev->gc_cac_wreg = &vi_gc_cac_wreg; + adev->reg.gc_cac.rreg = &vi_gc_cac_rreg; + adev->reg.gc_cac.wreg = &vi_gc_cac_wreg; adev->asic_funcs = &vi_asic_funcs; From e37d2b608b815244dcc441bd15eebf304ae0315b Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 19:04:47 +0530 Subject: [PATCH 1725/2070] drm/amdgpu: Add se cac method to register block Move se cac access callbacks to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++----- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 24 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/soc15.c | 12 +++++----- 5 files changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index aeb74714c328b..52925c25e1f54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -935,10 +935,6 @@ struct amdgpu_device { amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; amdgpu_wreg64_ext_t pcie_wreg64_ext; - /* protects concurrent se_cac register access */ - spinlock_t se_cac_idx_lock; - amdgpu_rreg_t se_cac_rreg; - amdgpu_wreg_t se_cac_wreg; /* protects concurrent ENDPOINT (audio) register access */ spinlock_t audio_endpt_idx_lock; amdgpu_block_rreg_t audio_endpt_rreg; @@ -1363,8 +1359,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) -#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) -#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) +#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) +#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) #define WREG32_P(reg, val, mask) \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 210d8be119212..165d4ef3daa6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3924,7 +3924,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->pcie_idx_lock); - spin_lock_init(&adev->se_cac_idx_lock); spin_lock_init(&adev->audio_endpt_idx_lock); spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->virt.rlcg_reg_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 69db9de507c55..d75ef23581a05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -50,6 +50,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) spin_lock_init(&adev->reg.gc_cac.lock); adev->reg.gc_cac.rreg = NULL; adev->reg.gc_cac.wreg = NULL; + + spin_lock_init(&adev->reg.se_cac.lock); + adev->reg.se_cac.rreg = NULL; + adev->reg.se_cac.wreg = NULL; } uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) @@ -129,6 +133,26 @@ void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, adev->reg.gc_cac.wreg(adev, reg, v); } +uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.se_cac.rreg) { + dev_err_once(adev->dev, "SE_CAC register read not supported\n"); + return 0; + } + return adev->reg.se_cac.rreg(adev, reg); +} + +void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v) +{ + if (!adev->reg.se_cac.wreg) { + dev_err_once(adev->dev, + "SE_CAC register write not supported\n"); + return; + } + adev->reg.se_cac.wreg(adev, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 3736fd5717713..63929999cd76a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -43,6 +43,7 @@ struct amdgpu_reg_access { struct amdgpu_reg_ind uvd_ctx; struct amdgpu_reg_ind didt; struct amdgpu_reg_ind gc_cac; + struct amdgpu_reg_ind se_cac; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); @@ -55,6 +56,9 @@ void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 3099a5e73e934..7f2f047bee10f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -320,10 +320,10 @@ static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->se_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.se_cac.lock, flags); WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); - spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); return r; } @@ -331,10 +331,10 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->se_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.se_cac.lock, flags); WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); } static u32 soc15_get_config_memsize(struct amdgpu_device *adev) @@ -975,8 +975,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.didt.wreg = &soc15_didt_wreg; adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; - adev->se_cac_rreg = &soc15_se_cac_rreg; - adev->se_cac_wreg = &soc15_se_cac_wreg; + adev->reg.se_cac.rreg = &soc15_se_cac_rreg; + adev->reg.se_cac.wreg = &soc15_se_cac_wreg; adev->rev_id = amdgpu_device_get_rev_id(adev); adev->external_rev_id = 0xFF; From d714a336a32992c0fada6ddd2f7ad23065dfe0ce Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 8 Dec 2025 19:11:57 +0530 Subject: [PATCH 1726/2070] drm/amdgpu: Add audio method to register block Move audio endpoint callbacks to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 ------------------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 26 +++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 21 ++++++--- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 12 ++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 12 ++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 12 ++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- 8 files changed, 66 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 52925c25e1f54..0ab2072cc90e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -935,10 +935,6 @@ struct amdgpu_device { amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; amdgpu_wreg64_ext_t pcie_wreg64_ext; - /* protects concurrent ENDPOINT (audio) register access */ - spinlock_t audio_endpt_idx_lock; - amdgpu_block_rreg_t audio_endpt_rreg; - amdgpu_block_wreg_t audio_endpt_wreg; struct amdgpu_doorbell doorbell; /* clock/pll info */ @@ -1361,8 +1357,10 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) -#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) -#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) +#define RREG32_AUDIO_ENDPT(block, reg) \ + amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) +#define WREG32_AUDIO_ENDPT(block, reg, v) \ + amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 165d4ef3daa6d..0f3cf6c2d0b1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -966,48 +966,6 @@ static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, BUG(); } -/** - * amdgpu_block_invalid_rreg - dummy reg read function - * - * @adev: amdgpu_device pointer - * @block: offset of instance - * @reg: offset of register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - * Returns the value in the register. - */ -static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, - uint32_t block, uint32_t reg) -{ - dev_err(adev->dev, - "Invalid callback to read register 0x%04X in block 0x%04X\n", - reg, block); - BUG(); - return 0; -} - -/** - * amdgpu_block_invalid_wreg - dummy reg write function - * - * @adev: amdgpu_device pointer - * @block: offset of instance - * @reg: offset of register - * @v: value to write to the register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - */ -static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, - uint32_t block, - uint32_t reg, uint32_t v) -{ - dev_err(adev->dev, - "Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", - reg, block, v); - BUG(); -} - static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev) { if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) @@ -3875,8 +3833,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; - adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; - adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; dev_info( adev->dev, @@ -3924,7 +3880,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mmio_idx_lock); spin_lock_init(&adev->pcie_idx_lock); - spin_lock_init(&adev->audio_endpt_idx_lock); spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->virt.rlcg_reg_lock); spin_lock_init(&adev->wb.lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index d75ef23581a05..563b155b15c6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -54,6 +54,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) spin_lock_init(&adev->reg.se_cac.lock); adev->reg.se_cac.rreg = NULL; adev->reg.se_cac.wreg = NULL; + + spin_lock_init(&adev->reg.audio_endpt.lock); + adev->reg.audio_endpt.rreg = NULL; + adev->reg.audio_endpt.wreg = NULL; } uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) @@ -153,6 +157,28 @@ void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, adev->reg.se_cac.wreg(adev, reg, v); } +uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg) +{ + if (!adev->reg.audio_endpt.rreg) { + dev_err_once(adev->dev, + "AUDIO_ENDPT register read not supported\n"); + return 0; + } + return adev->reg.audio_endpt.rreg(adev, block, reg); +} + +void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg, uint32_t v) +{ + if (!adev->reg.audio_endpt.wreg) { + dev_err_once(adev->dev, + "AUDIO_ENDPT register write not supported\n"); + return; + } + adev->reg.audio_endpt.wreg(adev, block, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 63929999cd76a..e19b7a5319063 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -32,18 +32,30 @@ struct amdgpu_device; typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); +typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, + uint32_t); +typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, + uint32_t); + struct amdgpu_reg_ind { spinlock_t lock; amdgpu_rreg_t rreg; amdgpu_wreg_t wreg; }; +struct amdgpu_reg_ind_blk { + spinlock_t lock; + amdgpu_block_rreg_t rreg; + amdgpu_block_wreg_t wreg; +}; + struct amdgpu_reg_access { struct amdgpu_reg_ind smc; struct amdgpu_reg_ind uvd_ctx; struct amdgpu_reg_ind didt; struct amdgpu_reg_ind gc_cac; struct amdgpu_reg_ind se_cac; + struct amdgpu_reg_ind_blk audio_endpt; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); @@ -59,6 +71,10 @@ void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg); +void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg, uint32_t v); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); @@ -69,11 +85,6 @@ typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); -typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, - uint32_t); -typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, - uint32_t); - uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t acc_flags); uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index b46e82877aa05..63e2cdfd74455 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -175,10 +175,10 @@ static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, unsigned long flags; u32 r; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); return r; } @@ -188,10 +188,10 @@ static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, { unsigned long flags; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); } static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) @@ -2764,8 +2764,8 @@ static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; + adev->reg.audio_endpt.rreg = &dce_v10_0_audio_endpt_rreg; + adev->reg.audio_endpt.wreg = &dce_v10_0_audio_endpt_wreg; dce_v10_0_set_display_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 831e6cb450663..6fd625c3904bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -138,10 +138,10 @@ static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, unsigned long flags; u32 r; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); return r; } @@ -151,11 +151,11 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, { unsigned long flags; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); } static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) @@ -2711,8 +2711,8 @@ static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; + adev->reg.audio_endpt.rreg = &dce_v6_0_audio_endpt_rreg; + adev->reg.audio_endpt.wreg = &dce_v6_0_audio_endpt_wreg; dce_v6_0_set_display_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 8d68edc0b3934..8d77476abf380 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -126,10 +126,10 @@ static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, unsigned long flags; u32 r; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); return r; } @@ -139,10 +139,10 @@ static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, { unsigned long flags; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); } static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) @@ -2669,8 +2669,8 @@ static int dce_v8_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; + adev->reg.audio_endpt.rreg = &dce_v8_0_audio_endpt_rreg; + adev->reg.audio_endpt.wreg = &dce_v8_0_audio_endpt_wreg; dce_v8_0_set_display_funcs(adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d501e7d13f0f7..bd43f391272d8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6048,8 +6048,8 @@ static int dm_early_init(struct amdgpu_ip_block *ip_block) adev->mode_info.funcs = &dm_display_funcs; /* - * Note: Do NOT change adev->audio_endpt_rreg and - * adev->audio_endpt_wreg because they are initialised in + * Note: Do NOT change adev->reg.audio_endpt.rreg and + * adev->reg.audio_endpt.wreg because they are initialised in * amdgpu_device_init() */ #if defined(CONFIG_DEBUG_KERNEL_DC) From 32f63c6f7175ff086f2880c7c24e36ae071a3e85 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 09:35:18 +0530 Subject: [PATCH 1727/2070] drm/amdgpu: Add pciep method to register block Move pcie port method to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 21 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 9 ++++++++ drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 4 ++-- 9 files changed, 42 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0ab2072cc90e5..76367459a5707 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -927,8 +927,6 @@ struct amdgpu_device { spinlock_t pcie_idx_lock; amdgpu_rreg_t pcie_rreg; amdgpu_wreg_t pcie_wreg; - amdgpu_rreg_t pciep_rreg; - amdgpu_wreg_t pciep_wreg; amdgpu_rreg_ext_t pcie_rreg_ext; amdgpu_wreg_ext_t pcie_wreg_ext; amdgpu_rreg64_t pcie_rreg64; @@ -1339,8 +1337,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) -#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) -#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) +#define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) +#define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0f3cf6c2d0b1a..302a0d42d2542 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3827,8 +3827,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->pcie_wreg = &amdgpu_invalid_wreg; adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext; - adev->pciep_rreg = &amdgpu_invalid_rreg; - adev->pciep_wreg = &amdgpu_invalid_wreg; adev->pcie_rreg64 = &amdgpu_invalid_rreg64; adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 563b155b15c6e..175fdfc5229b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -58,6 +58,9 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) spin_lock_init(&adev->reg.audio_endpt.lock); adev->reg.audio_endpt.rreg = NULL; adev->reg.audio_endpt.wreg = NULL; + + adev->reg.pcie.port_rreg = NULL; + adev->reg.pcie.port_wreg = NULL; } uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) @@ -179,6 +182,24 @@ void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, adev->reg.audio_endpt.wreg(adev, block, reg, v); } +uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.pcie.port_rreg) { + dev_err_once(adev->dev, "PCIEP register read not supported\n"); + return 0; + } + return adev->reg.pcie.port_rreg(adev, reg); +} + +void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.pcie.port_wreg) { + dev_err_once(adev->dev, "PCIEP register write not supported\n"); + return; + } + adev->reg.pcie.port_wreg(adev, reg, v); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index e19b7a5319063..eb449dbb8fd45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -49,6 +49,11 @@ struct amdgpu_reg_ind_blk { amdgpu_block_wreg_t wreg; }; +struct amdgpu_reg_pcie_ind { + amdgpu_rreg_t port_rreg; + amdgpu_wreg_t port_wreg; +}; + struct amdgpu_reg_access { struct amdgpu_reg_ind smc; struct amdgpu_reg_ind uvd_ctx; @@ -56,6 +61,7 @@ struct amdgpu_reg_access { struct amdgpu_reg_ind gc_cac; struct amdgpu_reg_ind se_cac; struct amdgpu_reg_ind_blk audio_endpt; + struct amdgpu_reg_pcie_ind pcie; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); @@ -75,6 +81,9 @@ uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, uint32_t reg); void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index dd8a85679f8f8..b3abf6554386f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -639,8 +639,8 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; adev->reg.didt.rreg = &nv_didt_rreg; adev->reg.didt.wreg = &nv_didt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index bf9ad3ce4c65a..a517c6cd07118 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2041,8 +2041,8 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.smc.wreg = si_smc_wreg; adev->pcie_rreg = &si_pcie_rreg; adev->pcie_wreg = &si_pcie_wreg; - adev->pciep_rreg = &si_pciep_rreg; - adev->pciep_wreg = &si_pciep_wreg; + adev->reg.pcie.port_rreg = &si_pciep_rreg; + adev->reg.pcie.port_wreg = &si_pciep_wreg; adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 8c5157439e9bb..23c26a25ac462 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -593,8 +593,8 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; adev->reg.didt.rreg = &soc21_didt_rreg; adev->reg.didt.wreg = &soc21_didt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 11e0264617d8f..7c59d9b0a5413 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -366,8 +366,8 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; adev->asic_funcs = &soc24_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 0be52dba6a26d..8c808a6d08a54 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -256,8 +256,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; From 5db1f0214e947e3d6793636381618ed1cb23479a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 09:47:13 +0530 Subject: [PATCH 1728/2070] drm/amdgpu: Add pcie indirect to register block Move pcie indirect access to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37 ------------------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 30 ++++++++++++--- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 4 ++ drivers/gpu/drm/amd/amdgpu/cik.c | 4 +- drivers/gpu/drm/amd/amdgpu/nv.c | 4 +- drivers/gpu/drm/amd/amdgpu/si.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/vi.c | 4 +- 12 files changed, 47 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 76367459a5707..4ee33252c21a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -925,8 +925,6 @@ struct amdgpu_device { struct amdgpu_reg_access reg; /* protects concurrent PCIE register access */ spinlock_t pcie_idx_lock; - amdgpu_rreg_t pcie_rreg; - amdgpu_wreg_t pcie_wreg; amdgpu_rreg_ext_t pcie_rreg_ext; amdgpu_wreg_ext_t pcie_wreg_ext; amdgpu_rreg64_t pcie_rreg64; @@ -1335,8 +1333,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) -#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) -#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) +#define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) +#define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 302a0d42d2542..8dd6880f20679 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -865,23 +865,6 @@ u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) return adev->nbio.funcs->get_rev_id(adev); } -/** - * amdgpu_invalid_rreg - dummy reg read function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - * Returns the value in the register. - */ -static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) -{ - dev_err(adev->dev, "Invalid callback to read register 0x%04X\n", reg); - BUG(); - return 0; -} - static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg) { dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); @@ -889,24 +872,6 @@ static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg return 0; } -/** - * amdgpu_invalid_wreg - dummy reg write function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * @v: value to write to the register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - */ -static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) -{ - dev_err(adev->dev, - "Invalid callback to write register 0x%04X with 0x%08X\n", reg, - v); - BUG(); -} - static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v) { dev_err(adev->dev, @@ -3823,8 +3788,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_reg_access_init(adev); - adev->pcie_rreg = &amdgpu_invalid_rreg; - adev->pcie_wreg = &amdgpu_invalid_wreg; adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext; adev->pcie_rreg64 = &amdgpu_invalid_rreg64; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 175fdfc5229b8..11ba235ee1438 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -59,6 +59,8 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) adev->reg.audio_endpt.rreg = NULL; adev->reg.audio_endpt.wreg = NULL; + adev->reg.pcie.rreg = NULL; + adev->reg.pcie.wreg = NULL; adev->reg.pcie.port_rreg = NULL; adev->reg.pcie.port_wreg = NULL; } @@ -182,6 +184,24 @@ void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, adev->reg.audio_endpt.wreg(adev, block, reg, v); } +uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.pcie.rreg) { + dev_err_once(adev->dev, "PCIE register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg(adev, reg); +} + +void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.pcie.wreg) { + dev_err_once(adev->dev, "PCIE register write not supported\n"); + return; + } + adev->reg.pcie.wreg(adev, reg, v); +} + uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg) { if (!adev->reg.pcie.port_rreg) { @@ -231,7 +251,7 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); } } else { - ret = adev->pcie_rreg(adev, reg * 4); + ret = amdgpu_reg_pcie_rd32(adev, reg * 4); } trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); @@ -296,7 +316,7 @@ uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); } } else { - ret = adev->pcie_rreg(adev, reg * 4); + ret = amdgpu_reg_pcie_rd32(adev, reg * 4); } return ret; @@ -354,7 +374,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); } } else { - adev->pcie_wreg(adev, reg * 4, v); + amdgpu_reg_pcie_wr32(adev, reg * 4, v); } trace_amdgpu_device_wreg(adev->pdev->device, reg, v); @@ -381,7 +401,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); } else if ((reg * 4) >= adev->rmmio_size) { - adev->pcie_wreg(adev, reg * 4, v); + amdgpu_reg_pcie_wr32(adev, reg * 4, v); } else { writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); } @@ -422,7 +442,7 @@ void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); } } else { - adev->pcie_wreg(adev, reg * 4, v); + amdgpu_reg_pcie_wr32(adev, reg * 4, v); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index eb449dbb8fd45..8a83eb36945ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -50,6 +50,8 @@ struct amdgpu_reg_ind_blk { }; struct amdgpu_reg_pcie_ind { + amdgpu_rreg_t rreg; + amdgpu_wreg_t wreg; amdgpu_rreg_t port_rreg; amdgpu_wreg_t port_wreg; }; @@ -81,6 +83,8 @@ uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, uint32_t reg); void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 90c9a2e1cf5b4..a4461574f881e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1986,8 +1986,8 @@ static int cik_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.smc.rreg = cik_smc_rreg; adev->reg.smc.wreg = cik_smc_wreg; - adev->pcie_rreg = &cik_pcie_rreg; - adev->pcie_wreg = &cik_pcie_wreg; + adev->reg.pcie.rreg = &cik_pcie_rreg; + adev->reg.pcie.wreg = &cik_pcie_wreg; adev->reg.uvd_ctx.rreg = &cik_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &cik_uvd_ctx_wreg; adev->reg.didt.rreg = &cik_didt_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index b3abf6554386f..302c56630bd8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -635,8 +635,8 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index a517c6cd07118..4aadb7a19a2a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2039,8 +2039,8 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.smc.rreg = si_smc_rreg; adev->reg.smc.wreg = si_smc_wreg; - adev->pcie_rreg = &si_pcie_rreg; - adev->pcie_wreg = &si_pcie_wreg; + adev->reg.pcie.rreg = &si_pcie_rreg; + adev->reg.pcie.wreg = &si_pcie_wreg; adev->reg.pcie.port_rreg = &si_pciep_rreg; adev->reg.pcie.port_wreg = &si_pciep_wreg; adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 7f2f047bee10f..440ebd845cf33 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -961,8 +961,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 23c26a25ac462..f4e6c4d3263a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -589,8 +589,8 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 7c59d9b0a5413..2b2b8737ec5e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -362,8 +362,8 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 8c808a6d08a54..d0bc844a5ba62 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -250,8 +250,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index b8b6e1ea0d523..7d1f9a25b109c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1460,8 +1460,8 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.smc.rreg = vi_smc_rreg; adev->reg.smc.wreg = vi_smc_wreg; } - adev->pcie_rreg = &vi_pcie_rreg; - adev->pcie_wreg = &vi_pcie_wreg; + adev->reg.pcie.rreg = &vi_pcie_rreg; + adev->reg.pcie.wreg = &vi_pcie_wreg; adev->reg.uvd_ctx.rreg = &vi_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; adev->reg.didt.rreg = &vi_didt_rreg; From fb6be4e1daeabe42d54a5727916f867913d7b791 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 10:09:37 +0530 Subject: [PATCH 1729/2070] drm/amdgpu: Add pcie ext access to register block Move pcie extended access (64-bit address) to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 --------------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 21 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 10 ++++++--- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 4 ++-- 6 files changed, 34 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4ee33252c21a6..a822d0459c14e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -925,8 +925,6 @@ struct amdgpu_device { struct amdgpu_reg_access reg; /* protects concurrent PCIE register access */ spinlock_t pcie_idx_lock; - amdgpu_rreg_ext_t pcie_rreg_ext; - amdgpu_wreg_ext_t pcie_wreg_ext; amdgpu_rreg64_t pcie_rreg64; amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; @@ -1337,8 +1335,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) -#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) -#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) +#define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) +#define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8dd6880f20679..0dee58dd0da87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -865,21 +865,6 @@ u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) return adev->nbio.funcs->get_rev_id(adev); } -static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg) -{ - dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); - BUG(); - return 0; -} - -static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v) -{ - dev_err(adev->dev, - "Invalid callback to write register 0x%llX with 0x%08X\n", reg, - v); - BUG(); -} - /** * amdgpu_invalid_rreg64 - dummy 64 bit reg read function * @@ -3788,8 +3773,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_reg_access_init(adev); - adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; - adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext; adev->pcie_rreg64 = &amdgpu_invalid_rreg64; adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 11ba235ee1438..395f02834404b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -61,6 +61,8 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) adev->reg.pcie.rreg = NULL; adev->reg.pcie.wreg = NULL; + adev->reg.pcie.rreg_ext = NULL; + adev->reg.pcie.wreg_ext = NULL; adev->reg.pcie.port_rreg = NULL; adev->reg.pcie.port_wreg = NULL; } @@ -202,6 +204,25 @@ void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) adev->reg.pcie.wreg(adev, reg, v); } +uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg) +{ + if (!adev->reg.pcie.rreg_ext) { + dev_err_once(adev->dev, "PCIE EXT register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg_ext(adev, reg); +} + +void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, + uint32_t v) +{ + if (!adev->reg.pcie.wreg_ext) { + dev_err_once(adev->dev, "PCIE EXT register write not supported\n"); + return; + } + adev->reg.pcie.wreg_ext(adev, reg, v); +} + uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg) { if (!adev->reg.pcie.port_rreg) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 8a83eb36945ba..4423b872b46e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -31,6 +31,8 @@ struct amdgpu_device; typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); +typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); +typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, uint32_t); @@ -52,6 +54,8 @@ struct amdgpu_reg_ind_blk { struct amdgpu_reg_pcie_ind { amdgpu_rreg_t rreg; amdgpu_wreg_t wreg; + amdgpu_rreg_ext_t rreg_ext; + amdgpu_wreg_ext_t wreg_ext; amdgpu_rreg_t port_rreg; amdgpu_wreg_t port_wreg; }; @@ -85,13 +89,13 @@ void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, uint32_t reg, uint32_t v); uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg); +void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, + uint32_t v); uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); -typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); -typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); - typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 440ebd845cf33..bf520fa6f19ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -963,8 +963,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->nbio.funcs->set_reg_remap(adev); adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; - adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; + adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; + adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index d0bc844a5ba62..c55a402f3dba8 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -252,8 +252,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; - adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; + adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; + adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; From 634746234403827c4c94a50ce55f0d3f0b9821c9 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 11:11:41 +0530 Subject: [PATCH 1730/2070] drm/amdgpu: Add pcie64 indirect to register block Move 64-bit pcie indirect read/writes to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 38 ------------------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 20 ++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 9 +++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 +- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 4 +- 9 files changed, 38 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a822d0459c14e..7710442309922 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -925,8 +925,6 @@ struct amdgpu_device { struct amdgpu_reg_access reg; /* protects concurrent PCIE register access */ spinlock_t pcie_idx_lock; - amdgpu_rreg64_t pcie_rreg64; - amdgpu_wreg64_t pcie_wreg64; amdgpu_rreg64_ext_t pcie_rreg64_ext; amdgpu_wreg64_ext_t pcie_wreg64_ext; struct amdgpu_doorbell doorbell; @@ -1337,8 +1335,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) -#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) -#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) +#define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) +#define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0dee58dd0da87..8c206d53704c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -865,24 +865,6 @@ u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) return adev->nbio.funcs->get_rev_id(adev); } -/** - * amdgpu_invalid_rreg64 - dummy 64 bit reg read function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - * Returns the value in the register. - */ -static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) -{ - dev_err(adev->dev, "Invalid callback to read 64 bit register 0x%04X\n", - reg); - BUG(); - return 0; -} - static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg) { dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); @@ -890,24 +872,6 @@ static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t r return 0; } -/** - * amdgpu_invalid_wreg64 - dummy reg write function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * @v: value to write to the register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - */ -static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) -{ - dev_err(adev->dev, - "Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", - reg, v); - BUG(); -} - static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v) { dev_err(adev->dev, @@ -3773,8 +3737,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_reg_access_init(adev); - adev->pcie_rreg64 = &amdgpu_invalid_rreg64; - adev->pcie_wreg64 = &amdgpu_invalid_wreg64; adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 395f02834404b..fc7c2dc458c30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -63,6 +63,8 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) adev->reg.pcie.wreg = NULL; adev->reg.pcie.rreg_ext = NULL; adev->reg.pcie.wreg_ext = NULL; + adev->reg.pcie.rreg64 = NULL; + adev->reg.pcie.wreg64 = NULL; adev->reg.pcie.port_rreg = NULL; adev->reg.pcie.port_wreg = NULL; } @@ -223,6 +225,24 @@ void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, adev->reg.pcie.wreg_ext(adev, reg, v); } +uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.pcie.rreg64) { + dev_err_once(adev->dev, "PCIE 64-bit register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg64(adev, reg); +} + +void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) +{ + if (!adev->reg.pcie.wreg64) { + dev_err_once(adev->dev, "PCIE 64-bit register write not supported\n"); + return; + } + adev->reg.pcie.wreg64(adev, reg, v); +} + uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg) { if (!adev->reg.pcie.port_rreg) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 4423b872b46e9..e6c0a59973c43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -33,6 +33,8 @@ typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); +typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); +typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, uint32_t); @@ -56,6 +58,8 @@ struct amdgpu_reg_pcie_ind { amdgpu_wreg_t wreg; amdgpu_rreg_ext_t rreg_ext; amdgpu_wreg_ext_t wreg_ext; + amdgpu_rreg64_t rreg64; + amdgpu_wreg64_t wreg64; amdgpu_rreg_t port_rreg; amdgpu_wreg_t port_wreg; }; @@ -92,13 +96,12 @@ void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg); void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, uint32_t v); +uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v); uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); -typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); -typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); - typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 302c56630bd8b..7ce1a1b956065 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -637,8 +637,8 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) adev->nbio.funcs->set_reg_remap(adev); adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index bf520fa6f19ff..7e682d19ca528 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -965,8 +965,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index f4e6c4d3263a6..fbd1d97f33add 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -591,8 +591,8 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) adev->nbio.funcs->set_reg_remap(adev); adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 2b2b8737ec5e7..308f32daa7802 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -364,8 +364,8 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) adev->nbio.funcs->set_reg_remap(adev); adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index c55a402f3dba8..ca6d6755dde18 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -254,8 +254,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; From 1f39872c1d7c97ce3593cda0432dc0e10bcb61e6 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 11:28:45 +0530 Subject: [PATCH 1731/2070] drm/amdgpu: Add pcie64 extended to register block Add extended pcie 64-bit access method to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 ---------------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 21 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 10 ++++++--- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 4 ++-- 6 files changed, 34 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7710442309922..c530d462aae29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -925,8 +925,6 @@ struct amdgpu_device { struct amdgpu_reg_access reg; /* protects concurrent PCIE register access */ spinlock_t pcie_idx_lock; - amdgpu_rreg64_ext_t pcie_rreg64_ext; - amdgpu_wreg64_ext_t pcie_wreg64_ext; struct amdgpu_doorbell doorbell; /* clock/pll info */ @@ -1337,8 +1335,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) -#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) -#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) +#define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) +#define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8c206d53704c3..b220349f22a25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -865,21 +865,6 @@ u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) return adev->nbio.funcs->get_rev_id(adev); } -static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg) -{ - dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); - BUG(); - return 0; -} - -static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v) -{ - dev_err(adev->dev, - "Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n", - reg, v); - BUG(); -} - static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev) { if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) @@ -3737,9 +3722,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_reg_access_init(adev); - adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; - adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; - dev_info( adev->dev, "initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index fc7c2dc458c30..0e2722e3722ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -65,6 +65,8 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) adev->reg.pcie.wreg_ext = NULL; adev->reg.pcie.rreg64 = NULL; adev->reg.pcie.wreg64 = NULL; + adev->reg.pcie.rreg64_ext = NULL; + adev->reg.pcie.wreg64_ext = NULL; adev->reg.pcie.port_rreg = NULL; adev->reg.pcie.port_wreg = NULL; } @@ -243,6 +245,25 @@ void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) adev->reg.pcie.wreg64(adev, reg, v); } +uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg) +{ + if (!adev->reg.pcie.rreg64_ext) { + dev_err_once(adev->dev, "PCIE EXT 64-bit register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg64_ext(adev, reg); +} + +void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, + uint64_t v) +{ + if (!adev->reg.pcie.wreg64_ext) { + dev_err_once(adev->dev, "PCIE EXT 64-bit register write not supported\n"); + return; + } + adev->reg.pcie.wreg64_ext(adev, reg, v); +} + uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg) { if (!adev->reg.pcie.port_rreg) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index e6c0a59973c43..791b3e50ac9c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -35,6 +35,8 @@ typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); +typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); +typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, uint32_t); @@ -60,6 +62,8 @@ struct amdgpu_reg_pcie_ind { amdgpu_wreg_ext_t wreg_ext; amdgpu_rreg64_t rreg64; amdgpu_wreg64_t wreg64; + amdgpu_rreg64_ext_t rreg64_ext; + amdgpu_wreg64_ext_t wreg64_ext; amdgpu_rreg_t port_rreg; amdgpu_wreg_t port_wreg; }; @@ -98,13 +102,13 @@ void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, uint32_t v); uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v); +uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg); +void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, + uint64_t v); uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); -typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); -typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); - uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t acc_flags); uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 7e682d19ca528..c95e5883e0573 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -967,8 +967,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; - adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; - adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; + adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; + adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; adev->reg.didt.rreg = &soc15_didt_rreg; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index ca6d6755dde18..26e7566a5479c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -258,8 +258,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; - adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; - adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; + adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; + adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; adev->asic_funcs = &soc_v1_0_asic_funcs; From f9d85562bb40049b5c10bab8908991a2bae48b78 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 11:32:42 +0530 Subject: [PATCH 1732/2070] drm/amdgpu: Move pcie lock to register block Move pcie register access lock to register access block. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 41 ++++++++++--------- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 1 + drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 20 ++++----- drivers/gpu/drm/amd/amdgpu/si.c | 32 +++++++-------- drivers/gpu/drm/amd/amdgpu/vi.c | 8 ++-- 8 files changed, 56 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c530d462aae29..aa9969b21d314 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -923,8 +923,6 @@ struct amdgpu_device { struct amdgpu_mmio_remap rmmio_remap; /* Indirect register access blocks */ struct amdgpu_reg_access reg; - /* protects concurrent PCIE register access */ - spinlock_t pcie_idx_lock; struct amdgpu_doorbell doorbell; /* clock/pll info */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b220349f22a25..2870ef4cbf45f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3767,7 +3767,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, return r; spin_lock_init(&adev->mmio_idx_lock); - spin_lock_init(&adev->pcie_idx_lock); spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->virt.rlcg_reg_lock); spin_lock_init(&adev->wb.lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 0e2722e3722ea..a996ab1254a17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -59,6 +59,7 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev) adev->reg.audio_endpt.rreg = NULL; adev->reg.audio_endpt.wreg = NULL; + spin_lock_init(&adev->reg.pcie.lock); adev->reg.pcie.rreg = NULL; adev->reg.pcie.wreg = NULL; adev->reg.pcie.rreg_ext = NULL; @@ -526,14 +527,14 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr) pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; writel(reg_addr, pcie_index_offset); readl(pcie_index_offset); r = readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -565,7 +566,7 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr) pcie_index_hi = 0; } - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; if (pcie_index_hi != 0) @@ -586,7 +587,7 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr) readl(pcie_index_hi_offset); } - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -609,7 +610,7 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr) pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; @@ -621,7 +622,7 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr) writel(reg_addr + 4, pcie_index_offset); readl(pcie_index_offset); r |= ((u64)readl(pcie_data_offset) << 32); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -641,7 +642,7 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr) pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; if (pcie_index_hi != 0) @@ -671,7 +672,7 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr) readl(pcie_index_hi_offset); } - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -694,7 +695,7 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; @@ -702,7 +703,7 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, readl(pcie_index_offset); writel(reg_data, pcie_data_offset); readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, @@ -721,7 +722,7 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, else pcie_index_hi = 0; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; if (pcie_index_hi != 0) @@ -743,7 +744,7 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, readl(pcie_index_hi_offset); } - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /** @@ -764,7 +765,7 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; @@ -778,7 +779,7 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, readl(pcie_index_offset); writel((u32)(reg_data >> 32), pcie_data_offset); readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, @@ -796,7 +797,7 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; if (pcie_index_hi != 0) @@ -828,7 +829,7 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, readl(pcie_index_hi_offset); } - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) @@ -839,11 +840,11 @@ u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) address = adev->nbio.funcs->get_pcie_port_index_offset(adev); data = adev->nbio.funcs->get_pcie_port_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, reg * 4); (void)RREG32(address); r = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -854,12 +855,12 @@ void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = adev->nbio.funcs->get_pcie_port_index_offset(adev); data = adev->nbio.funcs->get_pcie_port_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, reg * 4); (void)RREG32(address); WREG32(data, v); (void)RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index 791b3e50ac9c3..dc0e81cef3b99 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -56,6 +56,7 @@ struct amdgpu_reg_ind_blk { }; struct amdgpu_reg_pcie_ind { + spinlock_t lock; amdgpu_rreg_t rreg; amdgpu_wreg_t wreg; amdgpu_rreg_ext_t rreg_ext; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index a4461574f881e..29954c7d61b06 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -154,11 +154,11 @@ static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(mmPCIE_INDEX, reg); (void)RREG32(mmPCIE_INDEX); r = RREG32(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -166,12 +166,12 @@ static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(mmPCIE_INDEX, reg); (void)RREG32(mmPCIE_INDEX); WREG32(mmPCIE_DATA, v); (void)RREG32(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c index 621aeca538803..7e7e6c389895a 100644 --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c @@ -51,7 +51,7 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); WREG32(data, ficaa_val); @@ -61,7 +61,7 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); ficadh_val = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val); } @@ -74,7 +74,7 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); WREG32(data, ficaa_val); @@ -84,7 +84,7 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); WREG32(data, ficadh_val); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /* @@ -102,12 +102,12 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, lo_addr); *lo_val = RREG32(data); WREG32(address, hi_addr); *hi_val = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /* @@ -124,12 +124,12 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, lo_addr); WREG32(data, lo_val); WREG32(address, hi_addr); WREG32(data, hi_val); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /* same as perfmon_wreg but return status on write value check */ @@ -143,7 +143,7 @@ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, lo_addr); WREG32(data, lo_val); WREG32(address, hi_addr); @@ -153,7 +153,7 @@ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, lo_val_rb = RREG32(data); WREG32(address, hi_addr); hi_val_rb = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); if (!(lo_val == lo_val_rb && hi_val == hi_val_rb)) return -EBUSY; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 4aadb7a19a2a3..c26cb3e8bff6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1027,11 +1027,11 @@ static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(AMDGPU_PCIE_INDEX, reg); (void)RREG32(AMDGPU_PCIE_INDEX); r = RREG32(AMDGPU_PCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -1039,12 +1039,12 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(AMDGPU_PCIE_INDEX, reg); (void)RREG32(AMDGPU_PCIE_INDEX); WREG32(AMDGPU_PCIE_DATA, v); (void)RREG32(AMDGPU_PCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) @@ -1052,11 +1052,11 @@ static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); (void)RREG32(PCIE_PORT_INDEX); r = RREG32(PCIE_PORT_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -1064,12 +1064,12 @@ static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); (void)RREG32(PCIE_PORT_INDEX); WREG32(PCIE_PORT_DATA, (v)); (void)RREG32(PCIE_PORT_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) @@ -2380,10 +2380,10 @@ static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); r = RREG32(EVERGREEN_PIF_PHY0_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -2391,10 +2391,10 @@ static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) @@ -2402,10 +2402,10 @@ static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); r = RREG32(EVERGREEN_PIF_PHY1_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -2413,10 +2413,10 @@ static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static void si_program_aspm(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 7d1f9a25b109c..a256320b92f33 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -299,11 +299,11 @@ static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32_NO_KIQ(mmPCIE_INDEX, reg); (void)RREG32_NO_KIQ(mmPCIE_INDEX); r = RREG32_NO_KIQ(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -311,12 +311,12 @@ static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32_NO_KIQ(mmPCIE_INDEX, reg); (void)RREG32_NO_KIQ(mmPCIE_INDEX); WREG32_NO_KIQ(mmPCIE_DATA, v); (void)RREG32_NO_KIQ(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) From 37c4c01e9e6e958c3766410a33b4c4e2ce94e804 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 18:01:25 +0530 Subject: [PATCH 1733/2070] drm/amdgpu: Add smn callbacks to register block Add smn block to register access and callback interface definition to get smn base. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 11 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 13 +++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index a996ab1254a17..4f58e9e816703 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -283,6 +283,17 @@ void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) adev->reg.pcie.port_wreg(adev, reg, v); } +uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst) +{ + if (!adev->reg.smn.get_smn_base) { + dev_err_once(adev->dev, "SMN base address callback not set\n"); + return 0; + } + return adev->reg.smn.get_smn_base(adev, block, die_inst); +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index dc0e81cef3b99..b3b941cc7b7c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -27,6 +27,8 @@ #include #include +#include "amdgpu_ip.h" + struct amdgpu_device; typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); @@ -42,6 +44,9 @@ typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, uint32_t); +typedef uint64_t (*amdgpu_reg_get_smn_base64_t)(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst); struct amdgpu_reg_ind { spinlock_t lock; @@ -69,6 +74,10 @@ struct amdgpu_reg_pcie_ind { amdgpu_wreg_t port_wreg; }; +struct amdgpu_reg_smn_ext { + amdgpu_reg_get_smn_base64_t get_smn_base; +}; + struct amdgpu_reg_access { struct amdgpu_reg_ind smc; struct amdgpu_reg_ind uvd_ctx; @@ -77,6 +86,7 @@ struct amdgpu_reg_access { struct amdgpu_reg_ind se_cac; struct amdgpu_reg_ind_blk audio_endpt; struct amdgpu_reg_pcie_ind pcie; + struct amdgpu_reg_smn_ext smn; }; void amdgpu_reg_access_init(struct amdgpu_device *adev); @@ -109,6 +119,9 @@ void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst); uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t acc_flags); From 645a292438829292c938e581b08b11248b5d316f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Dec 2025 19:43:21 +0530 Subject: [PATCH 1734/2070] drm/amdgpu: Use get_smn_base in aqua_vanjaram Use get_smn_base interface to get IP die instance's base offset in aqua_vanjaram. encode_ext_smn_addressing is not used. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ++- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 56 ++++++++++++++++++- .../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 21 +------ drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.h | 1 - drivers/gpu/drm/amd/amdgpu/soc15_common.h | 31 +++++----- 9 files changed, 90 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 475ca05c87196..5dcba6ec295d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -21,6 +21,7 @@ * * */ +#include "amdgpu_reg_access.h" #include #include #include @@ -5546,11 +5547,11 @@ static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev, * is changed. In such case, replace the aqua_vanjaram implementation * with more common helper */ reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + - aqua_vanjaram_encode_ext_smn_addressing(instance); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance); fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr); reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) + - aqua_vanjaram_encode_ext_smn_addressing(instance); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance); boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr); socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error); @@ -5616,7 +5617,7 @@ static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev, int retry_loop; reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + - aqua_vanjaram_encode_ext_smn_addressing(instance); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance); for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) { reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 4f58e9e816703..bf8645390bdc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -283,17 +283,71 @@ void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) adev->reg.pcie.port_wreg(adev, reg, v); } +static int amdgpu_reg_get_smn_base_version(struct amdgpu_device *adev) +{ + struct pci_dev *pdev = adev->pdev; + int id; + + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + + id = (pdev->device >> 4) & 0xFFFF; + if (id == 0x74A || id == 0x74B || id == 0x75A || id == 0x75B) + return 1; + + return -EOPNOTSUPP; +} + uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, enum amd_hw_ip_block_type block, int die_inst) { if (!adev->reg.smn.get_smn_base) { - dev_err_once(adev->dev, "SMN base address callback not set\n"); + int version = amdgpu_reg_get_smn_base_version(adev); + switch (version) { + case 1: + return amdgpu_reg_smn_v1_0_get_base(adev, block, + die_inst); + default: + dev_err_once( + adev->dev, + "SMN base address query not supported for this device\n"); + return 0; + } return 0; } return adev->reg.smn.get_smn_base(adev, block, die_inst); } +uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst) +{ + uint64_t smn_base; + + if (die_inst == 0) + return 0; + + switch (block) { + case XGMI_HWIP: + case NBIO_HWIP: + case MP0_HWIP: + case UMC_HWIP: + case DF_HWIP: + smn_base = ((uint64_t)(die_inst & 0x3) << 32) | (1ULL << 34); + break; + default: + dev_warn_once( + adev->dev, + "SMN base address query not supported for this block %d\n", + block); + smn_base = 0; + break; + } + + return smn_base; +} + /* * register access helper functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index b3b941cc7b7c4..4d88e5cd19fc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -122,6 +122,9 @@ void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, enum amd_hw_ip_block_type block, int die_inst); +uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst); uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t acc_flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 9375e3f647848..b329d7b2dcb6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -338,7 +338,7 @@ static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link if (!(adev->aid_mask & BIT(i))) return U32_MAX; - addr += adev->asic_funcs->encode_ext_smn_addressing(i); + addr += amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i); return RREG32_PCIE_EXT(addr); } @@ -1299,7 +1299,10 @@ static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev) static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base) { - WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); + uint64_t smn_base = + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst); + + WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL); } static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst) @@ -1509,6 +1512,7 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a u64 mca_base, struct ras_err_data *err_data) { int xgmi_inst = mcm_info->die_id; + uint64_t smn_base; u64 status = 0; status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS); @@ -1525,8 +1529,8 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a default: break; } - - WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); + smn_base = amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst); + WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL); } static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index d9842aa25283a..72ea37dbfea8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -58,25 +58,6 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1; } -/* Fixed pattern for smn addressing on different AIDs: - * bit[34]: indicate cross AID access - * bit[33:32]: indicate target AID id - * AID id range is 0 ~ 3 as maximum AID number is 4. - */ -u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id) -{ - u64 ext_offset; - - /* local routing and bit[34:32] will be zeros */ - if (ext_id == 0) - return 0; - - /* Initiated from host, accessing to all non-zero aids are cross traffic */ - ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34); - - return ext_offset; -} - static enum amdgpu_gfx_partition __aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) { @@ -590,7 +571,7 @@ static void aqua_read_smn_ext(struct amdgpu_device *adev, uint64_t smn_addr, int i) { regdata->addr = - smn_addr + adev->asic_funcs->encode_ext_smn_addressing(i); + smn_addr + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i); regdata->value = RREG32_PCIE_EXT(regdata->addr); } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index d1e1a43695210..a0c84f81c0c9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -166,7 +166,7 @@ static void psp_v13_0_bootloader_print_status(struct psp_context *psp, bl_status_reg = (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92) << 2) + - adev->asic_funcs->encode_ext_smn_addressing(i); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, i); at += snprintf(bl_status_msg + at, PSP13_BL_STATUS_SIZE - at, " status(%02i): 0x%08x", i, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index c95e5883e0573..b456e4541d9ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -952,7 +952,6 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, .supports_baco = &soc15_supports_baco, .query_video_codecs = &soc15_query_video_codecs, - .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, .get_reg_state = &aqua_vanjaram_get_reg_state, }; @@ -1198,6 +1197,7 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(9, 4, 4): case IP_VERSION(9, 5, 0): adev->asic_funcs = &aqua_vanjaram_asic_funcs; + adev->reg.smn.get_smn_base = &amdgpu_reg_smn_v1_0_get_base; adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index c8ac11a9cdef6..46a6477b677ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -118,7 +118,6 @@ int vega10_reg_base_init(struct amdgpu_device *adev); int vega20_reg_base_init(struct amdgpu_device *adev); int arct_reg_base_init(struct amdgpu_device *adev); int aldebaran_reg_base_init(struct amdgpu_device *adev); -u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id); int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev); ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev, enum amdgpu_reg_state reg_state, void *buf, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 242b24f73c174..a7b5a95ebebbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -195,19 +195,22 @@ __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst) /* inst equals to ext for some IPs */ -#define RREG32_SOC15_EXT(ip, inst, reg, ext) \ - RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ - + adev->asic_funcs->encode_ext_smn_addressing(ext)) \ - -#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ - WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ - + adev->asic_funcs->encode_ext_smn_addressing(ext), \ - value) \ - -#define RREG64_MCA(ext, mca_base, idx) \ - RREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8)) - -#define WREG64_MCA(ext, mca_base, idx, val) \ - WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val) +#define RREG32_SOC15_EXT(ip, inst, reg, ext) \ + RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + \ + reg) * 4 + \ + amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst)) + +#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ + WREG32_PCIE_EXT( \ + (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * \ + 4 + \ + amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst), \ + value) + +#define RREG64_MCA(smn_base, mca_base, idx) \ + RREG64_PCIE_EXT(smn_base + mca_base + (idx * 8)) + +#define WREG64_MCA(smn_base, mca_base, idx, val) \ + WREG64_PCIE_EXT(smn_base + mca_base + (idx * 8), val) #endif From cd5f97c8bfcff0869677218d363ee857d11346f1 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 26 Feb 2026 17:56:26 +0800 Subject: [PATCH 1735/2070] drm/amdgpu: Fix static assertion failure issue Since the PAGE_SIZE is 8KB on sparc64, the size of structure amdsriov_ras_telemetry will exceed 64KB, so use absolute value to fix the buffer size. Fixes the issue: drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:522:2: error: static assertion failed due to requirement 'sizeof(struct amdsriov_ras_telemetry) <= 64 << 10': amdsriov_ras_telemetry must be 64 KB | sizeof(struct amdsriov_ras_telemetry) <= AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10, drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:522:40: note: expression evaluates to '115616 <= 65536' | sizeof(struct amdsriov_ras_telemetry) <= AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10, Fixes: cb48a6b2b61d ("drm/amd/ras: use dedicated memory as vf ras command buffer") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202602261700.rVOLIw4l-lkp@intel.com/ Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 5 +++-- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 4870c03627df1..a841f342a3ebb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -476,9 +476,10 @@ union amd_sriov_ras_host_push { struct amd_sriov_ras_chk_criti chk_criti; }; -#define AMD_SRIOV_UNIRAS_CMD_MAX_SIZE (PAGE_SIZE * 13) +#define AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE 4096 +#define AMD_SRIOV_UNIRAS_CMD_MAX_SIZE (4096 * 13) struct amd_sriov_uniras_shared_mem { - uint8_t blocks_ecc_buf[PAGE_SIZE]; + uint8_t blocks_ecc_buf[AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE]; uint8_t cmd_buf[AMD_SRIOV_UNIRAS_CMD_MAX_SIZE]; }; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c index 3e8b500caec1a..81553230dca44 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c @@ -63,7 +63,7 @@ static int amdgpu_virt_ras_get_cmd_shared_mem(struct ras_core_context *ras_core, ras_telemetry_offset); if (cmd == RAS_CMD__GET_ALL_BLOCK_ECC_STATUS) { - if (mem_size > PAGE_SIZE) + if (mem_size > AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE) return -ENOMEM; shared_mem->cpu_addr = ras_telemetry_cpu->uniras_shared_mem.blocks_ecc_buf; @@ -504,7 +504,7 @@ int amdgpu_virt_ras_hw_init(struct amdgpu_device *adev) memset(blks_ecc, 0, sizeof(*blks_ecc)); if (amdgpu_virt_ras_get_cmd_shared_mem(ras_mgr->ras_core, RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, - PAGE_SIZE, &blks_ecc->shared_mem)) + AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE, &blks_ecc->shared_mem)) return -ENOMEM; return 0; From 11dc6694c01900fc47095d4b3554d7ea1a7e2689 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Sat, 21 Feb 2026 10:48:14 +0800 Subject: [PATCH 1736/2070] drm/amdgpu: compatible with specific RAS old eeprom format Handle RAS eeprom record when UMC_CHANNEL_IDX_V2 is set. v2: get UMC_CHANNEL_IDX_V2 flag before the clear of it. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5dcba6ec295d8..bbed569f1807b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3142,9 +3142,11 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev, enum amdgpu_memory_partition nps) { int i = 0; + uint64_t chan_idx_v2; enum amdgpu_memory_partition save_nps; save_nps = (bps[0].retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + chan_idx_v2 = bps[0].retired_page & UMC_CHANNEL_IDX_V2; /*old asics just have pa in eeprom*/ if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { @@ -3156,7 +3158,7 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev, for (i = 0; i < adev->umc.retire_unit; i++) bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); - if (save_nps) { + if (save_nps || chan_idx_v2) { if (save_nps == nps) { if (amdgpu_umc_pages_in_a_row(adev, err_data, bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT)) @@ -3200,10 +3202,12 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, enum amdgpu_memory_partition nps) { int i = 0; + uint64_t chan_idx_v2; enum amdgpu_memory_partition save_nps; if (!amdgpu_ras_smu_eeprom_supported(adev)) { save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + chan_idx_v2 = bps->retired_page & UMC_CHANNEL_IDX_V2; bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); } else { /* if pmfw manages eeprom, save_nps is not stored on eeprom, @@ -3225,16 +3229,19 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, err_data->err_addr[i].mcumc_id = bps->mcumc_id; } } else { - if (bps->address) { + if (save_nps || chan_idx_v2) { if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data)) return -EINVAL; } else { /* for specific old eeprom data, mca address is not stored, * calc it from pa */ - if (amdgpu_umc_pa2mca(adev, bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, - &(bps->address), AMDGPU_NPS1_PARTITION_MODE)) - return -EINVAL; + if (bps->address == 0) + if (amdgpu_umc_pa2mca(adev, + bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, + &(bps->address), + AMDGPU_NPS1_PARTITION_MODE)) + return -EINVAL; if (amdgpu_ras_mca2pa(adev, bps, err_data)) return -EOPNOTSUPP; From 64558a860b7ad120cf4a9ae26959cf8df0597f38 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Feb 2026 13:05:55 +0530 Subject: [PATCH 1737/2070] drm/amdgpu/userq: change queue id type to u32 from int queue id always remain a positive value and should be of type unsigned. With this we also dont need to typecast the id to other types specially in xarray functions. Signed-off-by: Sunil Khatri Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 9e0cb31946733..0a5c3169c61ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -447,7 +447,7 @@ static int amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) } static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, - int queue_id) + u32 queue_id) { struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; @@ -461,7 +461,7 @@ static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, uq_funcs->mqd_destroy(queue); amdgpu_userq_fence_driver_free(queue); /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ - xa_erase_irq(&uq_mgr->userq_xa, (unsigned long)queue_id); + xa_erase_irq(&uq_mgr->userq_xa, queue_id); xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); queue->userq_mgr = NULL; list_del(&queue->userq_va_list); @@ -471,7 +471,7 @@ static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, } static struct amdgpu_usermode_queue * -amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid) +amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, u32 qid) { return xa_load(&uq_mgr->userq_xa, qid); } @@ -625,7 +625,7 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, } static int -amdgpu_userq_destroy(struct drm_file *filp, int queue_id) +amdgpu_userq_destroy(struct drm_file *filp, u32 queue_id) { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; From 27152fc273b8bba458704e2198ae40d3614688eb Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Feb 2026 21:14:27 +0530 Subject: [PATCH 1738/2070] drm/amdgpu: update type for num_syncobj_handles in drm_amdgpu_userq_signal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit update the type for num_syncobj_handles from __u64 to _u16 with required padding. This breaks the UAPI for big-endian platforms but this is deliberate and harmless since userqueues is still a beta feature. It is enabled via module parameter and need the right fw support to work. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- include/uapi/drm/amdgpu_drm.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 87858adf780ba..5f32a2d45945c 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -501,7 +501,9 @@ struct drm_amdgpu_userq_signal { * @num_syncobj_handles: A count that represents the number of syncobj handles in * @syncobj_handles. */ - __u64 num_syncobj_handles; + __u16 num_syncobj_handles; + __u16 pad0; + __u32 pad1; /** * @bo_read_handles: The list of BO handles that the submitted user queue job * is using for read only. This will update BO fences in the kernel. From e2b2bfcea3c17dfa4354d5df4960f4059b863e09 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Feb 2026 21:18:51 +0530 Subject: [PATCH 1739/2070] drm/amdgpu: update type for num_syncobj_handles in drm_amdgpu_userq_wait MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit update the type for num_syncobj_handles from __u32 to _u16 with required padding. This breaks the UAPI for big-endian platforms but this is deliberate and harmless since userqueues is still a beta feature. It is enabled via module parameter and need the right fw support to work. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- include/uapi/drm/amdgpu_drm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 5f32a2d45945c..e561e7e98bf97 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -587,7 +587,8 @@ struct drm_amdgpu_userq_wait { * @num_syncobj_handles: A count that represents the number of syncobj handles in * @syncobj_handles. */ - __u32 num_syncobj_handles; + __u16 num_syncobj_handles; + __u16 pad0; /** * @num_bo_read_handles: A count that represents the number of read BO handles in * @bo_read_handles. From ee7dae8b0b7b17bc815656ccf7af1532aae6caae Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 1 Mar 2026 18:19:50 +0530 Subject: [PATCH 1740/2070] drm/amdgpu: Drop redundant syncobj handle limit checks in userq ioctls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clang warns that comparing a __u16 value against 65536 is always false. num_syncobj_handles is defined as __u16 in both the userq signal and wait ioctl argument structs, so it can never exceed 65535. The checks against AMDGPU_USERQ_MAX_HANDLES are therefore redundant and trigger -Wtautological-constant-out-of-range-compare. Fixes: Clang -Wtautological-constant-out-of-range-compare in userq signal/wait ioctls Fixes: 2a235bc2e28e ("drm/amdgpu: add upper bound check on user inputs in signal ioctl") Fixes: 7d79dc596e6e ("drm/amdgpu: add upper bound check on user inputs in wait ioctl") Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 86319a9fef211..4fc8e44692d77 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -543,8 +543,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; - if (args->num_syncobj_handles > AMDGPU_USERQ_MAX_HANDLES || - args->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + if (args->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || args->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) return -EINVAL; @@ -699,8 +698,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; - if (wait_info->num_syncobj_handles > AMDGPU_USERQ_MAX_HANDLES || - wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + if (wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) return -EINVAL; From 0cf9ff42a34cb2c096d739852bc5df71871f9da0 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Thu, 11 Dec 2025 18:14:46 +0800 Subject: [PATCH 1741/2070] drm/amd/pm: add pmfw eeprom messages into uniras interface add pmfw eeprom related messages into smu_v13_0_6_ras_send_msg v2: add sriov check before sending smu commands Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index b8fa554559814..61df154aac002 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3344,14 +3344,25 @@ static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg) { + struct amdgpu_device *adev = smu->adev; int ret; + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + switch (msg) { case SMU_MSG_QueryValidMcaCount: case SMU_MSG_QueryValidMcaCeCount: case SMU_MSG_McaBankDumpDW: case SMU_MSG_McaBankCeDumpDW: case SMU_MSG_ClearMcaOnRead: + case SMU_MSG_GetRASTableVersion: + case SMU_MSG_GetBadPageCount: + case SMU_MSG_GetBadPageMcaAddr: + case SMU_MSG_SetTimestamp: + case SMU_MSG_GetTimestamp: + case SMU_MSG_GetBadPageIpid: + case SMU_MSG_EraseRasTable: ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg); break; default: From 2373ec0f60bf2d23be6a96e152b8ce529451e25a Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 2 Mar 2026 18:50:46 +0530 Subject: [PATCH 1742/2070] drm/amdgpu/userq: refcount userqueues to avoid any race conditions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To avoid race condition and avoid UAF cases, implement kref based queues and protect the below operations using xa lock a. Getting a queue from xarray b. Increment/Decrement it's refcount Every time some one want to access a queue, always get via amdgpu_userq_get to make sure we have locks in place and get the object if active. A userqueue is destroyed on the last refcount is dropped which typically would be via IOCTL or during fini. v2: Add the missing drop in one the condition in the signal ioclt [Alex] v3: remove the queue from the xarray first in the free queue ioctl path [Christian] - Pass queue to the amdgpu_userq_put directly. - make amdgpu_userq_put xa_lock free since we are doing put for each get only and final put is done via destroy and we remove the queue from xa with lock. - use userq_put in fini too so cleanup is done fully. v4: Use xa_erase directly rather than doing load and erase in free ioctl. Also remove some of the error logs which could be exploited by the user to flood the logs [Christian] Signed-off-by: Sunil Khatri Reviewed-by: Christian König Reviewed-by: Alex Deucher Change-Id: Ie2865bf9947e5d30546febe9fbed42eac095cbbd --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 116 ++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 4 + .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 14 ++- 3 files changed, 95 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 0a5c3169c61ce..56d5a87d3fa38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -446,8 +446,7 @@ static int amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) return ret; } -static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, - u32 queue_id) +static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue) { struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; @@ -461,7 +460,6 @@ static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, uq_funcs->mqd_destroy(queue); amdgpu_userq_fence_driver_free(queue); /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ - xa_erase_irq(&uq_mgr->userq_xa, queue_id); xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); queue->userq_mgr = NULL; list_del(&queue->userq_va_list); @@ -470,12 +468,6 @@ static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue, up_read(&adev->reset_domain->sem); } -static struct amdgpu_usermode_queue * -amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, u32 qid) -{ - return xa_load(&uq_mgr->userq_xa, qid); -} - void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr) @@ -625,22 +617,13 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, } static int -amdgpu_userq_destroy(struct drm_file *filp, u32 queue_id) +amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) { - struct amdgpu_fpriv *fpriv = filp->driver_priv; - struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; - struct amdgpu_usermode_queue *queue; int r = 0; cancel_delayed_work_sync(&uq_mgr->resume_work); mutex_lock(&uq_mgr->userq_mutex); - queue = amdgpu_userq_find(uq_mgr, queue_id); - if (!queue) { - drm_dbg_driver(adev_to_drm(uq_mgr->adev), "Invalid queue id to destroy\n"); - mutex_unlock(&uq_mgr->userq_mutex); - return -EINVAL; - } amdgpu_userq_wait_for_last_fence(queue); /* Cancel any pending hang detection work and cleanup */ if (queue->hang_detect_fence) { @@ -672,7 +655,7 @@ amdgpu_userq_destroy(struct drm_file *filp, u32 queue_id) drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n"); queue->state = AMDGPU_USERQ_STATE_HUNG; } - amdgpu_userq_cleanup(queue, queue_id); + amdgpu_userq_cleanup(queue); mutex_unlock(&uq_mgr->userq_mutex); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -680,6 +663,37 @@ amdgpu_userq_destroy(struct drm_file *filp, u32 queue_id) return r; } +static void amdgpu_userq_kref_destroy(struct kref *kref) +{ + int r; + struct amdgpu_usermode_queue *queue = + container_of(kref, struct amdgpu_usermode_queue, refcount); + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; + + r = amdgpu_userq_destroy(uq_mgr, queue); + if (r) + drm_file_err(uq_mgr->file, "Failed to destroy usermode queue %d\n", r); +} + +struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid) +{ + struct amdgpu_usermode_queue *queue; + + xa_lock(&uq_mgr->userq_xa); + queue = xa_load(&uq_mgr->userq_xa, qid); + if (queue) + kref_get(&queue->refcount); + xa_unlock(&uq_mgr->userq_xa); + + return queue; +} + +void amdgpu_userq_put(struct amdgpu_usermode_queue *queue) +{ + if (queue) + kref_put(&queue->refcount, amdgpu_userq_kref_destroy); +} + static int amdgpu_userq_priority_permit(struct drm_file *filp, int priority) { @@ -839,6 +853,9 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) goto unlock; } + /* drop this refcount during queue destroy */ + kref_init(&queue->refcount); + /* Wait for mode-1 reset to complete */ down_read(&adev->reset_domain->sem); r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); @@ -992,7 +1009,9 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { union drm_amdgpu_userq *args = data; - int r; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_usermode_queue *queue; + int r = 0; if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; @@ -1007,11 +1026,16 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, drm_file_err(filp, "Failed to create usermode queue\n"); break; - case AMDGPU_USERQ_OP_FREE: - r = amdgpu_userq_destroy(filp, args->in.queue_id); - if (r) - drm_file_err(filp, "Failed to destroy usermode queue\n"); + case AMDGPU_USERQ_OP_FREE: { + xa_lock(&fpriv->userq_mgr.userq_xa); + queue = __xa_erase(&fpriv->userq_mgr.userq_xa, args->in.queue_id); + xa_unlock(&fpriv->userq_mgr.userq_xa); + if (!queue) + return -ENOENT; + + amdgpu_userq_put(queue); break; + } default: drm_dbg_driver(dev, "Invalid user queue op specified: %d\n", args->in.op); @@ -1030,16 +1054,23 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) /* Resume all the queues for this process */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { + queue = amdgpu_userq_get(uq_mgr, queue_id); + if (!queue) + continue; + if (!amdgpu_userq_buffer_vas_mapped(queue)) { drm_file_err(uq_mgr->file, "trying restore queue without va mapping\n"); queue->state = AMDGPU_USERQ_STATE_INVALID_VA; + amdgpu_userq_put(queue); continue; } r = amdgpu_userq_restore_helper(queue); if (r) ret = r; + + amdgpu_userq_put(queue); } if (ret) @@ -1286,9 +1317,13 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) amdgpu_userq_detect_and_reset_queues(uq_mgr); /* Try to unmap all the queues in this process ctx */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { + queue = amdgpu_userq_get(uq_mgr, queue_id); + if (!queue) + continue; r = amdgpu_userq_preempt_helper(queue); if (r) ret = r; + amdgpu_userq_put(queue); } if (ret) @@ -1321,16 +1356,24 @@ amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) int ret; xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { + queue = amdgpu_userq_get(uq_mgr, queue_id); + if (!queue) + continue; + struct dma_fence *f = queue->last_fence; - if (!f || dma_fence_is_signaled(f)) + if (!f || dma_fence_is_signaled(f)) { + amdgpu_userq_put(queue); continue; + } ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100)); if (ret <= 0) { drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", f->context, f->seqno); + amdgpu_userq_put(queue); return -ETIMEDOUT; } + amdgpu_userq_put(queue); } return 0; @@ -1381,20 +1424,23 @@ int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *f void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) { struct amdgpu_usermode_queue *queue; - unsigned long queue_id; + unsigned long queue_id = 0; + + for (;;) { + xa_lock(&userq_mgr->userq_xa); + queue = xa_find(&userq_mgr->userq_xa, &queue_id, ULONG_MAX, + XA_PRESENT); + if (queue) + __xa_erase(&userq_mgr->userq_xa, queue_id); + xa_unlock(&userq_mgr->userq_xa); - cancel_delayed_work_sync(&userq_mgr->resume_work); + if (!queue) + break; - mutex_lock(&userq_mgr->userq_mutex); - amdgpu_userq_detect_and_reset_queues(userq_mgr); - xa_for_each(&userq_mgr->userq_xa, queue_id, queue) { - amdgpu_userq_wait_for_last_fence(queue); - amdgpu_userq_unmap_helper(queue); - amdgpu_userq_cleanup(queue, queue_id); + amdgpu_userq_put(queue); } xa_destroy(&userq_mgr->userq_xa); - mutex_unlock(&userq_mgr->userq_mutex); mutex_destroy(&userq_mgr->userq_mutex); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index c0d20343d662f..989e47308351b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -79,6 +79,7 @@ struct amdgpu_usermode_queue { struct dentry *debugfs_queue; struct delayed_work hang_detect_work; struct dma_fence *hang_detect_fence; + struct kref refcount; struct list_head userq_va_list; }; @@ -119,6 +120,9 @@ struct amdgpu_db_info { struct amdgpu_userq_obj *db_obj; }; +struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid); +void amdgpu_userq_put(struct amdgpu_usermode_queue *queue); + int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 4fc8e44692d77..8b08484a0e8e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -533,7 +533,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_gem_object **gobj_write, **gobj_read; u32 *syncobj_handles, num_syncobj_handles; struct amdgpu_userq_fence *userq_fence; - struct amdgpu_usermode_queue *queue; + struct amdgpu_usermode_queue *queue = NULL; struct drm_syncobj **syncobj = NULL; struct dma_fence *fence; struct drm_exec exec; @@ -583,7 +583,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, goto put_gobj_read; /* Retrieve the user queue */ - queue = xa_load(&userq_mgr->userq_xa, args->queue_id); + queue = amdgpu_userq_get(userq_mgr, args->queue_id); if (!queue) { r = -ENOENT; goto put_gobj_write; @@ -674,6 +674,9 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, free_syncobj_handles: kfree(syncobj_handles); + if (queue) + amdgpu_userq_put(queue); + return r; } @@ -688,7 +691,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; struct drm_gem_object **gobj_write, **gobj_read; u32 *timeline_points, *timeline_handles; - struct amdgpu_usermode_queue *waitq; + struct amdgpu_usermode_queue *waitq = NULL; u32 *syncobj_handles, num_syncobj; struct dma_fence **fences = NULL; u16 num_points, num_fences = 0; @@ -924,7 +927,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, */ num_fences = dma_fence_dedup_array(fences, num_fences); - waitq = xa_load(&userq_mgr->userq_xa, wait_info->waitq_id); + waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id); if (!waitq) { r = -EINVAL; goto free_fences; @@ -1016,5 +1019,8 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, free_syncobj_handles: kfree(syncobj_handles); + if (waitq) + amdgpu_userq_put(waitq); + return r; } From 3f49d3aadebce41747287474587051b86ff54ba1 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 3 Mar 2026 22:25:57 +0530 Subject: [PATCH 1743/2070] drm/amdgpu/userq: remove queue from doorbell xarray MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In case of failure in xa_alloc, remove the queue during clean up from the userq_doorbell_xa. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 56d5a87d3fa38..e4a76facdd479 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -870,6 +870,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) if (r) { drm_file_err(uq_mgr->file, "Failed to allocate a queue id\n"); amdgpu_userq_fence_driver_free(queue); + xa_erase_irq(&adev->userq_doorbell_xa, index); uq_funcs->mqd_destroy(queue); kfree(queue); r = -ENOMEM; From 8a53e63914b193779cd77254d247fdbd233ac62b Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 3 Mar 2026 22:30:04 +0530 Subject: [PATCH 1744/2070] drm/amdgpu/userq: remove queue from doorbell xa during clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If function amdgpu_userq_map_helper fails we do need to clean up and remove the queue from the userq_doorbell_xa. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index e4a76facdd479..bf7fcc9e74de5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -890,6 +890,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) r = amdgpu_userq_map_helper(queue); if (r) { drm_file_err(uq_mgr->file, "Failed to map Queue\n"); + xa_erase_irq(&adev->userq_doorbell_xa, index); xa_erase(&uq_mgr->userq_xa, qid); amdgpu_userq_fence_driver_free(queue); uq_funcs->mqd_destroy(queue); From bdf2c331be60196a0e5b73fef4d31272824d9915 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 26 Feb 2026 15:15:51 -0500 Subject: [PATCH 1745/2070] drm/amdgpu: GFX12.1 scratch memory limit up to 57-bit The scratch aperture or gmc private aperture in flat memory contains 57 bits of data on gfx v12.1.0 compared to the 32 bits from previous. Add new helper kfd_init_apertures_v12 for gfx version >= v12.1.0 which supports 57-bit VA space. v2: - update pdd->scratch_limit (Yu, Lang) - update fixes tag (Felix Kuehling) - add helper kfd_init_apertures_v12 Fixes: a1d7c4f45913 ("drm/amdkfd: Update LDS, Scratch base for 57bit address") Signed-off-by: Philip Yang Reviewed-by: Lang Yu Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 10 ++++-- drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 35 ++++++++++++++------ 3 files changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index eb9725ae1607a..557d15b90ad27 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -1405,7 +1405,7 @@ static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, /* * Configure apertures: * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) - * Scratch: 0x10000000'00000000 - 0x10000001'00000000 (4GB) + * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) */ sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, (adev->gmc.private_aperture_start >> 58)); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index b9671fc39e2a8..da4a0cf4aad0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -654,9 +654,15 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) adev->gmc.shared_aperture_start = 0x2000000000000000ULL; adev->gmc.shared_aperture_end = adev->gmc.shared_aperture_start + (4ULL << 30) - 1; + adev->gmc.private_aperture_start = 0x1000000000000000ULL; - adev->gmc.private_aperture_end = - adev->gmc.private_aperture_start + (4ULL << 30) - 1; + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) + adev->gmc.private_aperture_end = + adev->gmc.private_aperture_start + (1ULL << 57) - 1; + else + adev->gmc.private_aperture_end = + adev->gmc.private_aperture_start + (4ULL << 30) - 1; + adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index e8da0b4527dc5..04c5e26f01ed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -342,20 +342,14 @@ static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id) static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id) { - if (KFD_GC_VERSION(pdd->dev) >= IP_VERSION(12, 1, 0)) - pdd->lds_base = pdd->dev->adev->gmc.shared_aperture_start; - else - pdd->lds_base = MAKE_LDS_APP_BASE_V9(); + pdd->lds_base = MAKE_LDS_APP_BASE_V9(); pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base); pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM; pdd->gpuvm_limit = pdd->dev->kfd->shared_resources.gpuvm_size - 1; - if (KFD_GC_VERSION(pdd->dev) >= IP_VERSION(12, 1, 0)) - pdd->scratch_base = pdd->dev->adev->gmc.private_aperture_start; - else - pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9(); + pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9(); pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base); /* @@ -365,6 +359,25 @@ static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id) pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev); } +static void kfd_init_apertures_v12(struct kfd_process_device *pdd, uint8_t id) +{ + pdd->lds_base = pdd->dev->adev->gmc.shared_aperture_start; + pdd->lds_limit = pdd->dev->adev->gmc.shared_aperture_end; + + pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM; + pdd->gpuvm_limit = + pdd->dev->kfd->shared_resources.gpuvm_size - 1; + + pdd->scratch_base = pdd->dev->adev->gmc.private_aperture_start; + pdd->scratch_limit = pdd->dev->adev->gmc.private_aperture_end; + + /* + * Place TBA/TMA on opposite side of VM hole to prevent + * stray faults from triggering SVM on these pages. + */ + pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev); +} + int kfd_init_apertures(struct kfd_process *process) { uint8_t id = 0; @@ -412,9 +425,11 @@ int kfd_init_apertures(struct kfd_process *process) kfd_init_apertures_vi(pdd, id); break; default: - if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) + if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 1, 0)) { + kfd_init_apertures_v12(pdd, id); + } else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) { kfd_init_apertures_v9(pdd, id); - else { + } else { WARN(1, "Unexpected ASIC family %u", dev->adev->asic_type); return -EINVAL; From 45c0e739ad6d9ee94e45c9cd4ae5990f21bfa049 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 25 Feb 2026 22:51:06 -0500 Subject: [PATCH 1746/2070] drm/amd/pm: remove invalid gpu_metrics.energy_accumulator on smu v13.0.x v1: The metrics->EnergyAccumulator field has been deprecated on newer pmfw. v2: add smu 13.0.0/13.0.7/13.0.10 support. Signed-off-by: Yang Wang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 +++++++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 ++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 8b5ef34173e00..e2582c16d5132 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2035,6 +2035,7 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetricsExternal_t metrics_ext; SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; + uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0); int ret = 0; ret = smu_cmn_get_metrics_table(smu, @@ -2059,7 +2060,12 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, metrics->Vcn1ActivityPercentage); gpu_metrics->average_socket_power = metrics->AverageSocketPower; - gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; + + if ((mp1_ver == IP_VERSION(13, 0, 0) && smu->smc_fw_version <= 0x004e1e00) || + (mp1_ver == IP_VERSION(13, 0, 10) && smu->smc_fw_version <= 0x00500800)) + gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; + else + gpu_metrics->energy_accumulator = UINT_MAX; if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index a6c22ae86c985..4f729f54a64cc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2066,7 +2066,8 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, metrics->Vcn1ActivityPercentage); gpu_metrics->average_socket_power = metrics->AverageSocketPower; - gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; + gpu_metrics->energy_accumulator = smu->smc_fw_version <= 0x00521400 ? + metrics->EnergyAccumulator : UINT_MAX; if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; From d8a7339eb290ebcccb27977b0b3209e604c191e7 Mon Sep 17 00:00:00 2001 From: "Alysa.Liu@amd.com" Date: Thu, 5 Feb 2026 11:21:45 -0500 Subject: [PATCH 1747/2070] drm/amdgpu: Fix use-after-free race in VM acquire Replace non-atomic vm->process_info assignment with cmpxchg() to prevent race when parent/child processes sharing a drm_file both try to acquire the same VM after fork(). Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alysa Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 35fb1c3b4aee3..c6e2792e64e42 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1528,7 +1528,10 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, *process_info = info; } - vm->process_info = *process_info; + if (cmpxchg(&vm->process_info, NULL, *process_info) != NULL) { + ret = -EINVAL; + goto already_acquired; + } /* Validate page directory and attach eviction fence */ ret = amdgpu_bo_reserve(vm->root.bo, true); @@ -1568,6 +1571,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, amdgpu_bo_unreserve(vm->root.bo); reserve_pd_fail: vm->process_info = NULL; +already_acquired: if (info) { dma_fence_put(&info->eviction_fence->base); *process_info = NULL; From 6a19b7561635fde245a43ec9d8a7b2885fa544b3 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 7 Jan 2026 12:43:49 +0000 Subject: [PATCH 1748/2070] drm/amdgpu: Reject impossible entities early MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently there are two different behaviour modes when userspace tries to operate on not present HW IP blocks. On a machine without UVD, VCE and VPE blocks, this can be observed for example like this: $ sudo ./amd_fuzzing --r cs-wait-fuzzing ... amd_cs_wait_fuzzing DRM_IOCTL_AMDGPU_CTX r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_GFX r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_COMPUTE r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_DMA r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_UVD r -1 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCE r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_UVD_ENC r -1 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCN_DEC r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCN_ENC r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VCN_JPEG r 0 amd_cs_wait_fuzzing AMDGPU_WAIT_CS AMD_IP_VPE r 0 We can see that UVD returns an errno (-EINVAL) from the CS_WAIT ioctl, while VCE and VPE return unexpected successes. The difference stems from the fact the UVD is a load balancing engine which retains the context, so with a workaround implemented in amdgpu_ctx_init_entity(), but which does not account for the fact hardware block may not be present. This causes a single NULL scheduler to be passed to drm_sched_entity_init(), which immediately rejects this with -EINVAL. The not present VCE and VPE cases on the other hand pass zero schedulers to drm_sched_entity_init(), which is explicitly allowed and results in unusable entities. As the UVD case however shows, call paths can handle the errors, so we can consolidate this into a single path which will always return -EINVAL if the HW IP block is not present. We do this by rejecting it early and not calling drm_sched_entity_init() when there is no backing hardware. This also removes the need for the drm_sched_entity_init() to handle the zero schedulers and NULL scheduler cases, which means that we can follow up by removing the special casing from the DRM scheduler. Signed-off-by: Tvrtko Ursulin References: f34e8bb7d6c6 ("drm/sched: fix null-ptr-deref in init entity") Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 9989a7ff56fc0..38c52df687d52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -242,6 +242,11 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, goto error_free_entity; } + if (num_scheds == 0) { + r = -EINVAL; + goto error_free_entity; + } + /* disable load balance if the hw engine retains context among dependent jobs */ if (hw_ip == AMDGPU_HW_IP_VCN_ENC || hw_ip == AMDGPU_HW_IP_VCN_DEC || From 41f81bb7a9dbf970328922d2982829251e0f3c1d Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 7 Jan 2026 12:43:50 +0000 Subject: [PATCH 1749/2070] drm/amdgpu: Remove redundant missing hw ip handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that it is guaranteed there can be no entity if there is no hw ip block we can remove the open coded protection during CS parsing. Signed-off-by: Tvrtko Ursulin References: 55414ad5c983 ("drm/amdgpu: error out on entity with no run queue") Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 850aa2cd4abbf..eaec1ec52f5d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -86,13 +86,6 @@ static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p, if (r) return r; - /* - * Abort if there is no run queue associated with this entity. - * Possibly because of disabled HW IP. - */ - if (entity->rq == NULL) - return -EINVAL; - /* Check if we can add this IB to some existing job */ for (i = 0; i < p->gang_size; ++i) if (p->entities[i] == entity) From 3c225bc6972a1b250d32a87cb136398f08bd5f56 Mon Sep 17 00:00:00 2001 From: sguttula Date: Wed, 25 Feb 2026 13:57:01 +0530 Subject: [PATCH 1750/2070] drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox The reason the RAP is not granting access to 0x58200 is that a dedicated RSMU slot would have to be spent for this address range, and MPASP is close to running out of RSMU slots. This will help to fix PSP TOC load failure during secureboot. GFX Driver Need to use indirect access for SMN address regs. Signed-off-by: sguttula Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/psp_v15_0.c | 20 +++++++++---------- .../include/asic_reg/mp/mp_15_0_0_offset.h | 18 +++++++++++++++++ 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c index 723ddae176448..73a709773e85b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c @@ -69,12 +69,12 @@ static int psp_v15_0_0_ring_stop(struct psp_context *psp, 0x80000000, 0x80000000, false); } else { /* Write the ring destroy command*/ - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS); /* there might be handshake issue with hardware which needs delay */ mdelay(20); /* Wait for response flag (bit 31) */ - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 0x80000000, 0x80000000, false); } @@ -116,7 +116,7 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp, } else { /* Wait for sOS ready for ring creation */ - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 0x80000000, 0x80000000, false); if (ret) { DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); @@ -125,23 +125,23 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp, /* Write low address of the ring to C2PMSG_69 */ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg); /* Write high address of the ring to C2PMSG_70 */ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg); /* Write size of ring to C2PMSG_71 */ psp_ring_reg = ring->ring_size; - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg); /* Write the ring initialization command to C2PMSG_64 */ psp_ring_reg = ring_type; psp_ring_reg = psp_ring_reg << 16; - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg); /* there might be handshake issue with hardware which needs delay */ mdelay(20); /* Wait for response flag (bit 31) in C2PMSG_64 */ - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), 0x80000000, 0x8000FFFF, false); } @@ -174,7 +174,7 @@ static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp) if (amdgpu_sriov_vf(adev)) data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); else - data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); + data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67); return data; } @@ -188,7 +188,7 @@ static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value) WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); } else - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value); } static const struct psp_funcs psp_v15_0_0_funcs = { diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h index 0e4c195297a45..fe97943b9b977 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h @@ -82,6 +82,24 @@ #define regMPASP_SMN_IH_SW_INT_CTRL 0x0142 #define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +// addressBlock: mp_SmuMpASPPub_PcruDec +// base address: 0x3800000 +#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280 +#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281 +#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282 +#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283 +#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284 +#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285 +#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286 +#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287 +#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3 // addressBlock: mp_SmuMp1_SmnDec // base address: 0x0 From f89c85d9b149719f180e814ce5cb821c982fe27d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 25 Feb 2026 17:53:31 +0530 Subject: [PATCH 1751/2070] drm/amd/pm: Add pm firmware info to dmesg log Add PMFW info to dmesg log for SMUv13 SOCs. It's helpful as diagnostic data for some driver load issues. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 330f1e615b1bf..0f4b4f31bfeb6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -288,12 +288,13 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) * Considering above, we just leave user a verbal message instead * of halt driver loading. */ - if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && - if_version != smu->smc_driver_if_version) { - dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " + dev_info_once(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); + + if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && + if_version != smu->smc_driver_if_version) { dev_info(adev->dev, "SMU driver if version not matched\n"); } From 2569b4909f48746d38dbd1dbdb3d37ca492bfb8f Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sat, 28 Feb 2026 21:56:40 +0530 Subject: [PATCH 1752/2070] drm/amdgpu: Fix mutex handling in amdgpu_benchmark_do_move() v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_benchmark_do_move() can exit the loop early if amdgpu_copy_buffer() or dma_fence_wait() fails. In the error path, the function jumps to the exit label without releasing adev->mman.default_entity.lock, which leaves the mutex held and results in a lock imbalance. This can block subsequent users of default_entity and potentially cause deadlocks. Move the mutex_unlock() to the common exit path so the lock is released on both success and error returns. This fixes: drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c:57 amdgpu_benchmark_do_move() warn: inconsistent returns '&adev->mman.default_entity.lock'. v2: - Drop unrelated initialization of 'r' - Keep the change focused on the mutex imbalance fix (Pierre). v3: - Removed empty line Fixes: 64c9e5ec16fa ("drm/amdgpu: add missing lock in amdgpu_benchmark_do_move") Reported-by: Dan Carpenter Cc: Pierre-Eric Pelloux-Prayer Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Pierre-Eric Pelloux-Prayer Change-Id: I07f8abae51e0481a28340ede2876b00b69b7523a --- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c index 98ccd7ab9e9a3..6f3c68cde75eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -48,9 +48,9 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, if (r) goto exit_do_move; } - mutex_unlock(&adev->mman.default_entity.lock); exit_do_move: + mutex_unlock(&adev->mman.default_entity.lock); etime = ktime_get(); *time_ms = ktime_ms_delta(etime, stime); From 528af54675da87a9a160f61744cd465c1ca5178e Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 2 Mar 2026 13:35:30 +0800 Subject: [PATCH 1753/2070] drm/amd/pm: Avoid overflow when sorting pp_feature list pp_features sorting uses int8_t sort_feature[] to store driver feature enum indices. On newer ASICs the enum index can exceed 127, causing signed overflow and silently dropping entries from the output. Switch the array to int16_t so all enum indices are preserved. Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 293cb4d06193a..92455b842dfb1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -881,9 +881,9 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, char *buf) { #ifdef MAX - int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; + int16_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; #else - int8_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; + int16_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; #endif struct smu_feature_bits feature_mask; uint32_t features[2]; From 7a1b94a68904362ce440907af1dcf82e63eb9ce0 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 6 Feb 2026 18:51:41 +0530 Subject: [PATCH 1754/2070] drm/gem: Make drm_gem_objects_lookup() self-cleaning on failure v6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drm_gem_objects_lookup() can allocate the output array and take references on GEM objects before it fails. If an error happens part-way through, callers previously had to clean up partially created results themselves. This relied on subtle and undocumented behavior and was easy to get wrong. Make drm_gem_objects_lookup() clean up on failure. The function now drops any references it already took, frees the array, and sets *objs_out to NULL before returning an error. On success, behavior is unchanged. Existing callers remain correct and their error cleanup paths simply do nothing when *objs_out is NULL. v2/v3: Move partial-lookup cleanup into objects_lookup(), perform reference dropping outside the lock, and remove reliance on __GFP_ZERO or implicit NULL handling. (Christian) v4: Use goto-style error handling in objects_lookup(), drop partial references outside the lock, and simplify drm_gem_objects_lookup() cleanup by routing failures through err_free_handles as suggested. (Christian) v5: Rebase on drm-misc-next, drop the ret local variable. (Christian) v6: Drop superfluous initialization of handles. (Christian/Tvrtko) Cc: Alex Deucher Suggested-by: Christian König Suggested-by: Tvrtko Ursulin Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König Reviewed-by: Tvrtko Ursulin Signed-off-by: Arunpravin Paneer Selvam Link: https://patch.msgid.link/20260206132141.1474191-1-srinivasan.shanmugam@amd.com --- drivers/gpu/drm/drm_gem.c | 43 +++++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index ffa7852c8f6c9..3985def993af0 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -783,7 +783,7 @@ EXPORT_SYMBOL(drm_gem_put_pages); static int objects_lookup(struct drm_file *filp, u32 *handle, int count, struct drm_gem_object **objs) { - int i, ret = 0; + int i; struct drm_gem_object *obj; spin_lock(&filp->table_lock); @@ -791,16 +791,23 @@ static int objects_lookup(struct drm_file *filp, u32 *handle, int count, for (i = 0; i < count; i++) { /* Check if we currently have a reference on the object */ obj = idr_find(&filp->object_idr, handle[i]); - if (!obj) { - ret = -ENOENT; - break; - } + if (!obj) + goto err; + drm_gem_object_get(obj); objs[i] = obj; } + spin_unlock(&filp->table_lock); + return 0; - return ret; +err: + spin_unlock(&filp->table_lock); + + while (i--) + drm_gem_object_put(objs[i]); + + return -ENOENT; } /** @@ -828,24 +835,34 @@ int drm_gem_objects_lookup(struct drm_file *filp, void __user *bo_handles, u32 *handles; int ret; + *objs_out = NULL; + if (!count) return 0; - objs = kvmalloc_array(count, sizeof(struct drm_gem_object *), - GFP_KERNEL | __GFP_ZERO); + objs = kvmalloc_array(count, sizeof(*objs), GFP_KERNEL); if (!objs) return -ENOMEM; - *objs_out = objs; - handles = vmemdup_array_user(bo_handles, count, sizeof(u32)); - if (IS_ERR(handles)) - return PTR_ERR(handles); + if (IS_ERR(handles)) { + ret = PTR_ERR(handles); + goto err_free_objs; + } ret = objects_lookup(filp, handles, count, objs); + if (ret) + goto err_free_handles; + kvfree(handles); - return ret; + *objs_out = objs; + return 0; +err_free_handles: + kvfree(handles); +err_free_objs: + kvfree(objs); + return ret; } EXPORT_SYMBOL(drm_gem_objects_lookup); From 8ac2ff64228f3a9e2ff6b509219eea43db9be201 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 3 Mar 2026 21:10:11 -0500 Subject: [PATCH 1755/2070] drm/amd/pm: add missing od setting PP_OD_FEATURE_ZERO_FAN_BIT for smu v13 add missing od setting PP_OD_FEATURE_ZERO_FAN_BIT for smu v13.0.0/13.0.7 Fixes: cfffd980bf21 ("drm/amd/pm: add zero RPM OD setting support for SMU13") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5018 Signed-off-by: Yang Wang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 ++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index e2582c16d5132..fed3b737fecfe 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2223,7 +2223,8 @@ static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu) user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | BIT(PP_OD_FEATURE_UCLK_BIT) | BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table); user_od_table->OverDriveTable.FeatureCtrlMask = 0; if (res == 0) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 4f729f54a64cc..fa23f3d4a3fda 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2225,7 +2225,8 @@ static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu) user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | BIT(PP_OD_FEATURE_UCLK_BIT) | BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table); user_od_table->OverDriveTable.FeatureCtrlMask = 0; if (res == 0) From 3cdccf554a84fe5cfc3e185530900951ed592305 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 4 Mar 2026 14:07:40 -0600 Subject: [PATCH 1756/2070] drm/amd: Fix NULL pointer dereference in device cleanup When GPU initialization fails due to an unsupported HW block IP blocks may have a NULL version pointer. During cleanup in amdgpu_device_fini_hw, the code calls amdgpu_device_set_pg_state and amdgpu_device_set_cg_state which iterate over all IP blocks and access adev->ip_blocks[i].version without NULL checks, leading to a kernel NULL pointer dereference. Add NULL checks for adev->ip_blocks[i].version in both amdgpu_device_set_cg_state and amdgpu_device_set_pg_state to prevent dereferencing NULL pointers during GPU teardown when initialization has failed. Cc: stable@vger.kernel.org Fixes: 39fc2bc4da00 ("drm/amdgpu: Protect GPU register accesses in powergated state in some paths") Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2870ef4cbf45f..184dc9770f285 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2580,6 +2580,8 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev, i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; if (!adev->ip_blocks[i].status.late_initialized) continue; + if (!adev->ip_blocks[i].version) + continue; /* skip CG for GFX, SDMA on S0ix */ if (adev->in_s0ix && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || @@ -2619,6 +2621,8 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev, i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; if (!adev->ip_blocks[i].status.late_initialized) continue; + if (!adev->ip_blocks[i].version) + continue; /* skip PG for GFX, SDMA on S0ix */ if (adev->in_s0ix && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || From d882b4980b86830879ba057c1ac12ba3a338e851 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 3 Mar 2026 21:14:10 -0500 Subject: [PATCH 1757/2070] drm/amd/pm: add missing od setting PP_OD_FEATURE_ZERO_FAN_BIT for smu v14 add missing od setting PP_OD_FEATURE_ZERO_FAN_BIT for smu v14.0.2/14.0.3 Fixes: 9710b84e2a6a ("drm/amd/pm: add overdrive support on smu v14.0.2/3") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5018 Signed-off-by: Yang Wang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index becfd356b4e71..23a143b36fd0d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -2312,7 +2312,8 @@ static int smu_v14_0_2_restore_user_od_settings(struct smu_context *smu) user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | BIT(PP_OD_FEATURE_UCLK_BIT) | BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); res = smu_v14_0_2_upload_overdrive_table(smu, user_od_table); user_od_table->OverDriveTable.FeatureCtrlMask = 0; if (res == 0) From 4fad97b11fa00b7ec5393f51f841954726b02bd8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 10:06:04 -0500 Subject: [PATCH 1758/2070] drm/amdgpu: gfx 12.1 cleanups Remove some remnants from when the code was forked from gfx 12.0. Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 557d15b90ad27..3fd489ea0b79d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -3630,12 +3630,6 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, return -EINVAL; switch (me_id) { - case 0: - if (pipe_id == 0) - amdgpu_fence_process(&adev->gfx.gfx_ring[0]); - else - amdgpu_fence_process(&adev->gfx.gfx_ring[1]); - break; case 1: case 2: for (i = 0; i < adev->gfx.num_compute_rings; i++) { @@ -3652,6 +3646,9 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, amdgpu_fence_process(ring); } break; + default: + dev_dbg(adev->dev, "Unexpected me %d in eop_irq\n", me_id); + break; } } @@ -3720,14 +3717,6 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, return; switch (me_id) { - case 0: - for (i = 0; i < adev->gfx.num_gfx_rings; i++) { - ring = &adev->gfx.gfx_ring[i]; - /* we only enabled 1 gfx queue per pipe for now */ - if (ring->me == me_id && ring->pipe == pipe_id) - drm_sched_fault(&ring->sched); - } - break; case 1: case 2: for (i = 0; i < adev->gfx.num_compute_rings; i++) { @@ -3740,7 +3729,7 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, } break; default: - BUG(); + dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); break; } } From 48bab4888342cb34decf6ac56d1cdeab4d6b4d83 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 5 Mar 2026 09:06:11 -0600 Subject: [PATCH 1759/2070] drm/amd: Fix a few more NULL pointer dereference in device cleanup I found a few more paths that cleanup fails due to a NULL version pointer on unsupported hardware. Add NULL checks as applicable. Fixes: 39fc2bc4da00 ("drm/amdgpu: Protect GPU register accesses in powergated state in some paths") Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 184dc9770f285..a778083998ae2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2830,6 +2830,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) int i, r; for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].version) + continue; if (!adev->ip_blocks[i].version->funcs->early_fini) continue; @@ -2907,6 +2909,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.sw) continue; + if (!adev->ip_blocks[i].version) + continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { amdgpu_ucode_free_bo(adev); amdgpu_free_static_csa(&adev->virt.csa_obj); @@ -2933,6 +2937,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_blocks[i].status.late_initialized) continue; + if (!adev->ip_blocks[i].version) + continue; if (adev->ip_blocks[i].version->funcs->late_fini) adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]); adev->ip_blocks[i].status.late_initialized = false; From 879a212b021059d70bf3fc8bd4a1035e654dbe30 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 14:50:31 -0500 Subject: [PATCH 1760/2070] drm/amdgpu/gfx12.1: add support for disable_kq Plumb in support for disabling kernel queues and make it the default. For testing, kernel queues can be re-enabled by setting amdgpu.user_queue=0 v2: integrate feedback from Lijo Acked-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 90 ++++++++++++++++++++------ 1 file changed, 71 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 3fd489ea0b79d..4e02b62cdbb33 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -1155,11 +1155,13 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) break; } - /* recalculate compute rings to use based on hardware configuration */ - num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * - adev->gfx.mec.num_queue_per_pipe) / 2; - adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, - num_compute_rings); + if (adev->gfx.num_compute_rings) { + /* recalculate compute rings to use based on hardware configuration */ + num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * + adev->gfx.mec.num_queue_per_pipe) / 2; + adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, + num_compute_rings); + } num_xcc = NUM_XCC(adev->gfx.xcc_mask); @@ -2794,6 +2796,33 @@ static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); } +static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, + bool enable) +{ + unsigned int irq_type; + int m, p, r; + + if (adev->gfx.disable_kq) { + for (m = 0; m < adev->gfx.mec.num_mec; ++m) { + for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + + (m * adev->gfx.mec.num_pipe_per_mec) + + p; + if (enable) + r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, + irq_type); + else + r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, + irq_type); + if (r) + return r; + } + } + } + + return 0; +} + static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -2801,6 +2830,7 @@ static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + gfx_v12_1_set_userq_eop_interrupts(adev, false); num_xcc = NUM_XCC(adev->gfx.xcc_mask); for (i = 0; i < num_xcc; i++) { @@ -2868,10 +2898,26 @@ static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + + switch (amdgpu_user_queue) { + case -1: + default: + adev->gfx.disable_kq = true; + adev->gfx.disable_uq = true; + break; + case 0: + adev->gfx.disable_kq = false; + adev->gfx.disable_uq = true; + break; + } + adev->gfx.funcs = &gfx_v12_1_gfx_funcs; - adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), - AMDGPU_MAX_COMPUTE_RINGS); + if (adev->gfx.disable_kq) + adev->gfx.num_compute_rings = 0; + else + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), + AMDGPU_MAX_COMPUTE_RINGS); gfx_v12_1_set_kiq_pm4_funcs(adev); gfx_v12_1_set_ring_funcs(adev); @@ -2898,6 +2944,10 @@ static int gfx_v12_1_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = gfx_v12_1_set_userq_eop_interrupts(adev, true); + if (r) + return r; + return 0; } @@ -3716,21 +3766,23 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, if (xcc_id == -EINVAL) return; - switch (me_id) { - case 1: - case 2: - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring + if (!adev->gfx.disable_kq) { + switch (me_id) { + case 1: + case 2: + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring [i + xcc_id * adev->gfx.num_compute_rings]; - if (ring->me == me_id && ring->pipe == pipe_id && - ring->queue == queue_id) - drm_sched_fault(&ring->sched); + if (ring->me == me_id && ring->pipe == pipe_id && + ring->queue == queue_id) + drm_sched_fault(&ring->sched); + } + break; + default: + dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); + break; } - break; - default: - dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); - break; } } From aad1c0ae786655a2134e4616d450192fbe868e58 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 18 Feb 2026 14:34:28 -0500 Subject: [PATCH 1761/2070] drm/amd/display: Fallback to boot snapshot for dispclk [WHY & HOW] If the dentist is unavailable, fallback to reading CLKIP via the boot snapshot to get the current dispclk. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dillon Varone Signed-off-by: Alex Hung Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 95d9e17a269b3..69cc70106bf07 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -72,7 +72,11 @@ void dcn401_initialize_min_clocks(struct dc *dc) * audio corruption. Read current DISPCLK from DENTIST and request the same * freq to ensure that the timing is valid and unchanged. */ - clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); + if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { + clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); + } else { + clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000; + } } clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; clocks->fclk_p_state_change_support = true; From 4a6e7301968dc8a4370749f1c6d4a67b391f1069 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 18 Feb 2026 16:19:15 -0500 Subject: [PATCH 1762/2070] drm/amd/display: Initialize replay_state to PR_STATE_INVALID [WHY & HOW] Initialize the replay_state variable to PR_STATE_INVALID instead of PR_STATE_0 before retrieving the actual replay state. Reviewed-by: Wenjing Liu Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../drm/amd/display/dc/link/protocols/link_dp_panel_replay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index 7e45d1e767bb1..6661078c0241f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -389,7 +389,7 @@ bool dp_pr_get_state(const struct dc_link *link, uint64_t *state) const struct dc *dc = link->ctx->dc; unsigned int panel_inst = 0; uint32_t retry_count = 0; - uint32_t replay_state = 0; + uint32_t replay_state = PR_STATE_INVALID; if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; From b75143affbd41e07a4f69e52f5f00984cd8687d6 Mon Sep 17 00:00:00 2001 From: Clay King Date: Fri, 20 Feb 2026 11:25:47 -0500 Subject: [PATCH 1763/2070] drm/amd/display: Silence unused variable warning [WHY & HOW] Remove unused dpp_pipe_count variable. Reviewed-by: Austin Zheng Signed-off-by: Clay King Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c index 4cfe64aa84927..74812a7d5e28c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c @@ -909,10 +909,10 @@ static unsigned int get_source_mpc_factor(const struct dml2_context *ctx, const struct dc_plane_state *plane) { struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0}; - int dpp_pipe_count = ctx->config.callbacks.get_dpp_pipes_for_plane(plane, - &state->res_ctx, dpp_pipes); - ASSERT(dpp_pipe_count > 0); + if (ctx->config.callbacks.get_dpp_pipes_for_plane(plane, &state->res_ctx, dpp_pipes) <= 0) + ASSERT(false); + return ctx->config.callbacks.get_mpc_slice_count(dpp_pipes[0]); } From e6d562604adf1dae978838fd13a0d9cb6ee9ec27 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 18 Feb 2026 09:30:32 -0700 Subject: [PATCH 1764/2070] drm/amd/display: Remove redundant initializers [WHAT] Remove unnecessary default value assignments for variables that are unconditionally assigned before use. Linux kernel code style prefers no assignments during initialization when variables are assigned unconditionally as they can obscures the actual data flow. In addition, compilers will be able to catch them if variables are used without being updated later in all conditions. This is reported as UNUSED_VALUE errors by Coverity. Reviewed-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 10 +++++----- .../drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c index 19df8b47248b1..d3cc624cd7588 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c @@ -105,7 +105,7 @@ union dcn42_dpia_host_router_bw { static uint32_t dcn42_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) { - uint32_t res_val = DALSMC_Result_CmdRejectedBusy; + uint32_t res_val; do { res_val = REG_READ(DAL_RESP_REG); @@ -180,7 +180,7 @@ int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr) int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) { - int actual_dispclk_set_mhz = -1; + int actual_dispclk_set_mhz; if (!clk_mgr->smu_present) return requested_dispclk_khz; @@ -199,7 +199,7 @@ int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) { - int actual_dcfclk_set_mhz = -1; + int actual_dcfclk_set_mhz; if (!clk_mgr->smu_present) return requested_dcfclk_khz; @@ -217,7 +217,7 @@ int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) { - int actual_min_ds_dcfclk_mhz = -1; + int actual_min_ds_dcfclk_mhz; if (!clk_mgr->smu_present) return requested_min_ds_dcfclk_khz; @@ -235,7 +235,7 @@ int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) { - int actual_dppclk_set_mhz = -1; + int actual_dppclk_set_mhz; if (!clk_mgr->smu_present) return requested_dpp_khz; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 9f2f4d61d3233..8e41367cf2381 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -1811,8 +1811,8 @@ static bool dcn42_resource_construct( int i, j; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; - uint32_t pipe_fuses = 0; - uint32_t num_pipes = 4; + uint32_t pipe_fuses; + uint32_t num_pipes; #undef REG_STRUCT #define REG_STRUCT bios_regs From b184849c059efe48b123c57a339081ae48c1f04d Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 18 Feb 2026 09:50:15 -0700 Subject: [PATCH 1765/2070] drm/amd/display: Remove always-false branches [WHAT] program_prealpha_dealpha and hpo_frl_stream_enc_acquired are always false and all branches depending on them will never be taken. This is reported as DEADCODE errors by Coverity. Reviewed-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c | 5 ----- drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 6 +----- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c index 244c91b762b06..c126fb9d5bfa9 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c @@ -132,7 +132,6 @@ static void dpp42_dpp_setup( uint32_t alpha_plane_enable = 0; uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; uint32_t realpha_en = 0, realpha_ablnd_en = 0; - uint32_t program_prealpha_dealpha = 0; struct out_csc_color_matrix tbl_entry; int i; @@ -256,10 +255,6 @@ static void dpp42_dpp_setup( CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); - if (program_prealpha_dealpha) { - dealpha_en = 1; - realpha_en = 1; - } REG_SET_2(PRE_DEALPHA, 0, PRE_DEALPHA_EN, dealpha_en, PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index 0d9871f9864b9..f0e1ed0f29499 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -1078,7 +1078,6 @@ void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context) void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { - bool hpo_frl_stream_enc_acquired = false; bool hpo_dp_stream_enc_acquired = false; int i = 0, j = 0; @@ -1172,12 +1171,9 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, } } - if (hpo_frl_stream_enc_acquired || hpo_dp_stream_enc_acquired) + if (hpo_dp_stream_enc_acquired) update_state->pg_res_update[PG_HPO] = true; - if (hpo_frl_stream_enc_acquired) - update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true; - if (count_active_streams(dc) > 0) { update_state->pg_res_update[PG_DCCG] = true; update_state->pg_res_update[PG_DCIO] = true; From c73bdb60a0814f92ae9b893477b09c96fa4da703 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 18 Feb 2026 10:38:33 -0700 Subject: [PATCH 1766/2070] drm/amd/display: Prevent integer overflow when mhz to khz [WHAT] Cast to long long before multiplication to prevent overflow when converting mhz to khz by multiplying by 1000. This is reported as INTEGER_OVERFLOW errors by Coverity. Reviewed-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 14 +++++++------- .../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 12 ++++++------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c index 604d256cb47a6..9d8f81c3d3f05 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c @@ -204,7 +204,7 @@ int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl khz_to_mhz_ceil(requested_dispclk_khz)); smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz); - return actual_dispclk_set_mhz * 1000; + return (int)((long long)actual_dispclk_set_mhz * 1000); } int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) @@ -221,7 +221,7 @@ int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) /* TODO: add code for programing DP DTO, currently this is down by command table */ - return actual_dprefclk_set_mhz * 1000; + return (int)((long long)actual_dprefclk_set_mhz * 1000); } int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) @@ -238,7 +238,7 @@ int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz); - return actual_dcfclk_set_mhz * 1000; + return (int)((long long)actual_dcfclk_set_mhz * 1000); } int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) @@ -255,7 +255,7 @@ int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz); - return actual_min_ds_dcfclk_mhz * 1000; + return (int)((long long)actual_min_ds_dcfclk_mhz * 1000); } int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) @@ -272,7 +272,7 @@ int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz); - return actual_dppclk_set_mhz * 1000; + return (int)((long long)actual_dppclk_set_mhz * 1000); } void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) @@ -424,7 +424,7 @@ int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) 0); smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk); - return dprefclk * 1000; + return (int)((long long)dprefclk * 1000); } int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) @@ -439,7 +439,7 @@ int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) 0); smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); - return dtbclk * 1000; + return (int)((long long)dtbclk * 1000); } /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c index d3cc624cd7588..c791bb1edb47e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c @@ -193,7 +193,7 @@ int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz); - return actual_dispclk_set_mhz * 1000; + return (int)((long long)actual_dispclk_set_mhz * 1000); } @@ -212,7 +212,7 @@ int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz); - return actual_dcfclk_set_mhz * 1000; + return (int)((long long)actual_dcfclk_set_mhz * 1000); } int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) @@ -230,7 +230,7 @@ int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz); - return actual_min_ds_dcfclk_mhz * 1000; + return (int)((long long)actual_min_ds_dcfclk_mhz * 1000); } int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) @@ -248,7 +248,7 @@ int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz); - return actual_dppclk_set_mhz * 1000; + return (int)((long long)actual_dppclk_set_mhz * 1000); } void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) @@ -399,7 +399,7 @@ int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) 0); smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk); - return dprefclk * 1000; + return (int)((long long)dprefclk * 1000); } int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) @@ -414,7 +414,7 @@ int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) 0); smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); - return dtbclk * 1000; + return (int)((long long)dtbclk * 1000); } /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) From 61a8cc51e0be1d7291bd2587b811964067922270 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 20 Feb 2026 17:53:34 -0500 Subject: [PATCH 1767/2070] drm/amd/display: Promote DC to 3.2.372 This version brings along the following updates: - Prevent integer overflow when mhz to khz - Remove always-false branches - Remove redundant initializers - Silence unused variable warning - Initialize replay_state to PR_STATE_INVALID - Fallback to boot snapshot for dispclk - Skip cursor cache reset if hubp powergating is disabled Reviewed-by: Leo Li Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1df45ffe6eb1d..d11126c320465 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.371" +#define DC_VER "3.2.372" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 6ea1943e594051ad4d95d8a340c57737c42db7e7 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sat, 28 Feb 2026 09:59:38 +0000 Subject: [PATCH 1768/2070] drm/amd/display: remove extra ; from statement, remove extra tabs There is a statement that has a ;; at the end, remove the extraneous ; and remove extra tabs in the code block. Signed-off-by: Colin Ian King Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 02ecacfe9b2f9..47f070ff03ee2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1424,9 +1424,9 @@ void dm_helpers_override_panel_settings( link->panel_config.dsc.disable_dsc_edp = true; if (dc_get_edp_link_panel_inst(ctx->dc, link, &panel_inst) && panel_inst == 1) { - link->panel_config.psr.disable_psr = true; - link->panel_config.psr.disallow_psrsu = true;; - link->panel_config.psr.disallow_replay = true; + link->panel_config.psr.disable_psr = true; + link->panel_config.psr.disallow_psrsu = true; + link->panel_config.psr.disallow_replay = true; } } From 3cd63f2f7fc2f79e3c687400299522942b327f88 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Thu, 5 Mar 2026 13:16:36 +0200 Subject: [PATCH 1769/2070] drm/amdgpu: Fix kernel-doc comments for some LUT properties The following members of struct amdgpu_mode_info do not have valid references in the related kernel-doc sections: - plane_shaper_lut_property - plane_shaper_lut_size_property, - plane_lut3d_size_property Correct all affected comment blocks. Fixes: f545d82479b4 ("drm/amd/display: add plane shaper LUT and TF driver-specific properties") Fixes: 671994e3bf33 ("drm/amd/display: add plane 3D LUT driver-specific properties") Reviewed-by: Melissa Wen Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index de572e3a90ebc..7b59c0be8a405 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -368,15 +368,15 @@ struct amdgpu_mode_info { struct drm_property *plane_ctm_property; /** - * @shaper_lut_property: Plane property to set pre-blending shaper LUT - * that converts color content before 3D LUT. If - * plane_shaper_tf_property != Identity TF, AMD color module will + * @plane_shaper_lut_property: Plane property to set pre-blending + * shaper LUT that converts color content before 3D LUT. + * If plane_shaper_tf_property != Identity TF, AMD color module will * combine the user LUT values with pre-defined TF into the LUT * parameters to be programmed. */ struct drm_property *plane_shaper_lut_property; /** - * @shaper_lut_size_property: Plane property for the size of + * @plane_shaper_lut_size_property: Plane property for the size of * pre-blending shaper LUT as supported by the driver (read-only). */ struct drm_property *plane_shaper_lut_size_property; @@ -400,10 +400,10 @@ struct amdgpu_mode_info { */ struct drm_property *plane_lut3d_property; /** - * @plane_degamma_lut_size_property: Plane property to define the max - * size of 3D LUT as supported by the driver (read-only). The max size - * is the max size of one dimension and, therefore, the max number of - * entries for 3D LUT array is the 3D LUT size cubed; + * @plane_lut3d_size_property: Plane property to define the max size + * of 3D LUT as supported by the driver (read-only). The max size is + * the max size of one dimension and, therefore, the max number of + * entries for 3D LUT array is the 3D LUT size cubed. */ struct drm_property *plane_lut3d_size_property; /** From 75575ad088dadd68d8f56361888d36edcd628024 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 4 Mar 2026 18:45:45 -0500 Subject: [PATCH 1770/2070] drm/amdgpu: fix gpu idle power consumption issue for gfx v12 Older versions of the MES firmware may cause abnormal GPU power consumption. When performing inference tasks on the GPU (e.g., with Ollama using ROCm), the GPU may show abnormal power consumption in idle state and incorrect GPU load information. This issue has been fixed in firmware version 0x8b and newer. Closes: https://github.com/ROCm/ROCm/issues/5706 Signed-off-by: Yang Wang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 5bfa5d1d0b369..023c7345ea548 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -731,6 +731,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) int i; struct amdgpu_device *adev = mes->adev; union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; + uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ? + (mes->sched_version & AMDGPU_MES_VERSION_MASK) : + (mes->kiq_version & AMDGPU_MES_VERSION_MASK); memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); @@ -785,7 +788,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) * handling support, other queue will not use the oversubscribe timer. * handling mode - 0: disabled; 1: basic version; 2: basic+ version */ - mes_set_hw_res_pkt.oversubscription_timer = 50; + mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50; mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; if (amdgpu_mes_log_enable) { From b2228663eb4fc7b3e72156305d708caab2c304b4 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 2 Dec 2025 14:27:24 +0100 Subject: [PATCH 1771/2070] drm/amdgpu: include ip discovery data in devcoredump This is the best way to describe the GPU to a tool loading the devcoredump. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 42 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 3 ++ 3 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index ca71c2948227c..fb66d0d5a0a33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -261,6 +261,8 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, } } + amdgpu_discovery_dump(coredump->adev, &p); + /* IP firmware information */ drm_printf(&p, "\nIP Firmwares\n"); amdgpu_devcoredump_fw_info(coredump->adev, &p); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 9599c8247517d..bccdb2c788520 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1396,6 +1396,48 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) kobject_put(&ip_top->kobj); } +/* devcoredump support */ +void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) +{ + struct ip_discovery_top *ip_top = adev->discovery.ip_top; + struct ip_die_entry *ip_die_entry; + struct list_head *el_die, *el_hw_id, *el_hw_inst; + struct ip_hw_id *hw_id; + struct kset *die_kset; + struct ip_hw_instance *ip_inst; + int i = 0, j; + + die_kset = &ip_top->die_kset; + + drm_printf(p, "\nHW IP Discovery\n"); + spin_lock(&die_kset->list_lock); + list_for_each(el_die, &die_kset->list) { + drm_printf(p, "die %d\n", i++); + ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); + + list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { + hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); + drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); + + list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { + ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); + drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); + drm_printf(p, "\tmajor %d\n", ip_inst->major); + drm_printf(p, "\tminor %d\n", ip_inst->minor); + drm_printf(p, "\trevision %d\n", ip_inst->revision); + drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); + drm_printf(p, "\tnum_base_addresses %d\n", + ip_inst->num_base_addresses); + for (j = 0; j < ip_inst->num_base_addresses; j++) + drm_printf(p, "\tbase_addr[%d] 0x%08X\n", + j, ip_inst->base_addr[j]); + } + } + } + spin_unlock(&die_kset->list_lock); +} + + /* ================================================== */ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index 4ce04486cc319..c8242992c9122 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -30,6 +30,7 @@ #define DISCOVERY_TMR_OFFSET (64 << 10) struct ip_discovery_top; +struct drm_printer; struct amdgpu_discovery_info { struct debugfs_blob_wrapper debugfs_blob; @@ -47,4 +48,6 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, struct amdgpu_gmc_memrange **ranges, int *range_cnt, bool refresh); +void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p); + #endif /* __AMDGPU_DISCOVERY__ */ From 0ce779bf9fdad70e015c5a503f1e45e966fe5c42 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 2 Mar 2026 18:26:55 +0800 Subject: [PATCH 1772/2070] drm/amd/pm: Add aid/xcd/hbm temperatures Add aid, xcd & hbm temperatures to gpu metrics for smu_v13_0_12 v2: Use correct umc control per stack (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/include/kgd_pp_interface.h | 3 ++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 37 ++++++++++++++++++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 13 ++++++- 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 7f7136be4a5c0..e4c0cfd7fde43 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -593,6 +593,9 @@ enum amdgpu_metrics_attr_id { AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HBM, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, AMDGPU_METRICS_ATTR_ID_MAX, }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index f2a6ecb64c032..96a58d43db538 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -49,6 +49,13 @@ #undef pr_info #undef pr_debug +#define hbm_stack_mask_valid(umc_mask) \ + (((umc_mask) & 0x3) == 0x3) + +#define for_each_hbm_stack(stack_idx, umc_mask) \ + for ((stack_idx) = 0; (umc_mask); \ + (umc_mask) >>= 2, (stack_idx)++) \ + #define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \ [smu_feature] = { 1, (smu_13_0_12_feature) } @@ -834,7 +841,7 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, struct smu_v13_0_6_gpu_metrics *gpu_metrics) { struct amdgpu_device *adev = smu->adev; - int ret = 0, xcc_id, inst, i, j; + int ret = 0, xcc_id, inst, i, j, idx; u8 num_jpeg_rings_gpu_metrics; MetricsTable_t *metrics; @@ -849,6 +856,31 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, gpu_metrics->temperature_vrsoc = SMUQ10_ROUND(metrics->MaxVrTemperature); + if (smu_v13_0_6_cap_supported(smu, + SMU_CAP(TEMP_AID_XCD_HBM))) { + if (adev->umc.active_mask) { + u64 mask = adev->umc.active_mask; + int out_idx = 0; + int stack_idx; + + if (unlikely(hweight64(mask) / 2 > SMU_13_0_6_MAX_HBM_STACKS)) { + dev_warn(adev->dev, "Invalid umc mask %lld\n", mask); + } else { + for_each_hbm_stack(stack_idx, mask) { + if (!hbm_stack_mask_valid(mask)) + continue; + gpu_metrics->temperature_hbm[out_idx++] = + metrics->HbmTemperature[stack_idx]; + } + } + } + idx = 0; + for_each_inst(i, adev->aid_mask) { + gpu_metrics->temperature_aid[idx] = metrics->AidTemperature[i]; + idx++; + } + } + gpu_metrics->average_gfx_activity = SMUQ10_ROUND(metrics->SocketGfxBusy); gpu_metrics->average_umc_activity = @@ -964,6 +996,9 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, [i] = SMUQ10_ROUND( metrics->GfxclkBelowHostLimitTotalAcc[inst]); } + if (smu_v13_0_6_cap_supported(smu, + SMU_CAP(TEMP_AID_XCD_HBM))) + gpu_metrics->temperature_xcd[i] = metrics->XcdTemperature[inst]; } gpu_metrics->xgmi_link_width = metrics->XgmiWidth; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index ffb06564f8308..a150fc88902c4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -78,6 +78,7 @@ enum smu_v13_0_6_caps { SMU_CAP(RAS_EEPROM), SMU_CAP(FAST_PPT), SMU_CAP(SYSTEM_POWER_METRICS), + SMU_CAP(TEMP_AID_XCD_HBM), SMU_CAP(ALL), }; @@ -87,6 +88,8 @@ enum smu_v13_0_6_caps { #define SMU_13_0_6_MAX_XCC 8 #define SMU_13_0_6_MAX_VCN 4 #define SMU_13_0_6_MAX_JPEG 40 +#define SMU_13_0_6_MAX_AID 4 +#define SMU_13_0_6_MAX_HBM_STACKS 8 extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); @@ -222,7 +225,15 @@ extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; SMU_13_0_6_MAX_XCC); \ SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ - SMU_13_0_6_MAX_XCC); + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_HBM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hbm, \ + SMU_13_0_6_MAX_HBM_STACKS); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_AID), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_aid, SMU_13_0_6_MAX_AID); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_XCD), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_xcd, SMU_13_0_6_MAX_XCC); \ + DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS); void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, From 87f96b2f1e86919bbf4d12adec299bb9e811a3a5 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 3 Mar 2026 15:11:00 +0800 Subject: [PATCH 1773/2070] drm/amd/pm: Enable aid/xcd/hbm temperature reporting Enable aid/xcd/hbm temperature reporting for smu_v13_0_12 via gpu metrics Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 61df154aac002..4d1ca068fe636 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -380,6 +380,9 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) } else { smu_v13_0_12_tables_fini(smu); } + + if (fw_ver >= 0x04561000) + smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_AID_XCD_HBM)); } static void smu_v13_0_6_init_caps(struct smu_context *smu) From 74c283ec0caec37cde5227c31d6f4f09ad6943ee Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 6 Mar 2026 16:48:02 +0530 Subject: [PATCH 1774/2070] drm/amdgpu: fix warning for potentially insecure string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit linux/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2358:24: warning: format string is not a string literal (potentially insecure) [-Wformat-security] sprintf(ring->name, amdgpu_sw_ring_name(i)); ^~~~~~~~~~~~~~~~~~~~~~ linux/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2358:24: note: treat the string as an argument to avoid this sprintf(ring->name, amdgpu_sw_ring_name(i)); Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 8c4edb863c17b..186bc33f5ffff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2362,7 +2362,7 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { ring = &adev->gfx.sw_gfx_ring[i]; ring->ring_obj = NULL; - sprintf(ring->name, amdgpu_sw_ring_name(i)); + strscpy(ring->name, amdgpu_sw_ring_name(i), sizeof(ring->name)); ring->use_doorbell = true; ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; ring->is_sw_ring = true; From 7bfb37a15a28bc60ffc94b96ba7c3aad2c44a636 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 6 Mar 2026 12:53:30 +0530 Subject: [PATCH 1775/2070] drm/amdkfd: fix the warning for potential insecure string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Below is the warning thrown by the clang compiler: linux/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:588:9: warning: format string is not a string literal (potentially insecure) [-Wformat-security] stats_dir_filename); ^~~~~~~~~~~~~~~~~~ linux/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:588:9: note: treat the string as an argument to avoid this stats_dir_filename); ^ "%s", linux/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:635:18: warning: format string is not a string literal (potentially insecure) [-Wformat-security] p->kobj, counters_dir_filename); ^~~~~~~~~~~~~~~~~~~~~ linux/drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:635:18: note: treat the string as an argument to avoid this p->kobj, counters_dir_filename); ^ "%s", Signed-off-by: Sunil Khatri CC: Philip Yang CC: Felix Kuehling Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index b9d6be1464f1e..2677cbe3d364e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -601,7 +601,7 @@ static void kfd_procfs_add_sysfs_stats(struct kfd_process *p) ret = kobject_init_and_add(pdd->kobj_stats, &procfs_stats_type, p->kobj, - stats_dir_filename); + "%s", stats_dir_filename); if (ret) { pr_warn("Creating KFD proc/stats_%s folder failed", @@ -648,7 +648,7 @@ static void kfd_procfs_add_sysfs_counters(struct kfd_process *p) return; ret = kobject_init_and_add(kobj_counters, &sysfs_counters_type, - p->kobj, counters_dir_filename); + p->kobj, "%s", counters_dir_filename); if (ret) { pr_warn("Creating KFD proc/%s folder failed", counters_dir_filename); From 11837887e2412cd82e1a7b5d91fb2fafb1c57481 Mon Sep 17 00:00:00 2001 From: David Francis Date: Fri, 16 Jan 2026 10:21:15 -0500 Subject: [PATCH 1776/2070] drm/amdgpu: Check for multiplication overflow in checkpoint stack size get_checkpoint_info() in kfd_mqd_manager_v9.c finds 32-bit value ctl_stack_size by multiplying two 32-bit values. This can overflow to a lower value, which could result in copying outside the bounds of a buffer in checkpoint_mqd() in the same file. Put in a check for the overflow, and fail with -EINVAL if detected. v2: use check_mul_overflow() Signed-off-by: David Francis Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 7 +++++-- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 7 +++++-- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 8 +++++++- 6 files changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 2a24e2deedadf..afcd2ac980fa1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2774,7 +2774,7 @@ static int get_wave_state(struct device_queue_manager *dqm, ctl_stack, ctl_stack_used_size, save_area_used_size); } -static void get_queue_checkpoint_info(struct device_queue_manager *dqm, +static int get_queue_checkpoint_info(struct device_queue_manager *dqm, const struct queue *q, u32 *mqd_size, u32 *ctl_stack_size) @@ -2782,6 +2782,7 @@ static void get_queue_checkpoint_info(struct device_queue_manager *dqm, struct mqd_manager *mqd_mgr; enum KFD_MQD_TYPE mqd_type = get_mqd_type_from_queue_type(q->properties.type); + int ret = 0; dqm_lock(dqm); mqd_mgr = dqm->mqd_mgrs[mqd_type]; @@ -2789,9 +2790,11 @@ static void get_queue_checkpoint_info(struct device_queue_manager *dqm, *ctl_stack_size = 0; if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) - mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); + ret = mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); dqm_unlock(dqm); + + return ret; } static int checkpoint_mqd(struct device_queue_manager *dqm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 9e00a840704f9..61fdd8c5ee6db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -192,7 +192,7 @@ struct device_queue_manager_ops { int (*reset_queues)(struct device_queue_manager *dqm, uint16_t pasid); - void (*get_queue_checkpoint_info)(struct device_queue_manager *dqm, + int (*get_queue_checkpoint_info)(struct device_queue_manager *dqm, const struct queue *q, u32 *mqd_size, u32 *ctl_stack_size); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index a2c487b9bacd4..33cd46de954fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -104,7 +104,8 @@ struct mqd_manager { bool (*check_queue_active)(struct queue *q); - void (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, uint32_t *ctl_stack_size); + int (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, + uint32_t *ctl_stack_size); void (*checkpoint_mqd)(struct mqd_manager *mm, void *mqd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 77fcfb549601d..77662ce7d8aae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -442,11 +442,14 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, return 0; } -static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) +static int get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) { struct v9_mqd *m = get_mqd(mqd); - *ctl_stack_size = m->cp_hqd_cntl_stack_size * NUM_XCC(mm->dev->xcc_mask); + if (check_mul_overflow(m->cp_hqd_cntl_stack_size, NUM_XCC(mm->dev->xcc_mask), ctl_stack_size)) + return -EINVAL; + + return 0; } static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 4de4c365d657d..cdc762c30f8a2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -326,10 +326,11 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, return 0; } -static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) +static int get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) { /* Control stack is stored in user mode */ *ctl_stack_size = 0; + return 0; } static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 6fc290608baeb..369f9de4b59df 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -1073,6 +1073,7 @@ int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, uint32_t *ctl_stack_size) { struct process_queue_node *pqn; + int ret; pqn = get_queue_by_qid(pqm, qid); if (!pqn) { @@ -1085,9 +1086,14 @@ int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, return -EOPNOTSUPP; } - pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, + ret = pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, pqn->q, mqd_size, ctl_stack_size); + if (ret) { + pr_debug("amdkfd: Overflow while computing stack size for queue %d\n", qid); + return ret; + } + return 0; } From 0c13619f58016db76712b8618a0c6597a1eaae09 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 4 Mar 2026 00:38:06 +0530 Subject: [PATCH 1777/2070] drm/amdgpu/userq: defer queue publication until create completes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The userq create path publishes queues to global xarrays such as userq_doorbell_xa and userq_xa before creation was fully complete. Later on if create queue fails, teardown could free an already visible queue, opening a UAF race with concurrent queue walkers. Also calling amdgpu_userq_put in such cases complicates the cleanup. Solution is to defer queue publication until create succeeds and no partially initialized queue is exposed. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 70 +++++++++++------------ 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index bf7fcc9e74de5..b3e27adb73e48 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -758,7 +758,6 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) const struct amdgpu_userq_funcs *uq_funcs; struct amdgpu_usermode_queue *queue; struct amdgpu_db_info db_info; - char *queue_name; bool skip_map_queue; u32 qid; uint64_t index; @@ -853,32 +852,6 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) goto unlock; } - /* drop this refcount during queue destroy */ - kref_init(&queue->refcount); - - /* Wait for mode-1 reset to complete */ - down_read(&adev->reset_domain->sem); - r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); - if (r) { - kfree(queue); - up_read(&adev->reset_domain->sem); - goto unlock; - } - - r = xa_alloc(&uq_mgr->userq_xa, &qid, queue, - XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); - if (r) { - drm_file_err(uq_mgr->file, "Failed to allocate a queue id\n"); - amdgpu_userq_fence_driver_free(queue); - xa_erase_irq(&adev->userq_doorbell_xa, index); - uq_funcs->mqd_destroy(queue); - kfree(queue); - r = -ENOMEM; - up_read(&adev->reset_domain->sem); - goto unlock; - } - up_read(&adev->reset_domain->sem); - /* don't map the queue if scheduling is halted */ if (adev->userq_halt_for_enforce_isolation && ((queue->queue_type == AMDGPU_HW_IP_GFX) || @@ -890,30 +863,57 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) r = amdgpu_userq_map_helper(queue); if (r) { drm_file_err(uq_mgr->file, "Failed to map Queue\n"); - xa_erase_irq(&adev->userq_doorbell_xa, index); - xa_erase(&uq_mgr->userq_xa, qid); - amdgpu_userq_fence_driver_free(queue); uq_funcs->mqd_destroy(queue); + amdgpu_userq_fence_driver_free(queue); kfree(queue); goto unlock; } } -#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT - queue_name = kasprintf(GFP_KERNEL, "queue-%d", qid); - if (!queue_name) { + /* drop this refcount during queue destroy */ + kref_init(&queue->refcount); + + /* Wait for mode-1 reset to complete */ + down_read(&adev->reset_domain->sem); + r = xa_alloc(&uq_mgr->userq_xa, &qid, queue, + XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); + if (r) { + if (!skip_map_queue) + amdgpu_userq_unmap_helper(queue); + + uq_funcs->mqd_destroy(queue); + amdgpu_userq_fence_driver_free(queue); + kfree(queue); r = -ENOMEM; + up_read(&adev->reset_domain->sem); goto unlock; } + r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); + if (r) { + xa_erase(&uq_mgr->userq_xa, qid); + if (!skip_map_queue) + amdgpu_userq_unmap_helper(queue); + + uq_funcs->mqd_destroy(queue); + amdgpu_userq_fence_driver_free(queue); + kfree(queue); + up_read(&adev->reset_domain->sem); + goto unlock; + } + up_read(&adev->reset_domain->sem); + +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT #if defined(CONFIG_DEBUG_FS) + char queue_name[32]; + + scnprintf(queue_name, sizeof(queue_name), "queue_%d", qid); /* Queue dentry per client to hold MQD information */ queue->debugfs_queue = debugfs_create_dir(queue_name, filp->debugfs_client); debugfs_create_file("mqd_info", 0444, queue->debugfs_queue, queue, &amdgpu_mqd_info_fops); #endif - amdgpu_userq_init_hang_detect_work(queue); - kfree(queue_name); #endif + amdgpu_userq_init_hang_detect_work(queue); args->out.queue_id = qid; atomic_inc(&uq_mgr->userq_count[queue->queue_type]); From bad0e3fedd3a7c05146b6e870aa6cbcadb10c3f3 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 6 Mar 2026 12:24:29 +0530 Subject: [PATCH 1778/2070] drm/amdgpu/userq: declutter the code with goto MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up the amdgpu_userq_create function clean up in failure condition using goto method. This avoid replication of cleanup for every failure condition. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 40 ++++++++++------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b3e27adb73e48..288327a835f57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -818,17 +818,15 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) amdgpu_userq_input_va_validate(adev, queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || amdgpu_userq_input_va_validate(adev, queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { r = -EINVAL; - kfree(queue); - goto unlock; + goto free_queue; } /* Convert relative doorbell offset into absolute doorbell index */ index = amdgpu_userq_get_doorbell_index(uq_mgr, &db_info, filp); if (index == (uint64_t)-EINVAL) { drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n"); - kfree(queue); r = -EINVAL; - goto unlock; + goto free_queue; } queue->doorbell_index = index; @@ -841,15 +839,13 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) r = amdgpu_userq_fence_driver_alloc(adev, queue); if (r) { drm_file_err(uq_mgr->file, "Failed to alloc fence driver\n"); - goto unlock; + goto free_queue; } r = uq_funcs->mqd_create(queue, &args->in); if (r) { drm_file_err(uq_mgr->file, "Failed to create Queue\n"); - amdgpu_userq_fence_driver_free(queue); - kfree(queue); - goto unlock; + goto clean_fence_driver; } /* don't map the queue if scheduling is halted */ @@ -863,10 +859,8 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) r = amdgpu_userq_map_helper(queue); if (r) { drm_file_err(uq_mgr->file, "Failed to map Queue\n"); - uq_funcs->mqd_destroy(queue); - amdgpu_userq_fence_driver_free(queue); - kfree(queue); - goto unlock; + down_read(&adev->reset_domain->sem); + goto clean_mqd; } } @@ -875,18 +869,15 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) /* Wait for mode-1 reset to complete */ down_read(&adev->reset_domain->sem); + r = xa_alloc(&uq_mgr->userq_xa, &qid, queue, XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); if (r) { if (!skip_map_queue) amdgpu_userq_unmap_helper(queue); - uq_funcs->mqd_destroy(queue); - amdgpu_userq_fence_driver_free(queue); - kfree(queue); r = -ENOMEM; - up_read(&adev->reset_domain->sem); - goto unlock; + goto clean_mqd; } r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); @@ -895,11 +886,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) if (!skip_map_queue) amdgpu_userq_unmap_helper(queue); - uq_funcs->mqd_destroy(queue); - amdgpu_userq_fence_driver_free(queue); - kfree(queue); - up_read(&adev->reset_domain->sem); - goto unlock; + goto clean_mqd; } up_read(&adev->reset_domain->sem); @@ -917,7 +904,16 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) args->out.queue_id = qid; atomic_inc(&uq_mgr->userq_count[queue->queue_type]); + mutex_unlock(&uq_mgr->userq_mutex); + return 0; +clean_mqd: + uq_funcs->mqd_destroy(queue); + up_read(&adev->reset_domain->sem); +clean_fence_driver: + amdgpu_userq_fence_driver_free(queue); +free_queue: + kfree(queue); unlock: mutex_unlock(&uq_mgr->userq_mutex); From 24e1b69bcaddce0822c5c1d9f8022fc7eb298114 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 10:53:40 +0800 Subject: [PATCH 1779/2070] drm/amdkcl: fake drm_fb_helper_gem_is_fb() It's cauesd by the commit: 2fa95f4681 "drm/amdgpu: Move test for fbdev GEM object into generic helper" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 19 +++++++++++++++++++ .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 47 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 11e5390896f68..4dfc0efcc5e30 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #ifndef HAVE_DRM_FB_HELPER_FILL_INFO @@ -53,3 +54,21 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); #endif + +#ifndef HAVE_DRM_FB_HELPER_GEM_IS_FB +bool kcl_drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj) +{ + const struct drm_gem_object *gem = NULL; + + if (!fb_helper || !obj) + return false; + if (fb_helper->buffer && fb_helper->buffer->gem) + gem = fb_helper->buffer->gem; + else if (fb_helper->fb) + gem = drm_gem_fb_get_obj(fb_helper->fb, 0); + + return gem == obj; +} +EXPORT_SYMBOL_GPL(kcl_drm_fb_helper_gem_is_fb); +#endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 8c75bfc4e993b..5212937b89d88 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -41,4 +41,10 @@ void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif +#ifndef HAVE_DRM_FB_HELPER_GEM_IS_FB +bool kcl_drm_fb_helper_gem_is_fb(struct drm_fb_helper *fb_helper, + struct drm_gem_object *obj); +#define drm_fb_helper_gem_is_fb kcl_drm_fb_helper_gem_is_fb +#endif + #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0803565edd505..b1db941a8d696 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -601,6 +601,9 @@ /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 +/* drm_fb_helper_gem_is_fb is available */ +#define HAVE_DRM_FB_HELPER_GEM_IS_FB 1 + /* drm_fb_helper_init() has 2 args */ #define HAVE_DRM_FB_HELPER_INIT_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 new file mode 100644 index 0000000000000..7ce8c4a4c5c0d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit amd-staging-dkms-6.18.10-84-gdeca4d1c0b26 +dnl # drm/amdgpu: Move test for fbdev GEM object into generic helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_GEM_IS_FB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_fb_helper *fb_helper = NULL; + struct drm_gem_object *obj = NULL; + drm_fb_helper_gem_is_fb(fb_helper, obj); + ], [drm_fb_helper_gem_is_fb], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_GEM_IS_FB, 1, + [drm_fb_helper_gem_is_fb is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6093a5f8f7d9d..3cddb1122630c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -68,6 +68,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT + AC_AMDGPU_DRM_FB_HELPER_GEM_IS_FB AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID From 9b7d40f2a5423689aff58a19fb1b3b6e7347c8e3 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 6 Mar 2026 16:45:14 +0530 Subject: [PATCH 1780/2070] drm/amdgpu: push userq debugfs function in amdgpu_debugfs files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Debugfs files for amdgpu are better to be handled in the dedicated amdgpu_debugfs.c/.h files. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 55 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 51 +------------------ 3 files changed, 61 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index b22ed547a563e..8567d1762b786 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -39,6 +39,7 @@ #include "amdgpu_reset.h" #include "amdgpu_psp_ta.h" +#include "amdgpu_userq.h" #if defined(CONFIG_DEBUG_FS) @@ -2160,6 +2161,55 @@ static const struct file_operations amdgpu_pt_info_fops = { .release = single_release, }; +static int amdgpu_mqd_info_read(struct seq_file *m, void *unused) +{ + struct amdgpu_usermode_queue *queue = m->private; + struct amdgpu_bo *bo; + int r; + + if (!queue || !queue->mqd.obj) + return -EINVAL; + + bo = amdgpu_bo_ref(queue->mqd.obj); + r = amdgpu_bo_reserve(bo, true); + if (r) { + amdgpu_bo_unref(&bo); + return -EINVAL; + } + + seq_printf(m, "queue_type: %d\n", queue->queue_type); + seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue->mqd.obj)); + + amdgpu_bo_unreserve(bo); + amdgpu_bo_unref(&bo); + + return 0; +} + +static int amdgpu_mqd_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, amdgpu_mqd_info_read, inode->i_private); +} + +static const struct file_operations amdgpu_mqd_info_fops = { + .owner = THIS_MODULE, + .open = amdgpu_mqd_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +void amdgpu_debugfs_userq_init(struct drm_file *file, struct amdgpu_usermode_queue *queue, int qid) +{ +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT + char queue_name[32]; + + scnprintf(queue_name, sizeof(queue_name), "queue_%d", qid); + queue->debugfs_queue = debugfs_create_dir(queue_name, file->debugfs_client); + debugfs_create_file("mqd_info", 0444, queue->debugfs_queue, queue, &amdgpu_mqd_info_fops); +#endif +} + void amdgpu_debugfs_vm_init(struct drm_file *file) { #ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT @@ -2180,4 +2230,9 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) void amdgpu_debugfs_vm_init(struct drm_file *file) { } +void amdgpu_debugfs_userq_init(struct drm_file *file, + struct amdgpu_usermode_queue *queue, + int qid) +{ +} #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index aabfabbd5e3e5..e88b4a1e564c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,6 +25,8 @@ /* * Debugfs */ +struct amdgpu_usermode_queue; + int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); @@ -33,4 +35,7 @@ void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); void amdgpu_debugfs_gem_init(struct amdgpu_device *adev); void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev); void amdgpu_debugfs_vm_init(struct drm_file *file); +void amdgpu_debugfs_userq_init(struct drm_file *file, + struct amdgpu_usermode_queue *queue, + int qid); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 288327a835f57..c058e629cbd92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -709,46 +709,6 @@ static int amdgpu_userq_priority_permit(struct drm_file *filp, return -EACCES; } -#if defined(CONFIG_DEBUG_FS) -static int amdgpu_mqd_info_read(struct seq_file *m, void *unused) -{ - struct amdgpu_usermode_queue *queue = m->private; - struct amdgpu_bo *bo; - int r; - - if (!queue || !queue->mqd.obj) - return -EINVAL; - - bo = amdgpu_bo_ref(queue->mqd.obj); - r = amdgpu_bo_reserve(bo, true); - if (r) { - amdgpu_bo_unref(&bo); - return -EINVAL; - } - - seq_printf(m, "queue_type: %d\n", queue->queue_type); - seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue->mqd.obj)); - - amdgpu_bo_unreserve(bo); - amdgpu_bo_unref(&bo); - - return 0; -} - -static int amdgpu_mqd_info_open(struct inode *inode, struct file *file) -{ - return single_open(file, amdgpu_mqd_info_read, inode->i_private); -} - -static const struct file_operations amdgpu_mqd_info_fops = { - .owner = THIS_MODULE, - .open = amdgpu_mqd_info_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - static int amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) { @@ -890,16 +850,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } up_read(&adev->reset_domain->sem); -#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT -#if defined(CONFIG_DEBUG_FS) - char queue_name[32]; - - scnprintf(queue_name, sizeof(queue_name), "queue_%d", qid); - /* Queue dentry per client to hold MQD information */ - queue->debugfs_queue = debugfs_create_dir(queue_name, filp->debugfs_client); - debugfs_create_file("mqd_info", 0444, queue->debugfs_queue, queue, &amdgpu_mqd_info_fops); -#endif -#endif + amdgpu_debugfs_userq_init(filp, queue, qid); amdgpu_userq_init_hang_detect_work(queue); args->out.queue_id = qid; From 354f555b48ffae612f3229686c4eee69988a1494 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Wed, 4 Mar 2026 13:58:38 +0100 Subject: [PATCH 1781/2070] drm/amdgpu: Move test for fbdev GEM object into generic helper Provide a generic helper that tests if fbdev emulation is backed by a specific GEM object. Not all drivers use client buffers (yet), hence also test against the first GEM object in the fbdev framebuffer. Convert amdgpu. The helper will also be useful for radeon. Reviewed-by: Alex Deucher Signed-off-by: Thomas Zimmermann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 22 +++------------- drivers/gpu/drm/drm_fb_helper.c | 29 +++++++++++++++++++++ include/drm/drm_fb_helper.h | 8 ++++++ 3 files changed, 40 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index f847a0fda8634..bfc0d42fdce08 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1817,21 +1817,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } -static bool -amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_fb_helper *fb_helper = dev->fb_helper; - - if (!fb_helper || !fb_helper->buffer) - return false; - - if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj) - return false; - - return true; -} - int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); @@ -1854,7 +1839,6 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_framebuffer *fb = crtc->primary->fb; - struct amdgpu_bo *robj; if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); @@ -1866,12 +1850,12 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) } } - if (!fb || !drm_gem_fb_get_obj(fb, 0)) + if (!fb || !fb->obj[0]) continue; - robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); + if (!drm_fb_helper_gem_is_fb(dev->fb_helper, fb->obj[0])) { + struct amdgpu_bo *robj = gem_to_amdgpu_bo(fb->obj[0]); - if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { amdgpu_bo_unpin(robj); diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 05803169bed57..e5321b2896d96 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -1786,3 +1787,31 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper) return 0; } EXPORT_SYMBOL(drm_fb_helper_hotplug_event); + +/** + * drm_fb_helper_gem_is_fb - Tests if GEM object is framebuffer + * @fb_helper: fb_helper instance, can be NULL + * @obj: The GEM object to test, can be NULL + * + * Call drm_fb_helper_gem_is_fb to test is a DRM device's fbdev emulation + * uses the specified GEM object for its framebuffer. The result is always + * false if either poiner is NULL. + * + * Returns: + * True if fbdev emulation uses the provided GEM object, or false otherwise. + */ +bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj) +{ + const struct drm_gem_object *gem = NULL; + + if (!fb_helper || !obj) + return false; + if (fb_helper->buffer && fb_helper->buffer->gem) + gem = fb_helper->buffer->gem; + else if (fb_helper->fb) + gem = drm_gem_fb_get_obj(fb_helper->fb, 0); + + return gem == obj; +} +EXPORT_SYMBOL_GPL(drm_fb_helper_gem_is_fb); diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h index 05cca77b7249c..ca214b5c02833 100644 --- a/include/drm/drm_fb_helper.h +++ b/include/drm/drm_fb_helper.h @@ -271,7 +271,15 @@ int drm_fb_helper_ioctl(struct fb_info *info, unsigned int cmd, int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper); int drm_fb_helper_initial_config(struct drm_fb_helper *fb_helper); +bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj); #else +static inline bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj) +{ + return false; +} + static inline void drm_fb_helper_prepare(struct drm_device *dev, struct drm_fb_helper *helper, unsigned int preferred_bpp, From 87d8d919269dacdde6a451acb35e278486922b4c Mon Sep 17 00:00:00 2001 From: Joshua Peisach Date: Tue, 3 Mar 2026 16:18:22 -0500 Subject: [PATCH 1782/2070] drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid Some amdgpu code is still using deprecated edid functions. Switch to the newer functions and update the amdgpu_connector struct's edid type to the drm_edid type. At the same time, use the raw EDID when we need to for speaker allocations and for determining if the input is digital. Signed-off-by: Joshua Peisach Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 32 +++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +-- 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index a7c78899fd0f3..bb5b0ddca5722 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -280,10 +280,10 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, return NULL; } -static struct edid * +static const struct drm_edid * amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) { - return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); + return drm_edid_dup(adev->mode_info.bios_hardcoded_edid); } static void amdgpu_connector_get_edid(struct drm_connector *connector) @@ -302,8 +302,8 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != ENCODER_OBJECT_ID_NONE) && amdgpu_connector->ddc_bus->has_aux) { - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->aux.ddc); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->aux.ddc); } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; @@ -311,14 +311,14 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && amdgpu_connector->ddc_bus->has_aux) - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->aux.ddc); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->aux.ddc); else if (amdgpu_connector->ddc_bus) - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->adapter); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->adapter); } else if (amdgpu_connector->ddc_bus) { - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->adapter); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->adapter); } if (!amdgpu_connector->edid) { @@ -326,7 +326,7 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); - drm_connector_update_edid_property(connector, amdgpu_connector->edid); + drm_edid_connector_update(connector, amdgpu_connector->edid); } } } @@ -345,11 +345,11 @@ static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) int ret; if (amdgpu_connector->edid) { - drm_connector_update_edid_property(connector, amdgpu_connector->edid); - ret = drm_add_edid_modes(connector, amdgpu_connector->edid); + drm_edid_connector_update(connector, amdgpu_connector->edid); + ret = drm_edid_connector_add_modes(connector); return ret; } - drm_connector_update_edid_property(connector, NULL); + drm_edid_connector_update(connector, NULL); return 0; } @@ -932,7 +932,7 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) ret = connector_status_connected; } else { amdgpu_connector->use_digital = - !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + drm_edid_is_digital(amdgpu_connector->edid); /* some oems have boards with separate digital and analog connectors * with a shared ddc line (often vga + hdmi) @@ -1112,7 +1112,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) broken_edid = true; /* defer use_digital to later */ } else { amdgpu_connector->use_digital = - !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + drm_edid_is_digital(amdgpu_connector->edid); /* some oems have boards with separate digital and analog connectors * with a shared ddc line (often vga + hdmi) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 7b59c0be8a405..c899c647cc7f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -624,7 +624,7 @@ struct amdgpu_connector { bool use_digital; /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ - struct edid *edid; + const struct drm_edid *edid; void *con_priv; bool dac_load_detect; bool detected_by_load; /* if the connection status was determined by load */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 63e2cdfd74455..e3437219efedb 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1298,7 +1298,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder return; } - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); + sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); if (sad_count < 0) { DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); sad_count = 0; @@ -1368,7 +1368,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); + sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); if (sad_count < 0) DRM_ERROR("Couldn't read SADs: %d\n", sad_count); if (sad_count <= 0) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 6fd625c3904bf..89155beadcd11 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1265,7 +1265,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); + sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); if (sad_count < 0) { DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); sad_count = 0; @@ -1346,7 +1346,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); + sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); if (sad_count < 0) DRM_ERROR("Couldn't read SADs: %d\n", sad_count); if (sad_count <= 0) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 8d77476abf380..3ed41cec58e56 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1271,7 +1271,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); + sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); if (sad_count < 0) { DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); sad_count = 0; @@ -1339,7 +1339,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); + sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); if (sad_count < 0) DRM_ERROR("Couldn't read SADs: %d\n", sad_count); if (sad_count <= 0) From 9aab5921960310cce757e0b16db3ab5f605cc8c3 Mon Sep 17 00:00:00 2001 From: Joshua Peisach Date: Tue, 3 Mar 2026 16:18:23 -0500 Subject: [PATCH 1783/2070] drm/amdgpu/amdgpu_connectors: remove amdgpu_connector_free_edid Now that we are using struct drm_edid, we can just call drm_edid_free directly. Remove the function and update calls to drm_edid_free. Signed-off-by: Joshua Peisach Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 22 ++++++------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index bb5b0ddca5722..ed2946ad41949 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -331,14 +331,6 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) } } -static void amdgpu_connector_free_edid(struct drm_connector *connector) -{ - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - - kfree(amdgpu_connector->edid); - amdgpu_connector->edid = NULL; -} - static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -799,7 +791,7 @@ static void amdgpu_connector_destroy(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); kfree(amdgpu_connector->con_priv); drm_connector_unregister(connector); drm_connector_cleanup(connector); @@ -922,7 +914,7 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) dret = amdgpu_display_ddc_probe(amdgpu_connector, false); if (dret) { amdgpu_connector->detected_by_load = false; - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); amdgpu_connector_get_edid(connector); if (!amdgpu_connector->edid) { @@ -938,7 +930,7 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) * with a shared ddc line (often vga + hdmi) */ if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); ret = connector_status_disconnected; } else { ret = connector_status_connected; @@ -1033,7 +1025,7 @@ static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, /* hpd is our only option in this case */ if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); *status = connector_status_disconnected; } } @@ -1102,7 +1094,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) } if (dret) { amdgpu_connector->detected_by_load = false; - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); amdgpu_connector_get_edid(connector); if (!amdgpu_connector->edid) { @@ -1118,7 +1110,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) * with a shared ddc line (often vga + hdmi) */ if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); ret = connector_status_disconnected; } else { ret = connector_status_connected; @@ -1506,7 +1498,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) goto out; } - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { From 1f494bfc466b8ac2ac9a043a39d318b9542b534f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 10:54:11 +0800 Subject: [PATCH 1784/2070] drm/amdkcl: fake drm_edid_is_digital() It's caused by the commit: 69086dae8 "drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_edid.h | 14 +++++++++++++- 4 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b1db941a8d696..5c865ad58fe31 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -583,6 +583,9 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_is_digital is available */ +#define HAVE_DRM_EDID_IS_DIGITAL 1 + /* drm_edid_alloc() is available */ #define HAVE_DRM_EDID_MALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 new file mode 100644 index 0000000000000..38fb48bab685e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.5-rc2-869-g7218779efc46 +dnl # drm/edid: add drm_edid_is_digital() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_IS_DIGITAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct drm_edid *drm_edid = NULL; + drm_edid_is_digital(drm_edid); + ], [ + AC_DEFINE(HAVE_DRM_EDID_IS_DIGITAL, 1, + [drm_edid_is_digital is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3cddb1122630c..057d4bf809952 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,6 +72,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID + AC_AMDGPU_DRM_EDID_IS_DIGITAL AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE AC_AMDGPU_DRM_PANEL_BACKLIGHT_QUIRK diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index b992c2f76a6c5..d19f61d8db3b5 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -25,7 +25,8 @@ /* commit v5.18-rc5-1046-ge4ccf9a777d3 drm/edid: add struct drm_edid container */ -#if !defined(HAVE_DRM_EDID_MALLOC) || !defined(HAVE_DRM_EDID_RAW) || !defined(HAVE_DRM_EDID_VALID) +#if !defined(HAVE_DRM_EDID_MALLOC) || !defined(HAVE_DRM_EDID_RAW) || !defined(HAVE_DRM_EDID_VALID) \ + || !defined(HAVE_DRM_EDID_IS_DIGITAL) struct drm_edid { /* Size allocated for edid */ size_t size; @@ -56,4 +57,15 @@ static inline bool _kcl_drm_edid_valid(const struct drm_edid *drm_edid) #define drm_edid_valid _kcl_drm_edid_valid #endif +#ifndef HAVE_DRM_EDID_IS_DIGITAL +static inline bool kcl_drm_edid_is_digital(const struct drm_edid *drm_edid) +{ + if (!drm_edid || !drm_edid->edid) + return false; + + return drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; +} +#define drm_edid_is_digital kcl_drm_edid_is_digital +#endif + #endif From e1fe4811755488d15c60b8e0a12f9d0f0fd83939 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 13:27:19 +0800 Subject: [PATCH 1785/2070] drm/amdkcl: use struct drm_edid instead of struct edid on non-upstream code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's caused by the commit: 69086dae8 "drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid“ Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index ed2946ad41949..05e71af1c78c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -112,7 +112,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; @@ -124,7 +124,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; @@ -137,7 +137,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector->display_info.is_hdmi) { #else - drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; @@ -165,7 +165,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif /* * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make @@ -1311,7 +1311,7 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) #endif max_digital_pixel_clock_khz = max_hdmi_pixel_clock; @@ -1620,7 +1620,7 @@ static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index bfc0d42fdce08..8d084842a2a75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1612,7 +1612,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector && connector->display_info.is_hdmi && #else - drm_detect_hdmi_monitor(to_amdgpu_connector(connector)->edid) && + drm_detect_hdmi_monitor(drm_edid_raw(to_amdgpu_connector(connector)->edid)) && #endif amdgpu_display_is_hdtv_mode(mode)))) { if (amdgpu_encoder->underscan_hborder != 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index dbd12456ff5fa..173adcbb5eee0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -225,7 +225,7 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif if (pixel_clock > 340000) return true; @@ -251,7 +251,7 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { #else - if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { #endif if (pixel_clock > 340000) return true; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index e7b65e7fc55c1..d966cf0d5b283 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -475,7 +475,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && #else - else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && + else if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid)) && #endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; @@ -498,7 +498,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && #else - else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && + else if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid)) && #endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; @@ -520,7 +520,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && #else - else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && + else if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid)) && #endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; From ead7e0d6aaf848ef3cdb943188f0ef34148bd1e2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 14:25:39 +0800 Subject: [PATCH 1786/2070] drm/amdkcl: fake drm_edid_dup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's caused by the commit: 69086dae8 "drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid“ Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 9 +++++++++ include/kcl/kcl_drm_edid.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c index c5272121a0ab4..3028d7cda7641 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -53,6 +53,15 @@ void _kcl_drm_edid_free(const struct drm_edid *drm_edid) kfree(drm_edid); } EXPORT_SYMBOL(_kcl_drm_edid_free); + +const struct drm_edid *kcl_drm_edid_dup(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return NULL; + return _kcl_drm_edid_alloc(drm_edid->edid, drm_edid->size); +} +EXPORT_SYMBOL(kcl_drm_edid_dup); + #endif #ifndef HAVE_DRM_EDID_RAW diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index d19f61d8db3b5..dbaeeb8949a79 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -36,8 +36,10 @@ struct drm_edid { #ifndef HAVE_DRM_EDID_MALLOC const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size); +const struct drm_edid *kcl_drm_edid_dup(const struct drm_edid *drm_edid); void _kcl_drm_edid_free(const struct drm_edid *drm_edid); #define drm_edid_alloc _kcl_drm_edid_alloc +#define drm_edid_dup kcl_drm_edid_dup #define drm_edid_free _kcl_drm_edid_free #endif From 1a529ecfd5d71ff60c91e7def8a63379014ef1bf Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 15:37:41 +0800 Subject: [PATCH 1787/2070] drm/amdkcl: fake drm_edid_connector_add_modes() It's caused by the commit: 69086dae8 "drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_edid_connector_add_modes.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_edid.h | 5 +++++ 5 files changed, 42 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c index 3028d7cda7641..f0a852a459a3b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -7,6 +7,8 @@ */ #include #include +#include +#include #ifndef HAVE_DRM_EDID_MALLOC static const struct drm_edid *__kcl_drm_edid_alloc(const void *edid, size_t size) @@ -102,3 +104,18 @@ const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid) EXPORT_SYMBOL(_kcl_drm_edid_raw); #endif +#ifndef HAVE_DRM_EDID_CONNECTOR_ADD_MODES +int kcl_drm_edid_connector_add_modes(struct drm_connector *connector) +{ + struct edid *edid = NULL; + + if (connector->edid_blob_ptr) + edid = (struct edid *)connector->edid_blob_ptr->data; + + if (edid) + return drm_add_edid_modes(connector, edid); + + return 0; +} +EXPORT_SYMBOL(kcl_drm_edid_connector_add_modes); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5c865ad58fe31..812357a10cb7f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -583,6 +583,9 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_connector_add_modes is available */ +#define HAVE_DRM_EDID_CONNECTOR_ADD_MODES 1 + /* drm_edid_is_digital is available */ #define HAVE_DRM_EDID_IS_DIGITAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 new file mode 100644 index 0000000000000..efad63d148bcc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc2-707-gc533b5167c7e +dnl # drm/edid: add separate drm_edid_connector_add_modes() +dnl # +AC_DEFUN([AC_DRM_EDID_CONNECTOR_ADD_MODES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_connector_add_modes(NULL); + ], [drm_edid_connector_add_modes], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_CONNECTOR_ADD_MODES, 1, + [drm_edid_connector_add_modes is available]) + ]), + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 057d4bf809952..941cf232592a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -290,6 +290,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KFD_PEERDIRECT_SUPPORT AC_AMDGPU_SYSTEM_PERCPU_WQ AC_AMDGPU_PCI_DEV_IS_DISCONNECTED + AC_DRM_EDID_CONNECTOR_ADD_MODES AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index dbaeeb8949a79..66bb50cfffaa0 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -70,4 +70,9 @@ static inline bool kcl_drm_edid_is_digital(const struct drm_edid *drm_edid) #define drm_edid_is_digital kcl_drm_edid_is_digital #endif +#ifndef HAVE_DRM_EDID_CONNECTOR_ADD_MODES +int kcl_drm_edid_connector_add_modes(struct drm_connector *connector); +#define drm_edid_connector_add_modes kcl_drm_edid_connector_add_modes +#endif + #endif From 7bb21d2126a33970ee5b5923aa1d4bc55a90ee52 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 15:43:10 +0800 Subject: [PATCH 1788/2070] drm/amdkcl: fake drm_edid_connector_update() It's caused by the commit: 69086dae8 "drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 10 ++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_edid_connector_update.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_edid.h | 6 ++++++ 5 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c index f0a852a459a3b..6eb0e4a38d4ee 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -104,6 +104,16 @@ const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid) EXPORT_SYMBOL(_kcl_drm_edid_raw); #endif +#ifndef HAVE_DRM_EDID_CONNECTOR_UPDATE +int kcl_drm_edid_connector_update(struct drm_connector *connector, + const struct drm_edid *drm_edid) +{ + const struct edid *edid = _kcl_drm_edid_raw(drm_edid); + return drm_connector_update_edid_property(connector, edid); +} +EXPORT_SYMBOL(kcl_drm_edid_connector_update); +#endif + #ifndef HAVE_DRM_EDID_CONNECTOR_ADD_MODES int kcl_drm_edid_connector_add_modes(struct drm_connector *connector) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 812357a10cb7f..7fd422fef35d9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -586,6 +586,9 @@ /* drm_edid_connector_add_modes is available */ #define HAVE_DRM_EDID_CONNECTOR_ADD_MODES 1 +/* drm_edid_connector_update is available */ +#define HAVE_DRM_EDID_CONNECTOR_UPDATE 1 + /* drm_edid_is_digital is available */ #define HAVE_DRM_EDID_IS_DIGITAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 new file mode 100644 index 0000000000000..f88867def0c7e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.19-rc2-378-gb71c0aaab9ef +dnl # drm/edid: add drm_edid_connector_update() +dnl # +AC_DEFUN([AC_DRM_EDID_CONNECTOR_UPDATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_connector_update(NULL, NULL); + ], [drm_edid_connector_update], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_CONNECTOR_UPDATE, 1, + [drm_edid_connector_update is available]) + ]), + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 941cf232592a7..ae70a7e93f4f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -291,6 +291,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYSTEM_PERCPU_WQ AC_AMDGPU_PCI_DEV_IS_DISCONNECTED AC_DRM_EDID_CONNECTOR_ADD_MODES + AC_DRM_EDID_CONNECTOR_UPDATE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 66bb50cfffaa0..6be2d18c63c20 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -75,4 +75,10 @@ int kcl_drm_edid_connector_add_modes(struct drm_connector *connector); #define drm_edid_connector_add_modes kcl_drm_edid_connector_add_modes #endif +#ifndef HAVE_DRM_EDID_CONNECTOR_UPDATE +int kcl_drm_edid_connector_update(struct drm_connector *connector, + const struct drm_edid *drm_edid); +#define drm_edid_connector_update kcl_drm_edid_connector_update +#endif + #endif From 39331bd1813e6d47223edacd70eebe6632d49198 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 6 Mar 2026 15:49:51 +0800 Subject: [PATCH 1789/2070] drm/amdkcl: fake drm_edid_read_ddc() It's caused by the commit: 69086dae8 "drm/amdgpu/amdgpu_connectors: use struct drm_edid instead of struct edid" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 20 ++++++++++++++++++++ include/kcl/kcl_drm_edid.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c index 6eb0e4a38d4ee..5db1c1e936f38 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -64,6 +64,26 @@ const struct drm_edid *kcl_drm_edid_dup(const struct drm_edid *drm_edid) } EXPORT_SYMBOL(kcl_drm_edid_dup); +const struct drm_edid *kcl_drm_edid_read_ddc(struct drm_connector *connector, + struct i2c_adapter *adapter) +{ + struct edid *edid; + + if (connector->force == DRM_FORCE_OFF) + return NULL; + + if (connector->force == DRM_FORCE_ON && !connector->override_edid) + edid = drm_get_edid(connector, adapter); + else + edid = drm_get_edid(connector, adapter); + + if (!edid) + return NULL; + + return __kcl_drm_edid_alloc(edid, (edid->extensions + 1) * EDID_LENGTH); +} +EXPORT_SYMBOL(kcl_drm_edid_read_ddc); + #endif #ifndef HAVE_DRM_EDID_RAW diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 6be2d18c63c20..e9f3932178304 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -37,9 +37,12 @@ struct drm_edid { #ifndef HAVE_DRM_EDID_MALLOC const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size); const struct drm_edid *kcl_drm_edid_dup(const struct drm_edid *drm_edid); +const struct drm_edid *kcl_drm_edid_read_ddc(struct drm_connector *connector, + struct i2c_adapter *adapter); void _kcl_drm_edid_free(const struct drm_edid *drm_edid); #define drm_edid_alloc _kcl_drm_edid_alloc #define drm_edid_dup kcl_drm_edid_dup +#define drm_edid_read_ddc kcl_drm_edid_read_ddc #define drm_edid_free _kcl_drm_edid_free #endif From dba1ad1936c90dfa9228a6412a7ab4099855fe92 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Mon, 23 Feb 2026 14:56:15 -0500 Subject: [PATCH 1790/2070] drm/amd/display: Clean up NULL pointer warnings in dml2 This commit addresses multiple warnings by adding defensive checks for NULL pointers before dereferencing them. The changes ensure that pointers such as are validated, preventing potential undefined behavior. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../amd/display/dc/dml2_0/dml2_mall_phantom.c | 41 +++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c index 66040c877d68a..d56e58ce26c7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c @@ -357,7 +357,7 @@ static bool enough_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *st */ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *context) { - struct pipe_ctx *subvp_pipes[2]; + struct pipe_ctx *subvp_pipes[2] = { NULL, NULL }; struct dc_stream_state *phantom = NULL; uint32_t microschedule_lines = 0; uint32_t index = 0; @@ -369,6 +369,9 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; uint32_t time_us = 0; + if (pipe == NULL || pipe->stream == NULL) + continue; + /* Loop to calculate the maximum microschedule time between the two SubVP pipes, * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. */ @@ -386,14 +389,19 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c if (time_us > max_microschedule_us) max_microschedule_us = time_us; - subvp_pipes[index] = pipe; - index++; + if (index < 2) + subvp_pipes[index++] = pipe; // Maximum 2 SubVP pipes if (index == 2) break; } } + + /* Minimal guard to avoid C6001 before subvp_pipes[0]/[1] dereference */ + if (index < 2 || !subvp_pipes[0] || !subvp_pipes[1]) + return false; + vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / @@ -459,6 +467,11 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context break; } + if (pipe == NULL || pipe->stream == NULL) { + // Defensive: should never happen, try to catch in debug + ASSERT(0); + return false; + } phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream); main_timing = &pipe->stream->timing; phantom_timing = &phantom_stream->timing; @@ -549,6 +562,13 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state * if (!subvp_pipe && pipe_mall_type == SUBVP_MAIN) subvp_pipe = pipe; } + + if (subvp_pipe == NULL) { + // Defensive: should never happen, catch in debug + ASSERT(0); + return false; + } + // Use ignore_msa_timing_param flag to identify as DRR if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) { // SUBVP + DRR case @@ -753,6 +773,12 @@ static void enable_phantom_plane(struct dml2_context *ctx, return; } + /* Minimal NULL guard for C6011 */ + if (!phantom_plane) { + ASSERT(0); + continue; + } + memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, sizeof(phantom_plane->scaling_quality)); @@ -880,6 +906,11 @@ bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_s if (ctx->config.svp_pstate.force_disable_subvp) return false; + if (!state) { + ASSERT(0); + return false; + } + if (!all_pipes_have_stream_and_plane(ctx, state)) return false; @@ -898,6 +929,10 @@ bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_s } if (enough_pipes_for_subvp(ctx, state) && assign_subvp_pipe(ctx, state, &dc_pipe_idx)) { + if (state->res_ctx.pipe_ctx[dc_pipe_idx].stream == NULL) { + ASSERT(0); + return false; + } dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx, state->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id); svp_height = mode_support_info->SubViewportLinesNeededInMALL[dml_pipe_idx]; vstartup = dml_get_vstartup_calculated(&ctx->v20.dml_core_ctx, dml_pipe_idx); From ec16afd2abc2428c0680320413165b4eb5923ec1 Mon Sep 17 00:00:00 2001 From: Peichen Huang Date: Fri, 6 Feb 2026 15:10:25 +0800 Subject: [PATCH 1791/2070] drm/amd/display: Return early from vesa replay enable function [WHY & HOW] If the enable state is already as expect then just return. Reviewed-by: Robin Chen Reviewed-by: Wenjing Liu Signed-off-by: Peichen Huang Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../dc/link/protocols/link_dp_panel_replay.c | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c index 6661078c0241f..96afce4ffbfa2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -252,23 +252,24 @@ bool dp_pr_enable(struct dc_link *link, bool enable) if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; + if (link->replay_settings.replay_allow_active == enable) + return true; + if (enable && !dc_is_embedded_signal(link->connector_signal)) dp_pr_set_static_screen_param(link); - if (link->replay_settings.replay_allow_active != enable) { - //for sending PR enable commands to DMUB - memset(&cmd, 0, sizeof(cmd)); + // for sending PR enable commands to DMUB + memset(&cmd, 0, sizeof(cmd)); - cmd.pr_enable.header.type = DMUB_CMD__PR; - cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; - cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); - cmd.pr_enable.data.panel_inst = panel_inst; - cmd.pr_enable.data.enable = enable ? 1 : 0; + cmd.pr_enable.header.type = DMUB_CMD__PR; + cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; + cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); + cmd.pr_enable.data.panel_inst = panel_inst; + cmd.pr_enable.data.enable = enable ? 1 : 0; + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); - dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + link->replay_settings.replay_allow_active = enable; - link->replay_settings.replay_allow_active = enable; - } return true; } From 4a58d52076b369dcb2efe59491051a8996f6c07b Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Tue, 10 Feb 2026 15:26:18 -0500 Subject: [PATCH 1792/2070] drm/amd/display: Add min clock init for DML21 mode programming [WHY & HOW] 0 stream cases do not go through any DML validation which leaves DCN clocks in unoptimized states. If requesting DML validation or programming with 0 streams, program DCN clocks to lowest DPM state. Reviewed-by: Dillon Varone Signed-off-by: Ovidiu Bunea Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../dml2_0/dml21/dml21_translation_helper.c | 25 +++++++++++++++++++ .../dml2_0/dml21/dml21_translation_helper.h | 1 + .../display/dc/dml2_0/dml21/dml21_wrapper.c | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index 75a2799979615..cd12b7a6da657 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -931,3 +931,28 @@ void dml21_set_dc_p_state_type( } } +void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context) +{ + unsigned int lowest_dpm_state_index = 0; + struct dc_clocks *min_clocks = &context->bw_ctx.bw.dcn.clk; + + min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->dcfclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dcfclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->dramclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.uclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->fclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.fclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->idle_dramclk_khz = 0; + min_clocks->idle_fclk_khz = 0; + min_clocks->dcfclk_deep_sleep_khz = 0; + min_clocks->fclk_p_state_change_support = true; + min_clocks->p_state_change_support = true; + min_clocks->dtbclk_en = false; + min_clocks->ref_dtbclk_khz = 0; + min_clocks->socclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.socclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->subvp_prefetch_dramclk_khz = 0; + min_clocks->subvp_prefetch_fclk_khz = 0; + min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->stutter_efficiency.base_efficiency = 1; + min_clocks->stutter_efficiency.low_power_efficiency = 1; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h index 9880d3e0398e2..f51d3d8a52c3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h @@ -25,4 +25,5 @@ void dml21_map_hw_resources(struct dml2_context *dml_ctx); void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config); void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled); unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context); +void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c index 798abb2b2e676..96c62bd6a37b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c @@ -215,6 +215,7 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s return true; if (context->stream_count == 0) { + dml21_init_min_clocks_for_dc_state(dml_ctx, context); dml21_build_fams2_programming(in_dc, context, dml_ctx); return true; } From d028391e463571fc7b51ab6a300ed0cab271733f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 16 Jan 2026 09:39:05 -0500 Subject: [PATCH 1793/2070] drm/amd/display: Set chroma taps to 1 if luma taps are 1 When luma is unscaled we also want chroma to be pixel-perfect. When luma taps are > 1 the result will be a blurred luma plane, even when the image isn't scaled. This makes IGT tests for CSC colorop pass. Co-developed by Claude Sonnet 4.5. Reviewed-by: Alex Hung Signed-off-by: Harry Wentland Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c | 8 ++++++-- drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c index ce91e5d289567..0e70ffc784b19 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c @@ -172,10 +172,14 @@ bool dpp1_get_optimal_number_of_taps( scl_data->taps.h_taps_c = in_taps->h_taps_c; if (!dpp->ctx->dc->debug.always_scale) { - if (IDENTITY_RATIO(scl_data->ratios.horz)) + if (IDENTITY_RATIO(scl_data->ratios.horz)) { scl_data->taps.h_taps = 1; - if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.h_taps_c = 1; + } + if (IDENTITY_RATIO(scl_data->ratios.vert)) { scl_data->taps.v_taps = 1; + scl_data->taps.v_taps_c = 1; + } if (IDENTITY_RATIO(scl_data->ratios.horz_c)) scl_data->taps.h_taps_c = 1; if (IDENTITY_RATIO(scl_data->ratios.vert_c)) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index c7923531da83d..8a146968ee156 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -524,10 +524,14 @@ bool dpp3_get_optimal_number_of_taps( scl_data->taps.v_taps_c = max_taps_c; if (!dpp->ctx->dc->debug.always_scale) { - if (IDENTITY_RATIO(scl_data->ratios.horz)) + if (IDENTITY_RATIO(scl_data->ratios.horz)) { scl_data->taps.h_taps = 1; - if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.h_taps_c = 1; + } + if (IDENTITY_RATIO(scl_data->ratios.vert)) { scl_data->taps.v_taps = 1; + scl_data->taps.v_taps_c = 1; + } if (IDENTITY_RATIO(scl_data->ratios.horz_c)) scl_data->taps.h_taps_c = 1; if (IDENTITY_RATIO(scl_data->ratios.vert_c)) From 79e1ff521a119a8840c2d677cb867ff742e9156f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 15 Jan 2026 14:12:05 -0500 Subject: [PATCH 1794/2070] drm/amd/display: Add NV12/P010 formats to primary plane Add NV12, NV21, and P010 YUV formats to the primary plane's supported format list, enabling YUV content to be scanned out directly from the primary plane. Co-developed by Claude Sonnet 4.5. Reviewed-by: Alex Hung Signed-off-by: Harry Wentland Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index b5963a7d43222..fceb0677aa1d9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -64,6 +64,9 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, + DRM_FORMAT_NV21, + DRM_FORMAT_NV12, + DRM_FORMAT_P010 }; static const uint32_t overlay_formats[] = { From 048e6da3cbeda8f3f909c5380fd4f61cbadfb9fa Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 15 Jan 2026 14:12:46 -0500 Subject: [PATCH 1795/2070] drm/amd/display: Add COLOR_ENCODING/COLOR_RANGE to overlay planes Extend COLOR_ENCODING and COLOR_RANGE property creation to overlay planes in addition to primary planes. This allows overlay planes to use YUV formats with proper color space configuration when the hardware supports NV12/P010 formats. These properties control the YUV-to-RGB conversion matrix selection (BT.601/BT.709/BT.2020) and range handling (limited/full range). Co-developed by Claude Sonnet 4.5. Reviewed-by: Alex Hung Signed-off-by: Harry Wentland Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index fceb0677aa1d9..5d60c0a07a003 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1980,7 +1980,8 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_create_zpos_immutable_property(plane, 255); } - if (plane->type == DRM_PLANE_TYPE_PRIMARY && + if ((plane->type == DRM_PLANE_TYPE_PRIMARY || + plane->type == DRM_PLANE_TYPE_OVERLAY) && plane_cap && (plane_cap->pixel_format_support.nv12 || plane_cap->pixel_format_support.p010)) { From 60071224dd91200756cc650fee24d02a0631df93 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 23 Feb 2026 14:28:14 -0500 Subject: [PATCH 1796/2070] drm/amd/display: Update underflow detection [WHY] Add underflow detection for later ASICs. Reviewed-by: Leo Chen Signed-off-by: Charlene Liu Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h | 6 +++++- drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index cf05620fd8f53..d2ba63046a500 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -218,7 +218,7 @@ uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \ uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \ uint32_t OTG_DLPC_CONTROL; \ - uint32_t OTG_DRR_CONTROL2; \ + uint32_t OTG_DRR_CONTOL2; \ uint32_t OTG_DRR_TIMING_INT_STATUS; \ uint32_t OTG_GLOBAL_CONTROL3; \ uint32_t OTG_GLOBAL_SYNC_STATUS; \ @@ -676,6 +676,10 @@ struct dcn_optc_registers { type OTG_V_COUNT_STOP_TIMER; #define TG_REG_FIELD_LIST_DCN3_6(type) \ + type OPTC_RSMU_UNDERFLOW_CLEAR;\ + type OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS;\ + type OPTC_RSMU_UNDERFLOW_INT_EN;\ + type OPTC_RSMU_UNDERFLOW_INT_STATUS;\ type OTG_CRC_POLY_SEL; \ type CRC0_R_CR32; \ type CRC0_G_Y32; \ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index c6417538090f2..893d2aff1f826 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -363,7 +363,7 @@ void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_st optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG); optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL); optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); - optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2); + optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTOL2); optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL); optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS); optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW); From 2cdce3dd5a7aabe41df018481a95127c78cd70a3 Mon Sep 17 00:00:00 2001 From: Weiguang Li Date: Mon, 8 Dec 2025 14:13:20 +0800 Subject: [PATCH 1797/2070] drm/amd/display: Add ESD detection for replay recovery [HOW] Add Replay recovery flow so that when HPD occurs and ESD is detected, Replay can restore the system back to normal. Reviewed-by: Wenjing Liu Reviewed-by: Robin Chen Reviewed-by: Aric Cyr Signed-off-by: Weiguang Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../dc/link/protocols/link_dp_irq_handler.c | 36 +++++++++++++------ .../gpu/drm/amd/display/include/dpcd_defs.h | 3 ++ 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c index cc18a3bebef2b..1860d44f63c1f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c @@ -223,9 +223,10 @@ static void handle_hpd_irq_vesa_replay_sink(struct dc_link *link) } } -static void handle_hpd_irq_replay_sink(struct dc_link *link) +static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable) { union dpcd_replay_configuration replay_configuration = {0}; + union dpcd_replay_configuration replay_sink_status = {0}; /*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR status.*/ union psr_error_status replay_error_status = {0}; bool ret = false; @@ -265,9 +266,17 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link) &replay_error_status.raw, sizeof(replay_error_status.raw)); + dm_helpers_dp_read_dpcd( + link->ctx, + link, + DP_PR_REPLAY_SINK_STATUS, + &replay_sink_status.raw, + 1); + if (replay_error_status.bits.LINK_CRC_ERROR || replay_configuration.bits.DESYNC_ERROR_STATUS || - replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) { + replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS || + replay_sink_status.bits.SINK_DEVICE_REPLAY_STATUS == 0x7) { bool allow_active; link->replay_settings.config.replay_error_status.raw |= replay_error_status.raw; @@ -299,8 +308,7 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link) if (link->replay_settings.replay_allow_active) { allow_active = false; edp_set_replay_allow_active(link, &allow_active, true, false, NULL); - allow_active = true; - edp_set_replay_allow_active(link, &allow_active, true, false, NULL); + *need_re_enable = true; } } } @@ -460,6 +468,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, union device_service_irq device_service_clear = {0}; enum dc_status result; bool status = false; + bool replay_re_enable_needed = false; if (out_link_loss) *out_link_loss = false; @@ -519,7 +528,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, /* PSR-related error was detected and handled */ return true; - handle_hpd_irq_replay_sink(link); + handle_hpd_irq_replay_sink(link, &replay_re_enable_needed); /* If PSR-related error handled, Main link may be off, * so do not handle as a normal sink status change interrupt. @@ -538,16 +547,16 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, return false; } - /* For now we only handle 'Downstream port status' case. + /* Handle 'Downstream port status' case for all DP link types. * If we got sink count changed it means * Downstream port status changed, * then DM should call DC to do the detection. - * NOTE: Do not handle link loss on eDP since it is internal link + * NOTE: Now includes eDP link loss detection and retraining */ - if ((link->connector_signal != SIGNAL_TYPE_EDP) && - dp_parse_link_loss_status( - link, - &hpd_irq_dpcd_data)) { + + if (dp_parse_link_loss_status( + link, + &hpd_irq_dpcd_data)) { /* Connectivity log: link loss */ CONN_DATA_LINK_LOSS(link, hpd_irq_dpcd_data.raw, @@ -576,6 +585,11 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, != link->dpcd_sink_count) status = true; + if (replay_re_enable_needed) { + bool allow_active = true; + + edp_set_replay_allow_active(link, &allow_active, true, false, NULL); + } /* reasons for HPD RX: * 1. Link Loss - ie Re-train the Link * 2. MST sideband message diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index 1afa10e85eb59..4a8ca0ac12666 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -64,6 +64,9 @@ #ifndef DP_PR_ERROR_STATUS // can remove this once the define gets into linux drm_dp_helper.h #define DP_PR_ERROR_STATUS 0x2020 /* DP 2.0 */ #endif /* DP_PR_ERROR_STATUS */ +#ifndef DP_PR_REPLAY_SINK_STATUS // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_REPLAY_SINK_STATUS 0x2022 +#endif /* DP_PR_REPLAY_SINK_STATUS */ #ifndef DP_PR_LINK_CRC_ERROR // can remove this once the define gets into linux drm_dp_helper.h #define DP_PR_LINK_CRC_ERROR (1 << 0) #endif /* DP_PR_LINK_CRC_ERROR */ From 53e08e15eb1dcf8af2bcd416a610d432f5c8f4c2 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Tue, 24 Feb 2026 16:28:00 -0500 Subject: [PATCH 1798/2070] drm/amd/display: Add missing DCCG register entries for DCN20-DCN316 Commit f5472343f468 ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.") moved register writes from hwseq to dccg2_*() functions but did not add the registers to the DCCG register list macros. The struct fields default to 0, so REG_WRITE() targets MMIO offset 0, causing a GPU hang on resume (seen on DCN21/DCN30 during IGT kms_cursor_crc@cursor-suspend). Add - MICROSECOND_TIME_BASE_DIV - MILLISECOND_TIME_BASE_DIV - DCCG_GATE_DISABLE_CNTL - DCCG_GATE_DISABLE_CNTL2 - DC_MEM_GLOBAL_PWR_REQ_CNTL to macros in dcn20_dccg.h, dcn301_dccg.h, dcn31_dccg.h, and dcn314_dccg.h. Fixes: f5472343f468 ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.") Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h | 6 +++++- drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h | 8 +++++++- drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h | 5 ++++- drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h | 5 ++++- 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index ffcd2e139e764..463f5826a1ea1 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -38,7 +38,11 @@ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ SR(DISPCLK_FREQ_CHANGE_CNTL),\ - SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV),\ + SR(MILLISECOND_TIME_BASE_DIV),\ + SR(DCCG_GATE_DISABLE_CNTL),\ + SR(DCCG_GATE_DISABLE_CNTL2) #define DCCG_REG_LIST_DCN2() \ DCCG_COMMON_REG_LIST_DCN_BASE(),\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h index 067e49cb238ec..e2381ca0be0b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h @@ -34,7 +34,13 @@ DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ - SR(REFCLK_CNTL) + SR(REFCLK_CNTL),\ + SR(DISPCLK_FREQ_CHANGE_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV),\ + SR(MILLISECOND_TIME_BASE_DIV),\ + SR(DCCG_GATE_DISABLE_CNTL),\ + SR(DCCG_GATE_DISABLE_CNTL2) #define DCCG_MASK_SH_LIST_DCN301(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h index bf659920d4cc2..b5e3849ef12a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h @@ -64,9 +64,12 @@ SR(DSCCLK1_DTO_PARAM),\ SR(DSCCLK2_DTO_PARAM),\ SR(DSCCLK_DTO_CTRL),\ + SR(DCCG_GATE_DISABLE_CNTL),\ SR(DCCG_GATE_DISABLE_CNTL2),\ SR(DCCG_GATE_DISABLE_CNTL3),\ - SR(HDMISTREAMCLK0_DTO_PARAM) + SR(HDMISTREAMCLK0_DTO_PARAM),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV) #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h index a609635f35dbd..ecbdc05f7c459 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h @@ -70,11 +70,14 @@ SR(DSCCLK2_DTO_PARAM),\ SR(DSCCLK3_DTO_PARAM),\ SR(DSCCLK_DTO_CTRL),\ + SR(DCCG_GATE_DISABLE_CNTL),\ SR(DCCG_GATE_DISABLE_CNTL2),\ SR(DCCG_GATE_DISABLE_CNTL3),\ SR(HDMISTREAMCLK0_DTO_PARAM),\ SR(OTG_PIXEL_RATE_DIV),\ - SR(DTBCLK_P_CNTL) + SR(DTBCLK_P_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV) #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ From d067c909b1e909f65ac631e06d77d8717ed45d7c Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 24 Feb 2026 16:49:46 -0500 Subject: [PATCH 1799/2070] drm/amd/display: Fix HWSS v3 fast path determination [WHY] We're checking surface and stream updates after they've been applied to their respective states within `update_planes_and_stream_state`. Medium updates under the HWSS V3 fast path that are not supported or tested are getting implicitly if they don't trigger a DML validation and getting updated in place on the dc->current_state context. [HOW] Fix this issue by moving up the fast path determination check prior to `update_planes_and_stream_state`. This is how the V2 path works and how the V3 path used to work prior to the refactors in this area. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 38 +++++++++++------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 584cb550928c4..cba35cb70a10a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -7297,6 +7297,23 @@ static bool update_planes_and_stream_prepare_v3( ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID); dc_exit_ips_for_hw_access(scratch->dc); + /* HWSS path determination needs to be done prior to updating the surface and stream states. */ + struct dc_fast_update fast_update[MAX_SURFACES] = { 0 }; + + populate_fast_updates(fast_update, + scratch->surface_updates, + scratch->surface_count, + scratch->stream_update); + + const bool is_hwss_fast_path_only = + fast_update_only(scratch->dc, + fast_update, + scratch->surface_updates, + scratch->surface_count, + scratch->stream_update, + scratch->stream) && + !scratch->dc->check_config.enable_legacy_fast_update; + if (!update_planes_and_stream_state( scratch->dc, scratch->surface_updates, @@ -7312,26 +7329,7 @@ static bool update_planes_and_stream_prepare_v3( if (scratch->new_context == scratch->dc->current_state) { ASSERT(scratch->update_type < UPDATE_TYPE_FULL); - // TODO: Do we need this to be alive in execute? - struct dc_fast_update fast_update[MAX_SURFACES] = { 0 }; - - populate_fast_updates( - fast_update, - scratch->surface_updates, - scratch->surface_count, - scratch->stream_update - ); - const bool fast = fast_update_only( - scratch->dc, - fast_update, - scratch->surface_updates, - scratch->surface_count, - scratch->stream_update, - scratch->stream - ) - // TODO: Can this be used to skip `populate_fast_updates`? - && !scratch->dc->check_config.enable_legacy_fast_update; - scratch->flow = fast + scratch->flow = is_hwss_fast_path_only ? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST : UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL; return true; From 033b26b54a5ddd55e77766c54e832410641c3781 Mon Sep 17 00:00:00 2001 From: ChunTao Tso Date: Fri, 6 Feb 2026 15:41:54 +0800 Subject: [PATCH 1800/2070] drm/amd/display: Add new types to replay config [WHAT] Add FRAME_SKIPPING_ERROR_STATUS to dpcd_replay_configuration. Add received_frame_skipping_error_hpd to replay_config. Add REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE to dmub_cmd_replay_general_subtype. Reviewed-by: Aric Cyr Signed-off-by: ChunTao Tso Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 9540f0ead2794..7fa336bf1115d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1374,7 +1374,7 @@ union dpcd_replay_configuration { unsigned char DESYNC_ERROR_STATUS : 1; unsigned char SINK_DEVICE_REPLAY_STATUS : 3; unsigned char SINK_FRAME_LOCKED : 2; - unsigned char RESERVED : 1; + unsigned char FRAME_SKIPPING_ERROR_STATUS : 1; } bits; unsigned char raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index d2e60480fb2be..d0ae5c27a5113 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1194,6 +1194,8 @@ struct replay_config { union replay_optimization replay_optimization; /* Replay sub feature Frame Skipping is supported */ bool frame_skip_supported; + /* Replay Received Frame Skipping Error HPD. */ + bool received_frame_skipping_error_hpd; }; /* Replay feature flags*/ diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 2abbc6c97850a..f67a0ffb9335a 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4441,6 +4441,7 @@ enum dmub_cmd_replay_general_subtype { REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, + REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, }; struct dmub_alpm_auxless_data { From 499869342a12456f95b7e629f955f790596559ff Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 24 Feb 2026 10:36:29 -0500 Subject: [PATCH 1801/2070] drm/amd/display: Add documentation and cleanup DMUB HW lock manager To document how the helpers should be used before a subsequent change adds new locations that these helpers will be used. Reviewed-by: Ovidiu (Ovi) Bunea Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index 4c80ca8484ad3..9495857902ed5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -46,7 +46,25 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, * Return: true if the inbox1 lock should be used, false otherwise */ bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link); + +/** + * dmub_hw_lock_mgr_does_link_require_lock() - Returns true if the link has a feature that needs the HW lock. + * + * @dc: Pointer to DC object + * @link: The link to check + * + * Return: true if the link has a feature that needs the HW lock, false otherwise + */ bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link); + +/** + * dmub_hw_lock_mgr_does_context_require_lock() - Returns true if the context has any stream that needs the HW lock. + * + * @dc: Pointer to DC object + * @context: The context to check + * + * Return: true if the context has any stream that needs the HW lock, false otherwise + */ bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context); #endif /*_DMUB_HW_LOCK_MGR_H_ */ From e2d9788d20f31fae18669d288ca5e7dca74b3cb0 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 25 Feb 2026 21:48:36 -0500 Subject: [PATCH 1802/2070] drm/amd/display: Check for S0i3 to be done before DCCG init on DCN21 [WHY] On DCN21, dccg2_init() is called in dcn10_init_hw() before bios_golden_init(). During S0i3 resume, BIOS sets MICROSECOND_TIME_BASE_DIV to 0x00120464 as a marker. dccg2_init() overwrites this to 0x00120264, causing dcn21_s0i3_golden_init_wa() to misdetect the state and skip golden init. Eventually during the resume sequence, a flip timeout occurs. [HOW] Skip DCCG on dccg2_is_s0i3_golden_init_wa_done() on DCN21. Fixes: f5472343f468 ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.") Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../amd/display/dc/dccg/dcn21/dcn21_dccg.c | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c index b48dcafbae66a..bdc3ce5d4f473 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c @@ -96,6 +96,25 @@ static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppcl dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; } +/* + * On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to + * 0x00120464 as a marker that golden init has already been done. + * dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init() + * to decide whether to skip golden init. + * + * dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to + * 0x00120264, destroying the marker before it can be read. + * + * Guard the call: if the S0i3 marker is present, skip dccg2_init() so the + * WA can function correctly. bios_golden_init() will handle init in that case. + */ +static void dccg21_init(struct dccg *dccg) +{ + if (dccg2_is_s0i3_golden_init_wa_done(dccg)) + return; + + dccg2_init(dccg); +} static const struct dccg_funcs dccg21_funcs = { .update_dpp_dto = dccg21_update_dpp_dto, @@ -103,7 +122,7 @@ static const struct dccg_funcs dccg21_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init, + .dccg_init = dccg21_init, .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ .allow_clock_gating = dccg2_allow_clock_gating, .enable_memory_low_power = dccg2_enable_memory_low_power, From d8f06cfe17bf73913920ebc0f514401f6f6b7460 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Thu, 26 Feb 2026 11:06:17 -0500 Subject: [PATCH 1803/2070] drm/amd/display: Fix compile warnings in dml2_0 Fix static analysis warnings by ensuring swath size temporaries are initialized before use. No functional change intended. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c index 09303c282495b..8e8935995fca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c @@ -4089,8 +4089,8 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st dml_uint_t MaximumSwathHeightC[__DML_NUM_PLANES__]; dml_uint_t RoundedUpMaxSwathSizeBytesY[__DML_NUM_PLANES__]; dml_uint_t RoundedUpMaxSwathSizeBytesC[__DML_NUM_PLANES__]; - dml_uint_t RoundedUpSwathSizeBytesY[__DML_NUM_PLANES__]; - dml_uint_t RoundedUpSwathSizeBytesC[__DML_NUM_PLANES__]; + dml_uint_t RoundedUpSwathSizeBytesY[__DML_NUM_PLANES__] = { 0 }; + dml_uint_t RoundedUpSwathSizeBytesC[__DML_NUM_PLANES__] = { 0 }; dml_uint_t SwathWidthSingleDPP[__DML_NUM_PLANES__]; dml_uint_t SwathWidthSingleDPPChroma[__DML_NUM_PLANES__]; From b2988a3a13d13c701ac9a067598e3cf96c38c269 Mon Sep 17 00:00:00 2001 From: Tom Chung Date: Thu, 26 Feb 2026 16:16:19 +0800 Subject: [PATCH 1804/2070] drm/amd/display: Add back missing memory type in array [WHY & HOW] Add back some missing memory type in window_memory_type. It should be aligned with enum dmub_window_id. Reviewed-by: Aurabindo Pillai Signed-off-by: Tom Chung Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bd43f391272d8..1950ec6d7edd1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2506,6 +2506,8 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_IB_MEM DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_LSDMA_BUFFER + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_CURSOR_OFFLOAD }; int r; From 2cf98863f19096d8217e663a33ce95edda943115 Mon Sep 17 00:00:00 2001 From: Clay King Date: Fri, 27 Feb 2026 12:34:34 -0500 Subject: [PATCH 1805/2070] drm/amd/display: Clean up unused code [WHAT] Silence warning by cleaning up unused code. Reviewed-by: Dillon Varone Signed-off-by: Clay King Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 1 + .../gpu/drm/amd/display/dc/core/dc_resource.c | 1 - drivers/gpu/drm/amd/display/dc/dc_trace.h | 4 +-- .../display/dc/hubbub/dcn401/dcn401_hubbub.c | 4 --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 24 +++++++------- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 32 +++++++------------ .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 1 - .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 12 +++---- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 9 ------ .../drm/amd/display/dc/link/link_detection.c | 12 +------ .../link/protocols/link_edp_panel_control.c | 2 -- .../drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c | 4 +-- .../dc/resource/dcn20/dcn20_resource.c | 2 -- 13 files changed, 35 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index ef77fcd164ed3..f2a716e1e732a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -547,6 +547,7 @@ void dcn3_clk_mgr_construct( /* in case we don't get a value from the register, use default */ if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 3650000; + /* Convert dprefclk units from MHz to KHz */ /* Value already divided by 10, some resolution lost */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index c9fbb64d706a2..8271b12c1a66d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2431,7 +2431,6 @@ static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state, int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count; bool is_primary; - DC_LOGGER_INIT(dc->ctx->logger); slice_count = resource_get_opp_heads_for_otg_master(otg_master, &state->res_ctx, opp_heads); diff --git a/drivers/gpu/drm/amd/display/dc/dc_trace.h b/drivers/gpu/drm/amd/display/dc/dc_trace.h index bbec308a3a5e2..b7a011646d533 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_trace.h +++ b/drivers/gpu/drm/amd/display/dc/dc_trace.h @@ -23,8 +23,8 @@ #include "amdgpu_dm_trace.h" -#define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \ - for (index = 0; index < max_pipes; ++index) { \ +#define TRACE_DC_PIPE_STATE(pipe_ctx, max_pipes) \ + for (int index = 0; index < max_pipes; ++index) { \ struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \ if (pipe_ctx->plane_state) \ trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index 941dce439e979..b0a4b68cf359a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -1151,8 +1151,6 @@ void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_siz { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - unsigned int cur_compbuf_size_seg = 0; - if (safe_to_increase || compbuf_size_seg <= hubbub2->compbuf_size_segments) { if (compbuf_size_seg > hubbub2->compbuf_size_segments) { REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); @@ -1165,8 +1163,6 @@ void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_siz + hubbub2->det3_size + compbuf_size_seg <= hubbub2->crb_size_segs); REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_seg); hubbub2->compbuf_size_segments = compbuf_size_seg; - - ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &cur_compbuf_size_seg) && !cur_compbuf_size_seg); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 8aafd460c36fd..38a5f312ddb4b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -86,9 +86,9 @@ hws->ctx #define DC_LOGGER \ - ctx->logger -#define DC_LOGGER_INIT() \ - struct dc_context *ctx = dc->ctx + dc_ctx->logger +#define DC_LOGGER_INIT(ctx) \ + struct dc_context *dc_ctx = ctx #define REG(reg)\ hws->regs->reg @@ -687,7 +687,7 @@ dce110_external_encoder_control(enum bp_external_encoder_control_action action, .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000, .color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888, }; - DC_LOGGER_INIT(); + DC_LOGGER_INIT(dc->ctx); bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl); @@ -767,13 +767,14 @@ void dce110_edp_wait_for_hpd_ready( struct dc_link *link, bool power_up) { - struct dc_context *ctx = link->ctx; struct graphics_object_id connector = link->link_enc->connector; bool edp_hpd_high = false; uint32_t time_elapsed = 0; uint32_t timeout = power_up ? PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; + DC_LOGGER_INIT(link->ctx); + if (dal_graphics_object_id_get_connector_id(connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); @@ -825,6 +826,7 @@ void dce110_edp_power_control( enum bp_result bp_result; uint8_t pwrseq_instance; + DC_LOGGER_INIT(ctx); if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { @@ -993,6 +995,8 @@ void dce110_edp_backlight_control( unsigned int pre_T11_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0); unsigned int post_T7_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0); + DC_LOGGER_INIT(ctx); + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); @@ -1969,8 +1973,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) bool keep_edp_vdd_on = false; bool should_clean_dsc_block = true; struct dc_bios *dcb = dc->ctx->dc_bios; - DC_LOGGER_INIT(); - + DC_LOGGER_INIT(dc->ctx); get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); dc_get_edp_links(dc, edp_links, &edp_num); @@ -2736,7 +2739,6 @@ static bool wait_for_reset_trigger_to_occur( struct dc_context *dc_ctx, struct timing_generator *tg) { - struct dc_context *ctx = dc_ctx; bool rc = false; /* To avoid endless loop we wait at most @@ -2778,10 +2780,9 @@ static void dce110_enable_timing_synchronization( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct dcp_gsl_params gsl_params = { 0 }; int i; - DC_LOGGER_INIT(); + DC_LOGGER_INIT(dc->ctx); DC_SYNC_INFO("GSL: Setting-up...\n"); @@ -2824,10 +2825,9 @@ static void dce110_enable_per_frame_crtc_position_reset( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct dcp_gsl_params gsl_params = { 0 }; int i; - DC_LOGGER_INIT(); + DC_LOGGER_INIT(dc->ctx); gsl_params.gsl_group = 0; gsl_params.gsl_master = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 5243177c1faad..ffeec61824f51 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -60,9 +60,9 @@ #include "dc_state_priv.h" #define DC_LOGGER \ - dc_logger -#define DC_LOGGER_INIT(logger) \ - struct dal_logger *dc_logger = logger + dc_ctx->logger +#define DC_LOGGER_INIT(ctx) \ + struct dc_context *dc_ctx = ctx #define CTX \ hws->ctx @@ -1009,7 +1009,7 @@ static void power_on_plane_resources( struct dce_hwseq *hws, int plane_id) { - DC_LOGGER_INIT(hws->ctx->logger); + DC_LOGGER_INIT(hws->ctx); if (hws->funcs.dpp_root_clock_control) hws->funcs.dpp_root_clock_control(hws, plane_id, true); @@ -1286,7 +1286,7 @@ static void dcn10_reset_back_end_for_pipe( { int i; struct dc_link *link; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; @@ -1422,12 +1422,10 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc) return; if (!hubbub->funcs->verify_allow_pstate_change_high(hubbub)) { - int i = 0; - if (should_log_hw_state) dcn10_log_hw_state(dc, NULL); - TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); + TRACE_DC_PIPE_STATE(pipe_ctx, MAX_PIPES); BREAK_TO_DEBUGGER(); if (dcn10_hw_wa_force_recovery(dc)) { /*check again*/ @@ -1490,7 +1488,7 @@ void dcn10_plane_atomic_power_down(struct dc *dc, struct hubp *hubp) { struct dce_hwseq *hws = dc->hwseq; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (REG(DC_IP_REQUEST_CNTL)) { REG_SET(DC_IP_REQUEST_CNTL, 0, @@ -1554,7 +1552,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) { struct dce_hwseq *hws = dc->hwseq; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return; @@ -2268,8 +2266,6 @@ static bool wait_for_reset_trigger_to_occur( { bool rc = false; - DC_LOGGER_INIT(dc_ctx->logger); - /* To avoid endless loop we wait at most * frames_to_wait_on_triggered_reset frames for the reset to occur. */ const uint32_t frames_to_wait_on_triggered_reset = 10; @@ -2384,7 +2380,6 @@ static uint8_t get_clock_divider(struct pipe_ctx *pipe, static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; int i, master = -1, embedded = -1; struct dc_crtc_timing *hw_crtc_timing; uint64_t phase[MAX_PIPES]; @@ -2397,7 +2392,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, uint32_t dp_ref_clk_100hz = dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); hw_crtc_timing = kcalloc(MAX_PIPES, sizeof(*hw_crtc_timing), GFP_KERNEL); if (!hw_crtc_timing) @@ -2477,12 +2472,11 @@ void dcn10_enable_vblanks_synchronization( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct output_pixel_processor *opp; struct timing_generator *tg; int i, width = 0, height = 0, master; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); for (i = 1; i < group_size; i++) { opp = grouped_pipes[i]->stream_res.opp; @@ -2543,12 +2537,11 @@ void dcn10_enable_timing_synchronization( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct output_pixel_processor *opp; struct timing_generator *tg; int i, width = 0, height = 0; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); DC_SYNC_INFO("Setting up OTG reset trigger\n"); @@ -2624,10 +2617,9 @@ void dcn10_enable_per_frame_crtc_position_reset( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; int i; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); DC_SYNC_INFO("Setting up\n"); for (i = 0; i < group_size; i++) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index a069b7117d071..2c91a60f3334c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -513,7 +513,6 @@ static void dcn31_reset_back_end_for_pipe( { struct dc_link *link; - DC_LOGGER_INIT(dc->ctx->logger); if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index b5a4cefbd35f2..b5f60f59382ea 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -60,15 +60,15 @@ #include "dcn20/dcn20_hwseq.h" #include "dc_state_priv.h" -#define DC_LOGGER_INIT(logger) \ - struct dal_logger *dc_logger = logger +#define DC_LOGGER \ + dc_ctx->logger +#define DC_LOGGER_INIT(ctx) \ + struct dc_context *dc_ctx = ctx #define CTX \ hws->ctx #define REG(reg)\ hws->regs->reg -#define DC_LOGGER \ - dc_logger #undef FN @@ -331,7 +331,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) struct pipe_ctx *odm_pipe; int opp_cnt = 1; - DC_LOGGER_INIT(stream->ctx->logger); + DC_LOGGER_INIT(stream->ctx); ASSERT(dsc); for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) @@ -897,7 +897,7 @@ void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM; struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 69cc70106bf07..55c48c4bc6ce1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1982,7 +1982,6 @@ void dcn401_reset_back_end_for_pipe( struct dc_link *link = pipe_ctx->stream->link; const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); - DC_LOGGER_INIT(dc->ctx->logger); if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; @@ -2422,8 +2421,6 @@ void dcn401_program_front_end_for_ctx( struct dce_hwseq *hws = dc->hwseq; struct pipe_ctx *pipe = NULL; - DC_LOGGER_INIT(dc->ctx->logger); - if (resource_is_pipe_topology_changed(dc->current_state, context)) resource_log_pipe_topology_update(dc, context); @@ -2587,8 +2584,6 @@ void dcn401_post_unlock_program_front_end( struct dce_hwseq *hwseq = dc->hwseq; int i; - DC_LOGGER_INIT(dc->ctx->logger); - for (i = 0; i < dc->res_pool->pipe_count; i++) if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) && !resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD)) @@ -2968,8 +2963,6 @@ void dcn401_plane_atomic_power_down(struct dc *dc, struct dce_hwseq *hws = dc->hwseq; uint32_t org_ip_request_cntl = 0; - DC_LOGGER_INIT(dc->ctx->logger); - if (REG(DC_IP_REQUEST_CNTL)) { REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); if (org_ip_request_cntl == 0) @@ -3061,8 +3054,6 @@ void dcn401_plane_atomic_power_down_sequence(struct dc *dc, struct dce_hwseq *hws = dc->hwseq; uint32_t org_ip_request_cntl = 0; - DC_LOGGER_INIT(dc->ctx->logger); - /* Check and set DC_IP_REQUEST_CNTL if needed */ if (REG(DC_IP_REQUEST_CNTL)) { REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index d0bb26888f4b1..f992c2d167487 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -352,7 +352,7 @@ static void query_dp_dual_mode_adaptor( *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; - CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), + CONN_DATA_DETECT(link, type2_dongle_buf, sizeof(type2_dongle_buf), "DP-DVI passive dongle %dMhz: ", DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); return; @@ -657,8 +657,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link) unsigned long long time_taken_in_ns; int tries_taken; - DC_LOGGER_INIT(link->ctx->logger); - /** * this function will only exist if we are on dcn21 (is_in_alt_mode is a * function pointer, so checking to see if it is equal to 0 is the same @@ -729,8 +727,6 @@ static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) { - DC_LOGGER_INIT(link->ctx->logger); - LINK_INFO("link=%d, mst branch is now Connected\n", link->link_index); @@ -750,8 +746,6 @@ static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason bool link_reset_cur_dp_mst_topology(struct dc_link *link) { - DC_LOGGER_INIT(link->ctx->logger); - LINK_INFO("link=%d, mst branch is now Disconnected\n", link->link_index); @@ -977,8 +971,6 @@ static bool detect_link_and_local_sink(struct dc_link *link, enum dc_connection_type new_connection_type = dc_connection_none; const uint32_t post_oui_delay = 30; // 30ms - DC_LOGGER_INIT(link->ctx->logger); - if (dc_is_virtual_signal(link->connector_signal)) return false; @@ -1459,8 +1451,6 @@ bool link_detect(struct dc_link *link, enum dc_detect_reason reason) bool is_delegated_to_mst_top_mgr = false; enum dc_connection_type pre_link_type = link->type; - DC_LOGGER_INIT(link->ctx->logger); - is_local_sink_detect_success = detect_link_and_local_sink(link, reason); if (is_local_sink_detect_success && link->local_sink) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 5b2c1a4911cf0..ba311a8f3f654 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1094,8 +1094,6 @@ bool edp_send_replay_cmd(struct dc_link *link, if (!replay) return false; - DC_LOGGER_INIT(link->ctx->logger); - if (dp_pr_get_panel_inst(dc, link, &panel_inst)) cmd_data->panel_inst = panel_inst; else { diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c index b23c64004dd53..27e6532348509 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c @@ -118,9 +118,7 @@ void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) { - struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - - ASSERT(mpcc_id < mpc10->num_mpcc); + ASSERT(mpcc_id < TO_DCN10_MPC(mpc)->num_mpcc); return &(mpc->mpcc_array[mpcc_id]); } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 2c91a9e0305f0..911e9e2975351 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -2335,8 +2335,6 @@ static bool init_soc_bounding_box(struct dc *dc, struct _vcs_dpi_ip_params_st *loaded_ip = get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); - DC_LOGGER_INIT(dc->ctx->logger); - if (pool->base.pp_smu) { struct pp_smu_nv_clock_table max_clocks = {0}; unsigned int uclk_states[8] = {0}; From c5aae72526e9d7664f6a4bbe2bc5f0a70e3a5b7b Mon Sep 17 00:00:00 2001 From: Roman Li Date: Fri, 20 Feb 2026 16:48:14 -0500 Subject: [PATCH 1806/2070] drm/amd/display: Enable dcn42 DC clk_mgr Add support for DCN 4.2 clock manager. Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 16 + .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 236 ++++++------ drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + .../gpu/drm/amd/display/dc/dc_spl_translate.c | 1 + .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 3 +- .../amd/display/dc/dccg/dcn42/dcn42_dccg.c | 59 ++- .../amd/display/dc/dccg/dcn42/dcn42_dccg.h | 11 +- .../dml21/inc/bounding_boxes/dcn42_soc_bb.h | 359 ++++++++++++++++++ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 +- .../amd/display/dc/inc/hw/clk_mgr_internal.h | 73 +++- .../link/protocols/link_edp_panel_control.c | 1 + .../display/dc/soc_and_ip_translator/Makefile | 3 + .../dcn42/dcn42_soc_and_ip_translator.c | 159 +++++++- .../dcn42/dcn42_soc_and_ip_translator.h | 1 + .../soc_and_ip_translator.c | 4 + .../include/asic_reg/clk/clk_15_0_0_offset.h | 44 +++ .../include/asic_reg/clk/clk_15_0_0_sh_mask.h | 52 +++ 17 files changed, 885 insertions(+), 140 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index de016ea407b6d..a75d76d9f7405 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -48,6 +48,7 @@ #include "dcn32/dcn32_clk_mgr.h" #include "dcn35/dcn35_clk_mgr.h" #include "dcn401/dcn401_clk_mgr.h" +#include "dcn42/dcn42_clk_mgr.h" int clk_mgr_helper_get_active_display_cnt( struct dc *dc, @@ -362,6 +363,18 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p return &clk_mgr->base; } break; + case AMDGPU_FAMILY_GC_11_5_4: { + struct clk_mgr_dcn42 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); + + if (clk_mgr == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn42_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base.base; + } + break; #endif /* CONFIG_DRM_AMD_DC_FP */ default: ASSERT(0); /* Unknown Asic */ @@ -419,6 +432,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) case AMDGPU_FAMILY_GC_12_0_0: dcn401_clk_mgr_destroy(clk_mgr); break; + case AMDGPU_FAMILY_GC_11_5_4: + dcn42_clk_mgr_destroy(clk_mgr); + break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 55434f046fa29..cbb79789a5320 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -31,59 +31,19 @@ #include "link_service.h" #include "logger_types.h" +#include "clk/clk_15_0_0_offset.h" +#include "clk/clk_15_0_0_sh_mask.h" +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" + #undef DC_LOGGER #define DC_LOGGER \ - clk_mgr->base.base.ctx->logger - - -#define DCN_BASE__INST0_SEG1 0x000000C0 - -#define regCLK8_CLK2_BYPASS_CNTL 0x4c2a -#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX 0 -#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 -#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 -#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L -#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L - -#define regDENTIST_DISPCLK_CNTL 0x0064 -#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 - -// DENTIST_DISPCLK_CNTL -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 -#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 -#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L -#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L -#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L -#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L -#define mmDENTIST_DISPCLK_CNTL 0x0124 -#define mmCLK8_CLK_TICK_CNT_CONFIG_REG 0x1B851 -#define mmCLK8_CLK0_CURRENT_CNT 0x1B853 -#define mmCLK8_CLK1_CURRENT_CNT 0x1B854 -#define mmCLK8_CLK2_CURRENT_CNT 0x1B855 -#define mmCLK8_CLK3_CURRENT_CNT 0x1B856 -#define mmCLK8_CLK4_CURRENT_CNT 0x1B857 - - -#define mmCLK8_CLK0_BYPASS_CNTL 0x1B81A -#define mmCLK8_CLK1_BYPASS_CNTL 0x1B822 -#define mmCLK8_CLK2_BYPASS_CNTL 0x1B82A -#define mmCLK8_CLK3_BYPASS_CNTL 0x1B832 -#define mmCLK8_CLK4_BYPASS_CNTL 0x1B83A - - -#define mmCLK8_CLK0_DS_CNTL 0x1B814 -#define mmCLK8_CLK1_DS_CNTL 0x1B81C -#define mmCLK8_CLK2_DS_CNTL 0x1B824 -#define mmCLK8_CLK3_DS_CNTL 0x1B82C -#define mmCLK8_CLK4_DS_CNTL 0x1B834 - - + dc_logger +#define DC_LOGGER_INIT(logger) \ + struct dal_logger *dc_logger = logger +#define DCN42_CLKIP_REFCLK 48000 #undef FN #define FN(reg_name, field_name) \ @@ -92,16 +52,25 @@ #define REG(reg) \ (clk_mgr->regs->reg) +// for DCN register access +#define DCN_BASE__INST0_SEG0 0x00000012 +#define DCN_BASE__INST0_SEG1 0x000000C0 + #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg #define BASE(seg) BASE_INNER(seg) -#define SR(reg_name)\ - .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ - reg ## reg_name +#define SR(reg_name) \ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name + +// for CLKIP register access +#define CLK_BASE__INST0_SEG0 0x00016C00 -#define CLK_SR_DCN42(reg_name)\ - .reg_name = mm ## reg_name +#define CLK_BASE_INNER(seg) \ + CLK_BASE__INST0_SEG ## seg + +#define CLK_SR_DCN42(reg_name) \ + .reg_name = CLK_BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name static const struct clk_mgr_registers clk_mgr_regs_dcn42 = { CLK_REG_LIST_DCN42() @@ -115,8 +84,6 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn42 = { CLK_COMMON_MASK_SH_LIST_DCN42(_MASK) }; - - #define TO_CLK_MGR_DCN42(clk_mgr_int)\ container_of(clk_mgr_int, struct clk_mgr_dcn42, base) @@ -154,6 +121,49 @@ int dcn42_get_active_display_cnt_wa( return display_count; } +static uint32_t dcn42_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + uint64_t clock_freq_mhz = 0; + uint32_t timer_threshold = 0; + + // always safer to read the timer threshold instead of using cached value + REG_GET(CLK8_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, &timer_threshold); + + if (timer_threshold == 0) { + BREAK_TO_DEBUGGER(); + return 0; + } + + switch (clock) { + case clock_type_dispclk: + clock_freq_mhz = REG_READ(CLK8_CLK0_CURRENT_CNT); + break; + case clock_type_dppclk: + clock_freq_mhz = REG_READ(CLK8_CLK1_CURRENT_CNT); + break; + case clock_type_dprefclk: + clock_freq_mhz = REG_READ(CLK8_CLK2_CURRENT_CNT); + break; + case clock_type_dcfclk: + clock_freq_mhz = REG_READ(CLK8_CLK3_CURRENT_CNT); + break; + case clock_type_dtbclk: + clock_freq_mhz = REG_READ(CLK8_CLK4_CURRENT_CNT); + break; + default: + break; + } + + clock_freq_mhz *= DCN42_CLKIP_REFCLK; + clock_freq_mhz = div_u64(clock_freq_mhz, timer_threshold); + + // there are no DCN clocks over 0xFFFFFFFF MHz + ASSERT(clock_freq_mhz <= 0xFFFFFFFF); + + return (uint32_t)clock_freq_mhz; +} + void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz) @@ -224,8 +234,6 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, display_count = dcn42_get_active_display_cnt_wa(dc, context, &all_active_disps); - /*dml21 issue*/ - ASSERT(new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000); //remove this section if assert is hit if (new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz < 590000) new_clocks->ref_dtbclk_khz = 600000; @@ -262,9 +270,7 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); dcn42_smu_set_dtbclk(clk_mgr, true); - if (clk_mgr_base->boot_snapshot.timer_threhold) - actual_dtbclk = REG_READ(CLK8_CLK4_CURRENT_CNT) / (clk_mgr_base->boot_snapshot.timer_threhold / 48000); - + actual_dtbclk = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk); if (actual_dtbclk > 590000) { clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; @@ -386,34 +392,27 @@ bool dcn42_are_clock_states_equal(struct dc_clocks *a, static void dcn42_dump_clk_registers_internal(struct dcn42_clk_internal *internal, struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - uint32_t ratio = 1; - - internal->CLK8_CLK_TICK_CNT__TIMER_THRESHOLD = REG_READ(CLK8_CLK_TICK_CNT_CONFIG_REG) & 0xFFFFFF; - - ratio = internal->CLK8_CLK_TICK_CNT__TIMER_THRESHOLD / 48000; - ASSERT(ratio != 0); - - if (ratio) { - // read dcf deep sleep divider - internal->CLK8_CLK0_DS_CNTL = REG_READ(CLK8_CLK0_DS_CNTL); - internal->CLK8_CLK3_DS_CNTL = REG_READ(CLK8_CLK3_DS_CNTL); - // read dispclk - internal->CLK8_CLK0_CURRENT_CNT = REG_READ(CLK8_CLK0_CURRENT_CNT) / ratio; - internal->CLK8_CLK0_BYPASS_CNTL = REG_READ(CLK8_CLK0_BYPASS_CNTL); - // read dppclk - internal->CLK8_CLK1_CURRENT_CNT = REG_READ(CLK8_CLK1_CURRENT_CNT) / ratio; - internal->CLK8_CLK1_BYPASS_CNTL = REG_READ(CLK8_CLK1_BYPASS_CNTL); - // read dprefclk - internal->CLK8_CLK2_CURRENT_CNT = REG_READ(CLK8_CLK2_CURRENT_CNT) / ratio; - internal->CLK8_CLK2_BYPASS_CNTL = REG_READ(CLK8_CLK2_BYPASS_CNTL); - // read dcfclk - internal->CLK8_CLK3_CURRENT_CNT = REG_READ(CLK8_CLK3_CURRENT_CNT) / ratio; - internal->CLK8_CLK3_BYPASS_CNTL = REG_READ(CLK8_CLK3_BYPASS_CNTL); - // read dtbclk - internal->CLK8_CLK4_CURRENT_CNT = REG_READ(CLK8_CLK4_CURRENT_CNT) / ratio; - internal->CLK8_CLK4_BYPASS_CNTL = REG_READ(CLK8_CLK4_BYPASS_CNTL); - } + REG_GET(CLK8_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, &internal->CLK8_CLK_TICK_CNT__TIMER_THRESHOLD); + + // read dcf deep sleep divider + internal->CLK8_CLK0_DS_CNTL = REG_READ(CLK8_CLK0_DS_CNTL); + internal->CLK8_CLK3_DS_CNTL = REG_READ(CLK8_CLK3_DS_CNTL); + // read dispclk + internal->CLK8_CLK0_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dispclk); + internal->CLK8_CLK0_BYPASS_CNTL = REG_READ(CLK8_CLK0_BYPASS_CNTL); + // read dppclk + internal->CLK8_CLK1_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dppclk); + internal->CLK8_CLK1_BYPASS_CNTL = REG_READ(CLK8_CLK1_BYPASS_CNTL); + // read dprefclk + internal->CLK8_CLK2_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dprefclk); + internal->CLK8_CLK2_BYPASS_CNTL = REG_READ(CLK8_CLK2_BYPASS_CNTL); + // read dcfclk + internal->CLK8_CLK3_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dcfclk); + internal->CLK8_CLK3_BYPASS_CNTL = REG_READ(CLK8_CLK3_BYPASS_CNTL); + // read dtbclk + internal->CLK8_CLK4_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk); + internal->CLK8_CLK4_BYPASS_CNTL = REG_READ(CLK8_CLK4_BYPASS_CNTL); } static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, @@ -422,8 +421,11 @@ static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs struct dcn42_clk_internal internal = {0}; char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; + DC_LOGGER_INIT(clk_mgr->base.base.ctx->logger); + (void)dc_logger; + dcn42_dump_clk_registers_internal(&internal, &clk_mgr->base.base); - regs_and_bypass->timer_threhold = internal.CLK8_CLK_TICK_CNT__TIMER_THRESHOLD; + regs_and_bypass->timer_threshold = internal.CLK8_CLK_TICK_CNT__TIMER_THRESHOLD; regs_and_bypass->dcfclk = internal.CLK8_CLK3_CURRENT_CNT / 10; regs_and_bypass->dcf_deep_sleep_divider = internal.CLK8_CLK3_DS_CNTL / 10; regs_and_bypass->dcf_deep_sleep_allow = internal.CLK8_CLK3_DS_CNTL & 0x10; /*bit 4: CLK0_ALLOW_DS*/ @@ -432,18 +434,10 @@ static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs regs_and_bypass->dppclk = internal.CLK8_CLK1_CURRENT_CNT / 10; regs_and_bypass->dtbclk = internal.CLK8_CLK4_CURRENT_CNT / 10; - regs_and_bypass->dppclk_bypass = internal.CLK8_CLK1_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dppclk_bypass > 4) - regs_and_bypass->dppclk_bypass = 0; - regs_and_bypass->dcfclk_bypass = internal.CLK8_CLK3_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dcfclk_bypass > 4) - regs_and_bypass->dcfclk_bypass = 0; - regs_and_bypass->dispclk_bypass = internal.CLK8_CLK0_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dispclk_bypass > 4) - regs_and_bypass->dispclk_bypass = 0; - regs_and_bypass->dprefclk_bypass = internal.CLK8_CLK2_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dprefclk_bypass > 4) - regs_and_bypass->dprefclk_bypass = 0; + regs_and_bypass->dispclk_bypass = get_reg_field_value(internal.CLK8_CLK0_BYPASS_CNTL, CLK8_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL); + regs_and_bypass->dppclk_bypass = get_reg_field_value(internal.CLK8_CLK1_BYPASS_CNTL, CLK8_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL); + regs_and_bypass->dprefclk_bypass = get_reg_field_value(internal.CLK8_CLK2_BYPASS_CNTL, CLK8_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL); + regs_and_bypass->dcfclk_bypass = get_reg_field_value(internal.CLK8_CLK3_BYPASS_CNTL, CLK8_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL); if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); @@ -588,6 +582,9 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 }; + DC_LOGGER_INIT(clk_mgr_base->ctx->logger); + (void)dc_logger; + init_clk_states(clk_mgr_base); // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk @@ -1111,25 +1108,30 @@ void dcn42_clk_mgr_construct( */ clk_mgr->base.base.dprefclk_khz = 600000; - clk_mgr->base.smu_present = false; + clk_mgr->base.smu_present = false; + clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base); + if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1) + clk_mgr->base.smu_present = true; - if (ctx->dc_bios->integrated_info) { - clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; + if (ctx->dc_bios->integrated_info) { + clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) - dcn42_bw_params.wm_table = lpddr5_wm_table; - else - dcn42_bw_params.wm_table = ddr5_wm_table; - dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; - dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; - dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 4; - } - /* in case we don't get a value from the BIOS, use default */ - if (clk_mgr->base.base.dentist_vco_freq_khz == 0) - clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */ + if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) + dcn42_bw_params.wm_table = lpddr5_wm_table; + else + dcn42_bw_params.wm_table = ddr5_wm_table; + + dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; + dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; + dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 4; + } + + /* in case we don't get a value from the BIOS, use default */ + if (clk_mgr->base.base.dentist_vco_freq_khz == 0) + clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */ - /* Saved clocks configured at boot for debug purposes */ - dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); + /* Saved clocks configured at boot for debug purposes */ + dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); if (clk_mgr->base.smu_present) clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index cba35cb70a10a..29888c98e2c53 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5947,6 +5947,7 @@ bool dc_is_dmub_outbox_supported(struct dc *dc) case AMDGPU_FAMILY_GC_11_0_1: case AMDGPU_FAMILY_GC_11_5_0: + case AMDGPU_FAMILY_GC_11_5_4: if (!dc->debug.dpia_debug.bits.disable_dpia) return true; break; diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 37d1a79e8241e..ba7bf23f2b2fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -89,6 +89,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->callbacks = dcn32_spl_callbacks; break; case DCN_VERSION_4_01: + case DCN_VERSION_4_2: spl_in->callbacks = dcn401_spl_callbacks; break; default: diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 463f5826a1ea1..088cf305a772c 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -374,7 +374,8 @@ type OTG1_DROP_PIXEL;\ type OTG2_DROP_PIXEL;\ type OTG3_ADD_PIXEL;\ - type OTG3_DROP_PIXEL; + type OTG3_DROP_PIXEL;\ + type RESYNC_FIFO_LEVEL_ADJUST_EN; struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index d1593dc68e361..19dfc3fe5c3a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -180,6 +180,61 @@ void dccg42_set_physymclk( } } +void dccg42_set_pixel_rate_div( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div tmds_div, + enum pixel_rate_div unused) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA; + uint32_t dp_dto_int; + uint32_t reg_val; + + // only 2 and 4 are valid on dcn401 + if (tmds_div != PIXEL_RATE_DIV_BY_2 && tmds_div != PIXEL_RATE_DIV_BY_4) { + return; + } + + dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int); + if (tmds_div == cur_tmds_div) + return; + + // encode enum to register value + reg_val = tmds_div == PIXEL_RATE_DIV_BY_4 ? 1 : 0; + + switch (otg_inst) { + case 0: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG0_TMDS_PIXEL_RATE_DIV, reg_val); + break; + case 1: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG1_TMDS_PIXEL_RATE_DIV, reg_val); + break; + case 2: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG2_TMDS_PIXEL_RATE_DIV, reg_val); + break; + case 3: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG3_TMDS_PIXEL_RATE_DIV, reg_val); + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +void dccg42_trigger_dio_fifo_resync(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, RESYNC_FIFO_LEVEL_ADJUST_EN, 1); + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, RESYNC_FIFO_LEVEL_ADJUST_EN, 0); + REG_WAIT(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, 1, 50, 2000); +} + static void dccg42_init(struct dccg *dccg) { int otg_inst; @@ -240,9 +295,9 @@ static const struct dccg_funcs dccg42_funcs = { .otg_drop_pixel = dccg42_otg_drop_pixel, .disable_dsc = dccg35_disable_dscclk, .enable_dsc = dccg35_enable_dscclk, - .set_pixel_rate_div = dccg401_set_pixel_rate_div, + .set_pixel_rate_div = dccg42_set_pixel_rate_div, .get_pixel_rate_div = dccg401_get_pixel_rate_div, - .trigger_dio_fifo_resync = dccg35_trigger_dio_fifo_resync, + .trigger_dio_fifo_resync = dccg42_trigger_dio_fifo_resync, .set_dp_dto = dccg401_set_dp_dto, .enable_symclk_se = dccg35_enable_symclk_se, .disable_symclk_se = dccg35_disable_symclk_se, diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h index 96eae0003f439..d9831b0f82359 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h @@ -238,7 +238,8 @@ DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_SRC_SEL, mask_sh),\ DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, mask_sh),\ DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, mask_sh),\ - DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh) + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, RESYNC_FIFO_LEVEL_ADJUST_EN, mask_sh) void dccg42_otg_add_pixel(struct dccg *dccg, @@ -254,6 +255,14 @@ void dccg42_set_physymclk( enum physymclk_clock_source clk_src, bool force_enable); +void dccg42_set_pixel_rate_div( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div tmds_div, + enum pixel_rate_div unused); + +void dccg42_trigger_dio_fifo_resync(struct dccg *dccg); + struct dccg *dccg42_create( struct dc_context *ctx, const struct dccg_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h new file mode 100644 index 0000000000000..8cd074cfdf18d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DML_DML_DCN42_SOC_BB__ +#define __DML_DML_DCN42_SOC_BB__ + +#include "dml_top_soc_parameter_types.h" + +static const struct dml2_soc_qos_parameters dml_dcn42_variant_a_soc_qos_params = { + .derate_table = { + .system_active_urgent = { + .dram_derate_percent_pixel = 22, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 76, + .dcfclk_derate_percent = 100, + }, + .system_active_average = { + .dram_derate_percent_pixel = 17, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 57, + .dcfclk_derate_percent = 75, + }, + .dcn_mall_prefetch_urgent = { + .dram_derate_percent_pixel = 40, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 83, + .dcfclk_derate_percent = 100, + }, + .dcn_mall_prefetch_average = { + .dram_derate_percent_pixel = 33, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 62, + .dcfclk_derate_percent = 83, + }, + .system_idle_average = { + .dram_derate_percent_pixel = 70, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 83, + .dcfclk_derate_percent = 100, + }, + }, + .writeback = { + .base_latency_us = 12, + .scaling_factor_us = 0, + .scaling_factor_mhz = 0, + }, + .qos_params = { + .dcn4x = { + .df_qos_response_time_fclk_cycles = 300, + .max_round_trip_to_furthest_cs_fclk_cycles = 350, + .mall_overhead_fclk_cycles = 50, + .meta_trip_adder_fclk_cycles = 36, + .average_transport_distance_fclk_cycles = 257, + .umc_urgent_ramp_latency_margin = 50, + .umc_max_latency_margin = 30, + .umc_average_latency_margin = 20, + .fabric_max_transport_latency_margin = 20, + .fabric_average_transport_latency_margin = 10, + + .per_uclk_dpm_params = { + { + .minimum_uclk_khz = 97 * 1000, + .urgent_ramp_uclk_cycles = 472, + .trip_to_memory_uclk_cycles = 827, + .meta_trip_to_memory_uclk_cycles = 827, + .maximum_latency_when_urgent_uclk_cycles = 72, + .average_latency_when_urgent_uclk_cycles = 61, + .maximum_latency_when_non_urgent_uclk_cycles = 827, + .average_latency_when_non_urgent_uclk_cycles = 118, + }, + }, + }, + }, + .qos_type = dml2_qos_param_type_dcn4x, +}; + +static const struct dml2_soc_bb dml2_socbb_dcn42 = { + .clk_table = { + .uclk = { + .clk_values_khz = {97000}, + .num_clk_values = 1, + }, + .fclk = { + .clk_values_khz = {300000, 2500000}, + .num_clk_values = 2, + }, + .dcfclk = { + .clk_values_khz = {200000, 1564000}, + .num_clk_values = 2, + }, + .dispclk = { + .clk_values_khz = {100000, 1500000}, + .num_clk_values = 2, + }, + .dppclk = { + .clk_values_khz = {100000, 1500000}, + .num_clk_values = 2, + }, + .dtbclk = { + .clk_values_khz = {600000, 600000}, + .num_clk_values = 2, + }, + .phyclk = { + .clk_values_khz = {810000, 810000}, + .num_clk_values = 2, + }, + .socclk = { + .clk_values_khz = {300000, 1200000}, + .num_clk_values = 2, + }, + .dscclk = { + .clk_values_khz = {500000, 500000}, + .num_clk_values = 2, + }, + .phyclk_d18 = { + .clk_values_khz = {667000, 667000}, + .num_clk_values = 2, + }, + .phyclk_d32 = { + .clk_values_khz = {625000, 625000}, + .num_clk_values = 2, + }, + .dram_config = { + .channel_width_bytes = 4, + .channel_count = 4, + .alt_clock_bw_conversion = true, + }, + }, + + .qos_parameters = { + .derate_table = { + .system_active_urgent = { + .dram_derate_percent_pixel = 22, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 76, + .dcfclk_derate_percent = 100, + }, + .system_active_average = { + .dram_derate_percent_pixel = 15, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 57, + .dcfclk_derate_percent = 75, + }, + .dcn_mall_prefetch_urgent = { + .dram_derate_percent_pixel = 40, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 83, + .dcfclk_derate_percent = 100, + }, + .dcn_mall_prefetch_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 62, + .dcfclk_derate_percent = 83, + }, + .system_idle_average = { + .dram_derate_percent_pixel = 70, + .dram_derate_percent_vm = 0, + .dram_derate_percent_pixel_and_vm = 0, + .fclk_derate_percent = 83, + .dcfclk_derate_percent = 100, + }, + }, + .writeback = { + .base_latency_us = 12, + .scaling_factor_us = 0, + .scaling_factor_mhz = 0, + }, + .qos_params = { + .dcn4x = { + .df_qos_response_time_fclk_cycles = 300, + .max_round_trip_to_furthest_cs_fclk_cycles = 350, + .mall_overhead_fclk_cycles = 50, + .meta_trip_adder_fclk_cycles = 36, + .average_transport_distance_fclk_cycles = 260, + .umc_urgent_ramp_latency_margin = 50, + .umc_max_latency_margin = 30, + .umc_average_latency_margin = 20, + .fabric_max_transport_latency_margin = 20, + .fabric_average_transport_latency_margin = 10, + + .per_uclk_dpm_params = { + { + // State 1 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 472, + .trip_to_memory_uclk_cycles = 827, + .meta_trip_to_memory_uclk_cycles = 827, + .maximum_latency_when_urgent_uclk_cycles = 72, + .average_latency_when_urgent_uclk_cycles = 72, + .maximum_latency_when_non_urgent_uclk_cycles = 827, + .average_latency_when_non_urgent_uclk_cycles = 117, + }, + { + // State 2 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 546, + .trip_to_memory_uclk_cycles = 848, + .meta_trip_to_memory_uclk_cycles = 848, + .maximum_latency_when_urgent_uclk_cycles = 146, + .average_latency_when_urgent_uclk_cycles = 146, + .maximum_latency_when_non_urgent_uclk_cycles = 848, + .average_latency_when_non_urgent_uclk_cycles = 133, + }, + { + // State 3 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 564, + .trip_to_memory_uclk_cycles = 853, + .meta_trip_to_memory_uclk_cycles = 853, + .maximum_latency_when_urgent_uclk_cycles = 164, + .average_latency_when_urgent_uclk_cycles = 164, + .maximum_latency_when_non_urgent_uclk_cycles = 853, + .average_latency_when_non_urgent_uclk_cycles = 136, + }, + { + // State 4 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 613, + .trip_to_memory_uclk_cycles = 869, + .meta_trip_to_memory_uclk_cycles = 869, + .maximum_latency_when_urgent_uclk_cycles = 213, + .average_latency_when_urgent_uclk_cycles = 213, + .maximum_latency_when_non_urgent_uclk_cycles = 869, + .average_latency_when_non_urgent_uclk_cycles = 149, + }, + { + // State 5 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 632, + .trip_to_memory_uclk_cycles = 874, + .meta_trip_to_memory_uclk_cycles = 874, + .maximum_latency_when_urgent_uclk_cycles = 232, + .average_latency_when_urgent_uclk_cycles = 232, + .maximum_latency_when_non_urgent_uclk_cycles = 874, + .average_latency_when_non_urgent_uclk_cycles = 153, + }, + { + // State 6 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 665, + .trip_to_memory_uclk_cycles = 885, + .meta_trip_to_memory_uclk_cycles = 885, + .maximum_latency_when_urgent_uclk_cycles = 265, + .average_latency_when_urgent_uclk_cycles = 265, + .maximum_latency_when_non_urgent_uclk_cycles = 885, + .average_latency_when_non_urgent_uclk_cycles = 161, + }, + { + // State 7 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 689, + .trip_to_memory_uclk_cycles = 895, + .meta_trip_to_memory_uclk_cycles = 895, + .maximum_latency_when_urgent_uclk_cycles = 289, + .average_latency_when_urgent_uclk_cycles = 289, + .maximum_latency_when_non_urgent_uclk_cycles = 895, + .average_latency_when_non_urgent_uclk_cycles = 167, + }, + { + // State 8 + .minimum_uclk_khz = 0, + .urgent_ramp_uclk_cycles = 716, + .trip_to_memory_uclk_cycles = 902, + .meta_trip_to_memory_uclk_cycles = 902, + .maximum_latency_when_urgent_uclk_cycles = 316, + .average_latency_when_urgent_uclk_cycles = 316, + .maximum_latency_when_non_urgent_uclk_cycles = 902, + .average_latency_when_non_urgent_uclk_cycles = 174, + }, + }, + }, + }, + .qos_type = dml2_qos_param_type_dcn4x, + }, + + .power_management_parameters = { + .dram_clk_change_blackout_us = 11.72, + .fclk_change_blackout_us = 0, + .g7_ppt_blackout_us = 0, + .stutter_enter_plus_exit_latency_us = 11, + .stutter_exit_latency_us = 9, + .z8_stutter_enter_plus_exit_latency_us = 300, + .z8_stutter_exit_latency_us = 200, + }, + + .vmin_limit = { + .dispclk_khz = 600 * 1000, + }, + + .dprefclk_mhz = 600, + .xtalclk_mhz = 24, + .pcie_refclk_mhz = 100, + .dchub_refclk_mhz = 50, + .mall_allocated_for_dcn_mbytes = 64, + .max_outstanding_reqs = 256, + .fabric_datapath_to_dcn_data_return_bytes = 32, + .return_bus_width_bytes = 64, + .hostvm_min_page_size_kbytes = 4, + .gpuvm_min_page_size_kbytes = 256, + .phy_downspread_percent = 0.38, + .dcn_downspread_percent = 0.38, + .dispclk_dppclk_vco_speed_mhz = 3000, + .do_urgent_latency_adjustment = 0, + .mem_word_bytes = 32, + .num_dcc_mcaches = 8, + .mcache_size_bytes = 2048, + .mcache_line_size_bytes = 32, + .max_fclk_for_uclk_dpm_khz = 2200 * 1000, +}; + +static const struct dml2_ip_capabilities dml2_dcn42_max_ip_caps = { + .pipe_count = 4, + .otg_count = 4, + .num_dsc = 4, + .max_num_dp2p0_streams = 4, + .max_num_hdmi_frl_outputs = 1, + .max_num_dp2p0_outputs = 4, + .rob_buffer_size_kbytes = 64, + .config_return_buffer_size_in_kbytes = 1792, + .config_return_buffer_segment_size_in_kbytes = 64, + .meta_fifo_size_in_kentries = 32, + .compressed_buffer_segment_size_in_kbytes = 64, + .cursor_buffer_size = 24, + .max_flip_time_us = 110, + .max_flip_time_lines = 50, + .hostvm_mode = 0, + .subvp_drr_scheduling_margin_us = 100, + .subvp_prefetch_end_to_mall_start_us = 15, + .subvp_fw_processing_delay = 15, + .max_vactive_det_fill_delay_us = 400, + + .fams2 = { + .max_allow_delay_us = 100 * 1000, + .scheduling_delay_us = 550, + .vertical_interrupt_ack_delay_us = 40, + .allow_programming_delay_us = 18, + .min_allow_width_us = 20, + .subvp_df_throttle_delay_us = 100, + .subvp_programming_delay_us = 200, + .subvp_prefetch_to_mall_delay_us = 18, + .drr_programming_delay_us = 35, + + .lock_timeout_us = 5000, + .recovery_timeout_us = 5000, + .flip_programming_delay_us = 300, + }, +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 91eba1985bab1..21224fd6b36d6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -215,7 +215,7 @@ struct clk_state_registers_and_bypass { uint32_t dcfclk_bypass; uint32_t dprefclk_bypass; uint32_t dispclk_bypass; - uint32_t timer_threhold; + uint32_t timer_threshold; }; struct rv1_clk_internal { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 9e53eacee3f84..c69ccfcebeb5a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -243,7 +243,23 @@ enum dentist_divider_range { CLK_SR_DCN42(CLK8_CLK3_DS_CNTL), \ CLK_SR_DCN42(CLK8_CLK4_DS_CNTL) -#define CLK_COMMON_MASK_SH_LIST_DCN42(mask_sh) 0 +#define CLK_COMMON_MASK_SH_LIST_DCN42(mask_sh) \ + CLK_SF(CLK8_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, mask_sh), \ + CLK_SF(CLK8_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK4_BYPASS_CNTL, CLK4_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK0_DS_CNTL, CLK0_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK1_DS_CNTL, CLK1_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK2_DS_CNTL, CLK2_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK3_DS_CNTL, CLK3_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK4_DS_CNTL, CLK4_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK0_DS_CNTL, CLK0_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK1_DS_CNTL, CLK1_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK2_DS_CNTL, CLK2_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK3_DS_CNTL, CLK3_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK4_DS_CNTL, CLK4_ALLOW_DS, mask_sh), \ @@ -259,6 +275,42 @@ enum dentist_divider_range { type FbMult_int; \ type FbMult_frac; +#define CLK42_REG_LIST(clkip_num, type) \ + type CLK ## clkip_num ## _CLK_TICK_CNT_CONFIG_REG; \ + type CLK ## clkip_num ## _CLK0_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK1_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK2_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK3_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK4_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK0_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK1_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK2_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK3_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK4_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK0_DS_CNTL; \ + type CLK ## clkip_num ## _CLK1_DS_CNTL; \ + type CLK ## clkip_num ## _CLK2_DS_CNTL; \ + type CLK ## clkip_num ## _CLK3_DS_CNTL; \ + type CLK ## clkip_num ## _CLK4_DS_CNTL; + +#define CLK42_REG_FIELD_LIST(type) \ + type TIMER_THRESHOLD; \ + type CLK0_BYPASS_SEL; \ + type CLK1_BYPASS_SEL; \ + type CLK2_BYPASS_SEL; \ + type CLK3_BYPASS_SEL; \ + type CLK4_BYPASS_SEL; \ + type CLK0_DS_DIV_ID; \ + type CLK1_DS_DIV_ID; \ + type CLK2_DS_DIV_ID; \ + type CLK3_DS_DIV_ID; \ + type CLK4_DS_DIV_ID; \ + type CLK0_ALLOW_DS; \ + type CLK1_ALLOW_DS; \ + type CLK2_ALLOW_DS; \ + type CLK3_ALLOW_DS; \ + type CLK4_ALLOW_DS; + /* *************************************************************************************** ****************** Clock Manager Private Structures *********************************** @@ -322,32 +374,19 @@ struct clk_mgr_registers { uint32_t CLK1_CLK5_ALLOW_DS; uint32_t CLK5_spll_field_8; uint32_t CLK6_spll_field_8; - uint32_t CLK8_CLK0_CURRENT_CNT; - uint32_t CLK8_CLK1_CURRENT_CNT; - uint32_t CLK8_CLK2_CURRENT_CNT; - uint32_t CLK8_CLK3_CURRENT_CNT; - uint32_t CLK8_CLK4_CURRENT_CNT; - uint32_t CLK8_CLK0_DS_CNTL; - uint32_t CLK8_CLK1_DS_CNTL; - uint32_t CLK8_CLK2_DS_CNTL; - uint32_t CLK8_CLK3_DS_CNTL; - uint32_t CLK8_CLK4_DS_CNTL; - uint32_t CLK8_CLK0_BYPASS_CNTL; - uint32_t CLK8_CLK1_BYPASS_CNTL; - uint32_t CLK8_CLK2_BYPASS_CNTL; - uint32_t CLK8_CLK3_BYPASS_CNTL; - uint32_t CLK8_CLK4_BYPASS_CNTL; - uint32_t CLK8_CLK_TICK_CNT_CONFIG_REG; + CLK42_REG_LIST(8, uint32_t) }; struct clk_mgr_shift { CLK_REG_FIELD_LIST(uint8_t) CLK20_REG_FIELD_LIST(uint8_t) + CLK42_REG_FIELD_LIST(uint8_t) }; struct clk_mgr_mask { CLK_REG_FIELD_LIST(uint32_t) CLK20_REG_FIELD_LIST(uint32_t) + CLK42_REG_FIELD_LIST(uint32_t) }; enum clock_type { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index ba311a8f3f654..4a2699a374b7e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -847,6 +847,7 @@ bool edp_setup_psr(struct dc_link *link, case FAMILY_YELLOW_CARP: case AMDGPU_FAMILY_GC_10_3_6: case AMDGPU_FAMILY_GC_11_0_1: + case AMDGPU_FAMILY_GC_11_5_4: if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable) psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; break; diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile index 897a5e3f14663..f905b4d224488 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile @@ -46,11 +46,14 @@ endif endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) +CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.o := $(soc_and_ip_translator_rcflags) soc_and_ip_translator := soc_and_ip_translator.o soc_and_ip_translator += dcn401/dcn401_soc_and_ip_translator.o +soc_and_ip_translator += dcn42/dcn42_soc_and_ip_translator.o AMD_DAL_soc_and_ip_translator := $(addprefix $(AMDDALPATH)/dc/soc_and_ip_translator/, $(soc_and_ip_translator)) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c index c9e224d262c90..87ac567390305 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -11,13 +11,169 @@ * This component provides an interface to get DCN-specific bounding box values. */ +static void get_default_soc_bb(struct dml2_soc_bb *soc_bb) +{ + memcpy(soc_bb, &dml2_socbb_dcn42, sizeof(struct dml2_soc_bb)); + memcpy(&soc_bb->qos_parameters, &dml_dcn42_variant_a_soc_qos_params, sizeof(struct dml2_soc_qos_parameters)); +} + +/* + * DC clock table is obtained from SMU during runtime. + * SMU stands for System Management Unit. It is a power management processor. + * It owns the initialization of dc's clock table and programming of clock values + * based on dc's requests. + * Our clock values in base soc bb is a dummy placeholder. The real clock values + * are retrieved from SMU firmware to dc clock table at runtime. + * This function overrides our dummy placeholder values with real values in dc + * clock table. + */ +static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( + struct dml2_soc_state_table *dml_clk_table, + struct dml2_soc_vmin_clock_limits *vmin_limit, + const struct clk_bw_params *dc_bw_params) +{ + int i; + const struct clk_limit_table *dc_clk_table; + + if (dc_bw_params == NULL) + /* skip if bw params could not be obtained from smu */ + return; + + dc_clk_table = &dc_bw_params->clk_table; + + /* fclk/dcfclk - dcn42 pmfw table can have 0 entries for inactive dpm levels + * for use with dml we need to fill in using an active value aiming for >= 2x DCFCLK + */ + if (dc_clk_table->num_entries_per_clk.num_fclk_levels && dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + int j, max_fclk = 0; + + dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; + for (j = 0; j < MAX_NUM_DPM_LVL; j++) { + if (dc_clk_table->entries[j].fclk_mhz * 1000 > max_fclk) + max_fclk = dc_clk_table->entries[j].fclk_mhz * 1000; + dml_clk_table->fclk.clk_values_khz[i] = max_fclk; + if (max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i]) + break; + } + } else { + dml_clk_table->dcfclk.clk_values_khz[i] = 0; + dml_clk_table->fclk.clk_values_khz[i] = 0; + } + } + } + + /* uclk */ + if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { + dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->uclk.num_clk_values) { + dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; + dml_clk_table->wck_ratio.clk_values_khz[i] = dc_clk_table->entries[i].wck_ratio; + } else { + dml_clk_table->uclk.clk_values_khz[i] = 0; + dml_clk_table->wck_ratio.clk_values_khz[i] = 0; + } + } + } + + /* dispclk */ + if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { + dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dispclk.num_clk_values) { + dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; + } else { + dml_clk_table->dispclk.clk_values_khz[i] = 0; + } + } + vmin_limit->dispclk_khz = min(dc_clk_table->entries[0].dispclk_mhz * 1000, vmin_limit->dispclk_khz); + } + + /* dppclk */ + if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { + dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dppclk.num_clk_values) { + dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; + } else { + dml_clk_table->dppclk.clk_values_khz[i] = 0; + } + } + } + + /* dtbclk */ + if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { + dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dtbclk.num_clk_values) { + dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; + } else { + dml_clk_table->dtbclk.clk_values_khz[i] = 0; + } + } + } + + /* socclk */ + if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { + dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->socclk.num_clk_values) { + dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; + } else { + dml_clk_table->socclk.clk_values_khz[i] = 0; + } + } + } + + /* dram config */ + dml_clk_table->dram_config.channel_count = dc_bw_params->num_channels; + dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes; +} + +static void dcn42_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc) +{ + soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000; + soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + soc_bb->mall_allocated_for_dcn_mbytes = dc->caps.mall_size_total / (1024 * 1024); + + if (dc->clk_mgr->funcs->is_smu_present && + dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) { + dcn42_convert_dc_clock_table_to_soc_bb_clock_table(&soc_bb->clk_table, &soc_bb->vmin_limit, + dc->clk_mgr->bw_params); + } +} + +static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + /* Individual modification can be overwritten even if it was obtained by a previous function. + * Modifications are acquired in order of priority (lowest to highest). + */ + dc_assert_fp_enabled(); + + dcn42_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc); + dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc); + dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc); +} + +void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + //get default soc_bb with static values + get_default_soc_bb(soc_bb); + //update soc_bb values with more accurate values + apply_soc_bb_updates(soc_bb, dc, config); +} + static void dcn42_get_ip_caps(struct dml2_ip_capabilities *ip_caps) { *ip_caps = dml2_dcn42_max_ip_caps; } static struct soc_and_ip_translator_funcs dcn42_translator_funcs = { - .get_soc_bb = dcn401_get_soc_bb, + .get_soc_bb = dcn42_get_soc_bb, .get_ip_caps = dcn42_get_ip_caps, }; @@ -25,3 +181,4 @@ void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and { soc_and_ip_translator->translator_funcs = &dcn42_translator_funcs; } + diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h index 914dcbb369a75..1dded54261521 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h @@ -12,5 +12,6 @@ #include "soc_and_ip_translator.h" void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator); +void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); #endif /* _DCN42_SOC_AND_IP_TRANSLATOR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c index 0fc0e5a6c171c..bc1487d4ebda8 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c @@ -4,6 +4,7 @@ #include "soc_and_ip_translator.h" #include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h" +#include "soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h" static void dc_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator, enum dce_version dc_version) @@ -12,6 +13,9 @@ static void dc_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc case DCN_VERSION_4_01: dcn401_construct_soc_and_ip_translator(soc_and_ip_translator); break; + case DCN_VERSION_4_2: + dcn42_construct_soc_and_ip_translator(soc_and_ip_translator); + break; default: break; } diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h new file mode 100644 index 0000000000000..aa3ef3a340134 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _clk_15_0_0_OFFSET_HEADER +#define _clk_15_0_0_OFFSET_HEADER + +// addressBlock: clk_clk8_0_SmuClkDec +// base address: 0x6e000 +#define regCLK8_CLK0_DS_CNTL 0x4c14 +#define regCLK8_CLK0_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK1_DS_CNTL 0x4c1c +#define regCLK8_CLK1_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK2_DS_CNTL 0x4c24 +#define regCLK8_CLK2_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK3_DS_CNTL 0x4c2c +#define regCLK8_CLK3_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK4_DS_CNTL 0x4c34 +#define regCLK8_CLK4_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK0_BYPASS_CNTL 0x4c1a +#define regCLK8_CLK0_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK1_BYPASS_CNTL 0x4c22 +#define regCLK8_CLK1_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK2_BYPASS_CNTL 0x4c2a +#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK3_BYPASS_CNTL 0x4c32 +#define regCLK8_CLK3_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK4_BYPASS_CNTL 0x4c3a +#define regCLK8_CLK4_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK_TICK_CNT_CONFIG_REG 0x4c51 +#define regCLK8_CLK_TICK_CNT_CONFIG_REG_BASE_IDX 0 +#define regCLK8_CLK_TICK_CNT_STATUS 0x4c52 +#define regCLK8_CLK_TICK_CNT_STATUS_BASE_IDX 0 +#define regCLK8_CLK0_CURRENT_CNT 0x4c53 +#define regCLK8_CLK0_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK1_CURRENT_CNT 0x4c54 +#define regCLK8_CLK1_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK2_CURRENT_CNT 0x4c55 +#define regCLK8_CLK2_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK3_CURRENT_CNT 0x4c56 +#define regCLK8_CLK3_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK4_CURRENT_CNT 0x4c57 +#define regCLK8_CLK4_CURRENT_CNT_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h new file mode 100644 index 0000000000000..c78622d06e1be --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _clk_15_0_0_SH_MASK_HEADER +#define _clk_15_0_0_SH_MASK_HEADER + +// addressBlock: clk_clk8_0_SmuClkDec +//CLK8_CLK_TICK_CNT_CONFIG_REG +#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT 0x0 +#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK 0xFFFFL +//CLK8_CLK0_BYPASS_CNTL +#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK1_BYPASS_CNTL +#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK2_BYPASS_CNTL +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK3_BYPASS_CNTL +#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK4_BYPASS_CNTL +#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK0_DS_CNTL +#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK1_DS_CNTL +#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK2_DS_CNTL +#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK3_DS_CNTL +#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK4_DS_CNTL +#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS_MASK 0x00000010L + +#endif From b6d6d4c2439eb0a0cd6543d4bb892499679f3151 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Tue, 3 Mar 2026 12:00:55 -0500 Subject: [PATCH 1807/2070] drm/amd/display: Add DML support for dcn42 DML support for DCN 4.2 Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/dml2_0/Makefile | 3 + .../dml2_0/dml21/dml21_translation_helper.c | 13 ++ .../dc/dml2_0/dml21/inc/dml_top_types.h | 1 + .../dml21/src/dml2_core/dml2_core_dcn4.c | 111 ++++++++++++++++++ .../dml21/src/dml2_core/dml2_core_dcn4.h | 1 + .../dml21/src/dml2_core/dml2_core_factory.c | 8 ++ .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 34 ++++++ .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h | 1 + .../dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 5 + .../dml21/src/dml2_mcg/dml2_mcg_dcn42.c | 76 ++++++++++++ .../dml21/src/dml2_mcg/dml2_mcg_dcn42.h | 11 ++ .../dml21/src/dml2_mcg/dml2_mcg_factory.c | 5 + .../dml21/src/dml2_top/dml2_top_interfaces.c | 1 + 13 files changed, 270 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile index 66b4afa57742d..d681d4f09850b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile @@ -128,6 +128,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2 CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) @@ -145,6 +146,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(d CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) @@ -162,6 +164,7 @@ DML21 += src/dml2_core/dml2_core_dcn4_calcs.o DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o DML21 += src/dml2_dpmm/dml2_dpmm_factory.o DML21 += src/dml2_mcg/dml2_mcg_dcn4.o +DML21 += src/dml2_mcg/dml2_mcg_dcn42.o DML21 += src/dml2_mcg/dml2_mcg_factory.o DML21 += src/dml2_pmo/dml2_pmo_dcn3.o DML21 += src/dml2_pmo/dml2_pmo_factory.o diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index cd12b7a6da657..6cc03391fff6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -45,6 +45,9 @@ static enum dml2_project_id dml21_dcn_revision_to_dml2_project_id(enum dce_versi case DCN_VERSION_4_01: project_id = dml2_project_dcn4x_stage2_auto_drr_svp; break; + case DCN_VERSION_4_2: + project_id = dml2_project_dcn42; + break; default: project_id = dml2_project_invalid; DC_ERR("unsupported dcn version for DML21!"); @@ -615,6 +618,13 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm case DC_CM2_GPU_MEM_SIZE_171717: plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; break; + case DC_CM2_GPU_MEM_SIZE_333333: + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube; + break; + // handling when use case and HW support available + case DC_CM2_GPU_MEM_SIZE_454545: + case DC_CM2_GPU_MEM_SIZE_656565: + break; case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: default: //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined @@ -824,6 +834,9 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz; context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period; + context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/ } static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index 943fd3f040c3a..c854515b49a32 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -19,6 +19,7 @@ enum dml2_project_id { dml2_project_dcn4x_stage1, dml2_project_dcn4x_stage2, dml2_project_dcn4x_stage2_auto_drr_svp, + dml2_project_dcn42, }; enum dml2_pstate_change_support { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c index eba948e187c11..608b4a305c656 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c @@ -78,6 +78,86 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = { .subvp_swath_height_margin_lines = 16, }; +struct dml2_core_ip_params core_dcn42_ip_caps_base = { + .vblank_nom_default_us = 668, + .remote_iommu_outstanding_translations = 256, + .rob_buffer_size_kbytes = 64, + .config_return_buffer_size_in_kbytes = 1792, + .config_return_buffer_segment_size_in_kbytes = 64, + .compressed_buffer_segment_size_in_kbytes = 64, + .dpte_buffer_size_in_pte_reqs_luma = 68, + .dpte_buffer_size_in_pte_reqs_chroma = 36, + .pixel_chunk_size_kbytes = 8, + .alpha_pixel_chunk_size_kbytes = 4, + .min_pixel_chunk_size_bytes = 1024, + .writeback_chunk_size_kbytes = 8, + .line_buffer_size_bits = 1171920, + .max_line_buffer_lines = 32, + .writeback_interface_buffer_size_kbytes = 90, + + //Number of pipes after DCN Pipe harvesting + .max_num_dpp = 4, + .max_num_otg = 4, + .max_num_opp = 4, + .max_num_wb = 1, + .max_dchub_pscl_bw_pix_per_clk = 4, + .max_pscl_lb_bw_pix_per_clk = 2, + .max_lb_vscl_bw_pix_per_clk = 4, + .max_vscl_hscl_bw_pix_per_clk = 4, + .max_hscl_ratio = 6, + .max_vscl_ratio = 6, + .max_hscl_taps = 8, + .max_vscl_taps = 8, + .dispclk_ramp_margin_percent = 1, + .dppclk_delay_subtotal = 47, + .dppclk_delay_scl = 50, + .dppclk_delay_scl_lb_only = 16, + .dppclk_delay_cnvc_formatter = 28, + .dppclk_delay_cnvc_cursor = 6, + .cursor_buffer_size = 42, + .cursor_chunk_size = 2, + .dispclk_delay_subtotal = 125, + .max_inter_dcn_tile_repeaters = 8, + .writeback_max_hscl_ratio = 1, + .writeback_max_vscl_ratio = 1, + .writeback_min_hscl_ratio = 1, + .writeback_min_vscl_ratio = 1, + .writeback_max_hscl_taps = 1, + .writeback_max_vscl_taps = 1, + .writeback_line_buffer_buffer_size = 0, + .num_dsc = 4, + .maximum_dsc_bits_per_component = 12, + .maximum_pixels_per_line_per_dsc_unit = 5760, + .dsc422_native_support = true, + .dcc_supported = true, + .ptoi_supported = false, + + .cursor_64bpp_support = true, + .dynamic_metadata_vm_enabled = false, + + .max_num_hdmi_frl_outputs = 0, + .max_num_dp2p0_outputs = 2, + .max_num_dp2p0_streams = 4, + .imall_supported = 1, + .max_flip_time_us = 110, + .max_flip_time_lines = 50, + .words_per_channel = 16, + + .subvp_fw_processing_delay_us = 15, + .subvp_pstate_allow_width_us = 20, + .subvp_swath_height_margin_lines = 16, + + .dcn_mrq_present = 1, + .zero_size_buffer_entries = 512, + .compbuf_reserved_space_zs = 64, + .dcc_meta_buffer_size_bytes = 6272, + .meta_chunk_size_kbytes = 2, + .min_meta_chunk_size_bytes = 256, + + .dchub_arb_to_ret_delay = 102, + .hostvm_mode = 1, +}; + static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *ip_caps, const struct dml2_core_ip_params *ip_params) { ip_caps->pipe_count = ip_params->max_num_dpp; @@ -153,6 +233,37 @@ bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out) return true; } +bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out) +{ + struct dml2_core_instance *core = in_out->instance; + + if (!in_out->minimum_clock_table) + return false; + else + core->minimum_clock_table = in_out->minimum_clock_table; + + if (in_out->explicit_ip_bb && in_out->explicit_ip_bb_size > 0) { + memcpy(&core->clean_me_up.mode_lib.ip, in_out->explicit_ip_bb, in_out->explicit_ip_bb_size); + + // FIXME_STAGE2: + // DV still uses stage1 ip_param_st for each variant, need to patch the ip_caps with ip_param info + // Should move DV to use ip_caps but need move more overrides to ip_caps + patch_ip_caps_with_explicit_ip_params(in_out->ip_caps, in_out->explicit_ip_bb); + core->clean_me_up.mode_lib.ip.subvp_pstate_allow_width_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us; + core->clean_me_up.mode_lib.ip.subvp_fw_processing_delay_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us; + core->clean_me_up.mode_lib.ip.subvp_swath_height_margin_lines = core_dcn4_ip_caps_base.subvp_swath_height_margin_lines; + } else { + memcpy(&core->clean_me_up.mode_lib.ip, &core_dcn42_ip_caps_base, sizeof(struct dml2_core_ip_params)); + patch_ip_params_with_ip_caps(&core->clean_me_up.mode_lib.ip, in_out->ip_caps); + core->clean_me_up.mode_lib.ip.imall_supported = false; + } + + memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb)); + memcpy(&core->clean_me_up.mode_lib.ip_caps, in_out->ip_caps, sizeof(struct dml2_ip_capabilities)); + + return true; +} + static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main, const struct dml2_implicit_svp_meta *meta) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h index a68bb001a3465..5c26d819a6739 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h @@ -5,6 +5,7 @@ #ifndef __DML2_CORE_DCN4_H__ #define __DML2_CORE_DCN4_H__ bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out); +bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out); bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out); bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out); bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c index cc4f0663c6d67..67e307fa43108 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c @@ -30,6 +30,14 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance out->calculate_mcache_allocation = &core_dcn4_calculate_mcache_allocation; result = true; break; + case dml2_project_dcn42: + out->initialize = &core_dcn42_initialize; + out->mode_support = &core_dcn4_mode_support; + out->mode_programming = &core_dcn4_mode_programming; + out->populate_informative = &core_dcn4_populate_informative; + out->calculate_mcache_allocation = &core_dcn4_calculate_mcache_allocation; + result = true; + break; case dml2_project_invalid: default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c index 9d7741fd0adb1..037272d2c2e64 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c @@ -802,3 +802,37 @@ bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_ return true; } + +bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out) +{ + const struct dml2_display_cfg *display_cfg = &in_out->display_cfg->display_config; + const struct dml2_core_internal_display_mode_lib *mode_lib = &in_out->core->clean_me_up.mode_lib; + struct dml2_dchub_global_register_set *dchubbub_regs = &in_out->programming->global_regs; + + double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz; + + /* set A */ + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].fclk_pstate = (int unsigned)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter = (int unsigned)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit = (int unsigned)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].temp_read_or_ppt = (int unsigned)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].uclk_pstate = (int unsigned)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].urgent = (int unsigned)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].usr = (int unsigned)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_trip_to_mem = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_flip = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthImmediateFlip * 1000); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_nom = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidth * 1000); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_mall = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthMALL * 1000); + + /* set B */ + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A]; + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_C] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A]; + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_D] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A]; + + dchubbub_regs->num_watermark_sets = 4; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h index e7b58f2efda4b..5fbd07e238a8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h @@ -10,5 +10,6 @@ bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out); +bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index dfd01440737df..80d4932bf1544 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -41,6 +41,11 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance out->map_watermarks = &dpmm_dcn4_map_watermarks; result = true; break; + case dml2_project_dcn42: + out->map_mode_to_soc_dpm = &dpmm_dcn4_map_mode_to_soc_dpm; + out->map_watermarks = &dpmm_dcn42_map_watermarks; + result = true; + break; case dml2_project_invalid: default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c new file mode 100644 index 0000000000000..1f67cbc2c2366 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dml2_mcg_dcn42.h" +#include "dml_top_soc_parameter_types.h" + +static unsigned long long uclk_to_dram_bw_kbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, unsigned long wck_ratio) +{ + unsigned long long bw_kbps = 0; + + bw_kbps = (unsigned long long) uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * wck_ratio * 2; + return bw_kbps; +} + +static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table) +{ + int i; + + for (i = 0; i < soc_bb->clk_table.fclk.num_clk_values; i++) { + if (i < soc_bb->clk_table.uclk.num_clk_values) { + min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = + uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config, soc_bb->clk_table.wck_ratio.clk_values_khz[i]); + min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[i]; + } else { + min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = min_table->dram_bw_table.entries[soc_bb->clk_table.uclk.num_clk_values - 1].pre_derate_dram_bw_kbps; + min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[soc_bb->clk_table.uclk.num_clk_values - 1]; + } + + min_table->dram_bw_table.entries[i].min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[i]; + min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; + } + min_table->dram_bw_table.num_entries = soc_bb->clk_table.fclk.num_clk_values; + + return true; +} + +static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table) +{ + bool result; + + if (!soc_bb || !min_table) + return false; + + + if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE) + return false; + + min_table->fixed_clocks_khz.amclk = 0; + min_table->fixed_clocks_khz.dprefclk = soc_bb->dprefclk_mhz * 1000; + min_table->fixed_clocks_khz.pcierefclk = soc_bb->pcie_refclk_mhz * 1000; + min_table->fixed_clocks_khz.dchubrefclk = soc_bb->dchub_refclk_mhz * 1000; + min_table->fixed_clocks_khz.xtalclk = soc_bb->xtalclk_mhz * 1000; + + min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dispclk.num_clk_values - 1]; + min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppclk.num_clk_values - 1]; + min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dscclk.num_clk_values - 1]; + min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values - 1]; + min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phyclk.num_clk_values - 1]; + + min_table->max_ss_clocks_khz.dispclk = (unsigned int)((double)min_table->max_clocks_khz.dispclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); + min_table->max_ss_clocks_khz.dppclk = (unsigned int)((double)min_table->max_clocks_khz.dppclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); + min_table->max_ss_clocks_khz.dtbclk = (unsigned int)((double)min_table->max_clocks_khz.dtbclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); + + min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfclk.num_clk_values - 1]; + min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_clk_values - 1]; + + result = build_min_clk_table_coarse_grained(soc_bb, min_table); + + return result; +} + +bool mcg_dcn42_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out) +{ + return build_min_clock_table(in_out->soc_bb, in_out->min_clk_table); +} diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h new file mode 100644 index 0000000000000..ad8a847a0a178 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DML2_MCG_DCN42_H__ +#define __DML2_MCG_DCN42_H__ + +#include "dml2_internal_shared_types.h" + +bool mcg_dcn42_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c index c60b8fe90819d..1cff62b63e720 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c @@ -4,6 +4,7 @@ #include "dml2_mcg_factory.h" #include "dml2_mcg_dcn4.h" +#include "dml2_mcg_dcn42.h" #include "dml2_external_lib_deps.h" static bool dummy_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out) @@ -30,6 +31,10 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance * out->build_min_clock_table = &mcg_dcn4_build_min_clock_table; result = true; break; + case dml2_project_dcn42: + out->build_min_clock_table = &mcg_dcn42_build_min_clock_table; + result = true; + break; case dml2_project_invalid: default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c index 5a33e2f357f45..04860b6790df1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c @@ -17,6 +17,7 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out) case dml2_project_dcn4x_stage1: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: + case dml2_project_dcn42: return dml2_top_soc15_initialize_instance(in_out); case dml2_project_invalid: default: From 95d64a261903cc28aed940b2de959c7382e1f646 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 5 Mar 2026 12:56:09 -0500 Subject: [PATCH 1808/2070] drm/amd/display: Sync dcn42 with DC 3.2.373 This patch provides a bulk merge to align driver support for DCN42 with Display Core version 3.2.373. It includes upgrade for: - clk_mgr - dml2/dml21 - optc - hubp - mpc - optc - hwseq Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 11 +- .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 141 +++-- .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 95 ++- .../gpu/drm/amd/display/dc/core/dc_stream.c | 41 +- .../gpu/drm/amd/display/dc/core/dc_surface.c | 9 + drivers/gpu/drm/amd/display/dc/dc.h | 59 +- .../gpu/drm/amd/display/dc/dc_bios_types.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_plane.h | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 24 + .../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 20 + .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 16 + .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 13 + .../dml2_0/dml21/dml21_translation_helper.c | 30 +- .../amd/display/dc/dml2_0/dml21/dml21_utils.c | 1 + .../display/dc/dml2_0/dml21/dml21_wrapper.c | 14 +- .../dml21/inc/bounding_boxes/dcn42_soc_bb.h | 306 ++++------ .../dml21/inc/dml_top_display_cfg_types.h | 13 + .../dc/dml2_0/dml21/inc/dml_top_types.h | 2 + .../dml21/src/dml2_core/dml2_core_factory.c | 1 + .../dml21/src/dml2_core/dml2_core_utils.c | 63 +- .../dml21/src/dml2_core/dml2_core_utils.h | 2 + .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 1 - .../dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 1 + .../dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h | 2 +- .../dml21/src/dml2_mcg/dml2_mcg_dcn42.h | 3 +- .../dml21/src/dml2_mcg/dml2_mcg_factory.c | 1 + .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 6 + .../dml21/src/dml2_pmo/dml2_pmo_factory.c | 4 +- .../dml21/src/dml2_pmo/dml2_pmo_factory.h | 2 +- .../dml21/src/dml2_top/dml2_top_interfaces.c | 1 + .../dml21/src/dml2_top/dml2_top_legacy.c | 1 - .../src/inc/dml2_internal_shared_types.h | 3 + .../drm/amd/display/dc/dml2_0/dml2_wrapper.c | 3 +- .../amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 2 + .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 23 +- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 5 + .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 201 ++++--- .../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 23 +- .../amd/display/dc/hubp/dcn42/dcn42_hubp.c | 85 ++- .../amd/display/dc/hubp/dcn42/dcn42_hubp.h | 16 +- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 136 +++-- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 412 +++++-------- .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 553 +++--------------- .../amd/display/dc/hwss/dcn42/dcn42_hwseq.h | 10 +- .../amd/display/dc/hwss/dcn42/dcn42_init.c | 8 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 36 +- .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 18 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 112 ++-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 + .../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 177 +++--- .../amd/display/dc/mpc/dcn401/dcn401_mpc.h | 25 +- .../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c | 390 ++---------- .../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h | 50 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 2 +- .../amd/display/dc/optc/dcn42/dcn42_optc.c | 105 +++- .../amd/display/dc/optc/dcn42/dcn42_optc.h | 13 +- .../dc/resource/dcn42/dcn42_resource.c | 10 +- .../dcn401/dcn401_soc_and_ip_translator.c | 3 + .../dcn42/dcn42_soc_and_ip_translator.c | 12 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 38 +- .../include/asic_reg/dcn/dcn_4_2_0_offset.h | 2 + .../include/asic_reg/dcn/dcn_4_2_0_sh_mask.h | 9 + 63 files changed, 1493 insertions(+), 1879 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index f56f3ee81a223..82877f7b3b6fb 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -794,13 +794,11 @@ static enum bp_result bios_parser_external_encoder_control( static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id, - struct graphics_object_id ext_enc_id) + enum engine_id engine_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; - struct bp_external_encoder_control ext_cntl = {0}; enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; @@ -826,13 +824,6 @@ static enum bp_result bios_parser_dac_load_detection( bp_params.engine_id = engine_id; bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); - } else if (ext_enc_id.id) { - if (!bp->cmd_tbl.external_encoder_control) - return BP_RESULT_UNSUPPORTED; - - ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT; - ext_cntl.encoder_id = ext_enc_id; - bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl); } if (bp_result != BP_RESULT_OK) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index cbb79789a5320..97c9f0ce13e40 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -87,21 +87,18 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn42 = { #define TO_CLK_MGR_DCN42(clk_mgr_int)\ container_of(clk_mgr_int, struct clk_mgr_dcn42, base) -int dcn42_get_active_display_cnt_wa( - struct dc *dc, - struct dc_state *context, - int *all_active_disps) +bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context) { - int i, display_count = 0; - bool tmds_present = false; + int i, active_count = 0; for (i = 0; i < context->stream_count; i++) { const struct dc_stream_state *stream = context->streams[i]; - if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || - stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || - stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) - tmds_present = true; + /* Checking stream / link detection ensuring that PHY is active*/ + if (dc_is_hdmi_signal(stream->signal) || + dc_is_dvi_signal(stream->signal) || + (dc_is_dp_signal(stream->signal) && !stream->dpms_off)) + active_count++; } for (i = 0; i < dc->link_count; i++) { @@ -110,15 +107,10 @@ int dcn42_get_active_display_cnt_wa( /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ if (link->link_enc && link->link_enc->funcs->is_dig_enabled && link->link_enc->funcs->is_dig_enabled(link->link_enc)) - display_count++; + active_count++; } - if (all_active_disps != NULL) - *all_active_disps = display_count; - /* WA for hang on HDMI after display off back on*/ - if (display_count == 0 && tmds_present) - display_count = 1; - return display_count; + return active_count > 0; } static uint32_t dcn42_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock) @@ -223,20 +215,18 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; struct dc *dc = clk_mgr_base->ctx->dc; - int display_count = 0; bool update_dppclk = false; bool update_dispclk = false; bool dpp_clock_lowered = false; - int all_active_disps = 0; + bool has_active_display; if (dc->work_arounds.skip_clock_update) return; - display_count = dcn42_get_active_display_cnt_wa(dc, context, &all_active_disps); + has_active_display = dcn42_has_active_display(dc, context); if (new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz < 590000) new_clocks->ref_dtbclk_khz = 600000; - /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything * also if safe to lower is false, we just go in the higher state @@ -256,7 +246,7 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, /* check that we're not already in lower */ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { /* if we can go lower, go lower */ - if (display_count == 0) + if (has_active_display == false) clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; } } else { @@ -314,7 +304,7 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && - (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { + (new_clocks->dispclk_khz > 0 || (safe_to_lower && has_active_display == false))) { int requested_dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -461,7 +451,6 @@ static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs // REGISTER VALUES DC_LOG_SMU("reg_name,value,clk_type\n"); - DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", internal.CLK8_CLK3_CURRENT_CNT); @@ -594,6 +583,7 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) else clk_mgr_base->dp_dto_source_clock_in_khz = clk_mgr_base->dprefclk_khz; + DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz); dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; @@ -602,6 +592,12 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) clk_mgr_base->clks.dtbclk_en = true; } + if (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels != 0) { + /*skip to get clock table and notify pmfw watermark range again*/ + DC_LOG_SMU("skip to get dpm_clks from pmfw from resume and acr\n"); + return; + } + smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem( clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART, @@ -708,10 +704,9 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) /* DTBCLK*/ clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; - /* Refresh bounding box */ clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( - clk_mgr_base->ctx->dc, clk_mgr_base->bw_params); + clk_mgr_base->ctx->dc, clk_mgr_base->bw_params); } } if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) @@ -823,7 +818,6 @@ static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) } } -/* Exposed for dcn42b reuse */ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) { int i, num_valid_sets; @@ -882,18 +876,42 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { + int i = 0; + struct dcn42_watermarks *table = NULL; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_dcn42 *clk_mgr_dcn42 = TO_CLK_MGR_DCN42(clk_mgr); - struct dcn42_watermarks *table = clk_mgr_dcn42->smu_wm_set.wm_set; if (!clk_mgr->smu_ver) return; + /*send once already skip*/ + if (clk_mgr_base->bw_params->wm_table.entries[WM_A].valid == true) + return; + clk_mgr_dcn42->smu_wm_set.wm_set = (struct dcn42_watermarks *)dm_helpers_allocate_gpu_mem( + clk_mgr->base.ctx, + DC_MEM_ALLOC_TYPE_GART, + sizeof(struct dcn42_watermarks), + &clk_mgr_dcn42->smu_wm_set.mc_address.quad_part); + + ASSERT(clk_mgr_dcn42->smu_wm_set.wm_set); + + table = clk_mgr_dcn42->smu_wm_set.wm_set; if (!table || clk_mgr_dcn42->smu_wm_set.mc_address.quad_part == 0) return; memset(table, 0, sizeof(*table)); + /*same as previous asic, set wm valid before building watermark ranges*/ + for (i = 0; i < WM_SET_COUNT; i++) { + clk_mgr_base->bw_params->wm_table.entries[i].wm_inst = i; + if (i >= clk_mgr_base->bw_params->clk_table.num_entries) { + clk_mgr_base->bw_params->wm_table.entries[i].valid = false; + continue; + } + clk_mgr_base->bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; + clk_mgr_base->bw_params->wm_table.entries[i].valid = true; + } + /* build watermark_range will check this valid range*/ dcn42_build_watermark_ranges(clk_mgr_base->bw_params, table); dcn42_smu_set_dram_addr_high(clk_mgr, @@ -901,18 +919,21 @@ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) dcn42_smu_set_dram_addr_low(clk_mgr, clk_mgr_dcn42->smu_wm_set.mc_address.low_part); dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr); + + if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, + clk_mgr_dcn42->smu_wm_set.wm_set); + } void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base) { - int display_count; struct dc *dc = clk_mgr_base->ctx->dc; struct dc_state *context = dc->current_state; if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { - display_count = dcn42_get_active_display_cnt_wa(dc, context, NULL); /* if we can go lower, go lower */ - if (display_count == 0) + if (dcn42_has_active_display(dc, context) == false) clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; } @@ -1093,14 +1114,7 @@ void dcn42_clk_mgr_construct( clk_mgr->base.dprefclk_ss_divider = 1000; clk_mgr->base.ss_on_dprefclk = false; clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/ - - clk_mgr->smu_wm_set.wm_set = (struct dcn42_watermarks *)dm_helpers_allocate_gpu_mem( - clk_mgr->base.base.ctx, - DC_MEM_ALLOC_TYPE_GART, - sizeof(struct dcn42_watermarks), - &clk_mgr->smu_wm_set.mc_address.quad_part); - - ASSERT(clk_mgr->smu_wm_set.wm_set); + clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; /* Changed from DCN3.2_clock_frequency doc to match * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz / @@ -1108,34 +1122,31 @@ void dcn42_clk_mgr_construct( */ clk_mgr->base.base.dprefclk_khz = 600000; - clk_mgr->base.smu_present = false; - clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base); - if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1) - clk_mgr->base.smu_present = true; - - if (ctx->dc_bios->integrated_info) { - clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; - - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) - dcn42_bw_params.wm_table = lpddr5_wm_table; - else - dcn42_bw_params.wm_table = ddr5_wm_table; - - dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; - dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; - dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 4; - } - - /* in case we don't get a value from the BIOS, use default */ - if (clk_mgr->base.base.dentist_vco_freq_khz == 0) - clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */ + clk_mgr->base.smu_present = false; + clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base); + if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1) + clk_mgr->base.smu_present = true; + + if (ctx->dc_bios->integrated_info) { + clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; + + if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) + dcn42_bw_params.wm_table = lpddr5_wm_table; + else + dcn42_bw_params.wm_table = ddr5_wm_table; + dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; + dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; + dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; + clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); + clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + } + /* in case we don't get a value from the BIOS, use default */ + if (clk_mgr->base.base.dentist_vco_freq_khz == 0) + clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */ - /* Saved clocks configured at boot for debug purposes */ - dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); + /* Saved clocks configured at boot for debug purposes */ + dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); - if (clk_mgr->base.smu_present) - clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); - clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; dce_clock_read_ss_info(&clk_mgr->base); /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h index 99fcdb602c621..5ad027a9edaf0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h @@ -59,7 +59,6 @@ void dcn42_clk_mgr_construct(struct dc_context *ctx, void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); -/* Exposed for dcn42b reuse */ void dcn42_init_single_clock(unsigned int *entry_0, uint32_t *smu_entry_0, uint8_t num_levels); @@ -76,4 +75,5 @@ int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower); void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz); bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base); +bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context); #endif //__DCN42_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 29888c98e2c53..373b613d1805b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2896,16 +2896,27 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->blend_tf || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { + if (u->cm || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { update_flags->bits.gamma_change = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->lut3d_func || u->func_shaper) { + if (u->cm && (u->cm->flags.bits.lut3d_enable || u->surface->cm.flags.bits.lut3d_enable)) { update_flags->bits.lut_3d = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + if (u->cm && u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable && + u->cm->flags.bits.lut3d_enable && u->surface->cm.flags.bits.lut3d_enable) { + /* Toggling 3DLUT loading between DMA and Host is illegal */ + BREAK_TO_DEBUGGER(); + } + + if (u->cm && u->cm->flags.bits.lut3d_enable && !u->cm->flags.bits.lut3d_dma_enable) { + /* Host loading 3DLUT requires full update but only stream lock */ + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); + } + if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { // TODO: Should be fast? @@ -2920,24 +2931,15 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } - if (u->cm2_params) { - if (u->cm2_params->component_settings.shaper_3dlut_setting != u->surface->mcm_shaper_3dlut_setting - || u->cm2_params->component_settings.lut1d_enable != u->surface->mcm_lut1d_enable - || u->cm2_params->cm2_luts.lut3d_data.lut3d_src != u->surface->mcm_luts.lut3d_data.lut3d_src) { - update_flags->bits.mcm_transfer_function_enable_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - } - } - - if (update_flags->bits.lut_3d && - u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + if (u->cm_hist_control) { + update_flags->bits.cm_hist_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (check_config->enable_legacy_fast_update && (update_flags->bits.gamma_change || update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || + update_flags->bits.cm_hist_change || update_flags->bits.coeff_reduction_change)) { elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } @@ -3169,6 +3171,11 @@ static void copy_surface_update_to_plane( surface->gamma_correction.type = srf_update->gamma->type; } + if (srf_update->cm_hist_control) { + memcpy(&surface->cm_hist_control, + srf_update->cm_hist_control, + sizeof(surface->cm_hist_control)); + } if (srf_update->in_transfer_func) { surface->in_transfer_func.sdr_ref_white_level = @@ -3182,24 +3189,12 @@ static void copy_surface_update_to_plane( sizeof(struct dc_transfer_func_distributed_points)); } - if (srf_update->cm2_params) { - surface->mcm_shaper_3dlut_setting = srf_update->cm2_params->component_settings.shaper_3dlut_setting; - surface->mcm_lut1d_enable = srf_update->cm2_params->component_settings.lut1d_enable; - surface->mcm_luts = srf_update->cm2_params->cm2_luts; - } - - if (srf_update->func_shaper) { - memcpy(&surface->in_shaper_func, srf_update->func_shaper, - sizeof(surface->in_shaper_func)); - - if (surface->mcm_shaper_3dlut_setting >= DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER) - surface->mcm_luts.shaper = &surface->in_shaper_func; + /* Shaper, 3DLUT, 1DLUT */ + if (srf_update->cm) { + memcpy(&surface->cm, srf_update->cm, + sizeof(surface->cm)); } - if (srf_update->lut3d_func) - memcpy(&surface->lut3d_func, srf_update->lut3d_func, - sizeof(surface->lut3d_func)); - if (srf_update->hdr_mult.value) surface->hdr_mult = srf_update->hdr_mult; @@ -3208,17 +3203,6 @@ static void copy_surface_update_to_plane( surface->sdr_white_level_nits = srf_update->sdr_white_level_nits; - if (srf_update->blend_tf) { - memcpy(&surface->blend_tf, srf_update->blend_tf, - sizeof(surface->blend_tf)); - - if (surface->mcm_lut1d_enable) - surface->mcm_luts.lut1d_func = &surface->blend_tf; - } - - if (srf_update->cm2_params || srf_update->blend_tf) - surface->lut_bank_a = !surface->lut_bank_a; - if (srf_update->input_csc_color_matrix) surface->input_csc_color_matrix = *srf_update->input_csc_color_matrix; @@ -4503,11 +4487,9 @@ static void commit_planes_for_stream(struct dc *dc, if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; - if (srf_updates[i].cm2_params && - srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src == - DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM && - srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting == - DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT && + if (srf_updates[i].cm && + srf_updates[i].cm->flags.bits.lut3d_enable && + srf_updates[i].cm->flags.bits.lut3d_dma_enable && dc->hwss.trigger_3dlut_dma_load) dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx); @@ -5075,6 +5057,7 @@ void populate_fast_updates(struct dc_fast_update *fast_update, fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix; fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor; fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix; + fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control; } } @@ -5092,6 +5075,7 @@ static bool fast_updates_exist(const struct dc_fast_update *fast_update, int sur fast_update[i].gamut_remap_matrix || fast_update[i].input_csc_color_matrix || fast_update[i].cursor_csc_color_matrix || + fast_update[i].cm_hist_control || fast_update[i].coeff_reduction_factor) return true; } @@ -5112,6 +5096,7 @@ bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_ fast_update[i].gamma || fast_update[i].gamut_remap_matrix || fast_update[i].coeff_reduction_factor || + fast_update[i].cm_hist_control || fast_update[i].cursor_csc_color_matrix) return true; } @@ -5153,6 +5138,12 @@ static bool full_update_required( const struct dc_stream_update *stream_update, const struct dc_stream_state *stream) { + const union dc_plane_cm_flags blend_only_flags = { + .bits = { + .blend_enable = 1, + } + }; + if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) return true; @@ -5165,14 +5156,12 @@ static bool full_update_required( (srf_updates[i].sdr_white_level_nits && srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || srf_updates[i].in_transfer_func || - srf_updates[i].func_shaper || - srf_updates[i].lut3d_func || srf_updates[i].surface->force_full_update || (srf_updates[i].flip_addr && srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || - (srf_updates[i].cm2_params && - (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting || - srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)))) + (srf_updates[i].cm && + ((srf_updates[i].cm->flags.all != blend_only_flags.all && srf_updates[i].cm->flags.all != 0) || + (srf_updates[i].surface->cm.flags.all != blend_only_flags.all && srf_updates[i].surface->cm.flags.all != 0))))) return true; } @@ -6900,7 +6889,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa struct dc_plane_state *plane_state = pipe_ctx->plane_state; /* MPCC blending tree and mode control - capture actual blend configuration */ - state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0; + state->mpc.mpcc_mode[i] = (plane_state->cm.blend_func.type != TF_TYPE_BYPASS) ? 1 : 0; state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0; state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0; state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 87c0cf7e290ea..44e17329c6373 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -33,6 +33,7 @@ #include "dc_dmub_srv.h" #include "dc_state_priv.h" #include "dc_stream_priv.h" +#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER dc->ctx->logger #ifndef MIN @@ -171,10 +172,12 @@ struct dc_stream_state *dc_create_stream_for_sink( goto fail; stream = kzalloc(sizeof(struct dc_stream_state), GFP_ATOMIC); + if (stream == NULL) goto fail; stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC); + if (stream->update_scratch == NULL) goto fail; @@ -245,7 +248,6 @@ const struct dc_stream_status *dc_stream_get_status_const( const struct dc_stream_state *stream) { struct dc *dc = stream->ctx->dc; - return dc_state_get_stream_status(dc->current_state, stream); } @@ -257,6 +259,7 @@ void program_cursor_attributes( struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + bool unlock_dmub = false; if (!stream) return; @@ -275,6 +278,12 @@ void program_cursor_attributes( if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); } else { + if (dc->hwss.dmub_hw_control_lock && pipe_ctx->stream && + should_use_dmub_inbox0_lock_for_link(dc, pipe_ctx->stream->link)) { + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, true); + unlock_dmub = true; + } + dc->hwss.cursor_lock(dc, pipe_to_program, true); if (pipe_to_program->next_odm_pipe) dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); @@ -297,6 +306,9 @@ void program_cursor_attributes( dc->hwss.cursor_lock(dc, pipe_to_program, false); if (pipe_to_program->next_odm_pipe) dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); + + if (unlock_dmub) + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, false); } } } @@ -404,6 +416,7 @@ void program_cursor_position( struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); + bool unlock_dmub = false; if (!stream) return; @@ -423,10 +436,16 @@ void program_cursor_position( if (!pipe_to_program) { pipe_to_program = pipe_ctx; - if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); - else + } else { + if (dc->hwss.dmub_hw_control_lock && pipe_ctx->stream && + should_use_dmub_inbox0_lock_for_link(dc, pipe_ctx->stream->link)) { + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, true); + unlock_dmub = true; + } dc->hwss.cursor_lock(dc, pipe_to_program, true); + } } dc->hwss.set_cursor_position(pipe_ctx); @@ -438,10 +457,14 @@ void program_cursor_position( } if (pipe_to_program) { - if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { dc->hwss.commit_cursor_offload_update(dc, pipe_to_program); - else + } else { dc->hwss.cursor_lock(dc, pipe_to_program, false); + + if (unlock_dmub) + dc->hwss.dmub_hw_control_lock(dc, dc->current_state, false); + } } } @@ -523,8 +546,10 @@ bool dc_stream_program_cursor_position( struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; /* trigger event on first pipe with current stream */ - if (stream == pipe_ctx->stream) { - pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + if (stream == pipe_ctx->stream && + pipe_ctx->stream_res.tg->funcs->program_manual_trigger) { + pipe_ctx->stream_res.tg->funcs->program_manual_trigger( + pipe_ctx->stream_res.tg); break; } } @@ -984,7 +1009,6 @@ void dc_stream_release_3dlut_for_stream( if (rmcm_3dlut) { rmcm_3dlut->isInUse = false; rmcm_3dlut->stream = NULL; - rmcm_3dlut->protection_bits = 0; } } @@ -996,7 +1020,6 @@ void dc_stream_init_rmcm_3dlut(struct dc *dc) for (int i = 0; i < num_rmcm; i++) { dc->res_pool->rmcm_3dlut[i].isInUse = false; dc->res_pool->rmcm_3dlut[i].stream = NULL; - dc->res_pool->rmcm_3dlut[i].protection_bits = 0; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 0971dfa258454..5d3a8a63b7cdb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -139,6 +139,9 @@ const struct dc_plane_status *dc_plane_get_status( if (pipe_ctx->plane_state && flags.bits.address) pipe_ctx->plane_state->status.is_flip_pending = false; + if (pipe_ctx->plane_state && flags.bits.histogram) + memset(&pipe_ctx->plane_state->status.cm_hist, 0, + sizeof(pipe_ctx->plane_state->status.cm_hist)); break; } @@ -154,6 +157,12 @@ const struct dc_plane_status *dc_plane_get_status( if (flags.bits.address) dc->hwss.update_pending_status(pipe_ctx); + if (flags.bits.histogram) { + struct dpp *dpp = pipe_ctx->plane_res.dpp; + + if (dpp && dpp->funcs->dpp_cm_hist_read) + dpp->funcs->dpp_cm_hist_read(dpp, &pipe_ctx->plane_state->status.cm_hist); + } } return plane_status; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d11126c320465..9379b6ebcac32 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1407,15 +1407,50 @@ struct lut_mem_mapping { struct dc_rmcm_3dlut { bool isInUse; const struct dc_stream_state *stream; - uint8_t protection_bits; }; struct dc_3dlut { struct kref refcount; struct tetrahedral_params lut_3d; - struct fixed31_32 hdr_multiplier; union dc_3dlut_state state; }; + +/* 3DLUT DMA (Fast Load) params */ +struct dc_3dlut_dma { + struct dc_plane_address addr; + enum dc_cm_lut_swizzle swizzle; + enum dc_cm_lut_pixel_format format; + uint16_t bias; /* FP1.5.10 */ + uint16_t scale; /* FP1.5.10 */ + enum dc_cm_lut_size size; +}; + +/* color manager */ +union dc_plane_cm_flags { + unsigned int all; + struct { + unsigned int shaper_enable : 1; + unsigned int lut3d_enable : 1; + unsigned int blend_enable : 1; + /* whether legacy (lut3d_func) or DMA is valid */ + unsigned int lut3d_dma_enable : 1; + /* RMCM lut to be used instead of MCM */ + unsigned int rmcm_enable : 1; + unsigned int reserved: 27; + } bits; +}; + +struct dc_plane_cm { + struct kref refcount; + struct dc_transfer_func shaper_func; + union { + struct dc_3dlut lut3d_func; + struct dc_3dlut_dma lut3d_dma; + }; + struct dc_transfer_func blend_func; + union dc_plane_cm_flags flags; +}; + /* * This structure is filled in by dc_surface_get_status and contains * the last requested address and the currently active address so the called @@ -1493,14 +1528,18 @@ struct dc_plane_state { struct fixed31_32 hdr_mult; struct colorspace_transform gamut_remap_matrix; - // TODO: No longer used, remove - struct dc_hdr_static_metadata hdr_static_ctx; - enum dc_color_space color_space; + bool lut_bank_a; + struct dc_hdr_static_metadata hdr_static_ctx; struct dc_3dlut lut3d_func; struct dc_transfer_func in_shaper_func; struct dc_transfer_func blend_tf; + enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; + bool mcm_lut1d_enable; + struct dc_cm2_func_luts mcm_luts; + enum mpcc_movable_cm_location mcm_location; + struct dc_plane_cm cm; struct dc_transfer_func *gamcor_tf; enum surface_pixel_format format; @@ -1537,11 +1576,6 @@ struct dc_plane_state { bool is_statically_allocated; enum chroma_cositing cositing; - enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; - bool mcm_lut1d_enable; - struct dc_cm2_func_luts mcm_luts; - bool lut_bank_a; - enum mpcc_movable_cm_location mcm_location; struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; int adaptive_sharpness_policy; @@ -1887,6 +1921,7 @@ struct dc_surface_update { * change cm2_params.cm2_luts: Fast update */ const struct dc_cm2_parameters *cm2_params; + const struct dc_plane_cm *cm; const struct dc_csc_transform *cursor_csc_color_matrix; unsigned int sdr_white_level_nits; struct dc_bias_and_scale bias_and_scale; @@ -1931,6 +1966,10 @@ struct dc_3dlut *dc_create_3dlut_func(void); void dc_3dlut_func_release(struct dc_3dlut *lut); void dc_3dlut_func_retain(struct dc_3dlut *lut); +struct dc_plane_cm *dc_plane_cm_create(void); +void dc_plane_cm_release(struct dc_plane_cm *cm); +void dc_plane_cm_retain(struct dc_plane_cm *cm); + void dc_post_update_surfaces_to_stream( struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 526f71616f94b..6f96c5cf39fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -102,8 +102,7 @@ struct dc_vbios_funcs { struct bp_external_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id, - struct graphics_object_id ext_enc_id); + enum engine_id engine_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/dc_plane.h index 14feb843e6940..2ad6d9318566e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_plane.h +++ b/drivers/gpu/drm/amd/display/dc/dc_plane.h @@ -31,6 +31,7 @@ union dc_plane_status_update_flags { struct { uint32_t address : 1; + uint32_t histogram : 1; } bits; uint32_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index d0ae5c27a5113..e224077c8902e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1483,4 +1483,28 @@ struct dc_validation_dpia_set { uint32_t required_bw; }; +enum dc_cm_lut_swizzle { + CM_LUT_3D_SWIZZLE_LINEAR_RGB, + CM_LUT_3D_SWIZZLE_LINEAR_BGR, + CM_LUT_1D_PACKED_LINEAR +}; + +enum dc_cm_lut_pixel_format { + CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB, + CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB, + CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB, + CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB, + CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10, + CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10 +}; + +enum dc_cm_lut_size { + CM_LUT_SIZE_NONE, + CM_LUT_SIZE_999, + CM_LUT_SIZE_171717, + CM_LUT_SIZE_333333, + CM_LUT_SIZE_454545, + CM_LUT_SIZE_656565, +}; + #endif /* DC_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index f1d3945608920..0cdf93c614b77 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -827,6 +827,16 @@ void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint3 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1); break; + case 4: + if (dccg_dcn->dccg_mask->SYMCLKE_FE_ROOT_GATE_DISABLE) { + REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE, + SYMCLKE_FE_EN, 1, + SYMCLKE_FE_SRC_SEL, link_enc_inst); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 1); + } + break; + default: + return; } } @@ -855,6 +865,16 @@ void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint SYMCLKD_FE_EN, 0, SYMCLKD_FE_SRC_SEL, 0); break; + case 4: + if (dccg_dcn->dccg_mask->SYMCLKE_FE_ROOT_GATE_DISABLE) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 0); + REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE, + SYMCLKE_FE_EN, 0, + SYMCLKE_FE_SRC_SEL, 0); + } + break; + default: + return; } } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index 7116fdd4c7ecd..d0ffa99f1fe0d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -28,6 +28,14 @@ #include "dc_types.h" #include "core_types.h" +static bool dmub_hw_lock_has_inbox0_lock(const struct dc *dc) +{ + return dc->ctx && dc->ctx->dmub_srv && + dc->hwss.dmub_hw_control_lock && + dc->hwss.dmub_hw_control_lock_fast && + dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support; +} + void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, bool lock, union dmub_hw_lock_flags *hw_locks, @@ -105,5 +113,13 @@ bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link if (dc->ctx->dce_version >= DCN_VERSION_4_01) return false; + if (dmub_hw_lock_has_inbox0_lock(dc)) + return false; + return dmub_hw_lock_mgr_does_link_require_lock(dc, link); } + +bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link) +{ + return dmub_hw_lock_has_inbox0_lock(dc) && dmub_hw_lock_mgr_does_link_require_lock(dc, link); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index 9495857902ed5..3e8caa9303906 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -67,4 +67,17 @@ bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct d */ bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context); +/** + * should_use_dmub_inbox0_lock_for_link() - Checks if the inbox0 interlock with DMU should be used. + * + * Is not functionally equivalent to inbox1 as DMUB will not own programming of the relevant locking + * registers. + * + * @dc: pointer to DC object + * @link: optional pointer to the link object to check for enabled link features + * + * Return: true if the inbox0 lock should be used, false otherwise + */ +bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link); + #endif /*_DMUB_HW_LOCK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index 6cc03391fff6f..847fab5087503 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -601,36 +601,31 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm plane->composition.viewport.stationary = false; - if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + if (plane_state->cm.flags.bits.lut3d_dma_enable) { plane->tdlut.setup_for_tdlut = true; - switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.layout) { - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + switch (plane_state->cm.lut3d_dma.swizzle) { + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: plane->tdlut.tdlut_addressing_mode = dml2_tdlut_sw_linear; break; - case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + case CM_LUT_1D_PACKED_LINEAR: + default: plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear; break; } - switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.size) { - case DC_CM2_GPU_MEM_SIZE_171717: - plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; - break; - case DC_CM2_GPU_MEM_SIZE_333333: + switch (plane_state->cm.lut3d_dma.size) { + case CM_LUT_SIZE_333333: plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube; break; - // handling when use case and HW support available - case DC_CM2_GPU_MEM_SIZE_454545: - case DC_CM2_GPU_MEM_SIZE_656565: - break; - case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + case CM_LUT_SIZE_171717: default: - //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; break; } } + plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable; plane->dynamic_meta_data.enable = false; @@ -967,5 +962,8 @@ void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_s min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_state_index]; min_clocks->stutter_efficiency.base_efficiency = 1; min_clocks->stutter_efficiency.low_power_efficiency = 1; + min_clocks->stutter_efficiency.z8_stutter_efficiency = 1; + min_clocks->stutter_efficiency.z8_stutter_period = 100000; + min_clocks->zstate_support = DCN_ZSTATE_SUPPORT_ALLOW; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c index 732b994b88643..ab7ec24268bea 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c @@ -374,6 +374,7 @@ void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *c dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state); } + static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c index 96c62bd6a37b2..2623e917ec28c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c @@ -9,16 +9,21 @@ #include "dml21_utils.h" #include "dml21_translation_helper.h" #include "dml2_dc_resource_mgmt.h" +#include "dc_fpu.h" + +#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif // !DC_RUN_WITH_PREEMPTION_ENABLED #define INVALID -1 static bool dml21_allocate_memory(struct dml2_context **dml_ctx) { - *dml_ctx = vzalloc(sizeof(struct dml2_context)); + DC_RUN_WITH_PREEMPTION_ENABLED(*dml_ctx = vzalloc(sizeof(struct dml2_context))); if (!(*dml_ctx)) return false; - (*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance)); + DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance))); if (!((*dml_ctx)->v21.dml_init.dml2_instance)) return false; @@ -28,7 +33,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; - (*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming)); + DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming))); if (!((*dml_ctx)->v21.mode_programming.programming)) return false; @@ -70,8 +75,9 @@ static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, con bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) { /* Allocate memory for initializing DML21 instance */ - if (!dml21_allocate_memory(dml_ctx)) + if (!dml21_allocate_memory(dml_ctx)) { return false; + } dml21_init(in_dc, *dml_ctx, config); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h index 8cd074cfdf18d..c75778ea7a2c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: MIT */ -/* Copyright 2026 Advanced Micro Devices, Inc. */ +// +// Copyright 2024 Advanced Micro Devices, Inc. #ifndef __DML_DML_DCN42_SOC_BB__ #define __DML_DML_DCN42_SOC_BB__ @@ -9,39 +10,39 @@ static const struct dml2_soc_qos_parameters dml_dcn42_variant_a_soc_qos_params = { .derate_table = { .system_active_urgent = { - .dram_derate_percent_pixel = 22, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 76, - .dcfclk_derate_percent = 100, + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, }, .system_active_average = { - .dram_derate_percent_pixel = 17, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 57, - .dcfclk_derate_percent = 75, + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, }, .dcn_mall_prefetch_urgent = { - .dram_derate_percent_pixel = 40, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 83, - .dcfclk_derate_percent = 100, + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, }, .dcn_mall_prefetch_average = { - .dram_derate_percent_pixel = 33, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 62, - .dcfclk_derate_percent = 83, + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, }, .system_idle_average = { - .dram_derate_percent_pixel = 70, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 83, - .dcfclk_derate_percent = 100, + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, }, }, .writeback = { @@ -50,80 +51,71 @@ static const struct dml2_soc_qos_parameters dml_dcn42_variant_a_soc_qos_params = .scaling_factor_mhz = 0, }, .qos_params = { - .dcn4x = { - .df_qos_response_time_fclk_cycles = 300, - .max_round_trip_to_furthest_cs_fclk_cycles = 350, - .mall_overhead_fclk_cycles = 50, - .meta_trip_adder_fclk_cycles = 36, - .average_transport_distance_fclk_cycles = 257, - .umc_urgent_ramp_latency_margin = 50, - .umc_max_latency_margin = 30, - .umc_average_latency_margin = 20, - .fabric_max_transport_latency_margin = 20, - .fabric_average_transport_latency_margin = 10, - - .per_uclk_dpm_params = { - { - .minimum_uclk_khz = 97 * 1000, - .urgent_ramp_uclk_cycles = 472, - .trip_to_memory_uclk_cycles = 827, - .meta_trip_to_memory_uclk_cycles = 827, - .maximum_latency_when_urgent_uclk_cycles = 72, - .average_latency_when_urgent_uclk_cycles = 61, - .maximum_latency_when_non_urgent_uclk_cycles = 827, - .average_latency_when_non_urgent_uclk_cycles = 118, - }, + .dcn32x = { + .loaded_round_trip_latency_fclk_cycles = 106, + .urgent_latency_us = { + .base_latency_us = 4, + .base_latency_pixel_vm_us = 4, + .base_latency_vm_us = 4, + .scaling_factor_fclk_us = 0, + .scaling_factor_mhz = 0, }, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, }, }, - .qos_type = dml2_qos_param_type_dcn4x, + .qos_type = dml2_qos_param_type_dcn3, }; static const struct dml2_soc_bb dml2_socbb_dcn42 = { .clk_table = { + .wck_ratio = { + .clk_values_khz = {2}, + }, .uclk = { - .clk_values_khz = {97000}, + .clk_values_khz = {400000}, .num_clk_values = 1, }, .fclk = { - .clk_values_khz = {300000, 2500000}, - .num_clk_values = 2, + .clk_values_khz = {400000}, + .num_clk_values = 1, }, .dcfclk = { - .clk_values_khz = {200000, 1564000}, - .num_clk_values = 2, + .clk_values_khz = {200000}, + .num_clk_values = 1, }, .dispclk = { - .clk_values_khz = {100000, 1500000}, - .num_clk_values = 2, + .clk_values_khz = {1500000}, + .num_clk_values = 1, }, .dppclk = { - .clk_values_khz = {100000, 1500000}, - .num_clk_values = 2, + .clk_values_khz = {1500000}, + .num_clk_values = 1, }, .dtbclk = { - .clk_values_khz = {600000, 600000}, - .num_clk_values = 2, + .clk_values_khz = {600000}, + .num_clk_values = 1, }, .phyclk = { - .clk_values_khz = {810000, 810000}, - .num_clk_values = 2, + .clk_values_khz = {810000}, + .num_clk_values = 1, }, .socclk = { - .clk_values_khz = {300000, 1200000}, - .num_clk_values = 2, + .clk_values_khz = {600000}, + .num_clk_values = 1, }, .dscclk = { - .clk_values_khz = {500000, 500000}, - .num_clk_values = 2, + .clk_values_khz = {500000}, + .num_clk_values = 1, }, .phyclk_d18 = { - .clk_values_khz = {667000, 667000}, - .num_clk_values = 2, + .clk_values_khz = {667000}, + .num_clk_values = 1, }, .phyclk_d32 = { - .clk_values_khz = {625000, 625000}, - .num_clk_values = 2, + .clk_values_khz = {625000}, + .num_clk_values = 1, }, .dram_config = { .channel_width_bytes = 4, @@ -135,39 +127,39 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = { .qos_parameters = { .derate_table = { .system_active_urgent = { - .dram_derate_percent_pixel = 22, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 76, - .dcfclk_derate_percent = 100, + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, }, .system_active_average = { - .dram_derate_percent_pixel = 15, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 57, - .dcfclk_derate_percent = 75, + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, }, .dcn_mall_prefetch_urgent = { - .dram_derate_percent_pixel = 40, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 83, - .dcfclk_derate_percent = 100, + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, }, .dcn_mall_prefetch_average = { .dram_derate_percent_pixel = 30, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 62, - .dcfclk_derate_percent = 83, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, }, .system_idle_average = { - .dram_derate_percent_pixel = 70, - .dram_derate_percent_vm = 0, - .dram_derate_percent_pixel_and_vm = 0, - .fclk_derate_percent = 83, - .dcfclk_derate_percent = 100, + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, }, }, .writeback = { @@ -176,115 +168,25 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = { .scaling_factor_mhz = 0, }, .qos_params = { - .dcn4x = { - .df_qos_response_time_fclk_cycles = 300, - .max_round_trip_to_furthest_cs_fclk_cycles = 350, - .mall_overhead_fclk_cycles = 50, - .meta_trip_adder_fclk_cycles = 36, - .average_transport_distance_fclk_cycles = 260, - .umc_urgent_ramp_latency_margin = 50, - .umc_max_latency_margin = 30, - .umc_average_latency_margin = 20, - .fabric_max_transport_latency_margin = 20, - .fabric_average_transport_latency_margin = 10, - - .per_uclk_dpm_params = { - { - // State 1 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 472, - .trip_to_memory_uclk_cycles = 827, - .meta_trip_to_memory_uclk_cycles = 827, - .maximum_latency_when_urgent_uclk_cycles = 72, - .average_latency_when_urgent_uclk_cycles = 72, - .maximum_latency_when_non_urgent_uclk_cycles = 827, - .average_latency_when_non_urgent_uclk_cycles = 117, - }, - { - // State 2 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 546, - .trip_to_memory_uclk_cycles = 848, - .meta_trip_to_memory_uclk_cycles = 848, - .maximum_latency_when_urgent_uclk_cycles = 146, - .average_latency_when_urgent_uclk_cycles = 146, - .maximum_latency_when_non_urgent_uclk_cycles = 848, - .average_latency_when_non_urgent_uclk_cycles = 133, - }, - { - // State 3 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 564, - .trip_to_memory_uclk_cycles = 853, - .meta_trip_to_memory_uclk_cycles = 853, - .maximum_latency_when_urgent_uclk_cycles = 164, - .average_latency_when_urgent_uclk_cycles = 164, - .maximum_latency_when_non_urgent_uclk_cycles = 853, - .average_latency_when_non_urgent_uclk_cycles = 136, - }, - { - // State 4 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 613, - .trip_to_memory_uclk_cycles = 869, - .meta_trip_to_memory_uclk_cycles = 869, - .maximum_latency_when_urgent_uclk_cycles = 213, - .average_latency_when_urgent_uclk_cycles = 213, - .maximum_latency_when_non_urgent_uclk_cycles = 869, - .average_latency_when_non_urgent_uclk_cycles = 149, - }, - { - // State 5 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 632, - .trip_to_memory_uclk_cycles = 874, - .meta_trip_to_memory_uclk_cycles = 874, - .maximum_latency_when_urgent_uclk_cycles = 232, - .average_latency_when_urgent_uclk_cycles = 232, - .maximum_latency_when_non_urgent_uclk_cycles = 874, - .average_latency_when_non_urgent_uclk_cycles = 153, - }, - { - // State 6 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 665, - .trip_to_memory_uclk_cycles = 885, - .meta_trip_to_memory_uclk_cycles = 885, - .maximum_latency_when_urgent_uclk_cycles = 265, - .average_latency_when_urgent_uclk_cycles = 265, - .maximum_latency_when_non_urgent_uclk_cycles = 885, - .average_latency_when_non_urgent_uclk_cycles = 161, - }, - { - // State 7 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 689, - .trip_to_memory_uclk_cycles = 895, - .meta_trip_to_memory_uclk_cycles = 895, - .maximum_latency_when_urgent_uclk_cycles = 289, - .average_latency_when_urgent_uclk_cycles = 289, - .maximum_latency_when_non_urgent_uclk_cycles = 895, - .average_latency_when_non_urgent_uclk_cycles = 167, - }, - { - // State 8 - .minimum_uclk_khz = 0, - .urgent_ramp_uclk_cycles = 716, - .trip_to_memory_uclk_cycles = 902, - .meta_trip_to_memory_uclk_cycles = 902, - .maximum_latency_when_urgent_uclk_cycles = 316, - .average_latency_when_urgent_uclk_cycles = 316, - .maximum_latency_when_non_urgent_uclk_cycles = 902, - .average_latency_when_non_urgent_uclk_cycles = 174, - }, + .dcn32x = { + .loaded_round_trip_latency_fclk_cycles = 106, + .urgent_latency_us = { + .base_latency_us = 4, + .base_latency_pixel_vm_us = 4, + .base_latency_vm_us = 4, + .scaling_factor_fclk_us = 0, + .scaling_factor_mhz = 0, }, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, }, }, - .qos_type = dml2_qos_param_type_dcn4x, + .qos_type = dml2_qos_param_type_dcn3, }, .power_management_parameters = { - .dram_clk_change_blackout_us = 11.72, + .dram_clk_change_blackout_us = 29, .fclk_change_blackout_us = 0, .g7_ppt_blackout_us = 0, .stutter_enter_plus_exit_latency_us = 11, @@ -293,9 +195,9 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = { .z8_stutter_exit_latency_us = 200, }, - .vmin_limit = { - .dispclk_khz = 600 * 1000, - }, + .vmin_limit = { + .dispclk_khz = 632 * 1000, + }, .dprefclk_mhz = 600, .xtalclk_mhz = 24, @@ -307,6 +209,8 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = { .return_bus_width_bytes = 64, .hostvm_min_page_size_kbytes = 4, .gpuvm_min_page_size_kbytes = 256, + .gpuvm_max_page_table_levels = 1, + .hostvm_max_non_cached_page_table_levels = 2, .phy_downspread_percent = 0.38, .dcn_downspread_percent = 0.38, .dispclk_dppclk_vco_speed_mhz = 3000, diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h index b44762e21550f..4e9abe1a568d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h @@ -27,6 +27,19 @@ enum dml2_swizzle_mode { dml2_gfx11_sw_256kb_d_x, dml2_gfx11_sw_256kb_r_x, + dml2_sw_linear_256b, // GFX10 SW_LINEAR only accepts 256 byte aligned pitch + dml2_gfx10_sw_64kb_r_x, + dml2_gfx102_sw_64kb_s, + dml2_gfx102_sw_64kb_s_t, + dml2_gfx102_sw_64kb_s_x, + dml2_gfx102_sw_64kb_r_x, + + dml2_linear_64elements, // GFX7 LINEAR_ALIGNED accepts pitch alignment of the maximum of 64 elements or 256 bytes + dml2_gfx7_1d_thin, + dml2_gfx7_2d_thin_gen_zero, + dml2_gfx7_2d_thin_gen_one, + dml2_gfx7_2d_thin_arlene, + dml2_gfx7_2d_thin_anubis }; enum dml2_source_format_class { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index c854515b49a32..98b26116cdc14 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -19,6 +19,7 @@ enum dml2_project_id { dml2_project_dcn4x_stage1, dml2_project_dcn4x_stage2, dml2_project_dcn4x_stage2_auto_drr_svp, + dml2_project_dcn40, dml2_project_dcn42, }; @@ -80,6 +81,7 @@ struct dml2_options { struct dml2_pmo_options pmo_options; }; + struct dml2_initialize_instance_in_out { struct dml2_instance *dml2_instance; struct dml2_options options; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c index 67e307fa43108..6cad99c21139b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c @@ -21,6 +21,7 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance case dml2_project_dcn4x_stage1: result = false; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->initialize = &core_dcn4_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c index b57d0f6ea6a1c..6930ba7ce5b76 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c @@ -428,6 +428,9 @@ bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_c unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) { + if (dml2_core_utils_get_gfx_version(sw_mode) == 10 || dml2_core_utils_get_gfx_version(sw_mode) == 7) { + return dml2_core_utils_get_tile_block_size_bytes_backcompat(sw_mode, byte_per_pixel); + } if (sw_mode == dml2_sw_linear) return 256; @@ -459,14 +462,56 @@ unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw }; } +unsigned int dml2_core_utils_get_tile_block_size_bytes_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) +{ + if (sw_mode == dml2_sw_linear_256b) + return 256; + else if (sw_mode == dml2_gfx10_sw_64kb_r_x) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_s) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_s_t) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_s_x) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_r_x) + return 65536; + else if (sw_mode == dml2_linear_64elements) + return 256; + else if (sw_mode == dml2_gfx7_1d_thin) + return 256; + else if (sw_mode == dml2_gfx7_2d_thin_gen_zero) + return (128 * 64 * byte_per_pixel); + else if (sw_mode == dml2_gfx7_2d_thin_gen_one) + return (128 * 128 * byte_per_pixel); + else if (sw_mode == dml2_gfx7_2d_thin_arlene) + return (64 * 32 * byte_per_pixel); + else if (sw_mode == dml2_gfx7_2d_thin_anubis) + return (128 * 128 * byte_per_pixel); + else { + DML_ASSERT(0); + return 256; + }; +} + bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) { - return (byte_per_pixel != 2); + if (dml2_core_utils_get_gfx_version(sw_mode) == 10 || dml2_core_utils_get_gfx_version(sw_mode) == 7) { + return dml2_core_utils_get_segment_horizontal_contiguous_backcompat(sw_mode, byte_per_pixel); + } else { + return (byte_per_pixel != 2); + } +} + +bool dml2_core_utils_get_segment_horizontal_contiguous_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) +{ + return !((byte_per_pixel == 4) && + ((sw_mode == dml2_gfx10_sw_64kb_r_x) || (sw_mode == dml2_gfx102_sw_64kb_s) || (sw_mode == dml2_gfx102_sw_64kb_s_t) || (sw_mode == dml2_gfx102_sw_64kb_s_x))); } bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode) { - return sw_mode == dml2_sw_linear; + return (sw_mode == dml2_sw_linear || sw_mode == dml2_sw_linear_256b || sw_mode == dml2_linear_64elements); }; @@ -499,6 +544,20 @@ int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode) sw_mode == dml2_gfx11_sw_256kb_d_x || sw_mode == dml2_gfx11_sw_256kb_r_x) version = 11; + else if (sw_mode == dml2_sw_linear_256b || + sw_mode == dml2_gfx10_sw_64kb_r_x || + sw_mode == dml2_gfx102_sw_64kb_s || + sw_mode == dml2_gfx102_sw_64kb_s_t || + sw_mode == dml2_gfx102_sw_64kb_s_x || + sw_mode == dml2_gfx102_sw_64kb_r_x) + version = 10; + else if (sw_mode == dml2_linear_64elements || + sw_mode == dml2_gfx7_1d_thin || + sw_mode == dml2_gfx7_2d_thin_gen_zero || + sw_mode == dml2_gfx7_2d_thin_gen_one || + sw_mode == dml2_gfx7_2d_thin_arlene || + sw_mode == dml2_gfx7_2d_thin_anubis) + version = 7; else { DML_LOG_VERBOSE("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode); DML_ASSERT(0); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h index 95f0d017add45..471e73ed671cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h @@ -22,6 +22,8 @@ void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_in bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg); unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); +unsigned int dml2_core_utils_get_tile_block_size_bytes_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); +bool dml2_core_utils_get_segment_horizontal_contiguous_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan); bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode); int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c index 037272d2c2e64..d17e59d684fd1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c @@ -802,7 +802,6 @@ bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_ return true; } - bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out) { const struct dml2_display_cfg *display_cfg = &in_out->display_cfg->display_config; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index 80d4932bf1544..1f2d9e97f5fdb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -31,6 +31,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance out->map_watermarks = &dummy_map_watermarks; result = true; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->map_mode_to_soc_dpm = &dpmm_dcn3_map_mode_to_soc_dpm; out->map_watermarks = &dummy_map_watermarks; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h index f54fde8fba906..02da6f45cbf75 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h @@ -10,4 +10,4 @@ bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); bool mcg_dcn4_unit_test(void); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h index ad8a847a0a178..d4ea49e3e6744 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: MIT */ -/* Copyright 2026 Advanced Micro Devices, Inc. */ +// +// Copyright 2026 Advanced Micro Devices, Inc. #ifndef __DML2_MCG_DCN42_H__ #define __DML2_MCG_DCN42_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c index 1cff62b63e720..3dcd2c250633a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c @@ -26,6 +26,7 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance * out->build_min_clock_table = &dummy_build_min_clock_table; result = true; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->build_min_clock_table = &mcg_dcn4_build_min_clock_table; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index c26e100fcaf2e..e8691983c0eba 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -23,6 +23,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = { .allow_state_increase = true, }, + // Then VBlank { .per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na }, @@ -53,6 +54,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_2_display[] = { .allow_state_increase = true, }, + // Then VActive + VBlank { .per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na }, @@ -113,6 +115,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_3_display[] = { .allow_state_increase = true, }, + // VActive + 1 VBlank { .per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vblank, dml2_pstate_method_na }, @@ -149,6 +152,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_4_display[] = { .allow_state_increase = true, }, + // VActive + 1 VBlank { .per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vblank }, @@ -1651,6 +1655,7 @@ static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_ins if (svp_count > 0 && (pmo->options->disable_svp || !all_timings_support_svp(pmo, display_cfg, svp_stream_mask))) return false; + return is_config_schedulable(pmo, display_cfg, pstate_strategy); } @@ -1980,6 +1985,7 @@ static void reset_display_configuration(struct display_configuation_with_meta *d } } + static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *display_config, struct dml2_pmo_instance *pmo, int plane_mask) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c index 55d2464365d04..4d687fa86caab 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c @@ -3,8 +3,8 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dml2_pmo_factory.h" -#include "dml2_pmo_dcn4_fams2.h" #include "dml2_pmo_dcn3.h" +#include "dml2_pmo_dcn4_fams2.h" #include "dml2_external_lib_deps.h" static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out) @@ -37,6 +37,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * out->optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache; result = true; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->initialize = pmo_dcn3_initialize; @@ -56,6 +57,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * result = true; break; + case dml2_project_dcn42: case dml2_project_dcn4x_stage2_auto_drr_svp: out->initialize = pmo_dcn4_fams2_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h index b90f6263cd85d..7218de1824cca 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h @@ -10,4 +10,4 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c index 04860b6790df1..a6c5031f69c19 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c @@ -17,6 +17,7 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out) case dml2_project_dcn4x_stage1: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: + case dml2_project_dcn40: case dml2_project_dcn42: return dml2_top_soc15_initialize_instance(in_out); case dml2_project_invalid: diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c index 5e14d85821e27..0e3177fe9d27e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c @@ -3,7 +3,6 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dml2_top_legacy.h" -#include "dml2_top_soc15.h" #include "dml2_core_factory.h" #include "dml2_pmo_factory.h" #include "display_mode_core_structs.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h index a6bd75f30d202..d328d92240b4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h @@ -410,6 +410,7 @@ struct dml2_core_mode_support_in_out { } legacy; }; + struct dml2_core_mode_programming_in_out { /* * Inputs @@ -501,6 +502,7 @@ struct dml2_core_instance { bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); + struct { struct dml2_core_internal_display_mode_lib mode_lib; } clean_me_up; @@ -753,6 +755,7 @@ struct dml2_pmo_instance { bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); + struct dml2_pmo_init_data init_data; struct dml2_pmo_scratch scratch; }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c index 307186eb6af08..408559d6fb2d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c @@ -84,8 +84,9 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) { // TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete. - if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) + if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) { return dml21_create(in_dc, dml2, config); + } // Allocate Mode Lib Ctx *dml2 = dml2_allocate_memory(); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c index 82eca0e7b7d05..3284084ca7ad4 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c @@ -132,6 +132,8 @@ static void dpp3_power_on_gamcor_lut( if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 0); + if (dpp_base->ctx->dc->caps.ips_v2_support) + REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, 1); REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5); } else { dpp_base->ctx->dc->optimized_required = true; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index a62c4733ed3be..8b6155f9122f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -155,7 +155,12 @@ static void dpp401_power_on_dscl( if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { if (power_on) { REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0); - REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); + if (dpp->base.ctx->dc->caps.ips_v2_support) { + /*hw default changes to LS*/ + REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, 1); + REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 100); + } else + REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); } else { if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { dpp->base.ctx->dc->optimized_required = true; @@ -956,6 +961,15 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, *bs_coeffs_updated = false; PERF_TRACE(); + /*power on isharp_delta_mem first*/ + if (dpp_base->ctx->dc->caps.ips_v2_support) { + /*HW default is LS, need to wake up*/ + REG_UPDATE_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, + ISHARP_DELTA_LUT_MEM_PWR_DIS, 1); + REG_WAIT(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_STATE, 0, 1, 100); + } /* ISHARP_MODE */ REG_SET_6(ISHARP_MODE, 0, ISHARP_EN, scl_data->dscl_prog_data.isharp_en, @@ -1033,6 +1047,13 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, } } + /*power on isharp_delta_mem first*/ + if (dpp_base->ctx->dc->caps.ips_v2_support) { + /*HW default is LS, need to wake up*/ + REG_UPDATE_SEQ_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, + ISHARP_DELTA_LUT_MEM_PWR_DIS, 0); + } PERF_TRACE(); } // dpp401_dscl_program_isharp /** diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 759b453385c46..92ed130aeaec9 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -640,6 +640,11 @@ static void dcn31_hpo_dp_stream_enc_audio_setup( REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst); + if (enc3->hpo_se_mask->DP_STREAM_ENC_APG_CLOCK_EN) { + /*enable apg clk*/ + REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL, + DP_STREAM_ENC_APG_CLOCK_EN, 1); + } ASSERT(enc->apg); enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info); } diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index c205500290ecd..4985e885952d9 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -41,12 +41,12 @@ hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name void hubp401_program_3dlut_fl_addr(struct hubp *hubp, - const struct dc_plane_address address) + const struct dc_plane_address *address) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); - REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address->lut3d.addr.high_part); + REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address->lut3d.addr.low_part); } void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group) @@ -72,33 +72,46 @@ int hubp401_get_3dlut_fl_done(struct hubp *hubp) return ret; } -void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode) +static void hubp401_get_3dlut_fl_xbar_map( + const enum dc_cm_lut_pixel_format format, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode); -} - -void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); + switch (format) { + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: + /* BGRA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: + default: + /* RGBA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } } -void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits) +void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, + const enum dc_cm_lut_pixel_format format) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits); -} + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r = 0; -void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + hubp401_get_3dlut_fl_xbar_map(format, + &bit_slice_y_g, + &bit_slice_cb_b, + &bit_slice_cr_r); REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g, @@ -106,62 +119,122 @@ void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r); } -void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale) +static enum hubp_3dlut_fl_width hubp401_get_3dlut_fl_width( + const enum dc_cm_lut_size size, + const enum dc_cm_lut_swizzle swizzle) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_width width = 0; + + switch (size) { + case CM_LUT_SIZE_333333: + ASSERT(swizzle != CM_LUT_1D_PACKED_LINEAR); + width = hubp_3dlut_fl_width_33; + break; + case CM_LUT_SIZE_171717: + if (swizzle != CM_LUT_1D_PACKED_LINEAR) { + width = hubp_3dlut_fl_width_17; + } else { + width = hubp_3dlut_fl_width_17_transformed; + } + break; + default: + width = 0; + break; + } - REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale); + return width; } -void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode) +static enum hubp_3dlut_fl_format hubp401_get_3dlut_fl_format( + const enum dc_cm_lut_pixel_format dc_format) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_format hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode); + switch (dc_format) { + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: + hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: + hubp_format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: + hubp_format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + return hubp_format; } -void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format) +static enum hubp_3dlut_fl_addressing_mode hubp401_get_3dlut_fl_addr_mode( + const enum dc_cm_lut_swizzle swizzle) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_addressing_mode addr_mode; + + switch (swizzle) { + case CM_LUT_1D_PACKED_LINEAR: + addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: + default: + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } - REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); + return addr_mode; } -void hubp401_program_3dlut_fl_config( - struct hubp *hubp, - struct hubp_fl_3dlut_config *cfg) +static enum hubp_3dlut_fl_mode hubp401_get_3dlut_fl_mode( + const enum dc_cm_lut_swizzle swizzle) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_mode mode; - uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1}; - uint32_t width = {cfg->width}; + switch (swizzle) { + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + mode = hubp_3dlut_fl_mode_native_1; + break; + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: + mode = hubp_3dlut_fl_mode_native_2; + break; + case CM_LUT_1D_PACKED_LINEAR: + mode = hubp_3dlut_fl_mode_transform; + break; + default: + mode = hubp_3dlut_fl_mode_disable; + break; + } - if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR) - width = (cfg->width == 17) ? 4916 : 35940; + return mode; +} + +void hubp401_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + enum hubp_3dlut_fl_width width = hubp401_get_3dlut_fl_width(config->size, config->swizzle); + enum hubp_3dlut_fl_format format = hubp401_get_3dlut_fl_format(config->format); + enum hubp_3dlut_fl_addressing_mode addr_mode = hubp401_get_3dlut_fl_addr_mode(config->swizzle); + enum hubp_3dlut_fl_mode mode = hubp401_get_3dlut_fl_mode(config->swizzle); REG_UPDATE_2(_3DLUT_FL_CONFIG, - HUBP0_3DLUT_FL_MODE, cfg->mode, - HUBP0_3DLUT_FL_FORMAT, cfg->format); + HUBP0_3DLUT_FL_MODE, mode, + HUBP0_3DLUT_FL_FORMAT, format); REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, - HUBP0_3DLUT_FL_BIAS, cfg->bias, - HUBP0_3DLUT_FL_SCALE, cfg->scale); - - REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, - HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part); - REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW, - HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part); - - //cross bar - REG_UPDATE_8(HUBP_3DLUT_CONTROL, - HUBP_3DLUT_MPC_WIDTH, mpc_width, - HUBP_3DLUT_WIDTH, width, - HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r, - HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g, - HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b, - HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode, - HUBP_3DLUT_TMZ, cfg->protection_bits, - HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0); + HUBP0_3DLUT_FL_BIAS, config->bias, + HUBP0_3DLUT_FL_SCALE, config->scale); + + REG_UPDATE_3(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_WIDTH, width, + HUBP_3DLUT_ADDRESSING_MODE, addr_mode, + HUBP_3DLUT_TMZ, config->addr.tmz_surface); } void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) @@ -1058,19 +1131,13 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_update_mall_sel = hubp401_update_mall_sel, .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, - .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, - .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, - .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, - .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, - .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, - .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, - .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_read_reg_state = hubp3_read_reg_state }; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 4570b8016de5a..043948f64b862 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -328,32 +328,17 @@ int hubp401_get_3dlut_fl_done(struct hubp *hubp); void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable); -void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale); - void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); - -void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits); - -void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width); - -void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); + const enum dc_cm_lut_pixel_format format); void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable); void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group); -void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address); +void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address *address); -void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format); - -void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode); - -void hubp401_program_3dlut_fl_config( - struct hubp *hubp, - struct hubp_fl_3dlut_config *cfg); +void hubp401_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config); void hubp401_clear_tiling(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c index 07c38dc039600..0e33c739f459f 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -147,13 +147,16 @@ static void hubp42_program_pixel_format( /* don't see the need of program the xbar in DCN 1.0 */ } -void hubp42_program_deadline( +static void hubp42_program_deadline( struct hubp *hubp, struct dml2_display_dlg_regs *dlg_attr, struct dml2_display_ttu_regs *ttu_attr) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + /* put DLG in mission mode */ + REG_WRITE(HUBPREQ_DEBUG_DB, 0); + /* DLG - Per hubp */ REG_SET_2(BLANK_OFFSET_0, 0, REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, @@ -274,19 +277,84 @@ static void hubp42_program_surface_config( hubp42_program_pixel_format(hubp, format); } +static void hubp42_get_3dlut_fl_xbar_map( + const enum dc_cm_lut_pixel_format format, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) +{ + switch (format) { + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: + /* BGRA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: + default: + /* RGBA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } +} + void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b) + const enum dc_cm_lut_pixel_format format) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r = 0; + + hubp42_get_3dlut_fl_xbar_map(format, + &bit_slice_g, + &bit_slice_b, + &bit_slice_r); + REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_R, bit_slice_r, HUBP_3DLUT_CROSSBAR_SEL_G, bit_slice_g, HUBP_3DLUT_CROSSBAR_SEL_B, bit_slice_b); } +static uint32_t hubp42_get_3dlut_fl_mpc_width( + const enum dc_cm_lut_size size) +{ + uint32_t width = 0; + + switch (size) { + case CM_LUT_SIZE_333333: + width = 1; + break; + case CM_LUT_SIZE_171717: + default: + width = 0; + break; + } + + return width; +} + +void hubp42_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + uint32_t mpc_width = hubp42_get_3dlut_fl_mpc_width(config->size); + + REG_UPDATE(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_MPC_WIDTH, mpc_width); + + hubp401_program_3dlut_fl_config(hubp, config); +} + static bool hubp42_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, @@ -548,6 +616,7 @@ struct hubp_funcs dcn42_hubp_funcs = { .hubp_setup_interdependent2 = hubp401_setup_interdependent, .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, .set_blank = hubp2_set_blank, + .set_blank_regs = hubp2_set_blank_regs, .dcc_control = hubp3_dcc_control, .hubp_reset = hubp_reset, .mem_program_viewport = min_set_viewport, @@ -567,17 +636,13 @@ struct hubp_funcs dcn42_hubp_funcs = { .hubp_set_flip_int = hubp1_set_flip_int, .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank_value, - .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, - .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, - .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, + .hubp_program_3dlut_fl_config = hubp42_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, - .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, - .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, - .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, + .hubp_clear_tiling = hubp3_clear_tiling, .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_read_reg_state = hubp3_read_reg_state }; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h index 976614f389814..486c8907413aa 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h @@ -56,11 +56,11 @@ bool hubp42_construct( const struct dcn_hubp2_shift *hubp_shift, const struct dcn_hubp2_mask *hubp_mask); -void hubp42_program_3dlut_fl_crossbar( - struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b); +void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, + const enum dc_cm_lut_pixel_format format); + +void hubp42_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config); void hubp42_read_state(struct hubp *hubp); @@ -70,10 +70,4 @@ void hubp42_setup( union dml2_global_sync_programming *pipe_global_sync, struct dc_crtc_timing *timing); -void hubp42_program_deadline( - struct hubp *hubp, - struct dml2_display_dlg_regs *dlg_attr, - struct dml2_display_ttu_regs *ttu_attr); - - #endif /* __DC_HUBP_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 38a5f312ddb4b..8a17cc036399a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -661,45 +661,16 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) } static void -dce110_external_encoder_control(enum bp_external_encoder_control_action action, - struct dc_link *link, - struct dc_crtc_timing *timing) +dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) { - struct dc *dc = link->ctx->dc; + struct dc_link *link = pipe_ctx->stream->link; struct dc_bios *bios = link->ctx->dc_bios; - const struct dc_link_settings *link_settings = &link->cur_link_settings; - enum bp_result bp_result = BP_RESULT_OK; - struct bp_external_encoder_control ext_cntl = { - .action = action, - .connector_obj_id = link->link_enc->connector, - .encoder_id = link->ext_enc_id, - .lanes_number = link_settings->lane_count, - .link_rate = link_settings->link_rate, - - /* Use signal type of the real link encoder, ie. DP */ - .signal = link->connector_signal, - - /* We don't know the timing yet when executing the SETUP action, - * so use a reasonably high default value. It seems that ENABLE - * can change the actual pixel clock but doesn't work with higher - * pixel clocks than what SETUP was called with. - */ - .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000, - .color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888, - }; - DC_LOGGER_INIT(dc->ctx); - - bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl); + struct bp_encoder_control encoder_control = {0}; - if (bp_result != BP_RESULT_OK) - DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action); -} - -static void -dce110_prepare_ddc(struct dc_link *link) -{ - if (link->ext_enc_id.id) - dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL); + encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; + encoder_control.engine_id = link->link_enc->analog_engine; + encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; + bios->funcs->encoder_control(bios, &encoder_control); } static bool @@ -709,8 +680,7 @@ dce110_dac_load_detect(struct dc_link *link) struct link_encoder *link_enc = link->link_enc; enum bp_result bp_result; - bp_result = bios->funcs->dac_load_detection( - bios, link_enc->analog_engine, link->ext_enc_id); + bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); return bp_result == BP_RESULT_OK; } @@ -726,6 +696,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) uint32_t early_control = 0; struct timing_generator *tg = pipe_ctx->stream_res.tg; + link_hwss->setup_stream_attribute(pipe_ctx); link_hwss->setup_stream_encoder(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); @@ -744,8 +715,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) tg->funcs->set_early_control(tg, early_control); - if (link->ext_enc_id.id) - dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing); + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + dce110_dac_encoder_control(pipe_ctx, true); } static enum bp_result link_transmitter_control( @@ -1244,8 +1215,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) link_enc->transmitter - TRANSMITTER_UNIPHY_A); } - if (link->ext_enc_id.id) - dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL); + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + dce110_dac_encoder_control(pipe_ctx, false); } void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, @@ -1627,6 +1598,22 @@ static enum dc_status dce110_enable_stream_timing( return DC_OK; } +static void +dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) +{ + struct dc_link *link = pipe_ctx->stream->link; + struct dc_bios *bios = link->ctx->dc_bios; + struct bp_crtc_source_select crtc_source_select = {0}; + enum engine_id engine_id = link->link_enc->preferred_engine; + + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + engine_id = link->link_enc->analog_engine; + crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; + crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth; + crtc_source_select.engine_id = engine_id; + crtc_source_select.sink_signal = pipe_ctx->stream->signal; + bios->funcs->select_crtc_source(bios, &crtc_source_select); +} enum dc_status dce110_apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, @@ -1647,6 +1634,10 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( hws->funcs.disable_stream_gating(dc, pipe_ctx); } + if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) { + dce110_select_crtc_source(pipe_ctx); + } + if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output = {0}; @@ -1726,7 +1717,8 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx->stream_res.tg, event_triggers, 2); - if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) + if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && + !dc_is_rgb_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.tg->inst); @@ -1948,6 +1940,35 @@ static void clean_up_dsc_blocks(struct dc *dc) } } +static void dc_hwss_enable_otg_pwa( + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + struct timing_generator *tg = NULL; + + if (dc->debug.enable_otg_frame_sync_pwa == 0) + return; + + if (pipe_ctx == NULL || pipe_ctx->stream_res.tg == NULL) + return; + tg = pipe_ctx->stream_res.tg; + + /*only enable this if one active*/ + if (tg->funcs->enable_otg_pwa) { + struct otc_pwa_frame_sync pwa_param = {0}; + + DC_LOGGER_INIT(dc->ctx); + /* mode 1 to choose generate pwa sync signal on line 0 counting + * from vstartup at very beginning of the frame + */ + pwa_param.pwa_frame_sync_line_offset = 0; + pwa_param.pwa_sync_mode = DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP; + /*frame sync line for generating high frame sync*/ + tg->funcs->enable_otg_pwa(tg, &pwa_param); + DC_LOG_DC("Enable OTG PWA frame sync on TG %d\n", tg->inst); + } +} + /* * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: * 1. Power down all DC HW blocks @@ -2024,6 +2045,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) // If VBios supports it, we check it from reigster or other flags. pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1; } + dc_hwss_enable_otg_pwa(dc, pipe_ctx); } break; } @@ -2593,6 +2615,18 @@ enum dc_status dce110_apply_ctx_to_hw( #endif } + + if (dc->debug.enable_otg_frame_sync_pwa && context->stream_count == 1) { + /* only enable this on one OTG*/ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx && pipe_ctx->stream != NULL) { + dc_hwss_enable_otg_pwa(dc, pipe_ctx); + break; + } + } + } if (dc->fbc_compressor) enable_fbc(dc, dc->current_state); @@ -3320,15 +3354,6 @@ void dce110_enable_tmds_link_output(struct dc_link *link, link->phy_state.symclk_state = SYMCLK_ON_TX_ON; } -static void dce110_enable_analog_link_output( - struct dc_link *link, - uint32_t pix_clk_100hz) -{ - link->link_enc->funcs->enable_analog_output( - link->link_enc, - pix_clk_100hz); -} - void dce110_enable_dp_link_output( struct dc_link *link, const struct link_resource *link_res, @@ -3376,11 +3401,6 @@ void dce110_enable_dp_link_output( } } - if (link->ext_enc_id.id) { - dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL); - dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL); - } - if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { if (dc->clk_mgr->funcs->notify_link_rate_change) dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); @@ -3471,10 +3491,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, - .enable_analog_link_output = dce110_enable_analog_link_output, .disable_link_output = dce110_disable_link_output, .dac_load_detect = dce110_dac_load_detect, - .prepare_ddc = dce110_prepare_ddc, }; static const struct hwseq_private_funcs dce110_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 55c48c4bc6ce1..357899116ecd5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -95,10 +95,6 @@ void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; - //For now assert if location is not pre-blend - if (pipe_ctx->plane_state) - ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); - // program MPCC_MCM_FIRST_GAMUT_REMAP memset(&mpc_adjust, 0, sizeof(mpc_adjust)); mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -304,6 +300,7 @@ void dcn401_init_hw(struct dc *dc) } } } + for (i = 0; i < res_pool->audio_count; i++) { struct audio *audio = res_pool->audios[i]; @@ -372,293 +369,179 @@ void dcn401_init_hw(struct dc *dc) } } -static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, - enum MCM_LUT_XABLE *shaper_xable, - enum MCM_LUT_XABLE *lut3d_xable, - enum MCM_LUT_XABLE *lut1d_xable) +void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) { - enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; - bool lut1d_enable = false; - struct mpc *mpc = dc->res_pool->mpc; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - - if (!pipe_ctx->plane_state) - return; - shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; - lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; - - *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; + struct hubp *hubp = pipe_ctx->plane_res.hubp; - switch (shaper_3dlut_setting) { - case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: - *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; - break; - case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: - *lut3d_xable = MCM_LUT_DISABLE; - *shaper_xable = MCM_LUT_ENABLE; - break; - case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: - *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; - break; + if (hubp->funcs->hubp_enable_3dlut_fl) { + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); } } -void dcn401_populate_mcm_luts(struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_cm2_func_luts mcm_luts, - bool lut_bank_a) +bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { + struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; struct dpp *dpp_base = pipe_ctx->plane_res.dpp; struct hubp *hubp = pipe_ctx->plane_res.hubp; + const struct dc_plane_cm *cm = &plane_state->cm; int mpcc_id = hubp->inst; struct mpc *mpc = dc->res_pool->mpc; union mcm_lut_params m_lut_params; - enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; - enum hubp_3dlut_fl_format format = 0; - enum hubp_3dlut_fl_mode mode; - enum hubp_3dlut_fl_width width = 0; - enum hubp_3dlut_fl_addressing_mode addr_mode; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; - enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; - enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; - enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + struct dc_3dlut_dma lut3d_dma; + bool lut_enable; + bool lut_bank_a; bool rval; + bool result = true; - dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + /* decide LUT bank based on current in use */ + mpc->funcs->get_lut_mode(mpc, MCM_LUT_1DLUT, mpcc_id, &lut_enable, &lut_bank_a); + if (!lut_enable) { + mpc->funcs->get_lut_mode(mpc, MCM_LUT_SHAPER, mpcc_id, &lut_enable, &lut_bank_a); + } + if (!lut_enable) { + mpc->funcs->get_lut_mode(mpc, MCM_LUT_3DLUT, mpcc_id, &lut_enable, &lut_bank_a); + } + + /* switch to the next bank */ + if (lut_enable) { + lut_bank_a = !lut_bank_a; + } + + /* MCM location fixed to pre-blend */ + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); /* 1D LUT */ - if (mcm_luts.lut1d_func) { - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) - m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; - else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, - mcm_luts.lut1d_func, - &dpp_base->regamma_params, false); + lut_enable = cm->flags.bits.blend_enable; + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (lut_enable) { + if (cm->blend_func.type == TF_TYPE_HWPWL) + m_lut_params.pwl = &cm->blend_func.pwl; + else if (cm->blend_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &cm->blend_func, + &dpp_base->regamma_params, + false); m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; } - if (m_lut_params.pwl) { - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + + if (!m_lut_params.pwl) { + lut_enable = false; } - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } else { + lut_enable = false; } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); + if (lut_enable && mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, &m_lut_params, lut_bank_a, mpcc_id); + /* Shaper */ - if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + lut_enable = cm->flags.bits.shaper_enable; + if (lut_enable) { memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts.shaper->type == TF_TYPE_HWPWL) - m_lut_params.pwl = &mcm_luts.shaper->pwl; - else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + if (cm->shaper_func.type == TF_TYPE_HWPWL) + m_lut_params.pwl = &cm->shaper_func.pwl; + else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { ASSERT(false); - rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, - mcm_luts.shaper, - &dpp_base->regamma_params, true); - m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &cm->shaper_func, + &dpp_base->shaper_params, + true); + m_lut_params.pwl = rval ? &dpp_base->shaper_params : NULL; } - if (m_lut_params.pwl) { - if (mpc->funcs->mcm.populate_lut) - mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + if (!m_lut_params.pwl) { + lut_enable = false; } + } else { + lut_enable = false; } - /* 3DLUT */ - switch (lut3d_src) { - case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, false); - - if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { - m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, - mpcc_id); - } - break; - case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: - switch (mcm_luts.lut3d_data.gpu_mem_params.size) { - case DC_CM2_GPU_MEM_SIZE_171717: - width = hubp_3dlut_fl_width_17; - break; - case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: - width = hubp_3dlut_fl_width_transformed; - break; - default: - //TODO: handle default case - break; - } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); + if (lut_enable && mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER, &m_lut_params, lut_bank_a, mpcc_id); - //check for support - if (mpc->funcs->mcm.is_config_supported && - !mpc->funcs->mcm.is_config_supported(width)) - break; + /* NOTE: Toggling from DMA->Host is not supported atomically as hardware + * blocks writes until 3DLUT FL mode is cleared from HUBP on VUpdate. + * Expectation is either option is used consistently. + */ - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + /* 3DLUT */ + lut_enable = cm->flags.bits.lut3d_enable; + if (lut_enable && cm->flags.bits.lut3d_dma_enable) { + /* Fast (DMA) Load Mode */ + /* MPC */ if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); - - if (mpc->funcs->mcm.program_bit_depth) - mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut_enable, lut_bank_a, cm->lut3d_dma.size, mpcc_id); - switch (mcm_luts.lut3d_data.gpu_mem_params.layout) { - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: - mode = hubp_3dlut_fl_mode_native_1; - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: - mode = hubp_3dlut_fl_mode_native_2; - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: - mode = hubp_3dlut_fl_mode_transform; - addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; - break; - default: - mode = hubp_3dlut_fl_mode_disable; - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - } - if (hubp->funcs->hubp_program_3dlut_fl_mode) - hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + /* only supports 12 bit */ + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id); - if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) - hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); - switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: - format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: - format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: - format = hubp_3dlut_fl_format_float_fp1_5_10; - break; - } - if (hubp->funcs->hubp_program_3dlut_fl_format) - hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); - if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && - mpc->funcs->mcm.program_bias_scale) { - mpc->funcs->mcm.program_bias_scale(mpc, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, - mpcc_id); - hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); - } - - //navi 4x has a bug and r and blue are swapped and need to be worked around here in - //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x - switch (mcm_luts.lut3d_data.gpu_mem_params.component_order) { - case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: - default: - crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } + /* HUBP */ + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); if (hubp->funcs->hubp_program_3dlut_fl_crossbar) - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, - crossbar_bit_slice_cr_r, - crossbar_bit_slice_y_g, - crossbar_bit_slice_cb_b); - - if (mpc->funcs->mcm.program_lut_read_write_control) - mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); - if (mpc->funcs->mcm.program_3dlut_size) - mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); - - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); - if (hubp->funcs->hubp_enable_3dlut_fl) + if (hubp->funcs->hubp_enable_3dlut_fl) { hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - else { - if (mpc->funcs->program_lut_mode) { - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - } + } else { + /* GPU memory only supports fast load path */ + BREAK_TO_DEBUGGER(); + lut_enable = false; + result = false; } - break; + } else { + /* Legacy (Host) Load Mode */ + memset(&m_lut_params, 0, sizeof(m_lut_params)); - } -} + if (cm->flags.bits.lut3d_enable && cm->lut3d_func.state.bits.initialized) { + m_lut_params.lut3d = &cm->lut3d_func.lut_3d; + } else { + lut_enable = false; + } -void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) -{ - struct hubp *hubp = pipe_ctx->plane_res.hubp; + /* MPC */ + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, + MCM_LUT_3DLUT, + lut_enable, + lut_bank_a, + cm->lut3d_func.lut_3d.use_tetrahedral_9 ? CM_LUT_SIZE_999 : CM_LUT_SIZE_171717, + mpcc_id); + + if (lut_enable) { + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, + MCM_LUT_3DLUT, + lut_bank_a, + cm->lut3d_func.lut_3d.use_12bits ? 12 : 10, + mpcc_id); - if (hubp->funcs->hubp_enable_3dlut_fl) { - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - } -} + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, 0xf); -bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) -{ - struct dpp *dpp_base = pipe_ctx->plane_res.dpp; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; - struct mpc *mpc = dc->res_pool->mpc; - bool result; - const struct pwl_params *lut_params = NULL; - bool rval; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, &m_lut_params, lut_bank_a, mpcc_id); + } - if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); - return true; - } + /* HUBP */ + memset(&lut3d_dma, 0, sizeof(lut3d_dma)); + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; - // 1D LUT - if (plane_state->blend_tf.type == TF_TYPE_HWPWL) - lut_params = &plane_state->blend_tf.pwl; - else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &plane_state->blend_tf, - &dpp_base->regamma_params, false); - lut_params = rval ? &dpp_base->regamma_params : NULL; - } - result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); - lut_params = NULL; - - // Shaper - if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) - lut_params = &plane_state->in_shaper_func.pwl; - else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - // TODO: dpp_base replace - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &plane_state->in_shaper_func, - &dpp_base->shaper_params, true); - lut_params = rval ? &dpp_base->shaper_params : NULL; - } - result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); - - // 3D - if (mpc->funcs->program_3dlut) { - if (plane_state->lut3d_func.state.bits.initialized == 1) - result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); - else - result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); } return result; @@ -982,6 +865,8 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) } } + link_hwss->setup_stream_attribute(pipe_ctx); + if (dc->res_pool->dccg->funcs->set_pixel_rate_div) { dc->res_pool->dccg->funcs->set_pixel_rate_div( dc->res_pool->dccg, @@ -1930,10 +1815,9 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) { for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { - if (mpc_pipe->plane_state && mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src - == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM - && mpc_pipe->plane_state->mcm_shaper_3dlut_setting - == DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT) { + if (mpc_pipe->plane_state && + mpc_pipe->plane_state->cm.flags.bits.lut3d_enable && + mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) { wa_pipes[wa_pipe_ct++] = mpc_pipe; } } @@ -2060,6 +1944,22 @@ void dcn401_reset_back_end_for_pipe( DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); } +static void dc_hwss_disable_otg_pwa(struct dc *dc) +{ + if (dc->debug.enable_otg_frame_sync_pwa) { + int i; + + /*reset all the otg*/ + for (i = dc->res_pool->timing_generator_count - 1; i >= 0 ; i--) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + + if (tg->funcs->disable_otg_pwa) { + tg->funcs->disable_otg_pwa(tg); + DC_LOG_DC("otg frame sync pwa disabled on otg%d\n", tg->inst); + } + } + } +} void dcn401_reset_hw_ctx_wrap( struct dc *dc, @@ -2068,6 +1968,7 @@ void dcn401_reset_hw_ctx_wrap( int i; struct dce_hwseq *hws = dc->hwseq; + dc_hwss_disable_otg_pwa(dc); /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = @@ -2258,6 +2159,10 @@ void dcn401_program_pipe( pipe_ctx->stream_res.test_pattern_params.height, pipe_ctx->stream_res.test_pattern_params.offset); } + if (pipe_ctx->plane_state + && pipe_ctx->plane_state->update_flags.bits.cm_hist_change + && hws->funcs.program_cm_hist) + hws->funcs.program_cm_hist(dc, pipe_ctx, pipe_ctx->plane_state); } /* @@ -2409,6 +2314,13 @@ void dcn401_program_pipe_sequence( pipe_ctx->stream_res.test_pattern_params.offset); } + if (pipe_ctx->plane_state + && pipe_ctx->plane_state->update_flags.bits.cm_hist_change + && hws->funcs.program_cm_hist) { + + hwss_add_dpp_program_cm_hist(seq_state, pipe_ctx->plane_res.dpp, + pipe_ctx->plane_state->cm_hist_control, pipe_ctx->plane_state->color_space); + } } void dcn401_program_front_end_for_ctx( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index f0e1ed0f29499..8e12dc1297c4d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -261,7 +261,7 @@ void dcn42_init_hw(struct dc *dc) dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) - dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); + dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->clk_mgr->bw_params->num_channels, dc->config.sdpif_request_limit_words_per_umc); // Get DMCUB capabilities if (dc->ctx->dmub_srv) { @@ -275,8 +275,7 @@ void dcn42_init_hw(struct dc *dc) || res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq) { /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ if (dc->clk_mgr) - dc->res_pool->funcs->update_bw_bounding_box(dc, - dc->clk_mgr->bw_params); + dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); } } if (dc->res_pool->pg_cntl) { @@ -383,68 +382,6 @@ void dcn42_program_cm_hist( plane_state->cm_hist_control, plane_state->color_space); } -static void dc_get_lut_xbar( - enum dc_cm2_gpu_mem_pixel_component_order order, - enum hubp_3dlut_fl_crossbar_bit_slice *cr_r, - enum hubp_3dlut_fl_crossbar_bit_slice *y_g, - enum hubp_3dlut_fl_crossbar_bit_slice *cb_b) -{ - switch (order) { - case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: - *cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; - *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; - break; - case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA: - *cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - *y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - *cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } -} - -static void dc_get_lut_mode( - enum dc_cm2_gpu_mem_layout layout, - enum hubp_3dlut_fl_mode *mode, - enum hubp_3dlut_fl_addressing_mode *addr_mode) -{ - switch (layout) { - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: - *mode = hubp_3dlut_fl_mode_native_1; - *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: - *mode = hubp_3dlut_fl_mode_native_2; - *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: - *mode = hubp_3dlut_fl_mode_transform; - *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; - break; - default: - *mode = hubp_3dlut_fl_mode_disable; - *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - } -} - -static void dc_get_lut_format( - enum dc_cm2_gpu_mem_format dc_format, - enum hubp_3dlut_fl_format *format) -{ - switch (dc_format) { - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: - *format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: - *format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: - *format = hubp_3dlut_fl_format_float_fp1_5_10; - break; - } -} - static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) { if (mpc->funcs->rmcm.power_on_shaper_3dlut && @@ -455,119 +392,17 @@ static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) return false; } -static bool is_rmcm_3dlut_fl_supported(struct dc *dc, enum dc_cm2_gpu_mem_size size) -{ - if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut) - return false; - if (size == DC_CM2_GPU_MEM_SIZE_171717) - return (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17); - else if (size == DC_CM2_GPU_MEM_SIZE_333333) - return (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33); - return false; -} - -static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend) -{ - struct mpc *mpc = dc->res_pool->mpc; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - - if (!pipe_ctx->plane_state) - return; - - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = (bPostBlend) ? - MPCC_MOVABLE_CM_LOCATION_AFTER : - MPCC_MOVABLE_CM_LOCATION_BEFORE; -} - -static void dcn42_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, - enum MCM_LUT_XABLE *shaper_xable, - enum MCM_LUT_XABLE *lut3d_xable, - enum MCM_LUT_XABLE *lut1d_xable) -{ - enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; - bool lut1d_enable = false; - struct mpc *mpc = dc->res_pool->mpc; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - - if (!pipe_ctx->plane_state) - return; - shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; - lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; - - *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; - - switch (shaper_3dlut_setting) { - case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: - *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; - break; - case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: - *lut3d_xable = MCM_LUT_DISABLE; - *shaper_xable = MCM_LUT_ENABLE; - break; - case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: - *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; - break; - } -} - -static void fl_get_lut_mode( - enum dc_cm2_gpu_mem_layout layout, - enum dc_cm2_gpu_mem_size size, - enum hubp_3dlut_fl_mode *mode, - enum hubp_3dlut_fl_addressing_mode *addr_mode, - enum hubp_3dlut_fl_width *width) -{ - *width = hubp_3dlut_fl_width_17; - - if (size == DC_CM2_GPU_MEM_SIZE_333333) - *width = hubp_3dlut_fl_width_33; - - switch (layout) { - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: - *mode = hubp_3dlut_fl_mode_native_1; - *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: - *mode = hubp_3dlut_fl_mode_native_2; - *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: - *mode = hubp_3dlut_fl_mode_transform; - *addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; - break; - default: - *mode = hubp_3dlut_fl_mode_disable; - *addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - } -} - bool dcn42_program_rmcm_luts( struct hubp *hubp, struct pipe_ctx *pipe_ctx, - enum dc_cm2_transfer_func_source lut3d_src, - struct dc_cm2_func_luts *mcm_luts, + const struct dc_plane_cm *cm, struct mpc *mpc, - bool lut_bank_a, int mpcc_id) { struct dpp *dpp_base = pipe_ctx->plane_res.dpp; union mcm_lut_params m_lut_params = {0}; - enum MCM_LUT_XABLE shaper_xable, lut3d_xable = MCM_LUT_DISABLE, lut1d_xable; - enum hubp_3dlut_fl_mode mode; - enum hubp_3dlut_fl_addressing_mode addr_mode; - enum hubp_3dlut_fl_format format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; - enum hubp_3dlut_fl_width width = hubp_3dlut_fl_width_17; - struct dc *dc = hubp->ctx->dc; - struct hubp_fl_3dlut_config fl_config; struct mpc_fl_3dlut_config mpc_fl_config; struct dc_stream_state *stream = pipe_ctx->stream; @@ -575,25 +410,23 @@ bool dcn42_program_rmcm_luts( // true->false when it can be allocated at DI time struct dc_rmcm_3dlut *rmcm_3dlut = dc_stream_get_3dlut_for_stream(dc, stream, false); + bool lut_bank_a = true; // TODO get from HW + //check to see current pipe is part of a stream with allocated rmcm 3dlut if (!rmcm_3dlut) return false; - rmcm_3dlut->protection_bits = mcm_luts->lut3d_data.rmcm_tmz; - - dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); - /* Shaper */ - if (mcm_luts->shaper) { + if (cm->flags.bits.shaper_enable) { memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts->shaper->type == TF_TYPE_HWPWL) { - m_lut_params.pwl = &mcm_luts->shaper->pwl; - } else if (mcm_luts->shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + if (cm->shaper_func.type == TF_TYPE_HWPWL) { + m_lut_params.pwl = &cm->shaper_func.pwl; + } else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { ASSERT(false); cm_helper_translate_curve_to_hw_format( dc->ctx, - mcm_luts->shaper, + &cm->shaper_func, &dpp_base->shaper_params, true); m_lut_params.pwl = &dpp_base->shaper_params; } @@ -609,58 +442,21 @@ bool dcn42_program_rmcm_luts( } /* 3DLUT */ - switch (lut3d_src) { - case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: + if (!cm->flags.bits.lut3d_dma_enable) { memset(&m_lut_params, 0, sizeof(m_lut_params)); // Don't know what to do in this case. - //case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: - break; - case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: - fl_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, - mcm_luts->lut3d_data.gpu_mem_params.size, - &mode, - &addr_mode, - &width); - - if (!dc_is_rmcm_3dlut_supported(hubp, mpc) || - !mpc->funcs->rmcm.is_config_supported( - (width == hubp_3dlut_fl_width_17 || - width == hubp_3dlut_fl_width_transformed) ? 17 : 33)) + } else { + if (!dc_is_rmcm_3dlut_supported(hubp, mpc)) return false; - // setting native or transformed mode, - dc_get_lut_mode(mcm_luts->lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); - //seems to be only for the MCM - dc_get_lut_format(mcm_luts->lut3d_data.gpu_mem_params.format_params.format, &format); - - dc_get_lut_xbar( - mcm_luts->lut3d_data.gpu_mem_params.component_order, - &crossbar_bit_slice_cr_r, - &crossbar_bit_slice_y_g, - &crossbar_bit_slice_cb_b); - - fl_config.mode = mode; - fl_config.enabled = lut3d_xable != MCM_LUT_DISABLE; - fl_config.address = mcm_luts->lut3d_data.gpu_mem_params.addr; - fl_config.format = format; - fl_config.crossbar_bit_slice_y_g = crossbar_bit_slice_y_g; - fl_config.crossbar_bit_slice_cb_b = crossbar_bit_slice_cb_b; - fl_config.crossbar_bit_slice_cr_r = crossbar_bit_slice_cr_r; - fl_config.width = width; - fl_config.protection_bits = rmcm_3dlut->protection_bits; - fl_config.addr_mode = addr_mode; - fl_config.layout = mcm_luts->lut3d_data.gpu_mem_params.layout; - fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; - fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; - - mpc_fl_config.enabled = fl_config.enabled; - mpc_fl_config.width = width; + mpc_fl_config.enabled = cm->flags.bits.lut3d_enable; + mpc_fl_config.size = cm->lut3d_dma.size; mpc_fl_config.select_lut_bank_a = lut_bank_a; - mpc_fl_config.bit_depth = mcm_luts->lut3d_data.gpu_mem_params.bit_depth; + mpc_fl_config.bit_depth = 0; mpc_fl_config.hubp_index = hubp->inst; - mpc_fl_config.bias = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.bias; - mpc_fl_config.scale = mcm_luts->lut3d_data.gpu_mem_params.format_params.float_params.scale; + mpc_fl_config.bias = cm->lut3d_dma.bias; + mpc_fl_config.scale = cm->lut3d_dma.scale; //1. power down the block mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, false); @@ -668,268 +464,44 @@ bool dcn42_program_rmcm_luts( //2. program RMCM - 3dlut reg programming mpc->funcs->rmcm.fl_3dlut_configure(mpc, &mpc_fl_config, mpcc_id); - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &fl_config); + /* HUBP */ + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); //3. power on the block mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, true); - - break; - default: - return false; } return true; } -void dcn42_populate_mcm_luts(struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_cm2_func_luts mcm_luts, - bool lut_bank_a) +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { - struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; struct hubp *hubp = pipe_ctx->plane_res.hubp; - int mpcc_id = hubp->inst; + const struct dc_plane_cm *cm = &plane_state->cm; struct mpc *mpc = dc->res_pool->mpc; - union mcm_lut_params m_lut_params; - enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; - enum hubp_3dlut_fl_format format = 0; - enum hubp_3dlut_fl_mode mode; - enum hubp_3dlut_fl_width width = 0; - enum hubp_3dlut_fl_addressing_mode addr_mode; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; - enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; - enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; - enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; - bool rval; - - dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); - - //MCM - setting its location (Before/After) blender - //set to post blend (true) - dcn42_set_mcm_location_post_blend( - dc, - pipe_ctx, - mcm_luts.lut3d_data.mpc_mcm_post_blend); - - //RMCM - 3dLUT+Shaper - if (mcm_luts.lut3d_data.rmcm_3dlut_enable && - is_rmcm_3dlut_fl_supported(dc, mcm_luts.lut3d_data.gpu_mem_params.size)) { + int mpcc_id = hubp->inst; + bool result; + + /* MCM */ + result = dcn401_set_mcm_luts(pipe_ctx, plane_state); + + /* RMCM */ + if (cm->flags.bits.rmcm_enable && cm->flags.bits.lut3d_dma_enable) { + /* TODO - move RMCM to its own block */ dcn42_program_rmcm_luts( hubp, pipe_ctx, - lut3d_src, - &mcm_luts, + cm, mpc, - lut_bank_a, mpcc_id); } - /* 1D LUT */ - if (mcm_luts.lut1d_func) { - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) - m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; - else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, - mcm_luts.lut1d_func, - &dpp_base->regamma_params, false); - m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; - } - if (m_lut_params.pwl) { - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); - } - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); - } - - /* Shaper */ - if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts.shaper->type == TF_TYPE_HWPWL) - m_lut_params.pwl = &mcm_luts.shaper->pwl; - else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { - ASSERT(false); - rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, - mcm_luts.shaper, - &dpp_base->regamma_params, true); - m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; - } - if (m_lut_params.pwl) { - if (mpc->funcs->mcm.populate_lut) - mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); - } - } - - /* 3DLUT */ - switch (lut3d_src) { - case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, false); - - if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { - m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, - mpcc_id); - } - break; - case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: - switch (mcm_luts.lut3d_data.gpu_mem_params.size) { - case DC_CM2_GPU_MEM_SIZE_333333: - width = hubp_3dlut_fl_width_33; - break; - case DC_CM2_GPU_MEM_SIZE_171717: - width = hubp_3dlut_fl_width_17; - break; - case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: - width = hubp_3dlut_fl_width_transformed; - break; - default: - //TODO: Handle default case - break; - } - - //check for support - if (mpc->funcs->mcm.is_config_supported && - !mpc->funcs->mcm.is_config_supported(width)) - break; - - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); - - if (mpc->funcs->mcm.program_bit_depth) - mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); - - dc_get_lut_mode(mcm_luts.lut3d_data.gpu_mem_params.layout, &mode, &addr_mode); - if (hubp->funcs->hubp_program_3dlut_fl_mode) - hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); - - if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) - hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); - - switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: - format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: - format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: - format = hubp_3dlut_fl_format_float_fp1_5_10; - break; - } - if (hubp->funcs->hubp_program_3dlut_fl_format) - hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); - if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && - mpc->funcs->mcm.program_bias_scale) { - mpc->funcs->mcm.program_bias_scale(mpc, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, - mpcc_id); - hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); - } - - //navi 4x has a bug and r and blue are swapped and need to be worked around here in - //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x - dc_get_lut_xbar( - mcm_luts.lut3d_data.gpu_mem_params.component_order, - &crossbar_bit_slice_cr_r, - &crossbar_bit_slice_y_g, - &crossbar_bit_slice_cb_b); - - if (hubp->funcs->hubp_program_3dlut_fl_crossbar) - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, - crossbar_bit_slice_cr_r, - crossbar_bit_slice_y_g, - crossbar_bit_slice_cb_b); - - if (mpc->funcs->mcm.program_lut_read_write_control) - mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); - - if (mpc->funcs->mcm.program_3dlut_size) - mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); - - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); - - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - else { - if (mpc->funcs->program_lut_mode) { - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - } - } - break; - } -} - -bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) -{ - struct dpp *dpp_base = pipe_ctx->plane_res.dpp; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; - struct mpc *mpc = dc->res_pool->mpc; - bool result; - const struct pwl_params *lut_params = NULL; - bool rval; - - if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); - return true; - } - - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; - // 1D LUT - if (plane_state->blend_tf.type == TF_TYPE_HWPWL) - lut_params = &plane_state->blend_tf.pwl; - else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &plane_state->blend_tf, - &dpp_base->regamma_params, false); - lut_params = rval ? &dpp_base->regamma_params : NULL; - } - result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); - lut_params = NULL; - - // Shaper - if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) - lut_params = &plane_state->in_shaper_func.pwl; - else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - // TODO: dpp_base replace - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &plane_state->in_shaper_func, - &dpp_base->shaper_params, true); - lut_params = rval ? &dpp_base->shaper_params : NULL; - } - result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); - - // 3D - if (mpc->funcs->program_3dlut) { - if (plane_state->lut3d_func.state.bits.initialized == 1) - result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); - else - result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); - } - return result; } void dcn42_hardware_release(struct dc *dc) @@ -1050,7 +622,7 @@ void dcn42_prepare_bandwidth( dc->hwss.hw_block_power_up(dc, &pg_update_state); } - dcn20_prepare_bandwidth(dc, context); + dcn401_prepare_bandwidth(dc, context); } void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context) @@ -1470,3 +1042,50 @@ void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params) dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); } } + +/* In headless boot cases, DIG may be turned + * on which causes HW/SW discrepancies. + * To avoid this, power down hardware on boot + * if DIG is turned on + */ +void dcn42_power_down_on_boot(struct dc *dc) +{ + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link = NULL; + int edp_num; + int i = 0; + + dc_get_edp_links(dc, edp_links, &edp_num); + if (edp_num) + edp_link = edp_links[0]; + + if (edp_link && edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwseq->funcs.edp_backlight_control && + dc->hwseq->funcs.power_down && + dc->hwss.edp_power_control) { + dc->hwseq->funcs.edp_backlight_control(edp_link, false); + dc->hwseq->funcs.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } else { + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->link_enc && link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc) && + dc->hwseq->funcs.power_down) { + dc->hwseq->funcs.power_down(dc); + break; + } + + } + } + + /* + * Call update_clocks with empty context + * to send DISPLAY_OFF + * Otherwise DISPLAY_OFF may not be asserted + */ + if (dc->clk_mgr->funcs->set_low_power_state) + dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr); +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h index 89ebb6520eaf5..c4cfeed45b190 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h @@ -18,18 +18,11 @@ void dcn42_program_cm_hist( bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); -void dcn42_populate_mcm_luts(struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_cm2_func_luts mcm_luts, - bool lut_bank_a); - bool dcn42_program_rmcm_luts( struct hubp *hubp, struct pipe_ctx *pipe_ctx, - enum dc_cm2_transfer_func_source lut3d_src, - struct dc_cm2_func_luts *mcm_luts, + const struct dc_plane_cm *cm, struct mpc *mpc, - bool lut_bank_a, int mpcc_id); void dcn42_hardware_release(struct dc *dc); @@ -50,4 +43,5 @@ void dcn42_root_clock_control(struct dc *dc, void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock); void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params); void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc); +void dcn42_power_down_on_boot(struct dc *dc); #endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c index a8e2f59d5e505..b324a2195e8a6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c @@ -19,7 +19,7 @@ static const struct hw_sequencer_funcs dcn42_funcs = { .program_gamut_remap = dcn401_program_gamut_remap, .init_hw = dcn42_init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, - .power_down_on_boot = dcn35_power_down_on_boot, + .power_down_on_boot = dcn42_power_down_on_boot, .apply_ctx_for_surface = NULL, .program_front_end_for_ctx = dcn401_program_front_end_for_ctx, .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling, @@ -64,6 +64,12 @@ static const struct hw_sequencer_funcs dcn42_funcs = { .set_cursor_position = dcn401_set_cursor_position, .set_cursor_attribute = dcn10_set_cursor_attribute, .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .abort_cursor_offload_update = dcn35_abort_cursor_offload_update, + .begin_cursor_offload_update = dcn35_begin_cursor_offload_update, + .commit_cursor_offload_update = dcn35_commit_cursor_offload_update, + .update_cursor_offload_pipe = dcn401_update_cursor_offload_pipe, + .notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update, + .program_cursor_offload_now = dcn35_program_cursor_offload_now, .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, .set_clock = dcn10_set_clock, .get_clock = dcn10_get_clock, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index a79019365af8c..2a5a81d159507 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -89,7 +89,7 @@ enum hubp_3dlut_fl_addressing_mode { enum hubp_3dlut_fl_width { hubp_3dlut_fl_width_17 = 17, hubp_3dlut_fl_width_33 = 33, - hubp_3dlut_fl_width_transformed = 4916, //mpc default + hubp_3dlut_fl_width_17_transformed = 4916, //mpc default }; enum hubp_3dlut_fl_crossbar_bit_slice { @@ -99,22 +99,6 @@ enum hubp_3dlut_fl_crossbar_bit_slice { hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 }; -struct hubp_fl_3dlut_config { - bool enabled; - enum hubp_3dlut_fl_width width; - enum hubp_3dlut_fl_mode mode; - enum hubp_3dlut_fl_format format; - uint16_t bias; - uint16_t scale; - struct dc_plane_address address; - enum hubp_3dlut_fl_addressing_mode addr_mode; - enum dc_cm2_gpu_mem_layout layout; - uint8_t protection_bits; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; -}; - struct hubp { const struct hubp_funcs *funcs; struct dc_context *ctx; @@ -243,7 +227,6 @@ struct hubp_funcs { void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); void (*hubp_init)(struct hubp *hubp); - void (*dmdata_set_attributes)( struct hubp *hubp, const struct dc_dmdata_attributes *attr); @@ -290,24 +273,15 @@ struct hubp_funcs { void (*hubp_wait_pipe_read_start)(struct hubp *hubp); void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); - void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); - void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, - enum hubp_3dlut_fl_mode mode); - void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, - enum hubp_3dlut_fl_format format); void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, - const struct dc_plane_address address); + const struct dc_plane_address *address); + void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, + const struct dc_3dlut_dma *config); void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); - void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); - void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); - void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits); void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + enum dc_cm_lut_pixel_format format); int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); - void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index a61d12ec61bc4..b152f68794954 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -152,6 +152,13 @@ struct dc_rgb { uint32_t blue; }; +struct tetrahedral_33x33x33 { + struct dc_rgb lut0[8985]; + struct dc_rgb lut1[8984]; + struct dc_rgb lut2[8984]; + struct dc_rgb lut3[8984]; +}; + struct tetrahedral_17x17x17 { struct dc_rgb lut0[1229]; struct dc_rgb lut1[1228]; @@ -165,14 +172,23 @@ struct tetrahedral_9x9x9 { struct dc_rgb lut3[182]; }; +enum lut_dimension { + LUT_DIM_INVALID = 0, + LUT_DIM_9 = 9, + LUT_DIM_17 = 17, + LUT_DIM_33 = 33, +}; + struct tetrahedral_params { union { +//TODO: Uncomment when in use. +// struct tetrahedral_33x33x33 tetrahedral_33; struct tetrahedral_17x17x17 tetrahedral_17; struct tetrahedral_9x9x9 tetrahedral_9; }; bool use_tetrahedral_9; bool use_12bits; - + enum lut_dimension lut_dim; }; /* arr_curve_points - regamma regions/segments specification diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 0db607f2a4105..f5617674bea8e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -54,6 +54,7 @@ #include "dc_hw_types.h" #include "hw_shared.h" #include "transform.h" +#include "dc_types.h" #define MAX_MPCC 6 #define MAX_OPP 6 @@ -66,7 +67,6 @@ enum mpc_output_csc_mode { MPC_OUTPUT_CSC_COEF_B }; - enum mpcc_blend_mode { MPCC_BLEND_MODE_BYPASS, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH, @@ -102,13 +102,6 @@ enum mpcc_movable_cm_location { MPCC_MOVABLE_CM_LOCATION_AFTER, }; -enum MCM_LUT_XABLE { - MCM_LUT_DISABLE, - MCM_LUT_DISABLED = MCM_LUT_DISABLE, - MCM_LUT_ENABLE, - MCM_LUT_ENABLED = MCM_LUT_ENABLE, -}; - enum MCM_LUT_ID { MCM_LUT_3DLUT, MCM_LUT_1DLUT, @@ -117,7 +110,7 @@ enum MCM_LUT_ID { struct mpc_fl_3dlut_config { bool enabled; - uint16_t width; + enum dc_cm_lut_size size; bool select_lut_bank_a; uint16_t bit_depth; int hubp_index; @@ -1042,22 +1035,22 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); -/** - * @get_3dlut_fast_load_status: - * - * Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. - * - * Parameters: - * - [in/out] mpc - MPC context. - * - [in] mpcc_id - * - [in/out] done - * - [in/out] soft_underflow - * - [in/out] hard_underflow - * - * Return: - * - * void - */ + /** + * @get_3dlut_fast_load_status: + * + * Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id + * - [in/out] done + * - [in/out] soft_underflow + * - [in/out] hard_underflow + * + * Return: + * + * void + */ void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); /** @@ -1076,8 +1069,11 @@ struct mpc_funcs { * * void */ - void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id); + void (*populate_lut)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const union mcm_lut_params *params, + const bool lut_bank_a, + const int mpcc_id); /** * @program_lut_read_write_control: @@ -1088,13 +1084,18 @@ struct mpc_funcs { * - [in/out] mpc - MPC context. * - [in] id * - [in] lut_bank_a + * - [in] bit_depth * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); + void (*program_lut_read_write_control)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const bool lut_bank_a, + const unsigned int bit_depth, + const int mpcc_id); /** * @program_lut_mode: @@ -1104,33 +1105,44 @@ struct mpc_funcs { * Parameters: * - [in/out] mpc - MPC context. * - [in] id - * - [in] xable + * - [in] enable * - [in] lut_bank_a + * - [in] size * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, - bool lut_bank_a, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const bool enable, + const bool lut_bank_a, + const enum dc_cm_lut_size size, + const int mpcc_id); - /** - * @mcm: - * - * MPC MCM new HW sequential programming functions - */ - struct { - void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); - void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); - void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); - bool (*is_config_supported)(uint32_t width); - void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, - bool lut_bank_a, bool enabled, int mpcc_id); - void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id); - } mcm; + /** + * @get_lut_mode: + * + * Obtains enablement and ram bank status. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] mpcc_id + * - [out] enable + * - [out] lut_bank_a + * + * Return: + * + * void + */ + void (*get_lut_mode)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const int mpcc_id, + bool *enable, + bool *lut_bank_a); /** * @rmcm: @@ -1143,9 +1155,11 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); - void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable, - bool lut_bank_a, int mpcc_id); - void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, + bool enable, + bool lut_bank_a, + int mpcc_id); + void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 79746d931471a..cecd3282a29f7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -60,6 +60,7 @@ struct resource_caps { int num_hpo_dp_stream_encoder; int num_hpo_dp_link_encoder; int num_mpc_3dlut; + int num_rmcm; }; struct resource_straps { diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index ce1ee2062e41d..e0617db2d0c1d 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -73,56 +73,15 @@ void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_locati } } -static enum dc_lut_mode get3dlut_config( - struct mpc *mpc, - bool *is_17x17x17, - bool *is_12bits_color_channel, - int mpcc_id) -{ - uint32_t i_mode, i_enable_10bits, lut_size; - enum dc_lut_mode mode; - struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); - - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], - MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode); - - REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], - MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits); - - switch (i_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - if (i_enable_10bits > 0) - *is_12bits_color_channel = false; - else - *is_12bits_color_channel = true; - - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); - - if (lut_size == 0) - *is_17x17x17 = true; - else - *is_17x17x17 = false; - - return mode; -} - -void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id) +void mpc401_populate_lut(struct mpc *mpc, + const enum MCM_LUT_ID id, + const union mcm_lut_params *params, + const bool lut_bank_a, + const int mpcc_id) { const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; - const struct pwl_params *lut1d = params.pwl; - const struct pwl_params *lut_shaper = params.pwl; + const struct pwl_params *lut1d = params->pwl; + const struct pwl_params *lut_shaper = params->pwl; bool is_17x17x17; bool is_12bits_color_channel; const struct dc_rgb *lut0; @@ -131,7 +90,7 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union const struct dc_rgb *lut3; int lut_size0; int lut_size; - const struct tetrahedral_params *lut3d = params.lut3d; + const struct tetrahedral_params *lut3d = params->lut3d; switch (id) { case MCM_LUT_1DLUT: @@ -174,8 +133,6 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); - get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id); - is_17x17x17 = !lut3d->use_tetrahedral_9; is_12bits_color_channel = lut3d->use_12bits; if (is_17x17x17) { @@ -198,8 +155,6 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union sizeof(lut3d->tetrahedral_9.lut1[0]); } - mpc32_select_3dlut_ram(mpc, next_mode, - is_12bits_color_channel, mpcc_id); mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id); if (is_12bits_color_channel) mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id); @@ -232,46 +187,69 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union } +static uint32_t mpc401_cm_lut_size_to_3dlut_size(const enum dc_cm_lut_size cm_size) +{ + uint32_t size = 0; + + switch (cm_size) { + case CM_LUT_SIZE_999: + size = 1; + break; + case CM_LUT_SIZE_171717: + size = 0; + break; + default: + /* invalid LUT size */ + ASSERT(false); + size = 0; + break; + } + + return size; +} + void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const enum MCM_LUT_XABLE xable, - bool lut_bank_a, - int mpcc_id) + const bool enable, + const bool lut_bank_a, + const enum dc_cm_lut_size size, + const int mpcc_id) { + uint32_t lut_size; struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: - switch (xable) { - case MCM_LUT_DISABLE: + if (enable) { + lut_size = mpc401_cm_lut_size_to_3dlut_size(size); + REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2, + MPCC_MCM_3DLUT_SIZE, lut_size); + } else { + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0); - break; - case MCM_LUT_ENABLE: - REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2); - break; } break; case MCM_LUT_SHAPER: - switch (xable) { - case MCM_LUT_DISABLE: - REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0); - break; - case MCM_LUT_ENABLE: + if (enable) { REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); - break; + } else { + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0); } break; case MCM_LUT_1DLUT: - switch (xable) { - case MCM_LUT_DISABLE: - REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], - MPCC_MCM_1DLUT_MODE, 0); - break; - case MCM_LUT_ENABLE: + if (enable) { REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_MODE, 2); - break; + } else { + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_blnd_lut(mpc, mpcc_id, false); + REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], + MPCC_MCM_1DLUT_MODE, 0); } REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_SELECT, lut_bank_a ? 0 : 1); @@ -279,14 +257,20 @@ void mpc401_program_lut_mode( } } -void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id) +void mpc401_program_lut_read_write_control(struct mpc *mpc, + const enum MCM_LUT_ID id, + const bool lut_bank_a, + const unsigned int bit_depth, + const int mpcc_id) { struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id); - REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, (bit_depth == 10) ? 1 : 0, + MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); break; case MCM_LUT_SHAPER: mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); @@ -578,6 +562,44 @@ void mpc401_get_gamut_remap(struct mpc *mpc, arr_reg_val, ARRAY_SIZE(arr_reg_val)); } +void mpc401_get_lut_mode(struct mpc *mpc, + const enum MCM_LUT_ID id, + const int mpcc_id, + bool *enable, + bool *lut_bank_a) +{ + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + uint32_t lut_mode = 0; + uint32_t lut_select = 0; + + *enable = false; + *lut_bank_a = true; + + switch (id) { + case MCM_LUT_SHAPER: + REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], + MPCC_MCM_SHAPER_MODE_CURRENT, &lut_mode); + *enable = lut_mode != 0; + *lut_bank_a = lut_mode != 2; + break; + case MCM_LUT_1DLUT: + REG_GET_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id], + MPCC_MCM_1DLUT_MODE_CURRENT, &lut_mode, + MPCC_MCM_1DLUT_SELECT_CURRENT, &lut_select); + *enable = lut_mode != 0; + *lut_bank_a = lut_mode == 0 || lut_select == 0; + break; + case MCM_LUT_3DLUT: + default: + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE_CURRENT, &lut_mode); + *enable = lut_mode != 0; + *lut_bank_a = lut_mode != 2; + break; + } +} + static const struct mpc_funcs dcn401_mpc_funcs = { .read_mpcc_state = mpc1_read_mpcc_state, .insert_plane = mpc1_insert_plane, @@ -616,6 +638,7 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, + .get_lut_mode = mpc401_get_lut_mode, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h index 6d842d7b95c7e..c16560c84453e 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h @@ -206,21 +206,32 @@ void dcn401_mpc_construct(struct dcn401_mpc *mpc401, int num_rmu); void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); -void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id); +void mpc401_populate_lut(struct mpc *mpc, + const enum MCM_LUT_ID id, + const union mcm_lut_params *params, + bool lut_bank_a, + int mpcc_id); void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const enum MCM_LUT_XABLE xable, - bool lut_bank_a, - int mpcc_id); + const bool enable, + const bool lut_bank_a, + const enum dc_cm_lut_size size, + const int mpcc_id); + +void mpc401_get_lut_mode(struct mpc *mpc, + const enum MCM_LUT_ID id, + const int mpcc_id, + bool *enable, + bool *lut_bank_a); void mpc401_program_lut_read_write_control( struct mpc *mpc, const enum MCM_LUT_ID id, - bool lut_bank_a, - int mpcc_id); + const bool lut_bank_a, + const unsigned int bit_depth, + const int mpcc_id); void mpc401_set_gamut_remap( struct mpc *mpc, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c index 304b23109fb0f..507dbdbea6008 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c @@ -20,7 +20,7 @@ mpc42->mpc_shift->field_name, mpc42->mpc_mask->field_name -static void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst) +void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst) { mpcc->mpcc_id = mpcc_inst; mpcc->dpp_id = 0xf; @@ -63,154 +63,6 @@ void mpc42_update_blending( mpcc->blnd_cfg = *blnd_cfg; } -/* Shaper functions */ -void mpc42_power_on_shaper_3dlut( - struct mpc *mpc, - uint32_t mpcc_id, - bool power_on) -{ - uint32_t power_status_shaper = 2; - uint32_t power_status_3dlut = 2; - struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - int max_retries = 10; - - REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, - MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0); - REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, - MPCC_MCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1:0); - /* wait for memory to fully power up */ - if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { - REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); - REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); - } - - /*read status is not mandatory, it is just for debugging*/ - REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); - REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); - - if (power_status_shaper != 0 && power_on == true) - BREAK_TO_DEBUGGER(); - - if (power_status_3dlut != 0 && power_on == true) - BREAK_TO_DEBUGGER(); -} - -void mpc42_configure_shaper_lut( - struct mpc *mpc, - bool is_ram_a, - uint32_t mpcc_id) -{ - struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - - REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], - MPCC_MCM_SHAPER_SCALE_B, 0x7000); - REG_UPDATE(MPCC_MCM_SHAPER_SCALE_G_B[mpcc_id], - MPCC_MCM_SHAPER_SCALE_G, 0x7000); - REG_UPDATE(MPCC_MCM_SHAPER_SCALE_R[mpcc_id], - MPCC_MCM_SHAPER_SCALE_R, 0x7000); - REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], - MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], - MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); - REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); -} - - -void mpc42_program_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) -{ - struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - uint32_t size = 0xff; - - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); - - REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, - (width == 33) ? 2 : - (width == 17) ? 0 : 2); - - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &size); -} - -void mpc42_program_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) -{ - struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - - REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_R[mpcc_id], - MPCC_MCM_3DLUT_OUT_OFFSET_R, bias, - MPCC_MCM_3DLUT_OUT_SCALE_R, scale); - - REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_G[mpcc_id], - MPCC_MCM_3DLUT_OUT_OFFSET_G, bias, - MPCC_MCM_3DLUT_OUT_SCALE_G, scale); - - REG_UPDATE_2(MPCC_MCM_3DLUT_OUT_OFFSET_B[mpcc_id], - MPCC_MCM_3DLUT_OUT_OFFSET_B, bias, - MPCC_MCM_3DLUT_OUT_SCALE_B, scale); -} - -void mpc42_program_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) -{ - struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - - REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK, 0xF); - - //program bit_depth - REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], - MPCC_MCM_3DLUT_30BIT_EN, - (bit_depth == 10) ? 1 : 0); -} - -bool mpc42_is_config_supported(uint32_t width) -{ - if (width == 17) - return true; - - return false; -} - -void mpc42_populate_lut(struct mpc *mpc, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id) -{ - const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; - const struct pwl_params *lut_shaper = params.pwl; - - if (lut_shaper == NULL) - return; - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc42_power_on_shaper_3dlut(mpc, mpcc_id, true); - - mpc42_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); - - if (next_mode == LUT_RAM_A) - mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id); - else - mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); - - mpc32_program_shaper_lut( - mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); - - mpc42_power_on_shaper_3dlut(mpc, mpcc_id, false); -} - -void mpc42_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, - bool lut_bank_a, bool enabled, int mpcc_id) -{ - struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - - switch (id) { - case MCM_LUT_3DLUT: - REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, - (!enabled) ? 0 : - (lut_bank_a) ? 1 : 2); - REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); - break; - case MCM_LUT_SHAPER: - mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); - break; - default: - break; - } -} - /* RMCM Shaper functions */ void mpc42_power_on_rmcm_shaper_3dlut( struct mpc *mpc, @@ -674,32 +526,47 @@ void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_L } } -void mpc42_program_lut_mode(struct mpc *mpc, const enum MCM_LUT_XABLE xable, - bool lut_bank_a, int mpcc_id) +void mpc42_program_lut_mode(struct mpc *mpc, + bool enable, + bool lut_bank_a, + int mpcc_id) { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - switch (xable) { - case MCM_LUT_DISABLE: + if (enable) { + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + } else { REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, 0); + } +} + +static uint32_t mpc42_get_rmcm_3dlut_width( + const enum dc_cm_lut_size size) +{ + uint32_t width = 0; + + switch (size) { + case CM_LUT_SIZE_333333: + width = 2; break; - case MCM_LUT_ENABLE: - REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + case CM_LUT_SIZE_171717: + default: + width = 0; break; } + + return width; } -void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, uint32_t width, int mpcc_id) +void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, + const enum dc_cm_lut_size size, + int mpcc_id) { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); - uint32_t size = 0xff; - - REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); + uint32_t width = mpc42_get_rmcm_3dlut_width(size); - REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, - (width == 33) ? 2 : 0); - - REG_GET(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_SIZE, &size); + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], + MPC_RMCM_3DLUT_SIZE, width); } void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) @@ -731,14 +598,6 @@ void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_ (bit_depth == 10) ? 1 : 0); } -bool mpc42_is_rmcm_config_supported(uint32_t width) -{ - if (width == 17 || width == 33) - return true; - - return false; -} - void mpc42_set_fl_config( struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, @@ -746,6 +605,7 @@ void mpc42_set_fl_config( { struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + uint32_t width = mpc42_get_rmcm_3dlut_width(cfg->size); /* From: Jie Zhou @@ -786,7 +646,7 @@ void mpc42_set_fl_config( //width REG_UPDATE_2(MPC_RMCM_3DLUT_MODE[mpcc_id], - MPC_RMCM_3DLUT_SIZE, (cfg->width == 33) ? 2 : 0, + MPC_RMCM_3DLUT_SIZE, width, MPC_RMCM_3DLUT_MODE, (!cfg->enabled) ? 0 : (cfg->select_lut_bank_a) ? 1 : 2); //connect to hubp @@ -799,182 +659,6 @@ void mpc42_set_fl_config( REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, cfg->enabled ? 0 : 0xF); } -//static void rmcm_program_gamut_remap( -// struct mpc *mpc, -// unsigned int mpcc_id, -// const uint16_t *regval, -// enum mpcc_gamut_remap_id gamut_remap_block_id, -// enum mpcc_gamut_remap_mode_select mode_select) -//{ -// struct color_matrices_reg gamut_regs; -// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); -// -// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || -// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || -// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { -// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); -// return; -// } -// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP) { -// -// if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { -// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, -// MPC_RMCM_GAMUT_REMAP_MODE, mode_select); -// return; -// } -// -// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; -// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; -// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; -// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; -// -// switch (mode_select) { -// case MPCC_GAMUT_REMAP_MODE_SELECT_1: -// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); -// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); -// break; -// case MPCC_GAMUT_REMAP_MODE_SELECT_2: -// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); -// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); -// break; -// default: -// break; -// } -// -// cm_helper_program_color_matrices( -// mpc->ctx, -// regval, -// &gamut_regs); -// -// //select coefficient set to use, set A (MODE_1) or set B (MODE_2) -// REG_SET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], 0, MPC_RMCM_GAMUT_REMAP_MODE, mode_select); -// } -//} - -//static bool is_mpc_legacy_gamut_id(enum mpcc_gamut_remap_id gamut_remap_block_id) -//{ -// if (gamut_remap_block_id == MPCC_OGAM_GAMUT_REMAP || -// gamut_remap_block_id == MPCC_MCM_FIRST_GAMUT_REMAP || -// gamut_remap_block_id == MPCC_MCM_SECOND_GAMUT_REMAP) { -// return true; -// } -// return false; -//} -//static void program_gamut_remap( -// struct mpc *mpc, -// unsigned int mpcc_id, -// const uint16_t *regval, -// enum mpcc_gamut_remap_id gamut_remap_block_id, -// enum mpcc_gamut_remap_mode_select mode_select) -//{ -// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) -// mpc_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); -// else -// rmcm_program_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); -//} - -//void mpc42_set_gamut_remap( -// struct mpc *mpc, -// int mpcc_id, -// const struct mpc_grph_gamut_adjustment *adjust) -//{ -// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); -// unsigned int i = 0; -// uint32_t mode_select = 0; -// -// if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) { -// /* Bypass / Disable if type is bypass or hw */ -// program_gamut_remap(mpc, mpcc_id, NULL, -// adjust->mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0); -// } else { -// struct fixed31_32 arr_matrix[12]; -// uint16_t arr_reg_val[12]; -// -// for (i = 0; i < 12; i++) -// arr_matrix[i] = adjust->temperature_matrix[i]; -// -// convert_float_matrix(arr_reg_val, arr_matrix, 12); -// -// if (is_mpc_legacy_gamut_id(adjust->mpcc_gamut_remap_block_id)) -// REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], -// MPCC_GAMUT_REMAP_MODE_CURRENT, &mode_select); -// else -// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], -// MPC_RMCM_GAMUT_REMAP_MODE_CURRENT, &mode_select); -// -// //If current set in use not set A (MODE_1), then use set A, otherwise use set B -// if (mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_1) -// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_1; -// else -// mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_2; -// -// program_gamut_remap(mpc, mpcc_id, arr_reg_val, -// adjust->mpcc_gamut_remap_block_id, mode_select); -// } -//} - -//static void read_gamut_remap(struct mpc *mpc, -// int mpcc_id, -// uint16_t *regval, -// enum mpcc_gamut_remap_id gamut_remap_block_id, -// uint32_t *mode_select) -//{ -// struct color_matrices_reg gamut_regs = {0}; -// struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); -// -// if (is_mpc_legacy_gamut_id(gamut_remap_block_id)) { -// mpc_read_gamut_remap(mpc, mpcc_id, regval, gamut_remap_block_id, mode_select); -// } -// if (gamut_remap_block_id == MPCC_RMCM_GAMUT_REMAP) { -// //current coefficient set in use -// REG_GET(MPC_RMCM_GAMUT_REMAP_MODE[mpcc_id], MPC_RMCM_GAMUT_REMAP_MODE, mode_select); -// -// gamut_regs.shifts.csc_c11 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C11_A; -// gamut_regs.masks.csc_c11 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C11_A; -// gamut_regs.shifts.csc_c12 = mpc42->mpc_shift->MPCC_GAMUT_REMAP_C12_A; -// gamut_regs.masks.csc_c12 = mpc42->mpc_mask->MPCC_GAMUT_REMAP_C12_A; -// -// switch (*mode_select) { -// case MPCC_GAMUT_REMAP_MODE_SELECT_1: -// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_A[mpcc_id]); -// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_A[mpcc_id]); -// break; -// case MPCC_GAMUT_REMAP_MODE_SELECT_2: -// gamut_regs.csc_c11_c12 = REG(MPC_RMCM_GAMUT_REMAP_C11_C12_B[mpcc_id]); -// gamut_regs.csc_c33_c34 = REG(MPC_RMCM_GAMUT_REMAP_C33_C34_B[mpcc_id]); -// break; -// default: -// break; -// } -// } -// -// if (*mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_0) { -// cm_helper_read_color_matrices( -// mpc42->base.ctx, -// regval, -// &gamut_regs); -// } -//} - -//void mpc42_get_gamut_remap(struct mpc *mpc, -// int mpcc_id, -// struct mpc_grph_gamut_adjustment *adjust) -//{ -// uint16_t arr_reg_val[12] = {0}; -// uint32_t mode_select; -// -// read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select); -// -// if (mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) { -// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; -// return; -// } -// -// adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; -// convert_hw_matrix(adjust->temperature_matrix, -// arr_reg_val, ARRAY_SIZE(arr_reg_val)); -//} - void mpc42_read_mpcc_state( struct mpc *mpc, int mpcc_inst, @@ -1071,14 +755,7 @@ static const struct mpc_funcs dcn42_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, - .mcm = { - .program_lut_read_write_control = mpc42_program_lut_read_write_control, - .program_3dlut_size = mpc42_program_3dlut_size, - .program_bias_scale = mpc42_program_3dlut_fl_bias_scale, - .program_bit_depth = mpc42_program_bit_depth, - .is_config_supported = mpc42_is_config_supported, - .populate_lut = mpc42_populate_lut, - }, + .get_lut_mode = mpc401_get_lut_mode, .rmcm = { .enable_3dlut_fl = mpc42_enable_3dlut_fl, .update_3dlut_fast_load_select = mpc42_update_3dlut_fast_load_select, @@ -1087,7 +764,6 @@ static const struct mpc_funcs dcn42_mpc_funcs = { .program_3dlut_size = mpc42_program_rmcm_3dlut_size, .program_bias_scale = mpc42_program_rmcm_3dlut_fast_load_bias_scale, .program_bit_depth = mpc42_program_rmcm_bit_depth, - .is_config_supported = mpc42_is_rmcm_config_supported, .power_on_shaper_3dlut = mpc42_power_on_rmcm_shaper_3dlut, .populate_lut = mpc42_populate_rmcm_lut, .fl_3dlut_configure = mpc42_set_fl_config, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h index 9b87fd2be904c..a5f7f4f2bb3bc 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h @@ -882,49 +882,7 @@ void dcn42_mpc_construct(struct dcn42_mpc *mpc401, int num_mpcc, int num_rmu); - -void mpc42_program_shaper_lutb_settings( - struct mpc *mpc, - const struct pwl_params *params, - uint32_t mpcc_id); -void mpc42_program_shaper_luta_settings( - struct mpc *mpc, - const struct pwl_params *params, - uint32_t mpcc_id); -void mpc42_configure_shaper_lut( - struct mpc *mpc, - bool is_ram_a, - uint32_t mpcc_id); -void mpc42_power_on_shaper_3dlut( - struct mpc *mpc, - uint32_t mpcc_id, - bool power_on); -void mpc42_program_3dlut_size( - struct mpc *mpc, - uint32_t width, - int mpcc_id); -void mpc42_program_3dlut_fl_bias_scale( - struct mpc *mpc, - uint16_t bias, - uint16_t scale, - int mpcc_id); -void mpc42_program_bit_depth( - struct mpc *mpc, - uint16_t bit_depth, - int mpcc_id); -void mpc42_populate_lut( - struct mpc *mpc, - const union mcm_lut_params params, - bool lut_bank_a, - int mpcc_id); -void mpc42_program_lut_read_write_control( - struct mpc *mpc, - const enum MCM_LUT_ID id, - bool lut_bank_a, - bool enabled, - int mpcc_id); - -bool mpc42_is_config_supported(uint32_t width); +void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst); /* RMCM */ void mpc42_program_rmcm_shaper_lut( @@ -969,12 +927,12 @@ void mpc42_program_rmcm_lut_read_write_control( int mpcc_id); void mpc42_program_lut_mode( struct mpc *mpc, - const enum MCM_LUT_XABLE xable, + bool enable, bool lut_bank_a, int mpcc_id); void mpc42_program_rmcm_3dlut_size( struct mpc *mpc, - uint32_t width, + const enum dc_cm_lut_size size, int mpcc_id); void mpc42_program_rmcm_3dlut_fast_load_bias_scale( struct mpc *mpc, @@ -986,8 +944,6 @@ void mpc42_program_rmcm_bit_depth( uint16_t bit_depth, int mpcc_id); -bool mpc42_is_rmcm_config_supported(uint32_t width); - void mpc42_set_fl_config( struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index d2ba63046a500..138081e6cc977 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -707,7 +707,7 @@ struct dcn_optc_shift { TG_REG_FIELD_LIST_DCN3_5(uint8_t) TG_REG_FIELD_LIST_DCN3_6(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) - TG_REG_FIELD_LIST_DCN42(uint8_t) + TG_REG_FIELD_LIST_DCN42(uint8_t) }; struct dcn_optc_mask { diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c index effd05b3685f5..ed66a2bbb8aeb 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c @@ -6,11 +6,13 @@ #include "dcn30/dcn30_optc.h" #include "dcn31/dcn31_optc.h" #include "dcn32/dcn32_optc.h" +#include "dcn35/dcn35_optc.h" #include "dcn401/dcn401_optc.h" #include "reg_helper.h" #include "dc.h" #include "dcn_calc_math.h" #include "dc_dmub_srv.h" +#include "dc_trace.h" #define REG(reg)\ optc1->tg_regs->reg @@ -108,6 +110,89 @@ void optc42_disable_pwa(struct timing_generator *optc) REG_UPDATE(OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_EN, 0); } +void optc42_clear_optc_underflow(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); + REG_UPDATE(OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_CLEAR, 1); +} +bool optc42_is_optc_underflow_occurred(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t underflow_occurred = 0, rsmu_underflow_occurred = 0; + + REG_GET(OPTC_INPUT_GLOBAL_CONTROL, + OPTC_UNDERFLOW_OCCURRED_STATUS, + &underflow_occurred); + + REG_GET(OPTC_RSMU_UNDERFLOW, + OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS, + &rsmu_underflow_occurred); + return (underflow_occurred == 1 || rsmu_underflow_occurred); +} +/* disable_crtc */ +bool optc42_disable_crtc(struct timing_generator *optc) +{ + optc401_disable_crtc(optc); + optc42_clear_optc_underflow(optc); + + return true; +} +static void optc42_set_timing_double_buffer(struct timing_generator *optc, bool enable) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t mode = enable ? 2 : 0; + /* actually we have 4 modes now, use as the same as previous dcn3x + * 00 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 Double buffer update occurs at any time in a frame. + * 01 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 Double buffer update occurs at OTG start of frame. + * 02 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 Double buffer occurs DP start of frame. + * 03 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 Reserved. + */ + + REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, + OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode); +} +void optc42_tg_init(struct timing_generator *optc) +{ + optc42_set_timing_double_buffer(optc, true); + optc42_clear_optc_underflow(optc); +} + +void optc42_lock_doublebuffer_enable(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t v_blank_start = 0; + uint32_t v_blank_end = 0; + uint32_t h_blank_start = 0; + uint32_t h_blank_end = 0; + + REG_GET_2(OTG_V_BLANK_START_END, + OTG_V_BLANK_START, &v_blank_start, + OTG_V_BLANK_END, &v_blank_end); + REG_GET_2(OTG_H_BLANK_START_END, + OTG_H_BLANK_START, &h_blank_start, + OTG_H_BLANK_END, &h_blank_end); + + REG_UPDATE_2(OTG_GLOBAL_CONTROL1, + MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start, + MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start); + REG_UPDATE_2(OTG_GLOBAL_CONTROL4, + DIG_UPDATE_POSITION_X, 20, + DIG_UPDATE_POSITION_Y, v_blank_start); + REG_UPDATE_3(OTG_GLOBAL_CONTROL0, + MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1, + MASTER_UPDATE_LOCK_DB_END_X, h_blank_end, + MASTER_UPDATE_LOCK_DB_EN, 1); + REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1); + + REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, + MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0, + MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100, + OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); + + TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true); +} static struct timing_generator_funcs dcn42_tg_funcs = { .validate_timing = optc1_validate_timing, @@ -117,7 +202,7 @@ static struct timing_generator_funcs dcn42_tg_funcs = { .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, .program_global_sync = optc401_program_global_sync, .enable_crtc = optc401_enable_crtc, - .disable_crtc = optc401_disable_crtc, + .disable_crtc = optc42_disable_crtc, .phantom_crtc_post_enable = optc401_phantom_crtc_post_enable, .disable_phantom_crtc = optc401_disable_phantom_otg, /* used by enable_timing_synchronization. Not need for FPGA */ @@ -138,7 +223,7 @@ static struct timing_generator_funcs dcn42_tg_funcs = { .disable_reset_trigger = optc1_disable_reset_trigger, .lock = optc3_lock, .unlock = optc1_unlock, - .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, + .lock_doublebuffer_enable = optc42_lock_doublebuffer_enable, .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, .enable_optc_clock = optc1_enable_optc_clock, .set_drr = optc401_set_drr, @@ -147,13 +232,13 @@ static struct timing_generator_funcs dcn42_tg_funcs = { .set_static_screen_control = optc1_set_static_screen_control, .program_stereo = optc1_program_stereo, .is_stereo_left_eye = optc1_is_stereo_left_eye, - .tg_init = optc3_tg_init, + .tg_init = optc42_tg_init, .is_tg_enabled = optc1_is_tg_enabled, - .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, - .clear_optc_underflow = optc1_clear_optc_underflow, + .is_optc_underflow_occurred = optc42_is_optc_underflow_occurred, + .clear_optc_underflow = optc42_clear_optc_underflow, .setup_global_swap_lock = NULL, .get_crc = optc42_get_crc, - .configure_crc = optc1_configure_crc, + .configure_crc = optc35_configure_crc, .set_dsc_config = optc3_set_dsc_config, .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, @@ -162,6 +247,7 @@ static struct timing_generator_funcs dcn42_tg_funcs = { .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear, .set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode, .get_optc_source = optc2_get_optc_source, + .wait_otg_disable = optc35_wait_otg_disable, .set_out_mux = optc401_set_out_mux, .set_drr_trigger_window = optc3_set_drr_trigger_window, .set_vtotal_change_limit = optc3_set_vtotal_change_limit, @@ -171,6 +257,8 @@ static struct timing_generator_funcs dcn42_tg_funcs = { .program_manual_trigger = optc2_program_manual_trigger, .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, + .init_odm = optc3_init_odm, + .set_long_vtotal = optc35_set_long_vtotal, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, .get_otg_double_buffer_pending = optc3_get_otg_update_pending, @@ -178,6 +266,7 @@ static struct timing_generator_funcs dcn42_tg_funcs = { .set_vupdate_keepout = optc401_set_vupdate_keepout, .wait_update_lock_status = optc401_wait_update_lock_status, .optc_read_reg_state = optc31_read_reg_state, + .read_otg_state = optc31_read_otg_state, .enable_otg_pwa = optc42_enable_pwa, .disable_otg_pwa = optc42_disable_pwa, }; @@ -194,5 +283,9 @@ void dcn42_timing_generator_init(struct optc *optc1) optc1->min_v_blank_interlace = 5; optc1->min_h_sync_width = 4; optc1->min_v_sync_width = 1; + optc1->max_frame_count = 0xFFFFFF; + + dcn35_timing_generator_set_fgcg( + optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc); } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h index 45d2187efaca0..fc7192f01b336 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h @@ -119,6 +119,10 @@ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_CLEAR, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_INT_EN, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_INT_STATUS, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ @@ -202,10 +206,15 @@ SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_EN, mask_sh),\ SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_VCOUNT_MODE, mask_sh),\ SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_LINE, mask_sh),\ - SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh) + SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh),\ + SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh) void dcn42_timing_generator_init(struct optc *optc1); void optc42_enable_pwa(struct timing_generator *optc, struct otc_pwa_frame_sync *pwa_sync_param); void optc42_disable_pwa(struct timing_generator *optc); - +void optc42_tg_init(struct timing_generator *optc); +void optc42_clear_optc_underflow(struct timing_generator *optc); +bool optc42_is_optc_underflow_occurred(struct timing_generator *optc); +bool optc42_disable_crtc(struct timing_generator *optc); +void optc42_lock_doublebuffer_enable(struct timing_generator *optc); #endif /* __DC_OPTC_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 8e41367cf2381..aef187bcf5c34 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -53,7 +53,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn42/dcn42_dccg.h" #include "dcn10/dcn10_resource.h" @@ -666,6 +666,7 @@ static const struct resource_caps res_cap_dcn42 = { .num_vmid = 16, .num_mpc_3dlut = 2, .num_dsc = 4, + .num_rmcm = 2, }; static const struct dc_plane_cap plane_cap = { @@ -755,6 +756,7 @@ static const struct dc_debug_options debug_defaults_drv = { .dcc_meta_propagation_delay_us = 10, .disable_timeout = true, .min_disp_clk_khz = 50000, + .static_screen_wait_frames = 2, .disable_z10 = false, .ignore_pg = true, .disable_stutter_for_wm_program = true, @@ -2302,14 +2304,12 @@ static bool dcn42_resource_construct( dc->dml2_options.max_segments_per_hubp = 24; dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; + dc->dml2_options.gpuvm_enable = true; + dc->dml2_options.hostvm_enable = true; /* SPL */ dc->caps.scl_caps.sharpener_support = true; - /* init DC limited DML2 options */ - memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options)); - dc->dml2_dc_power_options.use_clock_dc_limits = true; - return true; create_fail: diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c index 3190c76eb4820..1b397fa7e05c9 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c @@ -102,6 +102,9 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( } } else { dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; + #ifdef ENABLE_WCK + dml_clk_table->wck_ratio.clk_values_khz[i] = dc_clk_table->entries[i].wck_ratio; + #endif } } else { dml_clk_table->uclk.clk_values_khz[i] = 0; diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c index 87ac567390305..fd9c24b5df535 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -3,7 +3,7 @@ // Copyright 2025 Advanced Micro Devices, Inc. #include "dcn42_soc_and_ip_translator.h" -#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h" +#include "../dcn401/dcn401_soc_and_ip_translator.h" #include "bounding_boxes/dcn42_soc_bb.h" /* soc_and_ip_translator component used to get up-to-date values for bounding box. @@ -11,10 +11,12 @@ * This component provides an interface to get DCN-specific bounding box values. */ -static void get_default_soc_bb(struct dml2_soc_bb *soc_bb) +static void get_default_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc) { - memcpy(soc_bb, &dml2_socbb_dcn42, sizeof(struct dml2_soc_bb)); - memcpy(&soc_bb->qos_parameters, &dml_dcn42_variant_a_soc_qos_params, sizeof(struct dml2_soc_qos_parameters)); + { + memcpy(soc_bb, &dml2_socbb_dcn42, sizeof(struct dml2_soc_bb)); + memcpy(&soc_bb->qos_parameters, &dml_dcn42_variant_a_soc_qos_params, sizeof(struct dml2_soc_qos_parameters)); + } } /* @@ -162,7 +164,7 @@ static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) { //get default soc_bb with static values - get_default_soc_bb(soc_bb); + get_default_soc_bb(soc_bb, dc); //update soc_bb values with more accurate values apply_soc_bb_updates(soc_bb, dc, config); } diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f67a0ffb9335a..0b04f985b15ef 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -909,7 +909,8 @@ union dmub_fw_meta_feature_bits { struct { uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ - uint32_t reserved : 30; + uint32_t inbox0_lock_support: 1; /**< 1 supports inbox0 lock mechanism */ + uint32_t reserved : 29; } bits; /**< status bits */ uint32_t all; /**< 32-bit access to status bits */ }; @@ -1535,14 +1536,12 @@ enum dmub_gpint_command { * 1 - Enable ips measurement */ DMUB_GPINT__IPS_RESIDENCY = 121, - /** * DESC: Enable measurements for various task duration * ARGS: 0 - Disable measurement * 1 - Enable measurement */ DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, - /** * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency @@ -1552,21 +1551,18 @@ enum dmub_gpint_command { * RETURN: Total residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, - /** * DESC: Gets IPS1 histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, - /** * DESC: Gets IPS2 histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, - /** * DESC: Gets IPS residency * ARGS: 0 - Return IPS1 residency @@ -1576,21 +1572,18 @@ enum dmub_gpint_command { * RETURN: Total residency in milli-percent. */ DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, - /** * DESC: Gets IPS1_RCG histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, - /** * DESC: Gets IPS1_ONO2_ON histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, - /** * DESC: Gets IPS entry counter during residency measurement * ARGS: 0 - Return IPS1 entry counts @@ -1600,7 +1593,6 @@ enum dmub_gpint_command { * RETURN: Entry counter for selected IPS mode */ DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, - /** * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency @@ -1610,7 +1602,6 @@ enum dmub_gpint_command { * RETURN: Total inactive residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, - /** * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency @@ -1620,7 +1611,6 @@ enum dmub_gpint_command { * RETURN: Total inactive residency in microseconds - upper 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, - /** * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency @@ -1679,7 +1669,7 @@ union dmub_inbox0_cmd_lock_hw { uint32_t lock: 1; /**< Lock */ uint32_t should_release: 1; /**< Release */ - uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ + uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ } bits; uint32_t all; }; @@ -2614,9 +2604,9 @@ struct dmub_fams2_stream_static_state { uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline union { struct { - uint8_t is_drr: 1; // stream is DRR enabled - uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal - uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank + uint8_t is_drr : 1; // stream is DRR enabled + uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal + uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank } bits; uint8_t all; } config; @@ -4660,6 +4650,18 @@ struct dmub_rb_cmd_replay_enable_data { * This does not support HDMI/DP2 for now. */ uint8_t phy_rate; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; + /** + * @pad: Align structure to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -5273,8 +5275,8 @@ enum dmub_cmd_lsdma_type { */ DMUB_CMD__LSDMA_LINEAR_COPY = 1, /** - * LSDMA copies data from source to destination linearly in sub window - */ + * LSDMA copies data from source to destination linearly in sub window + */ DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, /** * Send the tiled-to-tiled copy command diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h index 825201f4e113f..52fbf2dc18995 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h @@ -9010,6 +9010,8 @@ // base address: 0x0 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_RSMU_UNDERFLOW 0x1acb +#define regODM0_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 #define regODM0_OPTC_UNDERFLOW_THRESHOLD 0x1acc #define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 #define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acd diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h index 4ed96244f61b2..01fb530933698 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h @@ -33583,6 +33583,15 @@ #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_RSMU_UNDERFLOW +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L //ODM0_OPTC_UNDERFLOW_THRESHOLD #define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 #define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL From 92029681212a02dc66568dfe86162552cc57c7f6 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 27 Feb 2026 16:35:12 -0500 Subject: [PATCH 1809/2070] drm/amd/display: [FW Promotion] Release 0.1.50.0 [WHAT] Introduce DMUB BOOT_TIME_CRC_INIT command. Acked-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 0b04f985b15ef..e11e32afac6be 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1892,6 +1892,11 @@ enum dmub_cmd_type { */ DMUB_CMD__IHC = 95, + /** + * Command type use for boot time crc commands. + */ + DMUB_CMD__BOOT_TIME_CRC = 96, + /** * Command type use for VBIOS shared commands. */ @@ -6838,6 +6843,29 @@ struct dmub_rb_cmd_pr_general_cmd { struct dmub_cmd_pr_general_cmd_data data; }; +/** + * Command type of a DMUB_CMD__BOOT_TIME_CRC command + */ +enum dmub_cmd_boot_time_crc_type { + DMUB_CMD__BOOT_TIME_CRC_INIT_MEM = 0 +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__BOOT_TIME_CRC_INIT command. + */ +struct dmub_cmd_boot_time_crc_init_data { + union dmub_addr buffer_addr; + uint32_t buffer_size; +}; + +/** + * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. + */ +struct dmub_rb_cmd_boot_time_crc_init { + struct dmub_cmd_header header; + struct dmub_cmd_boot_time_crc_init_data data; +}; + /** * union dmub_rb_cmd - DMUB inbox command. */ @@ -7199,6 +7227,10 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__IHC command. */ struct dmub_rb_cmd_ihc ihc; + /** + * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. + */ + struct dmub_rb_cmd_boot_time_crc_init boot_time_crc_init; }; /** From df1574e606ce3f24d13537d033214fe8d68a1842 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 7 Nov 2025 11:59:05 +0800 Subject: [PATCH 1810/2070] drm/amdgpu/discovery: support new discovery binary header Support for new IP discovery binary header version 2. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 128 +++++++++++++----- drivers/gpu/drm/amd/include/discovery.h | 13 ++ 2 files changed, 104 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index bccdb2c788520..0562faf40bc41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -431,14 +431,12 @@ static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) } static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, - struct binary_header *bhdr) + struct table_info *info) { uint8_t *discovery_bin = adev->discovery.bin; - struct table_info *info; uint16_t checksum; uint16_t offset; - info = &bhdr->table_list[NPS_INFO]; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -491,6 +489,30 @@ static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) } } +static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, + struct table_info **info, + uint16_t table_id) +{ + struct binary_header *bhdr = + (struct binary_header *)adev->discovery.bin; + struct binary_header_v2 *bhdrv2; + + switch (bhdr->version_major) { + case 2: + bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; + *info = &bhdrv2->table_list[table_id]; + break; + case 1: + *info = &bhdr->table_list[table_id]; + break; + default: + dev_err(adev->dev, "Invalid ip discovery table version\n"); + return -EINVAL; + } + + return 0; +} + static int amdgpu_discovery_init(struct amdgpu_device *adev) { struct table_info *info; @@ -547,7 +569,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } - info = &bhdr->table_list[IP_DISCOVERY]; + r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); + if (r) + goto out; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -569,7 +593,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) } } - info = &bhdr->table_list[GC]; + r = amdgpu_discovery_get_table_info(adev, &info, GC); + if (r) + goto out; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -592,7 +618,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) } } - info = &bhdr->table_list[HARVEST_INFO]; + r = amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO); + if (r) + goto out; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -615,7 +643,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) } } - info = &bhdr->table_list[VCN_INFO]; + r = amdgpu_discovery_get_table_info(adev, &info, VCN_INFO); + if (r) + goto out; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -638,7 +668,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) } } - info = &bhdr->table_list[MALL_INFO]; + r = amdgpu_discovery_get_table_info(adev, &info, MALL_INFO); + if (r) + goto out; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -770,14 +802,15 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, uint32_t *umc_harvest_count) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; struct harvest_table *harvest_info; u16 offset; int i; uint32_t umc_harvest_config = 0; - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) + return; + offset = le16_to_cpu(info->offset); if (!offset) { dev_err(adev->dev, "invalid harvest table offset\n"); @@ -1241,7 +1274,7 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) { struct ip_discovery_top *ip_top = adev->discovery.ip_top; uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; struct ip_discovery_header *ihdr; struct die_header *dhdr; struct kset *die_kset = &ip_top->die_kset; @@ -1249,10 +1282,12 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) size_t ip_offset; int ii, res; - bhdr = (struct binary_header *)discovery_bin; + res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); + if (res) + return res; ihdr = (struct ip_discovery_header *)(discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + le16_to_cpu(info->offset)); num_dies = le16_to_cpu(ihdr->num_dies); DRM_DEBUG("number of dies: %d\n", num_dies); @@ -1443,7 +1478,7 @@ void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) { uint8_t num_base_address, subrev, variant; - struct binary_header *bhdr; + struct table_info *info; struct ip_discovery_header *ihdr; struct die_header *dhdr; uint8_t *discovery_bin; @@ -1468,10 +1503,12 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) adev->sdma.sdma_mask = 0; adev->vcn.inst_mask = 0; adev->jpeg.inst_mask = 0; - bhdr = (struct binary_header *)discovery_bin; + r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); + if (r) + return r; ihdr = (struct ip_discovery_header *)(discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + le16_to_cpu(info->offset)); num_dies = le16_to_cpu(ihdr->num_dies); DRM_DEBUG("number of dies: %d\n", num_dies); @@ -1644,14 +1681,15 @@ static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; struct ip_discovery_header *ihdr; - struct binary_header *bhdr; + struct table_info *info; int vcn_harvest_count = 0; int umc_harvest_count = 0; - uint16_t offset, ihdr_ver; + uint16_t ihdr_ver; - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); - ihdr = (struct ip_discovery_header *)(discovery_bin + offset); + if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) + return; + ihdr = (struct ip_discovery_header *)(discovery_bin + + le16_to_cpu(info->offset)); ihdr_ver = le16_to_cpu(ihdr->version); /* * Harvest table does not fit Navi1x and legacy GPUs, @@ -1699,7 +1737,7 @@ union gc_info { static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; union gc_info *gc_info; u16 offset; @@ -1708,8 +1746,9 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[GC].offset); + if (amdgpu_discovery_get_table_info(adev, &info, GC)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return 0; @@ -1808,7 +1847,7 @@ union mall_info { static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; union mall_info *mall_info; u32 u, mall_size_per_umc, m_s_present, half_use; u64 mall_size; @@ -1819,8 +1858,9 @@ static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return 0; @@ -1865,7 +1905,7 @@ union vcn_info { static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; union vcn_info *vcn_info; u16 offset; int v; @@ -1885,8 +1925,9 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return 0; @@ -1923,14 +1964,26 @@ static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, uint64_t vram_size, pos, offset; struct nps_info_header *nhdr; struct binary_header bhdr; + struct binary_header_v2 bhdrv2; uint16_t checksum; vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; pos = vram_size - DISCOVERY_TMR_OFFSET; amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); - offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); - checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); + switch (bhdr.version_major) { + case 2: + amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); + offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); + checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); + break; + case 1: + offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); + checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); + break; + default: + return -EINVAL; + } amdgpu_device_vram_access(adev, (pos + offset), nps_data, sizeof(*nps_data), false); @@ -1953,7 +2006,7 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, { uint8_t *discovery_bin = adev->discovery.bin; struct amdgpu_gmc_memrange *mem_ranges; - struct binary_header *bhdr; + struct table_info *info; union nps_info *nps_info; union nps_info nps_data; u16 offset; @@ -1974,14 +2027,15 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return -ENOENT; /* If verification fails, return as if NPS table doesn't exist */ - if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) + if (amdgpu_discovery_verify_npsinfo(adev, info)) return -ENOENT; nps_info = (union nps_info *)(discovery_bin + offset); diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index 710e328fad48f..76c9f951bc1c8 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -64,6 +64,19 @@ typedef struct binary_header table_info table_list[TOTAL_TABLES]; } binary_header; +typedef struct binary_header_v2 +{ + /* psp structure should go at the top of this structure */ + uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ + uint16_t version_major; /* 0x02 */ + uint16_t version_minor; + uint16_t binary_checksum; /* Byte sum of the binary after this field */ + uint16_t binary_size; /* Binary Size*/ + uint16_t num_tables; + uint16_t padding; + table_info table_list[] __counted_by(num_tables); +} binary_header_v2; + typedef struct die_info { uint16_t die_id; From f06c9e8f62098bde337f8d485dd7ead05f4af6da Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 27 Feb 2026 17:40:05 -0500 Subject: [PATCH 1811/2070] drm/amd/display: Promote DC to 3.2.373 This version brings along the following updates: - [FW Promotion] Release 0.1.50.0 - Sync DCN42 with DC 3.2.373 - Add DML support for dcn42 - Enable dcn42 DC clk_mgr - Clean up unused code - Add back missing memory type in array - Fix compile warnings in dml2_0 - Check for S0i3 to be done before DCCG init on DCN21 - Add documentation and cleanup DMUB HW lock manager - Add new types to replay config - Fix HWSS v3 fast path determination - Add missing DCCG register entries for DCN20-DCN316 - Add ESD detection for replay recovery - Update underflow detection - Add COLOR_ENCODING/COLOR_RANGE to overlay planes - Add NV12/P010 formats to primary plane - Set chroma taps to 1 if luma taps are 1 - Add min clock init for DML21 mode programming - Return early from vesa replay enable function - Clean up NULL pointer warnings in dml2 Acked-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9379b6ebcac32..8cfa2da5e7da0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.372" +#define DC_VER "3.2.373" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 9d9c0be87f42e35acce79a2a5cddc7f90b24c99a Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Thu, 5 Mar 2026 14:34:56 -0500 Subject: [PATCH 1812/2070] drm/amdgpu/discovery: use common function to check discovery table Use an common function to check the validation of discovery table. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 206 +++++++----------- 1 file changed, 84 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 0562faf40bc41..86f1de1f4aed8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -513,15 +513,95 @@ static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, return 0; } -static int amdgpu_discovery_init(struct amdgpu_device *adev) +static int amdgpu_discovery_table_check(struct amdgpu_device *adev, + uint8_t *discovery_bin, + uint16_t table_id) { + int r, act_val, exp_val, table_size; + uint16_t offset, checksum; struct table_info *info; + bool check_table = true; + char *table_name; + + r = amdgpu_discovery_get_table_info(adev, &info, table_id); + if (r) + return r; + offset = le16_to_cpu(info->offset); + checksum = le16_to_cpu(info->checksum); + + switch (table_id) { + case IP_DISCOVERY: + struct ip_discovery_header *ihdr = + (struct ip_discovery_header *)(discovery_bin + offset); + act_val = le32_to_cpu(ihdr->signature); + exp_val = DISCOVERY_TABLE_SIGNATURE; + table_size = le16_to_cpu(ihdr->size); + table_name = "data table"; + break; + case GC: + struct gpu_info_header *ghdr = + (struct gpu_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(ghdr->table_id); + exp_val = GC_TABLE_ID; + table_size = le16_to_cpu(ghdr->size); + table_name = "gc table"; + break; + case HARVEST_INFO: + struct harvest_info_header *hhdr = + (struct harvest_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(hhdr->signature); + exp_val = HARVEST_TABLE_SIGNATURE; + table_size = sizeof(struct harvest_table); + table_name = "harvest table"; + break; + case VCN_INFO: + struct vcn_info_header *vhdr = + (struct vcn_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(vhdr->table_id); + exp_val = VCN_INFO_TABLE_ID; + table_size = le32_to_cpu(vhdr->size_bytes); + table_name = "vcn table"; + break; + case MALL_INFO: + struct mall_info_header *mhdr = + (struct mall_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(mhdr->table_id); + exp_val = MALL_INFO_TABLE_ID; + table_size = le32_to_cpu(mhdr->size_bytes); + table_name = "mall table"; + check_table = false; + break; + default: + dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); + check_table = false; + break; + } + + if (check_table && offset) { + if (act_val != exp_val) { + dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); + return -EINVAL; + } + + if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, + table_size, checksum)) { + dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); + return -EINVAL; + } + } + + return 0; +} + +static int amdgpu_discovery_init(struct amdgpu_device *adev) +{ struct binary_header *bhdr; uint8_t *discovery_bin; const char *fw_name; uint16_t offset; uint16_t size; uint16_t checksum; + uint16_t table_id; int r; adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); @@ -569,128 +649,10 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } - r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); - if (r) - goto out; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct ip_discovery_header *ihdr = - (struct ip_discovery_header *)(discovery_bin + offset); - if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { - dev_err(adev->dev, "invalid ip discovery data table signature\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, - le16_to_cpu(ihdr->size), - checksum)) { - dev_err(adev->dev, "invalid ip discovery data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - r = amdgpu_discovery_get_table_info(adev, &info, GC); - if (r) - goto out; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct gpu_info_header *ghdr = - (struct gpu_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { - dev_err(adev->dev, "invalid ip discovery gc table id\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, - le32_to_cpu(ghdr->size), - checksum)) { - dev_err(adev->dev, "invalid gc data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - r = amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO); - if (r) - goto out; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct harvest_info_header *hhdr = - (struct harvest_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { - dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(adev, - discovery_bin + offset, - sizeof(struct harvest_table), checksum)) { - dev_err(adev->dev, "invalid harvest data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - r = amdgpu_discovery_get_table_info(adev, &info, VCN_INFO); - if (r) - goto out; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct vcn_info_header *vhdr = - (struct vcn_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { - dev_err(adev->dev, "invalid ip discovery vcn table id\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(adev, - discovery_bin + offset, - le32_to_cpu(vhdr->size_bytes), checksum)) { - dev_err(adev->dev, "invalid vcn data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - r = amdgpu_discovery_get_table_info(adev, &info, MALL_INFO); - if (r) - goto out; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (0 && offset) { - struct mall_info_header *mhdr = - (struct mall_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { - dev_err(adev->dev, "invalid ip discovery mall table id\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(adev, - discovery_bin + offset, - le32_to_cpu(mhdr->size_bytes), checksum)) { - dev_err(adev->dev, "invalid mall data table checksum\n"); - r = -EINVAL; + for (table_id = 0; table_id <= MALL_INFO; table_id++) { + r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); + if (r) goto out; - } } return 0; From bce1e285bca61edb514a9fa20bd2ae11a3c16339 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 9 Dec 2025 15:13:23 -0500 Subject: [PATCH 1813/2070] drm/amdkfd: Unreserve bo if queue update failed Error handling path should unreserve bo then return failed. Fixes: 305cd109b761 ("drm/amdkfd: Validate user queue update") Signed-off-by: Philip Yang Reviewed-by: Alex Sierra Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 369f9de4b59df..f06d10a58300a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -597,6 +597,7 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm, p->queue_size)) { pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", p->queue_address, p->queue_size); + amdgpu_bo_unreserve(vm->root.bo); return -EFAULT; } From 0609b56dd2a5c361400508afea219210855f3ce3 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 11 Mar 2026 11:10:41 +0800 Subject: [PATCH 1814/2070] drm/amdkcl: add braces to case statements to fix build on gnu89 It's caused by the commit: "drm/amdgpu/discovery: use common function to check discovery table" Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 86f1de1f4aed8..1ec2b8327b393 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -530,7 +530,7 @@ static int amdgpu_discovery_table_check(struct amdgpu_device *adev, checksum = le16_to_cpu(info->checksum); switch (table_id) { - case IP_DISCOVERY: + case IP_DISCOVERY: { struct ip_discovery_header *ihdr = (struct ip_discovery_header *)(discovery_bin + offset); act_val = le32_to_cpu(ihdr->signature); @@ -538,7 +538,8 @@ static int amdgpu_discovery_table_check(struct amdgpu_device *adev, table_size = le16_to_cpu(ihdr->size); table_name = "data table"; break; - case GC: + } + case GC: { struct gpu_info_header *ghdr = (struct gpu_info_header *)(discovery_bin + offset); act_val = le32_to_cpu(ghdr->table_id); @@ -546,7 +547,8 @@ static int amdgpu_discovery_table_check(struct amdgpu_device *adev, table_size = le16_to_cpu(ghdr->size); table_name = "gc table"; break; - case HARVEST_INFO: + } + case HARVEST_INFO: { struct harvest_info_header *hhdr = (struct harvest_info_header *)(discovery_bin + offset); act_val = le32_to_cpu(hhdr->signature); @@ -554,7 +556,8 @@ static int amdgpu_discovery_table_check(struct amdgpu_device *adev, table_size = sizeof(struct harvest_table); table_name = "harvest table"; break; - case VCN_INFO: + } + case VCN_INFO: { struct vcn_info_header *vhdr = (struct vcn_info_header *)(discovery_bin + offset); act_val = le32_to_cpu(vhdr->table_id); @@ -562,7 +565,8 @@ static int amdgpu_discovery_table_check(struct amdgpu_device *adev, table_size = le32_to_cpu(vhdr->size_bytes); table_name = "vcn table"; break; - case MALL_INFO: + } + case MALL_INFO: { struct mall_info_header *mhdr = (struct mall_info_header *)(discovery_bin + offset); act_val = le32_to_cpu(mhdr->table_id); @@ -571,6 +575,7 @@ static int amdgpu_discovery_table_check(struct amdgpu_device *adev, table_name = "mall table"; check_table = false; break; + } default: dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); check_table = false; From 9c851855e0c437a39395ee188a9d5cd1ee41741f Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 10 Feb 2026 04:08:54 +0800 Subject: [PATCH 1815/2070] drm/amdgpu: New interface to get IP discovery binary v3 Implement a driver path to read the IP discovery binary offset and size from DRIVER_SCRATCH registers BIOS signals usage by setting a feature flag that instructs the driver to use this method. Otherwise, fallback to legacy approach. v2: Simplify discovery offset/size retrieval in get_tmr_info v3: Update get_tmr_info to cover discovery offset and size retrieval for both bare-metal and sriov Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 165 ++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 1 + 2 files changed, 93 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 1ec2b8327b393..8fc5fcda415bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -132,6 +132,7 @@ MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); +/* Note: These registers are consistent across all the SOCs */ #define mmIP_DISCOVERY_VERSION 0x16A00 #define mmRCC_CONFIG_MEMSIZE 0xde3 #define mmMP0_SMN_C2PMSG_33 0x16061 @@ -139,6 +140,10 @@ MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); #define mmMM_INDEX_HI 0x6 #define mmMM_DATA 0x1 +#define mmDRIVER_SCRATCH_0 0x94 +#define mmDRIVER_SCRATCH_1 0x95 +#define mmDRIVER_SCRATCH_2 0x96 + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -253,39 +258,12 @@ static int hw_id_map[MAX_HWIP] = { [ATU_HWIP] = ATU_HWID, }; -static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) +static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, + bool *is_tmr_in_sysmem) { - u64 tmr_offset, tmr_size, pos; - void *discv_regn; - int ret; - - ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); - if (ret) - return ret; - - pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; - - /* This region is read-only and reserved from system use */ - discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); - if (discv_regn) { - memcpy(binary, discv_regn, adev->discovery.size); - memunmap(discv_regn); - return 0; - } - - return -ENOENT; -} - -#define IP_DISCOVERY_V2 2 -#define IP_DISCOVERY_V4 4 - -static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, - uint8_t *binary) -{ - bool sz_valid = true; - uint64_t vram_size; - int i, ret = 0; - u32 msg; + u64 vram_size, tmr_offset, tmr_size; + u32 msg, tmr_offset_lo, tmr_offset_hi; + int i, ret; if (!amdgpu_sriov_vf(adev)) { /* It can take up to two second for IFWI init to complete on some dGPUs, @@ -305,51 +283,93 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, } vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); - if (!vram_size || vram_size == U32_MAX) - sz_valid = false; + if (vram_size == U32_MAX) + return -ENXIO; + else if (!vram_size) + *is_tmr_in_sysmem = true; else - vram_size <<= 20; - - /* - * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, - * then it is not required to be reserved. - */ - if (sz_valid) { - if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { - /* For SRIOV VFs with dynamic critical region enabled, - * we will get the IPD binary via below call. - * If dynamic critical is disabled, fall through to normal seq. - */ - if (amdgpu_virt_get_dynamic_data_info(adev, - AMD_SRIOV_MSG_IPD_TABLE_ID, binary, - &adev->discovery.size)) { - dev_err(adev->dev, - "failed to read discovery info from dynamic critical region."); - ret = -EINVAL; - goto exit; - } - } else { - uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; + *is_tmr_in_sysmem = false; - amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, - adev->discovery.size, false); - adev->discovery.reserve_tmr = true; + /* init the default tmr size and offset */ + adev->discovery.size = DISCOVERY_TMR_SIZE; + if (vram_size) + adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; + + if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { + adev->discovery.offset = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; + adev->discovery.size = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; + if (!adev->discovery.offset || !adev->discovery.size) + return -EINVAL; + } else { + tmr_size = RREG32(mmDRIVER_SCRATCH_2); + if (tmr_size) { + /* It's preferred to transition to PSP mailbox reg interface + * for both bare-metal and passthrough if available */ + adev->discovery.size = (u32)tmr_size; + tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); + tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); + adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | + le32_to_cpu(tmr_offset_lo)); + } else if (!vram_size) { + /* fall back to apci approach to query tmr offset if vram_size is 0 */ + ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); + if (ret) + return ret; + adev->discovery.size = (u32)tmr_size; + adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; } + } + + adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); + if (!adev->discovery.bin) + return -ENOMEM; + adev->discovery.debugfs_blob.data = adev->discovery.bin; + adev->discovery.debugfs_blob.size = adev->discovery.size; + + return 0; +} + +static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) +{ + void *discv_regn; + + /* This region is read-only and reserved from system use */ + discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); + if (discv_regn) { + memcpy(binary, discv_regn, adev->discovery.size); + memunmap(discv_regn); + return 0; + } + + return -ENOENT; +} + +#define IP_DISCOVERY_V2 2 +#define IP_DISCOVERY_V4 4 + +static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, + uint8_t *binary, + bool is_tmr_in_sysmem) +{ + int ret = 0; + + if (!is_tmr_in_sysmem) { + amdgpu_device_vram_access(adev, adev->discovery.offset, + (uint32_t *)binary, + adev->discovery.size, false); + adev->discovery.reserve_tmr = true; } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } - if (ret) - dev_err(adev->dev, - "failed to read discovery info from memory, vram size read: %llx", - vram_size); -exit: return ret; } static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, - uint8_t *binary, - const char *fw_name) + uint8_t *binary, + const char *fw_name) { const struct firmware *fw; int r; @@ -607,14 +627,12 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) uint16_t size; uint16_t checksum; uint16_t table_id; + bool is_tmr_in_sysmem; int r; - adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); - if (!adev->discovery.bin) - return -ENOMEM; - adev->discovery.size = DISCOVERY_TMR_SIZE; - adev->discovery.debugfs_blob.data = adev->discovery.bin; - adev->discovery.debugfs_blob.size = adev->discovery.size; + r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); + if (r) + return r; discovery_bin = adev->discovery.bin; /* Read from file if it is the preferred option */ @@ -627,7 +645,8 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } else { drm_dbg(&adev->ddev, "use ip discovery information from memory"); - r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); + r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, + is_tmr_in_sysmem); if (r) goto out; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index c8242992c9122..a7aeb47887a34 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -35,6 +35,7 @@ struct drm_printer; struct amdgpu_discovery_info { struct debugfs_blob_wrapper debugfs_blob; struct ip_discovery_top *ip_top; + uint64_t offset; uint32_t size; uint8_t *bin; bool reserve_tmr; From 948cc2462fc5a0ae51a3e7841604604613d58510 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 2 Feb 2026 03:32:52 +0800 Subject: [PATCH 1816/2070] drm/amdgpu: Use memcpy to update IPD table for sriov guest On some hardware configuration, sriov guests cannot access mm_index and mm_data. Update the IPD table via memcpy in these cases Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 13 +++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 3 ++- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 8fc5fcda415bf..f62c8684da26f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -356,10 +356,15 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, int ret = 0; if (!is_tmr_in_sysmem) { - amdgpu_device_vram_access(adev, adev->discovery.offset, - (uint32_t *)binary, - adev->discovery.size, false); - adev->discovery.reserve_tmr = true; + if (amdgpu_sriov_vf(adev) && + amdgpu_sriov_xgmi_connected_to_cpu(adev)) { + ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); + } else { + amdgpu_device_vram_access(adev, adev->discovery.offset, + (uint32_t *)binary, + adev->discovery.size, false); + adev->discovery.reserve_tmr = true; + } } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 886fbce0bfd1d..9da0c6e9b8695 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -162,6 +162,7 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), AMDGIM_FEATURE_RAS_CPER = (1 << 11), AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), + AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -412,6 +413,9 @@ struct amdgpu_video_codec_info; #define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK) +#define amdgpu_sriov_xgmi_connected_to_cpu(adev) \ +((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU) + static inline bool is_virtual_machine(void) { #if defined(CONFIG_X86) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index a841f342a3ebb..847cfd1fd0046 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -161,7 +161,8 @@ union amd_sriov_msg_feature_flags { uint32_t ras_telemetry : 1; uint32_t ras_cper : 1; uint32_t xgmi_ta_ext_peer_link : 1; - uint32_t reserved : 19; + uint32_t xgmi_connected_to_cpu : 1; + uint32_t reserved : 18; } flags; uint32_t all; }; From b11c761a65134d3c3add4ff08b5a6efd0987e39b Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Wed, 21 Jan 2026 14:56:54 +0800 Subject: [PATCH 1817/2070] drm/amdgpu: Add lsdma v7_1_0 ip headers Add header files for lsdma v7_1_0 register offsets and shift masks Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- .../asic_reg/lsdma/lsdma_7_1_0_offset.h | 44 ++++++++ .../asic_reg/lsdma/lsdma_7_1_0_sh_mask.h | 105 ++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h new file mode 100644 index 0000000000000..fa4e42a3ae9fc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h @@ -0,0 +1,44 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _lsdma_7_1_0_OFFSET_HEADER +#define _lsdma_7_1_0_OFFSET_HEADER + +#define regLSDMA_PIO_SRC_ADDR_LO 0x0080 +#define regLSDMA_PIO_SRC_ADDR_LO_BASE_IDX 0 +#define regLSDMA_PIO_SRC_ADDR_HI 0x0081 +#define regLSDMA_PIO_SRC_ADDR_HI_BASE_IDX 0 +#define regLSDMA_PIO_DST_ADDR_LO 0x0082 +#define regLSDMA_PIO_DST_ADDR_LO_BASE_IDX 0 +#define regLSDMA_PIO_DST_ADDR_HI 0x0083 +#define regLSDMA_PIO_DST_ADDR_HI_BASE_IDX 0 +#define regLSDMA_PIO_COMMAND 0x0084 +#define regLSDMA_PIO_COMMAND_BASE_IDX 0 +#define regLSDMA_PIO_CONSTFILL_DATA 0x0085 +#define regLSDMA_PIO_CONSTFILL_DATA_BASE_IDX 0 +#define regLSDMA_PIO_CONTROL 0x0086 +#define regLSDMA_PIO_CONTROL_BASE_IDX 0 + +#define regLSDMA_PIO_STATUS 0x008a +#define regLSDMA_PIO_STATUS_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h new file mode 100644 index 0000000000000..cf83dacf4acf5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h @@ -0,0 +1,105 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _lsdma_7_1_0_SH_MASK_HEADER +#define _lsdma_7_1_0_SH_MASK_HEADER + + +// addressBlock: lsdma0_lsdma0dec +//LSDMA_PIO_STATUS +#define LSDMA_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 +#define LSDMA_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 +#define LSDMA_PIO_STATUS__ERROR_INVALID_ADDR__SHIFT 0xb +#define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0xc +#define LSDMA_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xd +#define LSDMA_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xe +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 +#define LSDMA_PIO_STATUS__ERROR_REQ_DROP__SHIFT 0x13 +#define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c +#define LSDMA_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d +#define LSDMA_PIO_STATUS__PIO_IDLE__SHIFT 0x1f +#define LSDMA_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L +#define LSDMA_PIO_STATUS__CMD_PROCESSING_MASK 0x000003F8L +#define LSDMA_PIO_STATUS__ERROR_INVALID_ADDR_MASK 0x00000800L +#define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00001000L +#define LSDMA_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00002000L +#define LSDMA_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00004000L +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L +#define LSDMA_PIO_STATUS__ERROR_REQ_DROP_MASK 0x00080000L +#define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L +#define LSDMA_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L +#define LSDMA_PIO_STATUS__PIO_IDLE_MASK 0x80000000L +//LSDMA_PIO_SRC_ADDR_LO +#define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO__SHIFT 0x0 +#define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO_MASK 0xFFFFFFFFL +//LSDMA_PIO_SRC_ADDR_HI +#define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xFFFFFFFFL +//LSDMA_PIO_DST_ADDR_LO +#define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO__SHIFT 0x0 +#define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO_MASK 0xFFFFFFFFL +//LSDMA_PIO_DST_ADDR_HI +#define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK 0xFFFFFFFFL +//LSDMA_PIO_CONTROL +#define LSDMA_PIO_CONTROL__VMID__SHIFT 0x0 +#define LSDMA_PIO_CONTROL__DST_GPA__SHIFT 0x4 +#define LSDMA_PIO_CONTROL__DST_SYS__SHIFT 0x5 +#define LSDMA_PIO_CONTROL__DST_GCC__SHIFT 0x6 +#define LSDMA_PIO_CONTROL__DST_SNOOP__SHIFT 0x7 +#define LSDMA_PIO_CONTROL__DST_REUSE_HINT__SHIFT 0x8 +#define LSDMA_PIO_CONTROL__DST_COMP_EN__SHIFT 0xa +#define LSDMA_PIO_CONTROL__SRC_GPA__SHIFT 0x14 +#define LSDMA_PIO_CONTROL__SRC_SYS__SHIFT 0x15 +#define LSDMA_PIO_CONTROL__SRC_SNOOP__SHIFT 0x17 +#define LSDMA_PIO_CONTROL__SRC_REUSE_HINT__SHIFT 0x18 +#define LSDMA_PIO_CONTROL__SRC_COMP_EN__SHIFT 0x1a +#define LSDMA_PIO_CONTROL__VMID_MASK 0x0000000FL +#define LSDMA_PIO_CONTROL__DST_GPA_MASK 0x00000010L +#define LSDMA_PIO_CONTROL__DST_SYS_MASK 0x00000020L +#define LSDMA_PIO_CONTROL__DST_GCC_MASK 0x00000040L +#define LSDMA_PIO_CONTROL__DST_SNOOP_MASK 0x00000080L +#define LSDMA_PIO_CONTROL__DST_REUSE_HINT_MASK 0x00000300L +#define LSDMA_PIO_CONTROL__DST_COMP_EN_MASK 0x00000400L +#define LSDMA_PIO_CONTROL__SRC_GPA_MASK 0x00100000L +#define LSDMA_PIO_CONTROL__SRC_SYS_MASK 0x00200000L +#define LSDMA_PIO_CONTROL__SRC_SNOOP_MASK 0x00800000L +#define LSDMA_PIO_CONTROL__SRC_REUSE_HINT_MASK 0x03000000L +#define LSDMA_PIO_CONTROL__SRC_COMP_EN_MASK 0x04000000L +//LSDMA_PIO_COMMAND +#define LSDMA_PIO_COMMAND__COUNT__SHIFT 0x0 +#define LSDMA_PIO_COMMAND__RAW_WAIT__SHIFT 0x1e +#define LSDMA_PIO_COMMAND__CONSTANT_FILL__SHIFT 0x1f +#define LSDMA_PIO_COMMAND__COUNT_MASK 0x03FFFFFFL +#define LSDMA_PIO_COMMAND__RAW_WAIT_MASK 0x40000000L +#define LSDMA_PIO_COMMAND__CONSTANT_FILL_MASK 0x80000000L +//LSDMA_PIO_CONSTFILL_DATA +#define LSDMA_PIO_CONSTFILL_DATA__DATA__SHIFT 0x0 +#define LSDMA_PIO_CONSTFILL_DATA__DATA_MASK 0xFFFFFFFFL + +#endif From 426c4a591d90277c0a6fb44cc6e2255085f34650 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Wed, 21 Jan 2026 15:03:25 +0800 Subject: [PATCH 1818/2070] drm/amdgpu: add support for lsdma v7_1 Add support for LSDMA v7_1_0. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 + drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c | 99 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h | 31 ++++++ 4 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c create mode 100644 drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 9d24cf1e77f48..7d01841f803be 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -86,7 +86,7 @@ amdgpu-y += \ nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \ sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \ nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \ - cyan_skillfish_reg_init.o soc_v1_0.o + cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o # add DF block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index f62c8684da26f..e97f57ea190f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -87,6 +87,7 @@ #include "sdma_v7_1.h" #include "lsdma_v6_0.h" #include "lsdma_v7_0.h" +#include "lsdma_v7_1.h" #include "vcn_v2_0.h" #include "jpeg_v2_0.h" #include "vcn_v3_0.h" @@ -3332,6 +3333,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(7, 0, 1): adev->lsdma.funcs = &lsdma_v7_0_funcs; break; + case IP_VERSION(7, 1, 0): + adev->lsdma.funcs = &lsdma_v7_1_funcs; + break; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c new file mode 100644 index 0000000000000..d93a0e65ce7de --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c @@ -0,0 +1,99 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "lsdma_v7_1.h" +#include "amdgpu_lsdma.h" + +#include "lsdma/lsdma_7_1_0_offset.h" +#include "lsdma/lsdma_7_1_0_sh_mask.h" + +static int lsdma_v7_1_wait_pio_status(struct amdgpu_device *adev) +{ + return amdgpu_lsdma_wait_for(adev, SOC15_REG_OFFSET(LSDMA, 0, regLSDMA_PIO_STATUS), + LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK, + LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK); +} + +static int lsdma_v7_1_copy_mem(struct amdgpu_device *adev, + uint64_t src_addr, + uint64_t dst_addr, + uint64_t size) +{ + int ret; + uint32_t tmp; + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr)); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); + + tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, COUNT, size); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, RAW_WAIT, 0); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); + + ret = lsdma_v7_1_wait_pio_status(adev); + if (ret) + dev_err(adev->dev, "LSDMA PIO failed to copy memory!\n"); + + return ret; +} + +static int lsdma_v7_1_fill_mem(struct amdgpu_device *adev, + uint64_t dst_addr, + uint32_t data, + uint64_t size) +{ + int ret; + uint32_t tmp; + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); + + tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, COUNT, size); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, RAW_WAIT, 0); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); + + ret = lsdma_v7_1_wait_pio_status(adev); + if (ret) + dev_err(adev->dev, "LSDMA PIO failed to fill memory!\n"); + + return ret; +} + +const struct amdgpu_lsdma_funcs lsdma_v7_1_funcs = { + .copy_mem = lsdma_v7_1_copy_mem, + .fill_mem = lsdma_v7_1_fill_mem, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h new file mode 100644 index 0000000000000..3d1ab605849a0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h @@ -0,0 +1,31 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __LSDMA_V7_1_H__ +#define __LSDMA_V7_1_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_lsdma_funcs lsdma_v7_1_funcs; + +#endif /* __LSDMA_V7_1_H__ */ From 8e9117bb338d0bf69d01512986ff68ad9781ea3b Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 26 Jul 2024 09:33:17 +0800 Subject: [PATCH 1819/2070] drm/amdgpu: fix DF NULL pointer issue for soc24 If DF function not initialized, NULL pointer issue will happen on soc24. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 308f32daa7802..d1adf19a51c45 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -478,7 +478,7 @@ static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block) if (adev->nbio.funcs->remap_hdp_registers) adev->nbio.funcs->remap_hdp_registers(adev); - if (adev->df.funcs->hw_init) + if (adev->df.funcs && adev->df.funcs->hw_init) adev->df.funcs->hw_init(adev); /* enable the doorbell aperture */ From 55d8206156b1555318a7299342cd1b7cecc3592f Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 2 Dec 2025 21:36:19 +0800 Subject: [PATCH 1820/2070] drm/amdgpu: Handle IH v7_1 reg offset differences IH v7_1 changes the offsets of some registers relative to IH v7_0. Introduce IH v7_1-specific register access Signed-off-by: Hawking Zhang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 36 ++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 451828bf583e4..1fbe904f4223b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -289,6 +289,13 @@ static uint32_t ih_v7_0_setup_retry_doorbell(u32 doorbell_index) return val; } +#define regIH_RING1_CLIENT_CFG_INDEX_V7_1 0x122 +#define regIH_RING1_CLIENT_CFG_INDEX_V7_1_BASE_IDX 0 +#define regIH_RING1_CLIENT_CFG_DATA_V7_1 0x123 +#define regIH_RING1_CLIENT_CFG_DATA_V7_1_BASE_IDX 0 +#define regIH_CHICKEN_V7_1 0x129 +#define regIH_CHICKEN_V7_1_BASE_IDX 0 + /** * ih_v7_0_irq_init - init and enable the interrupt ring * @@ -307,6 +314,7 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) u32 tmp; int ret; int i; + u32 reg_addr; /* disable irqs */ ret = ih_v7_0_toggle_interrupts(adev, false); @@ -318,10 +326,15 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) { if (ih[0]->use_bus_addr) { - ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_CHICKEN_V7_1); + else + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_CHICKEN); + ih_chicken = RREG32(reg_addr); + /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); - WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken); + WREG32(reg_addr, ih_chicken); } } @@ -358,17 +371,26 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) /* Redirect the interrupts to IH RB1 for dGPU */ if (adev->irq.ih1.ring_size) { - tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX_V7_1); + else + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX); + tmp = RREG32(reg_addr); + /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0); - WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp); + WREG32(reg_addr, tmp); - tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA_V7_1); + else + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA); + tmp = RREG32(reg_addr); + /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa); tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0); tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID_MATCH_ENABLE, 0x1); - - WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp); + WREG32(reg_addr, tmp); } pci_set_master(adev->pdev); From 4fddd891b2f58478e1e1aafd21fc6fa757d5c8aa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 18 Nov 2025 17:41:02 -0500 Subject: [PATCH 1821/2070] drm/amdgpu: use common defines for GMC 12.1 HUB faults Use proper definitions rather than a number. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 0e8a52d965738..b9fdc3276e816 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -94,6 +94,10 @@ enum amdgpu_memory_partition { #define AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE 0x20 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_EXE 0x10 +#define AMDGPU_GMC121_FAULT_SOURCE_DATA_READ 0x400000 +#define AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE 0x200000 +#define AMDGPU_GMC121_FAULT_SOURCE_DATA_EXE 0x100000 + /* * GMC page fault information */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index dc8865c5879c8..c49112d8300e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -121,7 +121,7 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, if (entry->src_id == UTCL2_1_0__SRCID__RETRY) { retry_fault = true; - write_fault = !!(entry->src_data[1] & 0x200000); + write_fault = !!(entry->src_data[1] & AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE); } if (entry->client_id == SOC_V1_0_IH_CLIENTID_VMC) { From 63f36bf7da2f1d7f4ec54951e987c98611d9fbee Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 25 Nov 2025 01:42:42 +0800 Subject: [PATCH 1822/2070] drm/amdgpu: Add default reset method for soc_v1_0 Add mode2 as default reset method for soc_v1_0 v2: Remove unnecessary overrides while selecting reset method (Lijo) v4: Add dev_warn_once (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 26e7566a5479c..bd7043729e6a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -229,8 +229,31 @@ static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) return false; } +static enum amd_reset_method +soc_v1_0_asic_reset_method(struct amdgpu_device *adev) +{ + if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || + (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { + if (amdgpu_reset_method != -1) + dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); + + return AMD_RESET_METHOD_MODE2; + } + + return amdgpu_reset_method; +} + static int soc_v1_0_asic_reset(struct amdgpu_device *adev) { + switch (soc_v1_0_asic_reset_method(adev)) { + case AMD_RESET_METHOD_MODE2: + dev_info(adev->dev, "MODE2 reset\n"); + return amdgpu_dpm_mode2_reset(adev); + default: + dev_info(adev->dev, "Invalid reset method Not supported\n"); + return -EOPNOTSUPP; + } + return 0; } @@ -244,6 +267,7 @@ static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { .need_reset_on_init = &soc_v1_0_need_reset_on_init, .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, .reset = soc_v1_0_asic_reset, + .reset_method = &soc_v1_0_asic_reset_method, }; static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) From 26de2470c719221e6f865f13929e3d060656beb4 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 2 Dec 2025 10:54:59 +0800 Subject: [PATCH 1823/2070] drm/amd/amdgpu: Disable reset on init for soc_v1_0 Return false from soc_v1_0_reset_on_init as psp is loaded with ifwi and sol register will be non zero on first load itself Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index bd7043729e6a3..43209eae81bbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -214,17 +214,6 @@ static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) { - u32 sol_reg; - - if (adev->flags & AMD_IS_APU) - return false; - - /* Check sOS sign of life register to confirm sys driver and sOS - * are already been loaded. - */ - sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); - if (sol_reg) - return true; return false; } From 611d6cd91f6e727cfc5db98a0c9dbde94dd409f6 Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 2 Dec 2025 19:46:36 +0800 Subject: [PATCH 1824/2070] drm/amdgpu: update GFX CGCG/LS flags for gfx 12.1 Update GFX CGCG flags and fix num_xcc assignment Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 43209eae81bbc..a0e10dbf07337 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -281,7 +281,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 1, 0): - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; break; From 899049f6577904c774ed29b0224fb2c97dad237c Mon Sep 17 00:00:00 2001 From: Le Ma Date: Fri, 12 Dec 2025 18:43:47 +0800 Subject: [PATCH 1825/2070] drm/amdgpu: bypass IMU ucode loading for MP0 15.0.8 For MP0 15.0.8, IMU ucode is part of IFWI and ASP would load it by default. Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 9854858e4c731..727ce2eac40fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3096,6 +3096,13 @@ static int psp_load_non_psp_fw(struct psp_context *psp) */ continue; + /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ + if (amdgpu_ip_version(adev, MP0_HWIP, 0) == + IP_VERSION(15, 0, 8) && + (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || + ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) + continue; + psp_print_fw_hdr(psp, ucode); ret = psp_execute_ip_fw_load(psp, ucode); From c4e25cffa77d7b4eb918569a77a9a38590b86f7d Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Wed, 28 Jan 2026 18:53:40 +0800 Subject: [PATCH 1826/2070] drm/amdgpu: fix shift-out-of-bounds when updating umc active mask UMC node_inst_num can exceed 32, causing (1 << node_inst_num) to shift a 32-bit int out of bounds Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index e97f57ea190f2..4290d9a31cf60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -798,7 +798,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, struct harvest_table *harvest_info; u16 offset; int i; - uint32_t umc_harvest_config = 0; + u64 umc_harvest_config = 0; if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) return; @@ -855,7 +855,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, } } - adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & + adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & ~umc_harvest_config; } From 61dc0e38484898aa12ad93402cce5df9de771c4c Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 6 Feb 2026 09:09:47 +0800 Subject: [PATCH 1827/2070] drm/amdgpu: correct SDMA instance number for soc v1_0 Calculate sdma instance number according to xcc_mask and num_inst_per_xcc, and correct adev->sdma.sdma_mask according to totally sdma instance number. Signed-off-by: Likun Gao Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index a0e10dbf07337..90a69ef41c4b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -823,7 +823,7 @@ int soc_v1_0_init_soc_config(struct amdgpu_device *adev) { int ret, i; int xcc_inst_per_aid = 4; - uint16_t xcc_mask; + uint16_t xcc_mask, sdma_mask = 0; xcc_mask = adev->gfx.xcc_mask; adev->aid_mask = 0; @@ -833,10 +833,12 @@ int soc_v1_0_init_soc_config(struct amdgpu_device *adev) } adev->sdma.num_inst_per_xcc = 2; - adev->sdma.num_instances = - NUM_XCC(adev->gfx.xcc_mask) * adev->sdma.num_inst_per_xcc; - adev->sdma.sdma_mask = - GENMASK(adev->sdma.num_instances - 1, 0); + for_each_inst(i, adev->gfx.xcc_mask) + sdma_mask |= + GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << + (i * adev->sdma.num_inst_per_xcc); + adev->sdma.sdma_mask = sdma_mask; + adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); ret = soc_v1_0_xcp_mgr_init(adev); if (ret) From 5e236b246decbfa3d561fd417e8f2cb09ebe512b Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Thu, 26 Feb 2026 13:11:27 +0800 Subject: [PATCH 1828/2070] drm/amdgpu: change sdma doorbell size for soc v1 Change SDMA doorbel size to 14 per SDMA engine. Signed-off-by: Likun Gao Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 90a69ef41c4b0..0c7759b82fa63 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -57,7 +57,7 @@ static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; - adev->doorbell_index.sdma_doorbell_range = 20; + adev->doorbell_index.sdma_doorbell_range = 14; for (i = 0; i < adev->sdma.num_instances; i++) adev->doorbell_index.sdma_engine[i] = AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + From 09ae0a852d2061209a12ed23cff72198ab3fda6a Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Sat, 14 Feb 2026 04:22:56 +0800 Subject: [PATCH 1829/2070] drm/amdgpu: disable rlc fw info print Disable to print RLC v2_5 related firmware information by default. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 1ab61e7b35db6..82333aeb44530 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -291,22 +291,22 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) break; case 5: /* rlc_hdr v2_5 */ - DRM_INFO("rlc_iram_ucode_size_bytes: %u\n", + DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_size_bytes)); - DRM_INFO("rlc_iram_ucode_offset_bytes: %u\n", + DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_offset_bytes)); - DRM_INFO("rlc_dram_ucode_size_bytes: %u\n", + DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_size_bytes)); - DRM_INFO("rlc_dram_ucode_offset_bytes: %u\n", + DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_offset_bytes)); /* rlc_hdr v2_5 */ - DRM_INFO("rlc_1_iram_ucode_size_bytes: %u\n", + DRM_DEBUG("rlc_1_iram_ucode_size_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_size_bytes)); - DRM_INFO("rlc_1_iram_ucode_offset_bytes: %u\n", + DRM_DEBUG("rlc_1_iram_ucode_offset_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_offset_bytes)); - DRM_INFO("rlc_1_dram_ucode_size_bytes: %u\n", + DRM_DEBUG("rlc_1_dram_ucode_size_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_size_bytes)); - DRM_INFO("rlc_1_dram_ucode_offset_bytes: %u\n", + DRM_DEBUG("rlc_1_dram_ucode_offset_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_offset_bytes)); break; default: From 7847571f6abfe624dbdf516d6fc770b22e2a2f11 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 27 Feb 2026 15:16:09 +0800 Subject: [PATCH 1830/2070] drm/amdgpu: fix sysfs ip base addr with 64bit Correct the base addr value shown on sysfs with ignore reg_base_64, since the base_addr value have been over write when discovery_init. Signed-off-by: Likun Gao Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 4290d9a31cf60..b3876293d344f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1237,13 +1237,8 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, ip_hw_instance->num_instance); ip_hw_instance->num_base_addresses = ip->num_base_address; - for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { - if (reg_base_64) - ip_hw_instance->base_addr[kk] = - lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; - else - ip_hw_instance->base_addr[kk] = ip->base_address[kk]; - } + for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) + ip_hw_instance->base_addr[kk] = ip->base_address[kk]; kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; From 4fa62882149730c7533c6932181abca14569d32e Mon Sep 17 00:00:00 2001 From: Le Ma Date: Mon, 2 Mar 2026 15:43:20 +0800 Subject: [PATCH 1831/2070] drm/amdgpu: fix array out of bounds accesses for mes sw_fini The mes.fw[] is per-pipe resource shared accross xcc inst. And enlarge hung_queue array to max inst_pipes. Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 6 +++--- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 4 +++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index bcf2a067dc410..f80e3aca9c78e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -159,9 +159,9 @@ struct amdgpu_mes { int hung_queue_db_array_size; int hung_queue_hqd_info_offset; - struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES]; - void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; /* cooperative dispatch */ bool enable_coop_mode; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index 7b8c670d0a9ed..d8e4b52bdfd50 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -1611,7 +1611,6 @@ static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], &adev->mes.eop_gpu_addr[inst], NULL); - amdgpu_ucode_release(&adev->mes.fw[inst]); if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, @@ -1622,6 +1621,9 @@ static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) } } + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) + amdgpu_ucode_release(&adev->mes.fw[pipe]); + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { if (!adev->enable_uni_mes) { amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, From 8e0160ddc64b54f2c45faaf49b44c3f7f652915f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 9 Mar 2026 15:17:00 +0530 Subject: [PATCH 1832/2070] drm/amd/pm: Fix xgmi max speed reporting Fix XGMI max bitrate/width reporting on SMUv13.0.12 SOCs. The data format got changed when moved to static table from dynamic metrics table. Fixes: 1bec2f270766 ("drm/amd/pm: Fetch SMUv13.0.12 xgmi max speed/width") Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 96a58d43db538..67cd186bd2632 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -269,8 +269,9 @@ static void smu_v13_0_12_init_xgmi_data(struct smu_context *smu, int ret; if (smu_table->tables[SMU_TABLE_SMU_METRICS].version >= 0x13) { - max_width = (uint8_t)static_metrics->MaxXgmiWidth; - max_speed = (uint16_t)static_metrics->MaxXgmiBitrate; + max_width = (uint8_t)SMUQ10_ROUND(static_metrics->MaxXgmiWidth); + max_speed = + (uint16_t)SMUQ10_ROUND(static_metrics->MaxXgmiBitrate); ret = 0; } else { MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table; From caa4892742c6fe068cadfe8b166cd351ded06a7d Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 12 Mar 2026 10:25:05 +0800 Subject: [PATCH 1833/2070] Bump AMDGPU version to 6.19.1 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index c8b68a0e2e267..c5bf80bd9a95a 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.19.0) +AC_INIT(amdgpu-dkms, 6.19.1) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 78ed4bbae9c8caeadce5f7099f87e57399e344b4 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 10 Mar 2026 11:58:22 -0500 Subject: [PATCH 1834/2070] drm/amd: Set num IP blocks to 0 if discovery fails If discovery has failed for any reason (such as no support for a block) then there is no need to unwind all the IP blocks in fini. In this condition there can actually be failures during the unwind too. Reset num_ip_blocks to zero during failure path and skip the unnecessary cleanup path. Cc: stable@vger.kernel.org Suggested-by: Lijo Lazar Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a778083998ae2..9f18365048ec2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2025,8 +2025,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) break; default: r = amdgpu_discovery_set_ip_blocks(adev); - if (r) + if (r) { + adev->num_ip_blocks = 0; return r; + } break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 7897bdf25d4c8..bbf339b1ecbe4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -83,7 +83,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); - if (adev == NULL) + if (adev == NULL || !adev->num_ip_blocks) return; amdgpu_unregister_gpu_instance(adev); From 4db26f39ce822d59df31874d69d6c8dfe6adaadf Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 11 Jun 2025 10:11:13 +0800 Subject: [PATCH 1835/2070] drm/amdgpu/mes_v12_1: add mes self test Add mes self test to ensure that mes user queue work. V2: add pasid on amdgpu_vm_init. V3: Squash in fix non-SPX modes (Mukul) Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 335 ++++++++++++++++++++++++- 1 file changed, 334 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index d8e4b52bdfd50..2b3dbc3190ce6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -31,6 +31,8 @@ #include "gc/gc_11_0_0_default.h" #include "v12_structs.h" #include "mes_v12_api_def.h" +#include "gfx_v12_1_pkt.h" +#include "sdma_v7_1_0_pkt_open.h" MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); @@ -41,6 +43,7 @@ static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id); static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); +static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id); #define MES_EOP_SIZE 2048 @@ -1949,10 +1952,31 @@ static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) return 0; } +static int mes_v12_1_late_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + /* TODO: remove it if issue fixed. */ + if (adev->mes.enable_coop_mode) + return 0; + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + /* for COOP mode, only test master xcc. */ + if (adev->mes.enable_coop_mode && + adev->mes.master_xcc_ids[xcc_id] != xcc_id) + continue; + + mes_v12_1_self_test(adev, xcc_id); + } + + return 0; +} + static const struct amd_ip_funcs mes_v12_1_ip_funcs = { .name = "mes_v12_1", .early_init = mes_v12_1_early_init, - .late_init = NULL, + .late_init = mes_v12_1_late_init, .sw_init = mes_v12_1_sw_init, .sw_fini = mes_v12_1_sw_fini, .hw_init = mes_v12_1_hw_init, @@ -1968,3 +1992,312 @@ const struct amdgpu_ip_block_version mes_v12_1_ip_block = { .rev = 0, .funcs = &mes_v12_1_ip_funcs, }; + +static int mes_v12_1_alloc_test_buf(struct amdgpu_device *adev, + struct amdgpu_bo **bo, uint64_t *addr, + void **ptr, int size) +{ + amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, + bo, addr, ptr); + if (!*bo) { + dev_err(adev->dev, "failed to allocate test buffer bo\n"); + return -ENOMEM; + } + memset(*ptr, 0, size); + return 0; +} + +static int mes_v12_1_map_test_bo(struct amdgpu_device *adev, + struct amdgpu_bo *bo, struct amdgpu_vm *vm, + struct amdgpu_bo_va **bo_va, u64 va, int size) +{ + struct amdgpu_sync sync; + int r; + + r = amdgpu_map_static_csa(adev, vm, bo, bo_va, va, size); + if (r) + return r; + + amdgpu_sync_create(&sync); + + r = amdgpu_vm_bo_update(adev, *bo_va, false); + if (r) { + dev_err(adev->dev, "failed to do vm_bo_update on meta data\n"); + goto error; + } + amdgpu_sync_fence(&sync, (*bo_va)->last_pt_update, GFP_KERNEL); + + r = amdgpu_vm_update_pdes(adev, vm, false); + if (r) { + dev_err(adev->dev, "failed to update pdes on meta data\n"); + goto error; + } + amdgpu_sync_fence(&sync, vm->last_update, GFP_KERNEL); + amdgpu_sync_wait(&sync, false); + +error: + amdgpu_sync_free(&sync); + return 0; +} + +static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id, + u32 *queue_ptr, u64 fence_gpu_addr, + void *fence_cpu_ptr, void *wptr_cpu_addr, + u64 doorbell_idx, int queue_type) +{ + volatile uint32_t *cpu_ptr = fence_cpu_ptr; + int num_xcc = NUM_XCC(adev->gfx.xcc_mask); + int sdma_ring_align = 0x10, compute_ring_align = 0x100; + uint32_t tmp, xcc_offset; + int r = 0, i, wptr = 0; + + if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { + if (!adev->mes.enable_coop_mode) { + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regSCRATCH_REG0, 0xCAFEDEAD); + } else { + for (i = 0; i < num_xcc; i++) { + if (adev->mes.master_xcc_ids[i] == xcc_id) + WREG32_SOC15(GC, GET_INST(GC, i), + regSCRATCH_REG0, 0xCAFEDEAD); + } + } + + xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); + queue_ptr[wptr++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); + queue_ptr[wptr++] = xcc_offset - PACKET3_SET_UCONFIG_REG_START; + queue_ptr[wptr++] = 0xDEADBEEF; + + for (i = wptr; i < compute_ring_align; i++) + queue_ptr[wptr++] = PACKET3(PACKET3_NOP, 0x3FFF); + + } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { + *cpu_ptr = 0xCAFEDEAD; + + queue_ptr[wptr++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + queue_ptr[wptr++] = lower_32_bits(fence_gpu_addr); + queue_ptr[wptr++] = upper_32_bits(fence_gpu_addr); + queue_ptr[wptr++] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); + queue_ptr[wptr++] = 0xDEADBEEF; + + for (i = wptr; i < sdma_ring_align; i++) + queue_ptr[wptr++] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + + wptr <<= 2; + } + + atomic64_set((atomic64_t *)wptr_cpu_addr, wptr); + WDOORBELL64(doorbell_idx, wptr); + + for (i = 0; i < adev->usec_timeout; i++) { + if (queue_type == AMDGPU_RING_TYPE_SDMA) { + tmp = le32_to_cpu(*cpu_ptr); + } else { + if (!adev->mes.enable_coop_mode) { + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regSCRATCH_REG0); + } else { + for (i = 0; i < num_xcc; i++) { + if (xcc_id != adev->mes.master_xcc_ids[i]) + continue; + + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regSCRATCH_REG0); + if (tmp != 0xDEADBEEF) + break; + } + } + } + + if (tmp == 0xDEADBEEF) + break; + + if (amdgpu_emu_mode == 1) + msleep(1); + else + udelay(1); + } + + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "xcc%d: mes self test (%s) failed\n", xcc_id, + queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); + + while (halt_if_hws_hang) + schedule(); + + r = -ETIMEDOUT; + } else { + dev_info(adev->dev, "xcc%d: mes self test (%s) pass\n", xcc_id, + queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); + } + + return r; +} + +#define USER_CTX_SIZE (PAGE_SIZE * 2) +#define USER_CTX_VA AMDGPU_VA_RESERVED_BOTTOM +#define RING_OFFSET(addr) ((addr)) +#define EOP_OFFSET(addr) ((addr) + PAGE_SIZE) +#define WPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64)) +#define RPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 2) +#define FENCE_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 3) + +static int mes_v12_1_test_queue(struct amdgpu_device *adev, int xcc_id, + int pasid, struct amdgpu_vm *vm, u64 meta_gpu_addr, + u64 queue_gpu_addr, void *ctx_ptr, int queue_type) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + struct amdgpu_mqd *mqd_mgr = &adev->mqds[queue_type]; + struct amdgpu_mqd_prop mqd_prop = {0}; + struct mes_add_queue_input add_queue = {0}; + struct mes_remove_queue_input remove_queue = {0}; + struct amdgpu_bo *mqd_bo = NULL; + int num_xcc = NUM_XCC(adev->gfx.xcc_mask); + int i, r, off, mqd_size, mqd_count = 1; + void *mqd_ptr = NULL; + u64 mqd_gpu_addr, doorbell_idx; + + /* extra one page size padding for mes fw */ + mqd_size = mqd_mgr->mqd_size + PAGE_SIZE; + + if (queue_type == AMDGPU_RING_TYPE_SDMA) { + doorbell_idx = adev->mes.db_start_dw_offset + \ + adev->doorbell_index.sdma_engine[0]; + } else { + doorbell_idx = adev->mes.db_start_dw_offset + \ + adev->doorbell_index.userqueue_start; + } + + if (adev->mes.enable_coop_mode && + queue_type == AMDGPU_RING_TYPE_COMPUTE) { + for (i = 0, mqd_count = 0; i < num_xcc; i++) { + if (adev->mes.master_xcc_ids[i] == xcc_id) + mqd_count++; + } + mqd_size *= mqd_count; + } + + r = mes_v12_1_alloc_test_buf(adev, &mqd_bo, &mqd_gpu_addr, + &mqd_ptr, mqd_size * mqd_count); + if (r < 0) + return r; + + mqd_prop.mqd_gpu_addr = mqd_gpu_addr; + mqd_prop.hqd_base_gpu_addr = RING_OFFSET(USER_CTX_VA); + mqd_prop.eop_gpu_addr = EOP_OFFSET(USER_CTX_VA); + mqd_prop.wptr_gpu_addr = WPTR_OFFSET(USER_CTX_VA); + mqd_prop.rptr_gpu_addr = RPTR_OFFSET(USER_CTX_VA); + mqd_prop.doorbell_index = doorbell_idx; + mqd_prop.queue_size = PAGE_SIZE; + mqd_prop.mqd_stride_size = mqd_size; + mqd_prop.use_doorbell = true; + mqd_prop.hqd_active = false; + + mqd_mgr->init_mqd(adev, mqd_ptr, &mqd_prop); + if (mqd_count > 1) { + for (i = 1; i < mqd_count; i++) { + off = mqd_size * i; + mqd_prop.mqd_gpu_addr = mqd_gpu_addr + off; + mqd_mgr->init_mqd(adev, (char *)mqd_ptr + off, + &mqd_prop); + } + } + + add_queue.xcc_id = xcc_id; + add_queue.process_id = pasid; + add_queue.page_table_base_addr = adev->vm_manager.vram_base_offset + + amdgpu_bo_gpu_offset(vm->root.bo) - adev->gmc.vram_start; + add_queue.process_va_start = 0; + add_queue.process_va_end = adev->vm_manager.max_pfn - 1; + add_queue.process_context_addr = meta_gpu_addr; + add_queue.gang_context_addr = meta_gpu_addr + AMDGPU_MES_PROC_CTX_SIZE; + add_queue.doorbell_offset = doorbell_idx; + add_queue.mqd_addr = mqd_gpu_addr; + add_queue.wptr_addr = mqd_prop.wptr_gpu_addr; + add_queue.wptr_mc_addr = WPTR_OFFSET(queue_gpu_addr); + add_queue.queue_type = queue_type; + add_queue.vm_cntx_cntl = hub->vm_cntx_cntl; + + r = mes_v12_1_add_hw_queue(&adev->mes, &add_queue); + if (r) + goto error; + + mes_v12_1_test_ring(adev, xcc_id, (u32 *)RING_OFFSET((char *)ctx_ptr), + FENCE_OFFSET(USER_CTX_VA), + FENCE_OFFSET((char *)ctx_ptr), + WPTR_OFFSET((char *)ctx_ptr), + doorbell_idx, queue_type); + + remove_queue.xcc_id = xcc_id; + remove_queue.doorbell_offset = doorbell_idx; + remove_queue.gang_context_addr = add_queue.gang_context_addr; + r = mes_v12_1_remove_hw_queue(&adev->mes, &remove_queue); + +error: + amdgpu_bo_free_kernel(&mqd_bo, &mqd_gpu_addr, &mqd_ptr); + return r; +} + +static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id) +{ + int queue_types[] = { AMDGPU_RING_TYPE_COMPUTE, + /* AMDGPU_RING_TYPE_SDMA */ }; + struct amdgpu_bo_va *bo_va = NULL; + struct amdgpu_vm *vm = NULL; + struct amdgpu_bo *meta_bo = NULL, *ctx_bo = NULL; + void *meta_ptr = NULL, *ctx_ptr = NULL; + u64 meta_gpu_addr, ctx_gpu_addr; + int size, i, r, pasid;; + + pasid = amdgpu_pasid_alloc(16); + if (pasid < 0) + pasid = 0; + + size = AMDGPU_MES_PROC_CTX_SIZE + AMDGPU_MES_GANG_CTX_SIZE; + r = mes_v12_1_alloc_test_buf(adev, &meta_bo, &meta_gpu_addr, + &meta_ptr, size); + if (r < 0) + goto err2; + + r = mes_v12_1_alloc_test_buf(adev, &ctx_bo, &ctx_gpu_addr, + &ctx_ptr, USER_CTX_SIZE); + if (r < 0) + goto err2; + + vm = kzalloc(sizeof(*vm), GFP_KERNEL); + if (!vm) { + r = -ENOMEM; + goto err2; + } + + r = amdgpu_vm_init(adev, vm, -1, pasid); + if (r) + goto err1; + + r = mes_v12_1_map_test_bo(adev, ctx_bo, vm, &bo_va, + USER_CTX_VA, USER_CTX_SIZE); + if (r) + goto err0; + + for (i = 0; i < ARRAY_SIZE(queue_types); i++) { + memset(ctx_ptr, 0, USER_CTX_SIZE); + + r = mes_v12_1_test_queue(adev, xcc_id, pasid, vm, meta_gpu_addr, + ctx_gpu_addr, ctx_ptr, queue_types[i]); + if (r) + break; + } + + amdgpu_unmap_static_csa(adev, vm, ctx_bo, bo_va, USER_CTX_VA); +err0: + amdgpu_vm_fini(adev, vm); +err1: + kfree(vm); +err2: + amdgpu_bo_free_kernel(&meta_bo, &meta_gpu_addr, &meta_ptr); + amdgpu_bo_free_kernel(&ctx_bo, &ctx_gpu_addr, &ctx_ptr); + amdgpu_pasid_free(pasid); + return r; +} + From 95f94cd7c85b9988e68100c3e4be6b8227768b7a Mon Sep 17 00:00:00 2001 From: Michael Chen Date: Tue, 6 Jan 2026 15:22:57 +0800 Subject: [PATCH 1836/2070] drm/amdgpu: Fix RRMT for gfx v12_1 Correct NORMALIZE_XCC_REG_OFFSET to 0xFFFF because reg offset is in DW. Also set mode 3 temporarily for out of XCD access for MMHUB TLB flush. Will need to figure out how to differentiate between AID and MID access later. Signed-off-by: Michael Chen Reviewed-by: Alex Sierra Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index 2b3dbc3190ce6..ca8cacd345736 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -512,7 +512,7 @@ static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; } else { - rrmt_opt->mode = MES_RRMT_MODE_LOCAL_REMOTE_AID; + rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID; } } From 18f940b6071e8d9528e09fe98999ba5d3fcf1cc8 Mon Sep 17 00:00:00 2001 From: Sreekant Somasekharan Date: Thu, 6 Nov 2025 19:15:11 -0500 Subject: [PATCH 1837/2070] drm/amdgpu: Revert setting up Retry based Thrashing on GFX 12.1 Bug found with retry based thrashing mechanism. Revert to the old thrashing method. Signed-off-by: Sreekant Somasekharan Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 4e02b62cdbb33..6f2240f0ac524 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2631,24 +2631,6 @@ static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); } -static void gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(struct amdgpu_device *adev, - int xcc_id) -{ - uint32_t val; - - /* Set the TCP UTCL0 register to enable atomics */ - val = RREG32_SOC15(GC, GET_INST(GC, xcc_id), - regTCP_UTCL0_THRASHING_CTRL); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x1); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x1); - - WREG32_SOC15(GC, GET_INST(GC, xcc_id), - regTCP_UTCL0_THRASHING_CTRL, val); -} - static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, int xcc_id) { @@ -2697,7 +2679,6 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { gfx_v12_1_xcc_disable_burst(adev, i); gfx_v12_1_xcc_enable_atomics(adev, i); - gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i); gfx_v12_1_xcc_disable_early_write_ack(adev, i); gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); } From 8cd368f280e532c822a458aec4e058f8fadef40f Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 9 Dec 2025 16:01:10 -0500 Subject: [PATCH 1838/2070] drm/amdkfd: Update queue properties for metadata ring Metadata ring and queue ring is allocated as one buffer and map to GPU, so update queue peoperties should add the queue metadata size and ring size as buffer size to validate queue ring buffer. Fixes: c51bb53d5c68 ("drm/amdkfd: Add metadata ring buffer for compute") Signed-off-by: Philip Yang Reviewed-by: Alex Sierra Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index f06d10a58300a..1c4a04029b82c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -594,7 +594,8 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm, return err; if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, - p->queue_size)) { + p->queue_size + + pqn->q->properties.metadata_queue_size)) { pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", p->queue_address, p->queue_size); amdgpu_bo_unreserve(vm->root.bo); From 3409da74f9bb765b39ddb4ea27a96a9e5d233c38 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Fri, 5 Dec 2025 16:45:41 +0800 Subject: [PATCH 1839/2070] drm/amdgpu/mes12_1: fix the failure access to MID1 registers Correct the mid die id and mid1 register relative offset for mes fw to access to mid1 registers. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 55 ++++++++------------------ drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 33 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/soc_v1_0.h | 2 + 3 files changed, 52 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index ca8cacd345736..5dcc2c32644ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -494,16 +494,12 @@ static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, } static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) { - /* Check xcc reg offset range */ - uint32_t xcc = (reg_offset & XCC_MID_MASK) ? 4 : 0; - /* Each XCC has two register ranges. - * These are represented in reg_offset[17:16] - */ - return ((reg_offset >> 16) & 0x3) + xcc; + return ((reg_offset >> 16) & 0x7); } static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, - struct RRMT_OPTION *rrmt_opt) + struct RRMT_OPTION *rrmt_opt, + uint32_t *out_reg) { uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); @@ -513,7 +509,11 @@ static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; } else { rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID; + if (soc_v1_0_mid1_reg_range(reg)) + rrmt_opt->mid_die_id = 1; } + + *out_reg = soc_v1_0_normalize_reg_offset(reg); } static int mes_v12_1_misc_op(struct amdgpu_mes *mes, @@ -537,65 +537,44 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes, switch (input->op) { case MES_MISC_OP_READ_REG: misc_pkt.opcode = MESAPI_MISC__READ_REG; - misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; mes_v12_1_get_rrmt(input->read_reg.reg_offset, GET_INST(GC, input->xcc_id), - &misc_pkt.read_reg.rrmt_opt); - if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) { - misc_pkt.read_reg.reg_offset = - soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset); - } + &misc_pkt.read_reg.rrmt_opt, + &misc_pkt.read_reg.reg_offset); break; case MES_MISC_OP_WRITE_REG: misc_pkt.opcode = MESAPI_MISC__WRITE_REG; - misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; misc_pkt.write_reg.reg_value = input->write_reg.reg_value; mes_v12_1_get_rrmt(input->write_reg.reg_offset, GET_INST(GC, input->xcc_id), - &misc_pkt.write_reg.rrmt_opt); - if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) { - misc_pkt.write_reg.reg_offset = - soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset); - } + &misc_pkt.write_reg.rrmt_opt, + &misc_pkt.write_reg.reg_offset); break; case MES_MISC_OP_WRM_REG_WAIT: misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; - misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; misc_pkt.wait_reg_mem.reg_offset2 = 0; mes_v12_1_get_rrmt(input->wrm_reg.reg0, GET_INST(GC, input->xcc_id), - &misc_pkt.wait_reg_mem.rrmt_opt1); - if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { - misc_pkt.wait_reg_mem.reg_offset1 = - soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1); - } + &misc_pkt.wait_reg_mem.rrmt_opt1, + &misc_pkt.wait_reg_mem.reg_offset1); break; case MES_MISC_OP_WRM_REG_WR_WAIT: misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; - misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; - misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; mes_v12_1_get_rrmt(input->wrm_reg.reg0, GET_INST(GC, input->xcc_id), - &misc_pkt.wait_reg_mem.rrmt_opt1); + &misc_pkt.wait_reg_mem.rrmt_opt1, + &misc_pkt.wait_reg_mem.reg_offset1); mes_v12_1_get_rrmt(input->wrm_reg.reg1, GET_INST(GC, input->xcc_id), - &misc_pkt.wait_reg_mem.rrmt_opt2); - - if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { - misc_pkt.wait_reg_mem.reg_offset1 = - soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1); - } - if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) { - misc_pkt.wait_reg_mem.reg_offset2 = - soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2); - } + &misc_pkt.wait_reg_mem.rrmt_opt2, + &misc_pkt.wait_reg_mem.reg_offset2); break; case MES_MISC_OP_SET_SHADER_DEBUGGER: pipe = AMDGPU_MES_SCHED_PIPE; diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 0c7759b82fa63..37552c91a8781 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -41,6 +41,11 @@ #define NORMALIZE_XCC_REG_OFFSET(offset) \ (offset & 0xFFFF) +#define MID1_REG_RANGE_0_LOW 0x40000 +#define MID1_REG_RANGE_0_HIGH 0x80000 +#define NORMALIZE_MID_REG_OFFSET(offset) \ + (offset & 0x3FFFF) + /* Initialized doorbells for amdgpu including multimedia * KFD can use all the rest in 2M doorbell bar */ static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) @@ -870,3 +875,31 @@ uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) else return reg; } + +bool soc_v1_0_mid1_reg_range(uint32_t reg) +{ + uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) + return false; + + if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH)) + return true; + else + return false; +} + +uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg) +{ + uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) + return soc_v1_0_normalize_xcc_reg_offset(reg); + + /* check if the reg offset is inside MID1. */ + if (soc_v1_0_mid1_reg_range(reg)) + return NORMALIZE_MID_REG_OFFSET(reg); + + return reg; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h index 146996101aa07..16c220fcc4e92 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h @@ -31,7 +31,9 @@ void soc_v1_0_grbm_select(struct amdgpu_device *adev, int xcc_id); int soc_v1_0_init_soc_config(struct amdgpu_device *adev); bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg); +bool soc_v1_0_mid1_reg_range(uint32_t reg); uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg); +uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg); u64 soc_v1_0_encode_ext_smn_addressing(int ext_id); #endif From 698f8d3d7e77b4c153bdd192a69722c9c0227cca Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 17 Dec 2025 07:35:10 -0600 Subject: [PATCH 1840/2070] drm/amdgpu: 57-bit enable for watch address on gfx_v12_1 Add 57-bit support for debugger set watch address API Signed-off-by: Alex Sierra Co-authored-by: Alexey Kondratiev Reviewed-by: Philip.Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c index 965c7e688535a..bcb180f9d3ff8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c @@ -330,7 +330,7 @@ static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev, watch_address_cntl = 0; watch_address_low = lower_32_bits(watch_address); - watch_address_high = upper_32_bits(watch_address) & 0xffff; + watch_address_high = upper_32_bits(watch_address) & 0x1ffffff; watch_address_cntl = REG_SET_FIELD(watch_address_cntl, TCP_WATCH0_CNTL, From cfad4c00b5037a156a04f47f3fc849e869504e5c Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 9 Jan 2026 13:19:38 +0800 Subject: [PATCH 1841/2070] drm/amdgpu: retire some unsupport cmd pkt bit for gfx v12_1 Retire some unsupport CP command bit set for gfx v12_1. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 6f2240f0ac524..1a7ccfed8f0ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -136,7 +136,6 @@ static void gfx_v12_1_kiq_map_queues(struct amdgpu_ring *kiq_ring, PACKET3_MAP_QUEUES_PIPE(ring->pipe) | PACKET3_MAP_QUEUES_ME((me)) | PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ - PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); @@ -245,8 +244,7 @@ static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, /* memory (1) or register (0) */ (WAIT_REG_MEM_MEM_SPACE(mem_space) | WAIT_REG_MEM_OPERATION(opt) | /* wait */ - WAIT_REG_MEM_FUNCTION(3) | /* equal */ - WAIT_REG_MEM_ENGINE(eng_sel))); + WAIT_REG_MEM_FUNCTION(3))); /* equal */ if (mem_space) BUG_ON(addr0 & 0x3); /* Dword align */ @@ -3412,11 +3410,10 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; - gfx_v12_1_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), + gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr), upper_32_bits(addr), seq, 0xffffffff, 4); } @@ -3455,8 +3452,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, /* write fence seq to the "addr" */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); + amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); @@ -3464,8 +3460,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, if (flags & AMDGPU_FENCE_FLAG_INT) { /* set register to trigger INT */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); + amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ @@ -3524,9 +3519,7 @@ static void gfx_v12_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask) { - int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - - gfx_v12_1_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, + gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, ref, mask, 0x20); } From 90d2cd0040e6b1e6c4a107d3fce162c48b0da4f0 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 9 Jan 2026 10:34:20 +0800 Subject: [PATCH 1842/2070] drm/amdgpu: update cp packets for gfx v12_1 Clean up some unsupport CP packets for gfx v12_1. Update CP packets for gfx v12_1 with some new definition. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h | 223 ++++++++++----------- 1 file changed, 101 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h index 9a5c82c8db53b..21a07530c64d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h @@ -53,16 +53,10 @@ /* Packet 3 types */ #define PACKET3_NOP 0x10 -#define PACKET3_SET_BASE 0x11 -#define PACKET3_BASE_INDEX(x) ((x) << 0) -#define CE_PARTITION_BASE 3 #define PACKET3_CLEAR_STATE 0x12 #define PACKET3_INDEX_BUFFER_SIZE 0x13 #define PACKET3_DISPATCH_DIRECT 0x15 #define PACKET3_DISPATCH_INDIRECT 0x16 -#define PACKET3_INDIRECT_BUFFER_END 0x17 -#define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 -#define PACKET3_ATOMIC_GDS 0x1D #define PACKET3_ATOMIC_MEM 0x1E #define PACKET3_OCCLUSION_QUERY 0x1F #define PACKET3_SET_PREDICATION 0x20 @@ -74,47 +68,42 @@ #define PACKET3_INDEX_BASE 0x26 #define PACKET3_DRAW_INDEX_2 0x27 #define PACKET3_CONTEXT_CONTROL 0x28 -#define PACKET3_INDEX_TYPE 0x2A #define PACKET3_DRAW_INDIRECT_MULTI 0x2C #define PACKET3_DRAW_INDEX_AUTO 0x2D #define PACKET3_NUM_INSTANCES 0x2F #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 -#define PACKET3_INDIRECT_BUFFER_PRIV 0x32 -#define PACKET3_INDIRECT_BUFFER_CNST 0x33 -#define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 -#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 -#define PACKET3_DRAW_PREAMBLE 0x36 #define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) ((x) << 8) +#define WRITE_DATA_DST_SEL(x) (((x) & 0xf) << 8) /* 0 - register - * 1 - memory (sync - via GRBM) - * 2 - gl2 - * 3 - gds + * 1 - reserved + * 2 - tc_l2 + * 3 - reserved * 4 - reserved - * 5 - memory (async - direct) + * 5 - memory (same as tc_l2) + * 6 - memory_mapped_adc_persistent_state */ -#define WR_ONE_ADDR (1 << 16) +#define WRITE_DATA_SCOPE(x) (((x) & 0x3) << 12) +#define WRITE_DATA_MODE(x) (((x) & 0x3) << 14) + /* 0 - local xcd + * 1 - remote/local aid + * 2 - remote xcd + * 3 - remote mid + */ +#define WRITE_DATA_ADDR_INCR (1 << 16) +#define WRITE_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) #define WR_CONFIRM (1 << 20) -#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) - /* 0 - me - * 1 - pfp - * 2 - ce +#define WRITE_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) +#define WRITE_DATA_TEMPORAL(x) (((x) & 0x3) << 25) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu */ +#define WRITE_DATA_COOP_DISABLE (1 << 27) #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 -#define PACKET3_MEM_SEMAPHORE 0x39 -# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) -# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ -# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) -# define PACKET3_SEM_SEL_WAIT (0x7 << 29) -#define PACKET3_DRAW_INDEX_MULTI_INST 0x3A -#define PACKET3_COPY_DW 0x3B #define PACKET3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) +#define WAIT_REG_MEM_FUNCTION(x) (((x) & 0x7) << 0) /* 0 - always * 1 - < * 2 - <= @@ -123,33 +112,66 @@ * 5 - >= * 6 - > */ -#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) +#define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4) /* 0 - reg * 1 - mem */ -#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) +#define WAIT_REG_MEM_OPERATION(x) (((x) & 0x3) << 6) /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg */ -#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) - /* 0 - me - * 1 - pfp +#define WAIT_REG_MEM_MODE(x) (((x) & 0x3) << 10) + /* 0 - local xcd + * 1 - remote/local aid + * 2 - remote xcd + * 3 - remote mid + */ +#define WAIT_REG_MEM_MID_DIE_ID(x) (((x) & 0x3) << 12) +#define WAIT_REG_MEM_XCD_DIE_ID(x) (((x) & 0xf) << 14) +#define WAIT_REG_MEM_MES_INTR_PIPE(x) (((x) & 0x3) << 22) +#define WAIT_REG_MEM_MES_ACTION(x) (((x) & 0x1) << 24) +#define WAIT_REG_MEM_TEMPORAL(x) (((x) & 0x3) << 25) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu */ #define PACKET3_INDIRECT_BUFFER 0x3F #define INDIRECT_BUFFER_VALID (1 << 23) -#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) - /* 0 - LRU - * 1 - Stream - * 2 - Bypass +#define INDIRECT_BUFFER_TEMPORAL(x) (x) << 28) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu */ -#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) -#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) #define PACKET3_COND_INDIRECT_BUFFER 0x3F #define PACKET3_COPY_DATA 0x40 -#define PACKET3_CP_DMA 0x41 +#define COPY_DATA_SRC_SEL(x) (((x) & 0xf) << 0) +#define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) +#define COPY_DATA_SRC_SCOPE(x) (((x) & 0x3) << 4) +#define COPY_DATA_DST_SCOPE(x) (((x) & 0x3) << 27) +#define COPY_DATA_MODE(x) (((x) & 0x3) << 6) + /* 0 - local xcd + * 1 - remote/local aid + * 2 - remote xcd + * 3 - remote mid + */ +#define COPY_DATA_SRC_TEMPORAL(x) (((x) & 0x3) << 13) +#define COPY_DATA_DST_TEMPORAL(x) (((x) & 0x3) << 25) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu + */ +#define COPY_DATA_COUNT_SEL (1 << 16) +#define COPY_DATA_SRC_DST_REMOTE_MODE(x) (((x)) & 0x1 << 16) + /* 0 - src remote + * 1 - dst remote + */ +#define COPY_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) +#define COPY_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) +#define COPY_DATA_PQ_EXE_STATUS (1 << 27) #define PACKET3_PFP_SYNC_ME 0x42 -#define PACKET3_SURFACE_SYNC 0x43 -#define PACKET3_ME_INITIALIZE 0x44 #define PACKET3_COND_WRITE 0x45 #define PACKET3_EVENT_WRITE 0x46 #define EVENT_TYPE(x) ((x) << 0) @@ -160,8 +182,6 @@ * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH */ -#define PACKET3_EVENT_WRITE_EOP 0x47 -#define PACKET3_EVENT_WRITE_EOS 0x48 #define PACKET3_RELEASE_MEM 0x49 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) @@ -180,27 +200,30 @@ * 2 - temporal__release_mem__ht * 3 - temporal__release_mem__lu */ -#define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) +#define PACKET3_RELEASE_MEM_PQ_EXE_STATUS (1 << 28) +#define PACKET3_RELEASE_MEM_GCR_GLK_INV (1 << 30) -#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) - /* 0 - discard - * 1 - send low 32bit data - * 2 - send 64bit data - * 3 - send 64bit GPU counter value - * 4 - send 64bit sys counter value +#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) + /* 0 - memory controller + * 1 - TC/L2 + * 2 - register */ +#define PACKET3_RELEASE_MEM_MES_INTR_PIPE(x) ((x) << 20) +#define PACKET3_RELEASE_MEM_MES_ACTION_ID(x) ((x) << 22) #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) /* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed */ -#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) - /* 0 - MC - * 1 - TC/L2 +#define PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x) (1 << 28) +#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit GPU counter value + * 4 - send 64bit sys counter value */ - - #define PACKET3_PREAMBLE_CNTL 0x4A # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) @@ -218,26 +241,29 @@ /* 0 - ME * 1 - PFP */ -# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) - /* 0 - LRU - * 1 - Stream +# define PACKET3_DMA_DATA_SRC_TEMPORAL(x) ((x) << 13) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu */ -# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) +# define PACKET3_DMA_DATA_SRC_SCOPE(x) ((x) << 15) +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) /* 0 - DST_ADDR using DAS * 1 - GDS * 3 - DST_ADDR using L2 */ -# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) +# define PACKET3_DMA_DATA_DST_TEMPORAL(x) ((x) << 25) /* 0 - LRU * 1 - Stream */ -# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) +# define PACKET3_DMA_DATA_DST_SCOPE(x) ((x) << 27) +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) /* 0 - SRC_ADDR using SAS * 1 - GDS * 2 - DATA * 3 - SRC_ADDR using L2 */ -# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) /* COMMAND */ # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) /* 0 - memory @@ -247,13 +273,11 @@ /* 0 - memory * 1 - register */ -# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) -# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) -# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +# define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) #define PACKET3_CONTEXT_REG_RMW 0x51 -#define PACKET3_GFX_CNTX_UPDATE 0x52 -#define PACKET3_BLK_CNTX_UPDATE 0x53 -#define PACKET3_INCR_UPDT_STATE 0x55 #define PACKET3_ACQUIRE_MEM 0x58 /* 1. HEADER * 2. COHER_CNTL [30:0] @@ -307,10 +331,7 @@ * 2: REVERSE */ #define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) -#define PACKET3_REWIND 0x59 -#define PACKET3_INTERRUPT 0x5A #define PACKET3_GEN_PDEPTE 0x5B -#define PACKET3_INDIRECT_BUFFER_PASID 0x5C #define PACKET3_PRIME_UTCL2 0x5D #define PACKET3_LOAD_UCONFIG_REG 0x5E #define PACKET3_LOAD_SH_REG 0x5F @@ -324,12 +345,6 @@ #define PACKET3_SET_CONTEXT_REG 0x69 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 -#define PACKET3_SET_CONTEXT_REG_INDEX 0x6A -#define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 -#define PACKET3_SET_SH_REG_DI 0x72 -#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 -#define PACKET3_SET_SH_REG_DI_MULTI 0x74 -#define PACKET3_GFX_PIPE_LOCK 0x75 #define PACKET3_SET_SH_REG 0x76 #define PACKET3_SET_SH_REG_START 0x00002c00 #define PACKET3_SET_SH_REG_END 0x00003000 @@ -339,47 +354,19 @@ #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 #define PACKET3_SET_UCONFIG_REG_INDEX 0x7A -#define PACKET3_FORWARD_HEADER 0x7C -#define PACKET3_SCRATCH_RAM_WRITE 0x7D -#define PACKET3_SCRATCH_RAM_READ 0x7E -#define PACKET3_LOAD_CONST_RAM 0x80 -#define PACKET3_WRITE_CONST_RAM 0x81 -#define PACKET3_DUMP_CONST_RAM 0x83 -#define PACKET3_INCREMENT_CE_COUNTER 0x84 -#define PACKET3_INCREMENT_DE_COUNTER 0x85 -#define PACKET3_WAIT_ON_CE_COUNTER 0x86 -#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 -#define PACKET3_SWITCH_BUFFER 0x8B #define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C -#define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C #define PACKET3_DISPATCH_DRAW 0x8D -#define PACKET3_DISPATCH_DRAW_ACE 0x8D -#define PACKET3_GET_LOD_STATS 0x8E -#define PACKET3_DRAW_MULTI_PREAMBLE 0x8F -#define PACKET3_FRAME_CONTROL 0x90 -# define FRAME_TMZ (1 << 0) -# define FRAME_CMD(x) ((x) << 28) - /* - * x=0: tmz_begin - * x=1: tmz_end - */ #define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 #define PACKET3_WAIT_REG_MEM64 0x93 -#define PACKET3_COND_PREEMPT 0x94 #define PACKET3_HDP_FLUSH 0x95 -#define PACKET3_COPY_DATA_RB 0x96 #define PACKET3_INVALIDATE_TLBS 0x98 #define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) #define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) #define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) #define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) -#define PACKET3_AQL_PACKET 0x99 #define PACKET3_DMA_DATA_FILL_MULTI 0x9A #define PACKET3_SET_SH_REG_INDEX 0x9B -#define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C -#define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D -#define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E #define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F #define PACKET3_SET_RESOURCES 0xA0 /* 1. header @@ -394,7 +381,6 @@ # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) -#define PACKET3_MAP_PROCESS 0xA1 #define PACKET3_MAP_QUEUES 0xA2 /* 1. header * 2. CONTROL @@ -411,11 +397,10 @@ # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) -# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) +# define PACKET3_MAP_QUEUES_QUEUE_GROUP(x) ((x) << 24) # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) /* CONTROL2 */ -# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) #define PACKET3_UNMAP_QUEUES 0xA3 /* 1. header @@ -464,12 +449,6 @@ # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) /* CONTROL2b */ # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) -# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) -#define PACKET3_RUN_LIST 0xA5 -#define PACKET3_MAP_PROCESS_VM 0xA6 -/* GFX11 */ -#define PACKET3_SET_Q_PREEMPTION_MODE 0xF0 -# define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) -# define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0) +# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 28) #endif From 0cbe1a46c85ffb9a43d3504d0b0ce6265140d61b Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 28 Jan 2026 10:54:10 -0500 Subject: [PATCH 1843/2070] drm/amdkfd: Don't expect signal mailbox update GFX12.1 CP to improve performance has removed updating event_id into signal mailbox. In future, this optimization can be extended to older ASICs. Update driver code to handle this case. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 12 ++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_events.h | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- 8 files changed, 26 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c index 73acbe0b7c212..b799c70f5742a 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c @@ -97,11 +97,11 @@ static void cik_event_interrupt_wq(struct kfd_node *dev, return; if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id, 28); + kfd_signal_event_interrupt(pasid, context_id, 28, true); else if (ihre->source_id == CIK_INTSRC_SDMA_TRAP) - kfd_signal_event_interrupt(pasid, context_id, 28); + kfd_signal_event_interrupt(pasid, context_id, 28, true); else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG) - kfd_signal_event_interrupt(pasid, context_id & 0xff, 8); + kfd_signal_event_interrupt(pasid, context_id & 0xff, 8, true); else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE) kfd_signal_hw_exception_event(pasid); else if (ihre->source_id == CIK_INTSRC_GFX_PAGE_INV_FAULT || diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 13416bff77636..ee70eb4b63193 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -142,6 +142,7 @@ static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id) * @p: Pointer to struct kfd_process * @id: ID to look up * @bits: Number of valid bits in @id + * @signal_mailbox_updated: flag indicates if FW updates signal mailbox entry * * Finds the first signaled event with a matching partial ID. If no * matching signaled event is found, returns NULL. In that case the @@ -155,7 +156,8 @@ static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id) * driver. */ static struct kfd_event *lookup_signaled_event_by_partial_id( - struct kfd_process *p, uint32_t id, uint32_t bits) + struct kfd_process *p, uint32_t id, uint32_t bits, + bool signal_mailbox_updated) { struct kfd_event *ev; @@ -166,7 +168,8 @@ static struct kfd_event *lookup_signaled_event_by_partial_id( * and we only need a single lookup. */ if (bits > 31 || (1U << bits) >= KFD_SIGNAL_EVENT_LIMIT) { - if (page_slots(p->signal_page)[id] == UNSIGNALED_EVENT_SLOT) + if (signal_mailbox_updated && + page_slots(p->signal_page)[id] == UNSIGNALED_EVENT_SLOT) return NULL; return idr_find(&p->event_idr, id); @@ -724,7 +727,7 @@ static void set_event_from_interrupt(struct kfd_process *p, } void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, - uint32_t valid_id_bits) + uint32_t valid_id_bits, bool signal_mailbox_updated) { struct kfd_event *ev = NULL; @@ -742,7 +745,8 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, if (valid_id_bits) ev = lookup_signaled_event_by_partial_id(p, partial_id, - valid_id_bits); + valid_id_bits, + signal_mailbox_updated); if (ev) { set_event_from_interrupt(p, ev); } else if (p->signal_page) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_events.h index 52ccfd397c2b3..1dc21c13833b7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.h @@ -85,6 +85,7 @@ struct kfd_event { #define KFD_EVENT_TYPE_MEMORY 8 extern void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, - uint32_t valid_id_bits); + uint32_t valid_id_bits, + bool signal_mailbox_updated); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c index 3e1ad89747979..19406ab92c5bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c @@ -211,7 +211,7 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SE2SH || client_id == SOC15_IH_CLIENTID_SE3SH) { if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, true); else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { encoding = REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING); @@ -324,7 +324,7 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23); + kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23, true); } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { kfd_set_dbg_ev_from_interrupt(dev, pasid, @@ -344,7 +344,7 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SDMA6 || client_id == SOC15_IH_CLIENTID_SDMA7) { if (source_id == SOC15_INTSRC_SDMA_TRAP) { - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); } } else if (client_id == SOC15_IH_CLIENTID_VMC || client_id == SOC15_IH_CLIENTID_VMC1 || diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c index 2788a52714d10..12d81abed7481 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c @@ -353,7 +353,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, /* CP */ if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, true); else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) { u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0); @@ -366,7 +366,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, /* SDMA */ else if (source_id == SOC21_INTSRC_SDMA_TRAP) - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); else if (source_id == SOC21_INTSRC_SDMA_ECC) { event_interrupt_poison_consumption_v11(dev, pasid, source_id); return; @@ -404,7 +404,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); + kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24, true); } } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c index 230e57dbcec58..5d8b5aa194da8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c @@ -326,7 +326,7 @@ static void event_interrupt_wq_v12_1(struct kfd_node *node, /* CP */ if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, false); else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) { u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0); @@ -339,7 +339,7 @@ static void event_interrupt_wq_v12_1(struct kfd_node *node, /* SDMA */ else if (source_id == SOC21_INTSRC_SDMA_TRAP) - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); else if (source_id == SOC21_INTSRC_SDMA_ECC) { event_interrupt_poison_consumption_v12_1(node, pasid, source_id); return; @@ -377,7 +377,7 @@ static void event_interrupt_wq_v12_1(struct kfd_node *node, default: break; } - kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); + kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24, true); } } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index d76fb61869c75..1688d8e595f2f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -379,7 +379,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SE2SH || client_id == SOC15_IH_CLIENTID_SE3SH) { if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, true); else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); @@ -513,7 +513,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, sq_int_data, 24); + kfd_signal_event_interrupt(pasid, sq_int_data, 24, true); } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { kfd_set_dbg_ev_from_interrupt(dev, pasid, @@ -530,7 +530,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SDMA6 || client_id == SOC15_IH_CLIENTID_SDMA7) { if (source_id == SOC15_INTSRC_SDMA_TRAP) { - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); } else if (source_id == SOC15_INTSRC_SDMA_ECC) { event_interrupt_poison_consumption_v9(dev, pasid, client_id); return; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6337848ef1824..8014cfec32d75 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1685,7 +1685,7 @@ int kfd_wait_on_events(struct kfd_process *p, bool all, uint32_t *user_timeout_ms, uint32_t *wait_result); void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, - uint32_t valid_id_bits); + uint32_t valid_id_bits, bool signal_mailbox_updated); void kfd_signal_hw_exception_event(u32 pasid); int kfd_set_event(struct kfd_process *p, uint32_t event_id); int kfd_reset_event(struct kfd_process *p, uint32_t event_id); From 6011bf36cc3a7bf09e13928278264afca9e9b749 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Thu, 29 Jan 2026 14:17:22 -0500 Subject: [PATCH 1844/2070] drm/amdgpu: Update MTYPE for GFX12.1 Update MTYPE for GFX12.1 for AID A0 and A1 Signed-off-by: Harish Kasiviswanathan Reviewed-by: Philip.Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 15 ++++++------ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 32 +++++++++++++++----------- 2 files changed, 26 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index c49112d8300e2..6015c09d72076 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -524,13 +524,16 @@ static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; - unsigned int mtype, mtype_local; + unsigned int mtype, mtype_local, mtype_remote; bool snoop = false; bool is_local = false; switch (gc_ip_version) { - case IP_VERSION(12, 1, 0): - mtype_local = MTYPE_RW; + case IP_VERSION(12, 1, 0): { + bool is_aid_a1 = (adev->rev_id & 0x10); + + mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC; + mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC; if (amdgpu_mtype_local == 1) { DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); mtype_local = MTYPE_NC; @@ -547,12 +550,10 @@ static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, } else if (ext_coherent) { mtype = is_local ? mtype_local : MTYPE_UC; } else { - if (is_local) - mtype = mtype_local; - else - mtype = MTYPE_NC; + mtype = is_local ? mtype_local : mtype_remote; } break; + } default: if (uncached || coherent) mtype = MTYPE_UC; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5d3cf3757b13e..d054573088fa8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1223,7 +1223,7 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN); bool coherent = flags & (KFD_IOCTL_SVM_FLAG_COHERENT | KFD_IOCTL_SVM_FLAG_EXT_COHERENT); bool ext_coherent = flags & KFD_IOCTL_SVM_FLAG_EXT_COHERENT; - unsigned int mtype_local; + unsigned int mtype_local, mtype_remote; if (domain == SVM_RANGE_VRAM_DOMAIN) bo_node = prange->svm_bo->node; @@ -1310,23 +1310,27 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, case IP_VERSION(12, 0, 1): mapping_flags |= AMDGPU_VM_MTYPE_NC; break; - case IP_VERSION(12, 1, 0): + case IP_VERSION(12, 1, 0): { + bool is_aid_a1 = (node->adev->rev_id & 0x10); + bool is_local = (domain == SVM_RANGE_VRAM_DOMAIN) && + (bo_node->adev == node->adev); + + mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : + is_aid_a1 ? + AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC; + mtype_remote = is_aid_a1 ? AMDGPU_VM_MTYPE_NC : AMDGPU_VM_MTYPE_UC; snoop = true; - if (domain == SVM_RANGE_VRAM_DOMAIN) { - mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : - AMDGPU_VM_MTYPE_RW; - /* local HBM */ - if (bo_node->adev == node->adev) - mapping_flags |= mtype_local; - /* Remote GPU memory */ - else - mapping_flags |= ext_coherent ? AMDGPU_VM_MTYPE_UC : - AMDGPU_VM_MTYPE_NC; - /* system memory accessed by the dGPU */ + + if (is_local) /* local HBM */ { + mapping_flags |= mtype_local; + } else if (ext_coherent) { + mapping_flags |= AMDGPU_VM_MTYPE_UC; } else { - mapping_flags |= ext_coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; + /* system memory or remote VRAM */ + mapping_flags |= mtype_remote; } break; + } default: mapping_flags |= coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; From 1c4c05b9e4572861e02e30dfeab4a758561cd818 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Sat, 14 Feb 2026 18:28:28 -0500 Subject: [PATCH 1845/2070] drm/amdgpu: Support forcing MTYPE_RW Set default value of module parameter amdgpu_mtype_local to -1. This allows to force MTYPE_RW on ASICs where MTYPE_RW is not default. v2: Fix SDMA get_vm_pte_pde MTYPE Signed-off-by: Harish Kasiviswanathan Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 9 ++++++--- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 21 +++++++++++++++------ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 +++--- 4 files changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index cea3da3bd7728..66772f01c28f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -863,8 +863,8 @@ MODULE_PARM_DESC(keep_idle_process_evicted, "Restore evicted process only if que /** * DOC: mtype_local (int) */ -int amdgpu_mtype_local; -MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); +int amdgpu_mtype_local = -1; +MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)"); module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); /** diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index 6015c09d72076..6023492407cfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -534,13 +534,16 @@ static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC; mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC; - if (amdgpu_mtype_local == 1) { + if (amdgpu_mtype_local == 0) { + DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); + mtype_local = MTYPE_RW; + } else if (amdgpu_mtype_local == 1) { DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); mtype_local = MTYPE_NC; } else if (amdgpu_mtype_local == 2) { - DRM_INFO_ONCE("MTYPE_CC not supported, using MTYPE_RW instead for local memory\n"); + DRM_INFO_ONCE("MTYPE_CC not supported, using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC"); } else { - DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); + DRM_INFO_ONCE("Using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC"); } is_local = (is_vram && adev == bo_adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 03bf1f86098f1..f20e0fc3fc743 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1129,12 +1129,21 @@ static void sdma_v7_1_vm_set_pte_pde(struct amdgpu_ib *ib, /* for physically contiguous pages (vram) */ u32 header = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); - if (amdgpu_mtype_local) - header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3); - else - header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2) | - SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) | - SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3)); + /* TODO: + * When VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is enabled, change below MTYPE + * to RW for AID A1 and UC for AID A0. NC needs additional GCR flush and need not + * be supported. Also, honour amdgpu_mtype_local override. RW would additionally + * require setting SCOPE bits in the header. + * + * header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2:RW) | + * SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) | + * SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3:SYS_SCOPE)); + */ + + /* VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is 0 which defaults to UC. So, + * use MTYPE_UC (0x3). For ref. MTYPE_RW=0x2 MTYPE_NC=0x0 + */ + header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3) | SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1); ib->ptr[ib->length_dw++] = header; ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index d054573088fa8..dc93ffb74647d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1315,9 +1315,9 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, bool is_local = (domain == SVM_RANGE_VRAM_DOMAIN) && (bo_node->adev == node->adev); - mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : - is_aid_a1 ? - AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC; + mtype_local = amdgpu_mtype_local == 0 ? AMDGPU_VM_MTYPE_RW : + amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : + is_aid_a1 ? AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC; mtype_remote = is_aid_a1 ? AMDGPU_VM_MTYPE_NC : AMDGPU_VM_MTYPE_UC; snoop = true; From ce9d815aa28bbdbeacd8f6859e219b5c7a0e43f6 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 16:01:20 +0800 Subject: [PATCH 1846/2070] drm/amdgpu: Limit physical transcation mode to A + A only Only enable page table walker to snoop CPU cache on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c index 4aa004ee2c4d9..6a6f1707cb53e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c @@ -325,10 +325,18 @@ static void gfxhub_v12_1_xcc_init_cache_regs(struct amdgpu_device *adev, WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL3, tmp); tmp = regGCVM_L2_CNTL4_DEFAULT; - tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, - VMC_TAP_PDE_REQUEST_PHYSICAL, 1); - tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, - VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + if (adev->gmc.xgmi.connected_to_cpu) { + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } + WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL4, tmp); tmp = regGCVM_L2_CNTL5_DEFAULT; From 0ff627f305b4fb807bf2449b8833c677bf280ea9 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 16:33:40 +0800 Subject: [PATCH 1847/2070] drm/amdgpu: Place gart and vram in sysvm aper for A + A On A + A platform, sysvm aperture is used for both vram and gart access. In sysvm aperture, vram starts at 0, and gart starts right after vram. Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index da4a0cf4aad0c..a68a398afebec 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -691,12 +691,15 @@ static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); - amdgpu_gmc_vram_location(adev, &adev->gmc, base); - amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); - if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) - amdgpu_gmc_agp_location(adev, mc); - + if (amdgpu_gmc_is_pdb0_enabled(adev)) { + amdgpu_gmc_sysvm_location(adev, mc); + } else { + amdgpu_gmc_set_agp_default(adev, mc); + amdgpu_gmc_vram_location(adev, &adev->gmc, base); + amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); + if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) + amdgpu_gmc_agp_location(adev, mc); + } /* base offset of vram pages */ if (amdgpu_sriov_vf(adev)) adev->vm_manager.vram_base_offset = 0; From b66aac74e645121ed0e0e0172d64f63ac2352980 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 16:54:52 +0800 Subject: [PATCH 1848/2070] drm/amdgpu: Init table depth and block_size for A + A Initialize page table depth and page table block size for 2-level gart table construction on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index a68a398afebec..f5a328bb421db 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -765,6 +765,14 @@ static int gmc_v12_0_gart_init(struct amdgpu_device *adev) return 0; } + if (amdgpu_gmc_is_pdb0_enabled(adev)) { + adev->gmc.vmid0_page_table_depth = 1; + adev->gmc.vmid0_page_table_block_size = 12; + } else { + adev->gmc.vmid0_page_table_depth = 0; + adev->gmc.vmid0_page_table_block_size = 0; + } + /* Initialize common gart structure */ r = amdgpu_gart_init(adev); if (r) From 23c3e10d86cf642230f584496a19113268549384 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 17:18:10 +0800 Subject: [PATCH 1849/2070] drm/amdgpu/gmc12: Set up pdb0 for vmid0 page table Alloc, Init and free pdb0 for vmid0 page table that is used for fb translation on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index f5a328bb421db..654c1c7adfae4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -783,7 +783,14 @@ static int gmc_v12_0_gart_init(struct amdgpu_device *adev) AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_IS_PTE; - return amdgpu_gart_table_vram_alloc(adev); + r = amdgpu_gart_table_vram_alloc(adev); + if (r) + return r; + + if (amdgpu_gmc_is_pdb0_enabled(adev)) + r = amdgpu_gmc_pdb0_alloc(adev); + + return r; } static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) @@ -955,6 +962,7 @@ static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vm_manager_fini(adev); gmc_v12_0_gart_fini(adev); amdgpu_gem_force_release(adev); + amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); amdgpu_bo_fini(adev); return 0; @@ -974,6 +982,9 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) int r; bool value; + if (adev->gmc.xgmi.connected_to_cpu) + amdgpu_gmc_init_pdb0(adev); + if (adev->gart.bo == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; @@ -995,6 +1006,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned)(adev->gmc.gart_size >> 20), + (adev->gmc.pdb0_bo) ? (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo) : (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); return 0; From aa67fd4ec815224ea77f6f1309fd179a18722e9b Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 18:31:50 +0800 Subject: [PATCH 1850/2070] drm/amdgpu: Correct mmhub system aperture settings for A + A Disable AGP and FB apeture on all available MMHUB instances when vmid0 page table is enabled Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 135 +++++++++++----------- 1 file changed, 68 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index a72770e3d0e99..60bba87e42a01 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -131,7 +131,7 @@ static void mmhub_v4_2_0_setup_vm_pt_regs(struct amdgpu_device *adev, static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, uint32_t mid_mask) { - uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + uint64_t pt_base; int i; if (adev->gmc.pdb0_bo) @@ -190,41 +190,74 @@ static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *ade return; for_each_inst(i, mid_mask) { - /* Program the AGP BAR */ - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_BASE_LO32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_BASE_HI32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_BOT_LO32, - lower_32_bits(adev->gmc.agp_start >> 24)); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_BOT_HI32, - upper_32_bits(adev->gmc.agp_start >> 24)); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_TOP_LO32, - lower_32_bits(adev->gmc.agp_end >> 24)); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_TOP_HI32, - upper_32_bits(adev->gmc.agp_end >> 24)); + if (adev->gmc.pdb0_bo) { + /* Disable agp and system aperture + * when vmid0 page table is enabled */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_TOP_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_TOP_HI32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_BASE_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_BASE_HI32, 1); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_HI32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_HI32, 1); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + 0x7F); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); + } else { + /* Program the AGP BAR */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BASE_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BASE_HI32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_LO32, + lower_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_HI32, + upper_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_LO32, + lower_32_bits(adev->gmc.agp_end >> 24)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_HI32, + upper_32_bits(adev->gmc.agp_end >> 24)); - /* Program the system aperture low logical page number. */ - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, - lower_32_bits(min(adev->gmc.fb_start, - adev->gmc.agp_start) >> 18)); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, - upper_32_bits(min(adev->gmc.fb_start, - adev->gmc.agp_start) >> 18)); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, - lower_32_bits(max(adev->gmc.fb_end, - adev->gmc.agp_end) >> 18)); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, - upper_32_bits(max(adev->gmc.fb_end, - adev->gmc.agp_end) >> 18)); + /* Program the system aperture low logical page number. */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + lower_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + upper_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, + lower_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, + upper_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + } /* Set default page address. */ value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); @@ -252,38 +285,6 @@ static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *ade WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); } - - /* In the case squeezing vram into GART aperture, we don't use - * FB aperture and AGP aperture. Disable them. - */ - if (adev->gmc.pdb0_bo) { - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_FB_LOCATION_TOP_LO32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_FB_LOCATION_TOP_HI32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_FB_LOCATION_BASE_LO32, 0xFFFFFFFF); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_FB_LOCATION_BASE_HI32, 1); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_TOP_LO32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_TOP_HI32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_BOT_LO32, 0xFFFFFFFF); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_AGP_BOT_HI32, 1); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, - 0xFFFFFFFF); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, - 0x7F); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); - WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), - regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); - } } static void mmhub_v4_2_0_mid_init_tlb_regs(struct amdgpu_device *adev, From e591e7cebebeb7c534e352ee67cffb9ef59673cb Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 18:36:37 +0800 Subject: [PATCH 1851/2070] drm/amdgpu: Update gfxhub system aperture settings for A + A Bypass the programming from SRIOV guest Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c | 135 ++++++++++++---------- 1 file changed, 71 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c index 6a6f1707cb53e..d086c23e4c2da 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c @@ -146,71 +146,15 @@ static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *ade uint32_t tmp; int i; - for_each_inst(i, xcc_mask) { - /* Program the AGP BAR */ - WREG32_SOC15_RLC(GC, GET_INST(GC, i), - regGCMC_VM_AGP_BASE_LO32, 0); - WREG32_SOC15_RLC(GC, GET_INST(GC, i), - regGCMC_VM_AGP_BASE_HI32, 0); - WREG32_SOC15_RLC(GC, GET_INST(GC, i), - regGCMC_VM_AGP_BOT_LO32, - lower_32_bits(adev->gmc.agp_start >> 24)); - WREG32_SOC15_RLC(GC, GET_INST(GC, i), - regGCMC_VM_AGP_BOT_HI32, - upper_32_bits(adev->gmc.agp_start >> 24)); - WREG32_SOC15_RLC(GC, GET_INST(GC, i), - regGCMC_VM_AGP_TOP_LO32, - lower_32_bits(adev->gmc.agp_end >> 24)); - WREG32_SOC15_RLC(GC, GET_INST(GC, i), - regGCMC_VM_AGP_TOP_HI32, - upper_32_bits(adev->gmc.agp_end >> 24)); - - if (!amdgpu_sriov_vf(adev)) { - /* Program the system aperture low logical page number. */ - WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, - lower_32_bits(min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18)); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, - upper_32_bits(min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18)); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, - lower_32_bits(max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18)); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, - upper_32_bits(max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18)); - - /* Set default page address. */ - value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, - (u32)(value >> 12)); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, - (u32)(value >> 44)); - - /* Program "protection fault". */ - WREG32_SOC15(GC, GET_INST(GC, i), - regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, - (u32)(adev->dummy_page_addr >> 12)); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, - (u32)((u64)adev->dummy_page_addr >> 44)); - - tmp = RREG32_SOC15(GC, GET_INST(GC, i), - regGCVM_L2_PROTECTION_FAULT_CNTL2); - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); - tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, - ENABLE_RETRY_FAULT_INTERRUPT, 0x1); - WREG32_SOC15(GC, GET_INST(GC, i), - regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); - } + /*TODO: revisit whether the SRIOV guest access to theseregisters + * is blocked by security policy or not */ + if (amdgpu_sriov_vf(adev)) + return; - /* In the case squeezing vram into GART aperture, we don't use - * FB aperture and AGP aperture. Disable them. - */ + for_each_inst(i, xcc_mask) { if (adev->gmc.pdb0_bo) { + /* Disable agp and system aperture + * when vmid0 page table is enabled */ WREG32_SOC15(GC, GET_INST(GC, i), regGCMC_VM_FB_LOCATION_TOP_LO32, 0); WREG32_SOC15(GC, GET_INST(GC, i), @@ -225,7 +169,8 @@ static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *ade WREG32_SOC15(GC, GET_INST(GC, i), regGCMC_VM_AGP_TOP_HI32, 0); WREG32_SOC15(GC, GET_INST(GC, i), - regGCMC_VM_AGP_BOT_LO32, 0xFFFFFFFF); + regGCMC_VM_AGP_BOT_LO32, + 0xFFFFFFFF); WREG32_SOC15(GC, GET_INST(GC, i), regGCMC_VM_AGP_BOT_HI32, 1); WREG32_SOC15(GC, GET_INST(GC, i), @@ -238,7 +183,69 @@ static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *ade regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); WREG32_SOC15(GC, GET_INST(GC, i), regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); + } else { + /* Program the AGP BAR */ + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BASE_LO32, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BASE_HI32, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BOT_LO32, + lower_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BOT_HI32, + upper_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_TOP_LO32, + lower_32_bits(adev->gmc.agp_end >> 24)); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_TOP_HI32, + upper_32_bits(adev->gmc.agp_end >> 24)); + + /* Program the system aperture low logical page number. */ + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + lower_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + upper_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, + lower_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, + upper_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); } + + /* Set default page address. */ + value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page_addr >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page_addr >> 44)); + + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL2); + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, + ENABLE_RETRY_FAULT_INTERRUPT, 0x1); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); } } From 97c60f37c4746babbfbb68a125613b49a2e74e00 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 19:25:56 +0800 Subject: [PATCH 1852/2070] drm/amdgpu/gmc12: Bypass FB resize on A + A platform Resizing fb bar is not needed/supported on A + A platform. Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 654c1c7adfae4..2bbd63ffe7105 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -725,7 +725,8 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; adev->gmc.real_vram_size = adev->gmc.mc_vram_size; - if (!(adev->flags & AMD_IS_APU)) { + if (!(adev->flags & AMD_IS_APU) && + !adev->gmc.xgmi.connected_to_cpu) { r = amdgpu_device_resize_fb_bar(adev); if (r) return r; From d5ffcf6f2bd991e15604a7f54426222aaaaf877b Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 19:47:09 +0800 Subject: [PATCH 1853/2070] drm/amdgpu/gmc12: Update gmc aperture base for A + A Query mmhub MC_VM_FB_OFFSET, XGMI_LFB_CNTL|SIZE registers to calculate gmc apeture base address for A + A configuration Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 2bbd63ffe7105..ac0536be0f90c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -736,8 +736,12 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); #ifdef CONFIG_X86_64 - if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { - adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); + if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || + (adev->gmc.xgmi.connected_to_cpu)) { + adev->gmc.aper_base = + adev->mmhub.funcs->get_mc_fb_offset(adev) + + adev->gmc.xgmi.physical_node_id * + adev->gmc.xgmi.node_segment_size; adev->gmc.aper_size = adev->gmc.real_vram_size; } #endif From 128f5e68fe120a5395c7cef2d41b64ebd07c620d Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 20:25:36 +0800 Subject: [PATCH 1854/2070] drm/amdgpu: Implement get_xgmi_info callback for mmhub_v4_2 Query memory region assignment and address via mmhub Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 + drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 40 +++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h index 1ca9d4ed8063a..92918101a95d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h @@ -63,6 +63,7 @@ struct amdgpu_mmhub_funcs { uint64_t page_table_base); void (*update_power_gating)(struct amdgpu_device *adev, bool enable); + int (*get_xgmi_info)(struct amdgpu_device *adev); }; struct amdgpu_mmhub { diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index 60bba87e42a01..b025c1fdc52c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -72,6 +72,45 @@ static const char *mmhub_client_ids_v4_2_0[][2] = { [23][1] = "VCN1", }; +static int mmhub_v4_2_0_get_xgmi_info(struct amdgpu_device *adev) +{ + u32 max_num_physical_nodes; + u32 max_physical_node_id; + u32 xgmi_lfb_cntl; + u32 max_region; + u64 seg_size; + + /* limit this callback to A + A configuration only */ + if (!adev->gmc.xgmi.connected_to_cpu) + return 0; + + xgmi_lfb_cntl = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), + regMMMC_VM_XGMI_LFB_CNTL); + seg_size = REG_GET_FIELD( + RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMMMC_VM_XGMI_LFB_SIZE), + MMMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; + max_region = + REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); + + max_num_physical_nodes = 4; + max_physical_node_id = 3; + + adev->gmc.xgmi.num_physical_nodes = max_region + 1; + + if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) + return -EINVAL; + + adev->gmc.xgmi.physical_node_id = + REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); + + if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) + return -EINVAL; + + adev->gmc.xgmi.node_segment_size = seg_size; + + return 0; +} + static u64 mmhub_v4_2_0_get_fb_location(struct amdgpu_device *adev) { u64 base; @@ -884,6 +923,7 @@ const struct amdgpu_mmhub_funcs mmhub_v4_2_0_funcs = { .set_fault_enable_default = mmhub_v4_2_0_set_fault_enable_default, .set_clockgating = mmhub_v4_2_0_set_clockgating, .get_clockgating = mmhub_v4_2_0_get_clockgating, + .get_xgmi_info = mmhub_v4_2_0_get_xgmi_info, }; static int mmhub_v4_2_0_xcp_resume(void *handle, uint32_t inst_mask) From 1c502a6ac0c220084884bbe350021ea8701e1259 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 20:33:06 +0800 Subject: [PATCH 1855/2070] drm/amdgpu: Query xgmi info from mmhub if available Query xgmi info from mmhub if available Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9f18365048ec2..71018e09e55c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3920,9 +3920,21 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_gmc_noretry_set(adev); /* Need to get xgmi info early to decide the reset behavior*/ if (adev->gmc.xgmi.supported) { - r = adev->gfxhub.funcs->get_xgmi_info(adev); - if (r) - return r; + if (adev->gfxhub.funcs && + adev->gfxhub.funcs->get_xgmi_info) { + r = adev->gfxhub.funcs->get_xgmi_info(adev); + if (r) + return r; + } + } + + if (adev->gmc.xgmi.connected_to_cpu) { + if (adev->mmhub.funcs && + adev->mmhub.funcs->get_xgmi_info) { + r = adev->mmhub.funcs->get_xgmi_info(adev); + if (r) + return r; + } } /* enable PCIE atomic ops */ From 437432c3d713443d924f79331626de45b1848700 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 20:34:44 +0800 Subject: [PATCH 1856/2070] drm/amdgpu: Retire get_xgmi_info callback for gfxhub v12_1 gfxhub v12_1 is not always on. querying xgmi info from it may not work consistently Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c | 42 ----------------------- 1 file changed, 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c index d086c23e4c2da..3544eb42dca60 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c @@ -822,47 +822,6 @@ static void gfxhub_v12_1_init(struct amdgpu_device *adev) gfxhub_v12_1_xcc_init(adev, xcc_mask); } -static int gfxhub_v12_1_get_xgmi_info(struct amdgpu_device *adev) -{ - u32 max_num_physical_nodes; - u32 max_physical_node_id; - u32 xgmi_lfb_cntl; - u32 max_region; - u64 seg_size; - - xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), - regGCMC_VM_XGMI_LFB_CNTL); - seg_size = REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, 0), - regGCMC_VM_XGMI_LFB_SIZE), - GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; - max_region = REG_GET_FIELD(xgmi_lfb_cntl, - GCMC_VM_XGMI_LFB_CNTL, - PF_MAX_REGION); - - max_num_physical_nodes = 8; - max_physical_node_id = 7; - - /* PF_MAX_REGION=0 means xgmi is disabled */ - if (max_region || adev->gmc.xgmi.connected_to_cpu) { - adev->gmc.xgmi.num_physical_nodes = max_region + 1; - - if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) - return -EINVAL; - - adev->gmc.xgmi.physical_node_id = - REG_GET_FIELD(xgmi_lfb_cntl, - GCMC_VM_XGMI_LFB_CNTL, - PF_LFB_REGION); - - if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) - return -EINVAL; - - adev->gmc.xgmi.node_segment_size = seg_size; - } - - return 0; -} - const struct amdgpu_gfxhub_funcs gfxhub_v12_1_funcs = { .get_fb_location = gfxhub_v12_1_get_fb_location, .get_mc_fb_offset = gfxhub_v12_1_get_mc_fb_offset, @@ -871,7 +830,6 @@ const struct amdgpu_gfxhub_funcs gfxhub_v12_1_funcs = { .gart_disable = gfxhub_v12_1_gart_disable, .set_fault_enable_default = gfxhub_v12_1_set_fault_enable_default, .init = gfxhub_v12_1_init, - .get_xgmi_info = gfxhub_v12_1_get_xgmi_info, }; static int gfxhub_v12_1_xcp_resume(void *handle, uint32_t inst_mask) From 7e6336368f53b3deb6d900fc807baffe340a5d71 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sat, 17 Jan 2026 19:18:06 +0800 Subject: [PATCH 1857/2070] drm/amdgpu/gmc12: Query host-gpu interface Query host-gpu interconnect type for gmc v12 devices Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index ac0536be0f90c..0e47268100ff9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -636,6 +636,10 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + if (adev->smuio.funcs && + adev->smuio.funcs->is_host_gpu_xgmi_supported) + adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 1, 0): gmc_v12_1_set_gmc_funcs(adev); From 772f1c801a24f41d5cd2d28dcff3ee0e337979fe Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Wed, 21 Jan 2026 00:12:36 +0800 Subject: [PATCH 1858/2070] drm/amdgpu/gmc12: Fix VRAM base offset calculation Include segment size when calculating vram base offset Signed-off-by: Hawking Zhang Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 0e47268100ff9..75bff46ca5946 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -709,6 +709,9 @@ static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, adev->vm_manager.vram_base_offset = 0; else adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); + + adev->vm_manager.vram_base_offset += + adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; } /** From 3e9be8942e8bac841adbeec62b449e540c3b35af Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 27 Jan 2026 16:07:19 +0800 Subject: [PATCH 1859/2070] drm/amdgpu/gmc12: Update connected_to_cpu flag MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Query the host–GPU interface in gmc early init phase and set xgmi.connected_to_cpu accordingly Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 75bff46ca5946..2b5f01f15fac3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -638,7 +638,8 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) if (adev->smuio.funcs && adev->smuio.funcs->is_host_gpu_xgmi_supported) - adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); + adev->gmc.xgmi.connected_to_cpu = + adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 1, 0): From 0c3495b20b68fdd4fc662f3953c58831f20ae4c2 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Wed, 28 Jan 2026 19:18:28 +0800 Subject: [PATCH 1860/2070] drm/amdgpu/gmc12: Init vram_size for A + A Calculate vram_size using the XGMI node segment size and node count for A+A configurations Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 2b5f01f15fac3..ac39011d1268c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -728,9 +728,13 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) { int r; - /* size in MB on si */ - adev->gmc.mc_vram_size = - adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; + if (adev->gmc.xgmi.connected_to_cpu) + adev->gmc.mc_vram_size = + adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; + else + adev->gmc.mc_vram_size = + adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; + adev->gmc.real_vram_size = adev->gmc.mc_vram_size; if (!(adev->flags & AMD_IS_APU) && From 45d1a7e4245002b0681e23acd78df71259d3a06b Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Sat, 31 Jan 2026 13:07:39 +0800 Subject: [PATCH 1861/2070] drm/amdgpu/mmhub_v4_2_0: expand gart aperture to gart_end on A+A On A+A, sysvm aperture is used to access vram and gart. Gart is placed right after vram. Adjust gart aperture range in mmhub for A+A. Signed-off-by: Feifei Xu Signed-off-by: Jack Xiao Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index b025c1fdc52c3..97a00075aa7aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -191,10 +191,10 @@ static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, - (u32)(adev->gmc.fb_end >> 12)); + (u32)(adev->gmc.gart_end >> 12)); WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, - (u32)(adev->gmc.fb_end >> 44)); + (u32)(adev->gmc.gart_end >> 44)); } else { WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, From e64901b4732cef5f8c8960491702b409f2b7d7ac Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 10 Feb 2026 04:35:24 +0800 Subject: [PATCH 1862/2070] drm/amdgpu: Place firmware bo in vram for A + A On A+A platforms, PSP requires the firmware bo to be located in VRAM Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 82333aeb44530..6d9e96fabd581 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -1150,7 +1150,7 @@ int amdgpu_ucode_create_bo(struct amdgpu_device *adev) if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, - (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? + (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, &adev->firmware.fw_buf, &adev->firmware.fw_buf_mc, From cd0505b03545244d6658358d8afb4b6bddf14b92 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 8 Dec 2025 16:28:49 +0800 Subject: [PATCH 1863/2070] drm/amd/ras: Add unified interface to handle ras interrupts Add unified interface to handle ras interrupts, some redundant interrupt function interfaces will be removed later. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 31 +++++++++++++++++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 1 + 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index 4fc29e548ecbe..861b1f2904754 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -535,6 +535,37 @@ int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void return ret; } +int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + uint64_t seq_no = 0; + int ret = 0; + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + if (!ih_info) + return 0; + + if (ih_info->block == RAS_BLOCK_ID__UMC) { + if (ras_mgr->ras_core->poison_supported) { + seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_DE); + RAS_DEV_INFO(adev, + "{%llu} RAS poison is created, no user action is needed.\n", + seq_no); + } + + ret = amdgpu_ras_process_handle_umc_interrupt(adev, ih_info); + } else if (ras_mgr->ras_core->poison_supported) { + ret = amdgpu_ras_process_handle_consumption_interrupt(adev, ih_info); + } else { + RAS_DEV_WARN(adev, + "No RAS interrupt handler for non-UMC block with poison disabled.\n"); + } + + return ret; +} + int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data) { if (!amdgpu_ras_mgr_is_ready(adev)) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h index 23c411c982319..4f44a917d48be 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -67,6 +67,7 @@ bool amdgpu_uniras_enabled(struct amdgpu_device *adev); int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data); +int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info); int amdgpu_ras_mgr_update_ras_ecc(struct amdgpu_device *adev); int amdgpu_ras_mgr_reset_gpu(struct amdgpu_device *adev, uint32_t flags); uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev, From 6edc45145c0b2b6db422df7062f56297f3b0bfad Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 8 Dec 2025 16:23:10 +0800 Subject: [PATCH 1864/2070] drm/amdgpu: Add umc ecc error handling for gmc v12_1 Add umc ecc error handling for gmc v12_1. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 11 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 10 +++++++--- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 7 +++++++ 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index 3f0b0e9af4f34..1be722ba6c9ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -398,6 +398,17 @@ int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, return 0; } +int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct ras_ih_info ih_info = {0}; + + ih_info.block = RAS_BLOCK_ID__UMC; + amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); + return 0; +} + int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, uint64_t err_addr, uint64_t retired_page, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h index 28dff750c47e3..8494a55ebf76c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h @@ -161,6 +161,9 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); +int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry); int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, uint64_t err_addr, uint64_t retired_page, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index ac39011d1268c..f1079bd8cf001 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -893,11 +893,15 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) && - !amdgpu_sriov_vf(adev)) { + if (!amdgpu_sriov_vf(adev)) { /* interrupt sent to DF. */ - r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 0)) + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, + &adev->gmc.ecc_irq); + else + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_DF, 0, &adev->gmc.ecc_irq); + if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index 6023492407cfc..f117a09252edc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -625,10 +625,17 @@ static const struct amdgpu_irq_src_funcs gmc_v12_1_irq_funcs = { .process = gmc_v12_1_process_interrupt, }; +static const struct amdgpu_irq_src_funcs gmc_v12_1_ecc_funcs = { + .process = amdgpu_umc_uniras_process_ecc_irq, +}; + void gmc_v12_1_set_irq_funcs(struct amdgpu_device *adev) { adev->gmc.vm_fault.num_types = 1; adev->gmc.vm_fault.funcs = &gmc_v12_1_irq_funcs; + + adev->gmc.ecc_irq.num_types = 1; + adev->gmc.ecc_irq.funcs = &gmc_v12_1_ecc_funcs; } void gmc_v12_1_init_vram_info(struct amdgpu_device *adev) From a5d761f362e330985cf6521a390f59734b82316c Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 8 Dec 2025 16:50:53 +0800 Subject: [PATCH 1865/2070] drm/amdgpu: Add poison consumption handling for gfx v12_1 Add poison consumption handling for gfx v12_1. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 44 +++++++++++++++++++ .../drm/amd/amdkfd/kfd_int_process_v12_1.c | 12 ++++- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 5126134713ee1..67b590daccb39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -474,6 +474,7 @@ struct amdgpu_gfx { struct amdgpu_irq_src spm_irq; struct amdgpu_irq_src sq_irq; struct amdgpu_irq_src rlc_gc_fed_irq; + struct amdgpu_irq_src rlc_poison_irq; struct sq_work sq_work; /* gfx status */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 1a7ccfed8f0ac..db49582a211f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -45,6 +45,7 @@ #include "v12_structs.h" #include "gfx_v12_1.h" #include "mes_v12_1.h" +#include "amdgpu_ras_mgr.h" #define GFX12_MEC_HPD_SIZE 2048 #define NUM_SIMD_PER_CU_GFX12_1 4 @@ -1184,6 +1185,13 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + /* RLC POISON Error */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_RLC, + GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT, + &adev->gfx.rlc_poison_irq); + if (r) + return r; + adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; r = gfx_v12_1_rlc_init(adev); @@ -3778,6 +3786,35 @@ static int gfx_v12_1_priv_inst_irq(struct amdgpu_device *adev, return 0; } +static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t rlc_fed_status = 0; + uint32_t ras_blk = RAS_BLOCK_ID__GFX; + struct ras_ih_info ih_info = {0}; + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + rlc_fed_status |= RREG32(SOC15_REG_OFFSET(GC, + GET_INST(GC, i), regRLC_RLCS_FED_STATUS)); + + if (!rlc_fed_status) + return 0; + + if (REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA0_FED_ERR) || + REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA1_FED_ERR)) + ras_blk = RAS_BLOCK_ID__SDMA; + + dev_warn(adev->dev, "RLC %d FED IRQ\n", ras_blk); + + ih_info.block = ras_blk; + ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); + return 0; +} + static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) { const unsigned int gcr_cntl = @@ -3902,6 +3939,10 @@ static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_inst_irq_funcs = { .process = gfx_v12_1_priv_inst_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v12_1_rlc_poison_irq_funcs = { + .process = gfx_v12_1_rlc_poison_irq, +}; + static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; @@ -3912,6 +3953,9 @@ static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) adev->gfx.priv_inst_irq.num_types = 1; adev->gfx.priv_inst_irq.funcs = &gfx_v12_1_priv_inst_irq_funcs; + + adev->gfx.rlc_poison_irq.num_types = 1; + adev->gfx.rlc_poison_irq.funcs = &gfx_v12_1_rlc_poison_irq_funcs; } static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c index 5d8b5aa194da8..47947b94926ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c @@ -28,6 +28,7 @@ #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" #include "kfd_smi_events.h" #include "kfd_debug.h" +#include "amdgpu_ras_mgr.h" /* * GFX12.1 SQ Interrupts @@ -185,6 +186,7 @@ static void event_interrupt_poison_consumption_v12_1(struct kfd_node *node, enum amdgpu_ras_block block = 0; int ret = -EINVAL; uint32_t reset = 0; + u64 event_id = RAS_EVENT_INVALID_ID; struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL); if (!p) @@ -220,7 +222,15 @@ static void event_interrupt_poison_consumption_v12_1(struct kfd_node *node, * resetting queue passes, do page retirement without gpu reset * resetting queue fails, fallback to gpu reset solution */ - amdgpu_amdkfd_ras_poison_consumption_handler(node->adev, block, reset); + if (amdgpu_uniras_enabled(node->adev)) + event_id = amdgpu_ras_mgr_gen_ras_event_seqno(node->adev, + RAS_SEQNO_TYPE_POISON_CONSUMPTION); + + RAS_EVENT_LOG(node->adev, event_id, + "poison is consumed by source %d, kick off gpu reset flow\n", source_id); + + amdgpu_amdkfd_ras_pasid_poison_consumption_handler(node->adev, + block, pasid, NULL, NULL, reset); } static bool event_interrupt_isr_v12_1(struct kfd_node *node, From d6e28f15af9cc3867930224a506eea0ebb8d3108 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 13 Mar 2026 14:07:55 +0800 Subject: [PATCH 1866/2070] drm/amdkcl: fix miss include headers in m4 It's caused by the commit: 4cac08c8a "drm/amdkcl: test if drm_gem_dmabuf_vmap() has struct iosys_map arg" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index 6bc1bbb0b3346..b3732d2b30714 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -49,6 +49,7 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include + #include ],[ struct iosys_map map; drm_gem_dmabuf_vmap(NULL, &map); From 6b955bc359ce1c28a54abb571d9cba7bc03df20f Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 12 Mar 2026 18:06:17 +0800 Subject: [PATCH 1867/2070] drm/amdgpu: Limit BO list entry count to prevent resource exhaustion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Userspace can pass an arbitrary number of BO list entries via the bo_number field. Although the previous multiplication overflow check prevents out-of-bounds allocation, a large number of entries could still cause excessive memory allocation (up to potentially gigabytes) and unnecessarily long list processing times. Introduce a hard limit of 128k entries per BO list, which is more than sufficient for any realistic use case (e.g., a single list containing all buffers in a large scene). This prevents memory exhaustion attacks and ensures predictable performance. Return -EINVAL if the requested entry count exceeds the limit Reviewed-by: Christian König Suggested-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 87ec46c56a6ee..3270ea50bdc74 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -36,6 +36,7 @@ #define AMDGPU_BO_LIST_MAX_PRIORITY 32u #define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1) +#define AMDGPU_BO_LIST_MAX_ENTRIES (128 * 1024) static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu) { @@ -188,6 +189,9 @@ int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in, const uint32_t bo_number = in->bo_number; struct drm_amdgpu_bo_list_entry *info; + if (bo_number > AMDGPU_BO_LIST_MAX_ENTRIES) + return -EINVAL; + /* copy the handle array from userspace to a kernel buffer */ if (likely(info_size == bo_info_size)) { info = vmemdup_array_user(uptr, bo_number, info_size); From 6cd82dbf3bb7c2c718904426af9806943b9704a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 22 Jan 2026 15:27:25 +0100 Subject: [PATCH 1868/2070] drm/amdgpu: fix amdgpu_userq_evict MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Canceling the resume worker synchonized can deadlock because it can in turn wait for the eviction worker through the userq_mutex. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index c058e629cbd92..c54a692d64c84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1349,13 +1349,8 @@ amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, /* Signal current eviction fence */ amdgpu_eviction_fence_signal(evf_mgr, ev_fence); - if (evf_mgr->fd_closing) { - cancel_delayed_work_sync(&uq_mgr->resume_work); - return; - } - - /* Schedule a resume work */ - schedule_delayed_work(&uq_mgr->resume_work, 0); + if (!evf_mgr->fd_closing) + schedule_delayed_work(&uq_mgr->resume_work, 0); } int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, From f7f3c495931b644274d993510c7a10f8a71cac63 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 12 Mar 2026 15:26:16 +0800 Subject: [PATCH 1869/2070] drm/amd/pm: Add common smu fw check function Add common smu firmware version check function Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 29 ++++++++++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 92455b842dfb1..8638d25ee839f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1039,6 +1039,35 @@ int smu_cmn_get_smc_version(struct smu_context *smu, return ret; } +int smu_cmn_check_fw_version(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t if_version = 0xff, smu_version = 0xff; + uint8_t smu_program, smu_major, smu_minor, smu_debug; + int ret; + + ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); + if (ret) + return ret; + + smu_program = (smu_version >> 24) & 0xff; + smu_major = (smu_version >> 16) & 0xff; + smu_minor = (smu_version >> 8) & 0xff; + smu_debug = (smu_version >> 0) & 0xff; + adev->pm.fw_version = smu_version; + + dev_info_once(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " + "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", + smu->smc_driver_if_version, if_version, + smu_program, smu_version, smu_major, smu_minor, smu_debug); + + if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && + if_version != smu->smc_driver_if_version) + dev_info(adev->dev, "SMU driver if version not matched\n"); + + return 0; +} + int smu_cmn_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index b7bfddc65fb21..e4d282d8bcae3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -207,6 +207,7 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu, int smu_cmn_dpm_pcie_gen_idx(int gen); int smu_cmn_dpm_pcie_width_idx(int width); +int smu_cmn_check_fw_version(struct smu_context *smu); /*SMU gpu metrics */ From a59048e71ee6bf8cec048f33fae3152c45ffb1ac Mon Sep 17 00:00:00 2001 From: Calvin Owens Date: Thu, 12 Mar 2026 10:13:34 -0700 Subject: [PATCH 1870/2070] drm/amd/display: Fix uninitialized variable use which breaks full LTO Commit e1b385726f7f ("drm/amd/display: Add additional checks for PSP footer size") introduced a use of an uninitialized stack variable in dm_dmub_sw_init() (region_params.bss_data_size). Interestingly, this seems to cause no issue on normal kernels. But when full LTO is enabled, it causes the compiler to "optimize" out huge swaths of amdgpu initialization code, and the driver is unusable: amdgpu 0000:03:00.0: [drm] Loading DMUB firmware via PSP: version=0x07002F00 amdgpu 0000:03:00.0: sw_init of IP block failed 5 amdgpu 0000:03:00.0: amdgpu_device_ip_init failed amdgpu 0000:03:00.0: Fatal error during GPU init It surprises me that neither gcc nor clang emit a warning about this: I only found it by bisecting the LTO breakage. Fix by using the bss_data_size field from fw_meta_info_params, as was presumably intended. Fixes: e1b385726f7f ("drm/amd/display: Add additional checks for PSP footer size") Signed-off-by: Calvin Owens Reviewed-by: Harry Wentland Reviewed-by: Nathan Chancellor --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1950ec6d7edd1..17dd1e046a3de 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2610,7 +2610,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) fw_meta_info_params.fw_inst_const = adev->dm.dmub_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + PSP_HEADER_BYTES_256; - fw_meta_info_params.fw_bss_data = region_params.bss_data_size ? adev->dm.dmub_fw->data + + fw_meta_info_params.fw_bss_data = fw_meta_info_params.bss_data_size ? adev->dm.dmub_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + le32_to_cpu(hdr->inst_const_bytes) : NULL; fw_meta_info_params.custom_psp_footer_size = 0; From 1b9c19a6da025da812b4bb97d01c5f44fd7692b8 Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Fri, 6 Mar 2026 14:28:03 +0800 Subject: [PATCH 1871/2070] drm/amd/display: Wrap dcn32_override_min_req_memclk() in DC_FP_{START, END} [Why] The dcn32_override_min_req_memclk function is in dcn32_fpu.c, which is compiled with CC_FLAGS_FPU into FP instructions. So when we call it we must use DC_FP_{START,END} to save and restore the FP context, and prepare the FP unit on architectures like LoongArch where the FP unit isn't always on. Reported-by: LiarOnce Fixes: ee7be8f3de1c ("drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO") Cc: stable@vger.kernel.org Signed-off-by: Xi Ruoyao Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index a55078458ba54..368ef798be829 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1789,7 +1789,10 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_valid dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); + DC_FP_START(); dcn32_override_min_req_memclk(dc, context); + DC_FP_END(); + dcn32_override_min_req_dcfclk(dc, context); BW_VAL_TRACE_END_WATERMARKS(); From 7842f7cde4b6bd2e5d977ea0d2744d03a7f64d32 Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Mon, 2 Mar 2026 10:26:51 +0800 Subject: [PATCH 1872/2070] drm/amd/display: Add debugfs to disallow eDP Replay entry [Why & How] Test applications need to read CRC from eDP sink side, but sink replay feature prevents proper CRC reading and causing timeout. Add disallow_edp_enter_replay debugfs interface to allow test apps to temporarily disable Replay for CRC operations. Reviewed-by: Tom Chung Signed-off-by: Ray Wu Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index e918686a46937..ac576dd293fef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3320,6 +3320,52 @@ static int disallow_edp_enter_psr_set(void *data, u64 val) return 0; } +/* check if kernel disallow eDP enter replay state + * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay + * 0: allow edp enter replay; 1: disallow + */ +static int disallow_edp_enter_replay_get(void *data, u64 *val) +{ + struct amdgpu_dm_connector *aconnector = data; + + *val = (u64) aconnector->disallow_edp_enter_replay; + return 0; +} + +/* set kernel disallow eDP enter replay state + * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay + * 0: allow edp enter replay; 1: disallow + * + * usage: test app read crc from PSR eDP rx. + * + * during kernel boot up, kernel write dpcd 0x37b to + * notify eDP rx replay enable. + * rx fw will start checking crc for rx internal logic. + * crc read count within dpcd 0x246 is not updated and + * value is 0. when eDP tx driver wants to read rx crc + * from dpcd 0x246, 0x270, read count 0 lead tx driver + * timeout. + * + * to avoid this, we add this debugfs to let test app to disbable + * rx replay. then test app can read non-zero crc read count. + * + * expected app sequence is as below: + * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. + * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay + * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but + * without programming dpcd 0x37b. + * 4. read crc from rx dpcd 0x270, 0x246, etc. + * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay. + * this will let eDP back to normal with replay setup dpcd 0x37b. + */ +static int disallow_edp_enter_replay_set(void *data, u64 val) +{ + struct amdgpu_dm_connector *aconnector = data; + + aconnector->disallow_edp_enter_replay = val ? true : false; + return 0; +} + static int dmub_trace_mask_set(void *data, u64 val) { struct amdgpu_device *adev = data; @@ -3448,6 +3494,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); +DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops, + disallow_edp_enter_replay_get, + disallow_edp_enter_replay_set, "%llu\n"); + DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, ips_residency_cntl_set, "%llu\n"); DEFINE_SHOW_ATTRIBUTE(current_backlight); @@ -3651,6 +3701,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) &allow_edp_hotplug_detection_fops); debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); + debugfs_create_file("disallow_edp_enter_replay", 0644, dir, connector, + &disallow_edp_enter_replay_fops); } for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { From fa42d62fc238d1a85cb26d745ee64e8ef3b7c1ce Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Fri, 23 Jan 2026 15:33:13 -0500 Subject: [PATCH 1873/2070] drm/amd/display: Fix number of opp [Why/How] Patch number of opp based on IP caps Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- .../amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c index 608b4a305c656..99fc2f0666e2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c @@ -187,6 +187,7 @@ static void patch_ip_params_with_ip_caps(struct dml2_core_ip_params *ip_params, { ip_params->max_num_dpp = ip_caps->pipe_count; ip_params->max_num_otg = ip_caps->otg_count; + ip_params->max_num_opp = ip_caps->otg_count; ip_params->num_dsc = ip_caps->num_dsc; ip_params->max_num_dp2p0_streams = ip_caps->max_num_dp2p0_streams; ip_params->max_num_dp2p0_outputs = ip_caps->max_num_dp2p0_outputs; From b296ea38d512c1a2baaaacb897d543eb8eaadf9d Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 29 Jan 2026 17:31:19 -0500 Subject: [PATCH 1874/2070] drm/amd/display: Add dcn_mrq_present Field [Why/How] Add MRQ flag so it can be passed from ip_caps to ip_params Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- .../display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h index ddbb8dfa9ff88..6152155d60735 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h @@ -192,6 +192,7 @@ struct dml2_ip_capabilities { unsigned int max_flip_time_us; unsigned int max_flip_time_lines; unsigned int hostvm_mode; + bool dcn_mrq_present; unsigned int subvp_drr_scheduling_margin_us; unsigned int subvp_prefetch_end_to_mall_start_us; unsigned int subvp_fw_processing_delay; From 7c0fdc63a09a62986fcecd677d38178e16b8a8ba Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 3 Mar 2026 09:48:37 -0500 Subject: [PATCH 1875/2070] drm/amd/display: Plumb MRQ programming out of DML for dml2_1 [Why] If the MRQ is present then these fields are also required to be plumbed out to the requestor for programming. [How] Pipe the fields out through rq_dlg_get_rq_reg. The implementation follows the previous generation in dml2_0 for DCN35 but adjusted for the new helpers and coding style of dml2_1. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- .../src/dml2_core/dml2_core_dcn4_calcs.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index ca5ac3c0deb56..b30d16474ceb0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -12262,11 +12262,15 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, unsigned int pixel_chunk_bytes = 0; unsigned int min_pixel_chunk_bytes = 0; + unsigned int meta_chunk_bytes = 0; + unsigned int min_meta_chunk_bytes = 0; unsigned int dpte_group_bytes = 0; unsigned int mpte_group_bytes = 0; unsigned int p1_pixel_chunk_bytes = 0; unsigned int p1_min_pixel_chunk_bytes = 0; + unsigned int p1_meta_chunk_bytes = 0; + unsigned int p1_min_meta_chunk_bytes = 0; unsigned int p1_dpte_group_bytes = 0; unsigned int p1_mpte_group_bytes = 0; @@ -12287,8 +12291,13 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, dpte_group_bytes = (unsigned int)(dml_get_dpte_group_size_in_bytes(mode_lib, pipe_idx)); mpte_group_bytes = (unsigned int)(dml_get_vm_group_size_in_bytes(mode_lib, pipe_idx)); + meta_chunk_bytes = (unsigned int)(mode_lib->ip.meta_chunk_size_kbytes * 1024); + min_meta_chunk_bytes = (unsigned int)(mode_lib->ip.min_meta_chunk_size_bytes); + p1_pixel_chunk_bytes = pixel_chunk_bytes; p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; + p1_meta_chunk_bytes = meta_chunk_bytes; + p1_min_meta_chunk_bytes = min_meta_chunk_bytes; p1_dpte_group_bytes = dpte_group_bytes; p1_mpte_group_bytes = mpte_group_bytes; @@ -12309,6 +12318,19 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, else rq_regs->rq_regs_c.min_chunk_size = log_and_substract_if_non_zero(p1_min_pixel_chunk_bytes, 8 - 1); + rq_regs->rq_regs_l.meta_chunk_size = log_and_substract_if_non_zero(meta_chunk_bytes, 10); + rq_regs->rq_regs_c.meta_chunk_size = log_and_substract_if_non_zero(p1_meta_chunk_bytes, 10); + + if (min_meta_chunk_bytes == 0) + rq_regs->rq_regs_l.min_meta_chunk_size = 0; + else + rq_regs->rq_regs_l.min_meta_chunk_size = log_and_substract_if_non_zero(min_meta_chunk_bytes, 6 - 1); + + if (min_meta_chunk_bytes == 0) + rq_regs->rq_regs_c.min_meta_chunk_size = 0; + else + rq_regs->rq_regs_c.min_meta_chunk_size = log_and_substract_if_non_zero(p1_min_meta_chunk_bytes, 6 - 1); + rq_regs->rq_regs_l.dpte_group_size = log_and_substract_if_non_zero(dpte_group_bytes, 6); rq_regs->rq_regs_l.mpte_group_size = log_and_substract_if_non_zero(mpte_group_bytes, 6); rq_regs->rq_regs_c.dpte_group_size = log_and_substract_if_non_zero(p1_dpte_group_bytes, 6); From 457f6cde9613d1f51d83bee8ea6490570d695bce Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Thu, 26 Feb 2026 15:17:20 -0500 Subject: [PATCH 1876/2070] drm/amd/display: Silence static analysis warning Silence static analysis warnings by ensuring swath size temporaries are initialized before use. No functional change intended. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 +- .../drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index cd8cca6514196..48905ca39b706 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -5304,7 +5304,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double LinesInDETC; unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; unsigned int LinesInDETCRoundedDownToSwath; - double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; + double FullDETBufferingTimeY[DC__NUM_DPP__MAX] = { 0 }; double FullDETBufferingTimeC; double ActiveDRAMClockChangeLatencyMarginY; double ActiveDRAMClockChangeLatencyMarginC; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 0748ef36a16a2..19b142412a84b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -459,8 +459,8 @@ void dml32_CalculateSwathAndDETConfiguration( { unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; - unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX]; - unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX]; + unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX] = { 0 }; unsigned int RoundedUpSwathSizeBytesY; unsigned int RoundedUpSwathSizeBytesC; double SwathWidthdoubleDPP[DC__NUM_DPP__MAX]; @@ -2988,7 +2988,7 @@ void dml32_UseMinimumDCFCLK( for (j = 0; j <= 1; ++j) { double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; double PrefetchPixelLinesTime[DC__NUM_DPP__MAX]; - double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX]; + double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX] = { 0 }; double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; double MinimumTWait = 0.0; double DPTEBandwidth; From 46d8565dcdd443387c07a72ead253b8ee475f431 Mon Sep 17 00:00:00 2001 From: Tom Chung Date: Wed, 4 Mar 2026 17:48:00 +0800 Subject: [PATCH 1877/2070] drm/amd/display: Add a buffer for boot time crc [Why] We need to reserve a memory buffer for boot time crc test during resume. [How] Create a buffer during boot up and send the buffer info to DMUB. Reviewed-by: Wayne Lin Signed-off-by: Tom Chung Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 58 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 21 +++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 27 +++++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 9 +++ 4 files changed, 115 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 17dd1e046a3de..77d2d6d3cd65c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2323,6 +2323,11 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) &adev->dm.dmub_bo_gpu_addr, &adev->dm.dmub_bo_cpu_addr); + if (adev->dm.boot_time_crc_info.bo_ptr) + amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, + &adev->dm.boot_time_crc_info.gpu_addr, + &adev->dm.boot_time_crc_info.cpu_addr); + if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { for (i = 0; i < adev->dm.dc->caps.max_links; i++) { if (adev->dm.hpd_rx_offload_wq[i].wq) { @@ -2772,6 +2777,54 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) return ret; } +static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) +{ + struct dm_boot_time_crc_info *bootcrc_info = NULL; + struct dmub_srv *dmub = NULL; + union dmub_fw_boot_options option = {0}; + int ret = 0; + const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ + + if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || + !adev->dm.dc->ctx->dmub_srv) { + return; + } + + dmub = adev->dm.dc->ctx->dmub_srv->dmub; + bootcrc_info = &adev->dm.boot_time_crc_info; + + if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { + drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); + return; + } + + option = dmub->hw_funcs.get_fw_boot_option(dmub); + + /* Return if boot time CRC is not enabled */ + if (option.bits.bootcrc_en_at_S0i3 == 0) + return; + + /* Create a buffer for boot time CRC */ + ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, + &bootcrc_info->bo_ptr, + &bootcrc_info->gpu_addr, + &bootcrc_info->cpu_addr); + + if (ret) { + drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); + } else { + bootcrc_info->size = fb_size; + + drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", + bootcrc_info->gpu_addr, bootcrc_info->size); + + /* Send the buffer info to DMUB */ + dc_dmub_srv_boot_time_crc_init(adev->dm.dc, + bootcrc_info->gpu_addr, bootcrc_info->size); + } +} + static int dm_late_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -2783,6 +2836,11 @@ static int dm_late_init(struct amdgpu_ip_block *ip_block) dmcu = adev->dm.dc->res_pool->dmcu; + /* Init the boot time CRC (skip in resume) */ + if ((adev->in_suspend == 0) && + (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) + amdgpu_dm_boot_time_crc_init(adev); + for (i = 0; i < 16; i++) linear_lut[i] = 0xFFFF * i / 15; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 14bc935cdf17e..befa3eb30dece 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -123,6 +123,20 @@ struct dm_compressor_info { uint64_t gpu_addr; }; +/** + * struct dm_boot_time_crc_info - Buffer info used by boot time CRC + * @cpu_addr: MMIO cpu addr + * @bo_ptr: Pointer to the buffer object + * @gpu_addr: MMIO gpu addr + * @size: Size of the buffer + */ +struct dm_boot_time_crc_info { + void *cpu_addr; + struct amdgpu_bo *bo_ptr; + uint64_t gpu_addr; + uint32_t size; +}; + typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); /** @@ -705,6 +719,13 @@ struct amdgpu_display_manager { struct completion replied; char reply_data[0x40]; // Cannot include dmub_cmd here } fused_io[8]; + + /** + * @dm_boot_time_crc_info: + * + * Buffer info for the boot time crc. + */ + struct dm_boot_time_crc_info boot_time_crc_info; }; enum dsc_clock_force_state { diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index e4dd5ca709877..d6a08064456b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -2349,6 +2349,33 @@ bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc) return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled; } +void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size) +{ + struct dc_dmub_srv *dc_dmub_srv; + struct dc_context *dc_ctx; + union dmub_rb_cmd cmd = {0}; + bool result = false; + + if (!dc || !dc->ctx || !dc->ctx->dmub_srv || size == 0) + return; + + dc_dmub_srv = dc->ctx->dmub_srv; + dc_ctx = dc_dmub_srv->ctx; + + memset(&cmd, 0, sizeof(cmd)); + cmd.boot_time_crc_init.header.type = DMUB_CMD__BOOT_TIME_CRC; + cmd.boot_time_crc_init.header.sub_type = DMUB_CMD__BOOT_TIME_CRC_INIT_MEM; + cmd.boot_time_crc_init.header.payload_bytes = + sizeof(struct dmub_rb_cmd_boot_time_crc_init); + cmd.boot_time_crc_init.data.buffer_addr.quad_part = gpu_addr; + cmd.boot_time_crc_init.data.buffer_size = size; + + result = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); + + if (!result) + DC_ERROR("Boot time crc init failed in DMUB"); +} + void dc_dmub_srv_release_hw(const struct dc *dc) { struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 72e0a41f39f04..6579cf9cce3c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -361,6 +361,15 @@ void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe); */ bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc); +/** + * dc_dmub_srv_boot_time_crc_init() - Initializes DMUB boot time CRC. + * + * @dc - pointer to DC object + * @gpu_addr - address for the boot time CRC buffer + * @size - size of the boot time CRC buffer + */ +void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size); + /** * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required. * From f954f6d843d15dffffbc0d41e58e8a26170b12a3 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Wed, 11 Mar 2026 14:36:05 +0800 Subject: [PATCH 1878/2070] drm/amd/display: Query DC for gfx handling when setting linear tiling [Why] Post-driver cases always use linear tiling yet gfx handling for this case is improper, allowing for incorrect gfx structs to be populated and used. [How] Query DC for the apporpriate linear tiling mode and populate the DCN specific gfx version structs. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Carbones Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 9 +++++++++ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + .../drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 9 ++++++++- .../drm/amd/display/dc/resource/dcn10/dcn10_resource.h | 2 ++ .../drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 3 ++- .../amd/display/dc/resource/dcn201/dcn201_resource.c | 3 ++- .../drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 3 ++- .../drm/amd/display/dc/resource/dcn30/dcn30_resource.c | 3 ++- .../amd/display/dc/resource/dcn301/dcn301_resource.c | 3 ++- .../amd/display/dc/resource/dcn302/dcn302_resource.c | 3 ++- .../amd/display/dc/resource/dcn303/dcn303_resource.c | 3 ++- .../drm/amd/display/dc/resource/dcn31/dcn31_resource.c | 1 + .../amd/display/dc/resource/dcn314/dcn314_resource.c | 3 ++- .../amd/display/dc/resource/dcn315/dcn315_resource.c | 3 ++- .../amd/display/dc/resource/dcn316/dcn316_resource.c | 3 ++- .../drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 1 + .../amd/display/dc/resource/dcn321/dcn321_resource.c | 1 + .../drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 3 ++- .../amd/display/dc/resource/dcn351/dcn351_resource.c | 3 ++- .../drm/amd/display/dc/resource/dcn36/dcn36_resource.c | 3 ++- .../amd/display/dc/resource/dcn401/dcn401_resource.c | 9 ++++++++- .../amd/display/dc/resource/dcn401/dcn401_resource.h | 2 ++ 23 files changed, 69 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 373b613d1805b..3d56d3e8c3e82 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2617,6 +2617,16 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) dc->optimized_required = false; } +void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info) +{ + if (!dc || !tiling_info) + return; + if (dc->res_pool && dc->res_pool->funcs && dc->res_pool->funcs->get_default_tiling_info) { + dc->res_pool->funcs->get_default_tiling_info(tiling_info); + return; + } +} + bool dc_set_generic_gpio_for_stereo(bool enable, struct gpio_service *gpio_service) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8cfa2da5e7da0..39419e9c51404 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1973,6 +1973,15 @@ void dc_plane_cm_retain(struct dc_plane_cm *cm); void dc_post_update_surfaces_to_stream( struct dc *dc); +/* + * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling + * description for (typically) linear surfaces. + * + * This is used by OS/DM paths that need a valid, fully-initialized tiling + * description without hardcoding gfx-version specifics in the caller. + */ +void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); + /** * struct dc_validation_set - Struct to store surface/stream associations for validation */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index f6ae3209fab02..0d59903c4a6bd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -213,6 +213,7 @@ struct resource_funcs { unsigned int index); void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); + void (*get_default_tiling_info)(struct dc_tiling_info *tiling_info); void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); /* * Get indicator of power from a context that went through full validation diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 476780a5450fb..9c1a57a1f989e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -1275,6 +1275,12 @@ static const struct dc_cap_funcs cap_funcs = { .get_dcc_compression_cap = dcn10_get_dcc_compression_cap }; +void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info) +{ + tiling_info->gfxversion = DcGfxVersion9; + tiling_info->gfx9.swizzle = DC_SW_LINEAR; +} + static const struct resource_funcs dcn10_res_pool_funcs = { .destroy = dcn10_destroy_resource_pool, .link_enc_create = dcn10_link_encoder_create, @@ -1286,7 +1292,8 @@ static const struct resource_funcs dcn10_res_pool_funcs = { .add_stream_to_ctx = dcn10_add_stream_to_ctx, .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static uint32_t read_pipe_fuses(struct dc_context *ctx) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h index 7bc1be53e8009..c7409298caa9a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h @@ -53,5 +53,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); +void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info); + #endif /* __DC_RESOURCE_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 911e9e2975351..e954c340e08d2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -2224,7 +2224,8 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .set_mcif_arb_params = dcn20_set_mcif_arb_params, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index 90d38631f63a0..5f0b592a3dc7e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1081,7 +1081,8 @@ static struct resource_funcs dcn201_res_pool_funcs = { .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .set_mcif_arb_params = dcn20_set_mcif_arb_params, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn201_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 666b7be36a952..d5b53ab5e2675 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -1378,7 +1378,8 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, .update_bw_bounding_box = dcn21_update_bw_bounding_box, .get_panel_config_defaults = dcn21_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn21_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 6cfdc37dab588..66b1a1c2db1da 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -2252,7 +2252,8 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .update_bw_bounding_box = dcn30_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn30_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; #define CTX ctx diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index f0078eb134981..ff3c4e5c5cf0d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1403,7 +1403,8 @@ static struct resource_funcs dcn301_res_pool_funcs = { .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, .update_bw_bounding_box = dcn301_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info, }; static bool dcn301_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index c0d4a1dc94f8a..7c4c5c8aa4b69 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -1155,7 +1155,8 @@ static struct resource_funcs dcn302_res_pool_funcs = { .update_bw_bounding_box = dcn302_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn302_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static struct dc_cap_funcs cap_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 75e09c2c283e0..360934bc54818 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -1099,7 +1099,8 @@ static struct resource_funcs dcn303_res_pool_funcs = { .update_bw_bounding_box = dcn303_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn303_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static struct dc_cap_funcs cap_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 8ad72557b16a4..a064d1fbce523 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -1855,6 +1855,7 @@ static struct resource_funcs dcn31_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, + .get_default_tiling_info = dcn10_get_default_tiling_info, .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 5f0fe6e5bd821..803b87986802b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -1786,7 +1786,8 @@ static struct resource_funcs dcn314_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static struct clock_source *dcn30_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 3ae787a377b18..67102b4c881fe 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1850,7 +1850,8 @@ static struct resource_funcs dcn315_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn315_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 61bd6d373bb7d..f6ec8708f2bf8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -1726,7 +1726,8 @@ static struct resource_funcs dcn316_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn316_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 368ef798be829..5c0658a609a81 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -2116,6 +2116,7 @@ static struct resource_funcs dcn32_res_pool_funcs = { .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .add_phantom_pipes = dcn32_add_phantom_pipes, + .get_default_tiling_info = dcn10_get_default_tiling_info, .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 5a82662f20df5..d3c60bed7735f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1621,6 +1621,7 @@ static struct resource_funcs dcn321_res_pool_funcs = { .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, + .get_default_tiling_info = dcn10_get_default_tiling_info, }; static uint32_t read_pipe_fuses(struct dc_context *ctx) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 5ea805fcff482..f7e2e79bc0e15 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1805,7 +1805,8 @@ static struct resource_funcs dcn35_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn35_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 424b52e2dd7b2..5dffaf12a7c0d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1778,7 +1778,8 @@ static struct resource_funcs dcn351_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn351_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 7582217bd06d5..40894afd990e4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1784,7 +1784,8 @@ static struct resource_funcs dcn36_res_pool_funcs = { .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info, }; static bool dcn36_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index f5e02a1ff771f..57ae4b216b5d2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1843,9 +1843,16 @@ static struct resource_funcs dcn401_res_pool_funcs = { .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .get_power_profile = dcn401_get_power_profile, .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, - .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size + .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, + .get_default_tiling_info = dcn401_get_default_tiling_info }; +void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info) +{ + tiling_info->gfxversion = DcGfxAddr3; + tiling_info->gfx_addr3.swizzle = DC_ADDR3_SW_LINEAR; +} + static uint32_t read_pipe_fuses(struct dc_context *ctx) { uint32_t value = REG_READ(CC_DC_PIPE_DIS); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 08bec17556174..5f3b0319cb5bb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -28,6 +28,8 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); +void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info); + unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); /* Following are definitions for run time init of reg offsets */ From 97f53b718d136550e947ae9ad02e50db6b62af44 Mon Sep 17 00:00:00 2001 From: Benjamin Nwankwo Date: Fri, 6 Mar 2026 12:49:44 -0500 Subject: [PATCH 1879/2070] drm/amd/display: Clamp dc_cursor_position x_hotspot to prevent integer overflow why: Workaround for duplicate cursor. Cursor offsetting via x_hotspot attempts to write a 32 bit unsigned integer to the 8 bit field CURSOR_HOT_SPOT_X. This wraps cursor position back into focus if x_hotspot exceeds 8 bits, making duplicate cursors visible how: Clamp x_hotspot before writing to hardware Reviewed-by: Charlene Liu Reviewed-by: Nevenko Stupar Signed-off-by: Benjamin Nwankwo Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 4985e885952d9..263e0c4d34f66 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -812,9 +812,8 @@ void hubp401_cursor_set_position( int x_pos_viewport = 0; int x_hot_viewport = 0; uint32_t cur_en = pos->enable ? 1 : 0; - + uint32_t x_hotspot_clamped = pos->x_hotspot; hubp->curs_pos = *pos; - /* Recout is zero for pipes if the entire dst_rect is contained * within preceeding ODM slices. */ @@ -845,6 +844,8 @@ void hubp401_cursor_set_position( ASSERT(param->h_scale_ratio.value); + if (x_hotspot_clamped > 0xFF) + x_hotspot_clamped = 0xFF; if (param->h_scale_ratio.value) dst_x_offset = dc_fixpt_floor(dc_fixpt_div( dc_fixpt_from_int(dst_x_offset), @@ -865,7 +866,7 @@ void hubp401_cursor_set_position( CURSOR_Y_POSITION, pos->y); REG_SET_2(CURSOR_HOT_SPOT, 0, - CURSOR_HOT_SPOT_X, pos->x_hotspot, + CURSOR_HOT_SPOT_X, x_hotspot_clamped, CURSOR_HOT_SPOT_Y, pos->y_hotspot); REG_SET(CURSOR_DST_OFFSET, 0, From 3f8683cd1f833c0fe601c58728657006a3fe2b2c Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 6 Mar 2026 17:43:58 -0500 Subject: [PATCH 1880/2070] drm/amd/display: Promote DC to 3.2.374 This version brings along the following updates: - Clamp dc_cursor_position x_hotspot to prevent integer overflow - Query DC for gfx handling when setting linear tiling - Add a buffer for boot time crc - Silence static analysis warnings - Plumb MRQ programming out of DML for dml2_1 - Add dcn_mrq_present Field - Fix number of opp - Add debugfs to disallow eDP Replay entry Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 39419e9c51404..2344f184ce079 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.373" +#define DC_VER "3.2.374" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 686fae2328d3344581237ef2f26b407dccef57ea Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 12 Mar 2026 15:33:07 +0800 Subject: [PATCH 1881/2070] drm/amd/pm: Use common smu fw check function for smu13 Use common smu fw check function for smu13 and remove deicated ones v2: Remove dedicated functions and directly use common one Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 - .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 2 +- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 43 ------------------- .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 2 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 2 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +- .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 2 +- 9 files changed, 7 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index b0d6b7b0946d8..89bbda0670ef1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -132,8 +132,6 @@ int smu_v13_0_setup_pptable(struct smu_context *smu); int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); -int smu_v13_0_check_fw_version(struct smu_context *smu); - int smu_v13_0_set_driver_table_location(struct smu_context *smu); int smu_v13_0_set_tool_table_location(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index ad23682217eeb..259e5a13c1bd2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1989,7 +1989,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { /* pptable related */ .setup_pptable = aldebaran_setup_pptable, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .write_pptable = smu_cmn_write_pptable, .set_driver_table_location = smu_v13_0_set_driver_table_location, .set_tool_table_location = smu_v13_0_set_tool_table_location, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 0f4b4f31bfeb6..5f6f7d2d44e4e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -258,49 +258,6 @@ int smu_v13_0_check_fw_status(struct smu_context *smu) return -EIO; } -int smu_v13_0_check_fw_version(struct smu_context *smu) -{ - struct amdgpu_device *adev = smu->adev; - uint32_t if_version = 0xff, smu_version = 0xff; - uint8_t smu_program, smu_major, smu_minor, smu_debug; - int ret = 0; - - ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); - if (ret) - return ret; - - smu_program = (smu_version >> 24) & 0xff; - smu_major = (smu_version >> 16) & 0xff; - smu_minor = (smu_version >> 8) & 0xff; - smu_debug = (smu_version >> 0) & 0xff; - adev->pm.fw_version = smu_version; - - /* only for dGPU w/ SMU13*/ - if (adev->pm.fw) - dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", - smu_program, smu_version, smu_major, smu_minor, smu_debug); - - /* - * 1. if_version mismatch is not critical as our fw is designed - * to be backward compatible. - * 2. New fw usually brings some optimizations. But that's visible - * only on the paired driver. - * Considering above, we just leave user a verbal message instead - * of halt driver loading. - */ - dev_info_once(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " - "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", - smu->smc_driver_if_version, if_version, - smu_program, smu_version, smu_major, smu_minor, smu_debug); - - if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && - if_version != smu->smc_driver_if_version) { - dev_info(adev->dev, "SMU driver if version not matched\n"); - } - - return ret; -} - static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) { struct amdgpu_device *adev = smu->adev; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index fed3b737fecfe..19c50f27422df 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -3134,7 +3134,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .fini_power = smu_v13_0_fini_power, .check_fw_status = smu_v13_0_check_fw_status, .setup_pptable = smu_v13_0_0_setup_pptable, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .write_pptable = smu_cmn_write_pptable, .set_driver_table_location = smu_v13_0_set_driver_table_location, .system_features_control = smu_v13_0_0_system_features_control, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 75b90ac0c29c5..167b3499f7f1b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -1098,7 +1098,7 @@ static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *sm static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { .check_fw_status = smu_v13_0_check_fw_status, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = smu_v13_0_4_init_smc_tables, .fini_smc_tables = smu_v13_0_4_fini_smc_tables, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index 8ee5002e3d6b2..141e778333c50 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -1102,7 +1102,7 @@ static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *sm static const struct pptable_funcs smu_v13_0_5_ppt_funcs = { .check_fw_status = smu_v13_0_check_fw_status, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = smu_v13_0_5_init_smc_tables, .fini_smc_tables = smu_v13_0_5_fini_smc_tables, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 4d1ca068fe636..63bcef2b326ed 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -488,7 +488,7 @@ static int smu_v13_0_6_check_fw_version(struct smu_context *smu) { int r; - r = smu_v13_0_check_fw_version(smu); + r = smu_cmn_check_fw_version(smu); /* Initialize caps flags once fw version is fetched */ if (!r) smu_v13_0_x_init_caps(smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index fa23f3d4a3fda..35b2b8f5801a3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2790,7 +2790,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .fini_power = smu_v13_0_fini_power, .check_fw_status = smu_v13_0_7_check_fw_status, .setup_pptable = smu_v13_0_7_setup_pptable, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .write_pptable = smu_cmn_write_pptable, .set_driver_table_location = smu_v13_0_set_driver_table_location, .system_features_control = smu_v13_0_system_features_control, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index f9789b1fcbf83..748b5b074fff6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -1331,7 +1331,7 @@ static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *sm static const struct pptable_funcs yellow_carp_ppt_funcs = { .check_fw_status = smu_v13_0_check_fw_status, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = yellow_carp_init_smc_tables, .fini_smc_tables = yellow_carp_fini_smc_tables, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, From 9594a73f1f5eff8b7a2b01f1f6d863f775ee8e71 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 12 Mar 2026 15:40:13 +0800 Subject: [PATCH 1882/2070] drm/amd/pm: Use common smu fw check function for smu15 Use common smu fw check function for smu15 and remove dedicated ones v2: Remove dedicated functions and directly use common one Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 2 - .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 52 ------------------- .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 3 +- 3 files changed, 2 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index ab4a64f54e797..09743ccd0d15c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -142,8 +142,6 @@ int smu_v15_0_setup_pptable(struct smu_context *smu); int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu); -int smu_v15_0_check_fw_version(struct smu_context *smu); - int smu_v15_0_set_driver_table_location(struct smu_context *smu); int smu_v15_0_set_tool_table_location(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index a2f446d38be88..478ee87af51f3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -207,58 +207,6 @@ int smu_v15_0_check_fw_status(struct smu_context *smu) return -EIO; } -int smu_v15_0_check_fw_version(struct smu_context *smu) -{ - struct amdgpu_device *adev = smu->adev; - uint32_t if_version = 0xff, smu_version = 0xff; - uint8_t smu_program, smu_major, smu_minor, smu_debug; - int ret = 0; - - ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); - if (ret) - return ret; - - smu_program = (smu_version >> 24) & 0xff; - smu_major = (smu_version >> 16) & 0xff; - smu_minor = (smu_version >> 8) & 0xff; - smu_debug = (smu_version >> 0) & 0xff; - if (smu->is_apu) - adev->pm.fw_version = smu_version; - - switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { - case IP_VERSION(15, 0, 0): - smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0; - break; - default: - dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", - amdgpu_ip_version(adev, MP1_HWIP, 0)); - smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_INV; - break; - } - - if (adev->pm.fw) - dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", - smu_program, smu_version, smu_major, smu_minor, smu_debug); - - /* - * 1. if_version mismatch is not critical as our fw is designed - * to be backward compatible. - * 2. New fw usually brings some optimizations. But that's visible - * only on the paired driver. - * Considering above, we just leave user a verbal message instead - * of halt driver loading. - */ - if (if_version != smu->smc_driver_if_version) { - dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " - "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", - smu->smc_driver_if_version, if_version, - smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(adev->dev, "SMU driver if version not matched\n"); - } - - return ret; -} - static int smu_v15_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) { struct amdgpu_device *adev = smu->adev; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index 660335d7bda95..9a4a5f482e75c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -1416,7 +1416,7 @@ static int smu_v15_0_common_get_dpm_table(struct smu_context *smu, struct dpm_cl static const struct pptable_funcs smu_v15_0_0_ppt_funcs = { .check_fw_status = smu_v15_0_check_fw_status, - .check_fw_version = smu_v15_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = smu_v15_0_0_init_smc_tables, .fini_smc_tables = smu_v15_0_0_fini_smc_tables, .get_vbios_bootup_values = smu_v15_0_get_vbios_bootup_values, @@ -1468,6 +1468,7 @@ void smu_v15_0_0_set_ppt_funcs(struct smu_context *smu) smu->feature_map = smu_v15_0_0_feature_mask_map; smu->table_map = smu_v15_0_0_table_map; smu->is_apu = true; + smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0; smu_v15_0_0_init_msg_ctl(smu); } From ef73ecaafac7889680c79d2f6942fe7f5f32ef72 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 13 Mar 2026 12:33:43 +0530 Subject: [PATCH 1883/2070] drm/amdgpu/userq: Use kvfree instead of kfree in amdgpu_userq_wait_ioctl In function amdgpu_userq_wait_ioctl, drm_gem_objects_lookup allocates memory via kvmalloc and hence when that memory is freed the memory via kvfree. Fixes: 2de9353e193f ("drm/amdgpu/userq: Use drm_gem_objects_lookup in amdgpu_userq_wait_ioctl") Signed-off-by: Sunil Khatri Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 8b08484a0e8e9..2651467beedbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -1007,11 +1007,11 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, put_gobj_write: for (i = 0; i < num_write_bo_handles; i++) drm_gem_object_put(gobj_write[i]); - kfree(gobj_write); + kvfree(gobj_write); put_gobj_read: for (i = 0; i < num_read_bo_handles; i++) drm_gem_object_put(gobj_read[i]); - kfree(gobj_read); + kvfree(gobj_read); free_timeline_points: kfree(timeline_points); free_timeline_handles: From 3e0df8397de9112b131981760a2667aed48f0076 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 8 Dec 2025 16:29:51 +0800 Subject: [PATCH 1884/2070] drm/amd/ras: Pass ras poison consumption message to sriov host Pass ras poison consumption message to sriov host. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c index 5782c007de71c..285d81a85a99d 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c @@ -103,6 +103,16 @@ int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, if (!ih_info) return -EINVAL; + if (amdgpu_sriov_vf(adev)) { + if (adev->virt.ops && adev->virt.ops->ras_poison_handler) + adev->virt.ops->ras_poison_handler(adev, ih_info->block); + else + dev_warn(adev->dev, + "No ras_poison_handler interface in SRIOV for block[%d]!\n", + ih_info->block); + return 0; + } + memset(&req, 0, sizeof(req)); req.block = ih_info->block; req.data = ih_info->data; From e1d897768c2403f1228125e3583093c06c4ea97c Mon Sep 17 00:00:00 2001 From: David Baum Date: Thu, 12 Mar 2026 20:52:26 -0500 Subject: [PATCH 1885/2070] drm/amdgpu: switch XGMI sysfs show helpers to sysfs_emit_at() The XGMI sysfs show helpers amdgpu_xgmi_show_num_hops() and amdgpu_xgmi_show_num_links() currently populate the output buffer with sprintf() and then call sysfs_emit(buf, "%s\n", buf) to append the final newline. Convert both helpers to use sysfs_emit_at() while tracking the current offset. This keeps buffer construction in the sysfs helpers, avoids feeding the output buffer back into the final formatted write, and matches the style already used by amdgpu_xgmi_show_connected_port_num(). Signed-off-by: David Baum Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index b329d7b2dcb6e..9a4e8715742a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -478,12 +478,12 @@ static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; - int i; + int i, offset = 0; for (i = 0; i < top->num_nodes; i++) - sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops); + offset += sysfs_emit_at(buf, offset, "%02x ", top->nodes[i].num_hops); - return sysfs_emit(buf, "%s\n", buf); + return offset + sysfs_emit_at(buf, offset, "\n"); } static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, @@ -493,12 +493,12 @@ static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; - int i; + int i, offset = 0; for (i = 0; i < top->num_nodes; i++) - sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links); + offset += sysfs_emit_at(buf, offset, "%02x ", top->nodes[i].num_links); - return sysfs_emit(buf, "%s\n", buf); + return offset + sysfs_emit_at(buf, offset, "\n"); } static ssize_t amdgpu_xgmi_show_connected_port_num(struct device *dev, From 1bd2a6f0a9151555982d3cde89c492b91e90ae44 Mon Sep 17 00:00:00 2001 From: Erik Kurzinger Date: Tue, 10 Feb 2026 15:08:15 -0500 Subject: [PATCH 1886/2070] drm/amd/display: remove duplicate format modifier amdgpu_dm_plane_get_plane_modifiers always adds DRM_FORMAT_MOD_LINEAR to the list of modifiers. However, with gfx12, amdgpu_dm_plane_add_gfx12_modifiers also adds that modifier to the list. So we end up with two copies. Most apps just ignore this but some (Weston) don't like it. As a fix, we change amdgpu_dm_plane_add_gfx12_modifiers to not add DRM_FORMAT_MOD_LINEAR to the list, matching the behavior of analogous functions for other chips. Signed-off-by: Erik Kurzinger Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 5d60c0a07a003..93145fdc2fbfd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -720,21 +720,21 @@ static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, uint8_t max_comp_block[] = {2, 1, 0}; uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0}; uint8_t i = 0, j = 0; - uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b, DRM_FORMAT_MOD_LINEAR}; + /* Note, linear (no DCC) gets added to the modifier list for all chips by the caller. */ + uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b}; for (i = 0; i < ARRAY_SIZE(max_comp_block); i++) max_comp_block_mod[i] = AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block[i]); /* With DCC: Best choice should be kept first. Hence, add all 256k modifiers of different * max compressed blocks first and then move on to the next smaller sized layouts. - * Do not add the linear modifier here, and hence the condition of size-1 for the loop */ - for (j = 0; j < ARRAY_SIZE(gfx12_modifiers) - 1; j++) + for (j = 0; j < ARRAY_SIZE(gfx12_modifiers); j++) for (i = 0; i < ARRAY_SIZE(max_comp_block); i++) amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | dcc | max_comp_block_mod[i] | gfx12_modifiers[j]); - /* Without DCC. Add all modifiers including linear at the end */ + /* Without DCC. */ for (i = 0; i < ARRAY_SIZE(gfx12_modifiers); i++) amdgpu_dm_plane_add_modifier(mods, size, capacity, gfx12_modifiers[i]); From 35c155c932ba47266a3cd7d5652784cfb3113dbb Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Fri, 27 Feb 2026 12:30:38 -0700 Subject: [PATCH 1887/2070] drm/amd/display: Enable DEGAMMA and reject COLOR_PIPELINE+DEGAMMA_LUT [WHAT] Create DEGAMMA properties even if color pipeline is enabled, and enforce the mutual exclusion in atomic check by rejecting any commit that attempts to enable both COLOR_PIPELINE on the plane and DEGAMMA_LUT on the CRTC simultaneously. Fixes: 18a4127e9315 ("drm/amd/display: Disable CRTC degamma when color pipeline is enabled") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4963 Reviewed-by: Melissa Wen Reviewed-by: Harry Wentland Signed-off-by: Alex Hung Signed-off-by: Alex Deucher (cherry picked from commit a4fa2355e0add57253468ef13bd08f11285f3b6e) --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 18 ++++++++---------- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 8 ++++++++ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 739737a51279b..a781ef874595d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -785,17 +785,15 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, dm->adev->mode_info.crtcs[crtc_index] = acrtc; /* Don't enable DRM CRTC degamma property for - * 1. Degamma is replaced by color pipeline. - * 2. DCE since it doesn't support programmable degamma anywhere. - * 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor. + * 1. DCE since it doesn't support programmable degamma anywhere. + * 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor. + * Note: DEGAMMA properties are created even if the primary plane has the + * COLOR_PIPELINE property. User space can use either the DEGAMMA properties + * or the COLOR_PIPELINE property. An atomic commit which attempts to enable + * both is rejected. */ -#ifdef HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY - if (plane->color_pipeline_property) - has_degamma = false; - else -#endif - has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && - dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; + has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && + dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0, true, MAX_COLOR_LUT_ENTRIES); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 93145fdc2fbfd..6520cc4556d56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1293,6 +1293,14 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (ret) return ret; + /* Reject commits that attempt to use both COLOR_PIPELINE and CRTC DEGAMMA_LUT */ + if (new_plane_state->color_pipeline && new_crtc_state->degamma_lut) { + drm_dbg_atomic(plane->dev, + "[PLANE:%d:%s] COLOR_PIPELINE and CRTC DEGAMMA_LUT cannot be enabled simultaneously\n", + plane->base.id, plane->name); + return -EINVAL; + } + ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); if (ret) return ret; From 09d949127e357850e344e08d251668ca3f4e6840 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 11 Mar 2026 14:41:18 +0800 Subject: [PATCH 1888/2070] drm/amdkcl: wrap code under HAVE_DRM_DRM_COLOROP_H It's caused by the commit: "drm/amd/display: Enable DEGAMMA and reject COLOR_PIPELINE+DEGAMMA_LUT" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 6520cc4556d56..f858deab4a221 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1293,6 +1293,7 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (ret) return ret; +#ifdef HAVE_DRM_DRM_COLOROP_H /* Reject commits that attempt to use both COLOR_PIPELINE and CRTC DEGAMMA_LUT */ if (new_plane_state->color_pipeline && new_crtc_state->degamma_lut) { drm_dbg_atomic(plane->dev, @@ -1300,6 +1301,7 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, plane->base.id, plane->name); return -EINVAL; } +#endif ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); if (ret) From c82777416ab42e78e6e17696bdfa79266d8d741c Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 15 Mar 2026 18:30:26 +0530 Subject: [PATCH 1889/2070] drm/amd/display: Fix DisplayID not-found handling in parse_edid_displayid_vrr() parse_edid_displayid_vrr() searches the EDID extension blocks for a DisplayID extension before parsing the dynamic video timing range. The code previously checked whether edid_ext was NULL after the search loop. However, edid_ext is assigned during each iteration of the loop, so it will never be NULL once the loop has executed. If no DisplayID extension is found, edid_ext ends up pointing to the last extension block, and the NULL check does not correctly detect the failure case. Instead, check whether the loop completed without finding a matching DisplayID block by testing "i == edid->extensions". This ensures the function exits early when no DisplayID extension is present and avoids parsing an unrelated EDID extension block. Also simplify the EDID validation check using "!edid || !edid->extensions". Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:13079 parse_edid_displayid_vrr() warn: variable dereferenced before check 'edid_ext' (see line 13075) Fixes: a638b837d0e6 ("drm/amd/display: Fix refresh rate range for some panel") Cc: Roman Li Cc: Alex Hung Cc: Jerry Zuo Cc: Sun peng Li Cc: Tom Chung Cc: Dan Carpenter Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Tom Chung Change-Id: Iaa2ffe93edd9fcc6f6fce7972c6c80f57e29f079 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 77d2d6d3cd65c..856f06369d2de 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13509,7 +13509,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, u16 min_vfreq; u16 max_vfreq; - if (edid == NULL || edid->extensions == 0) + if (!edid || !edid->extensions) return; /* Find DisplayID extension */ @@ -13519,7 +13519,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, break; } - if (edid_ext == NULL) + if (i == edid->extensions) return; while (j < EDID_LENGTH) { From 0c1b6ea98c85cde77ae52b7ca68162e48b8292f9 Mon Sep 17 00:00:00 2001 From: Andy Nguyen Date: Sun, 15 Mar 2026 17:51:47 +0100 Subject: [PATCH 1890/2070] drm/amd: fix dcn 2.01 check The ASICREV_IS_BEIGE_GOBY_P check always took precedence, because it includes all chip revisions upto NV_UNKNOWN. Fixes: 54b822b3eac3 ("drm/amd/display: Use dce_version instead of chip_id") Signed-off-by: Andy Nguyen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index a75d76d9f7405..d2e2e8f299671 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -244,6 +244,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p BREAK_TO_DEBUGGER(); return NULL; } + if (ctx->dce_version == DCN_VERSION_2_01) { + dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base; + } if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) { dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; @@ -256,10 +260,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } - if (ctx->dce_version == DCN_VERSION_2_01) { - dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); - return &clk_mgr->base; - } dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } From 0fefa3cecd01241831a2eab7e2c17c8c29c87af2 Mon Sep 17 00:00:00 2001 From: Yicong Hui Date: Fri, 9 Jan 2026 16:25:14 +0000 Subject: [PATCH 1891/2070] drm/amdgpu: Replace deprecated strcpy() in amdgpu_virt_write_vf2pf_data strcpy() is deprecated as it does not do any bounds checking (as specified in Documentation/process/deprecated.rst). There is a risk of buffer overflow in the case that the value for THIS_MODULE->version exceeds the 64 characters. This is unlikely, but replacing the deprecated function will pre-emptively remove this risk entirely. Replace both instances of strcpy() with the safer strscpy() function. Changes have been compile tested. Reviewed-by: Kees Cook Signed-off-by: Yicong Hui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index f01f385091083..112e6489aab70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -605,10 +605,10 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) #ifdef MODULE if (THIS_MODULE->version != NULL) - strcpy(vf2pf_info->driver_version, THIS_MODULE->version); + strscpy(vf2pf_info->driver_version, THIS_MODULE->version); else #endif - strcpy(vf2pf_info->driver_version, "N/A"); + strscpy(vf2pf_info->driver_version, "N/A"); vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all vf2pf_info->driver_cert = 0; From f1ca459726b9e80b203274f749c3ffa7640db71e Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 11 Mar 2026 18:52:59 +0800 Subject: [PATCH 1892/2070] drm/amdgpu: update flip bit setting of RAS bad page The flip bit setting is different if umc number is half of original configuration. v2: block the flip bit setting for unsupported umc configuration. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 113 +++++++++++++++++-------- 1 file changed, 80 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c index 0f5b1719fda56..6cf674dfc8c40 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c @@ -183,50 +183,97 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) if (adev->gmc.gmc_funcs->query_mem_partition_mode) nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); - /* default setting */ - flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; - flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; - flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; - flip_bits->flip_row_bit = 13; - flip_bits->bit_num = 4; - flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; - - if (nps == AMDGPU_NPS2_PARTITION_MODE) { + if (adev->gmc.num_umc == 16) { + /* default setting */ + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; + flip_bits->flip_row_bit = 13; + flip_bits->bit_num = 4; + flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; + + if (nps == AMDGPU_NPS2_PARTITION_MODE) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; + } else if (nps == AMDGPU_NPS4_PARTITION_MODE) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; + } + + switch (vram_type) { + case AMDGPU_VRAM_TYPE_HBM: + /* other nps modes are taken as nps1 */ + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; + else if (nps == AMDGPU_NPS4_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + + break; + case AMDGPU_VRAM_TYPE_HBM3E: + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; + flip_bits->flip_row_bit = 12; + + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + else if (nps == AMDGPU_NPS4_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + + break; + default: + dev_warn(adev->dev, + "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); + break; + } + } else if (adev->gmc.num_umc == 8) { + /* default setting */ flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + flip_bits->flip_row_bit = 12; + flip_bits->bit_num = 4; flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; - } else if (nps == AMDGPU_NPS4_PARTITION_MODE) { - flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; - flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; - flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; - flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; - } - switch (vram_type) { - case AMDGPU_VRAM_TYPE_HBM: - /* other nps modes are taken as nps1 */ - if (nps == AMDGPU_NPS2_PARTITION_MODE) + if (nps == AMDGPU_NPS2_PARTITION_MODE) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; + } + + switch (vram_type) { + case AMDGPU_VRAM_TYPE_HBM: flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; - else if (nps == AMDGPU_NPS4_PARTITION_MODE) - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; - break; - case AMDGPU_VRAM_TYPE_HBM3E: - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; - flip_bits->flip_row_bit = 12; + /* other nps modes are taken as nps1 */ + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; - if (nps == AMDGPU_NPS2_PARTITION_MODE) + break; + case AMDGPU_VRAM_TYPE_HBM3E: flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; - else if (nps == AMDGPU_NPS4_PARTITION_MODE) - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + flip_bits->flip_row_bit = 12; - break; - default: + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + + break; + default: + dev_warn(adev->dev, + "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); + break; + } + } else { dev_warn(adev->dev, - "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); - break; + "Unsupported UMC number(%d), failed to set RAS flip bits.\n", + adev->gmc.num_umc); + + return; } adev->umc.retire_unit = 0x1 << flip_bits->bit_num; From a1ad5ce41b34a2e8e3f41731bf8a0400355861fe Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 13 Mar 2026 12:36:46 +0530 Subject: [PATCH 1893/2070] drm/amdgpu/userq: Use kvfree instead of kfree in amdgpu_userq_signal_ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In function amdgpu_userq_signal_ioctl, drm_gem_objects_lookup allocates memory via kvmalloc and hence when that memory is freed the memory via kvfree. Fixes: 4ca06f6fb45d ("drm/amdgpu/userq: Use drm_gem_objects_lookup in amdgpu_userq_signal_ioctl") Signed-off-by: Sunil Khatri Reviewed-by: Tvrtko Ursulin Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 2651467beedbd..fb0713232e722 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -661,11 +661,11 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, put_gobj_write: for (i = 0; i < num_write_bo_handles; i++) drm_gem_object_put(gobj_write[i]); - kfree(gobj_write); + kvfree(gobj_write); put_gobj_read: for (i = 0; i < num_read_bo_handles; i++) drm_gem_object_put(gobj_read[i]); - kfree(gobj_read); + kvfree(gobj_read); free_syncobj: while (entry-- > 0) if (syncobj[entry]) From e4bc161bde22f0a3ee02cb4dedfb250ef0b853ac Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Tue, 6 Jan 2026 11:00:17 -0600 Subject: [PATCH 1894/2070] drm/amd/display: Attach OLED property to eDP panels amdgpu verifies that a given panel is an OLED panel from extended caps and can provide accurate information to userspace. Attach a property to the DRM connector. Reviewed-by: Leo Li Link: https://patch.msgid.link/20260106170017.68158-3-superm1@kernel.org Signed-off-by: Mario Limonciello (AMD) (cherry picked from commit 5d9d1247b2d5aa75ceccc9f9a915d4ed1109a205) --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 856f06369d2de..c65994ea82241 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -92,6 +92,7 @@ #include #include #include +#include #include #include #include @@ -3894,6 +3895,10 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; caps->aux_support = false; + drm_object_property_set_value(&conn_base->base, + adev_to_drm(adev)->mode_config.panel_type_property, + caps->ext_caps->bits.oled ? DRM_MODE_PANEL_TYPE_OLED : DRM_MODE_PANEL_TYPE_UNKNOWN); + if (caps->ext_caps->bits.oled == 1 /* * || @@ -9369,6 +9374,8 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_eDP) { struct drm_privacy_screen *privacy_screen; + drm_connector_attach_panel_type_property(&aconnector->base); + privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); if (!IS_ERR(privacy_screen)) { drm_connector_attach_privacy_screen_provider(&aconnector->base, From 0b380cef09ae478f64af85d74c3249749313f6f7 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Tue, 6 Jan 2026 11:00:16 -0600 Subject: [PATCH 1895/2070] drm/connector: Add a new 'panel_type' property If the driver can make an assertion whether a connected panel is an OLED panel or not then it can attach a property to the connector that userspace can use as a hint for color schemes. Reviewed-by: Leo Li Link: https://patch.msgid.link/20260106170017.68158-2-superm1@kernel.org Signed-off-by: Mario Limonciello (AMD) (cherry picked from commit 42dab3138176a944b09996441d837986f9ef13f8) --- drivers/gpu/drm/drm_connector.c | 33 +++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 1 + include/drm/drm_mode_config.h | 4 ++++ include/uapi/drm/drm_mode.h | 4 ++++ 4 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 4f5b27fab475c..aec05adbc8894 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -1173,6 +1173,11 @@ static const struct drm_prop_enum_list drm_link_status_enum_list[] = { { DRM_MODE_LINK_STATUS_BAD, "Bad" }, }; +static const struct drm_prop_enum_list drm_panel_type_enum_list[] = { + { DRM_MODE_PANEL_TYPE_UNKNOWN, "unknown" }, + { DRM_MODE_PANEL_TYPE_OLED, "OLED" }, +}; + /** * drm_display_info_set_bus_formats - set the supported bus formats * @info: display info to store bus formats in @@ -1501,6 +1506,9 @@ EXPORT_SYMBOL(drm_hdmi_connector_get_output_format_name); * Summarizing: Only set "DPMS" when the connector is known to be enabled, * assume that a successful SETCONFIG call also sets "DPMS" to on, and * never read back the value of "DPMS" because it can be incorrect. + * panel_type: + * Immutable enum property to indicate the type of connected panel. + * Possible values are "unknown" (default) and "OLED". * PATH: * Connector path property to identify how this sink is physically * connected. Used by DP MST. This should be set by calling @@ -1851,6 +1859,13 @@ int drm_connector_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.link_status_property = prop; + prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE, "panel_type", + drm_panel_type_enum_list, + ARRAY_SIZE(drm_panel_type_enum_list)); + if (!prop) + return -ENOMEM; + dev->mode_config.panel_type_property = prop; + prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop"); if (!prop) return -ENOMEM; @@ -3626,3 +3641,21 @@ struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev, return tg; } EXPORT_SYMBOL(drm_mode_create_tile_group); + +/** + * drm_connector_attach_panel_type_property - attaches panel type property + * @connector: connector to attach the property on. + * + * This is used to add support for panel type detection. + */ +void drm_connector_attach_panel_type_property(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.panel_type_property; + + if (!prop) + return; + + drm_object_attach_property(&connector->base, prop, DRM_MODE_PANEL_TYPE_UNKNOWN); +} +EXPORT_SYMBOL(drm_connector_attach_panel_type_property); diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 7eaec37ae1c73..c18be8c19de0a 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -2493,6 +2493,7 @@ int drm_connector_attach_scaling_mode_property(struct drm_connector *connector, u32 scaling_mode_mask); int drm_connector_attach_vrr_capable_property( struct drm_connector *connector); +void drm_connector_attach_panel_type_property(struct drm_connector *connector); int drm_connector_attach_broadcast_rgb_property(struct drm_connector *connector); int drm_connector_attach_colorspace_property(struct drm_connector *connector); int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 895fb820dba07..5e1dd0cfccde2 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -600,6 +600,10 @@ struct drm_mode_config { * multiple CRTCs. */ struct drm_property *tile_property; + /** + * @panel_type_property: Default connector property for panel type + */ + struct drm_property *panel_type_property; /** * @link_status_property: Default connector property for link status * of a connector diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index cbbbfc1dfe2b8..3693d82b5279f 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -166,6 +166,10 @@ extern "C" { #define DRM_MODE_LINK_STATUS_GOOD 0 #define DRM_MODE_LINK_STATUS_BAD 1 +/* Panel type property */ +#define DRM_MODE_PANEL_TYPE_UNKNOWN 0 +#define DRM_MODE_PANEL_TYPE_OLED 1 + /* * DRM_MODE_ROTATE_ * From cace4383bd0607520105e425ca6472b3dacf1f96 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 12 Mar 2026 13:50:12 +0800 Subject: [PATCH 1896/2070] drm/amdkcl: test whether drm_mode_config has the panel_type_property member It's caused by the commit: dabfdbf1e "drm/amd/display: Attach OLED property to eDP panels" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm_mode_config_panel_type_property.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c65994ea82241..6ddbd45344dc7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3895,9 +3895,11 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; caps->aux_support = false; +#if defined(HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY) drm_object_property_set_value(&conn_base->base, adev_to_drm(adev)->mode_config.panel_type_property, caps->ext_caps->bits.oled ? DRM_MODE_PANEL_TYPE_OLED : DRM_MODE_PANEL_TYPE_UNKNOWN); +#endif if (caps->ext_caps->bits.oled == 1 /* @@ -9374,7 +9376,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_eDP) { struct drm_privacy_screen *privacy_screen; +#if defined(HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY) drm_connector_attach_panel_type_property(&aconnector->base); +#endif privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); if (!IS_ERR(privacy_screen)) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7fd422fef35d9..d28ac47e0b1c1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1207,6 +1207,9 @@ /* struct drm_memory_stats is defined */ #define HAVE_STRUCT_DRM_MEMORY_STATS 1 +/* struct drm_mode_config has member panel_type_property */ +#define HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY 1 + /* drm_plane_helper_funcs->atomic_async_check() have three arguments */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 new file mode 100644 index 0000000000000..6d0309bc28be0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.19-1925-g227b955a0144 +dnl # drm/connector: Add a new 'panel_type' property +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_MODE_CONFIG_HAS_PANEL_TYPE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config config; + config.panel_type_property = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY, 1, + [struct drm_mode_config has member panel_type_property]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ae70a7e93f4f7..56e69120f3974 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -5,6 +5,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET AC_AMDGPU_LINUX_HEADERS + AC_AMDGPU_STRUCT_DRM_MODE_CONFIG_HAS_PANEL_TYPE_PROPERTY AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_SUPPORTED_AMD_CHIPS From ffdb06ac39f0c4718f6f1b3d88d57a126b13622a Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 16 Mar 2026 13:59:46 +0800 Subject: [PATCH 1897/2070] drm/amdkcl: fix use wrong file name Fixes: 67ef8eaad("drm/amdkcl: test if dma_fence_check_and_signal() is available") Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 index a203513509462..b150200ac1f89 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHECK_AND_SIGNAL], [ #include ], [ dma_fence_check_and_signal(NULL); - ], [dma_fence_check_and_signal], [drivers/dma-buf/st-dma-fence.c],[ + ], [dma_fence_check_and_signal], [drivers/dma-buf/dma-fence.c],[ AC_DEFINE(HAVE_DMA_FENCE_CHECK_AND_SIGNAL, 1, [dma_fence_check_and_signal() is available]) ]) From 84e621d9a255d2d4cda704d4b6bf42666bc8b439 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 17 Mar 2026 15:31:40 +0800 Subject: [PATCH 1898/2070] drm/amdkcl: handle shmem_file_setup() vma_flags_t change in kernel 7.0 It's caused by the commit: 590d356aa433 "mm: update shmem_[kernel]_file_*() functions to use vma_flags_t" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/shmem-file-setup-vma-flags.m4 | 17 +++++++++++++++++ drivers/gpu/drm/ttm/ttm_backup.c | 4 ++++ drivers/gpu/drm/ttm/ttm_tt.c | 4 ++++ 5 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d28ac47e0b1c1..29a973b0a74b7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1141,6 +1141,9 @@ /* sg_alloc_table_from_pages_segment() is available */ #define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 +/* shmem_file_setup() takes vma_flags_t arg */ +/* #undef HAVE_SHMEM_FILE_SETUP_VMA_FLAGS */ + /* shmem_read_folio() is available */ #define HAVE_SHMEM_READ_FOLIO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 56e69120f3974..1259d9c6ee6d3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -268,6 +268,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_AMDGPU_TIMER_DELETE AC_AMDGPU_SHMEM_WRITEOUT + AC_AMDGPU_SHMEM_FILE_SETUP_VMA_FLAGS AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 new file mode 100644 index 0000000000000..619dd99b8d0d7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v7.0-rc4-590d356aa433 +dnl # mm: update shmem_[kernel]_file_*() functions to use vma_flags_t +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_FILE_SETUP_VMA_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + shmem_file_setup("test", 0, EMPTY_VMA_FLAGS); + ], [ + AC_DEFINE(HAVE_SHMEM_FILE_SETUP_VMA_FLAGS, 1, + [shmem_file_setup() takes vma_flags_t arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_backup.c b/drivers/gpu/drm/ttm/ttm_backup.c index b31b324735b50..fe1aa25d9439a 100644 --- a/drivers/gpu/drm/ttm/ttm_backup.c +++ b/drivers/gpu/drm/ttm/ttm_backup.c @@ -195,5 +195,9 @@ EXPORT_SYMBOL_GPL(ttm_backup_bytes_avail); */ struct file *ttm_backup_shmem_create(loff_t size) { +#ifdef HAVE_SHMEM_FILE_SETUP_VMA_FLAGS + return shmem_file_setup("ttm shmem backup", size, EMPTY_VMA_FLAGS); +#else return shmem_file_setup("ttm shmem backup", size, 0); +#endif } diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 19673c3c112b2..b22eb736bca1a 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -336,7 +336,11 @@ int ttm_tt_swapout(struct ttm_device *bdev, struct ttm_tt *ttm, struct page *to_page; int i, ret; +#ifdef HAVE_SHMEM_FILE_SETUP_VMA_FLAGS + swap_storage = shmem_file_setup("ttm swap", size, EMPTY_VMA_FLAGS); +#else swap_storage = shmem_file_setup("ttm swap", size, 0); +#endif if (IS_ERR(swap_storage)) { pr_err("Failed allocating swap storage\n"); return PTR_ERR(swap_storage); From 89efa532891d4c2a1bb0bd71a552806bd3447d59 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Fri, 13 Mar 2026 21:32:03 +0800 Subject: [PATCH 1899/2070] drm/amdgpu: fallback to default discovery offset/size in sriov guest In SRIOV guest environment, if dynamic critical region is not enabled, fallback to default discovery offset and size to ensure proper initialization Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index b3876293d344f..0435e739059ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -296,13 +296,17 @@ static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, if (vram_size) adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; - if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { - adev->discovery.offset = - adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; - adev->discovery.size = - adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; - if (!adev->discovery.offset || !adev->discovery.size) - return -EINVAL; + if (amdgpu_sriov_vf(adev)) { + if (adev->virt.is_dynamic_crit_regn_enabled) { + adev->discovery.offset = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; + adev->discovery.size = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; + if (!adev->discovery.offset || !adev->discovery.size) + return -EINVAL; + } else { + goto out; + } } else { tmr_size = RREG32(mmDRIVER_SCRATCH_2); if (tmr_size) { @@ -322,7 +326,7 @@ static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; } } - +out: adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); if (!adev->discovery.bin) return -ENOMEM; From 0acf8baa538aa8df83d3b444de8780abe6bbe600 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 13 Mar 2026 12:41:22 +0530 Subject: [PATCH 1900/2070] drm/amdgpu/userq: fix dma_fence refcount underflow in userq path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit An extra dma_fence_put() can drop the last reference to a fence while it is still attached to a dma_resv object. This frees the fence prematurely via dma_fence_release() while other users still hold the pointer. Later accesses through dma_resv iteration may then operate on the freed fence object, leading to refcount underflow warnings and potential hangs when walking reservation fences. Fix this by correcting the fence lifetime so the dma_resv object retains a valid reference until it is done with the fence.i [ 31.133803] refcount_t: underflow; use-after-free. [ 31.133805] WARNING: lib/refcount.c:28 at refcount_warn_saturate+0x58/0x90, CPU#18: kworker/u96:1/188 Signed-off-by: Sunil Khatri Reviewed-by: Tvrtko Ursulin Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index fb0713232e722..d8895289d97e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -945,12 +945,9 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, * be good for now */ r = dma_fence_wait(fences[i], true); - if (r) { - dma_fence_put(fences[i]); + if (r) goto free_fences; - } - dma_fence_put(fences[i]); continue; } @@ -980,7 +977,6 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, fence_info[cnt].va = fence_drv->va; fence_info[cnt].value = fences[i]->seqno; - dma_fence_put(fences[i]); /* Increment the actual userq fence count */ cnt++; } From 01ba7b358af0de00867e4da2f22763d39c72027a Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 12 Mar 2026 13:55:32 +0530 Subject: [PATCH 1901/2070] drm/amdgpu/userq: unlock cancel_delayed_work_sync for hang_detect_work MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cancel_delayed_work_sync for work hand_detect_work should not be locked since the amdgpu_userq_hang_detect_work also need the same mutex and when they run together it could be a deadlock. we do not need to hold the mutex for cancel_delayed_work_sync(&queue->hang_detect_work). With this in place if cancel and worker thread run at same time they will not deadlock. Due to any failures if there is a hand detect and reset that there a deadlock scenarios between cancel and running the main thread. [ 243.118276] task:kworker/9:0 state:D stack:0 pid:73 tgid:73 ppid:2 task_flags:0x4208060 flags:0x00080000 [ 243.118283] Workqueue: events amdgpu_userq_hang_detect_work [amdgpu] [ 243.118636] Call Trace: [ 243.118639] [ 243.118644] __schedule+0x581/0x1810 [ 243.118649] ? srso_return_thunk+0x5/0x5f [ 243.118656] ? srso_return_thunk+0x5/0x5f [ 243.118659] ? wake_up_process+0x15/0x20 [ 243.118665] schedule+0x64/0xe0 [ 243.118668] schedule_preempt_disabled+0x15/0x30 [ 243.118671] __mutex_lock+0x346/0x950 [ 243.118677] __mutex_lock_slowpath+0x13/0x20 [ 243.118681] mutex_lock+0x2c/0x40 [ 243.118684] amdgpu_userq_hang_detect_work+0x63/0x90 [amdgpu] [ 243.118888] process_scheduled_works+0x1f0/0x450 [ 243.118894] worker_thread+0x27f/0x370 [ 243.118899] kthread+0x1ed/0x210 [ 243.118903] ? __pfx_worker_thread+0x10/0x10 [ 243.118906] ? srso_return_thunk+0x5/0x5f [ 243.118909] ? __pfx_kthread+0x10/0x10 [ 243.118913] ret_from_fork+0x10f/0x1b0 [ 243.118916] ? __pfx_kthread+0x10/0x10 [ 243.118920] ret_from_fork_asm+0x1a/0x30 Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index c54a692d64c84..40962c5ab249a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -623,13 +623,14 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que int r = 0; cancel_delayed_work_sync(&uq_mgr->resume_work); + + /* Cancel any pending hang detection work and cleanup */ + cancel_delayed_work_sync(&queue->hang_detect_work); + mutex_lock(&uq_mgr->userq_mutex); + queue->hang_detect_fence = NULL; amdgpu_userq_wait_for_last_fence(queue); - /* Cancel any pending hang detection work and cleanup */ - if (queue->hang_detect_fence) { - cancel_delayed_work_sync(&queue->hang_detect_work); - queue->hang_detect_fence = NULL; - } + r = amdgpu_bo_reserve(queue->db_obj.obj, true); if (!r) { amdgpu_bo_unpin(queue->db_obj.obj); From 4f28b4930f8ebc17eec27a589cac3588911dce86 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Fri, 21 Feb 2025 14:45:19 +0100 Subject: [PATCH 1902/2070] drm/amdgpu: move devcoredump generation to a worker MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the way drm_coredump_printer is used based on its documentation and Xe's code: the main idea is to generate the final version in one go and then use memcpy to return the chunks requested by the caller of amdgpu_devcoredump_read. The generation is moved to a separate worker thread. This cuts the time to copy the dump from 40s to ~0s on my machine. --- v3: - removed adev->coredump_in_progress and instead use work as the synchronisation mechanism - use kvfree instead of kfree --- Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Alex Deucher Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++ .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 83 +++++++++++++++++-- .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h | 7 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + 4 files changed, 91 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index aa9969b21d314..51a1c8d92f2f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -328,6 +328,7 @@ struct kfd_vm_fault_info; struct amdgpu_hive_info; struct amdgpu_reset_context; struct amdgpu_reset_control; +struct amdgpu_coredump_info; enum amdgpu_cp_irq { AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, @@ -1176,6 +1177,11 @@ struct amdgpu_device { struct amdgpu_reset_domain *reset_domain; +#ifdef CONFIG_DEV_COREDUMP + struct amdgpu_coredump_info *coredump; + struct work_struct coredump_work; +#endif + struct mutex benchmark_mutex; bool scpm_enabled; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index fb66d0d5a0a33..bbb5afd67b490 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -32,8 +32,13 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, bool vram_lost, struct amdgpu_job *job) { } +void amdgpu_coredump_init(struct amdgpu_device *adev) +{ +} #else +#define AMDGPU_CORE_DUMP_SIZE_MAX (256 * 1024 * 1024) + const char *hw_ip_names[MAX_HWIP] = { [GC_HWIP] = "GC", [HDP_HWIP] = "HDP", @@ -196,11 +201,9 @@ static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev, } static ssize_t -amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, - void *data, size_t datalen) +amdgpu_devcoredump_format(char *buffer, size_t count, struct amdgpu_coredump_info *coredump) { struct drm_printer p; - struct amdgpu_coredump_info *coredump = data; struct drm_print_iterator iter; struct amdgpu_vm_fault_info *fault_info; struct amdgpu_ip_block *ip_block; @@ -208,7 +211,6 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, iter.data = buffer; iter.offset = 0; - iter.start = offset; iter.remain = count; p = drm_coredump_printer(&iter); @@ -322,9 +324,63 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, return count - iter.remain; } +static ssize_t +amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, + void *data, size_t datalen) +{ + struct amdgpu_coredump_info *coredump = data; + ssize_t byte_copied; + + if (!coredump) + return -ENODEV; + + if (!coredump->formatted) + return -ENODEV; + + if (offset >= coredump->formatted_size) + return 0; + + byte_copied = count < coredump->formatted_size - offset ? count : + coredump->formatted_size - offset; + memcpy(buffer, coredump->formatted + offset, byte_copied); + + return byte_copied; +} + static void amdgpu_devcoredump_free(void *data) { - kfree(data); + struct amdgpu_coredump_info *coredump = data; + + kvfree(coredump->formatted); + kvfree(data); +} + +static void amdgpu_devcoredump_deferred_work(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, typeof(*adev), coredump_work); + struct amdgpu_coredump_info *coredump = adev->coredump; + + /* Do a one-time preparation of the coredump output because + * repeatingly calling drm_coredump_printer is very slow. + */ + coredump->formatted_size = amdgpu_devcoredump_format( + NULL, AMDGPU_CORE_DUMP_SIZE_MAX, coredump); + coredump->formatted = kvzalloc(coredump->formatted_size, GFP_KERNEL); + if (!coredump->formatted) { + amdgpu_devcoredump_free(coredump); + goto end; + } + + amdgpu_devcoredump_format(coredump->formatted, coredump->formatted_size, coredump); + + /* If there's an existing coredump for this device, the free function will be + * called immediately so coredump might be invalid after the call to dev_coredumpm. + */ + dev_coredumpm(coredump->adev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT, + amdgpu_devcoredump_read, amdgpu_devcoredump_free); + +end: + adev->coredump = NULL; } void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, @@ -334,6 +390,10 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, struct amdgpu_coredump_info *coredump; struct drm_sched_job *s_job; + /* No need to generate a new coredump if there's one in progress already. */ + if (work_pending(&adev->coredump_work)) + return; + coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT); if (!coredump) return; @@ -360,11 +420,20 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, ktime_get_ts64(&coredump->reset_time); - dev_coredumpm(dev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT, - amdgpu_devcoredump_read, amdgpu_devcoredump_free); + /* Update the current coredump pointer (no lock needed, this function can only be called + * from a single thread) + */ + adev->coredump = coredump; + /* Kick off coredump formatting to a worker thread. */ + queue_work(system_unbound_wq, &adev->coredump_work); drm_info(dev, "AMDGPU device coredump file has been created\n"); drm_info(dev, "Check your /sys/class/drm/card%d/device/devcoredump/data\n", dev->primary->index); } + +void amdgpu_coredump_init(struct amdgpu_device *adev) +{ + INIT_WORK(&adev->coredump_work, amdgpu_devcoredump_deferred_work); +} #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h index ef9772c6bcc9e..b3582d0b4ca43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h @@ -35,12 +35,19 @@ struct amdgpu_coredump_info { struct amdgpu_device *adev; struct amdgpu_task_info reset_task_info; struct timespec64 reset_time; + bool skip_vram_check; bool reset_vram_lost; struct amdgpu_ring *ring; + /* Readable form of coredevdump, generate once to speed up + * reading it (see drm_coredump_printer's documentation). + */ + ssize_t formatted_size; + char *formatted; }; #endif void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, bool vram_lost, struct amdgpu_job *job); +void amdgpu_coredump_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 71018e09e55c7..2f018f1c71952 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3821,6 +3821,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); INIT_WORK(&adev->userq_reset_work, amdgpu_userq_reset_work); + amdgpu_coredump_init(adev); + adev->gfx.gfx_off_req_count = 1; adev->gfx.gfx_off_residency = 0; adev->gfx.gfx_off_entrycount = 0; From 57fddb8607d7abe7eaff9a9c46950cfac94b6f14 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 22 Oct 2025 18:16:51 +0530 Subject: [PATCH 1903/2070] drm/amd/ras: Fix NULL deref in ras_core_ras_interrupt_detected() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a NULL pointer dereference when ras_core is NULL and ras_core->dev is accessed in the error path. Fixes: 2ebcf78447ca ("drm/amd/ras: Add rascore unified interface function") Reported by: Dan Carpenter Cc: YiPeng Chai Cc: Tao Zhou Cc: Hawking Zhang Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 10cd398d4ae23..b019e47233072 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -550,7 +550,9 @@ bool ras_core_ras_interrupt_detected(struct ras_core_context *ras_core) ras_core->sys_fn->detect_ras_interrupt) return ras_core->sys_fn->detect_ras_interrupt(ras_core); - RAS_DEV_ERR(ras_core->dev, "Failed to detect ras interrupt!\n"); + if (ras_core && ras_core->dev) + RAS_DEV_ERR(ras_core->dev, "Failed to detect ras interrupt!\n"); + return false; } From ca0e3c76f5c4c419c8b9b220bf7092acef2da137 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 12 Mar 2026 19:29:54 +0530 Subject: [PATCH 1904/2070] drm/amdgpu: Add default case in DVI mode validation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_connector_dvi_mode_valid() assigns max_digital_pixel_clock_khz based on connector_object_id using a switch statement that lacks a default case. In practice this code path should never be hit because the existing cases already cover all digital connector types that this function is used for. This is also legacy display code which is not used for new hardware. Add a default case returning MODE_BAD to make the switch exhaustive and silence the static analyzer smatch error. The new branch is effectively defensive and should never be reached during normal operation. Fixes: 585b2f685c56 ("drm/amdgpu: Respect max pixel clock for HDMI and DVI-D (v2)") Cc: Dan Carpenter Cc: Timur Kristóf Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 05e71af1c78c8..90d77ac3a209d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1302,6 +1302,8 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; break; + default: + return MODE_BAD; } /* When the display EDID claims that it's an HDMI display, From 41d6f1b50cd379408c2fd31d2fb2e1bd11207c3c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:22:43 -0500 Subject: [PATCH 1905/2070] drm/amdgpu/mmhub2.0: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c index a0cc8e218ca1e..534cb4c544dc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c @@ -154,14 +154,17 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(2, 0, 0): case IP_VERSION(2, 0, 2): - mmhub_cid = mmhub_client_ids_navi1x[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_navi1x) ? + mmhub_client_ids_navi1x[cid][rw] : NULL; break; case IP_VERSION(2, 1, 0): case IP_VERSION(2, 1, 1): - mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_sienna_cichlid) ? + mmhub_client_ids_sienna_cichlid[cid][rw] : NULL; break; case IP_VERSION(2, 1, 2): - mmhub_cid = mmhub_client_ids_beige_goby[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_beige_goby) ? + mmhub_client_ids_beige_goby[cid][rw] : NULL; break; default: mmhub_cid = NULL; From bc3061377b46b4a56376005c8b04ded1a51006ab Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:24:10 -0500 Subject: [PATCH 1906/2070] drm/amdgpu/mmhub2.3: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c index 5eb8122e27469..ceb2f6b46de52 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c @@ -94,7 +94,8 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, case IP_VERSION(2, 3, 0): case IP_VERSION(2, 4, 0): case IP_VERSION(2, 4, 1): - mmhub_cid = mmhub_client_ids_vangogh[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vangogh) ? + mmhub_client_ids_vangogh[cid][rw] : NULL; break; default: mmhub_cid = NULL; From e475fa2a05741a271f871c94042505eda2828121 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:24:35 -0500 Subject: [PATCH 1907/2070] drm/amdgpu/mmhub3.0.1: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c index 910337dc28d10..14a742d3a99d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c @@ -117,7 +117,8 @@ mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(3, 0, 1): - mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_1) ? + mmhub_client_ids_v3_0_1[cid][rw] : NULL; break; default: mmhub_cid = NULL; From 3ef653590bbd77ccb8a3334ee592ff4f352c11f4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:25:09 -0500 Subject: [PATCH 1908/2070] drm/amdgpu/mmhub3.0.2: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c index f0f182f033b98..e1f07f2a18527 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c @@ -108,7 +108,8 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_2) ? + mmhub_client_ids_v3_0_2[cid][rw] : NULL; dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", From 4d2ce318216eeaccbf26084f6e09e3ec63a4df3a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:25:30 -0500 Subject: [PATCH 1909/2070] drm/amdgpu/mmhub3.0: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c index 7d5242df58a51..ab966e69a342a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c @@ -110,7 +110,8 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 1): - mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_0) ? + mmhub_client_ids_v3_0_0[cid][rw] : NULL; break; default: mmhub_cid = NULL; From fb2b9e67a787cd73e126cd7e786ff26017d2d9aa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:25:56 -0500 Subject: [PATCH 1910/2070] drm/amdgpu/mmhub4.1.0: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c index 951998454b257..88bfe321f83aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c @@ -102,7 +102,8 @@ mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, status); switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(4, 1, 0): - mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_1_0) ? + mmhub_client_ids_v4_1_0[cid][rw] : NULL; break; default: mmhub_cid = NULL; From fbb525d707dd5abd2e4b774241b056fac6530ed2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Mar 2026 17:26:17 -0500 Subject: [PATCH 1911/2070] drm/amdgpu/mmhub4.2.0: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index 97a00075aa7aa..2fb82e022c79b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -728,7 +728,8 @@ mmhub_v4_2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, status); switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(4, 2, 0): - mmhub_cid = mmhub_client_ids_v4_2_0[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_2_0) ? + mmhub_client_ids_v4_2_0[cid][rw] : NULL; break; default: mmhub_cid = NULL; From b9311a9d35204029a4744d874665a6d1a59f8a1b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Mar 2026 15:51:08 -0400 Subject: [PATCH 1912/2070] drm/amdgpu/gmc9.0: add bounds checking for cid The value should never exceed the array size as those are the only values the hardware is expected to return, but add checks anyway. Cc: Benjamin Cheng Reviewed-by: Benjamin Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index aa95cb4818ee1..13caa47e3f38d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -662,28 +662,35 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, } else { switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(9, 0, 0): - mmhub_cid = mmhub_client_ids_vega10[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega10) ? + mmhub_client_ids_vega10[cid][rw] : NULL; break; case IP_VERSION(9, 3, 0): - mmhub_cid = mmhub_client_ids_vega12[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega12) ? + mmhub_client_ids_vega12[cid][rw] : NULL; break; case IP_VERSION(9, 4, 0): - mmhub_cid = mmhub_client_ids_vega20[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega20) ? + mmhub_client_ids_vega20[cid][rw] : NULL; break; case IP_VERSION(9, 4, 1): - mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_arcturus) ? + mmhub_client_ids_arcturus[cid][rw] : NULL; break; case IP_VERSION(9, 1, 0): case IP_VERSION(9, 2, 0): - mmhub_cid = mmhub_client_ids_raven[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_raven) ? + mmhub_client_ids_raven[cid][rw] : NULL; break; case IP_VERSION(1, 5, 0): case IP_VERSION(2, 4, 0): - mmhub_cid = mmhub_client_ids_renoir[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_renoir) ? + mmhub_client_ids_renoir[cid][rw] : NULL; break; case IP_VERSION(1, 8, 0): case IP_VERSION(9, 4, 2): - mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_aldebaran) ? + mmhub_client_ids_aldebaran[cid][rw] : NULL; break; default: mmhub_cid = NULL; From d79be529d5b47ef79758cfd371bd11ed1383712a Mon Sep 17 00:00:00 2001 From: Pratap Nirujogi Date: Wed, 11 Mar 2026 12:15:09 -0400 Subject: [PATCH 1913/2070] drm/amdgpu: Fix ISP segfault issue in kernel v7.0 Add NULL pointer checks for dev->type before accessing dev->type->name in ISP genpd add/remove functions to prevent kernel crashes. This regression was introduced in v7.0 as the wakeup sources are registered using physical device instead of ACPI device. This led to adding wakeup source device as the first child of AMDGPU device without initializing dev-type variable, and resulted in segfault when accessed it in the amdgpu isp driver. Fixes: 057edc58aa59 ("ACPI: PM: Register wakeup sources under physical devices") Suggested-by: Bin Du Reviewed-by: Mario Limonciello Signed-off-by: Pratap Nirujogi --- drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c index 0002bcc6c4ec0..b0931932e3194 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c @@ -129,7 +129,7 @@ static int isp_genpd_add_device(struct device *dev, void *data) if (!pdev) return -EINVAL; - if (!dev->type->name) { + if (!dev->type || !dev->type->name) { drm_dbg(&adev->ddev, "Invalid device type to add\n"); goto exit; } @@ -165,7 +165,7 @@ static int isp_genpd_remove_device(struct device *dev, void *data) if (!pdev) return -EINVAL; - if (!dev->type->name) { + if (!dev->type || !dev->type->name) { drm_dbg(&adev->ddev, "Invalid device type to remove\n"); goto exit; } From fca2b8387a69253fe906d30369fb9c2ab220792d Mon Sep 17 00:00:00 2001 From: Leo Li Date: Fri, 13 Mar 2026 14:22:41 -0400 Subject: [PATCH 1914/2070] drm/amdgpu/atomfirmware: Add LpDDR5x and new fields for info v2_3 [Why] Newer DCN bandwidth calculations require new definitions. [How] Add new fields cpu_id and vram_bit_width for atom_integrated_system_info_v2_3, and add a memtype for LpDDR5x. Reviewed-by: Alex Hung Signed-off-by: Leo Li --- drivers/gpu/drm/amd/include/atomfirmware.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 18f9642a42eed..62f7ed0b20667 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1695,7 +1695,9 @@ struct atom_integrated_system_info_v2_3 { uint8_t gpu_package_id; struct edp_info_table edp1_info; struct edp_info_table edp2_info; - uint32_t reserved2[8]; + uint32_t cpuid; + uint32_t vram_bit_width; + uint32_t reserved2[6]; struct atom_external_display_connection_info extdispconninfo; uint8_t UMACarveoutVersion; uint8_t UMACarveoutIndexMax; @@ -1770,6 +1772,7 @@ enum atom_dmi_t17_mem_type_def{ Hbm2MemType, ///< Assign 33 to HBM2 Ddr5MemType, ///< Assign 34 to DDR5 LpDdr5MemType, ///< Assign 35 to LPDDR5 + LpDdr5xMemType, ///< Assign 36 to LPDDR5x }; From 436092f28285c025261f35ae469854302632190d Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 13 Mar 2026 13:12:33 +0800 Subject: [PATCH 1915/2070] drm/amdgpu: validate fence_count in wait_fences ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an early parameter check in amdgpu_cs_wait_fences_ioctl() to reject a zero fence_count with -EINVAL. dma_fence_wait_any_timeout() requires count > 0. When userspace passes fence_count == 0, the call propagates down to dma_fence core which does not expect a zero-length array and triggers a WARN_ON. Return -EINVAL immediately so the caller gets a clear error instead of hitting an unexpected warning in the DMA fence subsystem. No functional change for well-formed userspace callers. v2: - Reworked commit message to clarify the parameter validation rationale - Removed verbose crash log from commit description - Simplified inline code comment Reviewed-by: Vitaly Prosyak Reviewed-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index eaec1ec52f5d9..4ba772eddc698 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1893,6 +1893,13 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_amdgpu_fence *fences; int r; + /* + * fence_count must be non-zero; dma_fence_wait_any_timeout() + * does not accept an empty fence array. + */ + if (!wait->in.fence_count) + return -EINVAL; + /* Get the fences from userspace */ fences = memdup_array_user(u64_to_user_ptr(wait->in.fences), wait->in.fence_count, From bbadc4d4d428b158a759b34783af99243c16f928 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 15 Mar 2026 11:29:41 +0530 Subject: [PATCH 1916/2070] drm/amd/ras: Fix NULL deref in ras_core_get_utc_second_timestamp() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ras_core_get_utc_second_timestamp() retrieves the current UTC timestamp (in seconds since the Unix epoch) through a platform-specific RAS system callback and is used for timestamping RAS error events. The function checks ras_core in the conditional statement before calling the sys_fn callback. However, when the condition fails, the function prints an error message using ras_core->dev. If ras_core is NULL, this can lead to a potential NULL pointer dereference when accessing ras_core->dev. Add an early NULL check for ras_core at the beginning of the function and return 0 when the pointer is not valid. This prevents the dereference and makes the control flow clearer. Fixes: 13c91b5b4378 ("drm/amd/ras: Add rascore unified interface function") Cc: YiPeng Chai Cc: Dan Carpenter Cc: Tao Zhou Cc: Hawking Zhang Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: YiPeng Chai Change-Id: Ia36e81b7d4fa592362604e031f84b1d877bb463f --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index b019e47233072..5d5d2d6430d12 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -527,8 +527,11 @@ bool ras_core_is_enabled(struct ras_core_context *ras_core) uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core) { - if (ras_core && ras_core->sys_fn && - ras_core->sys_fn->get_utc_second_timestamp) + if (!ras_core) + return 0; + + if (ras_core->sys_fn && + ras_core->sys_fn->get_utc_second_timestamp) return ras_core->sys_fn->get_utc_second_timestamp(ras_core); RAS_DEV_ERR(ras_core->dev, "Failed to get system timestamp!\n"); From 4a25f97039d43ed0525025bc617c0b0faa5da0fd Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 12 Mar 2026 14:07:36 +0530 Subject: [PATCH 1917/2070] drm/amdgpu: Drop unreachable return in amdgpu_reg_get_smn_base64() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_reg_get_smn_base64() returns from all control-flow paths inside the !adev->reg.smn.get_smn_base fallback path. For version == 1, the function returns the base address from amdgpu_reg_smn_v1_0_get_base(). For all other versions, the default switch branch emits a dev_err_once() and returns 0. The trailing return 0 after the switch is therefore unreachable and is reported by Smatch as dead code: drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c:317 amdgpu_reg_get_smn_base64() warn: ignoring unreachable code Remove the redundant return statement. Fixes: 37be67c441ef ("drm/amdgpu: Add smn callbacks to register block") Cc: Dan Carpenter Cc: Lijo Lazar Cc: Hawking Zhang Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Lijo Lazar Change-Id: I7a4280c2ca9fb9a0ce975c954f8aafd5a9cf96c7 --- drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index bf8645390bdc2..540040c76058b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -314,7 +314,6 @@ uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, "SMN base address query not supported for this device\n"); return 0; } - return 0; } return adev->reg.smn.get_smn_base(adev, block, die_inst); } From 1d2cb93cd4ca2ca620bbc533bab96b77e4f974a9 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 28 Jan 2026 16:30:01 +0800 Subject: [PATCH 1918/2070] drm/amd/pm: Add fru eeprom info support Add fru eeprom info support for smu_v15_0_8 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c index b0082aa7f3c61..c5178e2b794d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c @@ -106,6 +106,7 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr) *fru_addr = FRU_EEPROM_MADDR_8; return true; case IP_VERSION(13, 0, 12): + case IP_VERSION(15, 0, 8): if (fru_addr) *fru_addr = FRU_EEPROM_MADDR_INV; return true; From 8faf89dbe7747cda93fac9a4194549d81b28f6f4 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Mon, 16 Mar 2026 09:40:47 +0800 Subject: [PATCH 1919/2070] drm/amd/amdgpu: Fix build errors due to declarations after labels In C90 (which the kernel uses with -std=gnu89), declarations must appear at the beginning of a block and cannot follow a label. The switch cases in amdgpu_discovery.c and gmc_v12_1.c contained variable declarations immediately after case labels, causing the compiler to error: drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c:533:3: error: a label can only be part of a statement and a declaration is not a statement Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index f117a09252edc..7ea7b9c30bca9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -527,10 +527,11 @@ static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, unsigned int mtype, mtype_local, mtype_remote; bool snoop = false; bool is_local = false; + bool is_aid_a1; switch (gc_ip_version) { - case IP_VERSION(12, 1, 0): { - bool is_aid_a1 = (adev->rev_id & 0x10); + case IP_VERSION(12, 1, 0): + is_aid_a1 = (adev->rev_id & 0x10); mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC; mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC; @@ -556,7 +557,6 @@ static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, mtype = is_local ? mtype_local : mtype_remote; } break; - } default: if (uncached || coherent) mtype = MTYPE_UC; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index dc93ffb74647d..1ddccf386ad7e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1224,6 +1224,7 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, bool coherent = flags & (KFD_IOCTL_SVM_FLAG_COHERENT | KFD_IOCTL_SVM_FLAG_EXT_COHERENT); bool ext_coherent = flags & KFD_IOCTL_SVM_FLAG_EXT_COHERENT; unsigned int mtype_local, mtype_remote; + bool is_aid_a1, is_local; if (domain == SVM_RANGE_VRAM_DOMAIN) bo_node = prange->svm_bo->node; @@ -1310,9 +1311,9 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, case IP_VERSION(12, 0, 1): mapping_flags |= AMDGPU_VM_MTYPE_NC; break; - case IP_VERSION(12, 1, 0): { - bool is_aid_a1 = (node->adev->rev_id & 0x10); - bool is_local = (domain == SVM_RANGE_VRAM_DOMAIN) && + case IP_VERSION(12, 1, 0): + is_aid_a1 = (node->adev->rev_id & 0x10); + is_local = (domain == SVM_RANGE_VRAM_DOMAIN) && (bo_node->adev == node->adev); mtype_local = amdgpu_mtype_local == 0 ? AMDGPU_VM_MTYPE_RW : @@ -1330,7 +1331,6 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, mapping_flags |= mtype_remote; } break; - } default: mapping_flags |= coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; From 93a6d049234afe4e805c6c83e8f6a98ef9069ce4 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 16 Mar 2026 13:54:19 +0800 Subject: [PATCH 1920/2070] drm/amdkcl: update the config.h Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 29a973b0a74b7..a46c8c22eea1e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -635,7 +635,7 @@ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 /* drm_gem_dmabuf_vmap() has struct iosys_map arg */ -/* #undef HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG */ +#define HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG 1 /* drm_gem_is_imported() is available */ #define HAVE_DRM_GEM_IS_IMPORTED 1 From a43383512c55ef2eb63053fcdca4e610950d5429 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sun, 30 Nov 2025 19:45:28 +0800 Subject: [PATCH 1921/2070] drm/amd/pm: Update pm attributes Update pm attributes show/hide for gc_v12_1_0 v2: Use multi-aid check (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 36 +++++++++--------------------- 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 474624ed42ad3..73b9ad7e8bbce 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -1910,8 +1910,6 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { - uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); - *states = ATTR_STATE_SUPPORTED; if (!amdgpu_dpm_is_overdrive_supported(adev)) { @@ -1919,10 +1917,8 @@ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdg return 0; } - /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0 SRIOV/BM support */ - if (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0)) { + /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0, 12.1.0 SRIOV/BM support */ + if (amdgpu_is_multi_aid(adev)) { if (amdgpu_sriov_multi_vf_mode(adev)) *states = ATTR_STATE_UNSUPPORTED; return 0; @@ -2000,9 +1996,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd gc_ver == IP_VERSION(11, 5, 0) || gc_ver == IP_VERSION(11, 0, 2) || gc_ver == IP_VERSION(11, 0, 3) || - gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) + amdgpu_is_multi_aid(adev))) *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2023,9 +2017,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd gc_ver == IP_VERSION(11, 5, 0) || gc_ver == IP_VERSION(11, 0, 2) || gc_ver == IP_VERSION(11, 0, 3) || - gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) + amdgpu_is_multi_aid(adev))) *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2035,9 +2027,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { if (gc_ver == IP_VERSION(9, 4, 2) || - gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0)) + amdgpu_is_multi_aid(adev)) *states = ATTR_STATE_UNSUPPORTED; } @@ -2651,6 +2641,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ case IP_VERSION(11, 0, 3): case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): + case IP_VERSION(12, 1, 0): *states = ATTR_STATE_SUPPORTED; break; default: @@ -3732,8 +3723,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, /* Skip crit temp on APU */ if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || - (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) && + amdgpu_is_multi_aid(adev)) && (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) return 0; @@ -3815,18 +3805,14 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ - (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) && + amdgpu_is_multi_aid(adev)) && (attr == &sensor_dev_attr_in0_input.dev_attr.attr || attr == &sensor_dev_attr_in0_label.dev_attr.attr)) return 0; /* only APUs other than gc 9,4,3 have vddnb */ if ((!(adev->flags & AMD_IS_APU) || - (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) && + amdgpu_is_multi_aid(adev)) && (attr == &sensor_dev_attr_in1_input.dev_attr.attr || attr == &sensor_dev_attr_in1_label.dev_attr.attr)) return 0; @@ -3855,9 +3841,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; /* hotspot temperature for gc 9,4,3*/ - if (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0)) { + if (amdgpu_is_multi_aid(adev)) { if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || attr == &sensor_dev_attr_temp1_label.dev_attr.attr) From 50cd84f8b6e35b05b5e9984ce184772317e36ff0 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 31 Jan 2026 18:05:31 +0800 Subject: [PATCH 1922/2070] drm/amd/pm: Add mutex lock for metrics table Add metrics table mutex lock in smu table context struct Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 99eae4ab839e8..6eed4d6cc1d4a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -389,6 +389,7 @@ struct smu_table_context { void *metrics_table; void *clocks_table; void *watermarks_table; + struct mutex metrics_lock; void *max_sustainable_clocks; struct smu_bios_boot_up_values boot_values; From 7ce3ada107b679c043d0328efa7f2b6422c10a18 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Wed, 21 Jan 2026 10:02:11 -0500 Subject: [PATCH 1923/2070] drm/amdgpu: Add VCN v5_0_2 Add support for VCN_5_0_2 v2: squash in RRMT enable bit fix from Sonny (Alex) v3: sqaush in doorbell enablement patch (Alex) v4: drop some bringup leftovers (Alex) Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c | 1219 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h | 29 + 5 files changed, 1259 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 7d01841f803be..2af58ad2b1b21 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -213,6 +213,7 @@ amdgpu-y += \ vcn_v4_0_5.o \ vcn_v5_0_0.o \ vcn_v5_0_1.o \ + vcn_v5_0_2.o \ amdgpu_jpeg.o \ jpeg_v1_0.o \ jpeg_v2_0.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 0435e739059ab..edf486c19e2de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -112,6 +112,7 @@ #include "smuio_v15_0_8.h" #include "vcn_v5_0_0.h" #include "vcn_v5_0_1.h" +#include "vcn_v5_0_2.h" #include "jpeg_v5_0_0.h" #include "jpeg_v5_0_1.h" #include "jpeg_v5_3_0.h" @@ -2668,6 +2669,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); break; + case IP_VERSION(5, 0, 2): + amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); + break; default: dev_err(adev->dev, "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 75ae9b429420e..03d95dca93d75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -63,6 +63,7 @@ #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" +#define FIRMWARE_VCN5_0_2 "amdgpu/vcn_5_0_2.bin" #define FIRMWARE_VCN5_3_0 "amdgpu/vcn_5_3_0.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); @@ -91,6 +92,7 @@ MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); +MODULE_FIRMWARE(FIRMWARE_VCN5_0_2); MODULE_FIRMWARE(FIRMWARE_VCN5_3_0); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); @@ -1095,7 +1097,8 @@ int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) long r; if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) && - (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1))) { + (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1)) && + (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 2))) { r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); if (r) goto error; @@ -1132,7 +1135,8 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i) return; if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) || - amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1)) + amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1) || + amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 2)) && (i > 0)) return; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c new file mode 100644 index 0000000000000..c3d3cc0230580 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c @@ -0,0 +1,1219 @@ +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "amdgpu_vcn.h" +#include "amdgpu_pm.h" +#include "soc15.h" +#include "soc15d.h" +#include "soc15_hw_ip.h" +#include "vcn_v2_0.h" +#include "vcn_v4_0_3.h" + +#include "vcn/vcn_5_0_0_offset.h" +#include "vcn/vcn_5_0_0_sh_mask.h" +#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" +#include "vcn_v5_0_0.h" +#include "vcn_v5_0_1.h" +#include "vcn_v5_0_2.h" + +#include + +static void vcn_v5_0_2_set_unified_ring_funcs(struct amdgpu_device *adev); +static void vcn_v5_0_2_set_irq_funcs(struct amdgpu_device *adev); +static int vcn_v5_0_2_set_pg_state(struct amdgpu_vcn_inst *vinst, + enum amd_powergating_state state); +static void vcn_v5_0_2_unified_ring_set_wptr(struct amdgpu_ring *ring); + +/** + * vcn_v5_0_2_early_init - set function pointers and load microcode + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Set ring and irq function pointers + * Load microcode from filesystem + */ +static int vcn_v5_0_2_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, r; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) + /* re-use enc ring as unified ring */ + adev->vcn.inst[i].num_enc_rings = 1; + + vcn_v5_0_2_set_unified_ring_funcs(adev); + vcn_v5_0_2_set_irq_funcs(adev); + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + adev->vcn.inst[i].set_pg_state = vcn_v5_0_2_set_pg_state; + + r = amdgpu_vcn_early_init(adev, i); + if (r) + return r; + } + + return 0; +} + +static void vcn_v5_0_2_fw_shared_init(struct amdgpu_device *adev, int inst_idx) +{ + struct amdgpu_vcn5_fw_shared *fw_shared; + + fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + + if (fw_shared->sq.is_enabled) + return; + fw_shared->present_flag_0 = + cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); + fw_shared->sq.is_enabled = 1; + + if (amdgpu_vcnfw_log) + amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); +} + +/** + * vcn_v5_0_2_sw_init - sw init for VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Load firmware and sw initialization + */ +static int vcn_v5_0_2_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, r, vcn_inst; + + /* VCN UNIFIED TRAP */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_VCN, + VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); + if (r) + return r; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + vcn_inst = GET_INST(VCN, i); + + r = amdgpu_vcn_sw_init(adev, i); + if (r) + return r; + + amdgpu_vcn_setup_ucode(adev, i); + + r = amdgpu_vcn_resume(adev, i); + if (r) + return r; + + ring = &adev->vcn.inst[i].ring_enc[0]; + ring->use_doorbell = true; + + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 32 * vcn_inst; + + ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); + sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); + + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, + AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); + if (r) + return r; + + vcn_v5_0_2_fw_shared_init(adev, i); + } + + /* TODO: Add queue reset mask when FW fully supports it */ + adev->vcn.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); + + return amdgpu_vcn_sysfs_reset_mask_init(adev); +} + +/** + * vcn_v5_0_2_sw_fini - sw fini for VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * VCN suspend and free up sw allocation + */ +static int vcn_v5_0_2_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, r, idx; + + if (drm_dev_enter(adev_to_drm(adev), &idx)) { + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + struct amdgpu_vcn5_fw_shared *fw_shared; + + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->present_flag_0 = 0; + fw_shared->sq.is_enabled = 0; + } + + drm_dev_exit(idx); + } + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + r = amdgpu_vcn_suspend(adev, i); + if (r) + return r; + } + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + amdgpu_vcn_sw_fini(adev, i); + + amdgpu_vcn_sysfs_reset_mask_fini(adev); + + kfree(adev->vcn.ip_dump); //TODO check + + return 0; +} + +/** + * vcn_v5_0_2_hw_init - start and test VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int vcn_v5_0_2_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, r, vcn_inst; + uint32_t tmp; + + if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x200) + adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + vcn_inst = GET_INST(VCN, i); + ring = &adev->vcn.inst[i].ring_enc[0]; + + /* Remove Video Tiles antihang mechanism */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); + tmp &= (~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); + + if (ring->use_doorbell) + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 11 * vcn_inst), + adev->vcn.inst[i].aid_id); + + /* Re-init fw_shared, if required */ + vcn_v5_0_2_fw_shared_init(adev, i); + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + } + + return 0; +} + +/** + * vcn_v5_0_2_hw_fini - stop the hardware block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Stop the VCN block, mark ring as not ready any more + */ +static int vcn_v5_0_2_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; + + cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); + if (vinst->cur_state != AMD_PG_STATE_GATE) + vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); + } + + return 0; +} + +/** + * vcn_v5_0_2_suspend - suspend VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * HW fini and suspend VCN block + */ +static int vcn_v5_0_2_suspend(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r, i; + + r = vcn_v5_0_2_hw_fini(ip_block); + if (r) + return r; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + r = amdgpu_vcn_suspend(ip_block->adev, i); + if (r) + return r; + } + + return r; +} + +/** + * vcn_v5_0_2_resume - resume VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Resume firmware and hw init VCN block + */ +static int vcn_v5_0_2_resume(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r, i; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; + + if (amdgpu_in_reset(adev)) + vinst->cur_state = AMD_PG_STATE_GATE; + + r = amdgpu_vcn_resume(ip_block->adev, i); + if (r) + return r; + } + + r = vcn_v5_0_2_hw_init(ip_block); + + return r; +} + +/** + * vcn_v5_0_2_mc_resume - memory controller programming + * + * @vinst: VCN instance + * + * Let the VCN memory controller know it's offsets + */ +static void vcn_v5_0_2_mc_resume(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int inst = vinst->inst; + uint32_t offset, size, vcn_inst; + const struct common_firmware_header *hdr; + + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; + size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + + vcn_inst = GET_INST(VCN, inst); + /* cache window 0: fw */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); + offset = 0; + } else { + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].gpu_addr)); + offset = size; + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, + AMDGPU_UVD_FIRMWARE_OFFSET >> 3); + } + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); + + /* cache window 1: stack */ + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); + + /* cache window 2: context */ + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); + + /* non-cache window */ + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, + AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); +} + +/** + * vcn_v5_0_2_mc_resume_dpg_mode - memory controller programming for dpg mode + * + * @vinst: VCN instance + * @indirect: indirectly write sram + * + * Let the VCN memory controller know it's offsets with dpg mode + */ +static void vcn_v5_0_2_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, + bool indirect) +{ + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + uint32_t offset, size; + const struct common_firmware_header *hdr; + + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; + size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + + /* cache window 0: fw */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + if (!indirect) { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + + inst_idx].tmr_mc_addr_lo), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + + inst_idx].tmr_mc_addr_hi), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); + } else { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); + } + offset = 0; + } else { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); + offset = size; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET0), + AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); + } + + if (!indirect) + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); + else + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); + + /* cache window 1: stack */ + if (!indirect) { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); + } else { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); + } + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); + + /* cache window 2: context */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + + AMDGPU_VCN_STACK_SIZE), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + + AMDGPU_VCN_STACK_SIZE), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); + + /* non-cache window */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), + AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); + + /* VCN global tiling registers */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); +} + +/** + * vcn_v5_0_2_disable_clock_gating - disable VCN clock gating + * + * @vinst: VCN instance + * + * Disable clock gating for VCN block + */ +static void vcn_v5_0_2_disable_clock_gating(struct amdgpu_vcn_inst *vinst) +{ +} + +/** + * vcn_v5_0_2_enable_clock_gating - enable VCN clock gating + * + * @vinst: VCN instance + * + * Enable clock gating for VCN block + */ +static void vcn_v5_0_2_enable_clock_gating(struct amdgpu_vcn_inst *vinst) +{ +} + +/** + * vcn_v5_0_2_pause_dpg_mode - VCN pause with dpg mode + * + * @vinst: VCN instance + * @new_state: pause state + * + * Pause dpg mode for VCN block + */ +static int vcn_v5_0_2_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, + struct dpg_pause_state *new_state) +{ + struct amdgpu_device *adev = vinst->adev; + uint32_t reg_data = 0; + int vcn_inst; + + vcn_inst = GET_INST(VCN, vinst->inst); + + /* pause/unpause if state is changed */ + if (vinst->pause_state.fw_based != new_state->fw_based) { + DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d %s\n", + vinst->pause_state.fw_based, new_state->fw_based, + new_state->fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE"); + reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { + /* pause DPG */ + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); + + /* wait for ACK */ + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + } else { + /* unpause DPG, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); + } + vinst->pause_state.fw_based = new_state->fw_based; + } + + return 0; +} + +/** + * vcn_v5_0_2_start_dpg_mode - VCN start with dpg mode + * + * @vinst: VCN instance + * @indirect: indirectly write sram + * + * Start VCN block with dpg mode + */ +static int vcn_v5_0_2_start_dpg_mode(struct amdgpu_vcn_inst *vinst, + bool indirect) +{ + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + struct amdgpu_vcn5_fw_shared *fw_shared = + adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_ring *ring; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; + int vcn_inst, ret; + uint32_t tmp; + + vcn_inst = GET_INST(VCN, inst_idx); + + /* disable register anti-hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, + ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + + /* enable dynamic power gating mode */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); + tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); + + if (indirect) { + adev->vcn.inst[inst_idx].dpg_sram_curr_addr = + (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; + /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ + WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, + adev->vcn.inst[inst_idx].aid_id, 0, true); + } + + /* enable VCPU clock */ + tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); + tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); + + /* disable master interrupt */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); + + /* setup regUVD_LMI_CTRL */ + tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | + UVD_LMI_CTRL__CRC_RESET_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + 0x00100000L); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); + + vcn_v5_0_2_mc_resume_dpg_mode(vinst, indirect); + + tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); + tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); + + /* enable LMI MC and UMC channels */ + tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); + + /* enable master interrupt */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_MASTINT_EN), + UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); + + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } + + /* resetting ring, fw should not check RB ring */ + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; + + /* Pause dpg */ + vcn_v5_0_2_pause_dpg_mode(vinst, &state); + + ring = &adev->vcn.inst[inst_idx].ring_enc[0]; + + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); + + ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + /* resetting done, fw can check RB ring */ + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); + + WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + /* Read DB_CTRL to flush the write DB_CTRL command. */ + RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); + + return 0; +} + +/** + * vcn_v5_0_2_start - VCN start + * + * @vinst: VCN instance + * + * Start VCN block + */ +static int vcn_v5_0_2_start(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int i = vinst->inst; + struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_ring *ring; + uint32_t tmp; + int j, k, r, vcn_inst; + + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) + return vcn_v5_0_2_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); + + vcn_inst = GET_INST(VCN, i); + + /* set VCN status busy */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; + WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); + + /* enable VCPU clock */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); + + /* disable master interrupt */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, + ~UVD_MASTINT_EN__VCPU_EN_MASK); + + /* enable LMI MC and UMC channels */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); + tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; + tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); + + /* setup regUVD_LMI_CTRL */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); + + vcn_v5_0_2_mc_resume(vinst); + + /* VCN global tiling registers */ + WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + + /* unblock VCPU register access */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); + + /* release VCPU reset to boot */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + + for (j = 0; j < 10; ++j) { + uint32_t status; + + for (k = 0; k < 100; ++k) { + status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); + if (status & 2) + break; + mdelay(1000); + if (amdgpu_emu_mode == 1) + msleep(520); + } + + if (amdgpu_emu_mode == 1) { + r = -1; + if (status & 2) { + r = 0; + break; + } + } else { + r = 0; + if (status & 2) + break; + + dev_err(adev->dev, + "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__BLK_RST_MASK, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + mdelay(10); + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + + mdelay(10); + r = -1; + } + } + + if (r) { + dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); + return r; + } + + /* enable master interrupt */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), + UVD_MASTINT_EN__VCPU_EN_MASK, + ~UVD_MASTINT_EN__VCPU_EN_MASK); + + /* clear the busy bit of VCN_STATUS */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); + + ring = &adev->vcn.inst[i].ring_enc[0]; + + WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + + /* Read DB_CTRL to flush the write DB_CTRL command. */ + RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); + + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); + + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); + ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); + + return 0; +} + +/** + * vcn_v5_0_2_stop_dpg_mode - VCN stop with dpg mode + * + * @vinst: VCN instance + * + * Stop VCN block with dpg mode + */ +static void vcn_v5_0_2_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + uint32_t tmp; + int vcn_inst; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; + + vcn_inst = GET_INST(VCN, inst_idx); + + /* Unpause dpg */ + vcn_v5_0_2_pause_dpg_mode(vinst, &state); + + /* Wait for power status to be 1 */ + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + + /* wait for read ptr to be equal to write ptr */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); + + /* disable dynamic power gating mode */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, + ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); +} + +/** + * vcn_v5_0_2_stop - VCN stop + * + * @vinst: VCN instance + * + * Stop VCN block + */ +static int vcn_v5_0_2_stop(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int i = vinst->inst; + struct amdgpu_vcn5_fw_shared *fw_shared; + uint32_t tmp; + int r = 0, vcn_inst; + + vcn_inst = GET_INST(VCN, i); + + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { + vcn_v5_0_2_stop_dpg_mode(vinst); + return 0; + } + + /* wait for vcn idle */ + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); + if (r) + return r; + + tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | + UVD_LMI_STATUS__READ_CLEAN_MASK | + UVD_LMI_STATUS__WRITE_CLEAN_MASK | + UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); + if (r) + return r; + + /* disable LMI UMC channel */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); + tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); + tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | + UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); + if (r) + return r; + + /* block VCPU register access */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), + UVD_RB_ARB_CTRL__VCPU_DIS_MASK, + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); + + /* reset VCPU */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__BLK_RST_MASK, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + + /* disable VCPU clock */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, + ~(UVD_VCPU_CNTL__CLK_EN_MASK)); + + /* apply soft reset */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); + tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); + tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); + + /* clear status */ + WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); + + return 0; +} + +/** + * vcn_v5_0_2_unified_ring_get_rptr - get unified read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware unified read pointer + */ +static uint64_t vcn_v5_0_2_unified_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); +} + +/** + * vcn_v5_0_2_unified_ring_get_wptr - get unified write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware unified write pointer + */ +static uint64_t vcn_v5_0_2_unified_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + if (ring->use_doorbell) + return *ring->wptr_cpu_addr; + else + return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); +} + +/** + * vcn_v5_0_2_unified_ring_set_wptr - set enc write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the enc write pointer to the hardware + */ +static void vcn_v5_0_2_unified_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + if (ring->use_doorbell) { + *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); + } else { + WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, + lower_32_bits(ring->wptr)); + } +} + +static const struct amdgpu_ring_funcs vcn_v5_0_2_unified_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_ENC, + .align_mask = 0x3f, + .nop = VCN_ENC_CMD_NO_OP, + .get_rptr = vcn_v5_0_2_unified_ring_get_rptr, + .get_wptr = vcn_v5_0_2_unified_ring_get_wptr, + .set_wptr = vcn_v5_0_2_unified_ring_set_wptr, + .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + + 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ + 5 + + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ + 1, /* vcn_v2_0_enc_ring_insert_end */ + .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ + .emit_ib = vcn_v2_0_enc_ring_emit_ib, + .emit_fence = vcn_v2_0_enc_ring_emit_fence, + .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, + .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, + .test_ring = amdgpu_vcn_enc_ring_test_ring, + .test_ib = amdgpu_vcn_unified_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_end = vcn_v2_0_enc_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vcn_ring_begin_use, + .end_use = amdgpu_vcn_ring_end_use, + .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, + .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, +}; + +/** + * vcn_v5_0_2_set_unified_ring_funcs - set unified ring functions + * + * @adev: amdgpu_device pointer + * + * Set unified ring functions + */ +static void vcn_v5_0_2_set_unified_ring_funcs(struct amdgpu_device *adev) +{ + int i, vcn_inst; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_2_unified_ring_vm_funcs; + adev->vcn.inst[i].ring_enc[0].me = i; + vcn_inst = GET_INST(VCN, i); + adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid; + } +} + +/** + * vcn_v5_0_2_is_idle - check VCN block is idle + * + * @ip_block: Pointer to the amdgpu_ip_block structure + * + * Check whether VCN block is idle + */ +static bool vcn_v5_0_2_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, ret = 1; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) + ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); + + return ret; +} + +/** + * vcn_v5_0_2_wait_for_idle - wait for VCN block idle + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Wait for VCN block idle + */ +static int vcn_v5_0_2_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, ret = 0; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, + UVD_STATUS__IDLE); + if (ret) + return ret; + } + + return ret; +} + +/** + * vcn_v5_0_2_set_clockgating_state - set VCN block clockgating state + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * @state: clock gating state + * + * Set VCN block clockgating state + */ +static int vcn_v5_0_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + bool enable = state == AMD_CG_STATE_GATE; + int i; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; + + if (enable) { + if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) + return -EBUSY; + vcn_v5_0_2_enable_clock_gating(vinst); + } else { + vcn_v5_0_2_disable_clock_gating(vinst); + } + } + + return 0; +} + +static int vcn_v5_0_2_set_pg_state(struct amdgpu_vcn_inst *vinst, + enum amd_powergating_state state) +{ + int ret = 0; + + if (state == vinst->cur_state) + return 0; + + if (state == AMD_PG_STATE_GATE) + ret = vcn_v5_0_2_stop(vinst); + else + ret = vcn_v5_0_2_start(vinst); + + if (!ret) + vinst->cur_state = state; + + return ret; +} + +/** + * vcn_v5_0_2_process_interrupt - process VCN block interrupt + * + * @adev: amdgpu_device pointer + * @source: interrupt sources + * @entry: interrupt entry from clients and sources + * + * Process VCN block interrupt + */ +static int vcn_v5_0_2_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t i, inst; + + i = node_id_to_phys_map[entry->node_id]; + + DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); + + for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) + if (adev->vcn.inst[inst].aid_id == i) + break; + + if (inst >= adev->vcn.num_vcn_inst) { + dev_WARN_ONCE(adev->dev, 1, + "Interrupt received for unknown VCN instance %d", + entry->node_id); + return 0; + } + + switch (entry->src_id) { + case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: + amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); + break; + default: + DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs vcn_v5_0_2_irq_funcs = { + .process = vcn_v5_0_2_process_interrupt, +}; + +/** + * vcn_v5_0_2_set_irq_funcs - set VCN block interrupt irq functions + * + * @adev: amdgpu_device pointer + * + * Set VCN block interrupt irq functions + */ +static void vcn_v5_0_2_set_irq_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) + adev->vcn.inst->irq.num_types++; + adev->vcn.inst->irq.funcs = &vcn_v5_0_2_irq_funcs; +} + +static const struct amd_ip_funcs vcn_v5_0_2_ip_funcs = { + .name = "vcn_v5_0_2", + .early_init = vcn_v5_0_2_early_init, + .late_init = NULL, + .sw_init = vcn_v5_0_2_sw_init, + .sw_fini = vcn_v5_0_2_sw_fini, + .hw_init = vcn_v5_0_2_hw_init, + .hw_fini = vcn_v5_0_2_hw_fini, + .suspend = vcn_v5_0_2_suspend, + .resume = vcn_v5_0_2_resume, + .is_idle = vcn_v5_0_2_is_idle, + .wait_for_idle = vcn_v5_0_2_wait_for_idle, + .check_soft_reset = NULL, + .pre_soft_reset = NULL, + .soft_reset = NULL, + .post_soft_reset = NULL, + .set_clockgating_state = vcn_v5_0_2_set_clockgating_state, + .set_powergating_state = vcn_set_powergating_state, +}; + +const struct amdgpu_ip_block_version vcn_v5_0_2_ip_block = { + .type = AMD_IP_BLOCK_TYPE_VCN, + .major = 5, + .minor = 0, + .rev = 2, + .funcs = &vcn_v5_0_2_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h new file mode 100644 index 0000000000000..461bdda91eb60 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h @@ -0,0 +1,29 @@ +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCN_v5_0_2_H__ +#define __VCN_v5_0_2_H__ + +extern const struct amdgpu_ip_block_version vcn_v5_0_2_ip_block; + +#endif /* __VCN_v5_0_2_H__ */ From 0d6422700ba40e28bcf120968e5bdaa50bd4e819 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Thu, 22 Jan 2026 13:23:48 -0500 Subject: [PATCH 1924/2070] drm/amdgpu: Add VCN_5_0_2 codecs capabilities support Support VCN_5_0_2 codec query Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 37552c91a8781..3952181c077e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -46,6 +46,39 @@ #define NORMALIZE_MID_REG_OFFSET(offset) \ (offset & 0x3FFFF) +static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { + .codec_count = 0, + .codec_array = NULL, +}; + +static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = { + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, +}; + +static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = { + .codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0), + .codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0, +}; + +static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { + case IP_VERSION(5, 0, 2): + if (encode) + *codecs = &vcn_5_0_2_video_codecs_encode_vcn0; + else + *codecs = &vcn_5_0_2_video_codecs_decode_vcn0; + return 0; + default: + return -EINVAL; + } +} + /* Initialized doorbells for amdgpu including multimedia * KFD can use all the rest in 2M doorbell bar */ static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) @@ -262,6 +295,7 @@ static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, .reset = soc_v1_0_asic_reset, .reset_method = &soc_v1_0_asic_reset_method, + .query_video_codecs = &soc_v1_0_query_video_codecs, }; static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) From e124e2b75e5bfb10602a48c41ebf56b8bf4a6900 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Fri, 23 Jan 2026 11:08:35 -0500 Subject: [PATCH 1925/2070] drm/amdgpu: Set VCN_5_0_2 DPG mode Set DPG flag for VCN_5_0_2 Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 3952181c077e6..709b1669b07bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -322,7 +322,7 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(12, 1, 0): adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS; - adev->pg_flags = 0; + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0x50; break; default: From d4254e0845bcbf425d3e3193d67c4234ffd3c2a3 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Wed, 21 Jan 2026 17:56:36 -0500 Subject: [PATCH 1926/2070] drm/amdgpu: Add JPEG_v5_0_2 IP block Add support for JPEG_5_0_2 v2: comment out RAS for now (Alex) v3: drop some bringup leftovers (Alex) Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 + drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c | 840 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h | 111 +++ 4 files changed, 954 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 2af58ad2b1b21..8eb09c66509da 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -224,6 +224,7 @@ amdgpu-y += \ jpeg_v4_0_5.o \ jpeg_v5_0_0.o \ jpeg_v5_0_1.o \ + jpeg_v5_0_2.o \ jpeg_v5_3_0.o # add VPE block diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index edf486c19e2de..257fb33e60e81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -115,6 +115,7 @@ #include "vcn_v5_0_2.h" #include "jpeg_v5_0_0.h" #include "jpeg_v5_0_1.h" +#include "jpeg_v5_0_2.h" #include "jpeg_v5_3_0.h" #include "amdgpu_ras_mgr.h" @@ -2671,6 +2672,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) break; case IP_VERSION(5, 0, 2): amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); + amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); break; default: dev_err(adev->dev, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c new file mode 100644 index 0000000000000..285c459379c4a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu.h" +#include "amdgpu_jpeg.h" +#include "amdgpu_pm.h" +#include "soc15.h" +#include "soc15d.h" +#include "jpeg_v4_0_3.h" +#include "jpeg_v5_0_2.h" +#include "mmsch_v5_0.h" + +#include "vcn/vcn_5_0_0_offset.h" +#include "vcn/vcn_5_0_0_sh_mask.h" +#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" + +static void jpeg_v5_0_2_set_dec_ring_funcs(struct amdgpu_device *adev); +static void jpeg_v5_0_2_set_irq_funcs(struct amdgpu_device *adev); +static int jpeg_v5_0_2_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state); +static void jpeg_v5_0_2_dec_ring_set_wptr(struct amdgpu_ring *ring); + +static int amdgpu_ih_srcid_jpeg[] = { + VCN_5_0__SRCID__JPEG_DECODE, + VCN_5_0__SRCID__JPEG1_DECODE, + VCN_5_0__SRCID__JPEG2_DECODE, + VCN_5_0__SRCID__JPEG3_DECODE, + VCN_5_0__SRCID__JPEG4_DECODE, + VCN_5_0__SRCID__JPEG5_DECODE, + VCN_5_0__SRCID__JPEG6_DECODE, + VCN_5_0__SRCID__JPEG7_DECODE, + VCN_5_0__SRCID__JPEG8_DECODE, + VCN_5_0__SRCID__JPEG9_DECODE, +}; + +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_2[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS), +}; + +static int jpeg_v5_0_2_core_reg_offset(u32 pipe) +{ + if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3) + return ((0x40 * pipe) - 0xc80); + else + return ((0x40 * pipe) - 0x440); +} + +/** + * jpeg_v5_0_2_early_init - set function pointers + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Set ring and irq function pointers + */ +static int jpeg_v5_0_2_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) + return -ENOENT; + + adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; + jpeg_v5_0_2_set_dec_ring_funcs(adev); + jpeg_v5_0_2_set_irq_funcs(adev); + + return 0; +} + +/** + * jpeg_v5_0_2_sw_init - sw init for JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Load firmware and sw initialization + */ +static int jpeg_v5_0_2_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, j, r, jpeg_inst; + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + /* JPEG TRAP */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, + amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); + if (r) + return r; + } + + r = amdgpu_jpeg_sw_init(adev); + if (r) + return r; + + r = amdgpu_jpeg_resume(adev); + if (r) + return r; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + jpeg_inst = GET_INST(JPEG, i); + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + ring->use_doorbell = false; + ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 1 + j + 11 * jpeg_inst; + sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); + r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, + AMDGPU_RING_PRIO_DEFAULT, NULL); + if (r) + return r; + + adev->jpeg.internal.jpeg_pitch[j] = + regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; + adev->jpeg.inst[i].external.jpeg_pitch[j] = + SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0, + (j ? jpeg_v5_0_2_core_reg_offset(j) : 0)); + } + } + + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_2, ARRAY_SIZE(jpeg_reg_list_5_0_2)); + if (r) + return r; + + adev->jpeg.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); + adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + r = amdgpu_jpeg_sysfs_reset_mask_init(adev); + + return r; +} + +/** + * jpeg_v5_0_2_sw_fini - sw fini for JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * JPEG suspend and free up sw allocation + */ +static int jpeg_v5_0_2_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_jpeg_suspend(adev); + if (r) + return r; + + amdgpu_jpeg_sysfs_reset_mask_fini(adev); + + r = amdgpu_jpeg_sw_fini(adev); + + return r; +} + +/** + * jpeg_v5_0_2_hw_init - start and test JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + */ +static int jpeg_v5_0_2_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, j, r, jpeg_inst, tmp; + + if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) + adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + jpeg_inst = GET_INST(JPEG, i); + ring = adev->jpeg.inst[i].ring_dec; + + /* Remove JPEG Tile antihang mechanism */ + tmp = RREG32_SOC15(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS); + tmp &= (~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); + WREG32_SOC15(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS, tmp); + + if (ring->use_doorbell) + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 11 * jpeg_inst, + adev->jpeg.inst[i].aid_id); + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + if (ring->use_doorbell) + WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL, + ring->pipe, + ring->doorbell_index << + VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + } + } + + return 0; +} + +/** + * jpeg_v5_0_2_hw_fini - stop the hardware block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Stop the JPEG block, mark ring as not ready any more + */ +static int jpeg_v5_0_2_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret = 0; + + cancel_delayed_work_sync(&adev->jpeg.idle_work); + + if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) + ret = jpeg_v5_0_2_set_powergating_state(ip_block, AMD_PG_STATE_GATE); + + return ret; +} + +/** + * jpeg_v5_0_2_suspend - suspend JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * HW fini and suspend JPEG block + */ +static int jpeg_v5_0_2_suspend(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = jpeg_v5_0_2_hw_fini(ip_block); + if (r) + return r; + + r = amdgpu_jpeg_suspend(adev); + + return r; +} + +/** + * jpeg_v5_0_2_resume - resume JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Resume firmware and hw init JPEG block + */ +static int jpeg_v5_0_2_resume(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_jpeg_resume(adev); + if (r) + return r; + + r = jpeg_v5_0_2_hw_init(ip_block); + + return r; +} + +static void jpeg_v5_0_2_init_inst(struct amdgpu_device *adev, int i) +{ + int jpeg_inst = GET_INST(JPEG, i); + + /* disable anti hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, + ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); + + /* keep the JPEG in static PG mode */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, + ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); + + /* MJPEG global tiling registers */ + WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + + /* enable JMI channel */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, + ~UVD_JMI_CNTL__SOFT_RESET_MASK); +} + +static void jpeg_v5_0_2_deinit_inst(struct amdgpu_device *adev, int i) +{ + int jpeg_inst = GET_INST(JPEG, i); + /* reset JMI */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), + UVD_JMI_CNTL__SOFT_RESET_MASK, + ~UVD_JMI_CNTL__SOFT_RESET_MASK); + + /* enable anti hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), + UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, + ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); +} + +static void jpeg_v5_0_2_init_jrbc(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 reg, data, mask; + int jpeg_inst = GET_INST(JPEG, ring->me); + int reg_offset = ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0; + + /* enable System Interrupt for JRBC */ + reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN); + if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) { + data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe; + mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe); + WREG32_P(reg, data, mask); + } else { + data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12); + mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12)); + WREG32_P(reg, data, mask); + } + + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_LMI_JRBC_RB_VMID, + reg_offset, 0); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_CNTL, + reg_offset, + (0x00000001L | 0x00000002L)); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, + reg_offset, lower_32_bits(ring->gpu_addr)); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, + reg_offset, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_RPTR, + reg_offset, 0); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_WPTR, + reg_offset, 0); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_CNTL, + reg_offset, 0x00000002L); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_SIZE, + reg_offset, ring->ring_size / 4); + ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR, + reg_offset); +} + +/** + * jpeg_v5_0_2_start - start JPEG block + * + * @adev: amdgpu_device pointer + * + * Setup and start the JPEG block + */ +static int jpeg_v5_0_2_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int i, j; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + jpeg_v5_0_2_init_inst(adev, i); + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + jpeg_v5_0_2_init_jrbc(ring); + } + } + + return 0; +} + +/** + * jpeg_v5_0_2_stop - stop JPEG block + * + * @adev: amdgpu_device pointer + * + * stop the JPEG block + */ +static int jpeg_v5_0_2_stop(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) + jpeg_v5_0_2_deinit_inst(adev, i); + + return 0; +} + +/** + * jpeg_v5_0_2_dec_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t jpeg_v5_0_2_dec_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR, + ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0); +} + +/** + * jpeg_v5_0_2_dec_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t jpeg_v5_0_2_dec_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) + return adev->wb.wb[ring->wptr_offs]; + + return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR, + ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0); +} + +/** + * jpeg_v5_0_2_dec_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void jpeg_v5_0_2_dec_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); + } else { + WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), + regUVD_JRBC_RB_WPTR, + (ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0), + lower_32_bits(ring->wptr)); + } +} + +static bool jpeg_v5_0_2_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + bool ret = false; + int i, j; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + int reg_offset = (j ? jpeg_v5_0_2_core_reg_offset(j) : 0); + + ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), + regUVD_JRBC_STATUS, reg_offset) & + UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == + UVD_JRBC_STATUS__RB_JOB_DONE_MASK); + } + } + + return ret; +} + +static int jpeg_v5_0_2_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret = 0; + int i, j; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + int reg_offset = (j ? jpeg_v5_0_2_core_reg_offset(j) : 0); + + ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), + regUVD_JRBC_STATUS, reg_offset, + UVD_JRBC_STATUS__RB_JOB_DONE_MASK, + UVD_JRBC_STATUS__RB_JOB_DONE_MASK); + } + } + return ret; +} + +static int jpeg_v5_0_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + bool enable = state == AMD_CG_STATE_GATE; + + int i; + + if (!enable) + return 0; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + if (!jpeg_v5_0_2_is_idle(ip_block)) + return -EBUSY; + } + + return 0; +} + +static int jpeg_v5_0_2_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret; + + if (state == adev->jpeg.cur_state) + return 0; + + if (state == AMD_PG_STATE_GATE) + ret = jpeg_v5_0_2_stop(adev); + else + ret = jpeg_v5_0_2_start(adev); + + if (!ret) + adev->jpeg.cur_state = state; + + return ret; +} + +static int jpeg_v5_0_2_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + return 0; +} + +static int jpeg_v5_0_2_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u32 i, inst; + + i = node_id_to_phys_map[entry->node_id]; + DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); + + for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) + if (adev->jpeg.inst[inst].aid_id == i) + break; + + if (inst >= adev->jpeg.num_jpeg_inst) { + dev_WARN_ONCE(adev->dev, 1, + "Interrupt received for unknown JPEG instance %d", + entry->node_id); + return 0; + } + + switch (entry->src_id) { + case VCN_5_0__SRCID__JPEG_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); + break; + case VCN_5_0__SRCID__JPEG1_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); + break; + case VCN_5_0__SRCID__JPEG2_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); + break; + case VCN_5_0__SRCID__JPEG3_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); + break; + case VCN_5_0__SRCID__JPEG4_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); + break; + case VCN_5_0__SRCID__JPEG5_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); + break; + case VCN_5_0__SRCID__JPEG6_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); + break; + case VCN_5_0__SRCID__JPEG7_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); + break; + case VCN_5_0__SRCID__JPEG8_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]); + break; + case VCN_5_0__SRCID__JPEG9_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]); + break; + default: + DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static void jpeg_v5_0_2_core_stall_reset(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + int jpeg_inst = GET_INST(JPEG, ring->me); + int reg_offset = ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0; + + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_STALL, + reg_offset, 0x1F); + SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, + reg_offset, 0x1F, 0x1F); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_JPEG_LMI_DROP, + reg_offset, 0x1F); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_STALL, + reg_offset, 0x00); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_JPEG_LMI_DROP, + reg_offset, 0x00); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); +} + +static int jpeg_v5_0_2_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + jpeg_v5_0_2_core_stall_reset(ring); + jpeg_v5_0_2_init_jrbc(ring); + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + +static const struct amd_ip_funcs jpeg_v5_0_2_ip_funcs = { + .name = "jpeg_v5_0_2", + .early_init = jpeg_v5_0_2_early_init, + .late_init = NULL, + .sw_init = jpeg_v5_0_2_sw_init, + .sw_fini = jpeg_v5_0_2_sw_fini, + .hw_init = jpeg_v5_0_2_hw_init, + .hw_fini = jpeg_v5_0_2_hw_fini, + .suspend = jpeg_v5_0_2_suspend, + .resume = jpeg_v5_0_2_resume, + .is_idle = jpeg_v5_0_2_is_idle, + .wait_for_idle = jpeg_v5_0_2_wait_for_idle, + .check_soft_reset = NULL, + .pre_soft_reset = NULL, + .soft_reset = NULL, + .post_soft_reset = NULL, + .set_clockgating_state = jpeg_v5_0_2_set_clockgating_state, + .set_powergating_state = jpeg_v5_0_2_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, +}; + +static const struct amdgpu_ring_funcs jpeg_v5_0_2_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_JPEG, + .align_mask = 0xf, + .get_rptr = jpeg_v5_0_2_dec_ring_get_rptr, + .get_wptr = jpeg_v5_0_2_dec_ring_get_wptr, + .set_wptr = jpeg_v5_0_2_dec_ring_set_wptr, + .emit_frame_size = + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + + 8 + /* jpeg_v5_0_2_dec_ring_emit_vm_flush */ + 22 + 22 + /* jpeg_v5_0_2_dec_ring_emit_fence x2 vm fence */ + 8 + 16, + .emit_ib_size = 22, /* jpeg_v5_0_2_dec_ring_emit_ib */ + .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, + .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, + .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, + .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, + .test_ring = amdgpu_jpeg_dec_ring_test_ring, + .test_ib = amdgpu_jpeg_dec_ring_test_ib, + .insert_nop = jpeg_v4_0_3_dec_ring_nop, + .insert_start = jpeg_v4_0_3_dec_ring_insert_start, + .insert_end = jpeg_v4_0_3_dec_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_jpeg_ring_begin_use, + .end_use = amdgpu_jpeg_ring_end_use, + .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, + .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, + .reset = jpeg_v5_0_2_ring_reset, +}; + +static void jpeg_v5_0_2_set_dec_ring_funcs(struct amdgpu_device *adev) +{ + int i, j, jpeg_inst; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_2_dec_ring_vm_funcs; + adev->jpeg.inst[i].ring_dec[j].me = i; + adev->jpeg.inst[i].ring_dec[j].pipe = j; + } + jpeg_inst = GET_INST(JPEG, i); + adev->jpeg.inst[i].aid_id = + jpeg_inst / adev->jpeg.num_inst_per_aid; + } +} + +static const struct amdgpu_irq_src_funcs jpeg_v5_0_2_irq_funcs = { + .set = jpeg_v5_0_2_set_interrupt_state, + .process = jpeg_v5_0_2_process_interrupt, +}; + +static void jpeg_v5_0_2_set_irq_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) + adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; + + adev->jpeg.inst->irq.funcs = &jpeg_v5_0_2_irq_funcs; +} + +const struct amdgpu_ip_block_version jpeg_v5_0_2_ip_block = { + .type = AMD_IP_BLOCK_TYPE_JPEG, + .major = 5, + .minor = 0, + .rev = 2, + .funcs = &jpeg_v5_0_2_ip_funcs, +}; + +#if 0 +static int jpeg_v5_0_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, + enum aca_smu_type type, void *data) +{ + struct aca_bank_info info; + u64 misc0; + int ret; + + ret = aca_bank_info_decode(bank, &info); + if (ret) + return ret; + + misc0 = bank->regs[ACA_REG_IDX_MISC0]; + switch (type) { + case ACA_SMU_TYPE_UE: + bank->aca_err_type = ACA_ERROR_TYPE_UE; + ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, + 1ULL); + break; + case ACA_SMU_TYPE_CE: + bank->aca_err_type = ACA_ERROR_TYPE_CE; + ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, + ACA_REG__MISC0__ERRCNT(misc0)); + break; + default: + return -EINVAL; + } + + return ret; +} + +/* reference to smu driver if header file */ +static int jpeg_v5_0_2_err_codes[] = { + 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-9][S|D] */ + 24, 25, 26, 27, 28, 29, 30, 31, + 48, 49, 50, 51, +}; + +static bool jpeg_v5_0_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, + enum aca_smu_type type, void *data) +{ + u32 instlo; + + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); + instlo &= GENMASK(31, 1); + + if (instlo != mmSMNAID_AID0_MCA_SMU) + return false; + + if (aca_bank_check_error_codes(handle->adev, bank, + jpeg_v5_0_2_err_codes, + ARRAY_SIZE(jpeg_v5_0_2_err_codes))) + return false; + + return true; +} + +static const struct aca_bank_ops jpeg_v5_0_2_aca_bank_ops = { + .aca_bank_parser = jpeg_v5_0_2_aca_bank_parser, + .aca_bank_is_valid = jpeg_v5_0_2_aca_bank_is_valid, +}; + +static const struct aca_info jpeg_v5_0_2_aca_info = { + .hwip = ACA_HWIP_TYPE_SMU, + .mask = ACA_ERROR_UE_MASK, + .bank_ops = &jpeg_v5_0_2_aca_bank_ops, +}; +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h new file mode 100644 index 0000000000000..c201a2c42a0dc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h @@ -0,0 +1,111 @@ +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __JPEG_V5_0_2_H__ +#define __JPEG_V5_0_2_H__ + +extern const struct amdgpu_ip_block_version jpeg_v5_0_2_ip_block; + +#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094 +#define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe + +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640 +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649 +#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x0000 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC1_UVD_JRBC_STATUS 0x0009 +#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x000a +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0040 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0049 +#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x004a +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0080 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0089 +#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x008a +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_RB_WPTR 0x00c0 +#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_STATUS 0x00c9 +#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_RB_RPTR 0x00ca +#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_RB_WPTR 0x0100 +#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_STATUS 0x0109 +#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_RB_RPTR 0x010a +#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_RB_WPTR 0x0140 +#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_STATUS 0x0149 +#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_RB_RPTR 0x014a +#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_RB_WPTR 0x0180 +#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_STATUS 0x0189 +#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_RB_RPTR 0x018a +#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_RB_WPTR 0x01c0 +#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_STATUS 0x01c9 +#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_RB_RPTR 0x01ca +#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC9_UVD_JRBC_RB_WPTR 0x0440 +#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC9_UVD_JRBC_STATUS 0x0449 +#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC9_UVD_JRBC_RB_RPTR 0x044a +#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JMI0_JPEG_LMI_DROP 0x0663 +#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX 1 +#define regUVD_JMI0_UVD_JMI_CLIENT_STALL 0x067a +#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX 1 +#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS 0x067b +#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 1 +#define regJPEG_CORE_RST_CTRL 0x072e +#define regJPEG_CORE_RST_CTRL_BASE_IDX 1 + +#define regVCN_RRMT_CNTL 0x0940 +#define regVCN_RRMT_CNTL_BASE_IDX 1 + +enum amdgpu_jpeg_v5_0_2_sub_block { + AMDGPU_JPEG_V5_0_2_JPEG0 = 0, + AMDGPU_JPEG_V5_0_2_JPEG1, + + AMDGPU_JPEG_V5_0_2_MAX_SUB_BLOCK, +}; + +#endif /* __JPEG_V5_0_2_H__ */ From 5842c35f9ba0a7ecd91f872703d21e5abe807602 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Mar 2026 11:04:46 -0400 Subject: [PATCH 1927/2070] drm/amdgpu: rework how we handle TLB fences MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new VM flag to indicate whether or not we need a TLB fence. Userqs (KFD or KGD) require a TLB fence. A TLB fence is not strictly required for kernel queues, but it shouldn't hurt. That said, enabling this unconditionally should be fine, but it seems to tickle some issues in KIQ/MES. Only enable them for KFD, or when KGD userq queues are enabled (currently via module parameter). Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4798 Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4749 Fixes: f3854e04b708 ("drm/amdgpu: attach tlb fence to the PTs update") Cc: Christian König Cc: Prike Liang Reviewed-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 1ac46bb0389c5..00760231fcb16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1073,7 +1073,10 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, } /* Prepare a TLB flush fence to be attached to PTs */ - if (!params->unlocked) { + /* The check for need_tlb_fence should be dropped once we + * sort out the issues with KIQ/MES TLB invalidation timeouts. + */ + if (!params->unlocked && vm->need_tlb_fence) { amdgpu_vm_tlb_fence_create(params->adev, vm, fence); /* Makes sure no PD/PT is freed before the flush */ @@ -2642,6 +2645,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ttm_lru_bulk_move_init(&vm->lru_bulk_move); vm->is_compute_context = false; + vm->need_tlb_fence = amdgpu_userq_enabled(&adev->ddev); vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_GFX); @@ -2779,6 +2783,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) dma_fence_put(vm->last_update); vm->last_update = dma_fence_get_stub(); vm->is_compute_context = true; + vm->need_tlb_fence = true; unreserve_bo: amdgpu_bo_unreserve(vm->root.bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 27aed3df07dde..33c680c483c76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -441,6 +441,8 @@ struct amdgpu_vm { struct ttm_lru_bulk_move lru_bulk_move; /* Flag to indicate if VM is used for compute */ bool is_compute_context; + /* Flag to indicate if VM needs a TLB fence (KFD or KGD) */ + bool need_tlb_fence; /* Memory partition number, -1 means any partition */ int8_t mem_id; From 815b50bb6313739d5ed9586a5d4bb4497a8ecd47 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 25 Sep 2023 10:44:07 -0400 Subject: [PATCH 1928/2070] drm/amdgpu: apply state adjust rules to some additional HAINAN vairants They need a similar workaround. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1839 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index d8959e0f109cf..b75a6031c68a5 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3454,9 +3454,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, if (adev->asic_type == CHIP_HAINAN) { if ((adev->pdev->revision == 0x81) || (adev->pdev->revision == 0xC3) || + (adev->pdev->device == 0x6660) || (adev->pdev->device == 0x6664) || (adev->pdev->device == 0x6665) || - (adev->pdev->device == 0x6667)) { + (adev->pdev->device == 0x6667) || + (adev->pdev->device == 0x666F)) { max_sclk = 75000; } if ((adev->pdev->revision == 0xC3) || From 0cfb08d1ccb7086e86b651a04d441cb2a237e5ed Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Sun, 1 Mar 2026 15:19:13 +0000 Subject: [PATCH 1929/2070] drm/amdgpu : Update psp 13_0_15 ip block support Included psp_13_0_15 ip block for RAS Signed-off-by: Mangesh Gadre Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index bbed569f1807b..da221b5414440 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2254,6 +2254,7 @@ static bool amdgpu_ras_aca_is_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): ret = true; break; default: @@ -4012,6 +4013,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): return true; default: return false; @@ -4025,6 +4027,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): case IP_VERSION(14, 0, 3): return true; default: @@ -4194,7 +4197,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) adev->aca.is_enabled = (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)); + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)); } /* bad page feature is not applicable to specific app platform */ @@ -4282,6 +4286,7 @@ static void amdgpu_ras_init_reserved_vram_size(struct amdgpu_device *adev) case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): + case IP_VERSION(13, 0, 15): con->reserved_pages_in_bytes = AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT; break; case IP_VERSION(13, 0, 14): From 5c3c06960c43c4706b90af7f331bcf721b8d71f5 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 15 Mar 2026 12:42:42 +0530 Subject: [PATCH 1930/2070] drm/amdgpu: Drop redundant queue NULL check in hang detect worker MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_userq_hang_detect_work() retrieves the queue pointer using container_of() from the embedded work item. Since the work structure is part of struct amdgpu_usermode_queue, the returned queue pointer cannot be NULL in normal execution. Remove the redundant !queue check and keep the validation for queue->userq_mgr. Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c:159 amdgpu_userq_hang_detect_work() warn: can 'queue' even be NULL? Fixes: 290f46cf5726 ("drm/amdgpu: Implement user queue reset functionality") Cc: Jesse Zhang Cc: Dan Carpenter Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Acked-by: Jesse Zhang Reviewed-by: Lijo Lazar Change-Id: I28c615502c53f66e06edaca9a44b9a24fe3f0441 --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 40962c5ab249a..06f783787dfd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -156,7 +156,7 @@ static void amdgpu_userq_hang_detect_work(struct work_struct *work) struct dma_fence *fence; struct amdgpu_userq_mgr *uq_mgr; - if (!queue || !queue->userq_mgr) + if (!queue->userq_mgr) return; uq_mgr = queue->userq_mgr; From aaef48a219289b0e299f5608fa75b71ebd6ef03f Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 12 Mar 2026 18:53:59 +0530 Subject: [PATCH 1931/2070] drm/amdgpu: Remove dead negative offset check in amdgpu_virt_init_critical_region() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_virt_init_critical_region() stores init_hdr_offset as u64. The subsequent check for init_hdr_offset < 0 is therefore always false. Drop the unreachable validation and rely on the existing check_add_overflow() and VRAM end bounds check for offset validation. This resolves the Smatch warning about comparing an unsigned value against zero. drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:953 amdgpu_virt_init_critical_region() warn: unsigned 'init_hdr_offset' is never less than zero. Fixes: 07009df6494d ("drm/amdgpu: Introduce SRIOV critical regions v2 during VF init") Cc: Dan Carpenter Cc: Ellen Pan Cc: Lijo Lazar Cc: Alex Deucher Cc: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Bokun Zhang Reviewed-by: Ellen Pan Change-Id: I8a260daf96fcdeb837f6966eacbb640c2ea87362 --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 112e6489aab70..c8e4c6e356aab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -950,11 +950,6 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) if (adev->virt.req_init_data_ver != GPU_CRIT_REGION_V2) return 0; - if (init_hdr_offset < 0) { - dev_err(adev->dev, "Invalid init header offset\n"); - return -EINVAL; - } - vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); if (!vram_size || vram_size == U32_MAX) return -EINVAL; From 82645fda6719281210f7263d3279db9558ee1968 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 17 Mar 2026 13:04:51 -0400 Subject: [PATCH 1932/2070] Revert "drm/amd/display: Add NV12/P010 formats to primary plane" With this change we're adding NV12 and P010 twice to reported formats on a primary plane, which causes us to hit an assert in Weston. This reverts commit e01716e8352a3cf504058fd6ab90d8969e379275. Fixes: e01716e8352a ("drm/amd/display: Add NV12/P010 formats to primary plane") Signed-off-by: Harry Wentland Reviewed-by: Leo Li --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index f858deab4a221..d4c904f40175b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -64,9 +64,6 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, - DRM_FORMAT_NV21, - DRM_FORMAT_NV12, - DRM_FORMAT_P010 }; static const uint32_t overlay_formats[] = { From fef855c7692c958463f0987df3fab0a5ea4fc210 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Mar 2026 13:03:53 +0530 Subject: [PATCH 1933/2070] drm/amdgpu: Add client id helpers to mmhub Add data structure and helpers to get client id data of mmhub. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h index 92918101a95d1..6b8214650e5d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h @@ -66,12 +66,37 @@ struct amdgpu_mmhub_funcs { int (*get_xgmi_info)(struct amdgpu_device *adev); }; +struct amdgpu_mmhub_client_ids { + const char * const (*names)[2]; + unsigned int size; +}; + struct amdgpu_mmhub { struct ras_common_if *ras_if; const struct amdgpu_mmhub_funcs *funcs; struct amdgpu_mmhub_ras *ras; + struct amdgpu_mmhub_client_ids client_ids; }; +static inline void +amdgpu_mmhub_init_client_info(struct amdgpu_mmhub *mmhub, + const char * const (*names)[2], + unsigned int size) +{ + mmhub->client_ids.names = names; + mmhub->client_ids.size = size; +} + +static inline const char * +amdgpu_mmhub_client_name(struct amdgpu_mmhub *mmhub, + u32 cid, bool is_write) +{ + if (cid < mmhub->client_ids.size) + return mmhub->client_ids.names[cid][is_write]; + + return NULL; +} + int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); #endif From 41fb012466982c58e25fa636d633e76a18360d1d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Mar 2026 13:11:18 +0530 Subject: [PATCH 1934/2070] drm/amdgpu: Add client ids for mmhub v4.x Initialize client ids for mmhub v4.x Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c | 16 ++++++---------- drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c | 16 ++++++---------- 2 files changed, 12 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c index 88bfe321f83aa..bef75c4c48d3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c @@ -90,7 +90,7 @@ mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); @@ -100,15 +100,7 @@ mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(4, 1, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_1_0) ? - mmhub_client_ids_v4_1_0[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -515,6 +507,10 @@ static void mmhub_v4_1_0_init(struct amdgpu_device *adev) SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE); hub->vmhub_funcs = &mmhub_v4_1_0_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v4_1_0, + ARRAY_SIZE(mmhub_client_ids_v4_1_0)); } static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c index 2fb82e022c79b..29f7ed4668587 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -716,7 +716,7 @@ mmhub_v4_2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); @@ -726,15 +726,7 @@ mmhub_v4_2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(4, 2, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_2_0) ? - mmhub_client_ids_v4_2_0[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -825,6 +817,10 @@ static void mmhub_v4_2_0_init(struct amdgpu_device *adev) mid_mask = adev->aid_mask; mmhub_v4_2_0_mid_init(adev, mid_mask); + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v4_2_0, + ARRAY_SIZE(mmhub_client_ids_v4_2_0)); } static void From 984b875012dcb00a652b641b551e0acd2a1f3fbb Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Mar 2026 13:22:05 +0530 Subject: [PATCH 1935/2070] drm/amdgpu: Add client ids for mmhub v3.x Initialize client ids for mmhub v3.x Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 17 +++---- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 18 +++----- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 10 +++-- drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c | 55 +++++++++++++---------- 4 files changed, 49 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c index ab966e69a342a..3d82cfa0f1b51 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c @@ -97,7 +97,7 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -107,16 +107,7 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(3, 0, 0): - case IP_VERSION(3, 0, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_0) ? - mmhub_client_ids_v3_0_0[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -521,6 +512,10 @@ static void mmhub_v3_0_init(struct amdgpu_device *adev) SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE); hub->vmhub_funcs = &mmhub_v3_0_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_0_0, + ARRAY_SIZE(mmhub_client_ids_v3_0_0)); } static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c index 14a742d3a99d7..a1b0b7b39a42a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c @@ -104,7 +104,7 @@ mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -114,17 +114,7 @@ mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(3, 0, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_1) ? - mmhub_client_ids_v3_0_1[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } - + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -504,6 +494,10 @@ static void mmhub_v3_0_1_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_0_1, + ARRAY_SIZE(mmhub_client_ids_v3_0_1)); } static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c index e1f07f2a18527..34e8dbd47c0f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c @@ -97,7 +97,7 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -107,9 +107,7 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_2) ? - mmhub_client_ids_v3_0_2[cid][rw] : NULL; + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -510,6 +508,10 @@ static void mmhub_v3_0_2_init(struct amdgpu_device *adev) SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2); hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_0_2, + ARRAY_SIZE(mmhub_client_ids_v3_0_2)); } static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c index daf1f8ad4ccaa..cfce7e1297d4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c @@ -217,7 +217,7 @@ mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -227,29 +227,10 @@ mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(3, 3, 0): - case IP_VERSION(3, 3, 2): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? - mmhub_client_ids_v3_3[cid][rw] : - cid == 0x140 ? "UMSCH" : NULL; - break; - case IP_VERSION(3, 3, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3_1) ? - mmhub_client_ids_v3_3_1[cid][rw] : - cid == 0x140 ? "UMSCH" : NULL; - break; - case IP_VERSION(3, 4, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_4) ? - mmhub_client_ids_v3_4[cid][rw] : - cid == 0x140 ? "UMSCH" : NULL; - break; - default: - mmhub_cid = NULL; - break; - } - + if (cid == 0x140) + mmhub_cid = "UMSCH"; + else + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -640,6 +621,30 @@ static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { .get_invalidate_req = mmhub_v3_3_get_invalidate_req, }; +static void mmhub_v3_3_init_client_info(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { + case IP_VERSION(3, 3, 0): + case IP_VERSION(3, 3, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_3, + ARRAY_SIZE(mmhub_client_ids_v3_3)); + break; + case IP_VERSION(3, 3, 1): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_3_1, + ARRAY_SIZE(mmhub_client_ids_v3_3_1)); + break; + case IP_VERSION(3, 4, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_4, + ARRAY_SIZE(mmhub_client_ids_v3_4)); + break; + default: + break; + } +} + static void mmhub_v3_3_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; @@ -680,6 +685,8 @@ static void mmhub_v3_3_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; + + mmhub_v3_3_init_client_info(adev); } static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) From 0d2845d34d6f16f07bff997eba0223e7c285504d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Mar 2026 13:39:56 +0530 Subject: [PATCH 1936/2070] drm/amdgpu: Add client ids for mmhub v2.x Initialize client ids for mmhub v2.x Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 49 +++++++++++++++---------- drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 18 +++------ 2 files changed, 35 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c index 534cb4c544dc4..42a09a277ec3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c @@ -141,7 +141,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -151,25 +151,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(2, 0, 0): - case IP_VERSION(2, 0, 2): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_navi1x) ? - mmhub_client_ids_navi1x[cid][rw] : NULL; - break; - case IP_VERSION(2, 1, 0): - case IP_VERSION(2, 1, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_sienna_cichlid) ? - mmhub_client_ids_sienna_cichlid[cid][rw] : NULL; - break; - case IP_VERSION(2, 1, 2): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_beige_goby) ? - mmhub_client_ids_beige_goby[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -521,6 +503,31 @@ static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = { .get_invalidate_req = mmhub_v2_0_get_invalidate_req, }; +static void mmhub_v2_0_init_client_info(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { + case IP_VERSION(2, 0, 0): + case IP_VERSION(2, 0, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_navi1x, + ARRAY_SIZE(mmhub_client_ids_navi1x)); + break; + case IP_VERSION(2, 1, 0): + case IP_VERSION(2, 1, 1): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_sienna_cichlid, + ARRAY_SIZE(mmhub_client_ids_sienna_cichlid)); + break; + case IP_VERSION(2, 1, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_beige_goby, + ARRAY_SIZE(mmhub_client_ids_beige_goby)); + break; + default: + break; + } +} + static void mmhub_v2_0_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; @@ -561,6 +568,8 @@ static void mmhub_v2_0_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs; + + mmhub_v2_0_init_client_info(adev); } static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c index ceb2f6b46de52..31c479d76c421 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c @@ -80,7 +80,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -90,17 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(2, 3, 0): - case IP_VERSION(2, 4, 0): - case IP_VERSION(2, 4, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vangogh) ? - mmhub_client_ids_vangogh[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -487,6 +477,10 @@ static void mmhub_v2_3_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vangogh, + ARRAY_SIZE(mmhub_client_ids_vangogh)); } static void From a5529dc3a327fc2c77e6a22e8e179c101cac5f33 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Mar 2026 16:38:00 +0530 Subject: [PATCH 1937/2070] drm/amdgpu: Add client ids for gmcv9 mmhubs Initialize client ids for gmcv9 mmhubs Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 85 +++++++++++++++------------ 1 file changed, 49 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 13caa47e3f38d..34f5865e74f8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -660,42 +660,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, gfxhub_client_ids[cid], cid); } else { - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(9, 0, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega10) ? - mmhub_client_ids_vega10[cid][rw] : NULL; - break; - case IP_VERSION(9, 3, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega12) ? - mmhub_client_ids_vega12[cid][rw] : NULL; - break; - case IP_VERSION(9, 4, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega20) ? - mmhub_client_ids_vega20[cid][rw] : NULL; - break; - case IP_VERSION(9, 4, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_arcturus) ? - mmhub_client_ids_arcturus[cid][rw] : NULL; - break; - case IP_VERSION(9, 1, 0): - case IP_VERSION(9, 2, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_raven) ? - mmhub_client_ids_raven[cid][rw] : NULL; - break; - case IP_VERSION(1, 5, 0): - case IP_VERSION(2, 4, 0): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_renoir) ? - mmhub_client_ids_renoir[cid][rw] : NULL; - break; - case IP_VERSION(1, 8, 0): - case IP_VERSION(9, 4, 2): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_aldebaran) ? - mmhub_client_ids_aldebaran[cid][rw] : NULL; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); } @@ -1435,6 +1400,52 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) } } +static void gmc_v9_0_init_mmhub_client_info(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { + case IP_VERSION(9, 0, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vega10, + ARRAY_SIZE(mmhub_client_ids_vega10)); + break; + case IP_VERSION(9, 3, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vega12, + ARRAY_SIZE(mmhub_client_ids_vega12)); + break; + case IP_VERSION(9, 4, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vega20, + ARRAY_SIZE(mmhub_client_ids_vega20)); + break; + case IP_VERSION(9, 4, 1): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_arcturus, + ARRAY_SIZE(mmhub_client_ids_arcturus)); + break; + case IP_VERSION(9, 1, 0): + case IP_VERSION(9, 2, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_raven, + ARRAY_SIZE(mmhub_client_ids_raven)); + break; + case IP_VERSION(1, 5, 0): + case IP_VERSION(2, 4, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_renoir, + ARRAY_SIZE(mmhub_client_ids_renoir)); + break; + case IP_VERSION(1, 8, 0): + case IP_VERSION(9, 4, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_aldebaran, + ARRAY_SIZE(mmhub_client_ids_aldebaran)); + break; + default: + break; + } +} + static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) { switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { @@ -1452,6 +1463,8 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) adev->mmhub.funcs = &mmhub_v1_0_funcs; break; } + + gmc_v9_0_init_mmhub_client_info(adev); } static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) From 70905c0ec9633b2a37e02401b8c8f0e53171b08c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 28 Jan 2026 13:58:14 +0100 Subject: [PATCH 1938/2070] drm/amdgpu: completely rework eviction fence handling v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Well that was broken on multiple levels. First of all a lot of checks were placed at incorrect locations, especially if the resume worker should run or not. Then a bunch of code was just mid-layering because of incorrect assignment who should do what. And finally comments explaining what happens instead of why. Just re-write it from scratch, that should at least fix some of the hangs we are seeing. Use RCU for the eviction fence pointer in the manager, the spinlock usage was mostly incorrect as well. Then finally remove all the nonsense checks and actually add them in the correct locations. v2: some typo fixes and cleanups suggested by Sunil Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +- .../drm/amd/amdgpu/amdgpu_eviction_fence.c | 212 ++++++------------ .../drm/amd/amdgpu/amdgpu_eviction_fence.h | 54 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 29 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2 +- 7 files changed, 110 insertions(+), 206 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 66772f01c28f7..71271184328ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3024,9 +3024,9 @@ static int amdgpu_drm_release(struct inode *inode, struct file *filp) int idx; if (fpriv && drm_dev_enter(dev, &idx)) { - fpriv->evf_mgr.fd_closing = true; - amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); + amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); amdgpu_userq_mgr_fini(&fpriv->userq_mgr); + amdgpu_evf_mgr_fini(&fpriv->evf_mgr); drm_dev_exit(idx); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index aed29e3c0c4d0..edbefa210f91c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -25,9 +25,6 @@ #include #include "amdgpu.h" -#define work_to_evf_mgr(w, name) container_of(w, struct amdgpu_eviction_fence_mgr, name) -#define evf_mgr_to_fpriv(e) container_of(e, struct amdgpu_fpriv, evf_mgr) - static const char * amdgpu_eviction_fence_get_driver_name(struct dma_fence *fence) { @@ -43,127 +40,66 @@ amdgpu_eviction_fence_get_timeline_name(struct dma_fence *f) return ef->timeline_name; } -int -amdgpu_eviction_fence_replace_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct drm_exec *exec) +static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f) { - struct amdgpu_eviction_fence *old_ef, *new_ef; - struct drm_gem_object *obj; - unsigned long index; - int ret; - - if (evf_mgr->ev_fence && - !dma_fence_is_signaled(&evf_mgr->ev_fence->base)) - return 0; - /* - * Steps to replace eviction fence: - * * lock all objects in exec (caller) - * * create a new eviction fence - * * update new eviction fence in evf_mgr - * * attach the new eviction fence to BOs - * * release the old fence - * * unlock the objects (caller) - */ - new_ef = amdgpu_eviction_fence_create(evf_mgr); - if (!new_ef) { - DRM_ERROR("Failed to create new eviction fence\n"); - return -ENOMEM; - } - - /* Update the eviction fence now */ - spin_lock(&evf_mgr->ev_fence_lock); - old_ef = evf_mgr->ev_fence; - evf_mgr->ev_fence = new_ef; - spin_unlock(&evf_mgr->ev_fence_lock); + struct amdgpu_eviction_fence *ev_fence = to_ev_fence(f); - /* Attach the new fence */ - drm_exec_for_each_locked_object(exec, index, obj) { - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - - if (!bo) - continue; - ret = amdgpu_eviction_fence_attach(evf_mgr, bo); - if (ret) { - DRM_ERROR("Failed to attch new eviction fence\n"); - goto free_err; - } - } - - /* Free old fence */ - if (old_ef) - dma_fence_put(&old_ef->base); - return 0; - -free_err: - kfree(new_ef); - return ret; + schedule_work(&ev_fence->evf_mgr->suspend_work); + return true; } +static const struct dma_fence_ops amdgpu_eviction_fence_ops = { + .get_driver_name = amdgpu_eviction_fence_get_driver_name, + .get_timeline_name = amdgpu_eviction_fence_get_timeline_name, + .enable_signaling = amdgpu_eviction_fence_enable_signaling, +}; + static void amdgpu_eviction_fence_suspend_worker(struct work_struct *work) { - struct amdgpu_eviction_fence_mgr *evf_mgr = work_to_evf_mgr(work, suspend_work.work); - struct amdgpu_fpriv *fpriv = evf_mgr_to_fpriv(evf_mgr); + struct amdgpu_eviction_fence_mgr *evf_mgr = + container_of(work, struct amdgpu_eviction_fence_mgr, + suspend_work); + struct amdgpu_fpriv *fpriv = + container_of(evf_mgr, struct amdgpu_fpriv, evf_mgr); struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; - struct amdgpu_eviction_fence *ev_fence; + struct dma_fence *ev_fence; mutex_lock(&uq_mgr->userq_mutex); - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - if (ev_fence) - dma_fence_get(&ev_fence->base); - else - goto unlock; - spin_unlock(&evf_mgr->ev_fence_lock); - - amdgpu_userq_evict(uq_mgr, ev_fence); - - mutex_unlock(&uq_mgr->userq_mutex); - dma_fence_put(&ev_fence->base); - return; + ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + amdgpu_userq_evict(uq_mgr, !evf_mgr->shutdown); -unlock: - spin_unlock(&evf_mgr->ev_fence_lock); + /* + * Signaling the eviction fence must be done while holding the + * userq_mutex. Otherwise we won't resume the queues before issuing the + * next fence. + */ + dma_fence_signal(ev_fence); + dma_fence_put(ev_fence); mutex_unlock(&uq_mgr->userq_mutex); } -static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f) +void amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo) { - struct amdgpu_eviction_fence_mgr *evf_mgr; - struct amdgpu_eviction_fence *ev_fence; - - if (!f) - return true; - - ev_fence = to_ev_fence(f); - evf_mgr = ev_fence->evf_mgr; - - schedule_delayed_work(&evf_mgr->suspend_work, 0); - return true; -} - -static const struct dma_fence_ops amdgpu_eviction_fence_ops = { - .get_driver_name = amdgpu_eviction_fence_get_driver_name, - .get_timeline_name = amdgpu_eviction_fence_get_timeline_name, - .enable_signaling = amdgpu_eviction_fence_enable_signaling, -}; + struct dma_fence *ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + struct dma_resv *resv = bo->tbo.base.resv; -void amdgpu_eviction_fence_signal(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_eviction_fence *ev_fence) -{ - spin_lock(&evf_mgr->ev_fence_lock); - dma_fence_signal(&ev_fence->base); - spin_unlock(&evf_mgr->ev_fence_lock); + dma_resv_add_fence(resv, ev_fence, DMA_RESV_USAGE_BOOKKEEP); + dma_fence_put(ev_fence); } -struct amdgpu_eviction_fence * -amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr) +int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct drm_exec *exec) { struct amdgpu_eviction_fence *ev_fence; + struct drm_gem_object *obj; + unsigned long index; + /* Create and initialize a new eviction fence */ ev_fence = kzalloc(sizeof(*ev_fence), GFP_KERNEL); if (!ev_fence) - return NULL; + return -ENOMEM; ev_fence->evf_mgr = evf_mgr; get_task_comm(ev_fence->timeline_name, current); @@ -171,56 +107,22 @@ amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr) dma_fence_init64(&ev_fence->base, &amdgpu_eviction_fence_ops, &ev_fence->lock, evf_mgr->ev_fence_ctx, atomic_inc_return(&evf_mgr->ev_fence_seq)); - return ev_fence; -} - -void amdgpu_eviction_fence_destroy(struct amdgpu_eviction_fence_mgr *evf_mgr) -{ - struct amdgpu_eviction_fence *ev_fence; - - /* Wait for any pending work to execute */ - flush_delayed_work(&evf_mgr->suspend_work); - - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - spin_unlock(&evf_mgr->ev_fence_lock); - - if (!ev_fence) - return; - dma_fence_wait(&ev_fence->base, false); + /* Remember it for newly added BOs */ + dma_fence_put(evf_mgr->ev_fence); + evf_mgr->ev_fence = &ev_fence->base; - /* Last unref of ev_fence */ - dma_fence_put(&ev_fence->base); -} - -int amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo) -{ - struct amdgpu_eviction_fence *ev_fence; - struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); - int ret; - - if (!resv) - return 0; + /* And add it to all existing BOs */ + drm_exec_for_each_locked_object(exec, index, obj) { + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - ret = dma_resv_reserve_fences(resv, 1); - if (ret) { - DRM_DEBUG_DRIVER("Failed to resv fence space\n"); - return ret; + amdgpu_evf_mgr_attach_fence(evf_mgr, bo); } - - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - if (ev_fence) - dma_resv_add_fence(resv, &ev_fence->base, DMA_RESV_USAGE_BOOKKEEP); - spin_unlock(&evf_mgr->ev_fence_lock); - return 0; } -void amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo) +void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo) { struct dma_fence *stub = dma_fence_get_stub(); @@ -229,13 +131,25 @@ void amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, dma_fence_put(stub); } -int amdgpu_eviction_fence_init(struct amdgpu_eviction_fence_mgr *evf_mgr) +void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr) { - /* This needs to be done one time per open */ atomic_set(&evf_mgr->ev_fence_seq, 0); evf_mgr->ev_fence_ctx = dma_fence_context_alloc(1); - spin_lock_init(&evf_mgr->ev_fence_lock); + evf_mgr->ev_fence = dma_fence_get_stub(); - INIT_DELAYED_WORK(&evf_mgr->suspend_work, amdgpu_eviction_fence_suspend_worker); - return 0; + INIT_WORK(&evf_mgr->suspend_work, amdgpu_eviction_fence_suspend_worker); +} + +void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + evf_mgr->shutdown = true; + flush_work(&evf_mgr->suspend_work); +} + +void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + dma_fence_wait(rcu_dereference_protected(evf_mgr->ev_fence, true), + false); + flush_work(&evf_mgr->suspend_work); + dma_fence_put(evf_mgr->ev_fence); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h index fcd867b7147dd..527de3a235837 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h @@ -25,6 +25,8 @@ #ifndef AMDGPU_EV_FENCE_H_ #define AMDGPU_EV_FENCE_H_ +#include + struct amdgpu_eviction_fence { struct dma_fence base; spinlock_t lock; @@ -35,35 +37,35 @@ struct amdgpu_eviction_fence { struct amdgpu_eviction_fence_mgr { u64 ev_fence_ctx; atomic_t ev_fence_seq; - spinlock_t ev_fence_lock; - struct amdgpu_eviction_fence *ev_fence; - struct delayed_work suspend_work; - uint8_t fd_closing; -}; - -/* Eviction fence helper functions */ -struct amdgpu_eviction_fence * -amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr); -void -amdgpu_eviction_fence_destroy(struct amdgpu_eviction_fence_mgr *evf_mgr); - -int -amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo); + /* + * Only updated while holding the VM resv lock. + * Only signaled while holding the userq mutex. + */ + struct dma_fence __rcu *ev_fence; + struct work_struct suspend_work; + bool shutdown; +}; -void -amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo); +static inline struct dma_fence * +amdgpu_evf_mgr_get_fence(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + struct dma_fence *ev_fence; -int -amdgpu_eviction_fence_init(struct amdgpu_eviction_fence_mgr *evf_mgr); + rcu_read_lock(); + ev_fence = dma_fence_get_rcu_safe(&evf_mgr->ev_fence); + rcu_read_unlock(); + return ev_fence; +} -void -amdgpu_eviction_fence_signal(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_eviction_fence *ev_fence); +void amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo); +int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct drm_exec *exec); +void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo); +void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr); +void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr); +void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr); -int -amdgpu_eviction_fence_replace_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct drm_exec *exec); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index bd8d2a8244509..0fbcee53af61d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -318,13 +318,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, else ++bo_va->ref_count; - /* attach gfx eviction fence */ - r = amdgpu_eviction_fence_attach(&fpriv->evf_mgr, abo); - if (r) { - DRM_DEBUG_DRIVER("Failed to attach eviction fence to BO\n"); - amdgpu_bo_unreserve(abo); - return r; - } + amdgpu_evf_mgr_attach_fence(&fpriv->evf_mgr, abo); drm_exec_fini(&exec); /* Validate and add eviction fence to DMABuf imports with dynamic @@ -397,7 +391,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, } if (!amdgpu_vm_is_bo_always_valid(vm, bo)) - amdgpu_eviction_fence_detach(&fpriv->evf_mgr, bo); + amdgpu_evf_mgr_detach_fence(&fpriv->evf_mgr, bo); bo_va = amdgpu_vm_bo_find(vm, bo); if (!bo_va || --bo_va->ref_count) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index bbf339b1ecbe4..4a0fda4a660dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1567,10 +1567,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) "Failed to init usermode queue manager (%d), use legacy workload submission only\n", r); - r = amdgpu_eviction_fence_init(&fpriv->evf_mgr); - if (r) - goto error_vm; - + amdgpu_evf_mgr_init(&fpriv->evf_mgr); amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); file_priv->driver_priv = fpriv; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 06f783787dfd1..5c67fe803e08e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -472,17 +472,16 @@ void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr) { - struct amdgpu_eviction_fence *ev_fence; + struct dma_fence *ev_fence; retry: /* Flush any pending resume work to create ev_fence */ flush_delayed_work(&uq_mgr->resume_work); mutex_lock(&uq_mgr->userq_mutex); - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - spin_unlock(&evf_mgr->ev_fence_lock); - if (!ev_fence || dma_fence_is_signaled(&ev_fence->base)) { + ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + if (dma_fence_is_signaled(ev_fence)) { + dma_fence_put(ev_fence); mutex_unlock(&uq_mgr->userq_mutex); /* * Looks like there was no pending resume work, @@ -491,6 +490,7 @@ amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *uq_mgr, schedule_delayed_work(&uq_mgr->resume_work, 0); goto retry; } + dma_fence_put(ev_fence); } int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, @@ -1213,7 +1213,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) dma_fence_wait(bo_va->last_pt_update, false); dma_fence_wait(vm->last_update, false); - ret = amdgpu_eviction_fence_replace_fence(&fpriv->evf_mgr, &exec); + ret = amdgpu_evf_mgr_rearm(&fpriv->evf_mgr, &exec); if (ret) drm_file_err(uq_mgr->file, "Failed to replace eviction fence\n"); @@ -1235,11 +1235,13 @@ static void amdgpu_userq_restore_worker(struct work_struct *work) { struct amdgpu_userq_mgr *uq_mgr = work_to_uq_mgr(work, resume_work.work); struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + struct dma_fence *ev_fence; int ret; - flush_delayed_work(&fpriv->evf_mgr.suspend_work); - mutex_lock(&uq_mgr->userq_mutex); + ev_fence = amdgpu_evf_mgr_get_fence(&fpriv->evf_mgr); + if (!dma_fence_is_signaled(ev_fence)) + goto unlock; ret = amdgpu_userq_vm_validate(uq_mgr); if (ret) { @@ -1255,6 +1257,7 @@ static void amdgpu_userq_restore_worker(struct work_struct *work) unlock: mutex_unlock(&uq_mgr->userq_mutex); + dma_fence_put(ev_fence); } static int @@ -1330,11 +1333,8 @@ amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) } void -amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_eviction_fence *ev_fence) +amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, bool schedule_resume) { - struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); - struct amdgpu_eviction_fence_mgr *evf_mgr = &fpriv->evf_mgr; struct amdgpu_device *adev = uq_mgr->adev; int ret; @@ -1347,10 +1347,7 @@ amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, if (ret) dev_err(adev->dev, "Failed to evict userqueue\n"); - /* Signal current eviction fence */ - amdgpu_eviction_fence_signal(evf_mgr, ev_fence); - - if (!evf_mgr->fd_closing) + if (schedule_resume) schedule_delayed_work(&uq_mgr->resume_work, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 989e47308351b..f2896ba66b056 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -138,7 +138,7 @@ void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_userq_obj *userq_obj); void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_eviction_fence *ev_fence); + bool schedule_resume); void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr); From 8f376515f1dc01c78f9926eb36e6019ead88c0a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 30 Jan 2026 16:46:36 +0100 Subject: [PATCH 1939/2070] drm/amdgpu: fix eviction fence and userq manager shutdown MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That is a really complicated dance and wasn't implemented fully correct. Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c | 8 +++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 1 + 5 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 71271184328ea..8b801b5ea18ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3025,6 +3025,8 @@ static int amdgpu_drm_release(struct inode *inode, struct file *filp) if (fpriv && drm_dev_enter(dev, &idx)) { amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); + amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr); + amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr); amdgpu_userq_mgr_fini(&fpriv->userq_mgr); amdgpu_evf_mgr_fini(&fpriv->evf_mgr); drm_dev_exit(idx); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index edbefa210f91c..eea6787e2c400 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -143,13 +143,19 @@ void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr) void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr) { evf_mgr->shutdown = true; + /* Make sure that the shutdown is visible to the suspend work */ flush_work(&evf_mgr->suspend_work); } -void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr) +void amdgpu_evf_mgr_flush_suspend(struct amdgpu_eviction_fence_mgr *evf_mgr) { dma_fence_wait(rcu_dereference_protected(evf_mgr->ev_fence, true), false); + /* Make sure that we are done with the last suspend work */ flush_work(&evf_mgr->suspend_work); +} + +void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ dma_fence_put(evf_mgr->ev_fence); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h index 527de3a235837..132a13a5dc1c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h @@ -66,6 +66,7 @@ void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, struct amdgpu_bo *bo); void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr); void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr); +void amdgpu_evf_mgr_flush_suspend(struct amdgpu_eviction_fence_mgr *evf_mgr); void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 5c67fe803e08e..5f4c044199a83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1363,6 +1363,11 @@ int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *f return 0; } +void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr) +{ + cancel_delayed_work_sync(&userq_mgr->resume_work); +} + void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) { struct amdgpu_usermode_queue *queue; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index f2896ba66b056..bd40a98594d66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -128,6 +128,7 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, struct amdgpu_device *adev); +void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr); void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr); int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, From 5a8fabd3e244c0bb602ba596a4d203a498e40df2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 28 Jan 2026 16:07:03 +0100 Subject: [PATCH 1940/2070] drm/amdgpu: fix adding eviction fence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can't add the eviction fence without validating the BO. Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- .../drm/amd/amdgpu/amdgpu_eviction_fence.c | 19 ++++++++++++++++--- .../drm/amd/amdgpu/amdgpu_eviction_fence.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 9 ++++++--- 3 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index eea6787e2c400..e16796f4d289d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -79,14 +79,27 @@ amdgpu_eviction_fence_suspend_worker(struct work_struct *work) mutex_unlock(&uq_mgr->userq_mutex); } -void amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo) +int amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo) { struct dma_fence *ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + struct ttm_operation_ctx ctx = { false, false }; struct dma_resv *resv = bo->tbo.base.resv; + int ret; + + if (!dma_fence_is_signaled(ev_fence)) { + + amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (!ret) + dma_resv_add_fence(resv, ev_fence, + DMA_RESV_USAGE_BOOKKEEP); + } else { + ret = 0; + } - dma_resv_add_fence(resv, ev_fence, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(ev_fence); + return ret; } int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h index 132a13a5dc1c1..2a750add4e7b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h @@ -58,8 +58,8 @@ amdgpu_evf_mgr_get_fence(struct amdgpu_eviction_fence_mgr *evf_mgr) return ev_fence; } -void amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo); +int amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo); int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, struct drm_exec *exec); void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 0fbcee53af61d..5db51d7ff00ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -313,12 +313,15 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, amdgpu_vm_bo_update_shared(abo); bo_va = amdgpu_vm_bo_find(vm, abo); - if (!bo_va) + if (!bo_va) { bo_va = amdgpu_vm_bo_add(adev, vm, abo); - else + r = amdgpu_evf_mgr_attach_fence(&fpriv->evf_mgr, abo); + if (r) + goto out_unlock; + } else { ++bo_va->ref_count; + } - amdgpu_evf_mgr_attach_fence(&fpriv->evf_mgr, abo); drm_exec_fini(&exec); /* Validate and add eviction fence to DMABuf imports with dynamic From 76c537e697b69563438995290fddd13d692c89c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 29 Jan 2026 12:29:26 +0100 Subject: [PATCH 1941/2070] drm/amdgpu: rework amdgpu_userq_wait_ioctl v4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lockdep was complaining about a number of issues here. Especially lock inversion between syncobj, dma_resv and copying things into userspace. Rework the functionality. Split it up into multiple functions, consistenly use memdup_array_user(), fix the lock inversions and a few more bugs in error handling. v2: drop the dma_fence leak fix, turned out that was actually correct, just not well documented. Apply some more cleanup suggestion from Tvrtko. v3: rebase on already done cleanups v4: add missing dma_fence_put() in error path. Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 596 ++++++++++-------- 1 file changed, 330 insertions(+), 266 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index d8895289d97e6..3874c98d68b99 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -680,343 +680,407 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, return r; } -int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp) +/* Count the number of expected fences so userspace can alloc a buffer */ +static int +amdgpu_userq_wait_count_fences(struct drm_file *filp, + struct drm_amdgpu_userq_wait *wait_info, + u32 *syncobj_handles, u32 *timeline_points, + u32 *timeline_handles, + struct drm_gem_object **gobj_write, + struct drm_gem_object **gobj_read) { - struct drm_amdgpu_userq_wait *wait_info = data; - const unsigned int num_write_bo_handles = wait_info->num_bo_write_handles; - const unsigned int num_read_bo_handles = wait_info->num_bo_read_handles; - struct drm_amdgpu_userq_fence_info *fence_info = NULL; - struct amdgpu_fpriv *fpriv = filp->driver_priv; - struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; - struct drm_gem_object **gobj_write, **gobj_read; - u32 *timeline_points, *timeline_handles; - struct amdgpu_usermode_queue *waitq = NULL; - u32 *syncobj_handles, num_syncobj; - struct dma_fence **fences = NULL; - u16 num_points, num_fences = 0; + int num_read_bo_handles, num_write_bo_handles; + struct dma_fence_unwrap iter; + struct dma_fence *fence, *f; + unsigned int num_fences = 0; struct drm_exec exec; - int r, i, cnt; - - if (!amdgpu_userq_enabled(dev)) - return -ENOTSUPP; - - if (wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || - wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) - return -EINVAL; - - num_syncobj = wait_info->num_syncobj_handles; - syncobj_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_handles), - num_syncobj, sizeof(u32)); - if (IS_ERR(syncobj_handles)) - return PTR_ERR(syncobj_handles); - + int i, r; + + /* + * This needs to be outside of the lock provided by drm_exec for + * DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT to work correctly. + */ + + /* Count timeline fences */ + for (i = 0; i < wait_info->num_syncobj_timeline_handles; i++) { + r = drm_syncobj_find_fence(filp, timeline_handles[i], + timeline_points[i], + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + return r; + + dma_fence_unwrap_for_each(f, &iter, fence) + num_fences++; - num_points = wait_info->num_syncobj_timeline_handles; - timeline_handles = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_timeline_handles), - num_points, sizeof(u32)); - if (IS_ERR(timeline_handles)) { - r = PTR_ERR(timeline_handles); - goto free_syncobj_handles; + dma_fence_put(fence); } - timeline_points = memdup_array_user(u64_to_user_ptr(wait_info->syncobj_timeline_points), - num_points, sizeof(u32)); + /* Count boolean fences */ + for (i = 0; i < wait_info->num_syncobj_handles; i++) { + r = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + return r; - if (IS_ERR(timeline_points)) { - r = PTR_ERR(timeline_points); - goto free_timeline_handles; + num_fences++; + dma_fence_put(fence); } - r = drm_gem_objects_lookup(filp, - u64_to_user_ptr(wait_info->bo_read_handles), - num_read_bo_handles, - &gobj_read); - if (r) - goto free_timeline_points; - - r = drm_gem_objects_lookup(filp, - u64_to_user_ptr(wait_info->bo_write_handles), - num_write_bo_handles, - &gobj_write); - if (r) - goto put_gobj_read; - + /* Lock all the GEM objects */ + /* TODO: It is actually not necessary to lock them */ + num_read_bo_handles = wait_info->num_bo_read_handles; + num_write_bo_handles = wait_info->num_bo_write_handles; drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, - (num_read_bo_handles + num_write_bo_handles)); + num_read_bo_handles + num_write_bo_handles); - /* Lock all BOs with retry handling */ drm_exec_until_all_locked(&exec) { - r = drm_exec_prepare_array(&exec, gobj_read, num_read_bo_handles, 1); + r = drm_exec_prepare_array(&exec, gobj_read, + num_read_bo_handles, 1); drm_exec_retry_on_contention(&exec); - if (r) { - drm_exec_fini(&exec); - goto put_gobj_write; - } + if (r) + goto error_unlock; - r = drm_exec_prepare_array(&exec, gobj_write, num_write_bo_handles, 1); + r = drm_exec_prepare_array(&exec, gobj_write, + num_write_bo_handles, 1); drm_exec_retry_on_contention(&exec); - if (r) { - drm_exec_fini(&exec); - goto put_gobj_write; - } + if (r) + goto error_unlock; } - if (!wait_info->num_fences) { - if (num_points) { - struct dma_fence_unwrap iter; - struct dma_fence *fence; - struct dma_fence *f; - - for (i = 0; i < num_points; i++) { - r = drm_syncobj_find_fence(filp, timeline_handles[i], - timeline_points[i], - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto exec_fini; - - dma_fence_unwrap_for_each(f, &iter, fence) - num_fences++; - - dma_fence_put(fence); - } - } + /* Count read fences */ + for (i = 0; i < num_read_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; - /* Count syncobj's fence */ - for (i = 0; i < num_syncobj; i++) { - struct dma_fence *fence; + dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + DMA_RESV_USAGE_READ, fence) + num_fences++; + } - r = drm_syncobj_find_fence(filp, syncobj_handles[i], - 0, - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto exec_fini; + /* Count write fences */ + for (i = 0; i < num_write_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; + dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + DMA_RESV_USAGE_WRITE, fence) num_fences++; - dma_fence_put(fence); - } + } - /* Count GEM objects fence */ - for (i = 0; i < num_read_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; + wait_info->num_fences = num_fences; + r = 0; - dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), - DMA_RESV_USAGE_READ, fence) - num_fences++; - } +error_unlock: + /* Unlock all the GEM objects */ + drm_exec_fini(&exec); + return r; +} - for (i = 0; i < num_write_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; +static int +amdgpu_userq_wait_return_fence_info(struct drm_file *filp, + struct drm_amdgpu_userq_wait *wait_info, + u32 *syncobj_handles, u32 *timeline_points, + u32 *timeline_handles, + struct drm_gem_object **gobj_write, + struct drm_gem_object **gobj_read) +{ + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; + struct drm_amdgpu_userq_fence_info *fence_info; + int num_read_bo_handles, num_write_bo_handles; + struct amdgpu_usermode_queue *waitq; + struct dma_fence **fences, *fence, *f; + struct dma_fence_unwrap iter; + int num_points, num_syncobj; + unsigned int num_fences = 0; + struct drm_exec exec; + int i, cnt, r; - dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), - DMA_RESV_USAGE_WRITE, fence) - num_fences++; - } + fence_info = kmalloc_array(wait_info->num_fences, sizeof(*fence_info), + GFP_KERNEL); + if (!fence_info) + return -ENOMEM; - /* - * Passing num_fences = 0 means that userspace doesn't want to - * retrieve userq_fence_info. If num_fences = 0 we skip filling - * userq_fence_info and return the actual number of fences on - * args->num_fences. - */ - wait_info->num_fences = num_fences; - } else { - /* Array of fence info */ - fence_info = kmalloc_array(wait_info->num_fences, sizeof(*fence_info), GFP_KERNEL); - if (!fence_info) { - r = -ENOMEM; - goto exec_fini; - } + fences = kmalloc_array(wait_info->num_fences, sizeof(*fences), + GFP_KERNEL); + if (!fences) { + r = -ENOMEM; + goto free_fence_info; + } + + /* Retrieve timeline fences */ + num_points = wait_info->num_syncobj_timeline_handles; + for (i = 0; i < num_points; i++) { + r = drm_syncobj_find_fence(filp, timeline_handles[i], + timeline_points[i], + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + goto free_fences; + + dma_fence_unwrap_for_each(f, &iter, fence) { + if (num_fences >= wait_info->num_fences) { + r = -EINVAL; + dma_fence_put(fence); + goto free_fences; + } - /* Array of fences */ - fences = kmalloc_array(wait_info->num_fences, sizeof(*fences), GFP_KERNEL); - if (!fences) { - r = -ENOMEM; - goto free_fence_info; + fences[num_fences++] = dma_fence_get(f); } - /* Retrieve GEM read objects fence */ - for (i = 0; i < num_read_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; + dma_fence_put(fence); + } + + /* Retrieve boolean fences */ + num_syncobj = wait_info->num_syncobj_handles; + for (i = 0; i < num_syncobj; i++) { + struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), - DMA_RESV_USAGE_READ, fence) { - if (num_fences >= wait_info->num_fences) { - r = -EINVAL; - goto free_fences; - } + r = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + goto free_fences; - fences[num_fences++] = fence; - dma_fence_get(fence); - } + if (num_fences >= wait_info->num_fences) { + dma_fence_put(fence); + r = -EINVAL; + goto free_fences; } - /* Retrieve GEM write objects fence */ - for (i = 0; i < num_write_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; + /* Give the reference to the fence array */ + fences[num_fences++] = fence; + } - dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), - DMA_RESV_USAGE_WRITE, fence) { - if (num_fences >= wait_info->num_fences) { - r = -EINVAL; - goto free_fences; - } + /* Lock all the GEM objects */ + num_read_bo_handles = wait_info->num_bo_read_handles; + num_write_bo_handles = wait_info->num_bo_write_handles; + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, + num_read_bo_handles + num_write_bo_handles); - fences[num_fences++] = fence; - dma_fence_get(fence); - } - } + drm_exec_until_all_locked(&exec) { + r = drm_exec_prepare_array(&exec, gobj_read, + num_read_bo_handles, 1); + drm_exec_retry_on_contention(&exec); + if (r) + goto error_unlock; - if (num_points) { - struct dma_fence_unwrap iter; - struct dma_fence *fence; - struct dma_fence *f; - - for (i = 0; i < num_points; i++) { - r = drm_syncobj_find_fence(filp, timeline_handles[i], - timeline_points[i], - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto free_fences; - - dma_fence_unwrap_for_each(f, &iter, fence) { - if (num_fences >= wait_info->num_fences) { - r = -EINVAL; - dma_fence_put(fence); - goto free_fences; - } - - dma_fence_get(f); - fences[num_fences++] = f; - } + r = drm_exec_prepare_array(&exec, gobj_write, + num_write_bo_handles, 1); + drm_exec_retry_on_contention(&exec); + if (r) + goto error_unlock; + } - dma_fence_put(fence); + /* Retrieve GEM read objects fence */ + for (i = 0; i < num_read_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; + + dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + DMA_RESV_USAGE_READ, fence) { + if (num_fences >= wait_info->num_fences) { + r = -EINVAL; + goto error_unlock; } - } - /* Retrieve syncobj's fence */ - for (i = 0; i < num_syncobj; i++) { - struct dma_fence *fence; + fences[num_fences++] = dma_fence_get(fence); + } + } - r = drm_syncobj_find_fence(filp, syncobj_handles[i], - 0, - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto free_fences; + /* Retrieve GEM write objects fence */ + for (i = 0; i < num_write_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; + dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + DMA_RESV_USAGE_WRITE, fence) { if (num_fences >= wait_info->num_fences) { r = -EINVAL; - dma_fence_put(fence); - goto free_fences; + goto error_unlock; } - fences[num_fences++] = fence; + fences[num_fences++] = dma_fence_get(fence); } + } - /* - * Keep only the latest fences to reduce the number of values - * given back to userspace. - */ - num_fences = dma_fence_dedup_array(fences, num_fences); + drm_exec_fini(&exec); - waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id); - if (!waitq) { - r = -EINVAL; - goto free_fences; - } + /* + * Keep only the latest fences to reduce the number of values + * given back to userspace. + */ + num_fences = dma_fence_dedup_array(fences, num_fences); - for (i = 0, cnt = 0; i < num_fences; i++) { - struct amdgpu_userq_fence_driver *fence_drv; - struct amdgpu_userq_fence *userq_fence; - u32 index; - - userq_fence = to_amdgpu_userq_fence(fences[i]); - if (!userq_fence) { - /* - * Just waiting on other driver fences should - * be good for now - */ - r = dma_fence_wait(fences[i], true); - if (r) - goto free_fences; - - continue; - } + waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id); + if (!waitq) { + r = -EINVAL; + goto free_fences; + } - fence_drv = userq_fence->fence_drv; + for (i = 0, cnt = 0; i < num_fences; i++) { + struct amdgpu_userq_fence_driver *fence_drv; + struct amdgpu_userq_fence *userq_fence; + u32 index; + + userq_fence = to_amdgpu_userq_fence(fences[i]); + if (!userq_fence) { /* - * We need to make sure the user queue release their reference - * to the fence drivers at some point before queue destruction. - * Otherwise, we would gather those references until we don't - * have any more space left and crash. + * Just waiting on other driver fences should + * be good for now */ -#ifdef HAVE_STRUCT_XARRAY - r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, - xa_limit_32b, GFP_KERNEL); + r = dma_fence_wait(fences[i], true); if (r) + goto put_waitq; + + continue; + } + + fence_drv = userq_fence->fence_drv; + /* + * We need to make sure the user queue release their reference + * to the fence drivers at some point before queue destruction. + * Otherwise, we would gather those references until we don't + * have any more space left and crash. + */ +#ifdef HAVE_STRUCT_XARRAY + r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, + xa_limit_32b, GFP_KERNEL); + if (r) #else - spin_lock(&waitq->fence_drv_lock); - r = idr_alloc(&waitq->fence_drv_idr, fence_drv, 0, 0, GFP_KERNEL); - index = r; - spin_unlock(&waitq->fence_drv_lock); - if (r < 0) + spin_lock(&waitq->fence_drv_lock); + r = idr_alloc(&waitq->fence_drv_idr, fence_drv, 0, 0, GFP_KERNEL); + index = r; + spin_unlock(&waitq->fence_drv_lock); + if (r < 0) #endif - goto free_fences; + goto put_waitq; - amdgpu_userq_fence_driver_get(fence_drv); + amdgpu_userq_fence_driver_get(fence_drv); - /* Store drm syncobj's gpu va address and value */ - fence_info[cnt].va = fence_drv->va; - fence_info[cnt].value = fences[i]->seqno; + /* Store drm syncobj's gpu va address and value */ + fence_info[cnt].va = fence_drv->va; + fence_info[cnt].value = fences[i]->seqno; - /* Increment the actual userq fence count */ - cnt++; - } - - wait_info->num_fences = cnt; - /* Copy userq fence info to user space */ - if (copy_to_user(u64_to_user_ptr(wait_info->out_fences), - fence_info, wait_info->num_fences * sizeof(*fence_info))) { - r = -EFAULT; - goto free_fences; - } + /* Increment the actual userq fence count */ + cnt++; } + wait_info->num_fences = cnt; + + /* Copy userq fence info to user space */ + if (copy_to_user(u64_to_user_ptr(wait_info->out_fences), + fence_info, cnt * sizeof(*fence_info))) + r = -EFAULT; + else + r = 0; + +put_waitq: + amdgpu_userq_put(waitq); free_fences: - if (fences) { - while (num_fences-- > 0) - dma_fence_put(fences[num_fences]); - kfree(fences); - } + while (num_fences--) + dma_fence_put(fences[num_fences]); + kfree(fences); + free_fence_info: kfree(fence_info); -exec_fini: + return r; + +error_unlock: drm_exec_fini(&exec); -put_gobj_write: - for (i = 0; i < num_write_bo_handles; i++) - drm_gem_object_put(gobj_write[i]); + goto free_fences; +} + +int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + int num_points, num_syncobj, num_read_bo_handles, num_write_bo_handles; + u32 *syncobj_handles, *timeline_points, *timeline_handles; + struct drm_amdgpu_userq_wait *wait_info = data; + struct drm_gem_object **gobj_write; + struct drm_gem_object **gobj_read; + void __user *ptr; + int r; + + if (!amdgpu_userq_enabled(dev)) + return -ENOTSUPP; + + if (wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) + return -EINVAL; + + num_syncobj = wait_info->num_syncobj_handles; + ptr = u64_to_user_ptr(wait_info->syncobj_handles); + syncobj_handles = memdup_array_user(ptr, num_syncobj, sizeof(u32)); + if (IS_ERR(syncobj_handles)) + return PTR_ERR(syncobj_handles); + + num_points = wait_info->num_syncobj_timeline_handles; + ptr = u64_to_user_ptr(wait_info->syncobj_timeline_handles); + timeline_handles = memdup_array_user(ptr, num_points, sizeof(u32)); + if (IS_ERR(timeline_handles)) { + r = PTR_ERR(timeline_handles); + goto free_syncobj_handles; + } + + ptr = u64_to_user_ptr(wait_info->syncobj_timeline_points); + timeline_points = memdup_array_user(ptr, num_points, sizeof(u32)); + if (IS_ERR(timeline_points)) { + r = PTR_ERR(timeline_points); + goto free_timeline_handles; + } + + num_read_bo_handles = wait_info->num_bo_read_handles; + ptr = u64_to_user_ptr(wait_info->bo_read_handles), + r = drm_gem_objects_lookup(filp, ptr, num_read_bo_handles, &gobj_read); + if (r) + goto free_timeline_points; + + num_write_bo_handles = wait_info->num_bo_write_handles; + ptr = u64_to_user_ptr(wait_info->bo_write_handles), + r = drm_gem_objects_lookup(filp, ptr, num_write_bo_handles, + &gobj_write); + if (r) + goto put_gobj_read; + + /* + * Passing num_fences = 0 means that userspace doesn't want to + * retrieve userq_fence_info. If num_fences = 0 we skip filling + * userq_fence_info and return the actual number of fences on + * args->num_fences. + */ + if (!wait_info->num_fences) { + r = amdgpu_userq_wait_count_fences(filp, wait_info, + syncobj_handles, + timeline_points, + timeline_handles, + gobj_write, + gobj_read); + } else { + r = amdgpu_userq_wait_return_fence_info(filp, wait_info, + syncobj_handles, + timeline_points, + timeline_handles, + gobj_write, + gobj_read); + } + + while (num_write_bo_handles--) + drm_gem_object_put(gobj_write[num_write_bo_handles]); kvfree(gobj_write); + put_gobj_read: - for (i = 0; i < num_read_bo_handles; i++) - drm_gem_object_put(gobj_read[i]); + while (num_read_bo_handles--) + drm_gem_object_put(gobj_read[num_read_bo_handles]); kvfree(gobj_read); + free_timeline_points: kfree(timeline_points); free_timeline_handles: kfree(timeline_handles); free_syncobj_handles: kfree(syncobj_handles); - - if (waitq) - amdgpu_userq_put(waitq); - return r; } From 1ff8049c052aca3923744ebe76256482eea7242a Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 12 Mar 2026 20:34:48 +0530 Subject: [PATCH 1942/2070] drm/amdgpu: Move amdgpu_vm_is_bo_always_valid() before first use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Smatch reports that 'bo' could be NULL in amdgpu_vm_bo_update(), even though amdgpu_vm_is_bo_always_valid() already checks for a NULL BO. Move amdgpu_vm_is_bo_always_valid() earlier in the file so the helper definition appears before its first use. This allows static analysis tools to see the NULL check performed by the helper and avoids the warning. Suggested-by: Tvrtko Ursulin Cc: Dan Carpenter Cc: Tvrtko Ursulin Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Tvrtko Ursulin Change-Id: I9b4d5cf2cdbbb89c81911cf54bcbffcce2ce7b58 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 28 +++++++++++++------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 00760231fcb16..ef79044bdd0af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -138,6 +138,20 @@ static void amdgpu_vm_assert_locked(struct amdgpu_vm *vm) dma_resv_assert_held(vm->root.bo->tbo.base.resv); } +/** + * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid + * + * @vm: VM to test against. + * @bo: BO to be tested. + * + * Returns true if the BO shares the dma_resv object with the root PD and is + * always guaranteed to be valid inside the VM. + */ +bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) +{ + return bo && amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo); +} + /** * amdgpu_vm_bo_evicted - vm_bo is evicted * @@ -3271,20 +3285,6 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, #endif } -/** - * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid - * - * @vm: VM to test against. - * @bo: BO to be tested. - * - * Returns true if the BO shares the dma_resv object with the root PD and is - * always guaranteed to be valid inside the VM. - */ -bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) -{ - return bo && amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo); -} - void amdgpu_vm_print_task_info(struct amdgpu_device *adev, struct amdgpu_task_info *task_info) { From a9a3f6c13fc3b8635fb86e2a4bb0d2dd1f303d33 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 13 Mar 2026 14:17:10 +0800 Subject: [PATCH 1943/2070] drm/amdgpu: replace WARN with DRM_ERROR for invalid sched priority MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_sched_ioctl() currently uses WARN(1, ...) when userspace passes an out-of-range context priority value. WARN(1, ...) is unconditional and produces a full stack trace, which is disproportionate for a simple input validation failure -- the invalid value is already rejected with -EINVAL on the next line. Replace WARN(1, ...) with DRM_ERROR() to log the invalid value at an appropriate level without generating a stack dump. The -EINVAL return to userspace is unchanged. No functional change for well-formed userspace callers. v2: - Reworked commit message to focus on appropriate log level for parameter validation - Clarified that -EINVAL behavior is preserved (Vitaly) v3: completely drop that warning. Invalid parameters should never clutter the system log. (Christian) Reviewed-by: Vitaly Prosyak Reviewed-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 341beec595375..0eecfaa3a94c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -103,10 +103,8 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, return -EINVAL; } - if (!amdgpu_ctx_priority_is_valid(args->in.priority)) { - WARN(1, "Invalid context priority %d\n", args->in.priority); + if (!amdgpu_ctx_priority_is_valid(args->in.priority)) return -EINVAL; - } switch (args->in.op) { case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: From ceaf34c3b7d0afd1298533a189684f39e017aae1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 29 Jan 2026 12:58:10 +0100 Subject: [PATCH 1944/2070] drm/amdgpu: make amdgpu_user_wait_ioctl more resilent v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the memory allocated by userspace isn't sufficient for all the fences then just wait on them instead of returning an error. v2: use correct variable as pointed out by Sunil Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 48 +++++++++++-------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 3874c98d68b99..fdef444e0ad28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -769,7 +769,7 @@ amdgpu_userq_wait_count_fences(struct drm_file *filp, num_fences++; } - wait_info->num_fences = num_fences; + wait_info->num_fences = min(num_fences, USHRT_MAX); r = 0; error_unlock: @@ -778,6 +778,19 @@ amdgpu_userq_wait_count_fences(struct drm_file *filp, return r; } +static int +amdgpu_userq_wait_add_fence(struct drm_amdgpu_userq_wait *wait_info, + struct dma_fence **fences, unsigned int *num_fences, + struct dma_fence *fence) +{ + /* As fallback shouldn't userspace allocate enough space */ + if (*num_fences >= wait_info->num_fences) + return dma_fence_wait(fence, true); + + fences[(*num_fences)++] = dma_fence_get(fence); + return 0; +} + static int amdgpu_userq_wait_return_fence_info(struct drm_file *filp, struct drm_amdgpu_userq_wait *wait_info, @@ -821,13 +834,12 @@ amdgpu_userq_wait_return_fence_info(struct drm_file *filp, goto free_fences; dma_fence_unwrap_for_each(f, &iter, fence) { - if (num_fences >= wait_info->num_fences) { - r = -EINVAL; + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, f); + if (r) { dma_fence_put(fence); goto free_fences; } - - fences[num_fences++] = dma_fence_get(f); } dma_fence_put(fence); @@ -844,14 +856,12 @@ amdgpu_userq_wait_return_fence_info(struct drm_file *filp, if (r) goto free_fences; - if (num_fences >= wait_info->num_fences) { - dma_fence_put(fence); - r = -EINVAL; + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, fence); + dma_fence_put(fence); + if (r) goto free_fences; - } - /* Give the reference to the fence array */ - fences[num_fences++] = fence; } /* Lock all the GEM objects */ @@ -881,12 +891,10 @@ amdgpu_userq_wait_return_fence_info(struct drm_file *filp, dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, DMA_RESV_USAGE_READ, fence) { - if (num_fences >= wait_info->num_fences) { - r = -EINVAL; + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, fence); + if (r) goto error_unlock; - } - - fences[num_fences++] = dma_fence_get(fence); } } @@ -897,12 +905,10 @@ amdgpu_userq_wait_return_fence_info(struct drm_file *filp, dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, DMA_RESV_USAGE_WRITE, fence) { - if (num_fences >= wait_info->num_fences) { - r = -EINVAL; + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, fence); + if (r) goto error_unlock; - } - - fences[num_fences++] = dma_fence_get(fence); } } From d7fa7b47ef0024ca8acc67de55a20ed8598469ea Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 13 Mar 2026 14:07:55 +0800 Subject: [PATCH 1945/2070] drm/amdkcl: fix miss include headers in m4 It's caused by the commit: 4cac08c8a "drm/amdkcl: test if drm_gem_dmabuf_vmap() has struct iosys_map arg" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index 6bc1bbb0b3346..b3732d2b30714 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -49,6 +49,7 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include + #include ],[ struct iosys_map map; drm_gem_dmabuf_vmap(NULL, &map); From 564b35476203a47212beb2ecfb203c4f692755d5 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 19 Mar 2026 14:20:05 +0800 Subject: [PATCH 1946/2070] Bump AMDGPU version to 6.19.2 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index c5bf80bd9a95a..1f206d258caeb 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.19.1) +AC_INIT(amdgpu-dkms, 6.19.2) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From aa65c840ba4b9947e4b33cab86952c3ad706d544 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sun, 2 Nov 2025 18:55:16 +0800 Subject: [PATCH 1947/2070] drm/amd/pm: Add smu v15_0_8 driver interface header Add smu v15_0_8 driver interface header v2: squash in updates (Alex) Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- .../inc/pmfw_if/smu15_driver_if_v15_0_8.h | 295 ++++++++++++++++++ 1 file changed, 295 insertions(+) create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h new file mode 100644 index 0000000000000..6993d866183d7 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h @@ -0,0 +1,295 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SMU_15_0_8_DRIVER_IF_H +#define SMU_15_0_8_DRIVER_IF_H + +//I2C Interface +#define NUM_I2C_CONTROLLERS 8 +#define I2C_CONTROLLER_ENABLED 1 +#define I2C_CONTROLLER_DISABLED 0 + +#define MAX_SW_I2C_COMMANDS 24 + +typedef enum { + I2C_CONTROLLER_PORT_0, + I2C_CONTROLLER_PORT_COUNT, +} I2cControllerPort_e; + +typedef enum { + /* 50 Kbits/s not supported anymore! */ + UNSUPPORTED_1, + /* 100 Kbits/s */ + I2C_SPEED_STANDARD_100K, + /* 400 Kbits/s */ + I2C_SPEED_FAST_400K, + /* 1 Mbits/s (in fast mode) */ + I2C_SPEED_FAST_PLUS_1M, + /* 1 Mbits/s (in high speed mode) not supported anymore!*/ + UNSUPPORTED_2, + /* 2.3 Mbits/s not supported anymore! */ + UNSUPPORTED_3, + I2C_SPEED_COUNT, +} I2cSpeed_e; + +typedef enum { + I2C_CMD_READ, + I2C_CMD_WRITE, + I2C_CMD_COUNT, +} I2cCmdType_e; + +#define CMDCONFIG_STOP_BIT 0 +#define CMDCONFIG_RESTART_BIT 1 +/* bit should be 0 for read, 1 for write */ +#define CMDCONFIG_READWRITE_BIT 2 + +#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) +#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) +#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) + +/* 64 Bit register offsets for PPSMC_MSG_McaBankDumpDW, PPSMC_MSG_McaBankCeDumpDW messages + * eg to read MCA_BANK_OFFSET_SYND for CE index, call PPSMC_MSG_McaBankCeDumpDW twice, + * (index << 16 + MCA_BANK_OFFSET_SYND*8) argument for 1st DWORD, and + * ((index << 16 ) + MCA_BANK_OFFSET_SYND*8 + 4) argument for 2nd DWORD */ +typedef enum { + MCA_BANK_OFFSET_CTL = 0, + MCA_BANK_OFFSET_STATUS = 1, + MCA_BANK_OFFSET_ADDR = 2, + MCA_BANK_OFFSET_MISC = 3, + MCA_BANK_OFFSET_IPID = 5, + MCA_BANK_OFFSET_SYND = 6, + MCA_BANK_OFFSET_MAX = 16, +} MCA_BANK_OFFSET_e; + +/* Firmware MP1 AID MCA Error Codes stored in MCA_MP_MP1:MCMP1_SYNDT0 errorinformation */ +typedef enum { + /* MMHUB */ + CODE_DAGB0 = 0, + CODE_DAGB1 = 1, + CODE_DAGB2 = 2, + CODE_DAGB3 = 3, + CODE_DAGB4 = 4, + CODE_EA0 = 5, + CODE_EA1 = 6, + CODE_EA2 = 7, + CODE_EA3 = 8, + CODE_EA4 = 9, + CODE_UTCL2_ROUTER = 10, + CODE_VML2 = 11, + CODE_VML2_WALKER = 12, + CODE_MMCANE = 13, + + /* VCN VCPU */ + CODE_VIDD = 14, + CODE_VIDV = 15, + /* VCN JPEG */ + CODE_JPEG0S = 16, + CODE_JPEG0D = 17, + CODE_JPEG1S = 18, + CODE_JPEG1D = 19, + CODE_JPEG2S = 20, + CODE_JPEG2D = 21, + CODE_JPEG3S = 22, + CODE_JPEG3D = 23, + CODE_JPEG4S = 24, + CODE_JPEG4D = 25, + CODE_JPEG5S = 26, + CODE_JPEG5D = 27, + CODE_JPEG6S = 28, + CODE_JPEG6D = 29, + CODE_JPEG7S = 30, + CODE_JPEG7D = 31, + /* VCN MMSCH */ + CODE_MMSCHD = 32, + + /* SDMA */ + CODE_SDMA0 = 33, + CODE_SDMA1 = 34, + CODE_SDMA2 = 35, + CODE_SDMA3 = 36, + + /* SOC */ + CODE_HDP = 37, + CODE_ATHUB = 38, + CODE_IH = 39, + CODE_XHUB_POISON = 40, + CODE_SMN_SLVERR = 41, + CODE_WDT = 42, + + CODE_UNKNOWN = 43, + CODE_DMA = 44, + CODE_COUNT = 45, +} ERR_CODE_e; + +/* Firmware MP5 XCD MCA Error Codes stored in MCA_MP_MP5:MCMP5_SYNDT0 errorinformation */ +typedef enum { + /* SH POISON FED */ + SH_FED_CODE = 0, + /* GCEA Pin UE_ERR regs */ + GCEA_CODE = 1, + SQ_CODE = 2, + LDS_CODE = 3, + GDS_CODE = 4, + SP0_CODE = 5, + SP1_CODE = 6, + TCC_CODE = 7, + TCA_CODE = 8, + TCX_CODE = 9, + CPC_CODE = 10, + CPF_CODE = 11, + CPG_CODE = 12, + SPI_CODE = 13, + RLC_CODE = 14, + /* GCEA Pin, UE_EDC regs */ + SQC_CODE = 15, + TA_CODE = 16, + TD_CODE = 17, + TCP_CODE = 18, + TCI_CODE = 19, + /* GC Router */ + GC_ROUTER_CODE = 20, + VML2_CODE = 21, + VML2_WALKER_CODE = 22, + ATCL2_CODE = 23, + GC_CANE_CODE = 24, + + /* SOC error codes 41-43 are common with ERR_CODE_e */ + MP5_CODE_SMN_SLVERR = CODE_SMN_SLVERR, + MP5_CODE_UNKNOWN = CODE_UNKNOWN, +} GC_ERROR_CODE_e; + +/* SW I2C Command Table */ +typedef struct { + /* Return data for read. Data to send for write*/ + uint8_t ReadWriteData; + /* Includes whether associated command should have a stop or restart command, + * and is a read or write */ + uint8_t CmdConfig; +} SwI2cCmd_t; + +/* SW I2C Request Table */ +typedef struct { + /* CKSVII2C0(0) or //CKSVII2C1(1) */ + uint8_t I2CcontrollerPort; + /* Use I2cSpeed_e to indicate speed to select */ + uint8_t I2CSpeed; + /* Slave address of device */ + uint8_t SlaveAddress; + /* Number of commands */ + uint8_t NumCmds; + SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; +} SwI2cRequest_t; + +typedef struct { + SwI2cRequest_t SwI2cRequest; + uint32_t Spare[8]; + /* SMU internal use */ + uint32_t MmHubPadding[8]; +} SwI2cRequestExternal_t; + +typedef enum { + PPCLK_UCLK, + PPCLK_COUNT, +} PPCLK_e; + +typedef enum { + GPIO_INT_POLARITY_ACTIVE_LOW, + GPIO_INT_POLARITY_ACTIVE_HIGH, +} GpioIntPolarity_e; + +/* TODO confirm if this is used in MI300 PPSMC_MSG_SetUclkDpmMode */ +typedef enum { + UCLK_DPM_MODE_BANDWIDTH, + UCLK_DPM_MODE_LATENCY, +} UCLK_DPM_MODE_e; + +typedef struct { + /* 2 AVFS.PSM chains */ + uint16_t AvgPsmCount_Chain0[13]; + uint16_t AvgPsmCount_Chain1[15]; + uint16_t MinPsmCount_Chain0[13]; + uint16_t MinPsmCount_Chain1[15]; + float MaxTemperature; + + /* For voltage conversions, these are the array indexes + * 0:SOCIO + * 1:065_UCIE + * 2:075_UCIE + * 3:11_GTA + * 4:075_GTA */ + float MinPsmVoltage[5]; + float AvgPsmVoltage[5]; +} AvfsDebugTableMid_t; + +typedef struct { + /* 7 AVFS.PSM chains - not including TRO */ + uint16_t AvgPsmCount_Chain0[15]; + uint16_t AvgPsmCount_Chain1[15]; + uint16_t AvgPsmCount_Chain2[13]; + uint16_t AvgPsmCount_Chain3[13]; + uint16_t AvgPsmCount_Chain4[15]; + uint16_t AvgPsmCount_Chain5[15]; + uint16_t AvgPsmCount_Chain6[5]; + uint16_t MinPsmCount_Chain0[15]; + uint16_t MinPsmCount_Chain1[15]; + uint16_t MinPsmCount_Chain2[13]; + uint16_t MinPsmCount_Chain3[13]; + uint16_t MinPsmCount_Chain4[15]; + uint16_t MinPsmCount_Chain5[15]; + uint16_t MinPsmCount_Chain6[5]; + float MaxTemperature; + + /* For voltage conversions, these are the array indexes + * 0:VDDX */ + float MinPsmVoltage; + float AvgPsmVoltage; +} AvfsDebugTableAid_t; + +typedef struct { + /* 0-27 GFX, 28-29 SOC */ + uint16_t avgPsmCount[30]; + uint16_t minPsmCount[30]; + float avgPsmVoltage[30]; + float minPsmVoltage[30]; +} AvfsDebugTableXcd_t; + +/* Defines used for IH-based thermal interrupts to GFX driver - A/X only */ +#define IH_INTERRUPT_ID_TO_DRIVER 0xFE +#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 +#define IH_INTERRUPT_VFFLR_INT 0xA + +/* thermal over-temp mask defines for IH interrup to host */ +#define THROTTLER_PROCHOT_BIT 0 +#define THROTTLER_RESERVED 1 +/* AID, XCD, CCD throttling */ +#define THROTTLER_THERMAL_SOCKET_BIT 2 +/* VRHOT */ +#define THROTTLER_THERMAL_VR_BIT 3 +#define THROTTLER_THERMAL_HBM_BIT 4 +/* UEs are always reported, set flag to 0 to prevent clearing of UEs */ +#define ClearMcaOnRead_UE_FLAG_MASK 0x1 +/* Enable CE logging and clearing to driver */ +#define ClearMcaOnRead_CE_POLL_MASK 0x2 +/* AID MMHUB client IP CE Logging and clearing */ +#define ClearMcaOnRead_MMHUB_POLL_MASK 0x4 + +#endif From 9c2bb3683bd2d9b34564e76093d8f8c618ff3dd6 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sun, 2 Nov 2025 18:56:52 +0800 Subject: [PATCH 1948/2070] drm/amd/pm: Add smu v15_0_8 message header Add smu v15_0_8 message header v2: squash in updates (Alex) Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- .../pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h new file mode 100644 index 0000000000000..7ffb445f4c0cc --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h @@ -0,0 +1,100 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SMU_15_0_8_PPSMC_H +#define SMU_15_0_8_PPSMC_H + +/* SMU Response Codes */ +#define PPSMC_Result_OK 0x1 +#define PPSMC_Result_Failed 0xFF +#define PPSMC_Result_UnknownCmd 0xFE +#define PPSMC_Result_CmdRejectedPrereq 0xFD +#define PPSMC_Result_CmdRejectedBusy 0xFC + +/* Message Definitions */ +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion 0x2 +#define PPSMC_MSG_GfxDriverReset 0x3 +#define PPSMC_MSG_GetDriverIfVersion 0x4 +#define PPSMC_MSG_EnableAllSmuFeatures 0x5 +#define PPSMC_MSG_GetMetricsVersion 0x6 +#define PPSMC_MSG_GetMetricsTable 0x7 +#define PPSMC_MSG_GetEnabledSmuFeatures 0x8 +#define PPSMC_MSG_SetDriverDramAddr 0x9 //ARG0: low address, ARG1: high address +#define PPSMC_MSG_SetToolsDramAddr 0xA //ARG0: low address, ARG1: high address +//#define PPSMC_MSG_SetSystemVirtualDramAddr 0xB +#define PPSMC_MSG_SetSoftMaxByFreq 0xC +#define PPSMC_MSG_SetPptLimit 0xD +#define PPSMC_MSG_GetPptLimit 0xE +#define PPSMC_MSG_DramLogSetDramAddr 0xF //ARG0: low address, ARG1: high address, ARG2: size +#define PPSMC_MSG_HeavySBR 0x10 +#define PPSMC_MSG_DFCstateControl 0x11 +#define PPSMC_MSG_GfxDriverResetRecovery 0x12 +#define PPSMC_MSG_TriggerVFFLR 0x13 +#define PPSMC_MSG_SetSoftMinGfxClk 0x14 +#define PPSMC_MSG_SetSoftMaxGfxClk 0x15 +#define PPSMC_MSG_PrepareForDriverUnload 0x16 +#define PPSMC_MSG_QueryValidMcaCount 0x17 +#define PPSMC_MSG_McaBankDumpDW 0x18 +#define PPSMC_MSG_ClearMcaOnRead 0x19 +#define PPSMC_MSG_QueryValidMcaCeCount 0x1A +#define PPSMC_MSG_McaBankCeDumpDW 0x1B +#define PPSMC_MSG_SelectPLPDMode 0x1C +#define PPSMC_MSG_SetThrottlingPolicy 0x1D +#define PPSMC_MSG_ResetSDMA 0x1E +#define PPSMC_MSG_GetRasTableVersion 0x1F +#define PPSMC_MSG_GetRmaStatus 0x20 +#define PPSMC_MSG_GetBadPageCount 0x21 +#define PPSMC_MSG_GetBadPageMcaAddress 0x22 +#define PPSMC_MSG_GetBadPagePaAddress 0x23 +#define PPSMC_MSG_SetTimestamp 0x24 +#define PPSMC_MSG_GetTimestamp 0x25 +#define PPSMC_MSG_GetRasPolicy 0x26 +#define PPSMC_MSG_GetBadPageIpIdLoHi 0x27 +#define PPSMC_MSG_EraseRasTable 0x28 +#define PPSMC_MSG_GetStaticMetricsTable 0x29 +#define PPSMC_MSG_ResetVfArbitersByIndex 0x2A +#define PPSMC_MSG_GetBadPageSeverity 0x2B +#define PPSMC_MSG_GetSystemMetricsTable 0x2C +#define PPSMC_MSG_GetSystemMetricsVersion 0x2D +#define PPSMC_MSG_ResetVCN 0x2E +#define PPSMC_MSG_SetFastPptLimit 0x2F +#define PPSMC_MSG_GetFastPptLimit 0x30 +#define PPSMC_MSG_SetSoftMinGl2clk 0x31 +#define PPSMC_MSG_SetSoftMaxGl2clk 0x32 +#define PPSMC_MSG_SetSoftMinFclk 0x33 +#define PPSMC_MSG_SetSoftMaxFclk 0x34 +#define PPSMC_Message_Count 0x35 + +/* PSMC Reset Types for driver msg argument */ +#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 +#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x2 +#define PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET 0x3 + +/* PLPD modes */ +#define PPSMC_PLPD_MODE_DEFAULT 0x1 +#define PPSMC_PLPD_MODE_OPTIMIZED 0x2 + +typedef uint32_t PPSMC_Result; +typedef uint32_t PPSMC_MSG; + +#endif From e5669d63126c753217ad70d83a86a4c8b74404ca Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sun, 2 Nov 2025 18:58:46 +0800 Subject: [PATCH 1949/2070] drm/amd/pm: Add smu v15_0_8 pmfw header Add smu v15_0_8 pmfw header v2: squash in updates (Alex) Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- .../pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h | 427 ++++++++++++++++++ 1 file changed, 427 insertions(+) create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h new file mode 100644 index 0000000000000..a3401c4cc20bd --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h @@ -0,0 +1,427 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SMU_15_0_8_PMFW_H +#define SMU_15_0_8_PMFW_H + +#define NUM_VCLK_DPM_LEVELS 4 +#define NUM_DCLK_DPM_LEVELS 4 +#define NUM_SOCCLK_DPM_LEVELS 4 +#define NUM_LCLK_DPM_LEVELS 4 +#define NUM_UCLK_DPM_LEVELS 4 +#define NUM_FCLK_DPM_LEVELS 4 +#define NUM_XGMI_DPM_LEVELS 2 +#define NUM_PCIE_BITRATES 4 +#define NUM_XGMI_BITRATES 4 +#define NUM_XGMI_WIDTHS 3 +#define NUM_GFX_P2S_TABLES 8 +#define NUM_PSM_DIDT_THRESHOLDS 3 +#define NUM_XCD_XVMIN_VMIN_THRESHOLDS 3 + +#define PRODUCT_MODEL_NUMBER_LEN 20 +#define PRODUCT_NAME_LEN 64 +#define PRODUCT_SERIAL_LEN 20 +#define PRODUCT_MANUFACTURER_NAME_LEN 32 +#define PRODUCT_FRU_ID_LEN 32 + +//Feature ID list +#define FEATURE_ID_DATA_CALCULATION 1 +#define FEATURE_ID_DPM_FCLK 2 +#define FEATURE_ID_DPM_GFXCLK 3 +#define FEATURE_ID_DPM_SPARE_4 4 +#define FEATURE_ID_DPM_SPARE_5 5 +#define FEATURE_ID_DPM_UCLK 6 +#define FEATURE_ID_DPM_SPARE_7 7 +#define FEATURE_ID_DPM_XGMI 8 +#define FEATURE_ID_DS_FCLK 9 +#define FEATURE_ID_DS_GFXCLK 10 +#define FEATURE_ID_DS_LCLK 11 +#define FEATURE_ID_DS_MP0CLK 12 +#define FEATURE_ID_DS_MP1CLK 13 +#define FEATURE_ID_DS_MPIOCLK 14 +#define FEATURE_ID_DS_SOCCLK 15 +#define FEATURE_ID_DS_VCN 16 +#define FEATURE_ID_PPT 17 +#define FEATURE_ID_TDC 18 +#define FEATURE_ID_THERMAL 19 +#define FEATURE_ID_SOC_PCC 20 +#define FEATURE_ID_PROCHOT 21 +#define FEATURE_ID_XVMIN0_VMIN_AID 22 +#define FEATURE_ID_XVMIN1_DD_AID 23 +#define FEATURE_ID_XVMIN0_VMIN_XCD 24 +#define FEATURE_ID_XVMIN1_DD_XCD 25 +#define FEATURE_ID_FW_CTF 26 +#define FEATURE_ID_MGCG 27 +#define FEATURE_ID_PSI7 28 +#define FEATURE_ID_XGMI_PER_LINK_PWR_DOWN 29 +#define FEATURE_ID_SOC_DC_RTC 30 +#define FEATURE_ID_GFX_DC_RTC 31 +#define FEATURE_ID_DVM_MIN_PSM 32 +#define FEATURE_ID_PRC 33 +#define FEATURE_ID_PSM_DIDT 34 +#define FEATURE_ID_PIT 35 +#define FEATURE_ID_DVO 36 +#define FEATURE_ID_XVMIN_CLKSTOP_DS 37 +#define FEATURE_ID_HBM_THROTTLE_CTRL 38 +#define FEATURE_ID_DPM_GL2CLK 39 +#define FEATURE_ID_GC_CAC_EDC 40 +#define FEATURE_ID_DS_DMABECLK 41 +#define FEATURE_ID_DS_MPIFOECLK 42 +#define FEATURE_ID_DS_MPRASCLK 43 +#define FEATURE_ID_DS_MPNHTCLK 44 +#define FEATURE_ID_DS_FIOCLK 45 +#define FEATURE_ID_DS_DXIOCLK 46 +#define FEATURE_ID_PCC 47 +#define FEATURE_ID_OCP 48 +#define FEATURE_ID_TRO 49 +#define FEATURE_ID_GL2_CAC_EDC 50 +#define FEATURE_ID_SPARE_51 51 +#define FEATURE_ID_GL2_CGCG 52 +#define FEATURE_ID_XCAC 53 +#define FEATURE_ID_DS_GL2CLK 54 +#define FEATURE_ID_FCS_VIN_PCC 55 +#define FEATURE_ID_FCS_VDDX_OCP_WARN 56 +#define FEATURE_ID_FCS_PWRBRK 57 +#define FEATURE_ID_DF_CSTATE 58 +#define FEATURE_ID_ARO 59 +#define FEATURE_ID_PS_PsPowerLimit 60 +#define FEATURE_ID_PS_PsPowerFloor 61 +#define FEATURE_ID_OCPWARNRC 62 +#define FEATURE_ID_XGMI_FOLDING 63 +#define FEATURE_ID_SMU_CG 64 +#define NUM_FEATURES 65 + +//MGCG Feature ID List +#define WAFL_CG 0 +#define SMU_FUSE_CG_DEEPSLEEP 1 +#define SMUIO_CG 2 +#define RSMU_MGCG 3 +#define SMU_CLK_MGCG 4 +#define MP5_CG 5 +#define UMC_CG 6 +#define WAFL0_CLK 7 +#define WAFL1_CLK 8 +#define VCN_MGCG 9 +#define GL2_MGCG 10 +#define MGCG_NUM_FEATURES 11 + +/* enum for MPIO PCIe gen speed msgs */ +typedef enum { + PCIE_LINK_SPEED_INDEX_TABLE_GEN1, + PCIE_LINK_SPEED_INDEX_TABLE_GEN2, + PCIE_LINK_SPEED_INDEX_TABLE_GEN3, + PCIE_LINK_SPEED_INDEX_TABLE_GEN4, + PCIE_LINK_SPEED_INDEX_TABLE_GEN5, + PCIE_LINK_SPEED_INDEX_TABLE_GEN6, + PCIE_LINK_SPEED_INDEX_TABLE_GEN6_ESM, + PCIE_LINK_SPEED_INDEX_TABLE_COUNT +} PCIE_LINK_SPEED_INDEX_TABLE_e; + +typedef enum { + GFX_GUARDBAND_OFFSET_0, + GFX_GUARDBAND_OFFSET_1, + GFX_GUARDBAND_OFFSET_2, + GFX_GUARDBAND_OFFSET_3, + GFX_GUARDBAND_OFFSET_4, + GFX_GUARDBAND_OFFSET_5, + GFX_GUARDBAND_OFFSET_6, + GFX_GUARDBAND_OFFSET_7, + GFX_GUARDBAND_OFFSET_COUNT +} GFX_GUARDBAND_OFFSET_e; + +typedef enum { + GFX_DVM_MARGINHI_0, + GFX_DVM_MARGINHI_1, + GFX_DVM_MARGINHI_2, + GFX_DVM_MARGINHI_3, + GFX_DVM_MARGINHI_4, + GFX_DVM_MARGINHI_5, + GFX_DVM_MARGINHI_6, + GFX_DVM_MARGINHI_7, + GFX_DVM_MARGINLO_0, + GFX_DVM_MARGINLO_1, + GFX_DVM_MARGINLO_2, + GFX_DVM_MARGINLO_3, + GFX_DVM_MARGINLO_4, + GFX_DVM_MARGINLO_5, + GFX_DVM_MARGINLO_6, + GFX_DVM_MARGINLO_7, + GFX_DVM_MARGIN_COUNT +} GFX_DVM_MARGIN_e; + +typedef enum{ + SYSTEM_TEMP_UBB_FPGA, + SYSTEM_TEMP_UBB_FRONT, + SYSTEM_TEMP_UBB_BACK, + SYSTEM_TEMP_UBB_OAM7, + SYSTEM_TEMP_UBB_IBC, + SYSTEM_TEMP_UBB_UFPGA, + SYSTEM_TEMP_UBB_OAM1, + SYSTEM_TEMP_OAM_0_1_HSC, + SYSTEM_TEMP_OAM_2_3_HSC, + SYSTEM_TEMP_OAM_4_5_HSC, + SYSTEM_TEMP_OAM_6_7_HSC, + SYSTEM_TEMP_UBB_FPGA_0V72_VR, + SYSTEM_TEMP_UBB_FPGA_3V3_VR, + SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, + SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, + SYSTEM_TEMP_RETIMER_0_1_0V9_VR, + SYSTEM_TEMP_RETIMER_4_5_0V9_VR, + SYSTEM_TEMP_RETIMER_2_3_0V9_VR, + SYSTEM_TEMP_RETIMER_6_7_0V9_VR, + SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, + SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, + SYSTEM_TEMP_IBC_HSC, + SYSTEM_TEMP_IBC, + SYSTEM_TEMP_MAX_ENTRIES = 32 +} SYSTEM_TEMP_e; + +typedef enum{ + NODE_TEMP_RETIMER, + NODE_TEMP_IBC_TEMP, + NODE_TEMP_IBC_2_TEMP, + NODE_TEMP_VDD18_VR_TEMP, + NODE_TEMP_04_HBM_B_VR_TEMP, + NODE_TEMP_04_HBM_D_VR_TEMP, + NODE_TEMP_MAX_TEMP_ENTRIES = 12 +} NODE_TEMP_e; + +typedef enum { + SVI_PLANE_VDDCR_X0_TEMP, + SVI_PLANE_VDDCR_X1_TEMP, + + SVI_PLANE_VDDIO_HBM_B_TEMP, + SVI_PLANE_VDDIO_HBM_D_TEMP, + SVI_PLANE_VDDIO_04_HBM_B_TEMP, + SVI_PLANE_VDDIO_04_HBM_D_TEMP, + SVI_PLANE_VDDCR_HBM_B_TEMP, + SVI_PLANE_VDDCR_HBM_D_TEMP, + SVI_PLANE_VDDCR_075_HBM_B_TEMP, + SVI_PLANE_VDDCR_075_HBM_D_TEMP, + + SVI_PLANE_VDDIO_11_GTA_A_TEMP, + SVI_PLANE_VDDIO_11_GTA_C_TEMP, + SVI_PLANE_VDDAN_075_GTA_A_TEMP, + SVI_PLANE_VDDAN_075_GTA_C_TEMP, + + SVI_PLANE_VDDCR_075_UCIE_TEMP, + SVI_PLANE_VDDIO_065_UCIEAA_TEMP, + SVI_PLANE_VDDIO_065_UCIEAM_A_TEMP, + SVI_PLANE_VDDIO_065_UCIEAM_C_TEMP, + + SVI_PLANE_VDDCR_SOCIO_A_TEMP, + SVI_PLANE_VDDCR_SOCIO_C_TEMP, + + SVI_PLANE_VDDAN_075_TEMP, + SVI_MAX_TEMP_ENTRIES, //22 +} SVI_TEMP_e; + +typedef enum{ + SYSTEM_POWER_UBB_POWER, + SYSTEM_POWER_UBB_POWER_THRESHOLD, + SYSTEM_POWER_MAX_ENTRIES_WO_RESERVED, + SYSTEM_POWER_MAX_ENTRIES = 4 +} SYSTEM_POWER_e; + +#define SMU_METRICS_TABLE_VERSION 0xF + +typedef struct __attribute__((packed, aligned(4))) { + uint64_t AccumulationCounter; + + //TEMPERATURE + uint32_t MaxSocketTemperature; + uint32_t MaxVrTemperature; + uint32_t HbmTemperature[12]; + uint64_t MaxSocketTemperatureAcc; + uint64_t MaxVrTemperatureAcc; + uint64_t HbmTemperatureAcc[12]; + uint32_t MidTemperature[2]; + uint32_t AidTemperature[2]; + uint32_t XcdTemperature[8]; + + //POWER + uint32_t SocketPowerLimit; + uint32_t SocketPower; + + //ENERGY + uint64_t Timestamp; + uint64_t SocketEnergyAcc; + uint64_t HbmEnergyAcc; + + //FREQUENCY + uint32_t GfxclkFrequencyLimit; + uint32_t FclkFrequency[2]; + uint32_t UclkFrequency[2]; + uint64_t GfxclkFrequencyAcc[8]; + uint32_t GfxclkFrequency[8]; + uint32_t SocclkFrequency[2]; + uint32_t VclkFrequency[4]; + uint32_t DclkFrequency[4]; + uint32_t LclkFrequency[2]; + + //XGMI: + uint32_t XgmiWidth; + uint32_t XgmiBitrate; + uint64_t XgmiReadBandwidthAcc; + uint64_t XgmiWriteBandwidthAcc; + + //ACTIVITY: + uint32_t SocketGfxBusy; + uint32_t DramBandwidthUtilization; + uint64_t SocketGfxBusyAcc; + uint64_t DramBandwidthAcc; + uint32_t MaxDramBandwidth; + uint64_t DramBandwidthUtilizationAcc; + uint64_t PcieBandwidthAcc[2]; + + //THROTTLERS + uint64_t ProchotResidencyAcc; + uint64_t PptResidencyAcc; + uint64_t SocketThmResidencyAcc; + uint64_t VrThmResidencyAcc; + uint64_t HbmThmResidencyAcc; + + //PCIE BW Data and error count + uint32_t PcieBandwidth[2]; + uint64_t PCIeL0ToRecoveryCountAcc; + uint64_t PCIenReplayAAcc; + uint64_t PCIenReplayARolloverCountAcc; + uint64_t PCIeNAKSentCountAcc; + uint64_t PCIeNAKReceivedCountAcc; + uint64_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated + + // VCN/JPEG ACTIVITY + uint32_t VcnBusy[4]; + uint32_t JpegBusy[40]; + + // PCIE LINK Speed and width + uint32_t PCIeLinkSpeed; + uint32_t PCIeLinkWidth; + + // PER XCD ACTIVITY + uint32_t GfxBusy[8]; + uint64_t GfxBusyAcc[8]; + + //NVML-Parity: Total App Clock Counter + uint64_t GfxclkBelowHostLimitPptAcc[8]; + uint64_t GfxclkBelowHostLimitThmAcc[8]; + uint64_t GfxclkBelowHostLimitTotalAcc[8]; + uint64_t GfxclkLowUtilizationAcc[8]; +} MetricsTable_t; + +#define SMU_SYSTEM_METRICS_TABLE_VERSION 0x1 + +#pragma pack(push, 4) +typedef struct { + uint64_t AccumulationCounter; // Last update timestamp + uint16_t LabelVersion; //Defaults to 0. + uint16_t NodeIdentifier; + int16_t SystemTemperatures[SYSTEM_TEMP_MAX_ENTRIES]; // Signed integer temperature value in Celsius, unused fields are set to 0xFFFF + int16_t NodeTemperatures[NODE_TEMP_MAX_TEMP_ENTRIES]; // Signed integer temperature value in Celsius, unused fields are set to 0xFFFF + int16_t VrTemperatures[SVI_MAX_TEMP_ENTRIES]; // Signed integer temperature value in Celsius, 13 entries, + int16_t spare[7]; + + //NPM: NODE POWER MANAGEMENT + uint32_t NodePowerLimit; + uint32_t NodePower; + uint32_t GlobalPPTResidencyAcc; + + uint16_t SystemPower[SYSTEM_POWER_MAX_ENTRIES]; // UBB Current Power and Power Threshold +} SystemMetricsTable_t; +#pragma pack(pop) + +#define SMU_VF_METRICS_TABLE_VERSION 0x5 + +typedef struct __attribute__((packed, aligned(4))) { + uint32_t AccumulationCounter; + uint32_t InstGfxclk_TargFreq; + uint64_t AccGfxclk_TargFreq; + uint64_t AccGfxRsmuDpm_Busy; + uint64_t AccGfxclkBelowHostLimit; +} VfMetricsTable_t; + +/* FRU product information */ +typedef struct __attribute__((aligned(4))) { + uint8_t ModelNumber[PRODUCT_MODEL_NUMBER_LEN]; + uint8_t Name[PRODUCT_NAME_LEN]; + uint8_t Serial[PRODUCT_SERIAL_LEN]; + uint8_t ManufacturerName[PRODUCT_MANUFACTURER_NAME_LEN]; + uint8_t FruId[PRODUCT_FRU_ID_LEN]; +} FRUProductInfo_t; + +#define SMU_STATIC_METRICS_TABLE_VERSION 0x1 + +#pragma pack(push, 4) +typedef struct { + //FRU PRODUCT INFO + FRUProductInfo_t ProductInfo; //from i2c + + //POWER + uint32_t MaxSocketPowerLimit; + + //FREQUENCY RANGE + uint32_t MaxGfxclkFrequency; + uint32_t MinGfxclkFrequency; + uint32_t MaxFclkFrequency; + uint32_t MinFclkFrequency; + uint32_t MaxGl2clkFrequency; + uint32_t MinGl2clkFrequency; + uint32_t UclkFrequencyTable[4]; + uint32_t SocclkFrequency; + uint32_t LclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + + //CTF limits + uint32_t CTFLimit_MID; + uint32_t CTFLimit_AID; + uint32_t CTFLimit_XCD; + uint32_t CTFLimit_HBM; + + //Thermal Throttling limits + uint32_t ThermalLimit_MID; + uint32_t ThermalLimit_AID; + uint32_t ThermalLimit_XCD; + uint32_t ThermalLimit_HBM; + + //PSNs + uint64_t PublicSerialNumber_MID[2]; + uint64_t PublicSerialNumber_AID[2]; + uint64_t PublicSerialNumber_XCD[8]; + + //XGMI + uint32_t MaxXgmiWidth; + uint32_t MaxXgmiBitrate; + + // Telemetry + uint32_t InputTelemetryVoltageInmV; + + // General info + uint32_t pldmVersion[2]; + + uint32_t PPT1Max; + uint32_t PPT1Min; + uint32_t PPT1Default; +} StaticMetricsTable_t; +#pragma pack(pop) + +#endif From 408b2e58a2dcb7bf9900188a7368024a58e8e44c Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 15 Mar 2026 11:53:31 +0530 Subject: [PATCH 1950/2070] drm/amd/ras: Remove redundant NULL check in pending bad-bank list iteration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ras_umc_log_pending_bad_bank() walks through a list of pending ECC bad-bank entries. These entries are saved when a bad-bank error cannot be processed immediately, for example during a GPU reset. Later, this function iterates over the pending list and retries logging each bad-bank error. If logging succeeds, the entry is removed from the list and the memory for that node is freed. The loop uses list_for_each_entry_safe(), which already guarantees that ecc_node points to a valid list entry while the loop body is executing. Checking "ecc_node &&" inside the loop is therefore unnecessary and redundant. Fixes the below: drivers/gpu/drm/amd/amdgpu/../ras/rascore/ras_umc.c:225 ras_umc_log_pending_bad_bank() warn: variable dereferenced before check 'ecc_node' (see line 223) Fixes: 7a3f9c0992c4 ("drm/amd/ras: Add umc common ras functions") Cc: Dan Carpenter Cc: YiPeng Chai Cc: Tao Zhou Cc: Hawking Zhang Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: YiPeng Chai --- drivers/gpu/drm/amd/ras/rascore/ras_umc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index 6074807ef6b70..d4072350f48fe 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -222,7 +222,7 @@ int ras_umc_log_pending_bad_bank(struct ras_core_context *ras_core) mutex_lock(&ras_umc->pending_ecc_lock); list_for_each_entry_safe(ecc_node, tmp, &ras_umc->pending_ecc_list, node){ - if (ecc_node && !ras_umc_log_bad_bank(ras_core, &ecc_node->ecc)) { + if (!ras_umc_log_bad_bank(ras_core, &ecc_node->ecc)) { list_del(&ecc_node->node); kfree(ecc_node); } From 5157a70c68723ced78d245c2c0093b227c5bb698 Mon Sep 17 00:00:00 2001 From: Yussuf Khalil Date: Fri, 6 Mar 2026 12:06:35 +0000 Subject: [PATCH 1951/2070] drm/amd/display: Do not skip unrelated mode changes in DSC validation Starting with commit 17ce8a6907f7 ("drm/amd/display: Add dsc pre-validation in atomic check"), amdgpu resets the CRTC state mode_changed flag to false when recomputing the DSC configuration results in no timing change for a particular stream. However, this is incorrect in scenarios where a change in MST/DSC configuration happens in the same KMS commit as another (unrelated) mode change. For example, the integrated panel of a laptop may be configured differently (e.g., HDR enabled/disabled) depending on whether external screens are attached. In this case, plugging in external DP-MST screens may result in the mode_changed flag being dropped incorrectly for the integrated panel if its DSC configuration did not change during precomputation in pre_validate_dsc(). At this point, however, dm_update_crtc_state() has already created new streams for CRTCs with DSC-independent mode changes. In turn, amdgpu_dm_commit_streams() will never release the old stream, resulting in a memory leak. amdgpu_dm_atomic_commit_tail() will never acquire a reference to the new stream either, which manifests as a use-after-free when the stream gets disabled later on: BUG: KASAN: use-after-free in dc_stream_release+0x25/0x90 [amdgpu] Write of size 4 at addr ffff88813d836524 by task kworker/9:9/29977 Workqueue: events drm_mode_rmfb_work_fn Call Trace: dump_stack_lvl+0x6e/0xa0 print_address_description.constprop.0+0x88/0x320 ? dc_stream_release+0x25/0x90 [amdgpu] print_report+0xfc/0x1ff ? srso_alias_return_thunk+0x5/0xfbef5 ? __virt_addr_valid+0x225/0x4e0 ? dc_stream_release+0x25/0x90 [amdgpu] kasan_report+0xe1/0x180 ? dc_stream_release+0x25/0x90 [amdgpu] kasan_check_range+0x125/0x200 dc_stream_release+0x25/0x90 [amdgpu] dc_state_destruct+0x14d/0x5c0 [amdgpu] dc_state_release.part.0+0x4e/0x130 [amdgpu] dm_atomic_destroy_state+0x3f/0x70 [amdgpu] drm_atomic_state_default_clear+0x8ee/0xf30 ? drm_mode_object_put.part.0+0xb1/0x130 __drm_atomic_state_free+0x15c/0x2d0 atomic_remove_fb+0x67e/0x980 Since there is no reliable way of figuring out whether a CRTC has unrelated mode changes pending at the time of DSC validation, remember the value of the mode_changed flag from before the point where a CRTC was marked as potentially affected by a change in DSC configuration. Reset the mode_changed flag to this earlier value instead in pre_validate_dsc(). Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5004 Fixes: 17ce8a6907f7 ("drm/amd/display: Add dsc pre-validation in atomic check") Signed-off-by: Yussuf Khalil Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6ddbd45344dc7..9cbeb1ceb21ad 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12885,6 +12885,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) if (dc_resource_is_dsc_encoding_supported(dc)) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; + } + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { ret = add_affected_mst_dsc_crtcs(state, crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index befa3eb30dece..d5c193fe4d094 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1016,6 +1016,7 @@ struct dm_crtc_state { bool freesync_vrr_info_changed; + bool mode_changed_independent_from_dsc; bool dsc_force_changed; bool vrr_supported; struct mod_freesync_config freesync_config; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 449715733903b..54eea916c1681 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2032,9 +2032,11 @@ int pre_validate_dsc(struct drm_atomic_state *state, int ind = find_crtc_index_in_state_by_stream(state, stream); if (ind >= 0) { + struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(state->crtcs[ind].new_state); + DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n", __func__, __LINE__, stream); - state->crtcs[ind].new_state->mode_changed = 0; + dm_new_crtc_state->base.mode_changed = dm_new_crtc_state->mode_changed_independent_from_dsc; } } } From 1a5cbe00d0ae8b95f64e6e7e8874bed2ee6db0fe Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 18 Mar 2026 10:15:09 +0530 Subject: [PATCH 1952/2070] drm/amdgpu: Avoid NULL dereference in discovery topology coredump path v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a GPU fault or timeout happens, the driver creates a devcoredump to collect debug information. During this, amdgpu_devcoredump_format() calls amdgpu_discovery_dump() to print IP discovery data. amdgpu_discovery_dump() uses: adev->discovery.ip_top and then accesses: ip_top->die_kset amdgpu_discovery_dump() uses adev->discovery.ip_top. However, ip_top may be NULL if the discovery topology was never initialized. The current code does not check for this before using ip_top. As a result, when ip_top is NULL, the coredump worker crashes while taking the spinlock for ip_top->die_kset. Fix this by checking for a missing ip_top before walking the discovery topology. If it is unavailable, print a short message in the dump and return safely. - If ip_top is NULL, print a message and skip the dump - Also add the same check in the cleanup path This makes the coredump and cleanup paths safe even when the discovery topology is not available. KASAN trace: [ 522.228252] [IGT] amd_deadlock: starting subtest amdgpu-deadlock-sdma [ 522.240681] [IGT] amd_deadlock: starting dynamic subtest amdgpu-deadlock-sdma ... [ 522.952317] Write of size 4 at addr 0000000000000050 by task kworker/u129:5/5434 [ 522.937526] BUG: KASAN: null-ptr-deref in _raw_spin_lock+0x66/0xc0 [ 522.967659] Workqueue: events_unbound amdgpu_devcoredump_deferred_work [amdgpu] ... [ 522.969445] Call Trace: [ 522.969508] _raw_spin_lock+0x66/0xc0 [ 522.969518] ? __pfx__raw_spin_lock+0x10/0x10 [ 522.969534] amdgpu_discovery_dump+0x61/0x530 [amdgpu] [ 522.971346] ? pick_next_task_fair+0x3f6/0x1c60 [ 522.971363] amdgpu_devcoredump_format+0x84f/0x26f0 [amdgpu] [ 522.973188] ? __pfx_amdgpu_devcoredump_format+0x10/0x10 [amdgpu] [ 522.975012] ? psi_task_switch+0x2b5/0x9b0 [ 522.975027] ? __pfx___drm_printfn_coredump+0x10/0x10 [drm] [ 522.975198] ? __pfx___drm_puts_coredump+0x10/0x10 [drm] [ 522.975366] ? __schedule+0x113c/0x38d0 [ 522.975381] amdgpu_devcoredump_deferred_work+0x4c/0x1f0 [amdgpu] v2: Updated commit message - Clarified that ip_top is not freed, it can just be NULL if discovery was not initialized. (Christian/Lijo) v3: Removed the extra drm_warn() for sysfs init failure as sysfs already reports errors. (Christian) Fixes: 7083eb8982fb ("drm/amdgpu: include ip discovery data in devcoredump") Cc: Pierre-Eric Pelloux-Prayer Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 257fb33e60e81..5ec59c5feefd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1411,6 +1411,9 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) struct list_head *el, *tmp; struct kset *die_kset; + if (!ip_top) + return; + die_kset = &ip_top->die_kset; spin_lock(&die_kset->list_lock); list_for_each_prev_safe(el, tmp, &die_kset->list) { @@ -1435,9 +1438,15 @@ void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) struct ip_hw_instance *ip_inst; int i = 0, j; + drm_printf(p, "\nHW IP Discovery\n"); + + if (!ip_top) { + drm_printf(p, "ip discovery topology unavailable\n"); + return; + } + die_kset = &ip_top->die_kset; - drm_printf(p, "\nHW IP Discovery\n"); spin_lock(&die_kset->list_lock); list_for_each(el_die, &die_kset->list) { drm_printf(p, "die %d\n", i++); From a545e81369cf9607aaed60239d3288cfb66331df Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 19 Mar 2026 11:10:10 +0530 Subject: [PATCH 1953/2070] drm/amd/ras: Add NULL checks for ras_core sys_fn callbacks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some ras core helper functions access ras_core and its callback table (sys_fn) without validating them first. Cc: Tao Zhou Cc: YiPeng Chai Cc: Dan Carpenter Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: YiPeng Chai --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 5d5d2d6430d12..29856f5ac606e 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -116,6 +116,9 @@ bool ras_core_gpu_in_reset(struct ras_core_context *ras_core) { uint32_t status = 0; + if (!ras_core) + return false; + if (ras_core->sys_fn && ras_core->sys_fn->check_gpu_status) ras_core->sys_fn->check_gpu_status(ras_core, &status); @@ -127,6 +130,9 @@ bool ras_core_gpu_is_vf(struct ras_core_context *ras_core) { uint32_t status = 0; + if (!ras_core) + return false; + if (ras_core->sys_fn && ras_core->sys_fn->check_gpu_status) ras_core->sys_fn->check_gpu_status(ras_core, &status); @@ -479,6 +485,9 @@ int ras_core_handle_fatal_error(struct ras_core_context *ras_core) uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core) { + if (!ras_core) + return 0; + if (ras_core->ras_nbio.ip_func && ras_core->ras_nbio.ip_func->get_memory_partition_mode) return ras_core->ras_nbio.ip_func->get_memory_partition_mode(ras_core); @@ -562,6 +571,8 @@ bool ras_core_ras_interrupt_detected(struct ras_core_context *ras_core) int ras_core_get_gpu_mem(struct ras_core_context *ras_core, enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) { + if (!ras_core || !gpu_mem) + return -EINVAL; if (ras_core->sys_fn && ras_core->sys_fn->get_gpu_mem) return ras_core->sys_fn->get_gpu_mem(ras_core, mem_type, gpu_mem); @@ -572,6 +583,8 @@ int ras_core_get_gpu_mem(struct ras_core_context *ras_core, int ras_core_put_gpu_mem(struct ras_core_context *ras_core, enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) { + if (!ras_core || !gpu_mem) + return -EINVAL; if (ras_core->sys_fn && ras_core->sys_fn->put_gpu_mem) return ras_core->sys_fn->put_gpu_mem(ras_core, mem_type, gpu_mem); From 0d5c25ba1327098766982e23f882fd282562c7e1 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 19 Mar 2026 11:00:00 +0530 Subject: [PATCH 1954/2070] drm/amd/ras: Add input pointer validation in ras core helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add NULL checks for helper input/output pointers that are directly dereferenced, such as tm, seqno, dev_info and init_config. Cc: Tao Zhou Cc: YiPeng Chai Cc: Dan Carpenter Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: YiPeng Chai --- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 29856f5ac606e..29b1b8f0cc263 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -69,6 +69,9 @@ int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, int seconds_per_minute = 60; int days, remaining_seconds; + if (!tm) + return -EINVAL; + days = div64_u64_rem(timestamp, seconds_per_day, &remainder); /* remainder will always be less than seconds_per_day. */ remaining_seconds = remainder; @@ -277,6 +280,9 @@ struct ras_core_context *ras_core_create(struct ras_core_config *init_config) struct ras_core_context *ras_core; struct ras_core_config *config; + if (!init_config) + return NULL; + ras_core = kzalloc(sizeof(*ras_core), GFP_KERNEL); if (!ras_core) return NULL; @@ -638,6 +644,9 @@ int ras_core_event_notify(struct ras_core_context *ras_core, int ras_core_get_device_system_info(struct ras_core_context *ras_core, struct device_system_info *dev_info) { + if (!dev_info) + return -EINVAL; + if (ras_core && ras_core->sys_fn && ras_core->sys_fn->get_device_system_info) return ras_core->sys_fn->get_device_system_info(ras_core, dev_info); From a9f3fa5f8932a8f57b58a133d5b2c82f735bf386 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 19 Mar 2026 16:27:19 +0530 Subject: [PATCH 1955/2070] drm/amdgpu: Skip discovery dump when topology is unavailable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When generating a devcoredump, amdgpu_discovery_dump() prints the IP discovery topology. The function already needs to handle the case where adev->discovery.ip_top is NULL to avoid a crash. Currently, the code prints a section header and an additional message when the topology is unavailable. However, for platforms where discovery is not used, this section is not expected to be present. Printing an extra message adds unnecessary output. Simplify this by skipping the entire section when ip_top is NULL. The NULL check is kept to avoid a crash, but no output is generated when the discovery topology is unavailable. Cc: Pierre-Eric Pelloux-Prayer Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 5ec59c5feefd6..6cc8b52afc6a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1438,15 +1438,13 @@ void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) struct ip_hw_instance *ip_inst; int i = 0, j; - drm_printf(p, "\nHW IP Discovery\n"); - - if (!ip_top) { - drm_printf(p, "ip discovery topology unavailable\n"); + if (!ip_top) return; - } die_kset = &ip_top->die_kset; + drm_printf(p, "\nHW IP Discovery\n"); + spin_lock(&die_kset->list_lock); list_for_each(el_die, &die_kset->list) { drm_printf(p, "die %d\n", i++); From 53495411bb8c3c7709246694d6109943700e32d2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 17 Mar 2026 16:34:41 -0400 Subject: [PATCH 1956/2070] drm/amdgpu/pm: drop SMU driver if version not matched messages It just leads to user confusion. Cc: Yang Wang Cc: Lijo Lazar Reviewed-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 - drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c | 1 - drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 1 - drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 ---- 4 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 56efcfa327dfd..1eec1a88e05f8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -262,7 +262,6 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(smu->adev->dev, "SMU driver if version not matched\n"); } return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c index 2c20624caca45..ac5e44dff6c97 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c @@ -101,7 +101,6 @@ int smu_v12_0_check_fw_version(struct smu_context *smu) "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(smu->adev->dev, "SMU driver if version not matched\n"); } return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index 7dc6687c3693b..9f01bed3970ee 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -284,7 +284,6 @@ int smu_v14_0_check_fw_version(struct smu_context *smu) "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(adev->dev, "SMU driver if version not matched\n"); } return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 8638d25ee839f..ce5250ecdcd51 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1061,10 +1061,6 @@ int smu_cmn_check_fw_version(struct smu_context *smu) smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && - if_version != smu->smc_driver_if_version) - dev_info(adev->dev, "SMU driver if version not matched\n"); - return 0; } From 2a7f5f17aa703e3979440bbce67126017533aa1e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 19 Feb 2026 18:18:28 -0500 Subject: [PATCH 1957/2070] drm/amdgpu/gfx10: look at the right prop for gfx queue priority MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Look at hqd_queue_priority rather than hqd_pipe_priority. In practice, it didn't matter as both were always set for kernel queues, but that will change in the future. Fixes: b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue") Reviewed-by：Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 75cbb468c8421..66d22ec27ac98 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6759,7 +6759,7 @@ static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, /* set up default queue priority level * 0x0 = low priority, 0x1 = high priority */ - if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) + if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) priority = 1; tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); From 505cb734f17e5d5a8d2140262a27b710120e599b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 19 Feb 2026 18:20:27 -0500 Subject: [PATCH 1958/2070] drm/amdgpu/gfx11: look at the right prop for gfx queue priority MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Look at hqd_queue_priority rather than hqd_pipe_priority. In practice, it didn't matter as both were always set for kernel queues, but that will change in the future. Fixes: 2e216b1e6ba2 ("drm/amdgpu/gfx11: handle priority setup for gfx pipe1") Reviewed-by：Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a57942dc1c984..0f686c7473f3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4088,7 +4088,7 @@ static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, /* set up default queue priority level * 0x0 = low priority, 0x1 = high priority */ - if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) + if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) priority = 1; tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; From 6d0d0fe5f8d87f0e5bda113a70a6ac37c8294ddc Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Tue, 17 Mar 2026 13:54:11 -0400 Subject: [PATCH 1959/2070] drm/amdgpu: fix strsep() corrupting lockup_timeout on multi-GPU (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_device_get_job_timeout_settings() passes a pointer directly to the global amdgpu_lockup_timeout[] buffer into strsep(). strsep() destructively replaces delimiter characters with '\0' in-place. On multi-GPU systems, this function is called once per device. When a multi-value setting like "0,0,0,-1" is used, the first GPU's call transforms the global buffer into "0\00\00\0-1". The second GPU then sees only "0" (terminated at the first '\0'), parses a single value, hits the single-value fallthrough (index == 1), and applies timeout=0 to all rings — causing immediate false job timeouts. Fix this by copying into a stack-local array before calling strsep(), so the global module parameter buffer remains intact across calls. The buffer is AMDGPU_MAX_TIMEOUT_PARAM_LENGTH (256) bytes, which is safe for the stack. v2: wrap commit message to 72 columns, add Assisted-by tag. v3: use stack array with strscpy() instead of kstrdup()/kfree() to avoid unnecessary heap allocation (Christian). This patch was developed with assistance from Claude (claude-opus-4-6). Reviewed-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Ruijing Dong --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2f018f1c71952..b0aac25278003 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3528,7 +3528,8 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) { - char *input = amdgpu_lockup_timeout; + char buf[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; + char *input = buf; char *timeout_setting = NULL; int index = 0; long timeout; @@ -3538,9 +3539,17 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) adev->gfx_timeout = adev->compute_timeout = adev->sdma_timeout = adev->video_timeout = msecs_to_jiffies(2000); - if (!strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) + if (!strnlen(amdgpu_lockup_timeout, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) return 0; + /* + * strsep() destructively modifies its input by replacing delimiters + * with '\0'. Use a stack copy so the global module parameter buffer + * remains intact for multi-GPU systems where this function is called + * once per device. + */ + strscpy(buf, amdgpu_lockup_timeout, sizeof(buf)); + while ((timeout_setting = strsep(&input, ",")) && strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { ret = kstrtol(timeout_setting, 0, &timeout); From 4e28d337df257756a3d08f7abb998d6ab7d8f407 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Mon, 16 Mar 2026 11:01:30 -0400 Subject: [PATCH 1960/2070] drm/amdgpu: prevent immediate PASID reuse case MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PASID resue could cause interrupt issue when process immediately runs into hw state left by previous process exited with the same PASID, it's possible that page faults are still pending in the IH ring buffer when the process exits and frees up its PASID. To prevent the case, it uses idr cyclic allocator same as kernel pid's. Signed-off-by: Eric Huang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 45 ++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 + 3 files changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 9cab36322c165..644e413a4e692 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -35,10 +35,13 @@ * PASIDs are global address space identifiers that can be shared * between the GPU, an IOMMU and the driver. VMs on different devices * may use the same PASID if they share the same address - * space. Therefore PASIDs are allocated using a global IDA. VMs are - * looked up from the PASID per amdgpu_device. + * space. Therefore PASIDs are allocated using IDR cyclic allocator + * (similar to kernel PID allocation) which naturally delays reuse. + * VMs are looked up from the PASID per amdgpu_device. */ -static DEFINE_IDA(amdgpu_pasid_ida); + +static DEFINE_IDR(amdgpu_pasid_idr); +static DEFINE_SPINLOCK(amdgpu_pasid_idr_lock); /* Helper to free pasid from a fence callback */ struct amdgpu_pasid_cb { @@ -50,8 +53,8 @@ struct amdgpu_pasid_cb { * amdgpu_pasid_alloc - Allocate a PASID * @bits: Maximum width of the PASID in bits, must be at least 1 * - * Allocates a PASID of the given width while keeping smaller PASIDs - * available if possible. + * Uses kernel's IDR cyclic allocator (same as PID allocation). + * Allocates sequentially with automatic wrap-around. * * Returns a positive integer on success. Returns %-EINVAL if bits==0. * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on @@ -59,14 +62,15 @@ struct amdgpu_pasid_cb { */ int amdgpu_pasid_alloc(unsigned int bits) { - int pasid = -EINVAL; + int pasid; - for (bits = min(bits, 31U); bits > 0; bits--) { - pasid = ida_alloc_range(&amdgpu_pasid_ida, 1U << (bits - 1), - (1U << bits) - 1, GFP_KERNEL); - if (pasid != -ENOSPC) - break; - } + if (bits == 0) + return -EINVAL; + + spin_lock(&amdgpu_pasid_idr_lock); + pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1, + 1U << bits, GFP_KERNEL); + spin_unlock(&amdgpu_pasid_idr_lock); if (pasid >= 0) trace_amdgpu_pasid_allocated(pasid); @@ -81,7 +85,10 @@ int amdgpu_pasid_alloc(unsigned int bits) void amdgpu_pasid_free(u32 pasid) { trace_amdgpu_pasid_freed(pasid); - ida_free(&amdgpu_pasid_ida, pasid); + + spin_lock(&amdgpu_pasid_idr_lock); + idr_remove(&amdgpu_pasid_idr, pasid); + spin_unlock(&amdgpu_pasid_idr_lock); } static void amdgpu_pasid_free_cb(struct dma_fence *fence, @@ -616,3 +623,15 @@ void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev) } } } + +/** + * amdgpu_pasid_mgr_cleanup - cleanup PASID manager + * + * Cleanup the IDR allocator. + */ +void amdgpu_pasid_mgr_cleanup(void) +{ + spin_lock(&amdgpu_pasid_idr_lock); + idr_destroy(&amdgpu_pasid_idr); + spin_unlock(&amdgpu_pasid_idr_lock); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h index b3649cd3af569..a57919478d3bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h @@ -74,6 +74,7 @@ int amdgpu_pasid_alloc(unsigned int bits); void amdgpu_pasid_free(u32 pasid); void amdgpu_pasid_free_delayed(struct dma_resv *resv, u32 pasid); +void amdgpu_pasid_mgr_cleanup(void); bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, struct amdgpu_vmid *id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ef79044bdd0af..622f7033bbd28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2962,6 +2962,7 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) #endif amdgpu_vmid_mgr_fini(adev); + amdgpu_pasid_mgr_cleanup(); } /** From c20431ea1aa1c8e50df1b793b73c45c24259306b Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Thu, 22 Jan 2026 11:33:10 -0500 Subject: [PATCH 1961/2070] drm/amd/display: Update dpia supported configuration [Why & How] Init a flag to track if dpia enabled previously and update that to boot options. Reviewed-by: Ovidiu Bunea Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c index 4d274b7034e89..7833a4fb7fbfe 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c @@ -39,13 +39,14 @@ void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) { union dmub_fw_boot_options boot_options = {0}; - union dmub_fw_boot_options cur_boot_options = {0}; - cur_boot_options = dmub_dcn42_get_fw_boot_option(dmub); + if (!dmub->dpia_supported) { + dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia; + } boot_options.bits.z10_disable = params->disable_z10; boot_options.bits.dpia_supported = params->dpia_supported; - boot_options.bits.enable_dpia = cur_boot_options.bits.enable_dpia && !params->disable_dpia; + boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia; boot_options.bits.usb4_cm_version = params->usb4_cm_version; boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; boot_options.bits.power_optimization = params->power_optimization; From 3831b9328c9fc6d33ddf76c0c83c56d786899d76 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 2 Mar 2026 15:45:41 -0500 Subject: [PATCH 1962/2070] drm/amd/display: dcn42 don't round up disclk and dppclk [why] dml2 based on num_enabled clock != 2 to do clock ramming to dpm. apu has 8 levels dispclk/dppclk/dcfclk/fclk, but only 4 levels of memclk. to avoid mapping dispclk/dppclk to DPM clock, based on arch review, force dispclk/dppclk num_level as 2. Reviewed-by: Dillon Varone Signed-off-by: Charlene Liu Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../dcn42/dcn42_soc_and_ip_translator.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c index fd9c24b5df535..1c04171b296c2 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -93,6 +93,10 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( } } vmin_limit->dispclk_khz = min(dc_clk_table->entries[0].dispclk_mhz * 1000, vmin_limit->dispclk_khz); + /* dispclk is always fine-grain */ + dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels >= 2 ? 2 : 1; + dml_clk_table->dispclk.clk_values_khz[0] = 0; + dml_clk_table->dispclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk.num_dispclk_levels - 1].dispclk_mhz * 1000; } /* dppclk */ @@ -105,6 +109,10 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( dml_clk_table->dppclk.clk_values_khz[i] = 0; } } + /* dppclk is always fine-grain */ + dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels >= 2 ? 2 : 1; + dml_clk_table->dppclk.clk_values_khz[0] = 0; + dml_clk_table->dppclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk.num_dppclk_levels - 1].dppclk_mhz * 1000; } /* dtbclk */ From 931ad458656c4b537b4e6f59c17f1093e19061fe Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Mon, 2 Mar 2026 15:02:33 -0500 Subject: [PATCH 1963/2070] drm/amd/display: Add MRQ programming for DCN42 [Why] DCN401 didn't have a MRQ present so these fields didn't exist. They are still present on DCN42 so we need to continue programming them like we did on DCN35 or we can block have poor meta requesting efficiency which blocks p-state. [How] Add `hubp42_program_requestor` which takes DML21 input and programs the registers like DCN35 and prior. Reviewed-by: Leo Chen Signed-off-by: Nicholas Kazlauskas Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../amd/display/dc/hubp/dcn42/dcn42_hubp.c | 35 ++++++++++++++++++- .../amd/display/dc/hubp/dcn42/dcn42_hubp.h | 6 ++++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c index 0e33c739f459f..d85a4ab957a40 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -245,6 +245,39 @@ static void hubp42_program_deadline( REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata); } +void hubp42_program_requestor( + struct hubp *hubp, + struct dml2_display_rq_regs *rq_regs) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBPRET_CONTROL, + DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); + REG_SET_4(DCN_EXPANSION_MODE, 0, + DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, + PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, + MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, + CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); + REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, + CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, + MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, + META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, + MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, + DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, + VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, + SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, + PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); + REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, + CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, + MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, + META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, + MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, + DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, + SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, + PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); +} + + void hubp42_setup( struct hubp *hubp, struct dml2_dchub_per_pipe_register_set *pipe_regs, @@ -255,7 +288,7 @@ void hubp42_setup( * disable the requestors is not needed */ hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing); - hubp401_program_requestor(hubp, &pipe_regs->rq_regs); + hubp42_program_requestor(hubp, &pipe_regs->rq_regs); hubp42_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); } static void hubp42_program_surface_config( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h index 486c8907413aa..88bb1337ab9d6 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h @@ -48,6 +48,8 @@ HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW, HUBP_3DLUT_ADDRESS_LOW, mask_sh),\ HUBP_SF(CURSOR0_0_HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, mask_sh) +struct dml2_display_rq_regs; + bool hubp42_construct( struct dcn20_hubp *hubp2, struct dc_context *ctx, @@ -64,6 +66,10 @@ void hubp42_program_3dlut_fl_config(struct hubp *hubp, void hubp42_read_state(struct hubp *hubp); +void hubp42_program_requestor( + struct hubp *hubp, + struct dml2_display_rq_regs *rq_regs); + void hubp42_setup( struct hubp *hubp, struct dml2_dchub_per_pipe_register_set *pipe_regs, From 4a3268afed9e1bda3f9beeb9782bd748598c1c19 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Tue, 3 Mar 2026 20:07:58 -0500 Subject: [PATCH 1964/2070] drm/amd/display: Move DPM clk read to clk_mgr_construct in DCN42 [Why&How] The DPM clocks on DCN42 are currently read on every dm_resume, which can cause in gpu memory freeing while the device is still in suspend. Move the DPM clock read functionality to clk_mgr_construct() so it completes once on driver enablement. Reviewed-by: Charlene Liu Signed-off-by: Ivan Lipski Signed-off-by: Dmytro Laktyushkin Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 250 +++++++++--------- 1 file changed, 126 insertions(+), 124 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 97c9f0ce13e40..df904b6fafe98 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -569,7 +569,6 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); - struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 }; DC_LOGGER_INIT(clk_mgr_base->ctx->logger); (void)dc_logger; @@ -591,127 +590,6 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) /*dtbclk enabled based on*/ clk_mgr_base->clks.dtbclk_en = true; } - - if (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels != 0) { - /*skip to get clock table and notify pmfw watermark range again*/ - DC_LOG_SMU("skip to get dpm_clks from pmfw from resume and acr\n"); - return; - } - - smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem( - clk_mgr_base->ctx, - DC_MEM_ALLOC_TYPE_GART, - sizeof(DpmClocks_t_dcn42), - &smu_dpm_clks.mc_address.quad_part); - - ASSERT(smu_dpm_clks.dpm_clks); - if (clk_mgr_base->ctx->dc->debug.pstate_enabled && clk_mgr_int->smu_present && smu_dpm_clks.mc_address.quad_part != 0) { - int i; - DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks; - - dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks); - DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" - "NumDispClkLevelsEnabled: %d\n" - "NumSocClkLevelsEnabled: %d\n" - "VcnClkLevelsEnabled: %d\n" - "FClkLevelsEnabled: %d\n" - "NumMemPstatesEnabled: %d\n" - "MinGfxClk: %d\n" - "MaxGfxClk: %d\n", - dpm_clks->NumDcfClkLevelsEnabled, - dpm_clks->NumDispClkLevelsEnabled, - dpm_clks->NumSocClkLevelsEnabled, - dpm_clks->VcnClkLevelsEnabled, - dpm_clks->NumFclkLevelsEnabled, - dpm_clks->NumMemPstatesEnabled, - dpm_clks->MinGfxClk, - dpm_clks->MaxGfxClk); - - for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { - DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n", - i, - dpm_clks->DcfClocks[i]); - } - for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) { - DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n", - i, dpm_clks->DispClocks[i]); - } - for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { - DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n", - i, dpm_clks->SocClocks[i]); - } - for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { - DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n", - i, dpm_clks->FclkClocks_Freq[i]); - DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n", - i, dpm_clks->FclkClocks_Voltage[i]); - } - for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) - DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n", - i, dpm_clks->SocVoltage[i]); - - for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) { - DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d\n" - "dpm_clks->MemPstateTable[%d].MemClk= %d\n" - "dpm_clks->MemPstateTable[%d].Voltage = %d\n", - i, dpm_clks->MemPstateTable[i].UClk, - i, dpm_clks->MemPstateTable[i].MemClk, - i, dpm_clks->MemPstateTable[i].Voltage); - } - - if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) { - /* DCFCLK */ - dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, - dpm_clks->DcfClocks, - dpm_clks->NumDcfClkLevelsEnabled); - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled; - - /* SOCCLK */ - dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, - dpm_clks->SocClocks, - dpm_clks->NumSocClkLevelsEnabled); - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled; - - /* DISPCLK */ - dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, - dpm_clks->DispClocks, - dpm_clks->NumDispClkLevelsEnabled); - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled; - - /* DPPCLK */ - dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, - dpm_clks->DppClocks, - dpm_clks->NumDispClkLevelsEnabled); - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled; - - /* FCLK */ - dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, - dpm_clks->FclkClocks_Freq, - NUM_FCLK_DPM_LEVELS); - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled; - clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled; - - /* Memory Pstate table is in reverse order*/ - ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS); - if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) - dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS; - for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) { - clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].UClk; - clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ; - } - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; - - /* DTBCLK*/ - clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; - clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; - /* Refresh bounding box */ - clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( - clk_mgr_base->ctx->dc, clk_mgr_base->bw_params); - } - } - if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) - dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART, - smu_dpm_clks.dpm_clks); } static struct clk_bw_params dcn42_bw_params = { @@ -1071,6 +949,127 @@ bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base) return clk_mgr->smu_present; } +static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int) +{ + struct clk_mgr *clk_mgr_base = &clk_mgr_int->base; + struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 }; + + DC_LOGGER_INIT(clk_mgr_base->ctx->logger); + (void)dc_logger; + + smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem( + clk_mgr_base->ctx, + DC_MEM_ALLOC_TYPE_GART, + sizeof(DpmClocks_t_dcn42), + &smu_dpm_clks.mc_address.quad_part); + + ASSERT(smu_dpm_clks.dpm_clks); + if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) { + int i; + DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks; + + dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks); + DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" + "NumDispClkLevelsEnabled: %d\n" + "NumSocClkLevelsEnabled: %d\n" + "VcnClkLevelsEnabled: %d\n" + "FClkLevelsEnabled: %d\n" + "NumMemPstatesEnabled: %d\n" + "MinGfxClk: %d\n" + "MaxGfxClk: %d\n", + dpm_clks->NumDcfClkLevelsEnabled, + dpm_clks->NumDispClkLevelsEnabled, + dpm_clks->NumSocClkLevelsEnabled, + dpm_clks->VcnClkLevelsEnabled, + dpm_clks->NumFclkLevelsEnabled, + dpm_clks->NumMemPstatesEnabled, + dpm_clks->MinGfxClk, + dpm_clks->MaxGfxClk); + + for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n", + i, + dpm_clks->DcfClocks[i]); + } + for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n", + i, dpm_clks->DispClocks[i]); + } + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n", + i, dpm_clks->SocClocks[i]); + } + for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n", + i, dpm_clks->FclkClocks_Freq[i]); + DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n", + i, dpm_clks->FclkClocks_Voltage[i]); + } + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) + DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n", + i, dpm_clks->SocVoltage[i]); + + for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) { + DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d\n" + "dpm_clks->MemPstateTable[%d].MemClk= %d\n" + "dpm_clks->MemPstateTable[%d].Voltage = %d\n", + i, dpm_clks->MemPstateTable[i].UClk, + i, dpm_clks->MemPstateTable[i].MemClk, + i, dpm_clks->MemPstateTable[i].Voltage); + } + + if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) { + /* DCFCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, + dpm_clks->DcfClocks, + dpm_clks->NumDcfClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled; + + /* SOCCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, + dpm_clks->SocClocks, + dpm_clks->NumSocClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled; + + /* DISPCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, + dpm_clks->DispClocks, + dpm_clks->NumDispClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled; + + /* DPPCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, + dpm_clks->DppClocks, + dpm_clks->NumDispClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled; + + /* FCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, + dpm_clks->FclkClocks_Freq, + NUM_FCLK_DPM_LEVELS); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled; + clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled; + + /* Memory Pstate table is in reverse order*/ + ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS); + if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) + dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS; + for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) { + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].UClk; + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ; + } + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; + + /* DTBCLK*/ + clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; + } + } + if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART, + smu_dpm_clks.dpm_clks); +} + static struct clk_mgr_funcs dcn42_funcs = { .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, @@ -1139,6 +1138,11 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); } /* in case we don't get a value from the BIOS, use default */ if (clk_mgr->base.base.dentist_vco_freq_khz == 0) @@ -1151,8 +1155,6 @@ void dcn42_clk_mgr_construct( /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ dcn42_read_ss_info_from_lut(&clk_mgr->base); - - clk_mgr->base.base.bw_params = &dcn42_bw_params; } void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) From 56337c3976052f60d16092c1510f42f00d41f00d Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 5 Mar 2026 10:14:39 -0500 Subject: [PATCH 1965/2070] drm/amd/display: System Hang When System enters to S0i3 w/ iGPU [why] System Hang when system enters to S0i3 w/ iGPU some link_enc are NULL due to BIOS integration info table not correct, but driver should have enough null pointer protection. Reviewed-by: Leo Chen Signed-off-by: Charlene Liu Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index 8e12dc1297c4d..7bf94eae30a6f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -203,7 +203,8 @@ void dcn42_init_hw(struct dc *dc) for (i = 0; i < dc->link_count; i++) { struct dc_link *link = dc->links[i]; - if (link->link_enc->funcs->is_dig_enabled && + if (link && link->link_enc && + link->link_enc->funcs->is_dig_enabled && link->link_enc->funcs->is_dig_enabled(link->link_enc) && hws->funcs.power_down) { hws->funcs.power_down(dc); From 1a40a80f7138e621f4020ce39faa93a624128edd Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Thu, 5 Mar 2026 14:47:03 -0500 Subject: [PATCH 1966/2070] drm/amd/display: move dcn42 bw_params init Move it out of smu present block for cases where it isn't Reviewed-by: Ivan Lipski Signed-off-by: Dmytro Laktyushkin Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index df904b6fafe98..a0296d5f0102f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -1138,11 +1138,6 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); - - clk_mgr->base.base.bw_params = &dcn42_bw_params; - - if (clk_mgr->base.smu_present) - dcn42_get_smu_clocks(&clk_mgr->base); } /* in case we don't get a value from the BIOS, use default */ if (clk_mgr->base.base.dentist_vco_freq_khz == 0) @@ -1155,6 +1150,10 @@ void dcn42_clk_mgr_construct( /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ dcn42_read_ss_info_from_lut(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); } void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) From 142739263cb69f6280844d60d0a1f3df9be20e5e Mon Sep 17 00:00:00 2001 From: Roman Li Date: Fri, 13 Mar 2026 19:34:02 -0400 Subject: [PATCH 1967/2070] drm/amd/display: Add get_default_tiling_info for dcn42 Add DCN42 portion that was stripped during previously. Fixes: 28fb6e900b3b ("drm/amd/display: Query DC for gfx handling when setting linear tiling") Reviewed-by: Alex Hung Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index aef187bcf5c34..7b451c7db02c6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -1792,6 +1792,7 @@ static struct resource_funcs dcn42_res_pool_funcs = { .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static uint32_t read_pipe_fuses(struct dc_context *ctx) From 10a5757546871d6e74175228f30b10080ecf4b92 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Fri, 13 Mar 2026 20:27:54 -0400 Subject: [PATCH 1968/2070] drm/amd/display: Add missing dcn42 hubbub function pointers This aligning commit combines: - fix dcn42 det programming) - fix missing dcn42 pointers - fix SDPIF_Request_Rate_Limit programming value V2: Add back dchvm_init for DCN42 Reviewed-by: Alex Hung Reviewed-by: Leo Chen Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../display/dc/hubbub/dcn42/dcn42_hubbub.c | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c index d6e6fbaa041b3..9e4d526b6d523 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -6,6 +6,7 @@ #include "dcn31/dcn31_hubbub.h" #include "dcn32/dcn32_hubbub.h" #include "dcn35/dcn35_hubbub.h" +#include "dcn401/dcn401_hubbub.h" #include "dcn42/dcn42_hubbub.h" #include "dm_services.h" #include "reg_helper.h" @@ -494,6 +495,14 @@ static bool hubbub42_program_watermarks( return wm_pending; } +static void hubbub42_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t request_limit = 96; //MAX(12 * memory_channel_count, 96); + + REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit); +} + static const struct hubbub_funcs hubbub42_funcs = { .update_dchub = hubbub2_update_dchub, .init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx, @@ -509,13 +518,16 @@ static const struct hubbub_funcs hubbub42_funcs = { .force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes, .force_pstate_change_control = hubbub3_force_pstate_change_control, .init_watermarks = hubbub35_init_watermarks, - .program_det_size = dcn32_program_det_size, - .program_compbuf_size = dcn35_program_compbuf_size, - .init_crb = dcn35_init_crb, + .init_crb = dcn401_init_crb, + .dchvm_init = dcn35_dchvm_init, .hubbub_read_state = hubbub2_read_state, .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, - .dchubbub_init = hubbub35_init, - .dchvm_init = dcn35_dchvm_init, + .set_request_limit = hubbub42_set_request_limit, + .program_det_segments = dcn401_program_det_segments, + .program_compbuf_segments = dcn401_program_compbuf_segments, + .wait_for_det_update = dcn401_wait_for_det_update, + .program_arbiter = dcn401_program_arbiter, + .hubbub_read_reg_state = hubbub3_read_reg_state }; void hubbub42_construct(struct dcn20_hubbub *hubbub2, From 74e31fbe749043859dedcbf0be3a11590fc6a5f8 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Mon, 2 Mar 2026 10:47:34 -0500 Subject: [PATCH 1969/2070] drm/amd/display: Split arbiter programming for DCN42 [Why] We don't want to update the timeout threshold for stall recovery in firmware dynamically for DCN42 as we're not using FAMS. Firmware should own programming of this register since the recovery can be broken if driver updates the value to 0. [How] Split program_arbiter for dcn42 and skip the part that updates the timeout threshold. Reviewed-by: Leo Chen Signed-off-by: Nicholas Kazlauskas Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../display/dc/hubbub/dcn42/dcn42_hubbub.c | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c index 9e4d526b6d523..8582dcab1f225 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -503,6 +503,38 @@ static void hubbub42_set_request_limit(struct hubbub *hubbub, int memory_channel REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit); } +static bool dcn42_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + bool wm_pending = false; + uint32_t temp; + + /* request backpressure and outstanding return threshold (unused)*/ + //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); + + /* 401 delta: do not update P-State stall threshold (handled by fw) */ + // REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); + + if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + + /* only update the required bits */ + REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); + if (hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + temp |= (1 << 5); + } else { + temp &= ~(1 << 5); + } + REG_UPDATE(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, temp); + } else { + wm_pending = true; + } + + return wm_pending; +} + static const struct hubbub_funcs hubbub42_funcs = { .update_dchub = hubbub2_update_dchub, .init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx, @@ -526,7 +558,7 @@ static const struct hubbub_funcs hubbub42_funcs = { .program_det_segments = dcn401_program_det_segments, .program_compbuf_segments = dcn401_program_compbuf_segments, .wait_for_det_update = dcn401_wait_for_det_update, - .program_arbiter = dcn401_program_arbiter, + .program_arbiter = dcn42_program_arbiter, .hubbub_read_reg_state = hubbub3_read_reg_state }; From cf734ecadee0fa0e73ef603ae4543f322859e7ea Mon Sep 17 00:00:00 2001 From: Roman Li Date: Fri, 13 Mar 2026 20:34:48 -0400 Subject: [PATCH 1970/2070] drm/amd/display: Clamp min DS DCFCLK value to DCN limit [why & how] DCN has a global limit for minimum DS DCFCLK during any operation. Adhere to that limit and add a debug flag. Reviewed-by: Charlene Liu Signed-off-by: Ovidiu Bunea Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 1 + 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index a0296d5f0102f..bc11510b63a1a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -291,6 +291,11 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + + /* Clamp the requested clock to PMFW based on DCN limit. */ + if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && clk_mgr_base->clks.dcfclk_deep_sleep_khz < dc->debug.min_deep_sleep_dcfclk_khz) + clk_mgr_base->clks.dcfclk_deep_sleep_khz = dc->debug.min_deep_sleep_dcfclk_khz; + dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2344f184ce079..17b77868e4a0f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1218,6 +1218,7 @@ struct dc_debug_options { bool enable_dmu_recovery; unsigned int force_vmin_threshold; bool enable_otg_frame_sync_pwa; + unsigned int min_deep_sleep_dcfclk_khz; }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 7b451c7db02c6..8175109a66b0f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -760,6 +760,7 @@ static const struct dc_debug_options debug_defaults_drv = { .disable_z10 = false, .ignore_pg = true, .disable_stutter_for_wm_program = true, + .min_deep_sleep_dcfclk_khz = 8000, }; static const struct dc_check_config config_defaults = { From 62e7522c85fa1da373fae5df3d55d708a193c3d5 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 16 Mar 2026 20:17:57 -0400 Subject: [PATCH 1971/2070] drm/amd/display: Update underflow detection for DCN42 [Why] The DCN42 underflow detection functions in dcn42_optc.c use OPTC_RSMU_UNDERFLOW register but the register offset definitions were missing from dcn_4_2_0_offset.h and dcn42_resource.h. [How] Add missing register definitions. Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373") Reviewed-by: Alex Hung Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h index a9b26df14520a..8e7a09402de5c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h @@ -481,6 +481,8 @@ SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \ SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \ SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst), \ + SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst), \ SRI_ARR(CONTROL, VTG, inst), \ SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \ SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h index 52fbf2dc18995..3755a984681a5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h @@ -9036,6 +9036,8 @@ // base address: 0x40 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_RSMU_UNDERFLOW 0x1adb +#define regODM1_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 #define regODM1_OPTC_UNDERFLOW_THRESHOLD 0x1adc #define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 #define regODM1_OPTC_DATA_SOURCE_SELECT 0x1add @@ -9060,6 +9062,8 @@ // base address: 0x80 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_RSMU_UNDERFLOW 0x1aeb +#define regODM2_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 #define regODM2_OPTC_UNDERFLOW_THRESHOLD 0x1aec #define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 #define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aed @@ -9084,6 +9088,8 @@ // base address: 0xc0 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_RSMU_UNDERFLOW 0x1afb +#define regODM3_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 #define regODM3_OPTC_UNDERFLOW_THRESHOLD 0x1afc #define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 #define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afd From 5acc532cc9a37516bbfcec5dfff49a354d33aeb0 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 5 Mar 2026 20:23:25 -0500 Subject: [PATCH 1972/2070] drm/amd/display: Add Extra SMU Log for dtbclk [why] need to check dtbclk in log for confirmation Reviewed-by: Gabe Teeger Signed-off-by: Charlene Liu Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index bc11510b63a1a..7134d8998efc2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -474,6 +474,9 @@ static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", internal.CLK8_CLK1_CURRENT_CNT); + DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk\n", + internal.CLK8_CLK4_CURRENT_CNT); + DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", internal.CLK8_CLK3_BYPASS_CNTL); From a92bf41ee14d291f26f91ff01e82f3e91051b6ab Mon Sep 17 00:00:00 2001 From: Alexander Chechik Date: Mon, 9 Mar 2026 13:15:24 -0400 Subject: [PATCH 1973/2070] drm/amd/display: Fix DCN42 memory clock table using MemClk instead of UClk [Why] DCN42 was using UClk values instead of MemClk from MemPstateTable, causing DML to see half the actual DRAM bandwidth on DDR5 systems and reject high refresh rate modes. [How] Change dcn42_init_clocks() to use MemPstateTable[i].MemClk instead of MemPstateTable[i].UClk for memclk_mhz initialization. Reviewed-by: Charlene Liu Signed-off-by: Alexander Chechik Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 7134d8998efc2..24834f89711df 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -1063,7 +1063,7 @@ static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int) if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS; for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) { - clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].UClk; + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].MemClk; clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ; } clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; From 1fd0348092577dc0542ec2336fa0c01760541a96 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Tue, 10 Mar 2026 13:33:55 -0400 Subject: [PATCH 1974/2070] drm/amd/display: remove disable_sutter touch pstate debug code [why] diags is using disable_stutter, this will cause issue when pstate switch enabled Reviewed-by: Ilya Bakoulin Signed-off-by: Charlene Liu Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c index 8582dcab1f225..a436fa71d4b43 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -430,15 +430,6 @@ static void hubbub42_allow_self_refresh_control(struct hubbub *hubbub, bool allo REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow); - - if (!allow && hubbub->ctx->dc->debug.disable_stutter) {/*controlled by registry key*/ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE, 1); - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); - } } static void hubbub42_set_sdp_control(struct hubbub *hubbub, bool dc_control) { From 2f1c70aea577ad1a2d7ed7521d4fbec8fb533ca4 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Tue, 10 Mar 2026 10:53:08 -0400 Subject: [PATCH 1975/2070] drm/amd/display: pg cntl update based on previous asic. [why] switch to well tested sequence. Reviewed-by: Leo Chen Signed-off-by: Charlene Liu Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c index 3685080ce9dc4..96290538a889d 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c @@ -176,11 +176,12 @@ void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dp uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl; bool block_enabled; + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hubp_power_gate || + pg_cntl->ctx->dc->debug.disable_dpp_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_hubp_power_gate || - pg_cntl->ctx->dc->debug.disable_dpp_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) + if (skip_pg && !power_on) return; block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); From 96ea595d28243b0470660f081e3f5febd2fc5bfc Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 6 Mar 2026 10:40:07 -0500 Subject: [PATCH 1976/2070] drm/amd/display: export get_power_profile interface for later use [why] export dcn401 get_power_profile for later asic. Reviewed-by: Roman Li Signed-off-by: Charlene Liu Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 1 + drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 1 + drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 57ae4b216b5d2..7ac2f38bfde8d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1794,7 +1794,7 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) } } -static int dcn401_get_power_profile(const struct dc_state *context) +int dcn401_get_power_profile(const struct dc_state *context) { int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; int dpm_level = 0; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 5f3b0319cb5bb..47f82b8182627 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -32,6 +32,7 @@ void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info); unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); +int dcn401_get_power_profile(const struct dc_state *context); /* Following are definitions for run time init of reg offsets */ /* HUBP */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 8175109a66b0f..fa5d0558192cf 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -1791,6 +1791,7 @@ static struct resource_funcs dcn42_res_pool_funcs = { .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .prepare_mcache_programming = dcn42_prepare_mcache_programming, .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, + .get_power_profile = dcn401_get_power_profile, .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, .get_default_tiling_info = dcn10_get_default_tiling_info diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h index 8e7a09402de5c..60acf0e423d97 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h @@ -586,5 +586,6 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc, enum dc_validate_mode validate_mode); void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context); +int dcn42_get_power_profile(const struct dc_state *context); #endif /* _DCN42_RESOURCE_H_ */ From 38293ff6774d38f363aeecda5513592b1e1f9321 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Sat, 7 Mar 2026 18:57:57 -0500 Subject: [PATCH 1977/2070] drm/amd/display: Fix Silence warnings Also affects: freesync, hdcp, info_packet, power [Why] Resolve compiler warnings by marking unused parameters explicitly. [How] In .c/.h keep parameter names in signatures and add a line with `(void)param;` inside the function body Preserved function signatures and avoids breaking code paths that may reference the parameter under conditional compilation. Reviewed-by: Aric Cyr Signed-off-by: Gaghik Khachatrian Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 ++ drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 ++++++ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h | 1 + 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index a71df052cf252..0f9e8a11df0d9 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -896,6 +896,7 @@ static void build_de_pq(struct pwl_float_data_ex *de_pq, uint32_t hw_points_num, const struct hw_x_point *coordinate_x) { + (void)coordinate_x; uint32_t i; struct fixed31_32 output; struct fixed31_32 *de_pq_table = mod_color_get_table(type_de_pq_table); @@ -1339,6 +1340,7 @@ static void scale_gamma_dx(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) { + (void)dividers; uint32_t i; struct fixed31_32 min = dc_fixpt_zero; struct fixed31_32 max = dc_fixpt_one; diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 1aae46d703ba0..b7e03dda700c8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -114,6 +114,7 @@ static unsigned int calc_duration_in_us_from_v_total( const struct mod_vrr_params *in_vrr, unsigned int v_total) { + (void)in_vrr; unsigned int duration_in_us = (unsigned int)(div64_u64(((unsigned long long)(v_total) * 10000) * stream->timing.h_total, @@ -218,6 +219,7 @@ static void update_v_total_for_static_ramp( const struct dc_stream_state *stream, struct mod_vrr_params *in_out_vrr) { + (void)core_freesync; unsigned int v_total = 0; unsigned int current_duration_in_us = calc_duration_in_us_from_v_total( @@ -292,6 +294,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, unsigned int last_render_time_in_us, struct mod_vrr_params *in_out_vrr) { + (void)core_freesync; unsigned int inserted_frame_duration_in_us = 0; unsigned int mid_point_frames_ceil = 0; unsigned int mid_point_frames_floor = 0; @@ -447,6 +450,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, unsigned int last_render_time_in_us, struct mod_vrr_params *in_out_vrr) { + (void)core_freesync; bool update = false; unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us; @@ -545,6 +549,7 @@ static bool vrr_settings_require_update(struct core_freesync *core_freesync, unsigned int max_refresh_in_uhz, struct mod_vrr_params *in_vrr) { + (void)core_freesync; if (in_vrr->state != in_config->state) { return true; } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED && @@ -946,6 +951,7 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, struct dc_info_packet *infopacket, bool pack_sdp_v1_3) { + (void)mod_freesync; /* SPD info packet for FreeSync * VTEM info packet for HdmiVRR * Check if Freesync is supported. Return if false. If true, diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h index 26a351a184f33..d07387a961dd9 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h @@ -501,6 +501,7 @@ static inline void callback_in_ms(uint16_t time, struct mod_hdcp_output *output) static inline void set_watchdog_in_ms(struct mod_hdcp *hdcp, uint16_t time, struct mod_hdcp_output *output) { + (void)hdcp; output->watchdog_timer_needed = 1; output->watchdog_timer_delay = time; } From 982b0e2c947c39b395c9ce5e73feb2da8bd1c105 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Sat, 7 Mar 2026 05:53:03 +0000 Subject: [PATCH 1978/2070] drm/amd/display: Add 3DLUT DMA broadcast support [WHY&HOW] A single HUBP can be used to fetch 3DLUT and broadcast to a single HUBP. Add logic to select the top pipe for a given plane and use it's HUBP as the broadcast source for multiple MPC's. Reviewed-by: Ilya Bakoulin Signed-off-by: Dillon Varone Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 108 +++++++++++------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 3 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 2 +- 4 files changed, 67 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3d56d3e8c3e82..d6673c724cecb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4501,7 +4501,7 @@ static void commit_planes_for_stream(struct dc *dc, srf_updates[i].cm->flags.bits.lut3d_enable && srf_updates[i].cm->flags.bits.lut3d_dma_enable && dc->hwss.trigger_3dlut_dma_load) - dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx); + dc->hwss.trigger_3dlut_dma_load(pipe_ctx); /*program triple buffer after lock based on flip type*/ if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 357899116ecd5..a72284c3fa1c9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -369,12 +369,14 @@ void dcn401_init_hw(struct dc *dc) } } -void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) +void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx) { - struct hubp *hubp = pipe_ctx->plane_res.hubp; + const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx); + struct hubp *primary_hubp = primary_dpp_pipe_ctx ? + primary_dpp_pipe_ctx->plane_res.hubp : NULL; - if (hubp->funcs->hubp_enable_3dlut_fl) { - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + if (primary_hubp && primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); } } @@ -382,8 +384,11 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; + const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx); struct dpp *dpp_base = pipe_ctx->plane_res.dpp; struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct hubp *primary_hubp = primary_dpp_pipe_ctx ? + primary_dpp_pipe_ctx->plane_res.hubp : NULL; const struct dc_plane_cm *cm = &plane_state->cm; int mpcc_id = hubp->inst; struct mpc *mpc = dc->res_pool->mpc; @@ -481,25 +486,41 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id); if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, primary_hubp->inst); /* HUBP */ - if (hubp->funcs->hubp_program_3dlut_fl_config) - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); + if (primary_hubp->inst == hubp->inst) { + /* only program if this is the primary dpp pipe for the given plane */ + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); - if (hubp->funcs->hubp_program_3dlut_fl_crossbar) - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); - if (hubp->funcs->hubp_enable_3dlut_fl) { - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + if (hubp->funcs->hubp_enable_3dlut_fl) { + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + } else { + /* GPU memory only supports fast load path */ + BREAK_TO_DEBUGGER(); + lut_enable = false; + result = false; + } } else { - /* GPU memory only supports fast load path */ - BREAK_TO_DEBUGGER(); - lut_enable = false; - result = false; + /* re-trigger priamry HUBP to load 3DLUT */ + if (primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); + } + + /* clear FL setup on this pipe's HUBP */ + memset(&lut3d_dma, 0, sizeof(lut3d_dma)); + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); + + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); } } else { /* Legacy (Host) Load Mode */ @@ -1809,42 +1830,41 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless * of whether OTG lock is currently being held or not. */ - struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL }; - struct pipe_ctx *odm_pipe, *mpc_pipe; - int i, wa_pipe_ct = 0; - - for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) { - for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { - if (mpc_pipe->plane_state && - mpc_pipe->plane_state->cm.flags.bits.lut3d_enable && - mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) { - wa_pipes[wa_pipe_ct++] = mpc_pipe; - } - } + const struct pipe_ctx *otg_master_pipe_ctx = resource_get_otg_master(pipe_ctx); + struct timing_generator *tg = otg_master_pipe_ctx ? + otg_master_pipe_ctx->stream_res.tg : NULL; + const struct pipe_ctx *primary_dpp_pipe_ctx = resource_is_pipe_type(pipe_ctx, DPP_PIPE) ? + resource_get_primary_dpp_pipe(pipe_ctx) : pipe_ctx; + struct hubp *primary_hubp = primary_dpp_pipe_ctx ? + primary_dpp_pipe_ctx->plane_res.hubp : NULL; + + if (!otg_master_pipe_ctx && !tg) { + return; } - if (wa_pipe_ct > 0) { - if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout) - pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true); + if (primary_dpp_pipe_ctx && + primary_dpp_pipe_ctx->plane_state && + primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_enable && + primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_dma_enable) { + if (tg->funcs->set_vupdate_keepout) + tg->funcs->set_vupdate_keepout(tg, true); - for (i = 0; i < wa_pipe_ct; ++i) { - if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl) - wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); + if (primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); } - pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); - if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status) - pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false); + tg->funcs->unlock(tg); + if (tg->funcs->wait_update_lock_status) + tg->funcs->wait_update_lock_status(tg, false); - for (i = 0; i < wa_pipe_ct; ++i) { - if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl) - wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); + if (primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); } - if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout) - pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false); + if (tg->funcs->set_vupdate_keepout) + tg->funcs->set_vupdate_keepout(tg, false); } else { - pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); + tg->funcs->unlock(tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index f78162ab859b4..b9a03ffa27179 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -41,8 +41,7 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, bool dcn401_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); -void dcn401_trigger_3dlut_dma_load(struct dc *dc, - struct pipe_ctx *pipe_ctx); +void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx); void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx, unsigned int *tmds_div); enum dc_status dcn401_enable_stream_timing( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index d1dba7ffcd9b3..98abe0d2d30f6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1120,7 +1120,7 @@ struct hw_sequencer_funcs { void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id); - void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*trigger_3dlut_dma_load)(struct pipe_ctx *pipe_ctx); /* VM Related */ int (*init_sys_ctx)(struct dce_hwseq *hws, From 9bea38cb6325356010d2fd53a6265f73397ff53c Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 10 Mar 2026 16:33:44 -0400 Subject: [PATCH 1979/2070] drm/amd/display: Revert inbox0 lock for cursor due to deadlock [Why] A deadlock occurs when using inbox0 lock for cursor operations on PSR-SU and Replays that does not when using the inbox1 locking path. This is because of a priority inversion issue where inbox1 work cannot be serviced while holding the HW lock from driver and sending cursor notifications to DMUB. Typically the lower priority of inbox1 for the lock command would allow the PSR and Replay FSMs to complete their transition prior to giving driver the lock but this is no longer the case with inbox0 having the highest priority in servicing. [How] This will reintroduce any synchronization bugs that were there with Replay or PSR-SU touching the cursor at the same time as driver. Reviewed-by: Charlene Liu Signed-off-by: Nicholas Kazlauskas Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/dc/core/dc_stream.c | 30 +++---------------- 1 file changed, 4 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 44e17329c6373..87ecef6e699fa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -33,7 +33,6 @@ #include "dc_dmub_srv.h" #include "dc_state_priv.h" #include "dc_stream_priv.h" -#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER dc->ctx->logger #ifndef MIN @@ -259,7 +258,6 @@ void program_cursor_attributes( struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); - bool unlock_dmub = false; if (!stream) return; @@ -278,12 +276,6 @@ void program_cursor_attributes( if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); } else { - if (dc->hwss.dmub_hw_control_lock && pipe_ctx->stream && - should_use_dmub_inbox0_lock_for_link(dc, pipe_ctx->stream->link)) { - dc->hwss.dmub_hw_control_lock(dc, dc->current_state, true); - unlock_dmub = true; - } - dc->hwss.cursor_lock(dc, pipe_to_program, true); if (pipe_to_program->next_odm_pipe) dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); @@ -306,9 +298,6 @@ void program_cursor_attributes( dc->hwss.cursor_lock(dc, pipe_to_program, false); if (pipe_to_program->next_odm_pipe) dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); - - if (unlock_dmub) - dc->hwss.dmub_hw_control_lock(dc, dc->current_state, false); } } } @@ -416,7 +405,6 @@ void program_cursor_position( struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); - bool unlock_dmub = false; if (!stream) return; @@ -436,16 +424,10 @@ void program_cursor_position( if (!pipe_to_program) { pipe_to_program = pipe_ctx; - if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); - } else { - if (dc->hwss.dmub_hw_control_lock && pipe_ctx->stream && - should_use_dmub_inbox0_lock_for_link(dc, pipe_ctx->stream->link)) { - dc->hwss.dmub_hw_control_lock(dc, dc->current_state, true); - unlock_dmub = true; - } + else dc->hwss.cursor_lock(dc, pipe_to_program, true); - } } dc->hwss.set_cursor_position(pipe_ctx); @@ -457,14 +439,10 @@ void program_cursor_position( } if (pipe_to_program) { - if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) dc->hwss.commit_cursor_offload_update(dc, pipe_to_program); - } else { + else dc->hwss.cursor_lock(dc, pipe_to_program, false); - - if (unlock_dmub) - dc->hwss.dmub_hw_control_lock(dc, dc->current_state, false); - } } } From fced4b3fcec50f9ff070e1b8493e2bd38f44f350 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Tue, 3 Mar 2026 20:07:58 -0500 Subject: [PATCH 1980/2070] drm/amd/display: Move DPM clk read to clk_mgr_construct in DCN42 [Why&How] The DPM clocks on DCN42 are currently read on every dm_resume, which can cause in gpu memory freeing while the device is still in suspend. Move the DPM clock read functionality to clk_mgr_construct() so it completes once on driver enablement. Reviewed-by: Charlene Liu Signed-off-by: Ivan Lipski Signed-off-by: Dmytro Laktyushkin Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 24834f89711df..5671fe481d150 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -1146,6 +1146,11 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); } /* in case we don't get a value from the BIOS, use default */ if (clk_mgr->base.base.dentist_vco_freq_khz == 0) From 50e9108a050fdd254a64fb40f747ef3af175aff1 Mon Sep 17 00:00:00 2001 From: Matthew Stewart Date: Wed, 11 Mar 2026 15:16:00 -0400 Subject: [PATCH 1981/2070] drm/amd/display: Hardcode dtbclk value in bw_params [why&how] dtbclk should always be 600MHz. Previous logic was to get the real value from SMU, but this returns 0 when dtbclk is off. Not a problem during boot when pre-OS enables dtbclk, but PnP was broken due to this. Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Matthew Stewart Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 5671fe481d150..b4c6522e922c5 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -594,10 +594,7 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; - if (clk_mgr_base->boot_snapshot.dtbclk > 59000) { - /*dtbclk enabled based on*/ - clk_mgr_base->clks.dtbclk_en = true; - } + clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000; } static struct clk_bw_params dcn42_bw_params = { @@ -1069,7 +1066,7 @@ static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int) clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; /* DTBCLK*/ - clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; + clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = 600; /* Fixed on platform */ clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; } } From 62eecb2da65782bb5df23a90b6ca224fbdce6456 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Thu, 12 Mar 2026 10:21:43 -0400 Subject: [PATCH 1982/2070] drm/amd/display: Fix Signed/Unsigned Int Usage Compiler Warning [Why] Compiler generates compiler warnings when signed enum constants or literal -1 are implicitly converted to unsigned integer types, cluttering build output and masking genuine issues. [How] Use UINT_MAX as the invalid sentinel for unsigned IDs and align loop/index types to unsigned where appropriate to remove implicit signed-to-unsigned conversions, with no functional behavior change. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Gaghik Khachatrian Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c index 74812a7d5e28c..fd3c61509f1b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c @@ -143,7 +143,7 @@ static unsigned int find_pipes_assigned_to_plane(struct dml2_context *ctx, { int i; unsigned int num_found = 0; - unsigned int plane_id_assigned_to_pipe = -1; + unsigned int plane_id_assigned_to_pipe = UINT_MAX; for (i = 0; i < ctx->config.dcn_pipe_count; i++) { struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; From f16ef4b2010ee0a50ac64c26412acfa6c41ef28b Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 11 Mar 2026 17:05:19 -0400 Subject: [PATCH 1983/2070] drm/amd/display: remove dc_clock_limit for apu [why] current apu pmfw does not support dc_clock_limit Reviewed-by: Roman Li Signed-off-by: Charlene Liu Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index fa5d0558192cf..6328b3dc35f9d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -2018,7 +2018,7 @@ static bool dcn42_resource_construct( dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; dc->config.use_pipe_ctx_sync_logic = true; - dc->config.dc_mode_clk_limit_support = true; + dc->config.dc_mode_clk_limit_support = false; dc->config.enable_windowed_mpo_odm = true; /* Use psp mailbox to enable assr */ dc->config.use_assr_psp_message = true; From 04b06de6b98a1e65c725b6447c9e02df65813d04 Mon Sep 17 00:00:00 2001 From: ChunTao Tso Date: Wed, 4 Mar 2026 16:37:58 +0800 Subject: [PATCH 1984/2070] drm/amd/display: Agument live + capture with CVT case. 1. Add LIVE_CAPTURE_WITH_CVT bit (bit[2]) in union replay_optimization to control this feature via DalRegKey_ReplayOptimization. 2. Check the bit in mod_power_set_live_capture_with_cvt_activate function before enabling live capture with CVT. 3. Use LIVE_CAPTURE_WITH_CVT to control if Replay want to send CVT in live + capture or not. Reviewed-by: Leon Huang Signed-off-by: ChunTao Tso Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/dc_types.h | 8 ++++++-- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index e224077c8902e..fd8ec16603125 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1144,10 +1144,12 @@ union replay_low_refresh_rate_enable_options { union replay_optimization { struct { - //BIT[0-3]: Replay Teams Optimization + //BIT[0-1]: Replay Teams Optimization unsigned int TEAMS_OPTIMIZATION_VER_1 :1; unsigned int TEAMS_OPTIMIZATION_VER_2 :1; - unsigned int RESERVED_2_3 :2; + //BIT[2]: Replay Live Capture with CVT + unsigned int LIVE_CAPTURE_WITH_CVT :1; + unsigned int RESERVED_3 :1; } bits; unsigned int raw; @@ -1196,6 +1198,8 @@ struct replay_config { bool frame_skip_supported; /* Replay Received Frame Skipping Error HPD. */ bool received_frame_skipping_error_hpd; + /* Live capture with CVT is activated */ + bool live_capture_with_cvt_activated; }; /* Replay feature flags*/ diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index e11e32afac6be..8fbd179a4c87a 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4437,6 +4437,7 @@ enum dmub_cmd_replay_general_subtype { REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, + REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT, }; struct dmub_alpm_auxless_data { From d869c19648988969228b2eab4e44413cafbe61ee Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Fri, 13 Mar 2026 12:05:40 +0800 Subject: [PATCH 1985/2070] drm/amd/display: Remove unnecessary completion flag for secure display The completion flag is not used in secure display today. Remove unnecessary code. Reviewed-by: Tom Chung Signed-off-by: Wayne Lin Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 7 ------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 1 - 2 files changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 1b03f2bf8d7a8..dd79866df1fda 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -812,7 +812,6 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) unsigned long flags1; bool forward_roi_change = false; bool notify_ta = false; - bool all_crc_ready = true; struct dc_stream_state *stream_state; int i; @@ -936,9 +935,6 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) continue; } - if (!crtc_ctx->crc_info.crc[i].crc_ready) - all_crc_ready = false; - if (reset_crc_frame_count[i] || crtc_ctx->crc_info.crc[i].frame_count == UINT_MAX) /* Reset the reference frame count after user update the ROI * or it reaches the maximum value. @@ -948,9 +944,6 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) crtc_ctx->crc_info.crc[i].frame_count += 1; } spin_unlock_irqrestore(&crtc_ctx->crc_info.lock, flags1); - - if (all_crc_ready) - complete_all(&crtc_ctx->crc_info.completion); } void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 95bdb8699d7fa..8538513ea8799 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -70,7 +70,6 @@ struct crc_data { struct crc_info { struct crc_data crc[MAX_CRC_WINDOW_NUM]; - struct completion completion; spinlock_t lock; }; From 2ed622ce58a1a74e6987dba7ff866bb982fae3ce Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 12 Mar 2026 19:33:33 -0400 Subject: [PATCH 1986/2070] drm/amd/display: add dccg FGCG mask init [why] missing DCCG_GLOBAL_FGCG_REP_DIS mask macro init Reviewed-by: Swapnil Patel Signed-off-by: Charlene Liu Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h index d9831b0f82359..2076565b1caab 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h @@ -122,6 +122,7 @@ DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\ From ad2d0088826f21292ab6d560b091aa775510a465 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Thu, 12 Mar 2026 18:33:49 -0400 Subject: [PATCH 1987/2070] drm/amd/display: Restore full update for tiling change to linear [Why] There was previously a dc debug flag to indicate that tiling changes should only be a medium update instead of full. The function get_plane_info_type was refactored to not rely on dc state, but in the process the logic was unintentionally changed, which leads to screen corruption in some cases. [How] - add flag to tiling struct to avoid full update when necessary Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aric Cyr Signed-off-by: Joshua Aberback Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/core/dc.c | 26 ++++---------------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 4 +++ 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d6673c724cecb..604f75ec40c83 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2770,28 +2770,12 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { update_flags->bits.swizzle_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); - switch (tiling->gfxversion) { - case DcGfxVersion9: - case DcGfxVersion10: - case DcGfxVersion11: - if (tiling->gfx9.swizzle != DC_SW_LINEAR) { - update_flags->bits.bandwidth_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - } - break; - case DcGfxAddr3: - if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { - update_flags->bits.bandwidth_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - } - break; - case DcGfxVersion7: - case DcGfxVersion8: - case DcGfxVersionUnknown: - default: - break; + if (tiling->flags.avoid_full_update_on_tiling_change) { + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } else { + update_flags->bits.bandwidth_change = 1; + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } } diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 9bf853edc46fc..595e082db2816 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -445,6 +445,10 @@ enum dc_gfxversion { enum swizzle_mode_addr3_values swizzle; } gfx_addr3;/*gfx with addr3 and above*/ }; + + struct { + bool avoid_full_update_on_tiling_change; + } flags; }; /* Rotation angle */ From f016cd3113e1388dfa662d04acc0412673ea1da4 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Wed, 11 Mar 2026 17:02:24 -0400 Subject: [PATCH 1988/2070] drm/amd/display: Rework YCbCr422 DSC policy - Reworked YCbCr4:2:2 Native/Simple policy decision making with DSC enabled based on DSC caps and stream signal type Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 1 + .../amd/display/dc/dml2_0/dml2_translation_helper.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 13 ++++++------- .../gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 +- .../gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 2 +- .../gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c | 2 +- .../gpu/drm/amd/display/dc/link/link_detection.c | 10 +++++----- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 3 ++- .../amd/display/dc/resource/dcn31/dcn31_resource.c | 2 ++ .../display/dc/resource/dcn315/dcn315_resource.c | 2 ++ 11 files changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 17b77868e4a0f..b4e87ab9674c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -562,6 +562,7 @@ struct dc_config { bool frame_update_cmd_version2; struct spl_sharpness_range dcn_sharpness_range; struct spl_sharpness_range dcn_override_sharpness_range; + bool no_native422_support; }; enum visual_confirm { @@ -986,7 +987,6 @@ struct link_service; * causing an issue or not. */ struct dc_debug_options { - bool native422_support; bool disable_dsc; enum visual_confirm visual_confirm; int visual_confirm_rect_height; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 9d18f1c080791..101bce6b8de64 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -52,6 +52,7 @@ struct dc_dsc_policy { uint32_t max_target_bpp; uint32_t min_target_bpp; bool enable_dsc_when_not_needed; + bool ycbcr422_simple; }; struct dc_dsc_config_options { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c index d834cb595afab..e25b88f2d6b9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c @@ -1174,12 +1174,12 @@ static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2 const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index) { unsigned int plane_id; - int i = 0; - int location = -1; + unsigned int i = 0; + unsigned int location = UINT_MAX; if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { ASSERT(false); - return -1; + return UINT_MAX; } for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 5b3584ad5b6b3..8dfb6dd14eb29 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -680,9 +680,6 @@ static void get_dsc_enc_caps( } else { build_dsc_enc_caps(dsc, dsc_enc_caps); } - - if (dsc->ctx->dc->debug.native422_support) - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; } /* Returns 'false' if no intersection was found for at least one capability. @@ -1100,13 +1097,14 @@ static bool setup_dsc_config( branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps; break; case PIXEL_ENCODING_YCBCR422: - is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; - sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; - branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; - if (!is_dsc_possible) { + if (policy.ycbcr422_simple) { is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422; dsc_cfg->ycbcr422_simple = is_dsc_possible; sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps; + } else { + is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; + sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; + branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; } break; case PIXEL_ENCODING_YCBCR420: @@ -1406,6 +1404,7 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, policy->min_target_bpp = 8; /* DP specs limits to 3 x bpc */ policy->max_target_bpp = 3 * bpc; + policy->ycbcr422_simple = true; break; case PIXEL_ENCODING_YCBCR420: /* DP specs limits to 6 */ diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 8111e738f5d53..91d205f01beba 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -100,7 +100,7 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) dsc_enc_caps->color_formats.bits.RGB = 1; dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c index e712985f7abdb..17acb64a9d804 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c @@ -128,7 +128,7 @@ void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int m dsc_enc_caps->color_formats.bits.RGB = 1; dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index c1bdbb38c690b..bbb8b5b18a4e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -78,7 +78,7 @@ static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsign dsc_enc_caps->color_formats.bits.RGB = 1; dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index f992c2d167487..7f1761080aba0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -781,7 +781,6 @@ static void restore_phy_clocks_for_destructive_link_verification(const struct dc } static void verify_link_capability_destructive(struct dc_link *link, - struct dc_sink *sink, enum dc_detect_reason reason) { bool should_prepare_phy_clocks = @@ -855,11 +854,11 @@ static bool should_verify_link_capability_destructively(struct dc_link *link, return destrictive; } -static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, +static void verify_link_capability(struct dc_link *link, enum dc_detect_reason reason) { if (should_verify_link_capability_destructively(link, reason)) - verify_link_capability_destructive(link, sink, reason); + verify_link_capability_destructive(link, reason); else verify_link_capability_non_destructive(link); } @@ -1453,8 +1452,9 @@ bool link_detect(struct dc_link *link, enum dc_detect_reason reason) is_local_sink_detect_success = detect_link_and_local_sink(link, reason); - if (is_local_sink_detect_success && link->local_sink) - verify_link_capability(link, link->local_sink, reason); + if (is_local_sink_detect_success && link->local_sink) { + verify_link_capability(link, reason); + } DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, link->link_index, is_local_sink_detect_success, pre_link_type, link->type); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index e14c89eae6d89..dc3398ad5835e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -181,7 +181,8 @@ void link_set_all_streams_dpms_off_for_link(struct dc_link *link) /* link can be also enabled by vbios. In this case it is not recorded * in pipe_ctx. Disable link phy here to make sure it is completely off */ - dp_disable_link_phy(link, &link_res, link->connector_signal); + if (dc_is_dp_signal(link->connector_signal)) + dp_disable_link_phy(link, &link_res, link->connector_signal); } void link_resume(struct dc_link *link) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index a064d1fbce523..95c7ecdb34961 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -1967,6 +1967,8 @@ static bool dcn31_resource_construct( dc->config.use_pipe_ctx_sync_logic = true; dc->config.disable_hbr_audio_dp2 = true; + dc->config.no_native422_support = true; + /* read VBIOS LTTPR caps */ { if (ctx->dc_bios->funcs->get_lttpr_caps) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 67102b4c881fe..e488fa6f32e67 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1929,6 +1929,8 @@ static bool dcn315_resource_construct( dc->caps.color.mpc.ogam_rom_caps.hlg = 0; dc->caps.color.mpc.ocsc = 1; + dc->config.no_native422_support = true; + /* read VBIOS LTTPR caps */ { if (ctx->dc_bios->funcs->get_lttpr_caps) { From 9ff12058931739ceff606d4f3a5e5d42a07165f4 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 13 Mar 2026 17:42:59 -0500 Subject: [PATCH 1989/2070] drm/amd/display: Promote DC to 3.2.375 This version brings along following fixes: - Rework YCbCr422 DSC policy - Restore full update for tiling change to linear - add dccg FGCG mask init - Remove unnecessary completion flag for secure display - Agument live + capture with CVT case. - remove dc_clock_limit for apu - Fix Signed/Unsigned Int Usage Compiler Warning - Hardcode dtbclk value in bw_params - Revert inbox0 lock for cursor due to deadlock - Add 3DLUT DMA broadcast support - Fix Silence warnings - export get_power_profile interface for later use - pg cntl update based on previous asic. - remove disable_sutter touch pstate debug code - Refactor DC update checks - Fix drm_edid leak in amdgpu_dm - Add Extra SMU Log for dtbclk - Clamp min DS DCFCLK value to DCN limit - Update dpia supported configuration - Multiple DCN42 updates Acked-by: ChiaHsuan Chung Signed-off-by: Taimur Hassan Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b4e87ab9674c5..9e0f53a82c83f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.374" +#define DC_VER "3.2.375" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From f8582b163254de28f6883d317b891d8d4895990c Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Thu, 26 Feb 2026 11:41:48 +0800 Subject: [PATCH 1990/2070] drm/amdgpu: Add amdgpu_regs_pcie64 debugfs node Add amdgpu_regs_pcie64 debugfs node to read/write 64bit PCIE registers. Change-Id: I6c8a2245eb11ccd871c366ef103d40146f071d0b Signed-off-by: Stanley.Yang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 112 ++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 8567d1762b786..f21a57b7c74c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -617,6 +617,110 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user return r; } +/** + * amdgpu_debugfs_regs_pcie64_read - Read from a 64-bit PCIE register + * + * @f: open file handle + * @buf: User buffer to store read data in + * @size: Number of bytes to read + * @pos: Offset to seek to + */ +static ssize_t amdgpu_debugfs_regs_pcie64_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x7 || *pos & 0x7) + return -EINVAL; + + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + r = amdgpu_virt_enable_access_debugfs(adev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + uint64_t value; + + value = RREG64_PCIE_EXT(*pos); + + r = put_user(value, (uint64_t *)buf); + if (r) + goto out; + + result += 8; + buf += 8; + *pos += 8; + size -= 8; + } + + r = result; +out: + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + amdgpu_virt_disable_access_debugfs(adev); + return r; +} + +/** + * amdgpu_debugfs_regs_pcie64_write - Write to a 64-bit PCIE register + * + * @f: open file handle + * @buf: User buffer to write data from + * @size: Number of bytes to write + * @pos: Offset to seek to + */ +static ssize_t amdgpu_debugfs_regs_pcie64_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x7 || *pos & 0x7) + return -EINVAL; + + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + r = amdgpu_virt_enable_access_debugfs(adev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + uint64_t value; + + r = get_user(value, (uint64_t *)buf); + if (r) + goto out; + + WREG64_PCIE_EXT(*pos, value); + + result += 8; + buf += 8; + *pos += 8; + size -= 8; + } + + r = result; +out: + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + amdgpu_virt_disable_access_debugfs(adev); + return r; +} + /** * amdgpu_debugfs_regs_didt_read - Read from a DIDT register * @@ -1525,6 +1629,12 @@ static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { .write = amdgpu_debugfs_regs_pcie_write, .llseek = default_llseek }; +static const struct file_operations amdgpu_debugfs_regs_pcie64_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_pcie64_read, + .write = amdgpu_debugfs_regs_pcie64_write, + .llseek = default_llseek +}; static const struct file_operations amdgpu_debugfs_regs_smc_fops = { .owner = THIS_MODULE, .read = amdgpu_debugfs_regs_smc_read, @@ -1587,6 +1697,7 @@ static const struct file_operations *debugfs_regs[] = { &amdgpu_debugfs_gprwave_fops, &amdgpu_debugfs_regs_didt_fops, &amdgpu_debugfs_regs_pcie_fops, + &amdgpu_debugfs_regs_pcie64_fops, &amdgpu_debugfs_regs_smc_fops, &amdgpu_debugfs_gca_config_fops, &amdgpu_debugfs_sensors_fops, @@ -1604,6 +1715,7 @@ static const char * const debugfs_regs_names[] = { "amdgpu_gprwave", "amdgpu_regs_didt", "amdgpu_regs_pcie", + "amdgpu_regs_pcie64", "amdgpu_regs_smc", "amdgpu_gca_config", "amdgpu_sensors", From b8585907c2cf3a38c9127daba085663e1212cfdd Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Mon, 9 Mar 2026 11:16:08 -0600 Subject: [PATCH 1991/2070] drm/amd/display: Fix drm_edid leak in amdgpu_dm [WHAT] When a sink is connected, aconnector->drm_edid was overwritten without freeing the previous allocation, causing a memory leak on resume. [HOW] Free the previous drm_edid before updating it. Reviewed-by: Roman Li Signed-off-by: Alex Hung Signed-off-by: Chuanyu Tseng --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9cbeb1ceb21ad..49647ec2d1bff 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4053,12 +4053,13 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); - if (sink->dc_edid.length == 0) { #ifdef HAVE_DRM_DP_MST_EDID_READ - aconnector->drm_edid = NULL; + drm_edid_free(aconnector->drm_edid); + aconnector->drm_edid = NULL; #else - aconnector->edid = NULL; + aconnector->edid = NULL; #endif + if (sink->dc_edid.length == 0) { hdmi_cec_unset_edid(aconnector); if (aconnector->dc_link->aux_mode) { drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); From 959ba82019c43d7b4ef14226bcc0bfdbb2986566 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 5 Mar 2026 16:42:29 -0500 Subject: [PATCH 1992/2070] drm/amd/display: Refactor DC update checks [WHY&HOW] DC currently has fragmented definitions of update types. This changes consolidates them into a single interface, and adds expanded functionality to accommodate all use cases. - adds `dc_check_update_state_and_surfaces_for_stream` to determine update type including state, surface, and stream changes. - adds missing surface/stream update checks to `dc_check_update_surfaces_for_stream` - adds new update type `UPDATE_TYPE_ADDR_ONLY` to accomodate flows where further distinction from `UPDATE_TYPE_FAST` was needed - removes caller reliance on `enable_legacy_fast_update` to determine which commit function to use, instead embedding it in the update type Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dillon Varone Signed-off-by: Chuanyu Tseng --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 472 ++++++++---------- drivers/gpu/drm/amd/display/dc/dc.h | 20 +- 4 files changed, 201 insertions(+), 299 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 49647ec2d1bff..b434ba27df1e4 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10200,7 +10200,7 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, } /* Decrement skip count when SR is enabled and we're doing fast updates. */ - if (acrtc_state->update_type == UPDATE_TYPE_FAST && + if (acrtc_state->update_type <= UPDATE_TYPE_FAST && (psr->psr_feature_enabled || pr->config.replay_supported)) { if (aconn->sr_skip_count > 0) aconn->sr_skip_count--; @@ -10413,7 +10413,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if ((crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0 && #endif - (acrtc_state->update_type != UPDATE_TYPE_FAST || + (acrtc_state->update_type > UPDATE_TYPE_FAST || get_mem_type(old_plane_state->fb) != get_mem_type(fb))) drm_warn_once(state->dev, "[PLANE:%d:%s] async flip with non-fast update\n", @@ -10426,7 +10426,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0 && #endif - acrtc_state->update_type == UPDATE_TYPE_FAST && + acrtc_state->update_type <= UPDATE_TYPE_FAST && get_mem_type(old_plane_state->fb) == get_mem_type(fb); timestamp_ns = ktime_get_ns(); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index a781ef874595d..252c4d21c4967 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -703,7 +703,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, if ((crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0 && #endif - dm_crtc_state->update_type != UPDATE_TYPE_FAST) { + dm_crtc_state->update_type > UPDATE_TYPE_FAST) { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] async flips are only supported for fast updates\n", crtc->base.id, crtc->name); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 604f75ec40c83..0389c379d0120 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2696,7 +2696,7 @@ static bool is_surface_in_context( static struct surface_update_descriptor get_plane_info_update_type(const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; - struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor update_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; if (!u->plane_info) return update_type; @@ -2788,7 +2788,7 @@ static struct surface_update_descriptor get_scaling_info_update_type( const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; - struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor update_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; if (!u->scaling_info) return update_type; @@ -2839,11 +2839,11 @@ static struct surface_update_descriptor get_scaling_info_update_type( return update_type; } -static struct surface_update_descriptor det_surface_update( +static struct surface_update_descriptor check_update_surface( const struct dc_check_config *check_config, struct dc_surface_update *u) { - struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor overall_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; union surface_update_flags *update_flags = &u->surface->update_flags; if (u->surface->force_full_update) { @@ -2863,7 +2863,7 @@ static struct surface_update_descriptor det_surface_update( if (u->flip_addr) { update_flags->bits.addr_update = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_STREAM); if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { update_flags->bits.tmz_changed = 1; @@ -2877,27 +2877,43 @@ static struct surface_update_descriptor det_surface_update( if (u->input_csc_color_matrix) { update_flags->bits.input_csc_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); + } + + if (u->cursor_csc_color_matrix) { + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->coeff_reduction_factor) { update_flags->bits.coeff_reduction_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->gamut_remap_matrix) { update_flags->bits.gamut_remap_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->cm || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { update_flags->bits.gamma_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->cm && (u->cm->flags.bits.lut3d_enable || u->surface->cm.flags.bits.lut3d_enable)) { update_flags->bits.lut_3d = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->cm && u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable && @@ -2913,9 +2929,10 @@ static struct surface_update_descriptor det_surface_update( if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { - // TODO: Should be fast? update_flags->bits.hdr_mult = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->sdr_white_level_nits) @@ -2969,7 +2986,7 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( int surface_count, struct dc_stream_update *stream_update) { - struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor overall_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; /* When countdown finishes, promote this flip to full to trigger deferred final transition */ if (check_config->deferred_transition_state && !check_config->transition_countdown_to_steady_state) { @@ -3036,7 +3053,18 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( if (su_flags->raw) elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - // Non-global cases + /* Non-global cases */ + if (stream_update->hdr_static_metadata || + stream_update->vrr_infopacket || + stream_update->vsc_infopacket || + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket || + stream_update->adaptive_sync_infopacket || + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + if (stream_update->output_csc_transform) { su_flags->bits.out_csc = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); @@ -3046,11 +3074,32 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( su_flags->bits.out_tf = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + + if (stream_update->periodic_interrupt) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->dither_option) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->cursor_position || stream_update->cursor_attributes) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + + /* TODO - cleanup post blend CM */ + if (stream_update->func_shaper || stream_update->lut3d_func) { + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->pending_test_pattern) { + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } } for (int i = 0 ; i < surface_count; i++) { struct surface_update_descriptor inner_type = - det_surface_update(check_config, &updates[i]); + check_update_surface(check_config, &updates[i]); elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); } @@ -3077,6 +3126,81 @@ struct surface_update_descriptor dc_check_update_surfaces_for_stream( return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update); } +/* + * check_update_state_and_surfaces_for_stream() - Determine update type (fast, med, or full) + * + * This function performs checks on the DC global state, and is therefore not re-entrant. It + * should not be called from DM. + * + * See :c:type:`enum surface_update_type ` for explanation of update types + */ +static struct surface_update_descriptor check_update_state_and_surfaces_for_stream( + const struct dc *dc, + const struct dc_check_config *check_config, + const struct dc_stream_state *stream, + const struct dc_surface_update *updates, + const int surface_count, + const struct dc_stream_update *stream_update) +{ + const struct dc_state *context = dc->current_state; + + struct surface_update_descriptor overall_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE}; + + if (updates) + for (int i = 0; i < surface_count; i++) + if (!is_surface_in_context(context, updates[i].surface)) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + + if (stream) { + const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream); + if (stream_status == NULL || stream_status->plane_count != surface_count) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } + if (dc->idle_optimizations_allowed) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + + if (dc_can_clear_cursor_limit(dc)) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + + return overall_type; +} + +/* + * dc_check_update_state_and_surfaces_for_stream() - Determine update type (fast, med, or full) + * + * This function performs checks on the DC global state, stream and surface update, and is + * therefore not re-entrant. It should not be called from DM. + * + * See :c:type:`enum surface_update_type ` for explanation of update types + */ +static struct surface_update_descriptor dc_check_update_state_and_surfaces_for_stream( + const struct dc *dc, + const struct dc_check_config *check_config, + struct dc_stream_state *stream, + struct dc_surface_update *updates, + int surface_count, + struct dc_stream_update *stream_update) +{ + /* check updates against the entire DC state (global) first */ + struct surface_update_descriptor overall_update_type = check_update_state_and_surfaces_for_stream( + dc, + check_config, + stream, + updates, + surface_count, + stream_update); + + /* check updates for stream and plane */ + struct surface_update_descriptor stream_update_type = dc_check_update_surfaces_for_stream( + check_config, + updates, + surface_count, + stream_update); + elevate_update_type(&overall_update_type, stream_update_type.update_type, stream_update_type.lock_descriptor); + + return overall_update_type; +} + static struct dc_stream_status *stream_get_status( struct dc_state *ctx, struct dc_stream_state *stream) @@ -3434,13 +3558,6 @@ static void update_seamless_boot_flags(struct dc *dc, } } -static bool full_update_required_weak( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream); - struct pipe_split_policy_backup { bool dynamic_odm_policy; bool subvp_policy; @@ -3510,12 +3627,11 @@ static bool update_planes_and_stream_state(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update, - enum surface_update_type *new_update_type, + struct surface_update_descriptor *update_descriptor, struct dc_state **new_context) { struct dc_state *context; int i, j; - enum surface_update_type update_type; const struct dc_stream_status *stream_status; struct dc_context *dc_ctx = dc->ctx; @@ -3529,17 +3645,20 @@ static bool update_planes_and_stream_state(struct dc *dc, } context = dc->current_state; - update_type = dc_check_update_surfaces_for_stream( - &dc->check_config, srf_updates, surface_count, stream_update).update_type; - if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) - update_type = UPDATE_TYPE_FULL; + *update_descriptor = dc_check_update_state_and_surfaces_for_stream( + dc, + &dc->check_config, + stream, + srf_updates, + surface_count, + stream_update); /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. */ force_immediate_gsl_plane_flip(dc, srf_updates, surface_count); - if (update_type == UPDATE_TYPE_FULL) + if (update_descriptor->update_type == UPDATE_TYPE_FULL) backup_planes_and_stream_state(&dc->scratch.current_state, stream); /* update current stream with the new updates */ @@ -3565,7 +3684,7 @@ static bool update_planes_and_stream_state(struct dc *dc, } } - if (update_type == UPDATE_TYPE_FULL) { + if (update_descriptor->update_type == UPDATE_TYPE_FULL) { if (stream_update) { uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed; stream_update->stream->update_flags.raw = 0xFFFFFFFF; @@ -3575,13 +3694,13 @@ static bool update_planes_and_stream_state(struct dc *dc, srf_updates[i].surface->update_flags.raw = 0xFFFFFFFF; } - if (update_type >= update_surface_trace_level) + if (update_descriptor->update_type >= update_surface_trace_level) update_surface_trace(dc, srf_updates, surface_count); for (i = 0; i < surface_count; i++) copy_surface_update_to_plane(srf_updates[i].surface, &srf_updates[i]); - if (update_type >= UPDATE_TYPE_FULL) { + if (update_descriptor->update_type >= UPDATE_TYPE_FULL) { struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) @@ -3619,7 +3738,7 @@ static bool update_planes_and_stream_state(struct dc *dc, for (i = 0; i < surface_count; i++) { struct dc_plane_state *surface = srf_updates[i].surface; - if (update_type != UPDATE_TYPE_MED) + if (update_descriptor->update_type != UPDATE_TYPE_MED) continue; if (surface->update_flags.bits.position_change) { for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -3633,7 +3752,7 @@ static bool update_planes_and_stream_state(struct dc *dc, } } - if (update_type == UPDATE_TYPE_FULL) { + if (update_descriptor->update_type == UPDATE_TYPE_FULL) { struct pipe_split_policy_backup policy; bool minimize = false; @@ -3662,8 +3781,7 @@ static bool update_planes_and_stream_state(struct dc *dc, update_seamless_boot_flags(dc, context, surface_count, stream); *new_context = context; - *new_update_type = update_type; - if (update_type == UPDATE_TYPE_FULL) + if (update_descriptor->update_type == UPDATE_TYPE_FULL) backup_planes_and_stream_state(&dc->scratch.new_state, stream); return true; @@ -3743,7 +3861,7 @@ static void commit_planes_do_stream_update(struct dc *dc, program_cursor_position(dc, stream); /* Full fe update*/ - if (update_type == UPDATE_TYPE_FAST) + if (update_type <= UPDATE_TYPE_FAST) continue; if (stream_update->dsc_config) @@ -4052,7 +4170,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, struct pipe_ctx *top_pipe_to_program = NULL; struct dc_stream_status *stream_status = NULL; bool should_offload_fams2_flip = false; - bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); + bool should_lock_all_pipes = (update_type > UPDATE_TYPE_FAST); if (should_lock_all_pipes) determine_pipe_unlock_order(dc, context); @@ -4112,7 +4230,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, continue; pipe_ctx->plane_state->triplebuffer_flips = false; - if (update_type == UPDATE_TYPE_FAST && + if (update_type <= UPDATE_TYPE_FAST && dc->hwss.program_triplebuffer != NULL && !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { /*triple buffer for VUpdate only*/ @@ -4169,7 +4287,7 @@ static void commit_planes_for_stream(struct dc *dc, { int i, j; struct pipe_ctx *top_pipe_to_program = NULL; - bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); + bool should_lock_all_pipes = (update_type > UPDATE_TYPE_FAST); bool subvp_prev_use = false; bool subvp_curr_use = false; uint8_t current_stream_mask = 0; @@ -4186,7 +4304,7 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FULL && dc->optimized_required) hwss_process_outstanding_hw_updates(dc, dc->current_state); - if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming) + if (update_type > UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming) dc->res_pool->funcs->prepare_mcache_programming(dc, context); for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -4248,7 +4366,7 @@ static void commit_planes_for_stream(struct dc *dc, odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU; } - if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) + if ((update_type > UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program && top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { if (should_use_dmub_inbox1_lock(dc, stream->link)) { @@ -4319,7 +4437,7 @@ static void commit_planes_for_stream(struct dc *dc, } dc->hwss.post_unlock_program_front_end(dc, context); - if (update_type != UPDATE_TYPE_FAST) + if (update_type > UPDATE_TYPE_FAST) if (dc->hwss.commit_subvp_config) dc->hwss.commit_subvp_config(dc, context); @@ -4335,7 +4453,7 @@ static void commit_planes_for_stream(struct dc *dc, return; } - if (update_type != UPDATE_TYPE_FAST) { + if (update_type > UPDATE_TYPE_FAST) { for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -4363,7 +4481,7 @@ static void commit_planes_for_stream(struct dc *dc, if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; pipe_ctx->plane_state->triplebuffer_flips = false; - if (update_type == UPDATE_TYPE_FAST && + if (update_type <= UPDATE_TYPE_FAST && dc->hwss.program_triplebuffer != NULL && !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { /*triple buffer for VUpdate only*/ @@ -4390,7 +4508,7 @@ static void commit_planes_for_stream(struct dc *dc, continue; /* Full fe update*/ - if (update_type == UPDATE_TYPE_FAST) + if (update_type <= UPDATE_TYPE_FAST) continue; stream_status = @@ -4409,7 +4527,7 @@ static void commit_planes_for_stream(struct dc *dc, continue; /* Full fe update*/ - if (update_type == UPDATE_TYPE_FAST) + if (update_type <= UPDATE_TYPE_FAST) continue; ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); @@ -4420,7 +4538,7 @@ static void commit_planes_for_stream(struct dc *dc, } } - if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { + if (dc->hwss.program_front_end_for_ctx && update_type > UPDATE_TYPE_FAST) { dc->hwss.program_front_end_for_ctx(dc, context); //Pipe busy until some frame and line # @@ -4448,7 +4566,7 @@ static void commit_planes_for_stream(struct dc *dc, } // Update Type FAST, Surface updates - if (update_type == UPDATE_TYPE_FAST) { + if (update_type <= UPDATE_TYPE_FAST) { if (dc->hwss.set_flip_control_gsl) for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; @@ -4505,7 +4623,7 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); } - if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) + if ((update_type > UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program && top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { top_pipe_to_program->stream_res.tg->funcs->wait_for_state( @@ -4538,13 +4656,13 @@ static void commit_planes_for_stream(struct dc *dc, /* If enabling subvp or transitioning from subvp->subvp, enable the * phantom streams before we program front end for the phantom pipes. */ - if (update_type != UPDATE_TYPE_FAST) { + if (update_type > UPDATE_TYPE_FAST) { if (dc->hwss.enable_phantom_streams) dc->hwss.enable_phantom_streams(dc, context); } } - if (update_type != UPDATE_TYPE_FAST) + if (update_type > UPDATE_TYPE_FAST) dc->hwss.post_unlock_program_front_end(dc, context); if (subvp_prev_use && !subvp_curr_use) { @@ -4557,7 +4675,7 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.disable_phantom_streams(dc, context); } - if (update_type != UPDATE_TYPE_FAST) + if (update_type > UPDATE_TYPE_FAST) if (dc->hwss.commit_subvp_config) dc->hwss.commit_subvp_config(dc, context); /* Since phantom pipe programming is moved to post_unlock_program_front_end, @@ -5029,191 +5147,12 @@ static bool commit_minimal_transition_state(struct dc *dc, return true; } -void populate_fast_updates(struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_update *stream_update) -{ - int i = 0; - - if (stream_update) { - fast_update[0].out_transfer_func = stream_update->out_transfer_func; - fast_update[0].output_csc_transform = stream_update->output_csc_transform; - } else { - fast_update[0].out_transfer_func = NULL; - fast_update[0].output_csc_transform = NULL; - } - - for (i = 0; i < surface_count; i++) { - fast_update[i].flip_addr = srf_updates[i].flip_addr; - fast_update[i].gamma = srf_updates[i].gamma; - fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix; - fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix; - fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor; - fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix; - fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control; - } -} - -static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count) -{ - int i; - - if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) - return true; - - for (i = 0; i < surface_count; i++) { - if (fast_update[i].flip_addr || - fast_update[i].gamma || - fast_update[i].gamut_remap_matrix || - fast_update[i].input_csc_color_matrix || - fast_update[i].cursor_csc_color_matrix || - fast_update[i].cm_hist_control || - fast_update[i].coeff_reduction_factor) - return true; - } - - return false; -} - -bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count) -{ - int i; - - if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) - return true; - - for (i = 0; i < surface_count; i++) { - if (fast_update[i].input_csc_color_matrix || - fast_update[i].gamma || - fast_update[i].gamut_remap_matrix || - fast_update[i].coeff_reduction_factor || - fast_update[i].cm_hist_control || - fast_update[i].cursor_csc_color_matrix) - return true; - } - - return false; -} - -static bool full_update_required_weak( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - const struct dc_state *context = dc->current_state; - if (srf_updates) - for (int i = 0; i < surface_count; i++) - if (!is_surface_in_context(context, srf_updates[i].surface)) - return true; - - if (stream) { - const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream); - if (stream_status == NULL || stream_status->plane_count != surface_count) - return true; - } - if (dc->idle_optimizations_allowed) - return true; - - if (dc_can_clear_cursor_limit(dc)) - return true; - - return false; -} - -static bool full_update_required( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - const union dc_plane_cm_flags blend_only_flags = { - .bits = { - .blend_enable = 1, - } - }; - - if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) - return true; - - for (int i = 0; i < surface_count; i++) { - if (srf_updates && - (srf_updates[i].plane_info || - srf_updates[i].scaling_info || - (srf_updates[i].hdr_mult.value && - srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) || - (srf_updates[i].sdr_white_level_nits && - srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || - srf_updates[i].in_transfer_func || - srf_updates[i].surface->force_full_update || - (srf_updates[i].flip_addr && - srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || - (srf_updates[i].cm && - ((srf_updates[i].cm->flags.all != blend_only_flags.all && srf_updates[i].cm->flags.all != 0) || - (srf_updates[i].surface->cm.flags.all != blend_only_flags.all && srf_updates[i].surface->cm.flags.all != 0))))) - return true; - } - - if (stream_update && - (((stream_update->src.height != 0 && stream_update->src.width != 0) || - (stream_update->dst.height != 0 && stream_update->dst.width != 0) || - stream_update->integer_scaling_update) || - stream_update->hdr_static_metadata || - stream_update->abm_level || - stream_update->periodic_interrupt || - stream_update->vrr_infopacket || - stream_update->vsc_infopacket || - stream_update->vsp_infopacket || - stream_update->hfvsif_infopacket || - stream_update->vtem_infopacket || - stream_update->adaptive_sync_infopacket || - stream_update->avi_infopacket || - stream_update->dpms_off || - stream_update->allow_freesync || - stream_update->vrr_active_variable || - stream_update->vrr_active_fixed || - stream_update->gamut_remap || - stream_update->output_color_space || - stream_update->dither_option || - stream_update->wb_update || - stream_update->dsc_config || - stream_update->mst_bw_update || - stream_update->func_shaper || - stream_update->lut3d_func || - stream_update->pending_test_pattern || - stream_update->crtc_timing_adjust || - stream_update->scaler_sharpener_update || - stream_update->hw_cursor_req)) - return true; - - return false; -} - -static bool fast_update_only( - const struct dc *dc, - const struct dc_fast_update *fast_update, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - return fast_updates_exist(fast_update, surface_count) - && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); -} - static bool update_planes_and_stream_v2(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { struct dc_state *context; - enum surface_update_type update_type; - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; /* In cases where MPO and split or ODM are used transitions can * cause underflow. Apply stream configuration with minimal pipe @@ -5221,11 +5160,9 @@ static bool update_planes_and_stream_v2(struct dc *dc, */ bool force_minimal_pipe_splitting = 0; bool is_plane_addition = 0; - bool is_fast_update_only; - populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); - is_fast_update_only = fast_update_only(dc, fast_update, srf_updates, - surface_count, stream_update, stream); + struct surface_update_descriptor update_descriptor = {0}; + force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes( dc, stream, @@ -5244,7 +5181,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, surface_count, stream, stream_update, - &update_type, + &update_descriptor, &context)) return false; @@ -5254,7 +5191,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, dc_state_release(context); return false; } - update_type = UPDATE_TYPE_FULL; + elevate_update_type(&update_descriptor, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (dc->hwss.is_pipe_topology_transition_seamless && @@ -5263,13 +5200,13 @@ static bool update_planes_and_stream_v2(struct dc *dc, commit_minimal_transition_state_in_dc_update(dc, context, stream, srf_updates, surface_count); - if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) { + if (update_descriptor.update_type <= UPDATE_TYPE_FAST) { commit_planes_for_stream_fast(dc, srf_updates, surface_count, stream, stream_update, - update_type, + update_descriptor.update_type, context); } else { if (!stream_update && @@ -5285,7 +5222,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, surface_count, stream, stream_update, - update_type, + update_descriptor.update_type, context); } if (dc->current_state != context) @@ -5299,14 +5236,8 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc, struct dc_stream_update *stream_update, enum surface_update_type update_type) { - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; - ASSERT(update_type < UPDATE_TYPE_FULL); - populate_fast_updates(fast_update, srf_updates, surface_count, - stream_update); - if (fast_update_only(dc, fast_update, srf_updates, surface_count, - stream_update, stream) && - !dc->check_config.enable_legacy_fast_update) + if (update_type <= UPDATE_TYPE_FAST) commit_planes_for_stream_fast(dc, srf_updates, surface_count, @@ -5397,7 +5328,7 @@ static bool update_planes_and_stream_v3(struct dc *dc, struct dc_stream_update *stream_update) { struct dc_state *new_context; - enum surface_update_type update_type; + struct surface_update_descriptor update_descriptor = {0}; /* * When this function returns true and new_context is not equal to @@ -5409,22 +5340,26 @@ static bool update_planes_and_stream_v3(struct dc *dc, * replaced by a newer context. Refer to the use of * swap_and_free_current_context below. */ - if (!update_planes_and_stream_state(dc, srf_updates, surface_count, - stream, stream_update, &update_type, + if (!update_planes_and_stream_state(dc, + srf_updates, + surface_count, + stream, + stream_update, + &update_descriptor, &new_context)) return false; if (new_context == dc->current_state) { commit_planes_and_stream_update_on_current_context(dc, srf_updates, surface_count, stream, - stream_update, update_type); + stream_update, update_descriptor.update_type); if (dc->check_config.transition_countdown_to_steady_state) dc->check_config.transition_countdown_to_steady_state--; } else { commit_planes_and_stream_update_with_new_context(dc, srf_updates, surface_count, stream, - stream_update, update_type, new_context); + stream_update, update_descriptor.update_type, new_context); } return true; @@ -7198,7 +7133,7 @@ struct dc_update_scratch_space { struct dc_stream_update *stream_update; bool update_v3; bool do_clear_update_flags; - enum surface_update_type update_type; + struct surface_update_descriptor update_descriptor; struct dc_state *new_context; enum update_v3_flow flow; struct dc_state *backup_context; @@ -7281,45 +7216,28 @@ static bool update_planes_and_stream_prepare_v3( ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID); dc_exit_ips_for_hw_access(scratch->dc); - /* HWSS path determination needs to be done prior to updating the surface and stream states. */ - struct dc_fast_update fast_update[MAX_SURFACES] = { 0 }; - - populate_fast_updates(fast_update, - scratch->surface_updates, - scratch->surface_count, - scratch->stream_update); - - const bool is_hwss_fast_path_only = - fast_update_only(scratch->dc, - fast_update, - scratch->surface_updates, - scratch->surface_count, - scratch->stream_update, - scratch->stream) && - !scratch->dc->check_config.enable_legacy_fast_update; - if (!update_planes_and_stream_state( scratch->dc, scratch->surface_updates, scratch->surface_count, scratch->stream, scratch->stream_update, - &scratch->update_type, + &scratch->update_descriptor, &scratch->new_context )) { return false; } if (scratch->new_context == scratch->dc->current_state) { - ASSERT(scratch->update_type < UPDATE_TYPE_FULL); + ASSERT(scratch->update_descriptor.update_type < UPDATE_TYPE_FULL); - scratch->flow = is_hwss_fast_path_only + scratch->flow = scratch->update_descriptor.update_type <= UPDATE_TYPE_FAST ? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST : UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL; return true; } - ASSERT(scratch->update_type >= UPDATE_TYPE_FULL); + ASSERT(scratch->update_descriptor.update_type >= UPDATE_TYPE_FULL); const bool seamless = scratch->dc->hwss.is_pipe_topology_transition_seamless( scratch->dc, @@ -7392,7 +7310,7 @@ static void update_planes_and_stream_execute_v3_commit( intermediate_update ? scratch->intermediate_count : scratch->surface_count, scratch->stream, use_stream_update ? scratch->stream_update : NULL, - intermediate_context ? UPDATE_TYPE_FULL : scratch->update_type, + intermediate_context ? UPDATE_TYPE_FULL : scratch->update_descriptor.update_type, // `dc->current_state` only used in `NO_NEW_CONTEXT`, where it is equal to `new_context` intermediate_context ? scratch->intermediate_context : scratch->new_context ); @@ -7410,7 +7328,7 @@ static void update_planes_and_stream_execute_v3( scratch->surface_count, scratch->stream, scratch->stream_update, - scratch->update_type, + scratch->update_descriptor.update_type, scratch->new_context ); break; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9e0f53a82c83f..d682b32c4bd86 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -467,6 +467,7 @@ struct dc_static_screen_params { */ enum surface_update_type { + UPDATE_TYPE_ADDR_ONLY, /* only surface address is being updated, no other programming needed */ UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ UPDATE_TYPE_FULL, /* may need to shuffle resources */ @@ -1883,18 +1884,6 @@ struct dc_scaling_info { struct scaling_taps scaling_quality; }; -struct dc_fast_update { - const struct dc_flip_addrs *flip_addr; - const struct dc_gamma *gamma; - const struct colorspace_transform *gamut_remap_matrix; - const struct dc_csc_transform *input_csc_color_matrix; - const struct fixed31_32 *coeff_reduction_factor; - struct dc_transfer_func *out_transfer_func; - struct dc_csc_transform *output_csc_transform; - const struct dc_csc_transform *cursor_csc_color_matrix; - struct cm_hist_control *cm_hist_control; -}; - struct dc_surface_update { struct dc_plane_state *surface; @@ -2033,12 +2022,7 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); void get_audio_check(struct audio_info *aud_modes, struct audio_check *aud_chk); -bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); -void populate_fast_updates(struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_update *stream_update); -/* + /* * Set up streams and links associated to drive sinks * The streams parameter is an absolute set of all active streams. * From 28972b02292d8b3ca0625e9ecf7c1b4fac73ea15 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 18 Mar 2026 13:48:30 +0800 Subject: [PATCH 1993/2070] drm/amd/pm: Skip redundant UCLK restore in smu_v13_0_6 Only reapply UCLK soft limits during PP_OD_RESTORE_DEFAULT when the current max differs from the DPM table max. This avoids redundant SMC updates and prevents -EINVAL on restore when no change is needed. Fixes: b7a900344546 ("drm/amd/pm: Allow setting max UCLK on SMU v13.0.6") Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 63bcef2b326ed..977f4a108411b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2283,6 +2283,7 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; uint32_t min_clk; uint32_t max_clk; @@ -2382,14 +2383,16 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, if (ret) return ret; - min_clk = SMU_DPM_TABLE_MIN( - &dpm_context->dpm_tables.uclk_table); - max_clk = SMU_DPM_TABLE_MAX( - &dpm_context->dpm_tables.uclk_table); - ret = smu_v13_0_6_set_soft_freq_limited_range( - smu, SMU_UCLK, min_clk, max_clk, false); - if (ret) - return ret; + if (SMU_DPM_TABLE_MAX(uclk_table) != + pstate_table->uclk_pstate.curr.max) { + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, + SMU_UCLK, min_clk, + max_clk, false); + if (ret) + return ret; + } smu_v13_0_reset_custom_level(smu); } break; From 731fa11c90f172c783e3ce55f59464cece1db6ac Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 18 Mar 2026 13:52:57 +0800 Subject: [PATCH 1994/2070] drm/amd/pm: Return -EOPNOTSUPP for unsupported OD_MCLK on smu_v13_0_6 When SET_UCLK_MAX capability is absent, return -EOPNOTSUPP from smu_v13_0_6_emit_clk_levels() for OD_MCLK instead of 0. This makes unsupported OD_MCLK reporting consistent with other clock types and allows callers to skip the entry cleanly. Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 977f4a108411b..b9cf6f9166c16 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1552,7 +1552,7 @@ static int smu_v13_0_6_emit_clk_levels(struct smu_context *smu, break; case SMU_OD_MCLK: if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX))) - return 0; + return -EOPNOTSUPP; size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", From 9fa17506b6f3e759f834c07e03ed922ece5a102e Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 13 Mar 2026 13:39:21 +0800 Subject: [PATCH 1995/2070] drm/amd/pm: Add OD_FCLK interface Add OD_FCLK interface to set customa fclk max v2: Merge patch1 & 3, check EOPNOTSUPP for all clks (Lijo) v3: Remove redundant check (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++ drivers/gpu/drm/amd/pm/amdgpu_pm.c | 18 +++++++++++------- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 1 + 4 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index e4c0cfd7fde43..f5e32d3ca1cbb 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -119,6 +119,7 @@ enum pp_clock_type { PP_ISPXCLK, OD_SCLK, OD_MCLK, + OD_FCLK, OD_VDDC_CURVE, OD_RANGE, OD_VDDGFX_OFFSET, @@ -208,6 +209,7 @@ enum { enum PP_OD_DPM_TABLE_COMMAND { PP_OD_EDIT_SCLK_VDDC_TABLE, PP_OD_EDIT_MCLK_VDDC_TABLE, + PP_OD_EDIT_FCLK_TABLE, PP_OD_EDIT_CCLK_VDDC_TABLE, PP_OD_EDIT_VDDC_CURVE, PP_OD_RESTORE_DEFAULT_TABLE, diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 73b9ad7e8bbce..74d29075765a6 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -680,6 +680,8 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, * - minimum(not available for Vega20 and Navi1x) and maximum memory * clock labeled OD_MCLK * + * - minimum and maximum fabric clock labeled OD_FCLK (SMU13) + * * - three points labeled OD_VDDC_CURVE. * They can be used to calibrate the sclk voltage curve. This is * available for Vega20 and NV1X. @@ -715,10 +717,11 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, * - First select manual using power_dpm_force_performance_level * * - For clock frequency setting, enter a new value by writing a - * string that contains "s/m index clock" to the file. The index + * string that contains "s/m/f index clock" to the file. The index * should be 0 if to set minimum clock. And 1 if to set maximum * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. - * "m 1 800" will update maximum mclk to be 800Mhz. For core + * "m 1 800" will update maximum mclk to be 800Mhz. "f 1 1600" will + * update maximum fabric clock to be 1600Mhz. For core * clocks on VanGogh, the string contains "p core index clock". * E.g., "p 2 0 800" would set the minimum core clock on core * 2 to 800Mhz. @@ -768,6 +771,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, type = PP_OD_EDIT_CCLK_VDDC_TABLE; else if (*buf == 'm') type = PP_OD_EDIT_MCLK_VDDC_TABLE; + else if (*buf == 'f') + type = PP_OD_EDIT_FCLK_TABLE; else if (*buf == 'r') type = PP_OD_RESTORE_DEFAULT_TABLE; else if (*buf == 'c') @@ -843,9 +848,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, struct amdgpu_device *adev = drm_to_adev(ddev); int size = 0; int ret; - enum pp_clock_type od_clocks[6] = { + enum pp_clock_type od_clocks[] = { OD_SCLK, OD_MCLK, + OD_FCLK, OD_VDDC_CURVE, OD_RANGE, OD_VDDGFX_OFFSET, @@ -857,10 +863,8 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, if (ret) return ret; - for (clk_index = 0 ; clk_index < 6 ; clk_index++) { - ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); - if (ret) - break; + for (clk_index = 0 ; clk_index < ARRAY_SIZE(od_clocks) ; clk_index++) { + amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); } if (size == 0) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 8b39694608fee..bebd49abc8d89 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3056,6 +3056,8 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) clk_type = SMU_OD_SCLK; break; case OD_MCLK: clk_type = SMU_OD_MCLK; break; + case OD_FCLK: + clk_type = SMU_OD_FCLK; break; case OD_VDDC_CURVE: clk_type = SMU_OD_VDDC_CURVE; break; case OD_RANGE: diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index a4e283a3a1c9b..b07dc7fd9b019 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -331,6 +331,7 @@ enum smu_clk_type { SMU_OD_CCLK, SMU_OD_SCLK, SMU_OD_MCLK, + SMU_OD_FCLK, SMU_OD_VDDC_CURVE, SMU_OD_RANGE, SMU_OD_VDDGFX_OFFSET, From 927ee152cb3e48c9a1c682f24e3fc660ef2124f6 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 13 Mar 2026 17:11:03 +0800 Subject: [PATCH 1996/2070] drm/amd/pm: Add custom fclk setting support Add custom fclk setting support for smu_v13_x_x v2: Move uclk fix to separate patch, return EOPNOTSUPP in case of dpm disabled (Lijo) v3: remove dpm check for filling fclk pstate table (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 82 ++++++++++++++++++- 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 5f6f7d2d44e4e..99b8aae1bede1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -2467,4 +2467,6 @@ void smu_v13_0_reset_custom_level(struct smu_context *smu) pstate_table->uclk_pstate.custom.max = 0; pstate_table->gfxclk_pstate.custom.min = 0; pstate_table->gfxclk_pstate.custom.max = 0; + pstate_table->fclk_pstate.custom.min = 0; + pstate_table->fclk_pstate.custom.max = 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index b9cf6f9166c16..32b1081a734ea 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1357,6 +1357,7 @@ static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu) struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); @@ -1374,6 +1375,12 @@ static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu) pstate_table->socclk_pstate.curr.min = SMU_DPM_TABLE_MIN(soc_table); pstate_table->socclk_pstate.curr.max = SMU_DPM_TABLE_MAX(soc_table); + pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table); + pstate_table->fclk_pstate.curr.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.curr.max = SMU_DPM_TABLE_MAX(fclk_table); + pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table); + if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL && mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL && soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) { @@ -1559,7 +1566,15 @@ static int smu_v13_0_6_emit_clk_levels(struct smu_context *smu, pstate_table->uclk_pstate.curr.min, pstate_table->uclk_pstate.curr.max); break; + case SMU_OD_FCLK: + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) + return -EOPNOTSUPP; + size += sysfs_emit_at(buf, size, "%s:\n", "OD_FCLK"); + size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", + pstate_table->fclk_pstate.curr.min, + pstate_table->fclk_pstate.curr.max); + break; case SMU_SCLK: case SMU_GFXCLK: single_dpm_table = &(dpm_context->dpm_tables.gfx_table); @@ -2201,7 +2216,7 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, int ret = 0; if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK && - clk_type != SMU_UCLK) + clk_type != SMU_UCLK && clk_type != SMU_FCLK) return -EINVAL; if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && @@ -2242,6 +2257,15 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, pstate_table->uclk_pstate.curr.max = max; } + if (clk_type == SMU_FCLK) { + if (max == pstate_table->fclk_pstate.curr.max) + return 0; + + ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_FCLK, 0, max, false); + if (!ret) + pstate_table->fclk_pstate.curr.max = max; + } + return ret; } @@ -2284,6 +2308,7 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; uint32_t min_clk; uint32_t max_clk; @@ -2364,6 +2389,40 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, pstate_table->uclk_pstate.custom.max = input[1]; } break; + case PP_OD_EDIT_FCLK_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + if (!smu_cmn_feature_is_enabled(smu, + SMU_FEATURE_DPM_FCLK_BIT)) { + dev_warn(smu->adev->dev, + "FCLK limits setting not supported!\n"); + return -EOPNOTSUPP; + } + + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table); + if (input[0] == 0) { + dev_info(smu->adev->dev, + "Setting min FCLK level is not supported\n"); + return -EOPNOTSUPP; + } else if (input[0] == 1) { + if (input[1] > max_clk) { + dev_warn(smu->adev->dev, + "Maximum FCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); + pstate_table->fclk_pstate.custom.max = + pstate_table->fclk_pstate.curr.max; + return -EINVAL; + } + + pstate_table->fclk_pstate.custom.max = input[1]; + } else { + return -EINVAL; + } + break; case PP_OD_RESTORE_DEFAULT_TABLE: if (size != 0) { @@ -2393,6 +2452,17 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, if (ret) return ret; } + + if (SMU_DPM_TABLE_MAX(fclk_table) != + pstate_table->fclk_pstate.curr.max) { + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table); + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.fclk_table); + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, + SMU_FCLK, min_clk, + max_clk, false); + if (ret) + return ret; + } smu_v13_0_reset_custom_level(smu); } break; @@ -2419,6 +2489,16 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, if (ret) return ret; + if (pstate_table->fclk_pstate.custom.max) { + min_clk = pstate_table->fclk_pstate.curr.min; + max_clk = pstate_table->fclk_pstate.custom.max; + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, + SMU_FCLK, min_clk, + max_clk, false); + if (ret) + return ret; + } + if (!pstate_table->uclk_pstate.custom.max) return 0; From 8f1a42d44f9d44048a638220e134868fc606163d Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 20 Mar 2026 17:29:01 +0530 Subject: [PATCH 1997/2070] drm/amdgpu/userq: cleanup amdgpu_userq_get/put where not needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_userq_put/get are not needed in case we already holding the userq_mutex and reference is valid already from queue create time or from signal ioctl. These additional get/put could be a potential reason for deadlock in case the ref count reaches zero and destroy is called which again try to take the userq_mutex. Due to the above change we avoid deadlock between suspend/restore calling destroy queues trying to take userq_mutex again. Cc: Prike Liang Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 5f4c044199a83..e3f9b6618371f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1004,15 +1004,11 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) /* Resume all the queues for this process */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { - queue = amdgpu_userq_get(uq_mgr, queue_id); - if (!queue) - continue; if (!amdgpu_userq_buffer_vas_mapped(queue)) { drm_file_err(uq_mgr->file, "trying restore queue without va mapping\n"); queue->state = AMDGPU_USERQ_STATE_INVALID_VA; - amdgpu_userq_put(queue); continue; } @@ -1020,7 +1016,6 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) if (r) ret = r; - amdgpu_userq_put(queue); } if (ret) @@ -1270,13 +1265,9 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) amdgpu_userq_detect_and_reset_queues(uq_mgr); /* Try to unmap all the queues in this process ctx */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { - queue = amdgpu_userq_get(uq_mgr, queue_id); - if (!queue) - continue; r = amdgpu_userq_preempt_helper(queue); if (r) ret = r; - amdgpu_userq_put(queue); } if (ret) @@ -1309,24 +1300,18 @@ amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) int ret; xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { - queue = amdgpu_userq_get(uq_mgr, queue_id); - if (!queue) - continue; - struct dma_fence *f = queue->last_fence; - if (!f || dma_fence_is_signaled(f)) { - amdgpu_userq_put(queue); + if (!f || dma_fence_is_signaled(f)) continue; - } + ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100)); if (ret <= 0) { drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", f->context, f->seqno); - amdgpu_userq_put(queue); + return -ETIMEDOUT; } - amdgpu_userq_put(queue); } return 0; From cffaced868ac8a06dc4341e5e1df48e9a22c112e Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 3 Nov 2025 13:39:38 +0800 Subject: [PATCH 1998/2070] drm/amd/pm: Add initial support for smu v15_0_8 smu v15_0_8 is the new generation of smu ip block v2: Squash in rebase changes (Alex) v3: Squash in fw version check changes (Alex) Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 15 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 6 + drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile | 2 +- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 81 ++- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 483 ++++++++++++++++++ .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h | 28 + 7 files changed, 564 insertions(+), 52 deletions(-) create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index bebd49abc8d89..397dbc6e5686c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -47,6 +47,7 @@ #include "smu_v14_0_0_ppt.h" #include "smu_v14_0_2_ppt.h" #include "smu_v15_0_0_ppt.h" +#include "smu_v15_0_8_ppt.h" #include "amd_pcie.h" /* diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index b07dc7fd9b019..8b9c96d8a24b4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -299,7 +299,12 @@ __SMU_DUMMY_MAP(AllowZstates), \ __SMU_DUMMY_MAP(GetSmartShiftStatus), \ __SMU_DUMMY_MAP(EnableLSdma), \ - __SMU_DUMMY_MAP(DisableLSdma), + __SMU_DUMMY_MAP(DisableLSdma), \ + __SMU_DUMMY_MAP(InitializeGfx), \ + __SMU_DUMMY_MAP(SetSoftMaxFclk), \ + __SMU_DUMMY_MAP(SetSoftMaxGl2clk), \ + __SMU_DUMMY_MAP(SetSoftMinGl2clk), \ + __SMU_DUMMY_MAP(GetSystemMetricsVersion), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type @@ -480,6 +485,14 @@ enum smu_clk_type { __SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \ __SMU_DUMMY_MAP(FAN_ABNORMAL), \ __SMU_DUMMY_MAP(PIT), \ + __SMU_DUMMY_MAP(DS_DMABECLK), \ + __SMU_DUMMY_MAP(DS_MPIFOECLK), \ + __SMU_DUMMY_MAP(DS_MPRASCLK), \ + __SMU_DUMMY_MAP(DS_MPNHTCLK), \ + __SMU_DUMMY_MAP(DS_FIOCLK), \ + __SMU_DUMMY_MAP(DS_DXIOCLK), \ + __SMU_DUMMY_MAP(DS_GL2CLK), \ + __SMU_DUMMY_MAP(DPM_GL2CLK), \ __SMU_DUMMY_MAP(HROM_EN), #undef __SMU_DUMMY_MAP diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index 09743ccd0d15c..95c77e926e1fe 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -41,6 +41,10 @@ #define smnMP1_FIRMWARE_FLAGS 0x3010024 #define smnMP1_PUB_CTRL 0x3010d10 +#define SMU15_DRIVER_IF_VERSION_SMU_V15_0_8 0x007D0000 + +#define FEATURE_MASK(feature) (1ULL << feature) + #define MAX_DPM_LEVELS 16 #define MAX_PCIE_CONF 3 @@ -104,6 +108,7 @@ struct smu_15_0_dpm_context { struct smu_15_0_dpm_tables dpm_tables; uint32_t workload_policy_mask; uint32_t dcef_min_ds_clk; + uint64_t caps; }; enum smu_15_0_power_state { @@ -118,6 +123,7 @@ struct smu_15_0_power_context { uint32_t power_source; uint8_t in_power_limit_boost_mode; enum smu_15_0_power_state power_state; + atomic_t throttle_status; }; #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile index 7f59a0aabdeb6..fa083ad46c0fd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile @@ -23,7 +23,7 @@ # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -SMU15_MGR = smu_v15_0.o smu_v15_0_0_ppt.o +SMU15_MGR = smu_v15_0.o smu_v15_0_0_ppt.o smu_v15_0_8_ppt.o AMD_SWSMU_SMU15MGR = $(addprefix $(AMD_SWSMU_PATH)/smu15/,$(SMU15_MGR)) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index 478ee87af51f3..51d1f5d42ad31 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -590,71 +590,52 @@ int smu_v15_0_notify_memory_pool_location(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *memory_pool = &smu_table->memory_pool; - int ret = 0; - uint64_t address; - uint32_t address_low, address_high; + struct smu_msg_args args = { + .msg = SMU_MSG_DramLogSetDramAddr, + .num_args = 3, + .num_out_args = 0, + }; if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) - return ret; - - address = memory_pool->mc_address; - address_high = (uint32_t)upper_32_bits(address); - address_low = (uint32_t)lower_32_bits(address); + return 0; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, - address_high, NULL); - if (ret) - return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, - address_low, NULL); - if (ret) - return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, - (uint32_t)memory_pool->size, NULL); - if (ret) - return ret; + /* SMU_MSG_DramLogSetDramAddr: ARG0=low, ARG1=high, ARG2=size */ + args.args[0] = lower_32_bits(memory_pool->mc_address); + args.args[1] = upper_32_bits(memory_pool->mc_address); + args.args[2] = (u32)memory_pool->size; - return ret; + return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); } int smu_v15_0_set_driver_table_location(struct smu_context *smu) { struct smu_table *driver_table = &smu->smu_table.driver_table; - int ret = 0; + struct smu_msg_args args = { + .msg = SMU_MSG_SetDriverDramAddrHigh, + .num_args = 2, + .num_out_args = 0, + }; - if (driver_table->mc_address) { - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetDriverDramAddrHigh, - upper_32_bits(driver_table->mc_address), - NULL); - if (!ret) - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetDriverDramAddrLow, - lower_32_bits(driver_table->mc_address), - NULL); - } + args.args[0] = lower_32_bits(driver_table->mc_address); + args.args[1] = upper_32_bits(driver_table->mc_address); - return ret; + return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); } int smu_v15_0_set_tool_table_location(struct smu_context *smu) { - int ret = 0; struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; + struct smu_msg_args args = { + .msg = SMU_MSG_SetToolsDramAddrHigh, + .num_args = 2, + .num_out_args = 0, + }; - if (tool_table->mc_address) { - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetToolsDramAddrHigh, - upper_32_bits(tool_table->mc_address), - NULL); - if (!ret) - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetToolsDramAddrLow, - lower_32_bits(tool_table->mc_address), - NULL); - } + /* SMU_MSG_SetToolsDramAddr: ARG0=low, ARG1=high */ + args.args[0] = lower_32_bits(tool_table->mc_address); + args.args[1] = upper_32_bits(tool_table->mc_address); - return ret; + return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); } int smu_v15_0_set_allowed_mask(struct smu_context *smu) @@ -701,8 +682,7 @@ int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable) return ret; } -int smu_v15_0_system_features_control(struct smu_context *smu, - bool en) +int smu_v15_0_system_features_control(struct smu_context *smu, bool en) { return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : SMU_MSG_DisableAllSmuFeatures), NULL); @@ -906,7 +886,8 @@ static int smu_v15_0_wait_for_reset_complete(struct smu_context *smu, return ret; } -int smu_v15_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, +int smu_v15_0_wait_for_event(struct smu_context *smu, + enum smu_event_type event, uint64_t event_arg) { int ret = -EINVAL; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c new file mode 100644 index 0000000000000..c4da0cdc1222a --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -0,0 +1,483 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#define SWSMU_CODE_LAYER_L2 + +#include +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "smu_v15_0_8_pmfw.h" +#include "smu15_driver_if_v15_0_8.h" +#include "smu_v15_0_8_ppsmc.h" +#include "smu_v15_0_8_ppt.h" +#include +#include "smu_cmn.h" +#include "mp/mp_15_0_8_offset.h" +#include "mp/mp_15_0_8_sh_mask.h" +#include "smu_v15_0.h" + +#undef MP1_Public + +/* address block */ +#define MP1_Public 0x03b00000 +#define smnMP1_FIRMWARE_FLAGS_15_0_8 0x3010024 +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) + +#define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature) \ + [smu_feature] = { 1, (smu_15_0_8_feature) } + +#define FEATURE_MASK(feature) (1ULL << feature) + +static const struct smu_feature_bits smu_v15_0_8_dpm_features = { + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_ID_DATA_CALCULATION), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_GFXCLK), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_UCLK), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_FCLK), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_GL2CLK) } +}; + +static const struct cmn2asic_msg_mapping smu_v15_0_8_message_map[SMU_MSG_MAX_COUNT] = { + MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), + MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), + MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), + MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), + MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1), + MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1), + MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), + MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddr, 1), + MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddr, 0), + MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), + MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), + MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), + MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), + MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), + MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), + MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), + MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1), + MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0), + MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI), + MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI), + MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0), + MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI), + MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI), + MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0), + MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0), + MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), + MSG_MAP(GetRASTableVersion, PPSMC_MSG_GetRasTableVersion, 0), + MSG_MAP(SetTimestamp, PPSMC_MSG_SetTimestamp, 0), + MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0), + MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0), + MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0), + MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), + MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), + MSG_MAP(GetSystemMetricsVersion, PPSMC_MSG_GetSystemMetricsVersion, 0), + MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), + MSG_MAP(SetFastPptLimit, PPSMC_MSG_SetFastPptLimit, 0), + MSG_MAP(GetFastPptLimit, PPSMC_MSG_GetFastPptLimit, 0), + MSG_MAP(SetSoftMinGl2clk, PPSMC_MSG_SetSoftMinGl2clk, 0), + MSG_MAP(SetSoftMaxGl2clk, PPSMC_MSG_SetSoftMaxGl2clk, 0), + MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), + MSG_MAP(SetSoftMaxFclk, PPSMC_MSG_SetSoftMaxFclk, 0), +}; + +/* TODO: Update the clk map once enum PPCLK is updated in smu15_driver_if_v15_0_8.h */ +static struct cmn2asic_mapping smu_v15_0_8_clk_map[SMU_CLK_COUNT] = { + CLK_MAP(UCLK, PPCLK_UCLK), +}; + +static const struct cmn2asic_mapping smu_v15_0_8_feature_mask_map[SMU_FEATURE_COUNT] = { + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_ID_DATA_CALCULATION), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_ID_DPM_GFXCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_ID_DPM_UCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_ID_DPM_FCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_GL2CLK_BIT, FEATURE_ID_DPM_GL2CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_ID_DS_GFXCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_ID_DS_SOCCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_ID_DS_LCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_ID_DS_FCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_DMABECLK_BIT, FEATURE_ID_DS_DMABECLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPIFOECLK_BIT, FEATURE_ID_DS_MPIFOECLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPRASCLK_BIT, FEATURE_ID_DS_MPRASCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPNHTCLK_BIT, FEATURE_ID_DS_MPNHTCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_FIOCLK_BIT, FEATURE_ID_DS_FIOCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_DXIOCLK_BIT, FEATURE_ID_DS_DXIOCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_GL2CLK_BIT, FEATURE_ID_DS_GL2CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_ID_PPT), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_ID_TDC), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_ID_SMU_CG), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_ID_FW_CTF), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_ID_THERMAL), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, FEATURE_ID_SOC_PCC), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_ID_XGMI_PER_LINK_PWR_DOWN), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_ID_DS_VCN), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_ID_DS_MP1CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_ID_DS_MPIOCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_ID_DS_MP0CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_ID_PIT), +}; + +#define TABLE_PMSTATUSLOG 0 +#define TABLE_SMU_METRICS 1 +#define TABLE_I2C_COMMANDS 2 +#define TABLE_COUNT 3 + +static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { + TAB_MAP(PMSTATUSLOG), + TAB_MAP(SMU_METRICS), + TAB_MAP(I2C_COMMANDS), +}; + +static int smu_v15_0_8_tables_init(struct smu_context *smu) +{ + return 0; +} + +static int smu_v15_0_8_allocate_dpm_context(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + + smu_dpm->dpm_context = + kzalloc(sizeof(struct smu_15_0_dpm_context), GFP_KERNEL); + if (!smu_dpm->dpm_context) + return -ENOMEM; + smu_dpm->dpm_context_size = sizeof(struct smu_15_0_dpm_context); + + smu_dpm->dpm_policies = + kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL); + if (!smu_dpm->dpm_policies) { + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + + return 0; +} + +static int smu_v15_0_8_init_smc_tables(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_v15_0_8_tables_init(smu); + if (ret) + return ret; + + ret = smu_v15_0_8_allocate_dpm_context(smu); + + return ret; +} + +static int smu_v15_0_8_init_allowed_features(struct smu_context *smu) +{ + /* pptable will handle the features to enable */ + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); + + return 0; +} + +static int smu_v15_0_8_set_default_dpm_table(struct smu_context *smu) +{ + return 0; +} + +static int smu_v15_0_8_setup_pptable(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + + /* TODO: PPTable is not available. + * 1) Find an alternate way to get 'PPTable values' here. + * 2) Check if there is SW CTF + */ + table_context->thermal_controller_type = 0; + + return 0; +} + +static int smu_v15_0_8_check_fw_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t mp1_fw_flags; + + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS_15_0_8 & 0xffffffff)); + + if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return 0; + + return -EIO; +} + +static int smu_v15_0_8_irq_process(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_power_context *smu_power = &smu->smu_power; + struct smu_15_0_power_context *power_context = smu_power->power_context; + uint32_t client_id = entry->client_id; + uint32_t ctxid = entry->src_data[0]; + uint32_t src_id = entry->src_id; + uint32_t data; + + if (client_id == SOC_V1_0_IH_CLIENTID_MP1) { + if (src_id == IH_INTERRUPT_ID_TO_DRIVER) { + /* ACK SMUToHost interrupt */ + data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); + /* + * ctxid is used to distinguish different events for SMCToHost + * interrupt. + */ + switch (ctxid) { + case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING: + /* + * Increment the throttle interrupt counter + */ + atomic64_inc(&smu->throttle_int_counter); + + if (!atomic_read(&adev->throttling_logging_enabled)) + return 0; + + /* This uses the new method which fixes the + * incorrect throttling status reporting + * through metrics table. For older FWs, + * it will be ignored. + */ + if (__ratelimit(&adev->throttling_logging_rs)) { + atomic_set( + &power_context->throttle_status, + entry->src_data[1]); + schedule_work(&smu->throttling_logging_work); + } + break; + default: + dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n", + ctxid, client_id); + break; + } + } + } + + return 0; +} + +static int smu_v15_0_8_set_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + uint32_t val = 0; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* For MP1 SW irqs */ + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* For MP1 SW irqs */ + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); + + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + + break; + default: + break; + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs smu_v15_0_8_irq_funcs = { + .set = smu_v15_0_8_set_irq_state, + .process = smu_v15_0_8_irq_process, +}; + +static int smu_v15_0_8_register_irq_handler(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct amdgpu_irq_src *irq_src = &smu->irq_source; + int ret = 0; + + if (amdgpu_sriov_vf(adev)) + return 0; + + irq_src->num_types = 1; + irq_src->funcs = &smu_v15_0_8_irq_funcs; + + ret = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_MP1, + IH_INTERRUPT_ID_TO_DRIVER, + irq_src); + if (ret) + return ret; + + return ret; +} + +static int smu_v15_0_8_notify_unload(struct smu_context *smu) +{ + if (amdgpu_in_reset(smu->adev)) + return 0; + + dev_dbg(smu->adev->dev, "Notify PMFW about driver unload"); + /* Ignore return, just intimate FW that driver is not going to be there */ + smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); + + return 0; +} + + +static int smu_v15_0_8_system_features_control(struct smu_context *smu, + bool enable) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (amdgpu_sriov_vf(adev)) + return 0; + + if (enable) + ret = smu_v15_0_system_features_control(smu, enable); + else + smu_v15_0_8_notify_unload(smu); + + return ret; +} + +/** + * smu_v15_0_8_get_enabled_mask - Get enabled SMU features (128-bit) + * @smu: SMU context + * @feature_mask: feature mask structure + * + * SMU 15 returns all 128 feature bits in a single message via out_args[0..3]. + * For backward compatibility, this function returns only the first 64 bits. + * + * Return: 0 on success, negative errno on failure + */ +static int smu_v15_0_8_get_enabled_mask(struct smu_context *smu, + struct smu_feature_bits *feature_mask) +{ + struct smu_msg_args args = { + .msg = SMU_MSG_GetEnabledSmuFeatures, + .num_args = 0, + .num_out_args = 2, + }; + int ret; + + if (!feature_mask) + return -EINVAL; + + ret = smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + + if (ret) + return ret; + + smu_feature_bits_from_arr32(feature_mask, args.out_args, + SMU_FEATURE_NUM_DEFAULT); + + return 0; +} + +static bool smu_v15_0_8_is_dpm_running(struct smu_context *smu) +{ + int ret = 0; + struct smu_feature_bits feature_enabled; + + ret = smu_v15_0_8_get_enabled_mask(smu, &feature_enabled); + if (ret) + return false; + + return smu_feature_bits_test_mask(&feature_enabled, + smu_v15_0_8_dpm_features.bits); +} + +static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { + .init_allowed_features = smu_v15_0_8_init_allowed_features, + .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, + .is_dpm_running = smu_v15_0_8_is_dpm_running, + .init_smc_tables = smu_v15_0_8_init_smc_tables, + .fini_smc_tables = smu_v15_0_fini_smc_tables, + .init_power = smu_v15_0_init_power, + .fini_power = smu_v15_0_fini_power, + .check_fw_status = smu_v15_0_8_check_fw_status, + .check_fw_version = smu_cmn_check_fw_version, + .set_driver_table_location = smu_v15_0_set_driver_table_location, + .set_tool_table_location = smu_v15_0_set_tool_table_location, + .notify_memory_pool_location = smu_v15_0_notify_memory_pool_location, + .system_features_control = smu_v15_0_8_system_features_control, + .get_enabled_mask = smu_v15_0_8_get_enabled_mask, + .feature_is_enabled = smu_cmn_feature_is_enabled, + .register_irq_handler = smu_v15_0_8_register_irq_handler, + .setup_pptable = smu_v15_0_8_setup_pptable, + .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, + .wait_for_event = smu_v15_0_wait_for_event, +}; + +static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, + const struct cmn2asic_msg_mapping *message_map) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_40); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_41); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_42); + ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_43); + ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_44); + ctl->config.arg_regs[3] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_45); + ctl->config.num_arg_regs = 4; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = message_map; +} + +void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu) +{ + smu->ppt_funcs = &smu_v15_0_8_ppt_funcs; + smu->clock_map = smu_v15_0_8_clk_map; + smu->feature_map = smu_v15_0_8_feature_mask_map; + smu->table_map = smu_v15_0_8_table_map; + smu_v15_0_8_init_msg_ctl(smu, smu_v15_0_8_message_map); + smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0_8; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h new file mode 100644 index 0000000000000..40c410928c966 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -0,0 +1,28 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU_15_0_8_PPT_H__ +#define __SMU_15_0_8_PPT_H__ + +extern void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu); + +#endif From 8c5f96a46daada0b6912550e94088572d11a1205 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 25 Nov 2025 01:19:13 +0800 Subject: [PATCH 1999/2070] drm/amd/pm: Add mode2 support for smu_v15_0_8 Add initial mode2 support for smu_v15_0_8 v2: Move out non smu code, remove pci save/restore logic (Lijo) v3: squash in updated msg (Alex) Signed-off-by: Asad Kamal Reviewed-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index c4da0cdc1222a..b3dc04ea5e713 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -430,6 +430,49 @@ static bool smu_v15_0_8_is_dpm_running(struct smu_context *smu) smu_v15_0_8_dpm_features.bits); } +static int smu_v15_0_8_mode2_reset(struct smu_context *smu) +{ + struct smu_msg_ctl *ctl = &smu->msg_ctl; + struct amdgpu_device *adev = smu->adev; + int timeout = 10; + int ret = 0; + + mutex_lock(&ctl->lock); + + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, + SMU_RESET_MODE_2); + + if (ret) + goto out; + + /* Reset takes a bit longer, wait for 200ms. */ + msleep(200); + + dev_dbg(adev->dev, "wait for reset ack\n"); + do { + ret = smu_msg_wait_response(ctl, 0); + /* Wait a bit more time for getting ACK */ + if (ret == -ETIME) { + --timeout; + usleep_range(500, 1000); + continue; + } + + if (ret) + goto out; + + } while (ret == -ETIME && timeout); + +out: + mutex_unlock(&ctl->lock); + + if (ret) + dev_err(adev->dev, "failed to send mode2 reset, error code %d", + ret); + + return ret; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -450,6 +493,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .setup_pptable = smu_v15_0_8_setup_pptable, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .wait_for_event = smu_v15_0_wait_for_event, + .mode2_reset = smu_v15_0_8_mode2_reset, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, From 8c54a55db3cad68342b6d75ee9216a3bd67db266 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 26 Nov 2025 16:02:41 +0800 Subject: [PATCH 2000/2070] drm/amd/pm: Setup driver pptable for smu 15.0.8 Setup driver pptable and initialize data from static metrics table for smu_v15_0_8 v2: Remove unrelated changes and update description (Lijo) v3: Use ARRAY_SIZE (Lijo) v4: Move structure to header file v5: squash in static metrics support (Asad) Signed-off-by: Yang Wang Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 1 + .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 230 +++++++++++++++++- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h | 30 +++ 4 files changed, 257 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 51a1c8d92f2f5..f08de86bee0e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -708,6 +708,7 @@ enum amdgpu_uid_type { AMDGPU_UID_TYPE_XCD, AMDGPU_UID_TYPE_AID, AMDGPU_UID_TYPE_SOC, + AMDGPU_UID_TYPE_MID, AMDGPU_UID_TYPE_MAX }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index 95c77e926e1fe..06842d38c92bd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -109,6 +109,7 @@ struct smu_15_0_dpm_context { uint32_t workload_policy_mask; uint32_t dcef_min_ds_clk; uint64_t caps; + uint32_t board_volt; }; enum smu_15_0_power_state { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index b3dc04ea5e713..82b09fe7fccd5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -35,6 +35,7 @@ #include "mp/mp_15_0_8_offset.h" #include "mp/mp_15_0_8_sh_mask.h" #include "smu_v15_0.h" +#include "amdgpu_fru_eeprom.h" #undef MP1_Public @@ -51,6 +52,10 @@ #undef pr_info #undef pr_debug +#define SMUQ10_TO_UINT(x) ((x) >> 10) +#define SMUQ10_FRAC(x) ((x) & 0x3ff) +#define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) + #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) #define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature) \ @@ -161,6 +166,35 @@ static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { static int smu_v15_0_8_tables_init(struct smu_context *smu) { + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + int gpu_metrcs_size = sizeof(MetricsTable_t); + void *driver_pptable __free(kfree) = NULL; + void *metrics_table __free(kfree) = NULL; + + SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU15_TOOL_SIZE, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, + gpu_metrcs_size, + PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); + + metrics_table = kzalloc(gpu_metrcs_size, GFP_KERNEL); + if (!metrics_table) + return -ENOMEM; + + smu_table->metrics_time = 0; + + driver_pptable = kzalloc(sizeof(PPTable_t), GFP_KERNEL); + if (!driver_pptable) + return -ENOMEM; + + smu_table->metrics_table = no_free_ptr(metrics_table); + smu_table->driver_pptable = no_free_ptr(driver_pptable); + + mutex_init(&smu_table->metrics_lock); + return 0; } @@ -197,16 +231,35 @@ static int smu_v15_0_8_init_smc_tables(struct smu_context *smu) return ret; } -static int smu_v15_0_8_init_allowed_features(struct smu_context *smu) +static int smu_v15_0_8_tables_fini(struct smu_context *smu) { - /* pptable will handle the features to enable */ - smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); + struct smu_table_context *smu_table = &smu->smu_table; + + mutex_destroy(&smu_table->metrics_lock); return 0; } -static int smu_v15_0_8_set_default_dpm_table(struct smu_context *smu) +static int smu_v15_0_8_fini_smc_tables(struct smu_context *smu) +{ + int ret; + + ret = smu_v15_0_8_tables_fini(smu); + if (ret) + return ret; + + ret = smu_v15_0_fini_smc_tables(smu); + if (ret) + return ret; + + return ret; +} + +static int smu_v15_0_8_init_allowed_features(struct smu_context *smu) { + /* pptable will handle the features to enable */ + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); + return 0; } @@ -238,6 +291,173 @@ static int smu_v15_0_8_check_fw_status(struct smu_context *smu) return -EIO; } +static int smu_v15_0_8_get_static_metrics_table(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + struct smu_table *table = &smu_table->driver_table; + int ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL); + if (ret) { + dev_err(smu->adev->dev, + "Failed to export static metrics table!\n"); + return ret; + } + + amdgpu_hdp_invalidate(smu->adev, NULL); + memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + + return 0; +} + +static int smu_v15_0_8_fru_get_product_info(struct smu_context *smu, + StaticMetricsTable_t *static_metrics) +{ + struct amdgpu_fru_info *fru_info; + struct amdgpu_device *adev = smu->adev; + + if (!adev->fru_info) { + adev->fru_info = kzalloc(sizeof(*adev->fru_info), GFP_KERNEL); + if (!adev->fru_info) + return -ENOMEM; + } + + fru_info = adev->fru_info; + strscpy(fru_info->product_number, static_metrics->ProductInfo.ModelNumber, + sizeof(fru_info->product_number)); + strscpy(fru_info->product_name, static_metrics->ProductInfo.Name, + sizeof(fru_info->product_name)); + strscpy(fru_info->serial, static_metrics->ProductInfo.Serial, + sizeof(fru_info->serial)); + strscpy(fru_info->manufacturer_name, static_metrics->ProductInfo.ManufacturerName, + sizeof(fru_info->manufacturer_name)); + strscpy(fru_info->fru_id, static_metrics->ProductInfo.FruId, + sizeof(fru_info->fru_id)); + + return 0; +} + +static void smu_v15_0_8_init_xgmi_data(struct smu_context *smu, + StaticMetricsTable_t *static_metrics) +{ + uint16_t max_speed; + uint8_t max_width; + + max_width = (uint8_t)static_metrics->MaxXgmiWidth; + max_speed = (uint16_t)static_metrics->MaxXgmiBitrate; + amgpu_xgmi_set_max_speed_width(smu->adev, max_speed, max_width); +} + +static int smu_v15_0_8_set_driver_pptable(struct smu_context *smu) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_table_context *smu_table = &smu->smu_table; + StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int ret, i, n; + uint32_t table_version; + + if (!pptable->init) { + ret = smu_v15_0_8_get_static_metrics_table(smu); + if (ret) + return ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion, + &table_version); + if (ret) + return ret; + smu_table->tables[SMU_TABLE_SMU_METRICS].version = + table_version; + + pptable->MaxSocketPowerLimit = + SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit); + pptable->MaxGfxclkFrequency = + SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency); + pptable->MinGfxclkFrequency = + SMUQ10_ROUND(static_metrics->MinGfxclkFrequency); + pptable->MaxFclkFrequency = + SMUQ10_ROUND(static_metrics->MaxFclkFrequency); + pptable->MinFclkFrequency = + SMUQ10_ROUND(static_metrics->MinFclkFrequency); + pptable->MaxGl2clkFrequency = + SMUQ10_ROUND(static_metrics->MaxGl2clkFrequency); + pptable->MinGl2clkFrequency = + SMUQ10_ROUND(static_metrics->MinGl2clkFrequency); + + for (i = 0; i < ARRAY_SIZE(static_metrics->UclkFrequencyTable); ++i) + pptable->UclkFrequencyTable[i] = + SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]); + + pptable->SocclkFrequency = SMUQ10_ROUND(static_metrics->SocclkFrequency); + pptable->LclkFrequency = SMUQ10_ROUND(static_metrics->LclkFrequency); + pptable->VclkFrequency = SMUQ10_ROUND(static_metrics->VclkFrequency); + pptable->DclkFrequency = SMUQ10_ROUND(static_metrics->DclkFrequency); + + pptable->CTFLimitMID = SMUQ10_ROUND(static_metrics->CTFLimit_MID); + pptable->CTFLimitAID = SMUQ10_ROUND(static_metrics->CTFLimit_AID); + pptable->CTFLimitXCD = SMUQ10_ROUND(static_metrics->CTFLimit_XCD); + pptable->CTFLimitHBM = SMUQ10_ROUND(static_metrics->CTFLimit_HBM); + pptable->ThermalLimitMID = SMUQ10_ROUND(static_metrics->ThermalLimit_MID); + pptable->ThermalLimitAID = SMUQ10_ROUND(static_metrics->ThermalLimit_AID); + pptable->ThermalLimitXCD = SMUQ10_ROUND(static_metrics->ThermalLimit_XCD); + pptable->ThermalLimitHBM = SMUQ10_ROUND(static_metrics->ThermalLimit_HBM); + + /* use MID0 serial number by default */ + pptable->PublicSerialNumberMID = + static_metrics->PublicSerialNumber_MID[0]; + + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC, + 0, pptable->PublicSerialNumberMID); + pptable->PublicSerialNumberAID = + static_metrics->PublicSerialNumber_AID[0]; + pptable->PublicSerialNumberXCD = + static_metrics->PublicSerialNumber_XCD[0]; + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_MID); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_MID, i, + static_metrics->PublicSerialNumber_MID[i]); + } + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_AID); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i, + static_metrics->PublicSerialNumber_AID[i]); + } + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_XCD); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i, + static_metrics->PublicSerialNumber_XCD[i]); + } + + ret = smu_v15_0_8_fru_get_product_info(smu, static_metrics); + if (ret) + return ret; + pptable->PPT1Max = static_metrics->PPT1Max; + pptable->PPT1Min = static_metrics->PPT1Min; + pptable->PPT1Default = static_metrics->PPT1Default; + + if (static_metrics->pldmVersion[0] != 0xFFFFFFFF) + smu->adev->firmware.pldm_version = + static_metrics->pldmVersion[0]; + dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV; + smu_v15_0_8_init_xgmi_data(smu, static_metrics); + pptable->init = true; + } + + return 0; +} + +static int smu_v15_0_8_set_default_dpm_table(struct smu_context *smu) +{ + int ret; + + ret = smu_v15_0_8_set_driver_pptable(smu); + if (ret) + return ret; + + return 0; +} + static int smu_v15_0_8_irq_process(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) @@ -478,7 +698,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, .is_dpm_running = smu_v15_0_8_is_dpm_running, .init_smc_tables = smu_v15_0_8_init_smc_tables, - .fini_smc_tables = smu_v15_0_fini_smc_tables, + .fini_smc_tables = smu_v15_0_8_fini_smc_tables, .init_power = smu_v15_0_init_power, .fini_power = smu_v15_0_fini_power, .check_fw_status = smu_v15_0_8_check_fw_status, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h index 40c410928c966..6c85f23d31116 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -25,4 +25,34 @@ extern void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu); +typedef struct { + uint32_t MaxSocketPowerLimit; + uint32_t MaxGfxclkFrequency; + uint32_t MinGfxclkFrequency; + uint32_t MaxFclkFrequency; + uint32_t MinFclkFrequency; + uint32_t MaxGl2clkFrequency; + uint32_t MinGl2clkFrequency; + uint32_t UclkFrequencyTable[4]; + uint32_t SocclkFrequency; + uint32_t LclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t CTFLimitMID; + uint32_t CTFLimitAID; + uint32_t CTFLimitXCD; + uint32_t CTFLimitHBM; + uint32_t ThermalLimitMID; + uint32_t ThermalLimitAID; + uint32_t ThermalLimitXCD; + uint32_t ThermalLimitHBM; + uint64_t PublicSerialNumberMID; + uint64_t PublicSerialNumberAID; + uint64_t PublicSerialNumberXCD; + uint32_t PPT1Max; + uint32_t PPT1Min; + uint32_t PPT1Default; + bool init; +} PPTable_t; + #endif From da8f3a6b8b601811bf96c8d7a23eb76643180450 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 23 Dec 2025 23:35:32 +0800 Subject: [PATCH 2001/2070] drm/amd/pm: Update dpm table structs for smu_v15_0 Update dpm table structs to use common definitions for smu_15_0 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 47 +++-------- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 79 +++++++++---------- 2 files changed, 49 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index 06842d38c92bd..3c8c086f0f9d8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -45,7 +45,6 @@ #define FEATURE_MASK(feature) (1ULL << feature) -#define MAX_DPM_LEVELS 16 #define MAX_PCIE_CONF 3 #define SMU15_TOOL_SIZE 0x19000 @@ -69,39 +68,19 @@ struct smu_15_0_max_sustainable_clocks { uint32_t soc_clock; }; -struct smu_15_0_dpm_clk_level { - bool enabled; - uint32_t value; -}; - -struct smu_15_0_dpm_table { - uint32_t min; /* MHz */ - uint32_t max; /* MHz */ - uint32_t count; - bool is_fine_grained; - struct smu_15_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; -}; - -struct smu_15_0_pcie_table { - uint8_t pcie_gen[MAX_PCIE_CONF]; - uint8_t pcie_lane[MAX_PCIE_CONF]; - uint16_t clk_freq[MAX_PCIE_CONF]; - uint32_t num_of_link_levels; -}; - struct smu_15_0_dpm_tables { - struct smu_15_0_dpm_table soc_table; - struct smu_15_0_dpm_table gfx_table; - struct smu_15_0_dpm_table uclk_table; - struct smu_15_0_dpm_table eclk_table; - struct smu_15_0_dpm_table vclk_table; - struct smu_15_0_dpm_table dclk_table; - struct smu_15_0_dpm_table dcef_table; - struct smu_15_0_dpm_table pixel_table; - struct smu_15_0_dpm_table display_table; - struct smu_15_0_dpm_table phy_table; - struct smu_15_0_dpm_table fclk_table; - struct smu_15_0_pcie_table pcie_table; + struct smu_dpm_table soc_table; + struct smu_dpm_table gfx_table; + struct smu_dpm_table uclk_table; + struct smu_dpm_table eclk_table; + struct smu_dpm_table vclk_table; + struct smu_dpm_table dclk_table; + struct smu_dpm_table dcef_table; + struct smu_dpm_table pixel_table; + struct smu_dpm_table display_table; + struct smu_dpm_table phy_table; + struct smu_dpm_table fclk_table; + struct smu_pcie_table pcie_table; }; struct smu_15_0_dpm_context { @@ -204,7 +183,7 @@ int smu_v15_0_set_power_source(struct smu_context *smu, int smu_v15_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, - struct smu_15_0_dpm_table *single_dpm_table); + struct smu_dpm_table *single_dpm_table); int smu_v15_0_gfx_ulv_control(struct smu_context *smu, bool enablement); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index 51d1f5d42ad31..a9417cb4e920b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -1059,18 +1059,12 @@ int smu_v15_0_set_performance_level(struct smu_context *smu, { struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_15_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_15_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_15_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; - struct smu_15_0_dpm_table *vclk_table = - &dpm_context->dpm_tables.vclk_table; - struct smu_15_0_dpm_table *dclk_table = - &dpm_context->dpm_tables.dclk_table; - struct smu_15_0_dpm_table *fclk_table = - &dpm_context->dpm_tables.fclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; @@ -1085,34 +1079,34 @@ int smu_v15_0_set_performance_level(struct smu_context *smu, switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: - sclk_min = sclk_max = gfx_table->max; - mclk_min = mclk_max = mem_table->max; - socclk_min = socclk_max = soc_table->max; - vclk_min = vclk_max = vclk_table->max; - dclk_min = dclk_max = dclk_table->max; - fclk_min = fclk_max = fclk_table->max; + sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table); break; case AMD_DPM_FORCED_LEVEL_LOW: - sclk_min = sclk_max = gfx_table->min; - mclk_min = mclk_max = mem_table->min; - socclk_min = socclk_max = soc_table->min; - vclk_min = vclk_max = vclk_table->min; - dclk_min = dclk_max = dclk_table->min; - fclk_min = fclk_max = fclk_table->min; + sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table); break; case AMD_DPM_FORCED_LEVEL_AUTO: - sclk_min = gfx_table->min; - sclk_max = gfx_table->max; - mclk_min = mem_table->min; - mclk_max = mem_table->max; - socclk_min = soc_table->min; - socclk_max = soc_table->max; - vclk_min = vclk_table->min; - vclk_max = vclk_table->max; - dclk_min = dclk_table->min; - dclk_max = dclk_table->max; - fclk_min = fclk_table->min; - fclk_max = fclk_table->max; + sclk_min = SMU_DPM_TABLE_MIN(gfx_table); + sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = SMU_DPM_TABLE_MIN(mem_table); + mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = SMU_DPM_TABLE_MIN(soc_table); + socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = SMU_DPM_TABLE_MIN(vclk_table); + vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = SMU_DPM_TABLE_MIN(dclk_table); + dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = SMU_DPM_TABLE_MIN(fclk_table); + fclk_max = SMU_DPM_TABLE_MAX(fclk_table); auto_level = true; break; case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: @@ -1334,10 +1328,11 @@ static int smu_v15_0_get_fine_grained_status(struct smu_context *smu, int smu_v15_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, - struct smu_15_0_dpm_table *single_dpm_table) + struct smu_dpm_table *single_dpm_table) { int ret = 0; uint32_t clk; + bool is_fine_grained; int i; ret = smu_v15_0_get_dpm_level_count(smu, @@ -1350,12 +1345,15 @@ int smu_v15_0_set_single_dpm_table(struct smu_context *smu, ret = smu_v15_0_get_fine_grained_status(smu, clk_type, - &single_dpm_table->is_fine_grained); + &is_fine_grained); if (ret) { dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); return ret; } + if (is_fine_grained) + single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; + for (i = 0; i < single_dpm_table->count; i++) { ret = smu_v15_0_get_dpm_freq_by_index(smu, clk_type, @@ -1368,11 +1366,6 @@ int smu_v15_0_set_single_dpm_table(struct smu_context *smu, single_dpm_table->dpm_levels[i].value = clk; single_dpm_table->dpm_levels[i].enabled = true; - - if (i == 0) - single_dpm_table->min = clk; - else if (i == single_dpm_table->count - 1) - single_dpm_table->max = clk; } return 0; From 5418674b61aa44e28903d8c175e4355e2e6e0416 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 24 Dec 2025 00:33:49 +0800 Subject: [PATCH 2002/2070] drm/amd/pm: Add default dpm table support for smu 15.0.8 Add default dpm table support for smu 15.0.8 v2: Remove lclk, move pptable check up, add missing clk (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 1 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 1 + .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 211 ++++++++++++++++++ 3 files changed, 213 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 8b9c96d8a24b4..7de3a43489572 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -347,6 +347,7 @@ enum smu_clk_type { SMU_OD_FAN_MINIMUM_PWM, SMU_OD_FAN_ZERO_RPM_ENABLE, SMU_OD_FAN_ZERO_RPM_STOP_TEMP, + SMU_GL2CLK, SMU_CLK_COUNT, }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h index 3c8c086f0f9d8..e6fd8be2cc4a0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h @@ -81,6 +81,7 @@ struct smu_15_0_dpm_tables { struct smu_dpm_table phy_table; struct smu_dpm_table fclk_table; struct smu_pcie_table pcie_table; + struct smu_dpm_table gl2_table; }; struct smu_15_0_dpm_context { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 82b09fe7fccd5..149421b1c6cbf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -263,6 +263,212 @@ static int smu_v15_0_8_init_allowed_features(struct smu_context *smu) return 0; } +static int smu_v15_0_8_get_dpm_ultimate_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min, uint32_t *max) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + struct smu_dpm_table *dpm_table; + uint32_t min_clk = 0, max_clk = 0; + + if (!pptable->init) + return -EINVAL; + + /* Try cached DPM tables first */ + if (dpm_context) { + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + dpm_table = &dpm_context->dpm_tables.uclk_table; + break; + case SMU_GFXCLK: + case SMU_SCLK: + dpm_table = &dpm_context->dpm_tables.gfx_table; + break; + case SMU_SOCCLK: + dpm_table = &dpm_context->dpm_tables.soc_table; + break; + case SMU_FCLK: + dpm_table = &dpm_context->dpm_tables.fclk_table; + break; + case SMU_GL2CLK: + dpm_table = &dpm_context->dpm_tables.gl2_table; + break; + case SMU_VCLK: + dpm_table = &dpm_context->dpm_tables.vclk_table; + break; + case SMU_DCLK: + dpm_table = &dpm_context->dpm_tables.dclk_table; + break; + default: + dpm_table = NULL; + break; + } + + if (dpm_table && dpm_table->count > 0) { + min_clk = SMU_DPM_TABLE_MIN(dpm_table); + max_clk = SMU_DPM_TABLE_MAX(dpm_table); + + if (min_clk && max_clk) { + if (min) + *min = min_clk; + if (max) + *max = max_clk; + return 0; + } + } + } + + /* Fall back to pptable */ + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + min_clk = pptable->MinGfxclkFrequency; + max_clk = pptable->MaxGfxclkFrequency; + break; + case SMU_FCLK: + min_clk = pptable->MinFclkFrequency; + max_clk = pptable->MaxFclkFrequency; + break; + case SMU_GL2CLK: + min_clk = pptable->MinGl2clkFrequency; + max_clk = pptable->MaxGl2clkFrequency; + break; + case SMU_MCLK: + case SMU_UCLK: + min_clk = pptable->UclkFrequencyTable[0]; + max_clk = pptable->UclkFrequencyTable[ARRAY_SIZE(pptable->UclkFrequencyTable) - 1]; + break; + case SMU_SOCCLK: + min_clk = pptable->SocclkFrequency; + max_clk = pptable->SocclkFrequency; + break; + case SMU_VCLK: + min_clk = pptable->VclkFrequency; + max_clk = pptable->VclkFrequency; + break; + case SMU_DCLK: + min_clk = pptable->DclkFrequency; + max_clk = pptable->DclkFrequency; + break; + default: + return -EINVAL; + } + + if (min) + *min = min_clk; + if (max) + *max = max_clk; + + return 0; +} + +static int smu_v15_0_8_set_dpm_table(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_dpm_table *dpm_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int i, ret; + uint32_t gfxclkmin, gfxclkmax; + + /* gfxclk dpm table setup - fine-grained */ + dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { + ret = smu_v15_0_8_get_dpm_ultimate_freq(smu, SMU_GFXCLK, + &gfxclkmin, &gfxclkmax); + if (ret) + return ret; + + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = gfxclkmin; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = gfxclkmax; + dpm_table->dpm_levels[1].enabled = true; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + } + + /* fclk dpm table setup - fine-grained */ + dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = pptable->MinFclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = pptable->MaxFclkFrequency; + dpm_table->dpm_levels[1].enabled = true; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->MinFclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + } + + /* gl2clk dpm table setup - fine-grained */ + dpm_table = &dpm_context->dpm_tables.gl2_table; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GL2CLK_BIT)) { + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = pptable->MinGl2clkFrequency; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = pptable->MaxGl2clkFrequency; + dpm_table->dpm_levels[1].enabled = true; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->MinGl2clkFrequency; + dpm_table->dpm_levels[0].enabled = true; + } + + /* uclk dpm table setup - discrete levels */ + dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; + dpm_table->flags = 0; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + dpm_table->count = ARRAY_SIZE(pptable->UclkFrequencyTable); + for (i = 0; i < dpm_table->count; ++i) { + dpm_table->dpm_levels[i].value = pptable->UclkFrequencyTable[i]; + dpm_table->dpm_levels[i].enabled = true; + } + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->UclkFrequencyTable[0]; + dpm_table->dpm_levels[0].enabled = true; + } + + /* socclk dpm table setup - single boot-time value */ + dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; + dpm_table->flags = 0; + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->SocclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + + /* vclk dpm table setup - single boot-time value */ + dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = SMU_VCLK; + dpm_table->flags = 0; + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->VclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + + /* dclk dpm table setup - single boot-time value */ + dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = SMU_DCLK; + dpm_table->flags = 0; + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->DclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + + return 0; +} + static int smu_v15_0_8_setup_pptable(struct smu_context *smu) { struct smu_table_context *table_context = &smu->smu_table; @@ -455,6 +661,10 @@ static int smu_v15_0_8_set_default_dpm_table(struct smu_context *smu) if (ret) return ret; + ret = smu_v15_0_8_set_dpm_table(smu); + if (ret) + return ret; + return 0; } @@ -714,6 +924,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .wait_for_event = smu_v15_0_wait_for_event, .mode2_reset = smu_v15_0_8_mode2_reset, + .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, From f29c32ecd82afd7f2726eb0b3b208f27b990d0d1 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 26 Nov 2025 18:41:34 +0800 Subject: [PATCH 2003/2070] drm/amd/pm: Add get_pm_metrics support for smu 15.0.8 export .get_pm_metrics interface for smu 15.0.8. v2: Make tmo as unsigned (Lijo) Signed-off-by: Yang Wang Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 149421b1c6cbf..60a43ce5648a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -263,6 +263,37 @@ static int smu_v15_0_8_init_allowed_features(struct smu_context *smu) return 0; } +static int smu_v15_0_8_get_metrics_table_internal(struct smu_context *smu, uint32_t tmo, void *data) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + struct smu_table *table = &smu_table->driver_table; + struct amdgpu_device *adev = smu->adev; + int ret; + + mutex_lock(&smu_table->metrics_lock); + + if (!tmo || !smu_table->metrics_time || + time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(tmo))) { + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL); + if (ret) { + dev_info(adev->dev, + "Failed to export SMU metrics table!\n"); + return ret; + } + + amdgpu_device_invalidate_hdp(smu->adev, NULL); + memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + + smu_table->metrics_time = jiffies; + } + + if (data) + memcpy(data, smu_table->metrics_table, table_size); + mutex_unlock(&smu_table->metrics_lock); + return ret; +} + static int smu_v15_0_8_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) @@ -860,6 +891,39 @@ static bool smu_v15_0_8_is_dpm_running(struct smu_context *smu) smu_v15_0_8_dpm_features.bits); } +static ssize_t smu_v15_0_8_get_pm_metrics(struct smu_context *smu, + void *metrics, size_t max_size) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct amdgpu_pm_metrics *pm_metrics = (struct amdgpu_pm_metrics *)metrics; + uint32_t table_version = smu_table->tables[SMU_TABLE_SMU_METRICS].version; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + uint32_t pmfw_version; + int ret; + + if (!pm_metrics || !max_size) + return -EINVAL; + + if (max_size < (table_size + sizeof(pm_metrics->common_header))) + return -EOVERFLOW; + + /* Don't use cached metrics data */ + ret = smu_v15_0_8_get_metrics_table_internal(smu, 0, pm_metrics->data); + if (ret) + return ret; + + smu_cmn_get_smc_version(smu, NULL, &pmfw_version); + memset(&pm_metrics->common_header, 0, sizeof(pm_metrics->common_header)); + pm_metrics->common_header.mp1_ip_discovery_version = + amdgpu_ip_version(smu->adev, MP1_HWIP, 0); + pm_metrics->common_header.pmfw_version = pmfw_version; + pm_metrics->common_header.pmmetrics_version = table_version; + pm_metrics->common_header.structure_size = + sizeof(pm_metrics->common_header) + table_size; + + return pm_metrics->common_header.structure_size; +} + static int smu_v15_0_8_mode2_reset(struct smu_context *smu) { struct smu_msg_ctl *ctl = &smu->msg_ctl; @@ -923,6 +987,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .setup_pptable = smu_v15_0_8_setup_pptable, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .wait_for_event = smu_v15_0_wait_for_event, + .get_pm_metrics = smu_v15_0_8_get_pm_metrics, .mode2_reset = smu_v15_0_8_mode2_reset, .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, }; From 1d3eb8c7256c17b1f0183cd6ddaf697083957b0c Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 23 Oct 2025 11:04:40 +0800 Subject: [PATCH 2004/2070] drm/amd/pm: add get_gpu_metrics support for 15.0.8 export .get_gpu_metrics interface for 15.0.8 v2: Remove members already exposed by other interfaces, use mask, logical conversion (Lijo) v3: Use correct logic for hbm stacks loop (Lijo) Remove buffer allocation v4: Make out of bound check outside loop (Lijo) v5: fix locking in error case (Alex) Signed-off-by: Yang Wang Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/kgd_pp_interface.h | 1 + .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 180 +++++++++++++++++- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h | 126 ++++++++++++ 3 files changed, 303 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index f5e32d3ca1cbb..7ae1ce4e2a9c5 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -596,6 +596,7 @@ enum amdgpu_metrics_attr_id { AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HBM, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID, AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, AMDGPU_METRICS_ATTR_ID_MAX, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 60a43ce5648a5..b749f983b3a08 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -56,6 +56,13 @@ #define SMUQ10_FRAC(x) ((x) & 0x3ff) #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) +#define hbm_stack_mask_valid(umc_mask) \ + (((umc_mask) & 0xF) == 0xF) + +#define for_each_hbm_stack(stack_idx, umc_mask) \ + for ((stack_idx) = 0; (umc_mask); \ + (umc_mask) >>= 4, (stack_idx)++) \ + #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) #define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature) \ @@ -167,8 +174,9 @@ static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { static int smu_v15_0_8_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; + int ret, gpu_metrcs_size = sizeof(MetricsTable_t); struct smu_table *tables = smu_table->tables; - int gpu_metrcs_size = sizeof(MetricsTable_t); + struct smu_v15_0_8_gpu_metrics *gpu_metrics; void *driver_pptable __free(kfree) = NULL; void *metrics_table __free(kfree) = NULL; @@ -190,6 +198,15 @@ static int smu_v15_0_8_tables_init(struct smu_context *smu) if (!driver_pptable) return -ENOMEM; + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct smu_v15_0_8_gpu_metrics), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) + return ret; + + gpu_metrics = (struct smu_v15_0_8_gpu_metrics *)smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPU_METRICS); + smu_v15_0_8_gpu_metrics_init(gpu_metrics, 1, 9); smu_table->metrics_table = no_free_ptr(metrics_table); smu_table->driver_pptable = no_free_ptr(driver_pptable); @@ -269,16 +286,16 @@ static int smu_v15_0_8_get_metrics_table_internal(struct smu_context *smu, uint3 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; struct smu_table *table = &smu_table->driver_table; struct amdgpu_device *adev = smu->adev; - int ret; mutex_lock(&smu_table->metrics_lock); if (!tmo || !smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(tmo))) { - ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL); + int ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL); if (ret) { dev_info(adev->dev, "Failed to export SMU metrics table!\n"); + mutex_unlock(&smu_table->metrics_lock); return ret; } @@ -291,7 +308,7 @@ static int smu_v15_0_8_get_metrics_table_internal(struct smu_context *smu, uint3 if (data) memcpy(data, smu_table->metrics_table, table_size); mutex_unlock(&smu_table->metrics_lock); - return ret; + return 0; } static int smu_v15_0_8_get_dpm_ultimate_freq(struct smu_context *smu, @@ -967,6 +984,160 @@ static int smu_v15_0_8_mode2_reset(struct smu_context *smu) return ret; } +static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_v15_0_8_gpu_metrics *gpu_metrics; + struct amdgpu_device *adev = smu->adev; + int ret = 0, xcc_id, inst, i, j, idx; + uint32_t aid_mask = adev->aid_mask; + uint32_t mid_mask = adev->aid_mask; + MetricsTable_t *metrics; + + metrics = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL); + + ret = smu_v15_0_8_get_metrics_table_internal(smu, 1, NULL); + if (ret) + return ret; + + metrics = (MetricsTable_t *)smu_table->metrics_table; + gpu_metrics = (struct smu_v15_0_8_gpu_metrics *)smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPU_METRICS); + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + gpu_metrics->temperature_hotspot = SMUQ10_ROUND(metrics->MaxSocketTemperature); + + /* Per-HBM stack temperatures */ + if (adev->umc.active_mask) { + u64 mask = adev->umc.active_mask; + int out_idx = 0; + int stack_idx; + + if (unlikely(hweight64(mask)/4 > SMU_15_0_8_MAX_HBM_STACKS)) + dev_warn(adev->dev, "Invalid umc mask %lld\n", mask); + else { + for_each_hbm_stack(stack_idx, mask) { + if (!hbm_stack_mask_valid(mask)) + continue; + gpu_metrics->temperature_hbm[out_idx++] = + SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + } + } + } + + /* Reports max temperature of all voltage rails */ + gpu_metrics->temperature_vrsoc = SMUQ10_ROUND(metrics->MaxVrTemperature); + /* MID, AID, XCD temperatures */ + idx = 0; + for_each_inst(i, mid_mask) { + gpu_metrics->temperature_mid[idx] = SMUQ10_ROUND(metrics->MidTemperature[i]); + idx++; + } + + idx = 0; + for_each_inst(i, aid_mask) { + gpu_metrics->temperature_aid[idx] = SMUQ10_ROUND(metrics->AidTemperature[i]); + idx++; + } + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + xcc_id = GET_INST(GC, i); + if (xcc_id >= 0) + gpu_metrics->temperature_xcd[i] = SMUQ10_ROUND(metrics->XcdTemperature[xcc_id]); + } + /* Power */ + gpu_metrics->curr_socket_power = SMUQ10_ROUND(metrics->SocketPower); + + gpu_metrics->average_gfx_activity = SMUQ10_ROUND(metrics->SocketGfxBusy); + gpu_metrics->average_umc_activity = SMUQ10_ROUND(metrics->DramBandwidthUtilization); + gpu_metrics->mem_max_bandwidth = SMUQ10_ROUND(metrics->MaxDramBandwidth); + + /* Energy counter reported in 15.259uJ (2^-16) units */ + gpu_metrics->energy_accumulator = metrics->SocketEnergyAcc; + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + xcc_id = GET_INST(GC, i); + if (xcc_id >= 0) { + gpu_metrics->current_gfxclk[i] = + SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); + } + } + + /* Per-MID clocks */ + idx = 0; + for_each_inst(i, mid_mask) { + gpu_metrics->current_socclk[idx] = SMUQ10_ROUND(metrics->SocclkFrequency[i]); + idx++; + } + + /* Per-VCN clocks */ + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + inst = GET_INST(VCN, i); + if (inst >= 0) { + gpu_metrics->current_vclk0[i] = SMUQ10_ROUND(metrics->VclkFrequency[inst]); + gpu_metrics->current_dclk0[i] = SMUQ10_ROUND(metrics->DclkFrequency[inst]); + } + } + + /* Per-AID clocks */ + idx = 0; + for_each_inst(i, aid_mask) { + gpu_metrics->current_uclk[idx] = SMUQ10_ROUND(metrics->UclkFrequency[i]); + idx++; + } + + /* Total accumulated cycle counter */ + gpu_metrics->accumulation_counter = metrics->AccumulationCounter; + + /* Accumulated throttler residencies */ + gpu_metrics->prochot_residency_acc = metrics->ProchotResidencyAcc; + gpu_metrics->ppt_residency_acc = metrics->PptResidencyAcc; + gpu_metrics->socket_thm_residency_acc = metrics->SocketThmResidencyAcc; + gpu_metrics->vr_thm_residency_acc = metrics->VrThmResidencyAcc; + gpu_metrics->hbm_thm_residency_acc = metrics->HbmThmResidencyAcc; + + gpu_metrics->gfx_activity_acc = SMUQ10_ROUND(metrics->SocketGfxBusyAcc); + gpu_metrics->mem_activity_acc = SMUQ10_ROUND(metrics->DramBandwidthUtilizationAcc); + + for (i = 0; i < NUM_XGMI_LINKS; i++) { + j = amdgpu_xgmi_get_ext_link(adev, i); + if (j < 0 || j >= NUM_XGMI_LINKS) + continue; + ret = amdgpu_get_xgmi_link_status(adev, i); + if (ret >= 0) + gpu_metrics->xgmi_link_status[j] = ret; + } + + gpu_metrics->xgmi_read_data_acc = SMUQ10_ROUND(metrics->XgmiReadBandwidthAcc); + gpu_metrics->xgmi_write_data_acc = SMUQ10_ROUND(metrics->XgmiWriteBandwidthAcc); + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + inst = GET_INST(GC, i); + gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND(metrics->GfxBusy[inst]); + gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); + gpu_metrics->gfx_below_host_limit_ppt_acc[i] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); + gpu_metrics->gfx_below_host_limit_thm_acc[i] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); + gpu_metrics->gfx_low_utilization_acc[i] = + SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); + gpu_metrics->gfx_below_host_limit_total_acc[i] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); + } + + gpu_metrics->xgmi_link_width = metrics->XgmiWidth; + gpu_metrics->xgmi_link_speed = metrics->XgmiBitrate; + + gpu_metrics->firmware_timestamp = metrics->Timestamp; + + *table = gpu_metrics; + + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + + return sizeof(*gpu_metrics); +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -990,6 +1161,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_pm_metrics = smu_v15_0_8_get_pm_metrics, .mode2_reset = smu_v15_0_8_mode2_reset, .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, + .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h index 6c85f23d31116..8fc16796788b5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -23,6 +23,15 @@ #ifndef __SMU_15_0_8_PPT_H__ #define __SMU_15_0_8_PPT_H__ +#define SMU_15_0_8_NUM_XGMI_LINKS 8 +#define SMU_15_0_8_MAX_GFX_CLKS 8 +#define SMU_15_0_8_MAX_CLKS 4 +#define SMU_15_0_8_MAX_XCC 8 +#define SMU_15_0_8_MAX_VCN 4 +#define SMU_15_0_8_MAX_JPEG 40 +#define SMU_15_0_8_MAX_AID 2 +#define SMU_15_0_8_MAX_MID 2 +#define SMU_15_0_8_MAX_HBM_STACKS 12 extern void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu); typedef struct { @@ -55,4 +64,121 @@ typedef struct { bool init; } PPTable_t; +#if defined(SWSMU_CODE_LAYER_L2) +#include "smu_cmn.h" + +/* SMUv 15.0.8 GPU metrics*/ +#define SMU_15_0_8_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hotspot); \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_mem); \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_vrsoc); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_HBM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hbm, \ + SMU_15_0_8_MAX_HBM_STACKS); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_MID), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_mid, SMU_15_0_8_MAX_MID); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_AID), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_aid, SMU_15_0_8_MAX_AID); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_XCD), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_xcd, SMU_15_0_8_MAX_XCC); \ + SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1), \ + SMU_MTYPE(U16), curr_socket_power); \ + SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U16), average_gfx_activity); \ + SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U16), average_umc_activity); \ + SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1), \ + SMU_MTYPE(U64), mem_max_bandwidth); \ + SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), energy_accumulator); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ + SMU_MTYPE(U64), system_clock_counter); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), prochot_residency_acc); \ + SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), ppt_residency_acc); \ + SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), socket_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), vr_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), hbm_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), gfxclk_lock_status); \ + SMU_SCALAR(SMU_MATTR(PCIE_LINK_WIDTH), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), pcie_link_width); \ + SMU_SCALAR(SMU_MATTR(PCIE_LINK_SPEED), SMU_MUNIT(SPEED_2), \ + SMU_MTYPE(U16), pcie_link_speed); \ + SMU_SCALAR(SMU_MATTR(XGMI_LINK_WIDTH), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), xgmi_link_width); \ + SMU_SCALAR(SMU_MATTR(XGMI_LINK_SPEED), SMU_MUNIT(SPEED_1), \ + SMU_MTYPE(U16), xgmi_link_speed); \ + SMU_SCALAR(SMU_MATTR(GFX_ACTIVITY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_activity_acc); \ + SMU_SCALAR(SMU_MATTR(MEM_ACTIVITY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), mem_activity_acc); \ + SMU_ARRAY(SMU_MATTR(PCIE_BANDWIDTH_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_bandwidth_acc, SMU_15_0_8_MAX_MID); \ + SMU_ARRAY(SMU_MATTR(PCIE_BANDWIDTH_INST), SMU_MUNIT(BW_1), \ + SMU_MTYPE(U32), pcie_bandwidth_inst, SMU_15_0_8_MAX_MID); \ + SMU_SCALAR(SMU_MATTR(PCIE_L0_TO_RECOV_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_l0_to_recov_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_replay_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_ROVER_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_replay_rover_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_NAK_SENT_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_nak_sent_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_NAK_RCVD_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_nak_rcvd_count_acc); \ + SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), xgmi_link_status, \ + SMU_15_0_8_NUM_XGMI_LINKS); \ + SMU_SCALAR(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \ + SMU_MTYPE(U64), xgmi_read_data_acc); \ + SMU_SCALAR(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \ + SMU_MTYPE(U64), xgmi_write_data_acc); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); \ + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_gfxclk, SMU_15_0_8_MAX_GFX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_socclk, SMU_15_0_8_MAX_MID); \ + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_vclk0, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_dclk0, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_uclk, SMU_15_0_8_MAX_AID); \ + SMU_SCALAR(SMU_MATTR(PCIE_LC_PERF_OTHER_END_RECOVERY), \ + SMU_MUNIT(NONE), SMU_MTYPE(U64), \ + pcie_lc_perf_other_end_recovery); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U32), gfx_busy_inst, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + jpeg_busy, SMU_15_0_8_MAX_JPEG); \ + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + vcn_busy, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(NONE), SMU_MTYPE(U64), \ + gfx_busy_acc, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_low_utilization_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ + SMU_15_0_8_MAX_XCC); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); +#endif #endif From fbb239950ea02d224da6cba44c370eec81a09745 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 22 Oct 2025 21:08:13 +0800 Subject: [PATCH 2005/2070] drm/amd/pm: add get_unique_id support for smu 15.0.8 export .get_unique_id interface for smu 15.0.8 Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index b749f983b3a08..f3aa25c59f9ce 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1138,6 +1138,15 @@ static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table return sizeof(*gpu_metrics); } +static void smu_v15_0_8_get_unique_id(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + + adev->unique_id = pptable->PublicSerialNumberMID; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -1162,6 +1171,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .mode2_reset = smu_v15_0_8_mode2_reset, .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, + .get_unique_id = smu_v15_0_8_get_unique_id, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, From 5803bafe5004930cc82798bb5e4b2a7fa8b53708 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 22 Oct 2025 21:32:55 +0800 Subject: [PATCH 2006/2070] drm/amd/pm: add set{get}_power_limit support for smu 15.0.8 export .set_power_limit & .get_power_limit interface for smu 15.0.8 Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 397dbc6e5686c..fc35c0242fc8e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2966,6 +2966,7 @@ int smu_get_power_limit(void *handle, case IP_VERSION(11, 0, 11): case IP_VERSION(11, 0, 12): case IP_VERSION(11, 0, 13): + case IP_VERSION(15, 0, 8): ret = smu_get_asic_power_limits(smu, &smu->current_power_limit, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index f3aa25c59f9ce..0c06b65001219 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1147,6 +1147,38 @@ static void smu_v15_0_8_get_unique_id(struct smu_context *smu) adev->unique_id = pptable->PublicSerialNumberMID; } +static int smu_v15_0_8_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit, + uint32_t *min_power_limit) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + uint32_t power_limit = 0; + int ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit); + if (ret) { + dev_err(smu->adev->dev, "Couldn't get PPT limit"); + return -EINVAL; + } + + if (current_power_limit) + *current_power_limit = power_limit; + + if (default_power_limit) + *max_power_limit = pptable->MaxSocketPowerLimit; + + if (max_power_limit) + *max_power_limit = pptable->MaxSocketPowerLimit; + + if (min_power_limit) + *min_power_limit = 0; + + return 0; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -1172,6 +1204,8 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, .get_unique_id = smu_v15_0_8_get_unique_id, + .get_power_limit = smu_v15_0_8_get_power_limit, + .set_power_limit = smu_v15_0_set_power_limit, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, From aa82cd429d9e196f3a47da8e79b8179e08aeed55 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 24 Dec 2025 03:54:11 +0800 Subject: [PATCH 2007/2070] drm/amd/pm: Add emit clock support Add emit clock support and fetching other metrics data like temperature, clock for smu_v15_0_8 v2: Use umc count for hbm stack temperature (Lijo) v3: Use correct logic for hbm stacks (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 0c06b65001219..2a74acb2790fd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -311,6 +311,203 @@ static int smu_v15_0_8_get_metrics_table_internal(struct smu_context *smu, uint3 return 0; } +static int smu_v15_0_8_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table; + struct amdgpu_device *adev = smu->adev; + int ret, xcc_id; + + ret = smu_v15_0_8_get_metrics_table_internal(smu, 10, NULL); + if (ret) + return ret; + + switch (member) { + case METRICS_CURR_GFXCLK: + case METRICS_AVERAGE_GFXCLK: + xcc_id = GET_INST(GC, 0); + *value = SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); + break; + case METRICS_CURR_SOCCLK: + case METRICS_AVERAGE_SOCCLK: + *value = SMUQ10_ROUND(metrics->SocclkFrequency[0]); + break; + case METRICS_CURR_UCLK: + case METRICS_AVERAGE_UCLK: + *value = SMUQ10_ROUND(metrics->UclkFrequency[0]); + break; + case METRICS_CURR_VCLK: + *value = SMUQ10_ROUND(metrics->VclkFrequency[0]); + break; + case METRICS_CURR_DCLK: + *value = SMUQ10_ROUND(metrics->DclkFrequency[0]); + break; + case METRICS_CURR_FCLK: + *value = SMUQ10_ROUND(metrics->FclkFrequency[0]); + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = SMUQ10_ROUND(metrics->SocketGfxBusy); + break; + case METRICS_AVERAGE_MEMACTIVITY: + *value = SMUQ10_ROUND(metrics->DramBandwidthUtilization); + break; + case METRICS_CURR_SOCKETPOWER: + *value = SMUQ10_ROUND(metrics->SocketPower) << 8; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = SMUQ10_ROUND(metrics->MaxSocketTemperature) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_MEM: + { + struct amdgpu_device *adev = smu->adev; + u32 max_hbm_temp = 0; + + /* Find max temperature across all HBM stacks */ + if (adev->umc.active_mask) { + u64 mask = adev->umc.active_mask; + int stack_idx; + + for_each_hbm_stack(stack_idx, mask) { + u32 temp; + + if (!hbm_stack_mask_valid(mask)) + continue; + + temp = SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + if (temp > max_hbm_temp) + max_hbm_temp = temp; + } + } + *value = max_hbm_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + } + /* This is the max of all VRs and not just SOC VR. + */ + case METRICS_TEMPERATURE_VRSOC: + *value = SMUQ10_ROUND(metrics->MaxVrTemperature) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + default: + *value = UINT_MAX; + break; + } + + return 0; +} + +static int smu_v15_0_8_get_current_clk_freq_by_table(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + MetricsMember_t member_type; + + if (!value) + return -EINVAL; + + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + member_type = METRICS_CURR_GFXCLK; + break; + case SMU_UCLK: + case SMU_MCLK: + member_type = METRICS_CURR_UCLK; + break; + case SMU_SOCCLK: + member_type = METRICS_CURR_SOCCLK; + break; + case SMU_VCLK: + member_type = METRICS_CURR_VCLK; + break; + case SMU_DCLK: + member_type = METRICS_CURR_DCLK; + break; + case SMU_FCLK: + member_type = METRICS_CURR_FCLK; + break; + default: + return -EINVAL; + } + + return smu_v15_0_8_get_smu_metrics_data(smu, member_type, value); +} + +static int smu_v15_0_8_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type type, char *buf, + int *offset) +{ + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + struct smu_15_0_dpm_context *dpm_context; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + int ret, now, size = *offset; + + if (amdgpu_ras_intr_triggered()) { + sysfs_emit_at(buf, size, "unavailable\n"); + return -EBUSY; + } + + dpm_context = smu_dpm->dpm_context; + + switch (type) { + case SMU_OD_SCLK: + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); + size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", + pstate_table->gfxclk_pstate.curr.min, + pstate_table->gfxclk_pstate.curr.max); + break; + case SMU_OD_MCLK: + size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); + size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", + pstate_table->uclk_pstate.curr.min, + pstate_table->uclk_pstate.curr.max); + break; + case SMU_SCLK: + case SMU_GFXCLK: + single_dpm_table = &dpm_context->dpm_tables.gfx_table; + break; + case SMU_MCLK: + case SMU_UCLK: + single_dpm_table = &dpm_context->dpm_tables.uclk_table; + break; + case SMU_SOCCLK: + single_dpm_table = &dpm_context->dpm_tables.soc_table; + break; + case SMU_FCLK: + single_dpm_table = &dpm_context->dpm_tables.fclk_table; + break; + case SMU_VCLK: + single_dpm_table = &dpm_context->dpm_tables.vclk_table; + break; + case SMU_DCLK: + single_dpm_table = &dpm_context->dpm_tables.dclk_table; + break; + default: + break; + } + + if (single_dpm_table) { + ret = smu_v15_0_8_get_current_clk_freq_by_table(smu, type, &now); + if (ret) { + dev_err(smu->adev->dev, + "Attempt to get current clk Failed!"); + return ret; + } + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, now, + buf, offset); + if (ret < 0) + return ret; + + return 0; + } + + *offset = size; + + return 0; +} + static int smu_v15_0_8_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) @@ -1206,6 +1403,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_unique_id = smu_v15_0_8_get_unique_id, .get_power_limit = smu_v15_0_8_get_power_limit, .set_power_limit = smu_v15_0_set_power_limit, + .emit_clk_levels = smu_v15_0_8_emit_clk_levels, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, From c5f665f49234f8096911d4ada0db65f89cc928b1 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 15 Mar 2026 20:11:54 +0530 Subject: [PATCH 2008/2070] drm/amd/display: Add clk_mgr NULL checks in dcn32_initialize_min_clocks() dcn32_init_hw() checks dc->clk_mgr before calling init_clocks(), so the clock manager is not treated as unconditionally present on this path. However, dcn32_initialize_min_clocks() later dereferences dc->clk_mgr, bw_params, and clk_mgr callbacks without validating them. Add the required guards in dcn32_initialize_min_clocks() before accessing clk_mgr-dependent state, and check callback presence before calling get_dispclk_from_dentist() and update_clocks(). Also guard the later update_bw_bounding_box() call in the FAMS2-disabled path since it also dereferences dc->clk_mgr->bw_params. This keeps clk_mgr handling consistent in the DCN32 HW init flow and avoids possible NULL pointer dereferences reported by Smatch. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn32/dcn32_hwseq.c:1012 dcn32_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 978) Cc: Roman Li Cc: Alex Hung Cc: Jerry Zuo Cc: Sun peng Li Cc: Tom Chung Cc: Dan Carpenter Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Hung --- .../drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index ba2c06bd39505..bbd6f6e93bc03 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -756,6 +756,9 @@ static void dcn32_initialize_min_clocks(struct dc *dc) { struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; + if (!dc->clk_mgr || !dc->clk_mgr->bw_params || !dc->clk_mgr->funcs) + return; + clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; @@ -764,9 +767,10 @@ static void dcn32_initialize_min_clocks(struct dc *dc) clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; clocks->fclk_p_state_change_support = true; clocks->p_state_change_support = true; + if (dc->debug.disable_boot_optimizations) { clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; - } else { + } else if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { /* Even though DPG_EN = 1 for the connected display, it still requires the * correct timing so we cannot set DISPCLK to min freq or it could cause * audio corruption. Read current DISPCLK from DENTIST and request the same @@ -775,10 +779,10 @@ static void dcn32_initialize_min_clocks(struct dc *dc) clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); } - dc->clk_mgr->funcs->update_clocks( - dc->clk_mgr, - dc->current_state, - true); + if (dc->clk_mgr->funcs->update_clocks) + dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, + dc->current_state, + true); } void dcn32_init_hw(struct dc *dc) @@ -1006,7 +1010,8 @@ void dcn32_init_hw(struct dc *dc) DMUB_FW_VERSION(7, 0, 35)) { /* FAMS2 is disabled */ dc->debug.fams2_config.bits.enable = false; - if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) { + if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box && + dc->clk_mgr && dc->clk_mgr->bw_params) { /* update bounding box if FAMS2 disabled */ dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); } From bf5e424e0be92ac9abe0167b2818273d155cbf21 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Tue, 17 Mar 2026 08:38:38 +0530 Subject: [PATCH 2009/2070] drm/amd/display: Fix NULL pointer assumptions in dcn42_init_hw() dcn42_init_hw() calls update_bw_bounding_box() when FAMS2 is disabled or when the dchub reference clock changes. However the existing condition mixes the callback pointer check with only one side of the || expression: ((!fams2_enable && update_bw_bounding_box) || freq_changed) This allows the block to be entered through the freq_changed path even when update_bw_bounding_box() is NULL. The function is then called unconditionally inside the block, which can lead to a NULL pointer dereference. Additionally, the code dereferences dc->clk_mgr->bw_params without verifying that dc->clk_mgr and bw_params are valid. Restructure the condition so that the update trigger remains the same (FAMS2 disabled or dchub ref clock changed), but guard the call with explicit checks for: - update_bw_bounding_box callback - dc->clk_mgr - dc->clk_mgr->bw_params Also introduce a helper boolean (dchub_ref_freq_changed) to improve readability of the clock-change condition. This fixes Smatch warnings about inconsistent NULL assumptions in dcn42_init_hw(). drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn42/dcn42_hwseq.c:264 dcn42_init_hw() error: we previously assumed 'dc->clk_mgr' could be null (see line 253) drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn42/dcn42_hwseq.c:278 dcn42_init_hw() error: we previously assumed 'dc->res_pool->funcs->update_bw_bounding_box' could be null (see line 274) Cc: Roman Li Cc: Alex Hung Cc: Jerry Zuo Cc: Sun peng Li Cc: Tom Chung Cc: Dan Carpenter Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Hung --- .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 24 +++++++++++++------ 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index 7bf94eae30a6f..7f9c121c00e67 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -69,6 +69,7 @@ void dcn42_init_hw(struct dc *dc) int edp_num; uint32_t backlight = MAX_BACKLIGHT_LEVEL; uint32_t user_level = MAX_BACKLIGHT_LEVEL; + bool dchub_ref_freq_changed; int current_dchub_ref_freq = 0; if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) { @@ -261,8 +262,12 @@ void dcn42_init_hw(struct dc *dc) if (dc->res_pool->hubbub->funcs->init_crb) dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); - if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) - dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->clk_mgr->bw_params->num_channels, dc->config.sdpif_request_limit_words_per_umc); + if (dc->res_pool->hubbub->funcs->set_request_limit && + dc->clk_mgr && dc->clk_mgr->bw_params && + dc->config.sdpif_request_limit_words_per_umc > 0) + dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, + dc->clk_mgr->bw_params->num_channels, + dc->config.sdpif_request_limit_words_per_umc); // Get DMCUB capabilities if (dc->ctx->dmub_srv) { @@ -270,13 +275,18 @@ void dcn42_init_hw(struct dc *dc) dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0; dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; + + /* sw and fw FAMS versions must match for support */ dc->debug.fams2_config.bits.enable &= - dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; // sw & fw fams versions must match for support - if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box) - || res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq) { + dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; + dchub_ref_freq_changed = + res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq; + + if ((!dc->debug.fams2_config.bits.enable || dchub_ref_freq_changed) && + dc->res_pool->funcs->update_bw_bounding_box && + dc->clk_mgr && dc->clk_mgr->bw_params) { /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ - if (dc->clk_mgr) - dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); + dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); } } if (dc->res_pool->pg_cntl) { From 065903cf4d2a023fca858e41b3ed91949f8a2059 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 25 Dec 2025 23:44:20 +0800 Subject: [PATCH 2010/2070] drm/amd/pm: add populate_umd_state_clk support add populate_umd_state_clk support for smu 15.0.8 v2: remove gl2clk/socclk/fclk, restrict to only current min/max (Lijo) Signed-off-by: Asad Kamal Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 2a74acb2790fd..c13d9e5060824 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1376,6 +1376,21 @@ static int smu_v15_0_8_get_power_limit(struct smu_context *smu, return 0; } +static int smu_v15_0_8_populate_umd_state_clk(struct smu_context *smu) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + + pstate_table->gfxclk_pstate.curr.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = SMU_DPM_TABLE_MAX(gfx_table); + + pstate_table->uclk_pstate.curr.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.curr.max = SMU_DPM_TABLE_MAX(mem_table); + return 0; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -1404,7 +1419,8 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_power_limit = smu_v15_0_8_get_power_limit, .set_power_limit = smu_v15_0_set_power_limit, .emit_clk_levels = smu_v15_0_8_emit_clk_levels, -}; + .populate_umd_state_clk = smu_v15_0_8_populate_umd_state_clk, + }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, const struct cmn2asic_msg_mapping *message_map) From 077e3ec7b92e41d9792c35d059a4aa467e461675 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 26 Dec 2025 00:13:13 +0800 Subject: [PATCH 2011/2070] drm/amd/pm: Add od_edit_dpm_table support Add od_edit_dpm_table support for smu_v15_0_8 v2: Skip Gl2clk/Fclk (Lijo) v3: sqaush in set_performance_support (Asad) Signed-off-by: Asad Kamal Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 296 +++++++++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 1 + 3 files changed, 306 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index c13d9e5060824..6283e6b404f05 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1391,6 +1391,298 @@ static int smu_v15_0_8_populate_umd_state_clk(struct smu_context *smu) return 0; } +static int smu_v15_0_8_set_gfx_soft_freq_limited_range(struct smu_context *smu, + uint32_t min, + uint32_t max) +{ + int ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, + max & 0xffff, NULL); + if (ret) + return ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk, + min & 0xffff, NULL); + + return ret; +} + +static int smu_v15_0_8_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_15_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + int ret; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: + /* Determinism not supported on SMU v15.0.8 */ + ret = -EOPNOTSUPP; + break; + + case AMD_DPM_FORCED_LEVEL_AUTO: + /* Restore GFXCLK to default range */ + if ((SMU_DPM_TABLE_MIN(gfx_table) != + pstate_table->gfxclk_pstate.curr.min) || + (SMU_DPM_TABLE_MAX(gfx_table) != + pstate_table->gfxclk_pstate.curr.max)) { + ret = smu_v15_0_8_set_gfx_soft_freq_limited_range( + smu, SMU_DPM_TABLE_MIN(gfx_table), + SMU_DPM_TABLE_MAX(gfx_table)); + if (ret) + goto out; + + pstate_table->gfxclk_pstate.curr.min = + SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(gfx_table); + } + + /* Restore UCLK to default max */ + if (SMU_DPM_TABLE_MAX(uclk_table) != + pstate_table->uclk_pstate.curr.max) { + /* Min UCLK is not expected to be changed */ + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_UCLK, 0, + SMU_DPM_TABLE_MAX(uclk_table), + false); + if (ret) + goto out; + + pstate_table->uclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(uclk_table); + } + + if (ret) + goto out; + + smu_cmn_reset_custom_level(smu); + + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + ret = 0; + break; + default: + ret = -EOPNOTSUPP; + break; + } + +out: + return ret; +} + +static int smu_v15_0_8_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, uint32_t max, + bool automatic) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + int ret = 0; + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK && + clk_type != SMU_UCLK) + return -EINVAL; + + if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { + if (min >= max) { + dev_err(smu->adev->dev, + "Minimum clk should be less than the maximum allowed clock\n"); + return -EINVAL; + } + + if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) { + if ((min == pstate_table->gfxclk_pstate.curr.min) && + (max == pstate_table->gfxclk_pstate.curr.max)) + return 0; + + ret = smu_v15_0_8_set_gfx_soft_freq_limited_range(smu, + min, max); + if (!ret) { + pstate_table->gfxclk_pstate.curr.min = min; + pstate_table->gfxclk_pstate.curr.max = max; + } + } + + if (clk_type == SMU_UCLK) { + if (max == pstate_table->uclk_pstate.curr.max) + return 0; + + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_UCLK, + 0, max, + false); + if (!ret) + pstate_table->uclk_pstate.curr.max = max; + } + + return ret; + } + + return 0; +} + +static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu, + enum PP_OD_DPM_TABLE_COMMAND type, + long input[], uint32_t size) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + struct smu_15_0_dpm_context *dpm_context = smu_dpm->dpm_context; + uint32_t min_clk, max_clk; + int ret; + + /* Only allowed in manual mode */ + if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_OD_EDIT_SCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); + if (input[0] == 0) { + if (input[1] < min_clk) { + dev_warn(smu->adev->dev, + "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", + input[1], min_clk); + pstate_table->gfxclk_pstate.custom.min = + pstate_table->gfxclk_pstate.curr.min; + return -EINVAL; + } + + pstate_table->gfxclk_pstate.custom.min = input[1]; + } else if (input[0] == 1) { + if (input[1] > max_clk) { + dev_warn(smu->adev->dev, + "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); + pstate_table->gfxclk_pstate.custom.max = + pstate_table->gfxclk_pstate.curr.max; + return -EINVAL; + } + + pstate_table->gfxclk_pstate.custom.max = input[1]; + } else { + return -EINVAL; + } + break; + case PP_OD_EDIT_MCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + dev_warn(smu->adev->dev, + "UCLK_LIMITS setting not supported!\n"); + return -EOPNOTSUPP; + } + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + if (input[0] == 0) { + dev_info(smu->adev->dev, + "Setting min UCLK level is not supported"); + return -EINVAL; + } else if (input[0] == 1) { + if (input[1] > max_clk) { + dev_warn(smu->adev->dev, + "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); + pstate_table->uclk_pstate.custom.max = + pstate_table->uclk_pstate.curr.max; + + return -EINVAL; + } + + pstate_table->uclk_pstate.custom.max = input[1]; + } + break; + case PP_OD_RESTORE_DEFAULT_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + /* Use the default frequencies for manual mode */ + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); + + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_GFXCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_UCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + + smu_cmn_reset_custom_level(smu); + break; + case PP_OD_COMMIT_DPM_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + if (!pstate_table->gfxclk_pstate.custom.min) + pstate_table->gfxclk_pstate.custom.min = + pstate_table->gfxclk_pstate.curr.min; + + if (!pstate_table->gfxclk_pstate.custom.max) + pstate_table->gfxclk_pstate.custom.max = + pstate_table->gfxclk_pstate.curr.max; + + min_clk = pstate_table->gfxclk_pstate.custom.min; + max_clk = pstate_table->gfxclk_pstate.custom.max; + + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_GFXCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + + /* Commit UCLK custom range (only max supported) */ + if (pstate_table->uclk_pstate.custom.max) { + min_clk = pstate_table->uclk_pstate.curr.min; + max_clk = pstate_table->uclk_pstate.custom.max; + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_UCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + } + + break; + default: + return -ENOSYS; + } + + return 0; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -1420,7 +1712,9 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .set_power_limit = smu_v15_0_set_power_limit, .emit_clk_levels = smu_v15_0_8_emit_clk_levels, .populate_umd_state_clk = smu_v15_0_8_populate_umd_state_clk, - }; + .set_performance_level = smu_v15_0_8_set_performance_level, + .od_edit_dpm_table = smu_v15_0_8_od_edit_dpm_table, +}; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, const struct cmn2asic_msg_mapping *message_map) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index ce5250ecdcd51..8e44260f933e0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1305,6 +1305,16 @@ void smu_cmn_get_backend_workload_mask(struct smu_context *smu, } } +void smu_cmn_reset_custom_level(struct smu_context *smu) +{ + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + + pstate_table->gfxclk_pstate.custom.min = 0; + pstate_table->gfxclk_pstate.custom.max = 0; + pstate_table->uclk_pstate.custom.min = 0; + pstate_table->uclk_pstate.custom.max = 0; +} + static inline bool smu_cmn_freqs_match(uint32_t freq1, uint32_t freq2) { /* Frequencies within 25 MHz are considered equal */ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index e4d282d8bcae3..b76e86df5da78 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -204,6 +204,7 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu, struct smu_pcie_table *pcie_table, uint32_t cur_gen, uint32_t cur_lane, char *buf, int *offset); +void smu_cmn_reset_custom_level(struct smu_context *smu); int smu_cmn_dpm_pcie_gen_idx(int gen); int smu_cmn_dpm_pcie_width_idx(int width); From 888c99038438638b01afb589ca68d5e6a72221d4 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 26 Dec 2025 00:30:41 +0800 Subject: [PATCH 2012/2070] drm/amd/pm: Add get_thermal_temperature_range support Add get_thermal_temperature_range support smu_v15_0_8 v2: Remove sriov check (Lijo) v3: Restrict to 1VF mode(Lijo) Signed-off-by: Asad Kamal Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 6283e6b404f05..904779f67b063 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1683,6 +1683,38 @@ static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu, return 0; } +static int smu_v15_0_8_get_thermal_temperature_range(struct smu_context *smu, + struct smu_temperature_range *range) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + uint32_t max_ctf, max_thm; + + if (amdgpu_sriov_multi_vf_mode(smu->adev)) + return 0; + + if (!range) + return -EINVAL; + + /* CTF (Critical Temperature Fault) limits */ + max_ctf = max3(pptable->CTFLimitMID, pptable->CTFLimitXCD, + pptable->CTFLimitAID); + range->hotspot_emergency_max = max_ctf * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + range->mem_emergency_max = pptable->CTFLimitHBM * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + /* Thermal throttling limits */ + max_thm = max3(pptable->ThermalLimitMID, pptable->ThermalLimitXCD, + pptable->ThermalLimitAID); + range->hotspot_crit_max = max_thm * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + range->mem_crit_max = pptable->ThermalLimitHBM * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return 0; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -1714,6 +1746,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .populate_umd_state_clk = smu_v15_0_8_populate_umd_state_clk, .set_performance_level = smu_v15_0_8_set_performance_level, .od_edit_dpm_table = smu_v15_0_8_od_edit_dpm_table, + .get_thermal_temperature_range = smu_v15_0_8_get_thermal_temperature_range, }; static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, From 6e6468b62ebb0c7a8a5d8953b83b645804ad6f80 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 26 Dec 2025 13:00:48 +0800 Subject: [PATCH 2013/2070] drm/amd/pm: Add ppt1 support Add ppt1 support for smu_v15_0_8 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 75 ++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 904779f67b063..abfaf8b06e502 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1715,6 +1715,78 @@ static int smu_v15_0_8_get_thermal_temperature_range(struct smu_context *smu, return 0; } +static int smu_v15_0_8_set_power_limit(struct smu_context *smu, + enum smu_ppt_limit_type limit_type, + uint32_t limit) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int ret; + + if (limit_type == SMU_FAST_PPT_LIMIT) { + if (!pptable->PPT1Max) + return -EOPNOTSUPP; + + if (limit > pptable->PPT1Max || limit < pptable->PPT1Min) { + dev_err(smu->adev->dev, + "New PPT1 limit (%d) should be between min %d and max %d\n", + limit, pptable->PPT1Min, pptable->PPT1Max); + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetFastPptLimit, + limit, NULL); + if (ret) + dev_err(smu->adev->dev, "Set fast PPT limit failed!\n"); + + return ret; + } + + return smu_v15_0_set_power_limit(smu, limit_type, limit); +} + +static int smu_v15_0_8_get_ppt_limit(struct smu_context *smu, + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int ret = 0; + + if (!ppt_limit) + return -EINVAL; + + if (type == SMU_FAST_PPT_LIMIT) { + if (!pptable->PPT1Max) + return -EOPNOTSUPP; + + switch (level) { + case SMU_PPT_LIMIT_MAX: + *ppt_limit = pptable->PPT1Max; + break; + case SMU_PPT_LIMIT_CURRENT: + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPptLimit, + ppt_limit); + if (ret) + dev_err(smu->adev->dev, + "Get fast PPT limit failed!\n"); + break; + case SMU_PPT_LIMIT_DEFAULT: + *ppt_limit = pptable->PPT1Default; + break; + case SMU_PPT_LIMIT_MIN: + *ppt_limit = pptable->PPT1Min; + break; + default: + return -EOPNOTSUPP; + } + return ret; + } + + return -EOPNOTSUPP; +} + static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .init_allowed_features = smu_v15_0_8_init_allowed_features, .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, @@ -1741,7 +1813,8 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, .get_unique_id = smu_v15_0_8_get_unique_id, .get_power_limit = smu_v15_0_8_get_power_limit, - .set_power_limit = smu_v15_0_set_power_limit, + .set_power_limit = smu_v15_0_8_set_power_limit, + .get_ppt_limit = smu_v15_0_8_get_ppt_limit, .emit_clk_levels = smu_v15_0_8_emit_clk_levels, .populate_umd_state_clk = smu_v15_0_8_populate_umd_state_clk, .set_performance_level = smu_v15_0_8_set_performance_level, From 65825f27ad20e49b01831ff9542b654a519d0072 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 26 Dec 2025 13:12:56 +0800 Subject: [PATCH 2014/2070] drm/amd/pm: Add read sensor support Add read sensor support for smu_v15_0_8 v2: Remove gfx voltage support (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index abfaf8b06e502..8a49f1a190afb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -434,6 +434,117 @@ static int smu_v15_0_8_get_current_clk_freq_by_table(struct smu_context *smu, return smu_v15_0_8_get_smu_metrics_data(smu, member_type, value); } +static int smu_v15_0_8_get_current_activity_percent(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + int ret = 0; + + if (!value) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXACTIVITY, value); + break; + case AMDGPU_PP_SENSOR_MEM_LOAD: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_AVERAGE_MEMACTIVITY, value); + break; + default: + dev_err(smu->adev->dev, + "Invalid sensor for retrieving clock activity\n"); + return -EINVAL; + } + + return ret; +} + +static int smu_v15_0_8_thermal_get_temperature(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + int ret = 0; + + if (!value) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_HOTSPOT, value); + break; + case AMDGPU_PP_SENSOR_MEM_TEMP: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_MEM, value); + break; + default: + dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); + return -EINVAL; + } + + return ret; +} + +static int smu_v15_0_8_read_sensor(struct smu_context *smu, + enum amd_pp_sensors sensor, void *data, + uint32_t *size) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + int ret = 0; + + if (amdgpu_ras_intr_triggered()) + return 0; + + if (!data || !size) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_MEM_LOAD: + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = smu_v15_0_8_get_current_activity_percent(smu, sensor, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_CURR_SOCKETPOWER, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + case AMDGPU_PP_SENSOR_MEM_TEMP: + ret = smu_v15_0_8_thermal_get_temperature(smu, sensor, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: + ret = smu_v15_0_8_get_current_clk_freq_by_table(smu, + SMU_UCLK, (uint32_t *)data); + /* the output clock frequency in 10K unit */ + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_SCLK: + ret = smu_v15_0_8_get_current_clk_freq_by_table(smu, + SMU_GFXCLK, (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDBOARD: + *(uint32_t *)data = dpm_context->board_volt; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_AVG_POWER: + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + static int smu_v15_0_8_emit_clk_levels(struct smu_context *smu, enum smu_clk_type type, char *buf, int *offset) @@ -1816,6 +1927,7 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { .set_power_limit = smu_v15_0_8_set_power_limit, .get_ppt_limit = smu_v15_0_8_get_ppt_limit, .emit_clk_levels = smu_v15_0_8_emit_clk_levels, + .read_sensor = smu_v15_0_8_read_sensor, .populate_umd_state_clk = smu_v15_0_8_populate_umd_state_clk, .set_performance_level = smu_v15_0_8_set_performance_level, .od_edit_dpm_table = smu_v15_0_8_od_edit_dpm_table, From be57ee74699d135aed125cdf16d5be1df9356407 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 30 Jan 2026 21:10:47 +0800 Subject: [PATCH 2015/2070] drm/amd/pm: Add gpuboard temperature metrics support Add gpuboard temperature metrics support via system metrics table for smu_v15_0_8 v3: Use per sensor attr id (Lijo) v4: Use s16 for temp, remove cast, use separate function to fill gpuboard temperature metrics data (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/kgd_pp_interface.h | 35 ++++ .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 172 ++++++++++++++++++ .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h | 71 ++++++++ 3 files changed, 278 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 7ae1ce4e2a9c5..3f00e99088c27 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -599,6 +599,35 @@ enum amdgpu_metrics_attr_id { AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID, AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, + AMDGPU_METRICS_ATTR_ID_LABEL_VERSION, + AMDGPU_METRICS_ATTR_ID_NODE_ID, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_RETIMER, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC_2, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_VDD18_VR, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_B_VR, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_D_VR, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X0, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X1, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_UCIE, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAA, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, AMDGPU_METRICS_ATTR_ID_MAX, }; @@ -1851,4 +1880,10 @@ enum amdgpu_xgmi_link_status { AMDGPU_XGMI_LINK_NA = 2, }; +struct amdgpu_gpuboard_temp_metrics_v1_1 { + struct metrics_table_header common_header; + int attr_count; + struct gpu_metrics_attr metrics_attrs[]; +}; + #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 8a49f1a190afb..4c1a8f37d12cb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -171,8 +171,14 @@ static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { TAB_MAP(I2C_COMMANDS), }; +static size_t smu_v15_0_8_get_system_metrics_size(void) +{ + return sizeof(SystemMetricsTable_t); +} + static int smu_v15_0_8_tables_init(struct smu_context *smu) { + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; struct smu_table_context *smu_table = &smu->smu_table; int ret, gpu_metrcs_size = sizeof(MetricsTable_t); struct smu_table *tables = smu_table->tables; @@ -187,6 +193,9 @@ static int smu_v15_0_8_tables_init(struct smu_context *smu) gpu_metrcs_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); + SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS, + smu_v15_0_8_get_system_metrics_size(), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); metrics_table = kzalloc(gpu_metrcs_size, GFP_KERNEL); if (!metrics_table) @@ -207,6 +216,25 @@ static int smu_v15_0_8_tables_init(struct smu_context *smu) gpu_metrics = (struct smu_v15_0_8_gpu_metrics *)smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_GPU_METRICS); smu_v15_0_8_gpu_metrics_init(gpu_metrics, 1, 9); + + ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, + smu_v15_0_8_get_system_metrics_size(), 5); + + if (ret) + return ret; + + /* Initialize GPU board temperature metrics */ + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, + sizeof(*gpuboard_temp_metrics), 50); + if (ret) { + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); + return ret; + } + gpuboard_temp_metrics = (struct smu_v15_0_8_gpuboard_temp_metrics *) + smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_v15_0_8_gpuboard_temp_metrics_init(gpuboard_temp_metrics, 1, 1); + smu_table->metrics_table = no_free_ptr(metrics_table); smu_table->driver_pptable = no_free_ptr(driver_pptable); @@ -252,6 +280,8 @@ static int smu_v15_0_8_tables_fini(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); mutex_destroy(&smu_table->metrics_lock); return 0; @@ -487,6 +517,33 @@ static int smu_v15_0_8_thermal_get_temperature(struct smu_context *smu, return ret; } +static int smu_v15_0_8_get_system_metrics_table(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *table = &smu_table->driver_table; + struct smu_table *tables = smu_table->tables; + struct smu_table *sys_table; + int ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + if (smu_table_cache_is_valid(sys_table)) + return 0; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); + if (ret) { + dev_info(smu->adev->dev, + "Failed to export system metrics table!\n"); + return ret; + } + + amdgpu_hdp_invalidate(smu->adev, NULL); + smu_table_cache_update_time(sys_table, jiffies); + memcpy(sys_table->cache.buffer, table->cpu_addr, + sizeof(SystemMetricsTable_t)); + + return 0; +} + static int smu_v15_0_8_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, void *data, uint32_t *size) @@ -1292,6 +1349,115 @@ static int smu_v15_0_8_mode2_reset(struct smu_context *smu) return ret; } +static bool smu_v15_0_8_is_temp_metrics_supported(struct smu_context *smu, + enum smu_temp_metric_type type) +{ + switch (type) { + case SMU_TEMP_METRIC_GPUBOARD: + return true; + default: + return false; + } +} + +static void smu_v15_0_8_fill_gpuboard_temp_metrics( + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics, + const SystemMetricsTable_t *metrics) +{ + gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; + gpuboard_temp_metrics->label_version = metrics->LabelVersion; + gpuboard_temp_metrics->node_id = metrics->NodeIdentifier; + + gpuboard_temp_metrics->node_temp_retimer = + metrics->NodeTemperatures[NODE_TEMP_RETIMER]; + gpuboard_temp_metrics->node_temp_ibc = + metrics->NodeTemperatures[NODE_TEMP_IBC_TEMP]; + gpuboard_temp_metrics->node_temp_ibc_2 = + metrics->NodeTemperatures[NODE_TEMP_IBC_2_TEMP]; + gpuboard_temp_metrics->node_temp_vdd18_vr = + metrics->NodeTemperatures[NODE_TEMP_VDD18_VR_TEMP]; + gpuboard_temp_metrics->node_temp_04_hbm_b_vr = + metrics->NodeTemperatures[NODE_TEMP_04_HBM_B_VR_TEMP]; + gpuboard_temp_metrics->node_temp_04_hbm_d_vr = + metrics->NodeTemperatures[NODE_TEMP_04_HBM_D_VR_TEMP]; + + gpuboard_temp_metrics->vr_temp_vddcr_socio_a = + metrics->VrTemperatures[SVI_PLANE_VDDCR_SOCIO_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_socio_c = + metrics->VrTemperatures[SVI_PLANE_VDDCR_SOCIO_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_x0 = + metrics->VrTemperatures[SVI_PLANE_VDDCR_X0_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_x1 = + metrics->VrTemperatures[SVI_PLANE_VDDCR_X1_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDIO_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDIO_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_04_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDIO_04_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_04_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDIO_04_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDCR_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDCR_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_075_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_075_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_11_gta_a = + metrics->VrTemperatures[SVI_PLANE_VDDIO_11_GTA_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_11_gta_c = + metrics->VrTemperatures[SVI_PLANE_VDDIO_11_GTA_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddan_075_gta_a = + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_GTA_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddan_075_gta_c = + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_GTA_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_075_ucie = + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_UCIE_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_065_ucieaa = + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAA_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_065_ucieam_a = + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAM_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_065_ucieam_c = + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAM_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddan_075 = + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_TEMP]; +} + +static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu, + enum smu_temp_metric_type type, + void *table) +{ + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + enum smu_driver_table_id table_id; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + ssize_t size; + int ret; + + table_id = SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS; + gpuboard_temp_metrics = + (struct smu_v15_0_8_gpuboard_temp_metrics *) + smu_driver_table_ptr(smu, table_id); + size = sizeof(*gpuboard_temp_metrics); + + ret = smu_v15_0_8_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + smu_driver_table_update_cache_time(smu, table_id); + + smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, + metrics); + memcpy(table, gpuboard_temp_metrics, size); + return size; +} + static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; @@ -1954,6 +2120,11 @@ static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, ctl->message_map = message_map; } +static const struct smu_temp_funcs smu_v15_0_8_temp_funcs = { + .temp_metrics_is_supported = smu_v15_0_8_is_temp_metrics_supported, + .get_temp_metrics = smu_v15_0_8_get_temp_metrics, +}; + void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &smu_v15_0_8_ppt_funcs; @@ -1961,5 +2132,6 @@ void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu) smu->feature_map = smu_v15_0_8_feature_mask_map; smu->table_map = smu_v15_0_8_table_map; smu_v15_0_8_init_msg_ctl(smu, smu_v15_0_8_message_map); + smu->smu_temp.temp_funcs = &smu_v15_0_8_temp_funcs; smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0_8; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h index 8fc16796788b5..0856d11d8e55e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -180,5 +180,76 @@ typedef struct { SMU_15_0_8_MAX_XCC); DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); + +/* Maximum temperature sensor counts for system metrics */ +#define SMU_15_0_8_MAX_NODE_TEMP_ENTRIES 12 +#define SMU_15_0_8_MAX_VR_TEMP_ENTRIES 22 + +/* SMUv 15.0.8 GPU board temperature metrics */ +#define SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(LABEL_VERSION), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), label_version); \ + SMU_SCALAR(SMU_MATTR(NODE_ID), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), node_id); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_RETIMER), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_retimer); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_IBC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_ibc); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_IBC_2), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_ibc_2); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_VDD18_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_vdd18_vr); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_04_HBM_B_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_04_hbm_b_vr); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_04_HBM_D_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_04_hbm_d_vr); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_SOCIO_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_socio_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_SOCIO_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_socio_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_X0), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_x0); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_X1), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_x1); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_04_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_04_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_04_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_04_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_075_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_075_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_11_GTA_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_11_gta_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_11_GTA_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_11_gta_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075_GTA_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddan_075_gta_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075_GTA_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddan_075_gta_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_UCIE), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_075_ucie); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAA), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_065_ucieaa); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAM_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_065_ucieam_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAM_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_065_ucieam_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddan_075); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, + SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS); + #endif #endif From 74781687d607c5c340eb5630b2c54e41b1c4b1bf Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 30 Jan 2026 21:18:29 +0800 Subject: [PATCH 2016/2070] drm/amd/pm: Add baseboard temperature metrics support Add baseboard temperature metrics support via system metrics table for smu_v15_0_8 v4: Add separate function to fill baseboard temperature, use 16, remove casting v5: Optimize to use single switch case (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/kgd_pp_interface.h | 29 +++++ .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 110 +++++++++++++++--- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h | 58 +++++++++ 3 files changed, 184 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 3f00e99088c27..2e931aa89726d 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -628,6 +628,29 @@ enum amdgpu_metrics_attr_id { AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FRONT, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_BACK, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM7, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_IBC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_UFPGA, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM1, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_2_3_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_6_7_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_0V72_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_3V3_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_2_3_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_6_7_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC, AMDGPU_METRICS_ATTR_ID_MAX, }; @@ -1886,4 +1909,10 @@ struct amdgpu_gpuboard_temp_metrics_v1_1 { struct gpu_metrics_attr metrics_attrs[]; }; +struct amdgpu_baseboard_temp_metrics_v1_1 { + struct metrics_table_header common_header; + int attr_count; + struct gpu_metrics_attr metrics_attrs[]; +}; + #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 4c1a8f37d12cb..c850578f735c0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -178,6 +178,7 @@ static size_t smu_v15_0_8_get_system_metrics_size(void) static int smu_v15_0_8_tables_init(struct smu_context *smu) { + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics; struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; struct smu_table_context *smu_table = &smu->smu_table; int ret, gpu_metrcs_size = sizeof(MetricsTable_t); @@ -223,11 +224,23 @@ static int smu_v15_0_8_tables_init(struct smu_context *smu) if (ret) return ret; + /* Initialize base board temperature metrics */ + ret = smu_driver_table_init(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS, + sizeof(*baseboard_temp_metrics), 50); + if (ret) + return ret; + baseboard_temp_metrics = (struct smu_v15_0_8_baseboard_temp_metrics *) + smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_v15_0_8_baseboard_temp_metrics_init(baseboard_temp_metrics, 1, 1); /* Initialize GPU board temperature metrics */ ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, sizeof(*gpuboard_temp_metrics), 50); if (ret) { smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); + smu_driver_table_fini(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); return ret; } gpuboard_temp_metrics = (struct smu_v15_0_8_gpuboard_temp_metrics *) @@ -280,6 +293,7 @@ static int smu_v15_0_8_tables_fini(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); mutex_destroy(&smu_table->metrics_lock); @@ -1353,6 +1367,10 @@ static bool smu_v15_0_8_is_temp_metrics_supported(struct smu_context *smu, enum smu_temp_metric_type type) { switch (type) { + case SMU_TEMP_METRIC_BASEBOARD: + if (smu->adev->gmc.xgmi.physical_node_id == 0) + return true; + return false; case SMU_TEMP_METRIC_GPUBOARD: return true; default: @@ -1360,6 +1378,62 @@ static bool smu_v15_0_8_is_temp_metrics_supported(struct smu_context *smu, } } +static void smu_v15_0_8_fill_baseboard_temp_metrics( + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics, + const SystemMetricsTable_t *metrics) +{ + baseboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; + baseboard_temp_metrics->label_version = metrics->LabelVersion; + baseboard_temp_metrics->node_id = metrics->NodeIdentifier; + + baseboard_temp_metrics->system_temp_ubb_fpga = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA]; + baseboard_temp_metrics->system_temp_ubb_front = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FRONT]; + baseboard_temp_metrics->system_temp_ubb_back = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_BACK]; + baseboard_temp_metrics->system_temp_ubb_oam7 = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_OAM7]; + baseboard_temp_metrics->system_temp_ubb_ibc = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_IBC]; + baseboard_temp_metrics->system_temp_ubb_ufpga = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_UFPGA]; + baseboard_temp_metrics->system_temp_ubb_oam1 = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_OAM1]; + baseboard_temp_metrics->system_temp_oam_0_1_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_0_1_HSC]; + baseboard_temp_metrics->system_temp_oam_2_3_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_2_3_HSC]; + baseboard_temp_metrics->system_temp_oam_4_5_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_4_5_HSC]; + baseboard_temp_metrics->system_temp_oam_6_7_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_6_7_HSC]; + baseboard_temp_metrics->system_temp_ubb_fpga_0v72_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA_0V72_VR]; + baseboard_temp_metrics->system_temp_ubb_fpga_3v3_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA_3V3_VR]; + baseboard_temp_metrics->system_temp_retimer_0_1_2_3_1v2_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR]; + baseboard_temp_metrics->system_temp_retimer_4_5_6_7_1v2_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR]; + baseboard_temp_metrics->system_temp_retimer_0_1_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_0_1_0V9_VR]; + baseboard_temp_metrics->system_temp_retimer_4_5_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_4_5_0V9_VR]; + baseboard_temp_metrics->system_temp_retimer_2_3_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_2_3_0V9_VR]; + baseboard_temp_metrics->system_temp_retimer_6_7_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_6_7_0V9_VR]; + baseboard_temp_metrics->system_temp_oam_0_1_2_3_3v3_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR]; + baseboard_temp_metrics->system_temp_oam_4_5_6_7_3v3_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR]; + baseboard_temp_metrics->system_temp_ibc_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_IBC_HSC]; + baseboard_temp_metrics->system_temp_ibc = + metrics->SystemTemperatures[SYSTEM_TEMP_IBC]; +} + static void smu_v15_0_8_fill_gpuboard_temp_metrics( struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics, const SystemMetricsTable_t *metrics) @@ -1429,33 +1503,43 @@ static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu, enum smu_temp_metric_type type, void *table) { + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics; struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; - enum smu_driver_table_id table_id; SystemMetricsTable_t *metrics; struct smu_table *sys_table; - ssize_t size; int ret; - table_id = SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS; - gpuboard_temp_metrics = - (struct smu_v15_0_8_gpuboard_temp_metrics *) - smu_driver_table_ptr(smu, table_id); - size = sizeof(*gpuboard_temp_metrics); - ret = smu_v15_0_8_get_system_metrics_table(smu); if (ret) return ret; sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; - smu_driver_table_update_cache_time(smu, table_id); - smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, - metrics); - memcpy(table, gpuboard_temp_metrics, size); - return size; + switch (type) { + case SMU_TEMP_METRIC_GPUBOARD: + gpuboard_temp_metrics = + (struct smu_v15_0_8_gpuboard_temp_metrics *) + smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, + metrics); + memcpy(table, gpuboard_temp_metrics, sizeof(*gpuboard_temp_metrics)); + return sizeof(*gpuboard_temp_metrics); + case SMU_TEMP_METRIC_BASEBOARD: + baseboard_temp_metrics = + (struct smu_v15_0_8_baseboard_temp_metrics *) + smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_v15_0_8_fill_baseboard_temp_metrics(baseboard_temp_metrics, + metrics); + memcpy(table, baseboard_temp_metrics, sizeof(*baseboard_temp_metrics)); + return sizeof(*baseboard_temp_metrics); + default: + return -EINVAL; + } } static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h index 0856d11d8e55e..398ce44821741 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -182,6 +182,7 @@ typedef struct { DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); /* Maximum temperature sensor counts for system metrics */ +#define SMU_15_0_8_MAX_SYSTEM_TEMP_ENTRIES 32 #define SMU_15_0_8_MAX_NODE_TEMP_ENTRIES 12 #define SMU_15_0_8_MAX_VR_TEMP_ENTRIES 22 @@ -251,5 +252,62 @@ DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS); +/* SMUv 15.0.8 Baseboard temperature metrics - ID-based approach */ +#define SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(LABEL_VERSION), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), label_version); \ + SMU_SCALAR(SMU_MATTR(NODE_ID), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), node_id); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_fpga); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FRONT), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_front); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_BACK), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_back); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_OAM7), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_oam7); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_IBC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_ibc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_UFPGA), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_ufpga); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_OAM1), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_oam1); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_0_1_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_0_1_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_2_3_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_2_3_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_4_5_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_4_5_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_6_7_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_6_7_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA_0V72_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_fpga_0v72_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA_3V3_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_fpga_3v3_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_0_1_2_3_1v2_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_4_5_6_7_1v2_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_0_1_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_0_1_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_4_5_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_4_5_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_2_3_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_2_3_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_6_7_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_6_7_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_0_1_2_3_3v3_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_4_5_6_7_3v3_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_IBC_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ibc_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_IBC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ibc); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_baseboard_temp_metrics, + SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS); #endif #endif From ed3fd2e10a93eeaeb7de4d71ce6bbf6283b52f3b Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 30 Jan 2026 21:20:58 +0800 Subject: [PATCH 2017/2070] drm/amd/pm: Add NPM support for smu_v15_0_8 Add node power management support for smu_v15_0_8 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index c850578f735c0..13c2b0cb7ad19 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -558,6 +558,46 @@ static int smu_v15_0_8_get_system_metrics_table(struct smu_context *smu) return 0; } +static int smu_v15_0_8_get_npm_data(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + int ret; + + if (sensor == AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT) { + /*TBD as of now put 0 */ + *value = 0; + return 0; + } + + ret = smu_v15_0_8_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + + switch (sensor) { + case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: + *value = SMUQ10_ROUND(metrics->NodePowerLimit); + break; + case AMDGPU_PP_SENSOR_NODEPOWER: + *value = SMUQ10_ROUND(metrics->NodePower); + break; + case AMDGPU_PP_SENSOR_GPPTRESIDENCY: + *value = SMUQ10_ROUND(metrics->GlobalPPTResidencyAcc); + break; + default: + return -EINVAL; + } + + return 0; +} + static int smu_v15_0_8_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, void *data, uint32_t *size) @@ -607,6 +647,15 @@ static int smu_v15_0_8_read_sensor(struct smu_context *smu, *(uint32_t *)data = dpm_context->board_volt; *size = 4; break; + case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: + case AMDGPU_PP_SENSOR_NODEPOWER: + case AMDGPU_PP_SENSOR_GPPTRESIDENCY: + case AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT: + ret = smu_v15_0_8_get_npm_data(smu, sensor, (uint32_t *)data); + if (ret) + return ret; + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: default: ret = -EOPNOTSUPP; From 412746fb2452a35596a61b465a423db2c5cb2028 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sun, 2 Nov 2025 19:55:53 +0800 Subject: [PATCH 2018/2070] drm/amdgpu: Add smu v15_0_8 ip block Add smu v15_0_8 ip block Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 6cc8b52afc6a7..61e2919bf19e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2360,6 +2360,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); break; case IP_VERSION(15, 0, 0): + case IP_VERSION(15, 0, 8): amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); break; default: diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index fc35c0242fc8e..27a2aad4ef863 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -803,6 +803,9 @@ static int smu_set_funcs(struct amdgpu_device *adev) case IP_VERSION(15, 0, 0): smu_v15_0_0_set_ppt_funcs(smu); break; + case IP_VERSION(15, 0, 8): + smu_v15_0_8_set_ppt_funcs(smu); + break; default: return -EINVAL; } From cfe6753140e1bac1a713c4fef772b8d4143ce83b Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 7 Jan 2026 11:50:21 +0800 Subject: [PATCH 2019/2070] drm/amd/pm: Enable user specified gfx clock ranges Enable user specified gfx clock ranges for smu_15_0_8 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 27a2aad4ef863..4a69f2c0d1dde 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -805,6 +805,7 @@ static int smu_set_funcs(struct amdgpu_device *adev) break; case IP_VERSION(15, 0, 8): smu_v15_0_8_set_ppt_funcs(smu); + smu->od_enabled = true; break; default: return -EINVAL; From 805bb54d0cd13b7393c04cad86b434568b11f929 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 23 Mar 2026 21:16:39 +0800 Subject: [PATCH 2020/2070] drm/amdkcl: add removed pci_release_resource for legacy kernels It's caused by db92e3fef53e2083001dcc4c86a3ecff4ab4dc4e "drm/amdgpu: Remove driver side BAR release before resize" Commit db92e3fef53e removed explicit calls to pci_release_resource and pci_assign_unassigned_bus_resources inside amdgpu_device_resize_fb_bar.In environments falling back to the legacy PCI resize path (where HAVE_PCI_RESIZE_RESOURCE_ALIGN is undefined), relying only on pci_resize_resource without prior resource release causes the BAR resize operation to fail due to resource conflicts or insufficient address space. Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b0aac25278003..4a15a0b89def9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1190,9 +1190,19 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) r = pci_resize_resource(adev->pdev, 0, rbar_size, (adev->asic_type >= CHIP_BONAIRE) ? 1 << 5 : 1 << 2); + + if (r == -ENOSPC) + dev_info(adev->dev, + "Not enough PCI address space for a large BAR."); + else if (r && r != -ENOTSUPP) + dev_err(adev->dev, "Problem resizing BAR0 (%d).", r); #else + if (adev->asic_type >= CHIP_BONAIRE) + pci_release_resource(adev->pdev, 2); + + pci_release_resource(adev->pdev, 0); + r = pci_resize_resource(adev->pdev, 0, rbar_size); -#endif if (r == -ENOSPC) dev_info(adev->dev, @@ -1200,6 +1210,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) else if (r && r != -ENOTSUPP) dev_err(adev->dev, "Problem resizing BAR0 (%d).", r); + pci_assign_unassigned_bus_resources(adev->pdev->bus); +#endif + /* When the doorbell or fb BAR isn't available we have no chance of * using the device. */ From b5c787c09b75c53a79cc666da58803dd65a13c76 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 23 Mar 2026 13:17:58 +0800 Subject: [PATCH 2021/2070] drm/amdkcl: fix "Argument list too long" for large modules in DKMS build amdgpu has 700+ .o files, causing two build failures on older kernels (< 5.19) where Kbuild's cmd_mod uses shell echo: 1. E2BIG: shell echo in cmd_mod and cmd_link_multi-m exceeds ARG_MAX. 2. ENAMETOOLONG: RHEL modpost reads .mod as single-line path, exceeding PATH_MAX (4096) when the concatenated .o list reaches ~65KB. The upstream fix is commit c6031b1dbbbf ("kbuild: make *.mod rule robust against too long argument error"), merged in v5.19, which replaced cmd_mod with printf piped through awk. Kernels before v5.19 still use echo with all .o paths expanded inline as shell arguments. Add cmd_mod_fix.mk which overrides cmd_mod and cmd_link_multi-m using GNU Make's $(file) builtin (bypasses shell entirely) and writes one .o per line in .mod files (avoids RHEL modpost PATH_MAX issue). pre-build.sh unconditionally injects the include into amd/amdgpu/Makefile to cover the recursive make context where the large module is linked; cmd_mod_fix.mk itself detects whether the fix is needed and is a no-op on newer kernels. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk | 27 +++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 6 ++++++ 2 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk diff --git a/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk b/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk new file mode 100644 index 0000000000000..9968b0a30aa2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk @@ -0,0 +1,27 @@ +# Fix E2BIG/ENAMETOOLONG for amdgpu on kernels < 5.19: use $(file) instead +# of shell echo in cmd_mod, and write one .o per line in .mod files. +# +# $(subst $(space),$(newline),...) inside $(file) silently drops newlines, +# so we use $(file >) for the first entry and $(file >>) for the rest. + +ifndef _amdgpu_cmd_mod_fix_included +_amdgpu_cmd_mod_fix_included := 1 + +_kbuild_makefile_build := $(srctree)/scripts/Makefile.build +_cmd_mod_needs_fix := $(shell grep -q 'cmd_mod = printf' $(_kbuild_makefile_build) 2>/dev/null || echo 1) + +ifeq ($(_cmd_mod_needs_fix),1) + +_amdgpu_mod_objs = $(sort $(strip $(if $($*-objs)$($*-y)$($*-m),$(addprefix $(obj)/,$($*-objs) $($*-y) $($*-m)),$(@:.mod=.o)))) + +override quiet_cmd_mod = MOD $@ +override cmd_mod = $(file >$@,$(firstword $(_amdgpu_mod_objs))) \ + $(foreach o,$(wordlist 2,$(words $(_amdgpu_mod_objs)),$(_amdgpu_mod_objs)),$(file >>$@,$(o))) \ + true $(if $(cmd_undef_syms),; $(cmd_undef_syms)) + +override quiet_cmd_link_multi-m = LD [M] $@ +override cmd_link_multi-m = $(file >$@.args, $(filter %.o,$^)) \ + $(LD) $(ld_flags) -r -o $@ @$@.args + +endif +endif diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index f69be8865e1b8..f1b345835ed37 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -89,6 +89,12 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild done +# Fix "Argument list too long" in recursive make for large modules (700+ .o files). +# Makefile.build recurses into subdirectories via sub-makes that don't inherit +# overrides. Inject the include into amd/amdgpu/Makefile; cmd_mod_fix.mk itself +# checks whether the fix is needed and is a no-op on newer kernels. +sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile + export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env From a7c38b0c9fc3b05c49075de96877ae6264d103de Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 20 Mar 2026 14:36:11 +0800 Subject: [PATCH 2022/2070] drm/amdkcl: fake dma_fence_unwrap_merge() It's caused by the commits: d15b09f "drm/amdgpu: fix some more bug in amdgpu_gem_va_ioctl" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c | 95 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 | 16 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_unwrap.h | 15 +++ 5 files changed, 130 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c index cb179499f98e9..242a5bcc44171 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c @@ -5,6 +5,9 @@ * Scatterlist handling helpers. */ #include +#include +#include +#include #include #ifndef HAVE_DMA_FENCE_DEDUP_ARRAY @@ -61,4 +64,96 @@ int kcl_dma_fence_dedup_array(struct dma_fence **fences, int num_fences) } EXPORT_SYMBOL_GPL(kcl_dma_fence_dedup_array); +#endif + +#ifndef HAVE_DMA_FENCE_UNWRAP_MERGE +/* Implementation for the dma_fence_unwrap_merge() macro, don't use directly */ +struct dma_fence *kcl__dma_fence_unwrap_merge(unsigned int num_fences, + struct dma_fence **fences, + struct dma_fence_unwrap *iter) +{ + struct dma_fence *tmp, *unsignaled = NULL, **array; + struct dma_fence_array *result; + ktime_t timestamp; + int i, count; + + count = 0; + timestamp = ns_to_ktime(0); + for (i = 0; i < num_fences; ++i) { + dma_fence_unwrap_for_each(tmp, &iter[i], fences[i]) { + if (!dma_fence_is_signaled(tmp)) { + dma_fence_put(unsignaled); + unsignaled = dma_fence_get(tmp); + ++count; + } else { + ktime_t t = dma_fence_timestamp(tmp); + + if (ktime_after(t, timestamp)) + timestamp = t; + } + } + } + + /* + * If we couldn't find a pending fence just return a private signaled + * fence with the timestamp of the last signaled one. + * + * Or if there was a single unsignaled fence left we can return it + * directly and early since that is a major path on many workloads. + */ + if (count == 0) + return dma_fence_get_stub(); + else if (count == 1) + return unsignaled; + + dma_fence_put(unsignaled); + + array = kmalloc_array(count, sizeof(*array), GFP_KERNEL); + if (!array) + return NULL; + + count = 0; + for (i = 0; i < num_fences; ++i) { + dma_fence_unwrap_for_each(tmp, &iter[i], fences[i]) { + if (!dma_fence_is_signaled(tmp)) { + array[count++] = dma_fence_get(tmp); + } else { + ktime_t t = dma_fence_timestamp(tmp); + + if (ktime_after(t, timestamp)) + timestamp = t; + } + } + } + + if (count == 0 || count == 1) + goto return_fastpath; + + count = dma_fence_dedup_array(array, count); + + if (count > 1) { + result = dma_fence_array_create(count, array, + dma_fence_context_alloc(1), + 1, false); + if (!result) { + for (i = 0; i < count; i++) + dma_fence_put(array[i]); + tmp = NULL; + goto return_tmp; + } + return &result->base; + } + +return_fastpath: + if (count == 0) + tmp = dma_fence_get_stub(); + else + tmp = array[0]; + +return_tmp: + kfree(array); + return tmp; +} +EXPORT_SYMBOL_GPL(kcl__dma_fence_unwrap_merge); + #endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a46c8c22eea1e..87dbaae9c689a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -154,6 +154,9 @@ /* dma_fence_dedup_array() is available */ #define HAVE_DMA_FENCE_DEDUP_ARRAY 1 +/* dma_fence_unwrap_merge() is available */ +#define HAVE_DMA_FENCE_UNWRAP_MERGE 1 + /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 new file mode 100644 index 0000000000000..6f688ea3032f8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc2-285-g245a4a7b531c +dnl # dma-buf: generalize dma_fence unwrap & merging v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_UNWRAP_MERGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + __dma_fence_unwrap_merge(0, NULL, NULL); + ], [__dma_fence_unwrap_merge], [drivers/dma-buf/dma-fence-unwrap.c],[ + AC_DEFINE(HAVE_DMA_FENCE_UNWRAP_MERGE, 1, + [dma_fence_unwrap_merge() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1259d9c6ee6d3..2b78755675f3f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -257,6 +257,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY + AC_AMDGPU_DMA_FENCE_UNWRAP_MERGE AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL diff --git a/include/kcl/kcl_dma_fence_unwrap.h b/include/kcl/kcl_dma_fence_unwrap.h index 7c7cac6616168..58e0503d6d852 100644 --- a/include/kcl/kcl_dma_fence_unwrap.h +++ b/include/kcl/kcl_dma_fence_unwrap.h @@ -99,4 +99,19 @@ int kcl_dma_fence_dedup_array(struct dma_fence **array, int num_fences); #define dma_fence_dedup_array kcl_dma_fence_dedup_array #endif + +#ifndef HAVE_DMA_FENCE_UNWRAP_MERGE +struct dma_fence *kcl__dma_fence_unwrap_merge(unsigned int num_fences, + struct dma_fence **fences, + struct dma_fence_unwrap *cursors); + +#define kcl_dma_fence_unwrap_merge(...) \ + ({ \ + struct dma_fence *__f[] = { __VA_ARGS__ }; \ + struct dma_fence_unwrap __c[ARRAY_SIZE(__f)]; \ + \ + kcl__dma_fence_unwrap_merge(ARRAY_SIZE(__f), __f, __c); \ + }) +#define dma_fence_unwrap_merge kcl_dma_fence_unwrap_merge +#endif #endif From ed6aaf7ef2f9c23c5d113d265fa5c0e11bdc6a99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 3 Feb 2026 17:30:57 +0100 Subject: [PATCH 2023/2070] drm/amdgpu: fix some more bug in amdgpu_gem_va_ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some illegal combination of input flags were not checked and we need to take the PDEs into account when returning the fence as well. Signed-off-by: Christian König Acked-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 76 +++++++++++-------------- 1 file changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5db51d7ff00ce..8e7c04fb4435d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -893,11 +894,10 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, struct amdgpu_vm *vm = &fpriv->vm; int r = 0; - /* Always start from the VM's existing last update fence. */ - fence = dma_fence_get(vm->last_update); - + /* If the VM is not ready return only a stub. */ if (!amdgpu_vm_ready(vm)) - return fence; + return dma_fence_get_stub(); + /* * First clean up any freed mappings in the VM. @@ -906,7 +906,7 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, * schedules GPU work. If nothing needs clearing, @fence can remain as * the original vm->last_update. */ - r = amdgpu_vm_clear_freed(adev, vm, &fence); + r = amdgpu_vm_clear_freed(adev, vm, &vm->last_update); if (r) goto error; @@ -940,47 +940,34 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, } } - /* - * Decide which fence best represents the last update: - * - * MAP/REPLACE: - * - For always-valid mappings, use vm->last_update. - * - Otherwise, export bo_va->last_pt_update. - * - * UNMAP/CLEAR: - * Keep the fence returned by amdgpu_vm_clear_freed(). If no work was - * needed, it can remain as vm->last_pt_update. - * - * The VM and BO update fences are always initialized to a valid value. - * vm->last_update and bo_va->last_pt_update always start as valid fences. - * and are never expected to be NULL. - */ - switch (operation) { - case AMDGPU_VA_OP_MAP: - case AMDGPU_VA_OP_REPLACE: + if ((operation == AMDGPU_VA_OP_MAP || + operation == AMDGPU_VA_OP_REPLACE) && + !amdgpu_vm_is_bo_always_valid(vm, bo_va->base.bo)) { + /* - * For MAP/REPLACE, return the page table update fence for the - * mapping we just modified. bo_va is expected to be valid here. + * For MAP/REPLACE of non per-VM BOs we need to sync to both the + * bo_va->last_pt_update and vm->last_update or otherwise we + * potentially miss the PDE updates. */ - dma_fence_put(fence); - - if (amdgpu_vm_is_bo_always_valid(vm, bo_va->base.bo)) - fence = dma_fence_get(vm->last_update); - else - fence = dma_fence_get(bo_va->last_pt_update); - break; - case AMDGPU_VA_OP_UNMAP: - case AMDGPU_VA_OP_CLEAR: - default: - /* keep @fence as returned by amdgpu_vm_clear_freed() */ - break; + fence = dma_fence_unwrap_merge(vm->last_update, + bo_va->last_pt_update); + if (!fence) { + /* As fallback in OOM situations */ + dma_fence_wait(vm->last_update, false); + dma_fence_wait(bo_va->last_pt_update, false); + fence = dma_fence_get_stub(); + } + } else { + fence = dma_fence_get(vm->last_update); } + return fence; + error: if (r && r != -ERESTARTSYS) DRM_ERROR("Couldn't update BO_VA (%d)\n", r); - return fence; + return dma_fence_get(vm->last_update); } int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, @@ -1001,7 +988,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct amdgpu_bo_va *bo_va; struct drm_syncobj *timeline_syncobj = NULL; struct dma_fence_chain *timeline_chain = NULL; - struct dma_fence *fence; struct drm_exec exec; uint64_t vm_size; int r = 0; @@ -1053,6 +1039,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } + if (args->flags & AMDGPU_VM_DELAY_UPDATE && + args->vm_timeline_syncobj_out) + return -EINVAL; + if ((args->operation != AMDGPU_VA_OP_CLEAR) && !(args->flags & AMDGPU_VM_PAGE_PRT)) { gobj = drm_gem_object_lookup(filp, args->handle); @@ -1142,11 +1132,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, * that represents the last relevant update for this mapping. This * fence can then be exported to the user-visible VM timeline. */ - if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) { + if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && + (!adev->debug_vm || timeline_syncobj)) { + struct dma_fence *fence; + fence = amdgpu_gem_va_update_vm(adev, fpriv, bo_va, args->operation); - - if (timeline_syncobj && fence) { + if (timeline_syncobj) { if (!args->vm_timeline_point) { /* Replace the existing fence when no point is given. */ drm_syncobj_replace_fence(timeline_syncobj, From 58f5a3626ff2929a67663896b2640bf2b4de6c87 Mon Sep 17 00:00:00 2001 From: Hou Wenlong Date: Mon, 16 Mar 2026 11:46:29 +0800 Subject: [PATCH 2024/2070] drm/amd/display: Rename enum 'pixel_format' to 'dc_pixel_format' Rename the enum 'pixel_format' to 'dc_pixel_format' to avoid potential name conflicts with the pixel_format struct defined in include/video/pixel_format.h. Signed-off-by: Hou Wenlong Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 3 ++- drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +- 7 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 8271b12c1a66d..727bcf08a84fb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -749,10 +749,10 @@ struct clock_source *resource_find_used_clk_src_for_sharing( return NULL; } -static enum pixel_format convert_pixel_format_to_dalsurface( +static enum dc_pixel_format convert_pixel_format_to_dalsurface( enum surface_pixel_format surface_pixel_format) { - enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; + enum dc_pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; switch (surface_pixel_format) { case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 595e082db2816..c2ca08d26e371 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -218,7 +218,7 @@ enum surface_pixel_format { /* Pixel format */ -enum pixel_format { +enum dc_pixel_format { /*graph*/ PIXEL_FORMAT_UNINITIALIZED, PIXEL_FORMAT_INDEX8, diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index ba7bf23f2b2fd..52ed8deebf635 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -63,7 +63,8 @@ static void populate_inits_from_splinits(struct scl_inits *inits, inits->h_c = dc_fixpt_from_int_dy(spl_inits->h_filter_init_int_c, spl_inits->h_filter_init_frac_c >> 5, 0, 19); inits->v_c = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int_c, spl_inits->v_filter_init_frac_c >> 5, 0, 19); } -static void populate_splformat_from_format(enum spl_pixel_format *spl_pixel_format, const enum pixel_format pixel_format) +static void populate_splformat_from_format(enum spl_pixel_format *spl_pixel_format, + const enum dc_pixel_format pixel_format) { if (pixel_format < PIXEL_FORMAT_INVALID) *spl_pixel_format = (enum spl_pixel_format)pixel_format; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c index 808bca9fb8044..0d2c9fcd3362c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c @@ -102,7 +102,7 @@ static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) } } -static bool dpp1_dscl_is_video_format(enum pixel_format format) +static bool dpp1_dscl_is_video_format(enum dc_pixel_format format) { if (format >= PIXEL_FORMAT_VIDEO_BEGIN && format <= PIXEL_FORMAT_VIDEO_END) @@ -111,7 +111,7 @@ static bool dpp1_dscl_is_video_format(enum pixel_format format) return false; } -static bool dpp1_dscl_is_420_format(enum pixel_format format) +static bool dpp1_dscl_is_420_format(enum dc_pixel_format format) { if (format == PIXEL_FORMAT_420BPP8 || format == PIXEL_FORMAT_420BPP10) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 8b6155f9122f8..8b7e55e337d35 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -94,7 +94,7 @@ static int dpp401_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) } } -static bool dpp401_dscl_is_video_format(enum pixel_format format) +static bool dpp401_dscl_is_video_format(enum dc_pixel_format format) { if (format >= PIXEL_FORMAT_VIDEO_BEGIN && format <= PIXEL_FORMAT_VIDEO_END) @@ -103,7 +103,7 @@ static bool dpp401_dscl_is_video_format(enum pixel_format format) return false; } -static bool dpp401_dscl_is_420_format(enum pixel_format format) +static bool dpp401_dscl_is_420_format(enum dc_pixel_format format) { if (format == PIXEL_FORMAT_420BPP8 || format == PIXEL_FORMAT_420BPP10) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index b152f68794954..51581c10fd6bf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -256,7 +256,7 @@ struct default_adjustment { enum dc_color_space out_color_space; enum dc_color_space in_color_space; enum dc_color_depth color_depth; - enum pixel_format surface_pixel_format; + enum dc_pixel_format surface_pixel_format; enum graphics_csc_adjust_type csc_adjust_type; bool force_hw_default; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 5a1d9b708a9d9..30990355985dd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -160,7 +160,7 @@ struct scaler_data { struct scaling_ratios ratios; struct scl_inits inits; struct sharpness_adj sharpness; - enum pixel_format format; + enum dc_pixel_format format; struct line_buffer_params lb_params; // Below struct holds the scaler values to program hw registers struct dscl_prog_data dscl_prog_data; From d8324de0b879b844215078c4860055fdb4401ad6 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 23 Feb 2026 16:28:22 +0530 Subject: [PATCH 2025/2070] drm/amdgpu: Use stack variable to fetch nps info Instead of a dynamic allocation, use stack variable and let the caller pass the maximum ranges that can be held in the buffer. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 23 +++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 10 ++++---- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 61e2919bf19e5..623594d230924 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2001,11 +2001,10 @@ static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, - struct amdgpu_gmc_memrange **ranges, + struct amdgpu_gmc_memrange *ranges, int *range_cnt, bool refresh) { uint8_t *discovery_bin = adev->discovery.bin; - struct amdgpu_gmc_memrange *mem_ranges; struct table_info *info; union nps_info *nps_info; union nps_info nps_data; @@ -2043,22 +2042,22 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, switch (le16_to_cpu(nps_info->v1.header.version_major)) { case 1: - mem_ranges = kvcalloc(nps_info->v1.count, - sizeof(*mem_ranges), - GFP_KERNEL); - if (!mem_ranges) - return -ENOMEM; *nps_type = nps_info->v1.nps_type; + if (*range_cnt < nps_info->v1.count) { + dev_dbg(adev->dev, + "not enough space for nps ranges: %d < %d\n", + *range_cnt, nps_info->v1.count); + return -ENOSPC; + } *range_cnt = nps_info->v1.count; for (i = 0; i < *range_cnt; i++) { - mem_ranges[i].base_address = + ranges[i].base_address = nps_info->v1.instance_info[i].base_address; - mem_ranges[i].limit_address = + ranges[i].limit_address = nps_info->v1.instance_info[i].limit_address; - mem_ranges[i].nid_mask = -1; - mem_ranges[i].flags = 0; + ranges[i].nid_mask = -1; + ranges[i].flags = 0; } - *ranges = mem_ranges; break; default: dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index a7aeb47887a34..0ff1a7923eedf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -46,7 +46,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev); int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, - struct amdgpu_gmc_memrange **ranges, + struct amdgpu_gmc_memrange *ranges, int *range_cnt, bool refresh); void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 685139592e262..a3e452753c872 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1387,18 +1387,18 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges, uint8_t *exp_ranges) { - struct amdgpu_gmc_memrange *ranges; + struct amdgpu_gmc_memrange ranges[AMDGPU_MAX_MEM_RANGES]; int range_cnt, ret, i, j; uint32_t nps_type; bool refresh; if (!mem_ranges || !exp_ranges) return -EINVAL; - + range_cnt = AMDGPU_MAX_MEM_RANGES; refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS); - ret = amdgpu_discovery_get_nps_info(adev, &nps_type, &ranges, - &range_cnt, refresh); + ret = amdgpu_discovery_get_nps_info(adev, &nps_type, ranges, &range_cnt, + refresh); if (ret) return ret; @@ -1459,8 +1459,6 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, if (!*exp_ranges) *exp_ranges = range_cnt; err: - kvfree(ranges); - return ret; } From 6acf76a09413217d6cead4b3087b1f1b9f9bdbf0 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 19 Mar 2026 21:17:38 -0400 Subject: [PATCH 2026/2070] drm/amd/pm: disable OD_FAN_CURVE if temp or pwm range invalid for smu v13 Forcibly disable the OD_FAN_CURVE feature when temperature or PWM range is invalid, otherwise PMFW will reject this configuration on smu v13.0.x example: $ sudo cat /sys/bus/pci/devices//gpu_od/fan_ctrl/fan_curve OD_FAN_CURVE: 0: 0C 0% 1: 0C 0% 2: 0C 0% 3: 0C 0% 4: 0C 0% OD_RANGE: FAN_CURVE(hotspot temp): 0C 0C FAN_CURVE(fan speed): 0% 0% $ echo "0 50 40" | sudo tee fan_curve kernel log: [ 756.442527] amdgpu 0000:03:00.0: amdgpu: Fan curve temp setting(50) must be within [0, 0]! [ 777.345800] amdgpu 0000:03:00.0: amdgpu: Fan curve temp setting(50) must be within [0, 0]! Closes: https://github.com/ROCm/amdgpu/issues/208 Signed-off-by: Yang Wang Acked-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 33 ++++++++++++++++++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 33 ++++++++++++++++++- 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 19c50f27422df..4ccaff09ad8a7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -59,6 +59,10 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) +static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, + int od_feature_bit, + int32_t *min, int32_t *max); + static const struct smu_feature_bits smu_v13_0_0_dpm_features = { .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), @@ -1044,8 +1048,35 @@ static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu, PPTable_t *pptable = smu->smu_table.driver_pptable; const OverDriveLimits_t * const overdrive_upperlimits = &pptable->SkuTable.OverDriveLimitsBasicMax; + int32_t min_value, max_value; + bool feature_enabled; - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); + switch (od_feature_bit) { + case PP_OD_FEATURE_FAN_CURVE_BIT: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + if (feature_enabled) { + smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + + smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + } + break; + default: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + break; + } + +out: + return feature_enabled; } static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 35b2b8f5801a3..3ad756e141740 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -59,6 +59,10 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) +static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu, + int od_feature_bit, + int32_t *min, int32_t *max); + static const struct smu_feature_bits smu_v13_0_7_dpm_features = { .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), @@ -1054,8 +1058,35 @@ static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu, PPTable_t *pptable = smu->smu_table.driver_pptable; const OverDriveLimits_t * const overdrive_upperlimits = &pptable->SkuTable.OverDriveLimitsBasicMax; + int32_t min_value, max_value; + bool feature_enabled; - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); + switch (od_feature_bit) { + case PP_OD_FEATURE_FAN_CURVE_BIT: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + if (feature_enabled) { + smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + + smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + } + break; + default: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + break; + } + +out: + return feature_enabled; } static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu, From f768674a68ec0659e25340f8127455d6022fc09a Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 23 Mar 2026 13:41:18 +0530 Subject: [PATCH 2027/2070] drm/amdgpu: Fix fence put before wait in amdgpu_amdkfd_submit_ib MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_amdkfd_submit_ib() submits a GPU job and gets a fence from amdgpu_ib_schedule(). This fence is used to wait for job completion. Currently, the code drops the fence reference using dma_fence_put() before calling dma_fence_wait(). If dma_fence_put() releases the last reference, the fence may be freed before dma_fence_wait() is called. This can lead to a use-after-free. Fix this by waiting on the fence first and releasing the reference only after dma_fence_wait() completes. Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c:697 amdgpu_amdkfd_submit_ib() warn: passing freed memory 'f' (line 696) Fixes: 9ae55f030dc52 ("drm/amdgpu: Follow up change to previous drm scheduler change.") Cc: Felix Kuehling Cc: Dan Carpenter Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König Change-Id: I8eabe51b16bc3cd0603a443524c8d5c955d0bdbf --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index d2f1902d0e958..21633497265a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -703,9 +703,9 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, goto err_ib_sched; } - /* Drop the initial kref_init count (see drm_sched_main as example) */ - dma_fence_put(f); ret = dma_fence_wait(f, false); + /* Drop the returned fence reference after the wait completes */ + dma_fence_put(f); err_ib_sched: amdgpu_job_free(job); From a6077c1b26f3edb8a20066bea535003926bf186d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 20 Mar 2026 12:33:48 -0400 Subject: [PATCH 2028/2070] drm/amd/display: check if ext_caps is valid in BL setup LVDS connectors don't have extended backlight caps so check if the pointer is valid before accessing it. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5012 Fixes: 1454642960b0 ("drm/amd: Re-introduce property to control adaptive backlight modulation") Cc: Mario Limonciello Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b434ba27df1e4..e90c35c7f3a83 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5500,7 +5500,7 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, caps = &dm->backlight_caps[aconnector->bl_idx]; /* Only offer ABM property when non-OLED and user didn't turn off by module parameter */ - if (!caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) + if (caps->ext_caps && !caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) drm_object_attach_property(&aconnector->base.base, dm->adev->mode_info.abm_level_property, ABM_SYSFS_CONTROL); From e7a984e910b1f72d95b0f5bd57658991c485d486 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 23 Mar 2026 14:28:57 +0530 Subject: [PATCH 2029/2070] drm/amdkfd: Fix NULL pointer check order in kfd_ioctl_create_process MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In kfd_ioctl_create_process(), the pointer 'p' is used before checking if it is NULL. The code accesses p->context_id before validating 'p'. This can lead to a possible NULL pointer dereference. Move the NULL check before using 'p' so that the pointer is validated before access. Fixes the below: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.c:3177 kfd_ioctl_create_process() warn: variable dereferenced before check 'p' (see line 3174) Fixes: cc6b66d661fd ("amdkfd: introduce new ioctl AMDKFD_IOC_CREATE_PROCESS") Cc: Zhu Lingshan Cc: Felix Kuehling Cc: Christian König Cc: Alex Deucher Cc: Dan Carpenter Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König Change-Id: I259d9f7abd5e595fa5cc12bd9f716bbbe641d6f4 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index ab406e5a129dc..7ae654d7800c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3426,11 +3426,11 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v struct kfd_process *process; int ret; - /* Each FD owns only one kfd_process */ - if (p->context_id != KFD_CONTEXT_ID_PRIMARY) + if (!filep->private_data || !p) return -EINVAL; - if (!filep->private_data || !p) + /* Each FD owns only one kfd_process */ + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) return -EINVAL; mutex_lock(&kfd_processes_mutex); From c243039ad270a2ac1bd090426616a69bb1b446b9 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 19 Mar 2026 03:36:50 -0400 Subject: [PATCH 2030/2070] drm/amd/pm: disable OD_FAN_CURVE if temp or pwm range invalid for smu v14 Forcibly disable the OD_FAN_CURVE feature when temperature or PWM range is invalid, otherwise PMFW will reject this configuration on smu v14.0.2/14.0.3. example: $ sudo cat /sys/bus/pci/devices//gpu_od/fan_ctrl/fan_curve OD_FAN_CURVE: 0: 0C 0% 1: 0C 0% 2: 0C 0% 3: 0C 0% 4: 0C 0% OD_RANGE: FAN_CURVE(hotspot temp): 0C 0C FAN_CURVE(fan speed): 0% 0% $ echo "0 50 40" | sudo tee fan_curve kernel log: [ 969.761627] amdgpu 0000:03:00.0: amdgpu: Fan curve temp setting(50) must be within [0, 0]! [ 1010.897800] amdgpu 0000:03:00.0: amdgpu: Fan curve temp setting(50) must be within [0, 0]! Signed-off-by: Yang Wang Acked-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 23a143b36fd0d..baf6866477e7c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -56,6 +56,10 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) +static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, + int od_feature_bit, + int32_t *min, int32_t *max); + static const struct smu_feature_bits smu_v14_0_2_dpm_features = { .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), @@ -923,8 +927,35 @@ static bool smu_v14_0_2_is_od_feature_supported(struct smu_context *smu, PPTable_t *pptable = smu->smu_table.driver_pptable; const OverDriveLimits_t * const overdrive_upperlimits = &pptable->SkuTable.OverDriveLimitsBasicMax; + int32_t min_value, max_value; + bool feature_enabled; - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); + switch (od_feature_bit) { + case PP_OD_FEATURE_FAN_CURVE_BIT: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + if (feature_enabled) { + smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + + smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + } + break; + default: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + break; + } + +out: + return feature_enabled; } static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, From 25d5efc60e5e091d8f837f0cd8d5c642d724e380 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Sun, 22 Mar 2026 21:48:39 -0400 Subject: [PATCH 2031/2070] drm/amd/pm: add dedicated dram addr msg for smu v15 Add dedicated SMU Dram MSG mapping to avoid conflicts in SMU IP v15 common code for upcoming ASICs. add new smu msg: - SMU_MSG_SetDriverDramAddr - SMU_MSG_SetToolsDramAddr Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 7de3a43489572..85a0b2f6d4719 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -42,8 +42,10 @@ __SMU_DUMMY_MAP(SetPptLimit), \ __SMU_DUMMY_MAP(SetDriverDramAddrHigh), \ __SMU_DUMMY_MAP(SetDriverDramAddrLow), \ + __SMU_DUMMY_MAP(SetDriverDramAddr), \ __SMU_DUMMY_MAP(SetToolsDramAddrHigh), \ __SMU_DUMMY_MAP(SetToolsDramAddrLow), \ + __SMU_DUMMY_MAP(SetToolsDramAddr), \ __SMU_DUMMY_MAP(TransferTableSmu2Dram), \ __SMU_DUMMY_MAP(TransferTableDram2Smu), \ __SMU_DUMMY_MAP(UseDefaultPPTable), \ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index a9417cb4e920b..5649f2e71ac6e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -611,7 +611,7 @@ int smu_v15_0_set_driver_table_location(struct smu_context *smu) { struct smu_table *driver_table = &smu->smu_table.driver_table; struct smu_msg_args args = { - .msg = SMU_MSG_SetDriverDramAddrHigh, + .msg = SMU_MSG_SetDriverDramAddr, .num_args = 2, .num_out_args = 0, }; @@ -626,7 +626,7 @@ int smu_v15_0_set_tool_table_location(struct smu_context *smu) { struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; struct smu_msg_args args = { - .msg = SMU_MSG_SetToolsDramAddrHigh, + .msg = SMU_MSG_SetToolsDramAddr, .num_args = 2, .num_out_args = 0, }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 13c2b0cb7ad19..cc2babc6a341a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -87,8 +87,8 @@ static const struct cmn2asic_msg_mapping smu_v15_0_8_message_map[SMU_MSG_MAX_COU MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1), MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1), MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), - MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddr, 1), - MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddr, 0), + MSG_MAP(SetDriverDramAddr, PPSMC_MSG_SetDriverDramAddr, 1), + MSG_MAP(SetToolsDramAddr, PPSMC_MSG_SetToolsDramAddr, 0), MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), From 71215e37959440b3d20b04801e8fdd737062e6e4 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Mon, 23 Mar 2026 13:31:54 +0800 Subject: [PATCH 2032/2070] drm/amdgpu: use DISCOVERY_TMR_SIZE in ACPI TMR fallback amdgpu_acpi_get_tmr_info() returns the full TMR region size, not the IP discovery table size. Using tmr_size as discovery.size can lead to oversized allocations and probe failure. In the ACPI fallback path, keep discovery.size as DISCOVERY_TMR_SIZE and only use ACPI data for offset calculation. Fixes: 7055e5157742 ("drm/amdgpu: New interface to get IP discovery binary v3") Reviewed-by: Lijo Lazar Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 623594d230924..c3c6c4d1c8f22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -324,7 +324,7 @@ static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); if (ret) return ret; - adev->discovery.size = (u32)tmr_size; + adev->discovery.size = DISCOVERY_TMR_SIZE; adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; } } From 6c22d4d2d8596f535fc27ab343c616ef27b1a3fa Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 19 Mar 2026 15:54:38 +0800 Subject: [PATCH 2033/2070] drm/amd/pm: Enable VCN reset for pgm=4 with appropriate FW version Extend the VCN reset capability to include pgm=4 variants when the firmware version meets the required threshold (>= 0x04557100). This follows the existing pattern for pgm=0 and pgm=7, ensuring that VCN reset is enabled only on configurations where it is supported by the firmware. Reviewed-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 32b1081a734ea..8c4d81595c745 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -468,6 +468,7 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); if ((pgm == 0 && fw_ver >= 0x00558200) || + (pgm == 4 && fw_ver >= 0x04557100) || (pgm == 7 && fw_ver >= 0x07551400)) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } From 5b27086f0d205b172186baee2570cababcd0449f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 2 Feb 2026 13:06:25 +0100 Subject: [PATCH 2034/2070] drm/amdgpu: annotate eviction fence signaling path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make sure lockdep sees the dependencies here. Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index e16796f4d289d..ef299dae04daf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -64,8 +64,17 @@ amdgpu_eviction_fence_suspend_worker(struct work_struct *work) container_of(evf_mgr, struct amdgpu_fpriv, evf_mgr); struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; struct dma_fence *ev_fence; + bool cookie; mutex_lock(&uq_mgr->userq_mutex); + + /* + * This is intentionally after taking the userq_mutex since we do + * allocate memory while holding this lock, but only after ensuring that + * the eviction fence is signaled. + */ + cookie = dma_fence_begin_signalling(); + ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); amdgpu_userq_evict(uq_mgr, !evf_mgr->shutdown); @@ -75,6 +84,7 @@ amdgpu_eviction_fence_suspend_worker(struct work_struct *work) * next fence. */ dma_fence_signal(ev_fence); + dma_fence_end_signalling(cookie); dma_fence_put(ev_fence); mutex_unlock(&uq_mgr->userq_mutex); } From af342ae2102d94bd772b4a7f3b4d70630352f972 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 20 Mar 2026 10:25:37 +0800 Subject: [PATCH 2035/2070] drm/amdkcl: test whether dma_fence_begin_signalling is available It's caused by the commit:3ddc31de "drm/amdgpu: annotate eviction fence signaling path" Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/dma-fence-signalling.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 19 +++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 87dbaae9c689a..c55660f6ad4e0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -175,6 +175,9 @@ /* struct dma_fence_ops has use_64bit_seqno field */ /* #undef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO */ +/* test whether dma_fence_begin_signalling are available */ +#define HAVE_DMA_FENCE_SIGNALLING 1 + /* dma_fence_TIMESTAMP() is available */ #define HAVE_DMA_FENCE_TIMESTAMP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 new file mode 100644 index 0000000000000..d9e988cbc76d0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.8-rc2-471-g5fbff813a4a3 +dnl # dma-fence: basic lockdep annotations +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_SIGNALLING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_fence_begin_signalling(); + ],[ + AC_DEFINE(HAVE_DMA_FENCE_SIGNALLING, 1, + [test whether dma_fence_begin_signalling are available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2b78755675f3f..db9534eab47cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -275,6 +275,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 + AC_AMDGPU_DMA_FENCE_SIGNALLING AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index cd1f7814fceee..d8d028be35252 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -78,4 +78,23 @@ static inline bool dma_fence_is_later_or_same(struct dma_fence *f1, #ifndef HAVE_DMA_FENCE_INIT64 #define dma_fence_init64 dma_fence_init #endif + +#ifndef HAVE_DMA_FENCE_SIGNALLING +/* + * For older kernels where these functions are not available, + * we provide no-op implementations since LOCKDEP tracking may not be needed + */ +static inline bool kcl_dma_fence_begin_signalling(void) +{ + return true; +} + +static inline void kcl_dma_fence_end_signalling(bool cookie) +{ +} + +#define dma_fence_begin_signalling kcl_dma_fence_begin_signalling +#define dma_fence_end_signalling kcl_dma_fence_end_signalling +#endif + #endif From 5f3503865883cdca4f7a60e5b856ae9f221876b1 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Fri, 20 Mar 2026 16:16:16 +0800 Subject: [PATCH 2036/2070] drm/amdgpu/vcn4.0.3: gate per-queue reset by PSP SOS program version Add a PSP SOS firmware compatibility check before enabling VCN per-queue reset on vcn_v4_0_3. Per review, program check is sufficient: when PSP SOS program is 0x01, require fw version >= 0x0036015f; otherwise allow per-queue reset. Reviewed-by: Lijo Lazar Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index e78526a4e521e..ff3013b97abd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -134,6 +134,21 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) return 0; } +static bool vcn_v4_0_3_is_psp_fw_reset_supported(struct amdgpu_device *adev) +{ + uint32_t fw_ver = adev->psp.sos.fw_version; + uint32_t pgm = (fw_ver >> 8) & 0xFF; + + /* + * FWDEV-159155: PSP SOS FW must be >= 0x0036015f for program 0x01 + * before enabling VCN per-queue reset. + */ + if (pgm == 1) + return fw_ver >= 0x0036015f; + + return true; +} + static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -141,7 +156,9 @@ static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); - if (amdgpu_dpm_reset_vcn_is_supported(adev) && !amdgpu_sriov_vf(adev)) + if (amdgpu_dpm_reset_vcn_is_supported(adev) && + vcn_v4_0_3_is_psp_fw_reset_supported(adev) && + !amdgpu_sriov_vf(adev)) adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; return 0; From 3d0e77e4068371ea75ca9e4af73d025833ad85ee Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 19 Mar 2026 14:47:11 +0800 Subject: [PATCH 2037/2070] drm/amdgpu: fix syncobj leak for amdgpu_gem_va_ioctl() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It requires freeing the syncobj and chain alloction resource. Signed-off-by: Prike Liang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 8e7c04fb4435d..6e3e192e8210e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -107,6 +107,7 @@ amdgpu_gem_update_timeline_node(struct drm_file *filp, *chain = dma_fence_chain_alloc(); if (!*chain) { drm_syncobj_put(*syncobj); + *syncobj = NULL; return -ENOMEM; } @@ -1149,6 +1150,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, timeline_chain, fence, args->vm_timeline_point); + timeline_chain = NULL; } } dma_fence_put(fence); @@ -1156,6 +1158,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, } error: + dma_fence_chain_free(timeline_chain); + if (timeline_syncobj) + drm_syncobj_put(timeline_syncobj); drm_exec_fini(&exec); error_put_gobj: drm_gem_object_put(gobj); From 70a8008f512b7c144c9cc8629f64a9e556568916 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 24 Mar 2026 13:18:28 +0530 Subject: [PATCH 2038/2070] drm/amdgpu/userq: dont use goto to jump when at end of function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In function amdgpu_userq_restore_worker we dont need to use goto as we already in the end of function and it will exit naturally. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index e3f9b6618371f..cfd0ac8f5ebb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1245,10 +1245,8 @@ static void amdgpu_userq_restore_worker(struct work_struct *work) } ret = amdgpu_userq_restore_all(uq_mgr); - if (ret) { + if (ret) drm_file_err(uq_mgr->file, "Failed to restore all queues\n"); - goto unlock; - } unlock: mutex_unlock(&uq_mgr->userq_mutex); From 6f8c9eb4d4f6facf3197ccc4cb3b781d8362d4dd Mon Sep 17 00:00:00 2001 From: Adriano Vero Date: Tue, 17 Mar 2026 21:36:13 +0100 Subject: [PATCH 2039/2070] drm/amd/display: clean up typecasts and constants in dcn4_calcs Signed-off-by: Adriano Vero Signed-off-by: Alex Deucher --- .../src/dml2_core/dml2_core_dcn4_calcs.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index b30d16474ceb0..f6402e199354e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -202,7 +202,7 @@ static unsigned int dml_round_to_multiple(unsigned int num, unsigned int multipl return (num - remainder); } -static unsigned int dml_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info) +static unsigned int dml_get_num_active_pipes(unsigned int num_planes, const struct core_display_cfg_support_info *cfg_support_info) { unsigned int num_active_pipes = 0; @@ -546,9 +546,9 @@ static bool dml_is_vertical_rotation(enum dml2_rotation_angle Scan) return is_vert; } -static int unsigned dml_get_gfx_version(enum dml2_swizzle_mode sw_mode) +static unsigned int dml_get_gfx_version(enum dml2_swizzle_mode sw_mode) { - int unsigned version = 0; + unsigned int version = 0; if (sw_mode == dml2_sw_linear || sw_mode == dml2_sw_256b_2d || @@ -1761,7 +1761,7 @@ static unsigned int CalculateVMAndRowBytes(struct dml2_core_shared_calculate_vm_ *p->PixelPTEBytesPerRow = (unsigned int)((double)*p->dpte_row_width_ub / (double)*p->PixelPTEReqWidth * *p->PTERequestSize); // VBA_DELTA, VBA doesn't have programming value for pte row height linear. - *p->dpte_row_height_linear = (unsigned int)1 << (unsigned int)math_floor2(math_log((float)(p->PTEBufferSizeInRequests * PixelPTEReqWidth_linear / p->Pitch), 2.0), 1); + *p->dpte_row_height_linear = 1U << (unsigned int)math_floor2(math_log((float)(p->PTEBufferSizeInRequests * PixelPTEReqWidth_linear / p->Pitch), 2.0), 1); if (*p->dpte_row_height_linear > 128) *p->dpte_row_height_linear = 128; @@ -3377,7 +3377,7 @@ static void calculate_cursor_req_attributes( DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_line = %d\n", __func__, *cursor_bytes_per_line); DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_chunk = %d\n", __func__, *cursor_bytes_per_chunk); DML_LOG_VERBOSE("DML::%s: cursor_bytes = %d\n", __func__, *cursor_bytes); - DML_LOG_VERBOSE("DML::%s: cursor_pitch = %d\n", __func__, cursor_bpp == 2 ? 256 : (unsigned int)1 << (unsigned int)math_ceil2(math_log((float)cursor_width, 2), 1)); + DML_LOG_VERBOSE("DML::%s: cursor_pitch = %d\n", __func__, cursor_bpp == 2 ? 256 : 1U << (unsigned int)math_ceil2(math_log((float)cursor_width, 2), 1)); #endif } @@ -12205,15 +12205,15 @@ static void rq_dlg_get_wm_regs(const struct dml2_display_cfg *display_cfg, const { double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz; - wm_regs->fclk_pstate = (int unsigned)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz); - wm_regs->sr_enter = (int unsigned)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz); - wm_regs->sr_exit = (int unsigned)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz); - wm_regs->sr_enter_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz); - wm_regs->sr_exit_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz); - wm_regs->temp_read_or_ppt = (int unsigned)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz); - wm_regs->uclk_pstate = (int unsigned)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz); - wm_regs->urgent = (int unsigned)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); - wm_regs->usr = (int unsigned)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz); + wm_regs->fclk_pstate = (unsigned int)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz); + wm_regs->sr_enter = (unsigned int)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + wm_regs->sr_exit = (unsigned int)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz); + wm_regs->sr_enter_z8 = (unsigned int)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + wm_regs->sr_exit_z8 = (unsigned int)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz); + wm_regs->temp_read_or_ppt = (unsigned int)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz); + wm_regs->uclk_pstate = (unsigned int)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz); + wm_regs->urgent = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + wm_regs->usr = (unsigned int)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz); wm_regs->refcyc_per_trip_to_mem = (unsigned int)(mode_lib->mp.UrgentLatency * refclk_freq_in_mhz); wm_regs->refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib->mp.MetaTripToMemory * refclk_freq_in_mhz); wm_regs->frac_urg_bw_flip = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthImmediateFlip * 1000); @@ -12692,7 +12692,7 @@ static void rq_dlg_get_dlg_reg( disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(math_pow(2, 23) - 1); - DML_ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); + DML_ASSERT(disp_dlg_regs->dst_y_after_scaler < 8U); DML_ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)math_pow(2, 13)); if (disp_dlg_regs->dst_y_per_pte_row_nom_l >= (unsigned int)math_pow(2, 17)) { @@ -13248,7 +13248,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.misc.cstate_max_cap_mode = dml_get_cstate_max_cap_mode(mode_lib); - out->min_clocks.dcn4x.dpprefclk_khz = (int unsigned)dml_get_global_dppclk_khz(mode_lib); + out->min_clocks.dcn4x.dpprefclk_khz = (unsigned int)dml_get_global_dppclk_khz(mode_lib); out->informative.qos.max_active_fclk_change_latency_supported = dml_get_fclk_change_latency(mode_lib); From b7c9d1e121a3b05a7da1e8b3f395cb59b6175942 Mon Sep 17 00:00:00 2001 From: Kexin Sun Date: Sat, 21 Mar 2026 18:57:17 +0800 Subject: [PATCH 2040/2070] drm/amd/display: update outdated comments for renamed vblank_control_worker() The function vblank_control_worker() was renamed to amdgpu_dm_crtc_vblank_control_worker() by commit 6ce4f9ee25ff ("drm/amd/display: Add prefix to amdgpu crtc functions"). Update the two stale references in amdgpu_dm.c. Assisted-by: unnamed:deepseek-v3.2 coccinelle Signed-off-by: Kexin Sun Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e90c35c7f3a83..9e59ec757b118 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10213,7 +10213,8 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, * a vblank event disable request to enable PSR/RP. PSR SU/RP * can be enabled immediately once OS demonstrates an * adequate number of fast atomic commits to notify KMD - * of update events. See `vblank_control_worker()`. + * of update events. + * See `amdgpu_dm_crtc_vblank_control_worker()`. */ if (!vrr_active && acrtc_attach->dm_irq_params.allow_sr_entry && @@ -10381,8 +10382,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, /* * If the dirty regions changed, PSR-SU need to be disabled temporarily * and enabled it again after dirty regions are stable to avoid video glitch. - * PSR-SU will be enabled in vblank_control_worker() if user pause the video - * during the PSR-SU was disabled. + * PSR-SU will be enabled in + * amdgpu_dm_crtc_vblank_control_worker() if user + * pause the video during the PSR-SU was disabled. */ if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && acrtc_attach->dm_irq_params.allow_sr_entry && From d9673ae95057787309cce08aa1de54177aacb12f Mon Sep 17 00:00:00 2001 From: Donet Tom Date: Mon, 23 Mar 2026 09:58:36 +0530 Subject: [PATCH 2041/2070] drm/amdgpu: Handle GPU page faults correctly on non-4K page systems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During a GPU page fault, the driver restores the SVM range and then maps it into the GPU page tables. The current implementation passes a GPU-page-size (4K-based) PFN to svm_range_restore_pages() to restore the range. SVM ranges are tracked using system-page-size PFNs. On systems where the system page size is larger than 4K, using GPU-page-size PFNs to restore the range causes two problems: Range lookup fails: Because the restore function receives PFNs in GPU (4K) units, the SVM range lookup does not find the existing range. This will result in a duplicate SVM range being created. VMA lookup failure: The restore function also tries to locate the VMA for the faulting address. It converts the GPU-page-size PFN into an address using the system page size, which results in an incorrect address on non-4K page-size systems. As a result, the VMA lookup fails with the message: "address 0xxxx VMA is removed". This patch passes the system-page-size PFN to svm_range_restore_pages() so that the SVM range is restored correctly on non-4K page systems. Acked-by: Christian König Signed-off-by: Donet Tom Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 622f7033bbd28..c1d074c326000 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3047,14 +3047,14 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, if (!root) return false; - addr /= AMDGPU_GPU_PAGE_SIZE; - if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, - node_id, addr, ts, write_fault)) { + node_id, addr >> PAGE_SHIFT, ts, write_fault)) { amdgpu_bo_unref(&root); return true; } + addr /= AMDGPU_GPU_PAGE_SIZE; + r = amdgpu_bo_reserve(root, true); if (r) goto error_unref; From 09fd685ee0eb6650e50af09d9fee1ce152af3023 Mon Sep 17 00:00:00 2001 From: Chen Ni Date: Fri, 20 Mar 2026 16:32:47 +0800 Subject: [PATCH 2042/2070] drm/amdgpu/userq: convert comma to semicolon Using a ',' in place of a ';' can have unintended side effects. Although that is not the case here, it seems best to use ';' unless ',' is intended. Found by inspection. No functional change intended. Compile tested only. Signed-off-by: Chen Ni Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index fdef444e0ad28..cead6acb90759 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -1039,13 +1039,13 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, } num_read_bo_handles = wait_info->num_bo_read_handles; - ptr = u64_to_user_ptr(wait_info->bo_read_handles), + ptr = u64_to_user_ptr(wait_info->bo_read_handles); r = drm_gem_objects_lookup(filp, ptr, num_read_bo_handles, &gobj_read); if (r) goto free_timeline_points; num_write_bo_handles = wait_info->num_bo_write_handles; - ptr = u64_to_user_ptr(wait_info->bo_write_handles), + ptr = u64_to_user_ptr(wait_info->bo_write_handles); r = drm_gem_objects_lookup(filp, ptr, num_write_bo_handles, &gobj_write); if (r) From 6acc201f6214f8c003612a7f06a3c3447e8f6a11 Mon Sep 17 00:00:00 2001 From: Kexin Sun Date: Sat, 21 Mar 2026 18:57:28 +0800 Subject: [PATCH 2043/2070] drm/amdgpu: update outdated comment for renamed amdgpu_fence_driver_init() The function amdgpu_fence_driver_init() was renamed to amdgpu_fence_driver_sw_init() by commit 067f44c8b459 ("drm/amdgpu: avoid over-handle of fence driver fini in s3 test (v2)"). Update the stale reference in the amdgpu_fence_driver_init_ring() kdoc. Assisted-by: unnamed:deepseek-v3.2 coccinelle Signed-off-by: Kexin Sun Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index db7cfc4ea1c09..aefa0bcbf8d26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -438,7 +438,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, * @ring: ring to init the fence driver on * * Init the fence driver for the requested ring (all asics). - * Helper function for amdgpu_fence_driver_init(). + * Helper function for amdgpu_fence_driver_sw_init(). */ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) { From 86e3de1f07a94967e5cab6ada2743c3b35caa1af Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 26 Feb 2026 17:12:08 -0500 Subject: [PATCH 2044/2070] drm/amd/display: Fix DCE LVDS handling LVDS does not use an HPD pin so it may be invalid. Handle this case correctly in link encoder creation. Fixes: 7c8fb3b8e9ba ("drm/amd/display: Add hpd_source index check for DCE60/80/100/110/112/120 link encoders") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5012 Cc: Srinivasan Shanmugam Cc: Roman Li Reviewed-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- .../display/dc/resource/dce100/dce100_resource.c | 6 ++---- .../display/dc/resource/dce110/dce110_resource.c | 5 +++-- .../display/dc/resource/dce112/dce112_resource.c | 5 +++-- .../display/dc/resource/dce120/dce120_resource.c | 5 +++-- .../amd/display/dc/resource/dce60/dce60_resource.c | 14 ++++++-------- .../amd/display/dc/resource/dce80/dce80_resource.c | 6 ++---- 6 files changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 05f7ff60f8f5a..2b884e28727ba 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -651,9 +651,6 @@ static struct link_encoder *dce100_link_encoder_create( return &enc110->base; } - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) - return NULL; - link_regs_id = map_transmitter_id_to_phy_instance(enc_init_data->transmitter); @@ -662,7 +659,8 @@ static struct link_encoder *dce100_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index 7c09825cd9bd3..d957598911cbc 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -672,7 +672,7 @@ static struct link_encoder *dce110_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) return NULL; link_regs_id = @@ -683,7 +683,8 @@ static struct link_encoder *dce110_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 3f0a6bc4dcc23..1cce903d477aa 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -633,7 +633,7 @@ static struct link_encoder *dce112_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) return NULL; link_regs_id = @@ -644,7 +644,8 @@ static struct link_encoder *dce112_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index 92890784caa6e..8b568be20a77b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -717,7 +717,7 @@ static struct link_encoder *dce120_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) return NULL; link_regs_id = @@ -728,7 +728,8 @@ static struct link_encoder *dce120_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index d41d24b76c11f..2f5ee9d8536af 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -747,18 +747,16 @@ static struct link_encoder *dce60_link_encoder_create( return &enc110->base; } - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) - return NULL; - link_regs_id = map_transmitter_id_to_phy_instance(enc_init_data->transmitter); dce60_link_encoder_construct(enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[link_regs_id], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data, + &link_enc_feature, + &link_enc_regs[link_regs_id], + &link_enc_aux_regs[enc_init_data->channel - 1], + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index a68e799d58854..406705fac7d64 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -753,9 +753,6 @@ static struct link_encoder *dce80_link_encoder_create( return &enc110->base; } - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) - return NULL; - link_regs_id = map_transmitter_id_to_phy_instance(enc_init_data->transmitter); @@ -764,7 +761,8 @@ static struct link_encoder *dce80_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } From 0d90f90eeedfc2857bee840167941d6ece190d36 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 23 Mar 2026 22:43:48 +0000 Subject: [PATCH 2045/2070] drm/amdgpu/mes12_1: emove extra ; from declaration statement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is a declaration statement that has a ;; at the end, remove the extraneous ; Reviewed-by: Christian König Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index 5dcc2c32644ae..0e90895447691 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -2227,7 +2227,7 @@ static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id) struct amdgpu_bo *meta_bo = NULL, *ctx_bo = NULL; void *meta_ptr = NULL, *ctx_ptr = NULL; u64 meta_gpu_addr, ctx_gpu_addr; - int size, i, r, pasid;; + int size, i, r, pasid; pasid = amdgpu_pasid_alloc(16); if (pasid < 0) From f5ae542f6a72d8db77df54b42fbede7f72a325a5 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 24 Mar 2026 20:46:34 +0530 Subject: [PATCH 2046/2070] drm/amdgpu/userq: schedule_delayed_work should be after fence signalled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorganise the amdgpu_eviction_fence_suspend_worker code so schedule_delayed_work is the last thing we do after amdgpu_userq_evict is complete and the eviction fence is signalled. Suggested-by: Christian König Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 4 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 3 +-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index ef299dae04daf..790f21903386e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -76,7 +76,7 @@ amdgpu_eviction_fence_suspend_worker(struct work_struct *work) cookie = dma_fence_begin_signalling(); ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); - amdgpu_userq_evict(uq_mgr, !evf_mgr->shutdown); + amdgpu_userq_evict(uq_mgr); /* * Signaling the eviction fence must be done while holding the @@ -86,6 +86,10 @@ amdgpu_eviction_fence_suspend_worker(struct work_struct *work) dma_fence_signal(ev_fence); dma_fence_end_signalling(cookie); dma_fence_put(ev_fence); + + if (!evf_mgr->shutdown) + schedule_delayed_work(&uq_mgr->resume_work, 0); + mutex_unlock(&uq_mgr->userq_mutex); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index cfd0ac8f5ebb4..d4e38e92aada7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1316,7 +1316,7 @@ amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) } void -amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, bool schedule_resume) +amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_device *adev = uq_mgr->adev; int ret; @@ -1330,8 +1330,6 @@ amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, bool schedule_resume) if (ret) dev_err(adev->dev, "Failed to evict userqueue\n"); - if (schedule_resume) - schedule_delayed_work(&uq_mgr->resume_work, 0); } int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index bd40a98594d66..a379f70da8273 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -138,8 +138,7 @@ int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_userq_obj *userq_obj); -void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, - bool schedule_resume); +void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr); void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr); From f5b3ae22447d3e305e592b010b40be7881e0f33f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 20 Mar 2026 12:56:20 -0400 Subject: [PATCH 2047/2070] drm/amd/display: add a no_hpd link_encoder_funcs variant For link encoders without HPD (analog or LVDS), add a link_encoder_funcs structure with no hpd enable callbacks. Reviewed-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dce/dce_link_encoder.c | 64 ++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 2ba3d3a3aac58..a368802ba51db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -122,6 +122,33 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .program_hpd_filter = dce110_program_hpd_filter, }; +static const struct link_encoder_funcs dce110_lnk_enc_funcs_no_hpd = { + .validate_output_with_stream = + dce110_link_encoder_validate_output_with_stream, + .hw_init = dce110_link_encoder_hw_init, + .setup = dce110_link_encoder_setup, + .enable_tmds_output = dce110_link_encoder_enable_tmds_output, + .enable_dp_output = dce110_link_encoder_enable_dp_output, + .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, + .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, + .disable_output = dce110_link_encoder_disable_output, + .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dce110_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dce110_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dce110_psr_program_secondary_packet, + .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, + .is_dig_enabled = dce110_is_dig_enabled, + .destroy = dce110_link_encoder_destroy, + .get_max_link_cap = dce110_link_encoder_get_max_link_cap, + .get_dig_frontend = dce110_get_dig_frontend, + .get_hpd_state = dce110_get_hpd_state, + .program_hpd_filter = dce110_program_hpd_filter, +}; + static enum bp_result link_transmitter_control( struct dce110_link_encoder *enc110, struct bp_transmitter_control *cntl) @@ -865,7 +892,10 @@ void dce110_link_encoder_construct( const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; enum bp_result result = BP_RESULT_OK; - enc110->base.funcs = &dce110_lnk_enc_funcs; + if (hpd_regs) + enc110->base.funcs = &dce110_lnk_enc_funcs; + else + enc110->base.funcs = &dce110_lnk_enc_funcs_no_hpd; enc110->base.ctx = init_data->ctx; enc110->base.id = init_data->encoder; enc110->base.analog_id = init_data->analog_encoder; @@ -1855,6 +1885,33 @@ static const struct link_encoder_funcs dce60_lnk_enc_funcs = { .program_hpd_filter = dce110_program_hpd_filter, }; +static const struct link_encoder_funcs dce60_lnk_enc_funcs_no_hpd = { + .validate_output_with_stream = + dce110_link_encoder_validate_output_with_stream, + .hw_init = dce110_link_encoder_hw_init, + .setup = dce110_link_encoder_setup, + .enable_tmds_output = dce110_link_encoder_enable_tmds_output, + .enable_dp_output = dce60_link_encoder_enable_dp_output, + .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, + .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, + .disable_output = dce110_link_encoder_disable_output, + .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dce110_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dce110_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dce110_psr_program_secondary_packet, + .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, + .is_dig_enabled = dce110_is_dig_enabled, + .destroy = dce110_link_encoder_destroy, + .get_max_link_cap = dce110_link_encoder_get_max_link_cap, + .get_dig_frontend = dce110_get_dig_frontend, + .get_hpd_state = dce110_get_hpd_state, + .program_hpd_filter = dce110_program_hpd_filter, +}; + void dce60_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, @@ -1867,7 +1924,10 @@ void dce60_link_encoder_construct( const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; enum bp_result result = BP_RESULT_OK; - enc110->base.funcs = &dce60_lnk_enc_funcs; + if (hpd_regs) + enc110->base.funcs = &dce60_lnk_enc_funcs; + else + enc110->base.funcs = &dce60_lnk_enc_funcs_no_hpd; enc110->base.ctx = init_data->ctx; enc110->base.id = init_data->encoder; enc110->base.analog_id = init_data->analog_encoder; From e5de471475aeb017f9bdc0387d8ea2cb2670d550 Mon Sep 17 00:00:00 2001 From: Junrui Luo Date: Tue, 24 Mar 2026 17:39:02 +0800 Subject: [PATCH 2048/2070] drm/amdgpu: validate doorbell_offset in user queue creation amdgpu_userq_get_doorbell_index() passes the user-provided doorbell_offset to amdgpu_doorbell_index_on_bar() without bounds checking. An arbitrarily large doorbell_offset can cause the calculated doorbell index to fall outside the allocated doorbell BO, potentially corrupting kernel doorbell space. Validate that doorbell_offset falls within the doorbell BO before computing the BAR index, using u64 arithmetic to prevent overflow. Fixes: f09c1e6077ab ("drm/amdgpu: generate doorbell index for userqueue") Reported-by: Yuhao Jiang Cc: stable@vger.kernel.org Signed-off-by: Junrui Luo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d4e38e92aada7..853f75d27d530 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -600,6 +600,13 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, goto unpin_bo; } + /* Validate doorbell_offset is within the doorbell BO */ + if ((u64)db_info->doorbell_offset * db_size + db_size > + amdgpu_bo_size(db_obj->obj)) { + r = -EINVAL; + goto unpin_bo; + } + index = amdgpu_doorbell_index_on_bar(uq_mgr->adev, db_obj->obj, db_info->doorbell_offset, db_size); drm_dbg_driver(adev_to_drm(uq_mgr->adev), From 8eb2e7768721da85c9d133261eb65db4c44e20a5 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 24 Mar 2026 20:28:54 +0530 Subject: [PATCH 2049/2070] drm/amdgpu/userq: amdgpu_userq_vm_validate does not need userq mutex MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_userq_vm_validate function does not need userq_mutex and exec lock is good enough to locking all bos and updating the eviction fence. Also since we only need userq_mutex for amdgpu_userq_restore_all so move the locks in the function itself. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 853f75d27d530..611d67b7ff02f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1009,6 +1009,7 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) unsigned long queue_id; int ret = 0, r; + mutex_lock(&uq_mgr->userq_mutex); /* Resume all the queues for this process */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { @@ -1024,6 +1025,7 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) ret = r; } + mutex_unlock(&uq_mgr->userq_mutex); if (ret) drm_file_err(uq_mgr->file, "Failed to map all the queues\n"); @@ -1240,23 +1242,21 @@ static void amdgpu_userq_restore_worker(struct work_struct *work) struct dma_fence *ev_fence; int ret; - mutex_lock(&uq_mgr->userq_mutex); ev_fence = amdgpu_evf_mgr_get_fence(&fpriv->evf_mgr); if (!dma_fence_is_signaled(ev_fence)) - goto unlock; + goto put_fence; ret = amdgpu_userq_vm_validate(uq_mgr); if (ret) { drm_file_err(uq_mgr->file, "Failed to validate BOs to restore\n"); - goto unlock; + goto put_fence; } ret = amdgpu_userq_restore_all(uq_mgr); if (ret) drm_file_err(uq_mgr->file, "Failed to restore all queues\n"); -unlock: - mutex_unlock(&uq_mgr->userq_mutex); +put_fence: dma_fence_put(ev_fence); } From 322bd949bc2712bb11273d6809aef2d44888e0d1 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Tue, 24 Mar 2026 15:28:59 +0800 Subject: [PATCH 2050/2070] drm/amdgpu: guard atom_context in devcoredump VBIOS dump During GPU reset coredump generation, amdgpu_devcoredump_fw_info() unconditionally dereferences adev->mode_info.atom_context to print VBIOS fields. On reset/teardown paths this pointer can be NULL, causing a kernel page fault from the deferred coredump workqueue. Fix by checking ctx before printing VBIOS fields: if ctx is valid, print full VBIOS information as before; This prevents NULL-dereference crashes while preserving coredump output. Observed page fault log: [ 667.933329] RIP: 0010:amdgpu_devcoredump_format+0x780/0xc00 [amdgpu] [ 667.941517] amdgpu 0002:01:00.0: Dumping IP State [ 667.949660] Code: 8d 57 74 48 c7 c6 01 65 9f c2 48 8d 7d 98 e8 97 96 7a ff 49 8d 97 b4 00 00 00 48 c7 c6 18 65 9f c2 48 8d 7d 98 e8 80 96 7a ff <41> 8b 97 f4 00 00 00 48 c7 c6 2f 65 9f c2 48 8d 7d 98 e8 69 96 7a [ 667.949666] RSP: 0018:ffffc9002302bd50 EFLAGS: 00010246 [ 667.949673] RAX: 0000000000000000 RBX: ffff888110600000 RCX: 0000000000000000 [ 667.949676] RDX: 000000000000a9b5 RSI: 0000000000000405 RDI: 000000000000a999 [ 667.949680] RBP: ffffc9002302be00 R08: ffffffffc09c3084 R09: ffffffffc09c3085 [ 667.949684] R10: 0000000000000000 R11: 0000000000000004 R12: 00000000000048e0 [ 667.993908] amdgpu 0002:01:00.0: Dumping IP State Completed [ 667.994229] R13: 0000000000000025 R14: 000000000000000c R15: 0000000000000000 [ 667.994233] FS: 0000000000000000(0000) GS:ffff88c44c2c9000(0000) knlGS:0000000000000000 [ 668.000076] amdgpu 0002:01:00.0: [drm] AMDGPU device coredump file has been created [ 668.008025] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 668.008030] CR2: 00000000000000f4 CR3: 000000011195f001 CR4: 0000000000770ef0 [ 668.008035] PKRU: 55555554 [ 668.008040] Call Trace: [ 668.008045] [ 668.016010] amdgpu 0002:01:00.0: [drm] Check your /sys/class/drm/card16/device/devcoredump/data [ 668.023967] ? srso_alias_return_thunk+0x5/0xfbef5 [ 668.023988] ? __pfx___drm_printfn_coredump+0x10/0x10 [drm] [ 668.031950] amdgpu 0003:01:00.0: Dumping IP State [ 668.038159] ? __pfx___drm_puts_coredump+0x10/0x10 [drm] [ 668.083017] amdgpu 0003:01:00.0: Dumping IP State Completed [ 668.083824] amdgpu_devcoredump_deferred_work+0x26/0xc0 [amdgpu] [ 668.086163] amdgpu 0003:01:00.0: [drm] AMDGPU device coredump file has been created [ 668.095863] process_scheduled_works+0xa6/0x420 [ 668.095880] worker_thread+0x12a/0x270 [ 668.101223] amdgpu 0003:01:00.0: [drm] Check your /sys/class/drm/card24/device/devcoredump/data [ 668.107441] kthread+0x10d/0x230 [ 668.107451] ? __pfx_worker_thread+0x10/0x10 [ 668.107458] ? __pfx_kthread+0x10/0x10 [ 668.112709] amdgpu 0000:01:00.0: ring vcn_unified_1 timeout, signaled seq=9, emitted seq=10 [ 668.118630] ret_from_fork+0x17c/0x1f0 [ 668.118640] ? __pfx_kthread+0x10/0x10 [ 668.118647] ret_from_fork_asm+0x1a/0x30 Reviewed-by: Lijo Lazar Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index bbb5afd67b490..5aa46480f05fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -192,12 +192,16 @@ static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev, drm_printf(p, "VPE feature version: %u, fw version: 0x%08x\n", adev->vpe.feature_version, adev->vpe.fw_version); - drm_printf(p, "\nVBIOS Information\n"); - drm_printf(p, "vbios name : %s\n", ctx->name); - drm_printf(p, "vbios pn : %s\n", ctx->vbios_pn); - drm_printf(p, "vbios version : %d\n", ctx->version); - drm_printf(p, "vbios ver_str : %s\n", ctx->vbios_ver_str); - drm_printf(p, "vbios date : %s\n", ctx->date); + if (adev->bios) { + drm_printf(p, "\nVBIOS Information\n"); + drm_printf(p, "vbios name : %s\n", ctx->name); + drm_printf(p, "vbios pn : %s\n", ctx->vbios_pn); + drm_printf(p, "vbios version : %d\n", ctx->version); + drm_printf(p, "vbios ver_str : %s\n", ctx->vbios_ver_str); + drm_printf(p, "vbios date : %s\n", ctx->date); + }else { + drm_printf(p, "\nVBIOS Information: NA\n"); + } } static ssize_t From 9788587de8c8cc0c7ae9e76a7f08a97019f64444 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Tue, 24 Mar 2026 17:31:43 +0800 Subject: [PATCH 2051/2070] drm/amdgpu: flush coredump work before HW teardown In amdgpu_device_fini_hw(), deferred coredump formatting work may still be pending when hardware and IP components are being torn down. Since the work may access device registers and memory that will be freed or powered off, it must be completed before proceeding. Add a flush_work() call for adev->coredump_work, guarded by CONFIG_DEV_COREDUMP, to ensure any pending coredump work finishes before the device enters the early IP fini stage. This avoids potential use-after-free or accessing hardware resources that are no longer available. Reviewed-by: Lijo Lazar Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 3 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index 5aa46480f05fc..bbfda0be6d46e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -35,6 +35,9 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, void amdgpu_coredump_init(struct amdgpu_device *adev) { } +void amdgpu_coredump_fini(struct amdgpu_device *adev) +{ +} #else #define AMDGPU_CORE_DUMP_SIZE_MAX (256 * 1024 * 1024) @@ -440,4 +443,10 @@ void amdgpu_coredump_init(struct amdgpu_device *adev) { INIT_WORK(&adev->coredump_work, amdgpu_devcoredump_deferred_work); } + +void amdgpu_coredump_fini(struct amdgpu_device *adev) +{ + /* Finish deferred coredump formatting before HW/IP teardown. */ + flush_work(&adev->coredump_work); +} #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h index b3582d0b4ca43..f8f2f4df129b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h @@ -50,4 +50,5 @@ struct amdgpu_coredump_info { void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, bool vram_lost, struct amdgpu_job *job); void amdgpu_coredump_init(struct amdgpu_device *adev); +void amdgpu_coredump_fini(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4a15a0b89def9..d5995665f535d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4290,6 +4290,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) if (pci_dev_is_disconnected(adev->pdev)) amdgpu_amdkfd_device_fini_sw(adev); + amdgpu_coredump_fini(adev); amdgpu_device_ip_fini_early(adev); amdgpu_irq_fini_hw(adev); From 0dea60a03c05564182a302ac6b50e3f15541f108 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 26 Mar 2026 10:05:01 +0800 Subject: [PATCH 2052/2070] Bump AMDGPU version to 6.19.3 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 1f206d258caeb..8d5060ae5ce8a 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.19.2) +AC_INIT(amdgpu-dkms, 6.19.3) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 8e2e8e9631c67a16332f984daf0160cfa189b188 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 23 Mar 2026 16:07:02 +0800 Subject: [PATCH 2053/2070] drm/amdgpu: fix the idr allocation flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the IDR allocation flags by using atomic GFP flags in non‑sleepable contexts to avoid the __might_sleep() complaint. 268.290239] [drm] Initialized amdgpu 3.64.0 for 0000:03:00.0 on minor 0 [ 268.294900] BUG: sleeping function called from invalid context at ./include/linux/sched/mm.h:323 [ 268.295355] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1744, name: modprobe [ 268.295705] preempt_count: 1, expected: 0 [ 268.295886] RCU nest depth: 0, expected: 0 [ 268.296072] 2 locks held by modprobe/1744: [ 268.296077] #0: ffff8c3a44abd1b8 (&dev->mutex){....}-{4:4}, at: __driver_attach+0xe4/0x210 [ 268.296100] #1: ffffffffc1a6ea78 (amdgpu_pasid_idr_lock){+.+.}-{3:3}, at: amdgpu_pasid_alloc+0x26/0xe0 [amdgpu] [ 268.296494] CPU: 12 UID: 0 PID: 1744 Comm: modprobe Tainted: G U OE 6.19.0-custom #16 PREEMPT(voluntary) [ 268.296498] Tainted: [U]=USER, [O]=OOT_MODULE, [E]=UNSIGNED_MODULE [ 268.296499] Hardware name: AMD Majolica-RN/Majolica-RN, BIOS RMJ1009A 06/13/2021 [ 268.296501] Call Trace: Fixes: e6d765de3d6b ("drm/amdgpu: prevent immediate PASID reuse case") Signed-off-by: Prike Liang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 644e413a4e692..e495a8fa13fdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -68,8 +68,11 @@ int amdgpu_pasid_alloc(unsigned int bits) return -EINVAL; spin_lock(&amdgpu_pasid_idr_lock); + /* TODO: Need to replace the idr with an xarry, and then + * handle the internal locking with ATOMIC safe paths. + */ pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1, - 1U << bits, GFP_KERNEL); + 1U << bits, GFP_ATOMIC); spin_unlock(&amdgpu_pasid_idr_lock); if (pasid >= 0) From fa4c14176f974bc94b2306f9c92416f5e1e95ac2 Mon Sep 17 00:00:00 2001 From: Donet Tom Date: Mon, 23 Mar 2026 09:58:35 +0530 Subject: [PATCH 2054/2070] drm/amdkfd: Align expected_queue_size to PAGE_SIZE The AQL queue size can be 4K, but the minimum buffer object (BO) allocation size is PAGE_SIZE. On systems with a page size larger than 4K, the expected queue size does not match the allocated BO size, causing queue creation to fail. Align the expected queue size to PAGE_SIZE so that it matches the allocated BO size and allows queue creation to succeed. Reviewed-by: Felix Kuehling Signed-off-by: Donet Tom Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_queue.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c index d1978e3f68bee..572b21e39e83c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c @@ -249,10 +249,10 @@ int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_prope topo_dev->node_props.gfx_target_version < 90000) /* metadata_queue_size not supported on GFX7/GFX8 */ expected_queue_size = - properties->queue_size / 2; + PAGE_ALIGN(properties->queue_size / 2); else expected_queue_size = - properties->queue_size + properties->metadata_queue_size; + PAGE_ALIGN(properties->queue_size + properties->metadata_queue_size); vm = drm_priv_to_vm(pdd->drm_priv); err = amdgpu_bo_reserve(vm->root.bo, false); From d179da1ad574cbe07cdeb51aadeb5729c1fd03bd Mon Sep 17 00:00:00 2001 From: Donet Tom Date: Mon, 23 Mar 2026 09:58:38 +0530 Subject: [PATCH 2055/2070] drm/amd: Fix MQD and control stack alignment for non-4K MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For gfxV9, due to a hardware bug ("based on the comments in the code here [1]"), the control stack of a user-mode compute queue must be allocated immediately after the page boundary of its regular MQD buffer. To handle this, we allocate an enlarged MQD buffer where the first page is used as the MQD and the remaining pages store the control stack. Although these regions share the same BO, they require different memory types: the MQD must be UC (uncached), while the control stack must be NC (non-coherent), matching the behavior when the control stack is allocated in user space. This logic works correctly on systems where the CPU page size matches the GPU page size (4K). However, the current implementation aligns both the MQD and the control stack to the CPU PAGE_SIZE. On systems with a larger CPU page size, the entire first CPU page is marked UC—even though that page may contain multiple GPU pages. The GPU treats the second 4K GPU page inside that CPU page as part of the control stack, but it is incorrectly mapped as UC. This patch fixes the issue by aligning both the MQD and control stack sizes to the GPU page size (4K). The first 4K page is correctly marked as UC for the MQD, and the remaining GPU pages are marked NC for the control stack. This ensures proper memory type assignment on systems with larger CPU page sizes. [1]: https://elixir.bootlin.com/linux/v6.18/source/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c#L118 Acked-by: Felix Kuehling Signed-off-by: Donet Tom Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 ++----- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 23 ++++++---- 4 files changed, 64 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index ec911dce345ff..4d884180cf61c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -403,6 +403,50 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, drm_dev_exit(idx); } +/** + * amdgpu_gart_map_gfx9_mqd - map mqd and ctrl_stack dma_addresses into GART entries + * + * @adev: amdgpu_device pointer + * @offset: offset into the GPU's gart aperture + * @pages: number of pages to bind + * @dma_addr: DMA addresses of pages + * @flags: page table entry flags + * + * Map the MQD and control stack addresses into GART entries with the correct + * memory types on gfxv9. The MQD occupies the first 4KB and is followed by + * the control stack. The MQD uses UC (uncached) memory, while the control stack + * uses NC (non-coherent) memory. + */ +void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset, + int pages, dma_addr_t *dma_addr, uint64_t flags) +{ + uint64_t page_base; + unsigned int i, j, t; + int idx; + uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); + void *dst; + + if (!adev->gart.ptr) + return; + + if (!drm_dev_enter(adev_to_drm(adev), &idx)) + return; + + t = offset / AMDGPU_GPU_PAGE_SIZE; + dst = adev->gart.ptr; + for (i = 0; i < pages; i++) { + page_base = dma_addr[i]; + for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { + if ((i == 0) && (j == 0)) + amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); + else + amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, ctrl_flags); + page_base += AMDGPU_GPU_PAGE_SIZE; + } + } + drm_dev_exit(idx); +} + /** * amdgpu_gart_bind - bind pages into the gart page table * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index d3118275ddae8..6ebd2da32ea60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -62,6 +62,8 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, int pages, dma_addr_t *dma_addr, uint64_t flags, void *dst); +void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset, + int pages, dma_addr_t *dma_addr, uint64_t flags); void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, dma_addr_t *dma_addr, uint64_t flags); void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 6cac635535cff..b07d091379e7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1061,25 +1061,15 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); uint64_t page_idx, pages_per_xcc; int i; - uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); pages_per_xcc = total_pages; do_div(pages_per_xcc, num_xcc); for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { - /* MQD page: use default flags */ - amdgpu_gart_bind(adev, + amdgpu_gart_map_gfx9_mqd(adev, gtt->offset + (page_idx << PAGE_SHIFT), - 1, >t->ttm.dma_address[page_idx], flags); - /* - * Ctrl pages - modify the memory type to NC (ctrl_flags) from - * the second page of the BO onward. - */ - amdgpu_gart_bind(adev, - gtt->offset + ((page_idx + 1) << PAGE_SHIFT), - pages_per_xcc - 1, - >t->ttm.dma_address[page_idx + 1], - ctrl_flags); + pages_per_xcc, >t->ttm.dma_address[page_idx], + flags); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 77662ce7d8aae..974688f3f86f6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -42,9 +42,16 @@ static uint64_t mqd_stride_v9(struct mqd_manager *mm, struct queue_properties *q) { if (mm->dev->kfd->cwsr_enabled && - q->type == KFD_QUEUE_TYPE_COMPUTE) - return ALIGN(q->ctl_stack_size, PAGE_SIZE) + - ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); + q->type == KFD_QUEUE_TYPE_COMPUTE) { + + /* On gfxv9, the MQD resides in the first 4K page, + * followed by the control stack. Align both to + * AMDGPU_GPU_PAGE_SIZE to maintain the required 4K boundary. + */ + + return ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + + ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE); + } return mm->mqd_size; } @@ -193,8 +200,8 @@ static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, if (!mqd_mem_obj) return NULL; retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev, - (ALIGN(q->ctl_stack_size, PAGE_SIZE) + - ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * + (ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + + ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE)) * NUM_XCC(node->xcc_mask), mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, @@ -416,7 +423,7 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, struct kfd_context_save_area_header header; /* Control stack is located one page after MQD. */ - void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); + void *mqd_ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); m = get_mqd(mqd); @@ -456,7 +463,7 @@ static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, voi { struct v9_mqd *m; /* Control stack is located one page after MQD. */ - void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); + void *ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); m = get_mqd(mqd); @@ -502,7 +509,7 @@ static void restore_mqd(struct mqd_manager *mm, void **mqd, *gart_addr = addr; /* Control stack is located one page after MQD. */ - ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); + ctl_stack = (void *)((uintptr_t)*mqd + AMDGPU_GPU_PAGE_SIZE); memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); m->cp_hqd_pq_doorbell_control = From 8efdfa94dd9364ab99fcdb703e759b05f4a35082 Mon Sep 17 00:00:00 2001 From: Junrui Luo Date: Sat, 14 Mar 2026 23:33:53 +0800 Subject: [PATCH 2056/2070] drm/amdgpu/userq: fix memory leak in MQD creation error paths In mes_userq_mqd_create(), the memdup_user() allocations for IP-specific MQD structs are not freed when subsequent VA validation fails. The goto free_mqd label only cleans up the MQD BO object and userq_props. Fix by adding kfree() before each goto free_mqd on VA validation failure in the COMPUTE, GFX, and SDMA branches. Fixes: 9e46b8bb0539 ("drm/amdgpu: validate userq buffer virtual address and size") Reported-by: Yuhao Jiang Cc: stable@vger.kernel.org Signed-off-by: Junrui Luo Reviewed-by: Prike Liang --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 9508709abd49a..527cf2f14691d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -324,8 +324,10 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va, 2048); - if (r) + if (r) { + kfree(compute_mqd); goto free_mqd; + } userq_props->eop_gpu_addr = compute_mqd->eop_va; userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; @@ -365,12 +367,16 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, shadow_info.shadow_size); - if (r) + if (r) { + kfree(mqd_gfx_v11); goto free_mqd; + } r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, shadow_info.csa_size); - if (r) + if (r) { + kfree(mqd_gfx_v11); goto free_mqd; + } kfree(mqd_gfx_v11); } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { @@ -390,8 +396,10 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, } r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 32); - if (r) + if (r) { + kfree(mqd_sdma_v11); goto free_mqd; + } userq_props->csa_addr = mqd_sdma_v11->csa_va; kfree(mqd_sdma_v11); From 7d1ab59961314215449f90c4b0bc8d74a9ec2b6f Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Sun, 1 Mar 2026 15:19:13 +0000 Subject: [PATCH 2057/2070] drm/amdgpu : Update psp 13_0_15 ip block support Included psp_13_0_15 ip block for RAS Signed-off-by: Mangesh Gadre Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index bbed569f1807b..da221b5414440 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2254,6 +2254,7 @@ static bool amdgpu_ras_aca_is_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): ret = true; break; default: @@ -4012,6 +4013,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): return true; default: return false; @@ -4025,6 +4027,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): case IP_VERSION(14, 0, 3): return true; default: @@ -4194,7 +4197,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) adev->aca.is_enabled = (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)); + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)); } /* bad page feature is not applicable to specific app platform */ @@ -4282,6 +4286,7 @@ static void amdgpu_ras_init_reserved_vram_size(struct amdgpu_device *adev) case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): + case IP_VERSION(13, 0, 15): con->reserved_pages_in_bytes = AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT; break; case IP_VERSION(13, 0, 14): From 75cc91a39498d7283050aeb8966ba4601c56aaf8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Mar 2026 16:13:54 +0800 Subject: [PATCH 2058/2070] drm/amdkcl: limit cmd_mod_fix.mk under kernel 6.0 It's caused by c6031b1dbbbfec03891bf1baefa2e0803d705601 "kbuild: make *.mod rule robust against too long argument error" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index f1b345835ed37..3c70636d6d0eb 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -89,11 +89,15 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild done +# The upstream fix is commit c6031b1dbbbf ("kbuild: make *.mod rule robust against +# too long argument error"), merged in v5.19. Kernels < 6.0 may still lack this fix. # Fix "Argument list too long" in recursive make for large modules (700+ .o files). # Makefile.build recurses into subdirectories via sub-makes that don't inherit # overrides. Inject the include into amd/amdgpu/Makefile; cmd_mod_fix.mk itself # checks whether the fix is needed and is a no-op on newer kernels. -sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile +if version_lt 6.0; then + sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile +fi export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR From 97d9fd4be540574598490e18ae37ee2a0574fd32 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 23 Mar 2026 13:17:58 +0800 Subject: [PATCH 2059/2070] drm/amdkcl: fix "Argument list too long" for large modules in DKMS build amdgpu has 700+ .o files, causing two build failures on older kernels (< 5.19) where Kbuild's cmd_mod uses shell echo: 1. E2BIG: shell echo in cmd_mod and cmd_link_multi-m exceeds ARG_MAX. 2. ENAMETOOLONG: RHEL modpost reads .mod as single-line path, exceeding PATH_MAX (4096) when the concatenated .o list reaches ~65KB. The upstream fix is commit c6031b1dbbbf ("kbuild: make *.mod rule robust against too long argument error"), merged in v5.19, which replaced cmd_mod with printf piped through awk. Kernels before v5.19 still use echo with all .o paths expanded inline as shell arguments. Add cmd_mod_fix.mk which overrides cmd_mod and cmd_link_multi-m using GNU Make's $(file) builtin (bypasses shell entirely) and writes one .o per line in .mod files (avoids RHEL modpost PATH_MAX issue). pre-build.sh unconditionally injects the include into amd/amdgpu/Makefile to cover the recursive make context where the large module is linked; cmd_mod_fix.mk itself detects whether the fix is needed and is a no-op on newer kernels. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk | 27 +++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 6 ++++++ 2 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk diff --git a/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk b/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk new file mode 100644 index 0000000000000..9968b0a30aa2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk @@ -0,0 +1,27 @@ +# Fix E2BIG/ENAMETOOLONG for amdgpu on kernels < 5.19: use $(file) instead +# of shell echo in cmd_mod, and write one .o per line in .mod files. +# +# $(subst $(space),$(newline),...) inside $(file) silently drops newlines, +# so we use $(file >) for the first entry and $(file >>) for the rest. + +ifndef _amdgpu_cmd_mod_fix_included +_amdgpu_cmd_mod_fix_included := 1 + +_kbuild_makefile_build := $(srctree)/scripts/Makefile.build +_cmd_mod_needs_fix := $(shell grep -q 'cmd_mod = printf' $(_kbuild_makefile_build) 2>/dev/null || echo 1) + +ifeq ($(_cmd_mod_needs_fix),1) + +_amdgpu_mod_objs = $(sort $(strip $(if $($*-objs)$($*-y)$($*-m),$(addprefix $(obj)/,$($*-objs) $($*-y) $($*-m)),$(@:.mod=.o)))) + +override quiet_cmd_mod = MOD $@ +override cmd_mod = $(file >$@,$(firstword $(_amdgpu_mod_objs))) \ + $(foreach o,$(wordlist 2,$(words $(_amdgpu_mod_objs)),$(_amdgpu_mod_objs)),$(file >>$@,$(o))) \ + true $(if $(cmd_undef_syms),; $(cmd_undef_syms)) + +override quiet_cmd_link_multi-m = LD [M] $@ +override cmd_link_multi-m = $(file >$@.args, $(filter %.o,$^)) \ + $(LD) $(ld_flags) -r -o $@ @$@.args + +endif +endif diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index f69be8865e1b8..f1b345835ed37 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -89,6 +89,12 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild done +# Fix "Argument list too long" in recursive make for large modules (700+ .o files). +# Makefile.build recurses into subdirectories via sub-makes that don't inherit +# overrides. Inject the include into amd/amdgpu/Makefile; cmd_mod_fix.mk itself +# checks whether the fix is needed and is a no-op on newer kernels. +sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile + export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env From 0131e172bf54f62afc550ea67745e15e25f0e0f0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Mar 2026 16:13:54 +0800 Subject: [PATCH 2060/2070] drm/amdkcl: limit cmd_mod_fix.mk under kernel 6.0 It's caused by c6031b1dbbbfec03891bf1baefa2e0803d705601 "kbuild: make *.mod rule robust against too long argument error" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index f1b345835ed37..3c70636d6d0eb 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -89,11 +89,15 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild done +# The upstream fix is commit c6031b1dbbbf ("kbuild: make *.mod rule robust against +# too long argument error"), merged in v5.19. Kernels < 6.0 may still lack this fix. # Fix "Argument list too long" in recursive make for large modules (700+ .o files). # Makefile.build recurses into subdirectories via sub-makes that don't inherit # overrides. Inject the include into amd/amdgpu/Makefile; cmd_mod_fix.mk itself # checks whether the fix is needed and is a no-op on newer kernels. -sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile +if version_lt 6.0; then + sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile +fi export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR From 527831c232cf3bddca9f5148d1862bf97109b7c8 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Tue, 17 Mar 2026 15:31:48 +0800 Subject: [PATCH 2061/2070] drm/amdgpu: reset ras eeprom table when it is invalid reset ras eeprom table when it is invalid Signed-off-by: Gangliang Xie Reviewed-by: Hawking Zhang (cherry picked from commit fefb0695f6191abb6b0bf3e4e492b844b330c1b8) Change-Id: I174506f6929801937150efe6d2e60b09f895edfa --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 44fba4b6aa92a..cdf4909592d22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1558,6 +1558,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + int dev_var = adev->pdev->device & 0xF; + uint32_t vram_type = adev->gmc.vram_type; int res; if (amdgpu_ras_smu_eeprom_supported(adev)) @@ -1597,6 +1599,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) return amdgpu_ras_eeprom_reset_table(control); } + if (!(adev->flags & AMD_IS_APU) && (dev_var == 0x5) && + (vram_type == AMDGPU_VRAM_TYPE_HBM3E) && + (hdr->version < RAS_TABLE_VER_V3)) { + return amdgpu_ras_eeprom_reset_table(control); + } + switch (hdr->version) { case RAS_TABLE_VER_V2_1: case RAS_TABLE_VER_V3: From 4ad8ebaedfc2a4dfc9f2f78eefe9705304784f59 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Wed, 18 Mar 2026 16:09:39 +0800 Subject: [PATCH 2062/2070] drm/amdgpu: add support to query vram info from firmware add support to query vram info from firmware v2: change APU vram type, add multi-aid check v3: seperate vram info query function into 3 parts and call them in a helper func when requirements are met. v4: calculate vram_width for v9.x Signed-off-by: Gangliang Xie Reviewed-by: Lijo Lazar (cherry picked from commit 821a5c753d6a476808fccc866bea369015860725) Change-Id: I7020a7b263b6f63f5f297bfad3087a941ddcf03c --- .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 459 ++++++++++-------- .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 29 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 58 ++- 8 files changed, 315 insertions(+), 243 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index 7f4751e5caaf1..cd9aa5b45e943 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -373,249 +373,280 @@ int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, return -ENODEV; } -int -amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, +int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor) { struct amdgpu_mode_info *mode_info = &adev->mode_info; - int index, i = 0; + int index; u16 data_offset, size; union igp_info *igp_info; - union vram_info *vram_info; - union umc_info *umc_info; - union vram_module *vram_module; u8 frev, crev; u8 mem_type; - u8 mem_vendor; u32 mem_channel_number; u32 mem_channel_width; - u32 module_id; - if (adev->flags & AMD_IS_APU) - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, integratedsysteminfo); - else { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - case IP_VERSION(12, 0, 0): - case IP_VERSION(12, 0, 1): - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); + if (amdgpu_atom_parse_data_header(mode_info->atom_context, + index, &size, + &frev, &crev, &data_offset)) { + igp_info = (union igp_info *) + (mode_info->atom_context->bios + data_offset); + switch (frev) { + case 1: + switch (crev) { + case 11: + case 12: + mem_channel_number = igp_info->v11.umachannelnumber; + if (!mem_channel_number) + mem_channel_number = 1; + mem_type = igp_info->v11.memorytype; + if (mem_type == LpDdr5MemType) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + break; + default: + return -EINVAL; + } + break; + case 2: + switch (crev) { + case 1: + case 2: + mem_channel_number = igp_info->v21.umachannelnumber; + if (!mem_channel_number) + mem_channel_number = 1; + mem_type = igp_info->v21.memorytype; + if (mem_type == LpDdr5MemType) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + break; + case 3: + mem_channel_number = igp_info->v23.umachannelnumber; + if (!mem_channel_number) + mem_channel_number = 1; + mem_type = igp_info->v23.memorytype; + if (mem_type == LpDdr5MemType) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + break; + default: + return -EINVAL; + } break; default: - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info); + return -EINVAL; } + } else { + return -EINVAL; } + return 0; +} + +int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, + int *vram_vendor) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index; + u16 data_offset, size; + union umc_info *umc_info; + u8 frev, crev; + u8 mem_type; + u8 mem_vendor; + u32 mem_channel_number; + u32 mem_channel_width; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { - if (adev->flags & AMD_IS_APU) { - igp_info = (union igp_info *) - (mode_info->atom_context->bios + data_offset); - switch (frev) { - case 1: - switch (crev) { - case 11: - case 12: - mem_channel_number = igp_info->v11.umachannelnumber; - if (!mem_channel_number) - mem_channel_number = 1; - mem_type = igp_info->v11.memorytype; - if (mem_type == LpDdr5MemType) - mem_channel_width = 32; - else - mem_channel_width = 64; - if (vram_width) - *vram_width = mem_channel_number * mem_channel_width; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - break; - default: - return -EINVAL; - } - break; - case 2: - switch (crev) { - case 1: - case 2: - mem_channel_number = igp_info->v21.umachannelnumber; - if (!mem_channel_number) - mem_channel_number = 1; - mem_type = igp_info->v21.memorytype; - if (mem_type == LpDdr5MemType) - mem_channel_width = 32; - else - mem_channel_width = 64; - if (vram_width) - *vram_width = mem_channel_number * mem_channel_width; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - break; - case 3: - mem_channel_number = igp_info->v23.umachannelnumber; - if (!mem_channel_number) - mem_channel_number = 1; - mem_type = igp_info->v23.memorytype; - if (mem_type == LpDdr5MemType) - mem_channel_width = 32; - else - mem_channel_width = 64; - if (vram_width) - *vram_width = mem_channel_number * mem_channel_width; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - break; - default: - return -EINVAL; - } + umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); + + if (frev == 4) { + switch (crev) { + case 0: + mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); + mem_type = le32_to_cpu(umc_info->v40.vram_type); + mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); + mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); break; default: return -EINVAL; } } else { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - case IP_VERSION(12, 0, 0): - case IP_VERSION(12, 0, 1): - umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); - - if (frev == 4) { - switch (crev) { - case 0: - mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); - mem_type = le32_to_cpu(umc_info->v40.vram_type); - mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); - mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - break; - default: - return -EINVAL; - } - } else - return -EINVAL; + return -EINVAL; + } + } else { + return -EINVAL; + } + + return 0; +} + +int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, + int *vram_vendor) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index, i = 0; + u16 data_offset, size; + union vram_info *vram_info; + union vram_module *vram_module; + u8 frev, crev; + u8 mem_type; + u8 mem_vendor; + u32 mem_channel_number; + u32 mem_channel_width; + u32 module_id; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info); + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, + index, &size, + &frev, &crev, &data_offset)) { + vram_info = (union vram_info *) + (mode_info->atom_context->bios + data_offset); + + module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; + if (frev == 3) { + switch (crev) { + /* v30 */ + case 0: + vram_module = (union vram_module *)vram_info->v30.vram_module; + mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + mem_type = vram_info->v30.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_info->v30.channel_num; + mem_channel_width = vram_info->v30.channel_width; + if (vram_width) + *vram_width = mem_channel_number * 16; break; default: - vram_info = (union vram_info *) - (mode_info->atom_context->bios + data_offset); - - module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; - if (frev == 3) { - switch (crev) { - /* v30 */ - case 0: - vram_module = (union vram_module *)vram_info->v30.vram_module; - mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - mem_type = vram_info->v30.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_info->v30.channel_num; - mem_channel_width = vram_info->v30.channel_width; - if (vram_width) - *vram_width = mem_channel_number * 16; - break; - default: - return -EINVAL; - } - } else if (frev == 2) { - switch (crev) { - /* v23 */ - case 3: - if (module_id > vram_info->v23.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v23.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v9.vram_module_size); - i++; - } - mem_type = vram_module->v9.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v9.channel_num; - mem_channel_width = vram_module->v9.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - /* v24 */ - case 4: - if (module_id > vram_info->v24.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v24.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v10.vram_module_size); - i++; - } - mem_type = vram_module->v10.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v10.channel_num; - mem_channel_width = vram_module->v10.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - /* v25 */ - case 5: - if (module_id > vram_info->v25.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v25.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v11.vram_module_size); - i++; - } - mem_type = vram_module->v11.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v11.channel_num; - mem_channel_width = vram_module->v11.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - /* v26 */ - case 6: - if (module_id > vram_info->v26.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v26.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v9.vram_module_size); - i++; - } - mem_type = vram_module->v9.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v9.channel_num; - mem_channel_width = vram_module->v9.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - default: - return -EINVAL; - } - } else { - /* invalid frev */ - return -EINVAL; + return -EINVAL; + } + } else if (frev == 2) { + switch (crev) { + /* v23 */ + case 3: + if (module_id > vram_info->v23.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v23.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v9.vram_module_size); + i++; } + mem_type = vram_module->v9.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v9.channel_num; + mem_channel_width = vram_module->v9.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + /* v24 */ + case 4: + if (module_id > vram_info->v24.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v24.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v10.vram_module_size); + i++; + } + mem_type = vram_module->v10.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v10.channel_num; + mem_channel_width = vram_module->v10.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + /* v25 */ + case 5: + if (module_id > vram_info->v25.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v25.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v11.vram_module_size); + i++; + } + mem_type = vram_module->v11.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v11.channel_num; + mem_channel_width = vram_module->v11.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + /* v26 */ + case 6: + if (module_id > vram_info->v26.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v26.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v9.vram_module_size); + i++; + } + mem_type = vram_module->v9.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v9.channel_num; + mem_channel_width = vram_module->v9.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + default: + return -EINVAL; } + } else { + /* invalid frev */ + return -EINVAL; } + + } else { + return -EINVAL; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h index 67c8d105729b2..0760e45105133 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h @@ -30,6 +30,10 @@ uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *ade bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev); void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev); int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev); +int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor); +int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor); int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor); int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 685139592e262..24dca148b9f92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -34,6 +34,7 @@ #include "amdgpu_ras.h" #include "amdgpu_reset.h" #include "amdgpu_xgmi.h" +#include "amdgpu_atomfirmware.h" #include #include @@ -1763,3 +1764,31 @@ int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev) return 0; } + +int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor) +{ + int ret = 0; + + if (adev->flags & AMD_IS_APU) + return amdgpu_atomfirmware_get_integrated_system_info(adev, + vram_width, vram_type, vram_vendor); + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 0, 0): + case IP_VERSION(12, 0, 1): + return amdgpu_atomfirmware_get_umc_info(adev, + vram_width, vram_type, vram_vendor); + case IP_VERSION(9, 5, 0): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 4, 3): + ret = amdgpu_atomfirmware_get_umc_info(adev, + vram_width, vram_type, vram_vendor); + if (vram_width && !ret) + *vram_width *= hweight32(adev->aid_mask); + return ret; + default: + return amdgpu_atomfirmware_get_vram_info(adev, + vram_width, vram_type, vram_vendor); + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index b9fdc3276e816..32e73e8ba778c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -482,4 +482,6 @@ amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges); +int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 12d2f181b5344..feda8209f1fc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -765,7 +765,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ } else { - r = amdgpu_atomfirmware_get_vram_info(adev, + r = amdgpu_gmc_get_vram_info(adev, &vram_width, &vram_type, &vram_vendor); adev->gmc.vram_width = vram_width; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 9a2a15692c5e2..0f6e2b00c5735 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -749,7 +749,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) spin_lock_init(&adev->gmc.invalidate_lock); - r = amdgpu_atomfirmware_get_vram_info(adev, + r = amdgpu_gmc_get_vram_info(adev, &vram_width, &vram_type, &vram_vendor); adev->gmc.vram_width = vram_width; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index f1079bd8cf001..6e184ea069ef2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -825,7 +825,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { gmc_v12_1_init_vram_info(adev); } else { - r = amdgpu_atomfirmware_get_vram_info(adev, + r = amdgpu_gmc_get_vram_info(adev, &vram_width, &vram_type, &vram_vendor); adev->gmc.vram_width = vram_width; adev->gmc.vram_type = vram_type; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index aa95cb4818ee1..fabb09425d98e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1801,24 +1801,37 @@ static void gmc_v9_0_save_registers(struct amdgpu_device *adev) adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); } -static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) +static void gmc_v9_0_init_vram_info(struct amdgpu_device *adev) { static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; + int dev_var = adev->pdev->device & 0xF; u32 vram_info; - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; - adev->gmc.vram_width = 128 * 64; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && - adev->rev_id == 0x3) - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; - - if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { - vram_info = RREG32(regBIF_BIOS_SCRATCH_4); - adev->gmc.vram_vendor = vram_info & 0xF; + if (adev->gmc.is_app_apu) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; + adev->gmc.vram_width = 128 * 64; + } else if (adev->flags & AMD_IS_APU) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; + adev->gmc.vram_width = 64 * 64; + } else if (amdgpu_is_multi_aid(adev)) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; + adev->gmc.vram_width = 128 * 64; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && + adev->rev_id == 0x3) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && + (dev_var == 0x5)) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { + vram_info = RREG32(regBIF_BIOS_SCRATCH_4); + adev->gmc.vram_vendor = vram_info & 0xF; + } } } @@ -1834,19 +1847,11 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) spin_lock_init(&adev->gmc.invalidate_lock); - if (amdgpu_is_multi_aid(adev)) { - gmc_v9_4_3_init_vram_info(adev); - } else if (!adev->bios) { - if (adev->flags & AMD_IS_APU) { - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; - adev->gmc.vram_width = 64 * 64; - } else { - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; - adev->gmc.vram_width = 128 * 64; - } + if (!adev->bios) { + gmc_v9_0_init_vram_info(adev); } else { - r = amdgpu_atomfirmware_get_vram_info(adev, - &vram_width, &vram_type, &vram_vendor); + r = amdgpu_gmc_get_vram_info(adev, + &vram_width, &vram_type, &vram_vendor); if (amdgpu_sriov_vf(adev)) /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, * and DF related registers is not readable, seems hardcord is the @@ -1874,6 +1879,7 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gmc.vram_type = vram_type; adev->gmc.vram_vendor = vram_vendor; } + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 1, 0): case IP_VERSION(9, 2, 2): From 1aa81542640405610be405205771b909e007a190 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 3 Apr 2026 16:09:08 +0800 Subject: [PATCH 2063/2070] Bump AMDGPU version to 6.19.4 Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 8d5060ae5ce8a..42476e23441ea 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.19.3) +AC_INIT(amdgpu-dkms, 6.19.4) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 90c51b2574a9aac2b4fec0d731b2b19c8e5cb1b7 Mon Sep 17 00:00:00 2001 From: Mikhail Gavrilov Date: Tue, 31 Mar 2026 19:21:26 +0500 Subject: [PATCH 2064/2070] drm/amdgpu: replace PASID IDR with XArray MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the PASID IDR + spinlock with XArray as noted in the TODO left by commit ea56aa262570 ("drm/amdgpu: fix the idr allocation flags"). The IDR conversion still has an IRQ safety issue: amdgpu_pasid_free() can be called from hardirq context via the fence signal path, but amdgpu_pasid_idr_lock is taken with plain spin_lock() in process context, creating a potential deadlock: CPU0 ---- spin_lock(&amdgpu_pasid_idr_lock) // process context, IRQs on spin_lock(&amdgpu_pasid_idr_lock) // deadlock The hardirq call chain is: sdma_v6_0_process_trap_irq -> amdgpu_fence_process -> dma_fence_signal -> drm_sched_job_done -> dma_fence_signal -> amdgpu_pasid_free_cb -> amdgpu_pasid_free Use XArray with XA_FLAGS_LOCK_IRQ (all xa operations use IRQ-safe locking internally) and XA_FLAGS_ALLOC1 (zero is not a valid PASID). Both xa_alloc_cyclic() and xa_erase() then handle locking consistently, fixing the IRQ safety issue and removing the need for an explicit spinlock. v8: squash in irq safe fix Reviewed-by: Christian König Suggested-by: Lijo Lazar Fixes: ea56aa262570 ("drm/amdgpu: fix the idr allocation flags") Fixes: 8f1de51f49be ("drm/amdgpu: prevent immediate PASID reuse case") Signed-off-by: Mikhail Gavrilov Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 39 ++++++++++++------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index e495a8fa13fdb..684f40fce73ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -22,7 +22,7 @@ */ #include "amdgpu_ids.h" -#include +#include #include @@ -40,8 +40,8 @@ * VMs are looked up from the PASID per amdgpu_device. */ -static DEFINE_IDR(amdgpu_pasid_idr); -static DEFINE_SPINLOCK(amdgpu_pasid_idr_lock); +static DEFINE_XARRAY_FLAGS(amdgpu_pasid_xa, XA_FLAGS_LOCK_IRQ | XA_FLAGS_ALLOC1); +static u32 amdgpu_pasid_xa_next; /* Helper to free pasid from a fence callback */ struct amdgpu_pasid_cb { @@ -62,36 +62,37 @@ struct amdgpu_pasid_cb { */ int amdgpu_pasid_alloc(unsigned int bits) { - int pasid; + u32 pasid; + int r; if (bits == 0) return -EINVAL; - spin_lock(&amdgpu_pasid_idr_lock); - /* TODO: Need to replace the idr with an xarry, and then - * handle the internal locking with ATOMIC safe paths. - */ - pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1, - 1U << bits, GFP_ATOMIC); - spin_unlock(&amdgpu_pasid_idr_lock); - - if (pasid >= 0) - trace_amdgpu_pasid_allocated(pasid); + r = xa_alloc_cyclic_irq(&amdgpu_pasid_xa, &pasid, xa_mk_value(0), + XA_LIMIT(1, (1U << bits) - 1), + &amdgpu_pasid_xa_next, GFP_KERNEL); + if (r < 0) + return r; + trace_amdgpu_pasid_allocated(pasid); return pasid; } /** * amdgpu_pasid_free - Free a PASID * @pasid: PASID to free + * + * Called in IRQ context. */ void amdgpu_pasid_free(u32 pasid) { + unsigned long flags; + trace_amdgpu_pasid_freed(pasid); - spin_lock(&amdgpu_pasid_idr_lock); - idr_remove(&amdgpu_pasid_idr, pasid); - spin_unlock(&amdgpu_pasid_idr_lock); + xa_lock_irqsave(&amdgpu_pasid_xa, flags); + __xa_erase(&amdgpu_pasid_xa, pasid); + xa_unlock_irqrestore(&amdgpu_pasid_xa, flags); } static void amdgpu_pasid_free_cb(struct dma_fence *fence, @@ -634,7 +635,5 @@ void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev) */ void amdgpu_pasid_mgr_cleanup(void) { - spin_lock(&amdgpu_pasid_idr_lock); - idr_destroy(&amdgpu_pasid_idr); - spin_unlock(&amdgpu_pasid_idr_lock); + xa_destroy(&amdgpu_pasid_xa); } From a2a21fe7c155dcc39b6f84dd96030e7f4ce4700e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Sat, 18 Apr 2026 06:21:17 +0530 Subject: [PATCH 2065/2070] drm/amd/pm: Check SMUv13.0.6/12 metrics integrity Check if data fetch is proper by matching the first few bytes against 0xFFs. If 0xFFs, that means data couldn't be read properly. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 8c4d81595c745..1938d7c8de2e1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -929,6 +929,10 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, amdgpu_hdp_invalidate(smu->adev, NULL); memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + if (!memchr_inv(smu_table->metrics_table, 0xff, + min(16, table_size))) + return -EHWPOISON; + smu_table->metrics_time = jiffies; } From 5929fde8e6009f49aecee15ea16d6c795e6a6050 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 27 Apr 2026 17:17:41 +0530 Subject: [PATCH 2066/2070] drm/amd/pm: Update emit clock logic If only one level is enabled in clock table, there is no need to follow the fine grained clock logic which expects a minimum of two levels (min/max). Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 8e44260f933e0..59e746e571ff1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1349,7 +1349,7 @@ int smu_cmn_print_dpm_clk_levels(struct smu_context *smu, level_index = 1; } - if (!is_fine_grained) { + if (!is_fine_grained || count == 1) { for (i = 0; i < count; i++) { freq_match = !is_deep_sleep && smu_cmn_freqs_match( From be96c1c95eb46b9fda47ed98a621c88be802173c Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 27 Apr 2026 12:53:30 +0530 Subject: [PATCH 2067/2070] drm/amd/pm: Add fine grained flag to SMU v13.0.6 Gfx clock is fine grained on SMU v13.0.6/12 SOCs. Add the flag to report clock frequencies correctly. Fixes: 7380228401c4 ("drm/amd/pm: Use generic dpm table for SMUv13 SOCs") Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 1938d7c8de2e1..367a0b7dc4c08 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1288,6 +1288,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; dpm_table->clk_type = SMU_GFXCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { /* In the case of gfxclk, only fine-grained dpm is honored. * Get min/max values from FW. From bf899db40472f5b924ae4f3ede16ae302c1556e1 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 27 Apr 2026 12:53:30 +0530 Subject: [PATCH 2068/2070] drm/amd/pm: Add fine grained flag to SMU v13.0.6 Gfx clock is fine grained on SMU v13.0.6/12 SOCs. Add the flag to report clock frequencies correctly. Fixes: 7380228401c4 ("drm/amd/pm: Use generic dpm table for SMUv13 SOCs") Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal From 8fa1981194836936acd57c4cf4b3fd694af47cc3 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Thu, 7 May 2026 20:56:15 +0800 Subject: [PATCH 2069/2070] drm/amd/ras: Fix CPER ring debugfs read overflow The legacy CPER debugfs reader can reach the payload path without a valid pointer snapshot. The remaining user byte count is also treated as the ring occupancy in dwords, so reads past the header can copy more than requested. Take the CPER lock before sampling pointers. Resample rptr/wptr for payload reads, bound the payload copy by available dwords and the remaining user size, and advance the file position for each dword copied. Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 29 +++++++++++++++++------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 5de786551aaac..e47a155f4bb1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -552,8 +552,9 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { struct amdgpu_ring *ring = file_inode(f)->i_private; - uint32_t value, result, early[3]; + u32 value, result, early[3] = { 0 }; uint64_t p; + u32 avail_dw, start_dw, read_dw; loff_t i; int r; @@ -565,10 +566,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, result = 0; - if (*pos < 12) { - if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) - mutex_lock(&ring->adev->cper.ring_lock); + if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) + mutex_lock(&ring->adev->cper.ring_lock); + if (*pos < 12) { early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; early[2] = ring->wptr & ring->buf_mask; @@ -600,13 +601,24 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, *pos += 4; } } else { + early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; + early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; + p = early[0]; if (early[0] <= early[1]) - size = (early[1] - early[0]); + avail_dw = early[1] - early[0]; else - size = ring->ring_size - (early[0] - early[1]); + avail_dw = ring->buf_mask + 1 - (early[0] - early[1]); - while (size) { + start_dw = (*pos > 12) ? ((*pos - 12) >> 2) : 0; + if (start_dw >= avail_dw) + goto out; + + p = (p + start_dw) & ring->ptr_mask; + avail_dw -= start_dw; + read_dw = min_t(u32, avail_dw, size >> 2); + + while (read_dw) { if (p == early[1]) goto out; @@ -619,9 +631,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, buf += 4; result += 4; - size--; + read_dw--; p++; p &= ring->ptr_mask; + *pos += 4; } } From e27fa49b01d8e5e2103a510949a4c59916d1af71 Mon Sep 17 00:00:00 2001 From: Tom Donahue Date: Tue, 26 May 2026 22:50:05 -0500 Subject: [PATCH 2070/2070] /drm/amd/display Fix memory leak from bad dp cables If the dp cable couldn't validate the mode timing, some objects, including GTT entires, werent being cleaned up. Signed-off-by: Tom Donahue --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 53 ++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9e59ec757b118..251b9813b2a72 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10896,7 +10896,58 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, dm_enable_per_frame_crtc_master_sync(dc_state); mutex_lock(&dm->dc_lock); dc_exit_ips_for_hw_access(dm->dc); - WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); + + /* if commit_status isn't DC_OK, the cable has been pushed to its limits */ + enum dc_status commit_status = dc_commit_streams(dm->dc, ¶ms); + + if (commit_status != DC_OK) { + struct drm_plane *plane; + struct drm_plane_state *new_plane_state; + + drm_err(dev, "Display Core failed to commit streams due to link failure! Rolling back pinned framebuffers.\n"); + WARN_ON(1); + + /* release planes, unpin GTT memory */ + for_each_new_plane_in_state(state, plane, new_plane_state, i) { + const struct drm_plane_helper_funcs *funcs = plane->helper_private; + + if (funcs && funcs->cleanup_fb && new_plane_state->fb) { + drm_dbg_atomic(dev, + "Manually freeing stranded plane framebuffer allocation [ID: %d]\n", + plane->base.id); + funcs->cleanup_fb(plane, new_plane_state); + } + } + + /* release streams and vram */ + for (i = 0; i < state->num_connector; i++) { + struct drm_connector_state *new_con_state = state->connectors[i].new_state; + + if (new_con_state && new_con_state->crtc) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_con_state->crtc); + struct dm_crtc_state *dm_new_state = to_dm_crtc_state( + drm_atomic_get_new_crtc_state(state, &acrtc->base) + ); + + if (dm_new_state && dm_new_state->stream) { + dc_stream_release(dm_new_state->stream); + dm_new_state->stream = NULL; + } + } + } + + /* release dc state */ + struct dm_atomic_state *dm_state = dm_atomic_get_new_state(state); + + if (dm_state && dm_state->context) { + dc_state_release(dm_state->context); + dm_state->context = NULL; + } + + /* Release the engine lock safely and abandon the rest of the configuration */ + mutex_unlock(&dm->dc_lock); + return; + } /* Allow idle optimization when vblank count is 0 for display off */ if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev))